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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
914a3b8c | 2 | Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 5 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
6 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
7 | ||
35d965d5 RS |
8 | This file is part of GNU CC. |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 24 | |
b355a481 NC |
25 | #ifndef __ARM_H__ |
26 | #define __ARM_H__ | |
27 | ||
7a801826 RE |
28 | #define TARGET_CPU_arm2 0x0000 |
29 | #define TARGET_CPU_arm250 0x0000 | |
30 | #define TARGET_CPU_arm3 0x0000 | |
31 | #define TARGET_CPU_arm6 0x0001 | |
32 | #define TARGET_CPU_arm600 0x0001 | |
33 | #define TARGET_CPU_arm610 0x0002 | |
34 | #define TARGET_CPU_arm7 0x0001 | |
35 | #define TARGET_CPU_arm7m 0x0004 | |
36 | #define TARGET_CPU_arm7dm 0x0004 | |
37 | #define TARGET_CPU_arm7dmi 0x0004 | |
38 | #define TARGET_CPU_arm700 0x0001 | |
39 | #define TARGET_CPU_arm710 0x0002 | |
40 | #define TARGET_CPU_arm7100 0x0002 | |
41 | #define TARGET_CPU_arm7500 0x0002 | |
42 | #define TARGET_CPU_arm7500fe 0x1001 | |
43 | #define TARGET_CPU_arm7tdmi 0x0008 | |
44 | #define TARGET_CPU_arm8 0x0010 | |
45 | #define TARGET_CPU_arm810 0x0020 | |
46 | #define TARGET_CPU_strongarm 0x0040 | |
47 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 48 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
49 | #define TARGET_CPU_arm9 0x0080 |
50 | #define TARGET_CPU_arm9tdmi 0x0080 | |
82e9d970 | 51 | /* Configure didn't specify. */ |
7a801826 | 52 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 53 | |
89c7ca52 RE |
54 | enum arm_cond_code |
55 | { | |
56 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
57 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
58 | }; | |
6cfc7210 | 59 | |
89c7ca52 | 60 | extern enum arm_cond_code arm_current_cc; |
62b10bbc | 61 | extern char * arm_condition_codes[]; |
ff9940b0 | 62 | |
89c7ca52 RE |
63 | #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1)) |
64 | ||
6cfc7210 NC |
65 | extern int arm_target_label; |
66 | extern int arm_ccfsm_state; | |
67 | extern struct rtx_def * arm_target_insn; | |
68 | extern int lr_save_eliminated; | |
ff9940b0 RE |
69 | /* This is needed by the tail-calling peepholes */ |
70 | extern int frame_pointer_needed; | |
6cfc7210 NC |
71 | /* Run-time compilation parameters selecting different hardware subsets. */ |
72 | extern int target_flags; | |
73 | /* The floating point instruction architecture, can be 2 or 3 */ | |
74 | extern const char * target_fp_name; | |
ff9940b0 | 75 | |
35d965d5 | 76 | \f |
7a801826 RE |
77 | /* Just in case configure has failed to define anything. */ |
78 | #ifndef TARGET_CPU_DEFAULT | |
79 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
80 | #endif | |
81 | ||
82 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
83 | override it. If it doesn't, then default to an ARM6. */ | |
84 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic | |
85 | #undef TARGET_CPU_DEFAULT | |
86 | #ifdef SUBTARGET_CPU_DEFAULT | |
87 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
88 | #else | |
89 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
90 | #endif | |
91 | #endif | |
92 | ||
93 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
94 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
95 | #else | |
18543a22 | 96 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
97 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
98 | #else | |
99 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
100 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
101 | #else | |
9f6ce990 | 102 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 |
7a801826 RE |
103 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
104 | #else | |
105 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm | |
106 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" | |
107 | #else | |
108 | Unrecognized value in TARGET_CPU_DEFAULT. | |
109 | #endif | |
110 | #endif | |
111 | #endif | |
112 | #endif | |
113 | #endif | |
114 | ||
ff9940b0 RE |
115 | #ifndef CPP_PREDEFINES |
116 | #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" | |
117 | #endif | |
35d965d5 | 118 | |
38fc909b RE |
119 | #define CPP_SPEC "\ |
120 | %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \ | |
121 | %(cpp_endian) %(subtarget_cpp_spec)" | |
7a801826 | 122 | |
71791e16 RE |
123 | /* Set the architecture define -- if -march= is set, then it overrides |
124 | the -mcpu= setting. */ | |
7a801826 | 125 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
126 | %{march=arm2:-D__ARM_ARCH_2__} \ |
127 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
128 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
129 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
130 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
131 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
132 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
133 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
134 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 135 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
136 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
137 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
138 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
139 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
140 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
141 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
142 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
143 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
144 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 145 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
146 | %{march=arm920:-D__ARM_ARCH_4__} \ |
147 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 148 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
149 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
150 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 151 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
71791e16 RE |
152 | %{march=armv2:-D__ARM_ARCH_2__} \ |
153 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
154 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
155 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
156 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
157 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 158 | %{march=armv5:-D__ARM_ARCH_5__} \ |
71791e16 RE |
159 | %{!march=*: \ |
160 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
161 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
162 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
163 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
164 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
165 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
166 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
167 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
168 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 169 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
170 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
171 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
172 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
173 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
174 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
175 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
176 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
177 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
178 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 179 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
180 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
181 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 182 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
183 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
184 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 185 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
dfa08768 | 186 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 187 | " |
7a801826 RE |
188 | |
189 | /* Define __APCS_26__ if the PC also contains the PSR */ | |
7a801826 RE |
190 | #define CPP_APCS_PC_SPEC "\ |
191 | %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ | |
192 | -D__APCS_32__} \ | |
193 | %{mapcs-26:-D__APCS_26__} \ | |
dfa08768 | 194 | %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \ |
7a801826 RE |
195 | " |
196 | ||
b355a481 | 197 | #ifndef CPP_APCS_PC_DEFAULT_SPEC |
7a801826 | 198 | #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__" |
b355a481 | 199 | #endif |
7a801826 RE |
200 | |
201 | #define CPP_FLOAT_SPEC "\ | |
202 | %{msoft-float:\ | |
203 | %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \ | |
204 | -D__SOFTFP__} \ | |
205 | %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \ | |
206 | " | |
207 | ||
208 | /* Default is hard float, which doesn't define anything */ | |
209 | #define CPP_FLOAT_DEFAULT_SPEC "" | |
210 | ||
211 | #define CPP_ENDIAN_SPEC "\ | |
6cfc7210 NC |
212 | %{mbig-endian: \ |
213 | %{mlittle-endian: \ | |
214 | %e-mbig-endian and -mlittle-endian may not be used together} \ | |
215 | -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \ | |
216 | %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \ | |
7a801826 RE |
217 | " |
218 | ||
219 | /* Default is little endian, which doesn't define anything. */ | |
b020fd92 | 220 | #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__" |
7a801826 | 221 | |
dfa08768 | 222 | #define CC1_SPEC "" |
7a801826 RE |
223 | |
224 | /* This macro defines names of additional specifications to put in the specs | |
225 | that can be used in various specifications like CC1_SPEC. Its definition | |
226 | is an initializer with a subgrouping for each command option. | |
227 | ||
228 | Each subgrouping contains a string constant, that defines the | |
229 | specification name, and a string constant that used by the GNU CC driver | |
230 | program. | |
231 | ||
232 | Do not define this macro if it does not need to do anything. */ | |
233 | #define EXTRA_SPECS \ | |
234 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
235 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
236 | { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \ | |
237 | { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \ | |
238 | { "cpp_float", CPP_FLOAT_SPEC }, \ | |
239 | { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ | |
240 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
241 | { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ | |
38fc909b | 242 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
243 | SUBTARGET_EXTRA_SPECS |
244 | ||
914a3b8c | 245 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 246 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
247 | #endif |
248 | ||
6cfc7210 | 249 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 250 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 251 | #endif |
7a801826 | 252 | |
35d965d5 RS |
253 | \f |
254 | /* Run-time Target Specification. */ | |
ff9940b0 | 255 | #ifndef TARGET_VERSION |
6cfc7210 | 256 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 257 | #endif |
35d965d5 | 258 | |
35d965d5 RS |
259 | /* Nonzero if the function prologue (and epilogue) should obey |
260 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 261 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
262 | |
263 | /* Nonzero if the function prologue should output the function name to enable | |
264 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
265 | unused on RISCiX). Specifying this flag also enables |
266 | -fno-omit-frame-pointer. | |
35d965d5 | 267 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 268 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
269 | |
270 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
271 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 272 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 273 | |
11c1a207 RE |
274 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
275 | that assume restoration of the condition flags when returning from a | |
276 | branch and link (ie a function). */ | |
6cfc7210 | 277 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 278 | |
dfa08768 RE |
279 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
280 | ||
11c1a207 RE |
281 | /* Nonzero if stack checking should be performed on entry to each function |
282 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 283 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
284 | |
285 | /* Nonzero if floating point parameters should be passed to functions in | |
286 | floating point registers. */ | |
6cfc7210 | 287 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
288 | |
289 | /* Nonzero if re-entrant, position independent code should be generated. | |
290 | This is equivalent to -fpic. */ | |
6cfc7210 | 291 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 292 | |
5f1e6755 NC |
293 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
294 | be loaded using either LDRH or LDRB instructions. */ | |
295 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
296 | |
297 | /* Nonzero if all floating point instructions are missing (and there is no | |
298 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 299 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
300 | |
301 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 302 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
303 | |
304 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 305 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 306 | |
ddee6aba RE |
307 | /* Nonzero if we should have little-endian words even when compiling for |
308 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 309 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 310 | |
f5a1b0d2 | 311 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 312 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 313 | |
c11145f6 | 314 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 315 | function tries to return. */ |
6cfc7210 | 316 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 317 | |
ed0e6530 | 318 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 319 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 320 | |
b020fd92 NC |
321 | /* Nonzero if all call instructions should be indirect. */ |
322 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
323 | ||
11c1a207 RE |
324 | #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME) |
325 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) | |
326 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
327 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
328 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
329 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
330 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
5f1e6755 | 331 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
332 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
333 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
334 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
6cfc7210 | 335 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 336 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 337 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 338 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 339 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 340 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
3ada8e17 DE |
341 | |
342 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. | |
343 | Bit 31 is reserved. See riscix.h. */ | |
344 | #ifndef SUBTARGET_SWITCHES | |
345 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
346 | #endif |
347 | ||
6cfc7210 NC |
348 | #define TARGET_SWITCHES \ |
349 | { \ | |
350 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
351 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
352 | "Generate APCS conformant stack frames" }, \ | |
353 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
354 | {"poke-function-name", ARM_FLAG_POKE, \ | |
355 | "Store function names in object code" }, \ | |
356 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
357 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
358 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
359 | "Use the 32bit version of the APCS" }, \ | |
360 | {"apcs-26", -ARM_FLAG_APCS_32, \ | |
361 | "Use the 26bit version of the APCS" }, \ | |
362 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ | |
363 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
364 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
365 | "Pass FP arguments in FP registers" }, \ | |
366 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
367 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
368 | "Generate re-entrant, PIC code" }, \ | |
369 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
5f1e6755 | 370 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ |
82e9d970 | 371 | "The MMU will trap on unaligned accesses" }, \ |
5f1e6755 NC |
372 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ |
373 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
374 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
375 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
376 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
6cfc7210 NC |
377 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ |
378 | "Use library calls to perform FP operations" }, \ | |
379 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
380 | "Use hardware floating point instructions" }, \ | |
381 | {"big-endian", ARM_FLAG_BIG_END, \ | |
382 | "Assume target CPU is configured as big endian" }, \ | |
383 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
384 | "Assume target CPU is configured as little endian" }, \ | |
385 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
386 | "Assume big endian bytes, little endian words" }, \ | |
387 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
7e58a4d3 | 388 | "Support calls between THUMB and ARM instructions sets" }, \ |
6cfc7210 NC |
389 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ |
390 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
82e9d970 | 391 | "Generate a call to abort if a noreturn function returns"},\ |
dd18ae56 | 392 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \ |
6cfc7210 NC |
393 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \ |
394 | "Do not move instructions into a function's prologue" }, \ | |
395 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \ | |
ed0e6530 PB |
396 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ |
397 | "Do not load the PIC register in function prologues" }, \ | |
dd18ae56 | 398 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ |
b020fd92 | 399 | {"long-calls", ARM_FLAG_LONG_CALLS, \ |
82e9d970 | 400 | "Generate all call instructions as indirect calls"}, \ |
b020fd92 | 401 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \ |
6cfc7210 | 402 | SUBTARGET_SWITCHES \ |
949d79eb | 403 | {"", TARGET_DEFAULT, "" } \ |
35d965d5 RS |
404 | } |
405 | ||
43cffd11 RE |
406 | #define TARGET_OPTIONS \ |
407 | { \ | |
f5a1b0d2 NC |
408 | {"cpu=", & arm_select[0].string, \ |
409 | "Specify the name of the target CPU" }, \ | |
410 | {"arch=", & arm_select[1].string, \ | |
411 | "Specify the name of the target architecture" }, \ | |
412 | {"tune=", & arm_select[2].string, "" }, \ | |
413 | {"fpe=", & target_fp_name, "" }, \ | |
414 | {"fp=", & target_fp_name, \ | |
415 | "Specify the version of the floating point emulator" }, \ | |
416 | { "structure-size-boundary=", & structure_size_string, \ | |
82e9d970 | 417 | "Specify the minimum bit alignment of structures" }, \ |
ed0e6530 PB |
418 | { "pic-register=", & arm_pic_register_string, \ |
419 | "Specify the register to be used for PIC addressing" } \ | |
11c1a207 | 420 | } |
ff9940b0 | 421 | |
62dd06ea RE |
422 | struct arm_cpu_select |
423 | { | |
f9cc092a RE |
424 | const char * string; |
425 | const char * name; | |
426 | const struct processors * processors; | |
62dd06ea RE |
427 | }; |
428 | ||
f5a1b0d2 NC |
429 | /* This is a magic array. If the user specifies a command line switch |
430 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
431 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
432 | extern struct arm_cpu_select arm_select[]; |
433 | ||
11c1a207 RE |
434 | enum prog_mode_type |
435 | { | |
436 | prog_mode26, | |
437 | prog_mode32 | |
438 | }; | |
439 | ||
440 | /* Recast the program mode class to be the prog_mode attribute */ | |
441 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
442 | ||
443 | extern enum prog_mode_type arm_prgmode; | |
444 | ||
445 | /* What sort of floating point unit do we have? Hardware or software. | |
446 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
447 | enum floating_point_type |
448 | { | |
449 | FP_HARD, | |
11c1a207 RE |
450 | FP_SOFT2, |
451 | FP_SOFT3 | |
24f0c1b4 RE |
452 | }; |
453 | ||
454 | /* Recast the floating point class to be the floating point attribute. */ | |
455 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
456 | ||
71791e16 | 457 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
458 | extern enum floating_point_type arm_fpu; |
459 | ||
71791e16 RE |
460 | /* What type of floating point instructions are available */ |
461 | extern enum floating_point_type arm_fpu_arch; | |
462 | ||
18543a22 | 463 | /* Default floating point architecture. Override in sub-target if |
71791e16 RE |
464 | necessary. */ |
465 | #define FP_DEFAULT FP_SOFT2 | |
466 | ||
11c1a207 RE |
467 | /* Nonzero if the processor has a fast multiply insn, and one that does |
468 | a 64-bit multiply of two 32-bit values. */ | |
469 | extern int arm_fast_multiply; | |
470 | ||
71791e16 | 471 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
472 | extern int arm_arch4; |
473 | ||
62b10bbc NC |
474 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
475 | extern int arm_arch5; | |
476 | ||
f5a1b0d2 NC |
477 | /* Nonzero if this chip can benefit from load scheduling. */ |
478 | extern int arm_ld_sched; | |
479 | ||
480 | /* Nonzero if this chip is a StrongARM. */ | |
481 | extern int arm_is_strong; | |
482 | ||
483 | /* Nonzero if this chip is a an ARM6 or an ARM7. */ | |
484 | extern int arm_is_6_or_7; | |
485 | ||
2ce9c1b9 | 486 | #ifndef TARGET_DEFAULT |
35d965d5 | 487 | #define TARGET_DEFAULT 0 |
2ce9c1b9 | 488 | #endif |
35d965d5 | 489 | |
11c1a207 RE |
490 | /* The frame pointer register used in gcc has nothing to do with debugging; |
491 | that is controlled by the APCS-FRAME option. */ | |
914a3b8c | 492 | /* Not fully implemented yet. */ |
11c1a207 | 493 | /* #define CAN_DEBUG_WITHOUT_FP 1 */ |
35d965d5 | 494 | |
11c1a207 RE |
495 | #define TARGET_MEM_FUNCTIONS 1 |
496 | ||
497 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
498 | |
499 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
500 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
501 | Subtargets can override these if required. */ |
502 | #ifndef NEED_GOT_RELOC | |
503 | #define NEED_GOT_RELOC 0 | |
504 | #endif | |
505 | #ifndef NEED_PLT_RELOC | |
506 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 507 | #endif |
84306176 PB |
508 | |
509 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
510 | offset. In other words, generate | |
511 | ||
512 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
513 | ||
514 | rather than | |
515 | ||
516 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
517 | ||
518 | The default is true, which matches NetBSD. Subtargets can | |
519 | override this if required. */ | |
520 | #ifndef GOT_PCREL | |
521 | #define GOT_PCREL 1 | |
522 | #endif | |
35d965d5 RS |
523 | \f |
524 | /* Target machine storage Layout. */ | |
525 | ||
ff9940b0 RE |
526 | |
527 | /* Define this macro if it is advisable to hold scalars in registers | |
528 | in a wider mode than that declared by the program. In such cases, | |
529 | the value is constrained to be within the bounds of the declared | |
530 | type, but kept valid in the wider mode. The signedness of the | |
531 | extension may differ from that of the type. */ | |
532 | ||
533 | /* It is far faster to zero extend chars than to sign extend them */ | |
534 | ||
6cfc7210 | 535 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
536 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
537 | && GET_MODE_SIZE (MODE) < 4) \ | |
538 | { \ | |
539 | if (MODE == QImode) \ | |
540 | UNSIGNEDP = 1; \ | |
541 | else if (MODE == HImode) \ | |
5f1e6755 | 542 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 543 | (MODE) = SImode; \ |
ff9940b0 RE |
544 | } |
545 | ||
18543a22 ILT |
546 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
547 | should also be done for outgoing function arguments. */ | |
548 | /* This is required to ensure that push insns always push a word. */ | |
549 | #define PROMOTE_FUNCTION_ARGS | |
550 | ||
ff9940b0 RE |
551 | /* Define for XFmode extended real floating point support. |
552 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
553 | /* For the ARM: | |
554 | I think I have added all the code to make this work. Unfortunately, | |
555 | early releases of the floating point emulation code on RISCiX used a | |
556 | different format for extended precision numbers. On my RISCiX box there | |
557 | is a bug somewhere which causes the machine to lock up when running enquire | |
558 | with long doubles. There is the additional aspect that Norcroft C | |
559 | treats long doubles as doubles and we ought to remain compatible. | |
560 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
561 | to try this someday. */ | |
562 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
563 | ||
564 | /* Disable XFmode patterns in md file */ | |
565 | #define ENABLE_XF_PATTERNS 0 | |
566 | ||
567 | /* Define if you don't want extended real, but do want to use the | |
568 | software floating point emulator for REAL_ARITHMETIC and | |
569 | decimal <-> binary conversion. */ | |
570 | /* See comment above */ | |
571 | #define REAL_ARITHMETIC | |
572 | ||
35d965d5 RS |
573 | /* Define this if most significant bit is lowest numbered |
574 | in instructions that operate on numbered bit-fields. */ | |
575 | #define BITS_BIG_ENDIAN 0 | |
576 | ||
9c872872 | 577 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
578 | Most ARM processors are run in little endian mode, so that is the default. |
579 | If you want to have it run-time selectable, change the definition in a | |
580 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 581 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
582 | |
583 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
584 | numbered. |
585 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
586 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
587 | ||
588 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
589 | on processor pre-defineds when compiling libgcc2.c. */ | |
590 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
591 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
592 | #else | |
593 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
594 | #endif | |
35d965d5 | 595 | |
11c1a207 RE |
596 | /* Define this if most significant word of doubles is the lowest numbered. |
597 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
598 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
599 | ||
b4ac57ab | 600 | /* Number of bits in an addressable storage unit */ |
35d965d5 RS |
601 | #define BITS_PER_UNIT 8 |
602 | ||
603 | #define BITS_PER_WORD 32 | |
604 | ||
605 | #define UNITS_PER_WORD 4 | |
606 | ||
607 | #define POINTER_SIZE 32 | |
608 | ||
609 | #define PARM_BOUNDARY 32 | |
610 | ||
611 | #define STACK_BOUNDARY 32 | |
612 | ||
613 | #define FUNCTION_BOUNDARY 32 | |
614 | ||
615 | #define EMPTY_FIELD_BOUNDARY 32 | |
616 | ||
617 | #define BIGGEST_ALIGNMENT 32 | |
618 | ||
ff9940b0 RE |
619 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
620 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
621 | (TREE_CODE (EXP) == STRING_CST \ | |
622 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
623 | ||
723ae7c1 NC |
624 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
625 | value set in previous versions of this toolchain was 8, which produces more | |
626 | compact structures. The command line option -mstructure_size_boundary=<n> | |
627 | can be used to change this value. For compatability with the ARM SDK | |
628 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI | |
629 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
630 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
631 | extern int arm_structure_size_boundary; | |
723ae7c1 NC |
632 | |
633 | /* This is the value used to initialise arm_structure_size_boundary. If a | |
634 | particular arm target wants to change the default value it should change | |
635 | the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h | |
636 | for an example of this. */ | |
637 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
638 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 639 | #endif |
2a5307b1 | 640 | |
b355a481 | 641 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 642 | extern const char * structure_size_string; |
b4ac57ab | 643 | |
ff9940b0 RE |
644 | /* Non-zero if move instructions will actually fail to work |
645 | when given unaligned data. */ | |
35d965d5 RS |
646 | #define STRICT_ALIGNMENT 1 |
647 | ||
ff9940b0 RE |
648 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
649 | ||
35d965d5 RS |
650 | \f |
651 | /* Standard register usage. */ | |
652 | ||
653 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
654 | (S - saved over call). | |
655 | ||
656 | r0 * argument word/integer result | |
657 | r1-r3 argument word | |
658 | ||
659 | r4-r8 S register variable | |
660 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
661 | |
662 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
663 | r11 F S (fp) argument pointer |
664 | r12 (ip) temp workspace | |
665 | r13 F S (sp) lower end of current stack frame | |
666 | r14 (lr) link address/workspace | |
667 | r15 F (pc) program counter | |
668 | ||
669 | f0 floating point result | |
670 | f1-f3 floating point scratch | |
671 | ||
672 | f4-f7 S floating point variable | |
673 | ||
ff9940b0 RE |
674 | cc This is NOT a real register, but is used internally |
675 | to represent things that use or set the condition | |
676 | codes. | |
677 | sfp This isn't either. It is used during rtl generation | |
678 | since the offset between the frame pointer and the | |
679 | auto's isn't known until after register allocation. | |
680 | afp Nor this, we only need this because of non-local | |
681 | goto. Without it fp appears to be used and the | |
682 | elimination code won't get rid of sfp. It tracks | |
683 | fp exactly at all times. | |
684 | ||
35d965d5 RS |
685 | *: See CONDITIONAL_REGISTER_USAGE */ |
686 | ||
ff9940b0 RE |
687 | /* The stack backtrace structure is as follows: |
688 | fp points to here: | save code pointer | [fp] | |
689 | | return link value | [fp, #-4] | |
690 | | return sp value | [fp, #-8] | |
691 | | return fp value | [fp, #-12] | |
692 | [| saved r10 value |] | |
693 | [| saved r9 value |] | |
694 | [| saved r8 value |] | |
695 | [| saved r7 value |] | |
696 | [| saved r6 value |] | |
697 | [| saved r5 value |] | |
698 | [| saved r4 value |] | |
699 | [| saved r3 value |] | |
700 | [| saved r2 value |] | |
701 | [| saved r1 value |] | |
702 | [| saved r0 value |] | |
703 | [| saved f7 value |] three words | |
704 | [| saved f6 value |] three words | |
705 | [| saved f5 value |] three words | |
706 | [| saved f4 value |] three words | |
707 | r0-r3 are not normally saved in a C function. */ | |
708 | ||
709 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ | |
710 | #define FIRST_PSEUDO_REGISTER 27 | |
35d965d5 RS |
711 | |
712 | /* 1 for registers that have pervasive standard uses | |
713 | and are not available for the register allocator. */ | |
714 | #define FIXED_REGISTERS \ | |
715 | { \ | |
716 | 0,0,0,0,0,0,0,0, \ | |
6cc8c0b3 | 717 | 0,0,0,1,0,1,0,1, \ |
ff9940b0 RE |
718 | 0,0,0,0,0,0,0,0, \ |
719 | 1,1,1 \ | |
35d965d5 RS |
720 | } |
721 | ||
722 | /* 1 for registers not available across function calls. | |
723 | These must include the FIXED_REGISTERS and also any | |
724 | registers that can be used without being saved. | |
725 | The latter must include the registers where values are returned | |
726 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
727 | Aside from that, you can include as many other registers as you like. |
728 | The CC is not preserved over function calls on the ARM 6, so it is | |
729 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
730 | #define CALL_USED_REGISTERS \ |
731 | { \ | |
732 | 1,1,1,1,0,0,0,0, \ | |
6cc8c0b3 | 733 | 0,0,0,1,1,1,1,1, \ |
ff9940b0 RE |
734 | 1,1,1,1,0,0,0,0, \ |
735 | 1,1,1 \ | |
35d965d5 RS |
736 | } |
737 | ||
6cc8c0b3 NC |
738 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
739 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
740 | #endif | |
741 | ||
35d965d5 | 742 | #define CONDITIONAL_REGISTER_USAGE \ |
3ada8e17 | 743 | { \ |
3ada8e17 DE |
744 | if (TARGET_SOFT_FLOAT) \ |
745 | { \ | |
746 | int regno; \ | |
747 | for (regno = 16; regno < 24; ++regno) \ | |
748 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
749 | } \ | |
7a801826 RE |
750 | if (flag_pic) \ |
751 | { \ | |
752 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
6ed30148 | 753 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ |
7a801826 | 754 | } \ |
6cc8c0b3 | 755 | else if (TARGET_APCS_STACK) \ |
f5a1b0d2 | 756 | { \ |
6cc8c0b3 NC |
757 | fixed_regs[10] = 1; \ |
758 | call_used_regs[10] = 1; \ | |
f5a1b0d2 | 759 | } \ |
6cc8c0b3 | 760 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ |
35d965d5 RS |
761 | } |
762 | ||
dd18ae56 NC |
763 | /* These are a couple of extensions to the formats accecpted |
764 | by asm_fprintf: | |
765 | %@ prints out ASM_COMMENT_START | |
766 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
767 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
768 | case '@': \ | |
769 | fputs (ASM_COMMENT_START, FILE); \ | |
770 | break; \ | |
771 | \ | |
772 | case 'r': \ | |
773 | fputs (REGISTER_PREFIX, FILE); \ | |
774 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
775 | break; | |
776 | ||
6cfc7210 NC |
777 | /* Convert fron bytes to ints. */ |
778 | #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
779 | ||
780 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
781 | #define NUM_REGS(MODE) \ | |
782 | NUM_INTS (GET_MODE_SIZE (MODE)) | |
783 | ||
784 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
785 | #define NUM_REGS2(MODE, TYPE) \ | |
786 | NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) | |
787 | ||
788 | /* The number of (integer) argument register available. */ | |
789 | #define NUM_ARG_REGS 4 | |
790 | ||
791 | /* Return the regiser number of the N'th (integer) argument. */ | |
792 | #define ARG_REGISTER(N) (N - 1) | |
793 | ||
794 | /* The number of the last argument register. */ | |
795 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
796 | ||
35d965d5 RS |
797 | /* Return number of consecutive hard regs needed starting at reg REGNO |
798 | to hold something of mode MODE. | |
799 | This is ordinarily the length in words of a value of mode MODE | |
800 | but can be less for certain modes in special long registers. | |
801 | ||
802 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP | |
803 | mode. */ | |
6cfc7210 NC |
804 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
805 | (( REGNO >= 16 \ | |
806 | && REGNO != FRAME_POINTER_REGNUM \ | |
807 | && REGNO != ARG_POINTER_REGNUM) \ | |
808 | ? 1 : NUM_REGS (MODE)) | |
35d965d5 RS |
809 | |
810 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
811 | This is TRUE for ARM regs since they can hold anything, and TRUE for FPU | |
812 | regs holding FP. */ | |
ff9940b0 RE |
813 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
814 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
815 | ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
816 | || REGNO == ARG_POINTER_REGNUM \ | |
817 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) | |
35d965d5 RS |
818 | |
819 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
820 | when one has mode MODE1 and one has mode MODE2. | |
821 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
822 | for any hard reg, then this must be 0 for correct output. */ | |
823 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
3967692c | 824 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) |
35d965d5 RS |
825 | |
826 | /* Specify the registers used for certain standard purposes. | |
827 | The values of these macros are register numbers. */ | |
828 | ||
829 | /* Define this if the program counter is overloaded on a register. */ | |
830 | #define PC_REGNUM 15 | |
831 | ||
832 | /* Register to use for pushing function arguments. */ | |
833 | #define STACK_POINTER_REGNUM 13 | |
6cfc7210 | 834 | #define SP_REGNUM STACK_POINTER_REGNUM |
35d965d5 RS |
835 | |
836 | /* Base register for access to local variables of the function. */ | |
ff9940b0 RE |
837 | #define FRAME_POINTER_REGNUM 25 |
838 | ||
839 | /* Define this to be where the real frame pointer is if it is not possible to | |
840 | work out the offset between the frame pointer and the automatic variables | |
841 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
842 | should point to a special register that we will make sure is eliminated. */ | |
843 | #define HARD_FRAME_POINTER_REGNUM 11 | |
6cfc7210 | 844 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
35d965d5 | 845 | |
62b10bbc NC |
846 | /* Register which holds return address from a subroutine call. */ |
847 | #define LR_REGNUM 14 | |
848 | ||
849 | /* Scratch register - used in all kinds of places, eg trampolines. */ | |
850 | #define IP_REGNUM 12 | |
851 | ||
35d965d5 RS |
852 | /* Value should be nonzero if functions must have frame pointers. |
853 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
854 | via the stack pointer) in functions that seem suitable. |
855 | If we have to have a frame pointer we might as well make use of it. | |
856 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 857 | functions, or simple tail call functions. */ |
688743e7 RE |
858 | #define FRAME_POINTER_REQUIRED \ |
859 | (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) | |
35d965d5 RS |
860 | |
861 | /* Base register for access to arguments of the function. */ | |
ff9940b0 | 862 | #define ARG_POINTER_REGNUM 26 |
35d965d5 RS |
863 | |
864 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain | |
865 | as an invisible last argument (possible since varargs don't exist in | |
866 | Pascal), so the following is not true. */ | |
867 | #define STATIC_CHAIN_REGNUM 8 | |
868 | ||
869 | /* Register in which address to store a structure value | |
870 | is passed to a function. */ | |
871 | #define STRUCT_VALUE_REGNUM 0 | |
872 | ||
ff9940b0 RE |
873 | /* Internal, so that we don't need to refer to a raw number */ |
874 | #define CC_REGNUM 24 | |
875 | ||
35d965d5 | 876 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
877 | since no saving is required (though calls clobber it) and it never contains |
878 | function parameters. It is quite good to use lr since other calls may | |
879 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
880 | least likely to contain a function parameter; in addition results are | |
881 | returned in r0. | |
882 | */ | |
ff73fb53 | 883 | #define REG_ALLOC_ORDER \ |
35d965d5 | 884 | { \ |
ff73fb53 NC |
885 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
886 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 887 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
ff73fb53 | 888 | 24, 25, 26 \ |
35d965d5 RS |
889 | } |
890 | \f | |
891 | /* Register and constant classes. */ | |
892 | ||
893 | /* Register classes: all ARM regs or all FPU regs---simple! */ | |
894 | enum reg_class | |
895 | { | |
896 | NO_REGS, | |
897 | FPU_REGS, | |
898 | GENERAL_REGS, | |
899 | ALL_REGS, | |
900 | LIM_REG_CLASSES | |
901 | }; | |
902 | ||
903 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
904 | ||
905 | /* Give names of register classes as strings for dump file. */ | |
906 | #define REG_CLASS_NAMES \ | |
907 | { \ | |
908 | "NO_REGS", \ | |
909 | "FPU_REGS", \ | |
910 | "GENERAL_REGS", \ | |
911 | "ALL_REGS", \ | |
912 | } | |
913 | ||
914 | /* Define which registers fit in which classes. | |
915 | This is an initializer for a vector of HARD_REG_SET | |
916 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
917 | #define REG_CLASS_CONTENTS \ |
918 | { \ | |
919 | { 0x0000000 }, /* NO_REGS */ \ | |
920 | { 0x0FF0000 }, /* FPU_REGS */ \ | |
921 | { 0x200FFFF }, /* GENERAL_REGS */ \ | |
922 | { 0x2FFFFFF } /* ALL_REGS */ \ | |
35d965d5 RS |
923 | } |
924 | ||
925 | /* The same information, inverted: | |
926 | Return the class number of the smallest class containing | |
927 | reg number REGNO. This could be a conditional expression | |
928 | or could index an array. */ | |
ff9940b0 RE |
929 | #define REGNO_REG_CLASS(REGNO) \ |
930 | (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
931 | || REGNO == ARG_POINTER_REGNUM) \ | |
932 | ? GENERAL_REGS : (REGNO) == CC_REGNUM \ | |
933 | ? NO_REGS : FPU_REGS) | |
35d965d5 RS |
934 | |
935 | /* The class value for index registers, and the one for base regs. */ | |
936 | #define INDEX_REG_CLASS GENERAL_REGS | |
937 | #define BASE_REG_CLASS GENERAL_REGS | |
938 | ||
939 | /* Get reg_class from a letter such as appears in the machine description. | |
940 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ | |
941 | #define REG_CLASS_FROM_LETTER(C) \ | |
942 | ((C)=='f' ? FPU_REGS : NO_REGS) | |
943 | ||
944 | /* The letters I, J, K, L and M in a register constraint string | |
945 | can be used to stand for particular ranges of immediate operands. | |
946 | This macro defines what the ranges are. | |
947 | C is the letter, and VALUE is a constant value. | |
948 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 949 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 950 | J: valid indexing constants. |
aef1764c | 951 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
952 | L: -value ok in rhs argument of data operand. |
953 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
aef1764c RE |
954 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
955 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ | |
956 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
957 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
958 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
959 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
960 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
961 | : 0) | |
ff9940b0 RE |
962 | |
963 | /* For the ARM, `Q' means that this is a memory operand that is just | |
964 | an offset from a register. | |
965 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
966 | address. This means that the symbol is in the text segment and can be | |
967 | accessed without using a load. */ | |
968 | ||
7a801826 RE |
969 | #define EXTRA_CONSTRAINT(OP, C) \ |
970 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
971 | : (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
972 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
973 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ | |
974 | : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
975 | : 0) | |
ff9940b0 RE |
976 | |
977 | /* Constant letter 'G' for the FPU immediate constants. | |
978 | 'H' means the same constant negated. */ | |
979 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ | |
980 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ | |
981 | : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
35d965d5 RS |
982 | |
983 | /* Given an rtx X being reloaded into a reg required to be | |
984 | in class CLASS, return the class of reg to actually use. | |
985 | In general this is just CLASS; but on some machines | |
986 | in some cases it is preferable to use a more restrictive class. */ | |
987 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) | |
988 | ||
ff9940b0 RE |
989 | /* Return the register class of a scratch register needed to copy IN into |
990 | or out of a register in CLASS in MODE. If it can be done directly, | |
991 | NO_REGS is returned. */ | |
11c1a207 RE |
992 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
993 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
994 | ? GENERAL_REGS : NO_REGS) | |
ff9940b0 | 995 | |
2ce9c1b9 | 996 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
ed4c4348 | 997 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
5f1e6755 | 998 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ |
ed4c4348 RE |
999 | && (GET_CODE (X) == MEM \ |
1000 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1001 | && true_regnum (X) == -1))) \ | |
2ce9c1b9 RE |
1002 | ? GENERAL_REGS : NO_REGS) |
1003 | ||
6f734908 RE |
1004 | /* Try a machine-dependent way of reloading an illegitimate address |
1005 | operand. If we find one, push the reload and jump to WIN. This | |
1006 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1007 | ||
1008 | For the ARM, we wish to handle large displacements off a base | |
1009 | register by splitting the addend across a MOV and the mem insn. | |
1010 | This can cut the number of reloads needed. */ | |
15052bd1 BS |
1011 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ |
1012 | do \ | |
1013 | { \ | |
1014 | if (GET_CODE (X) == PLUS \ | |
1015 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1016 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1017 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1018 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1019 | { \ | |
1020 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1021 | HOST_WIDE_INT low, high; \ | |
1022 | \ | |
1023 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1024 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
1025 | else if (MODE == SImode \ | |
1026 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1027 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1028 | /* Need to be careful, -4096 is not a valid offset */ \ | |
1029 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1030 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1031 | /* Need to be careful, -256 is not a valid offset */ \ | |
1032 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1033 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1034 | && TARGET_HARD_FLOAT) \ | |
1035 | /* Need to be careful, -1024 is not a valid offset */ \ | |
1036 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1037 | else \ | |
1038 | break; \ | |
1039 | \ | |
1040 | high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \ | |
1041 | /* Check for overflow or zero */ \ | |
1042 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1043 | break; \ | |
1044 | \ | |
1045 | /* Reload the high part into a base reg; leave the low part \ | |
1046 | in the mem. */ \ | |
1047 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1048 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1049 | GEN_INT (high)), \ | |
1050 | GEN_INT (low)); \ | |
1051 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1052 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1053 | OPNUM, TYPE); \ | |
1054 | goto WIN; \ | |
1055 | } \ | |
1056 | } \ | |
62b10bbc | 1057 | while (0) |
6f734908 | 1058 | |
35d965d5 RS |
1059 | /* Return the maximum number of consecutive registers |
1060 | needed to represent mode MODE in a register of class CLASS. | |
1061 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
1062 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
6cfc7210 | 1063 | ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE)) |
35d965d5 | 1064 | |
ff9940b0 | 1065 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
35d965d5 RS |
1066 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
1067 | ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ | |
1068 | || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ | |
ff9940b0 | 1069 | ? 20 : 2) |
35d965d5 RS |
1070 | \f |
1071 | /* Stack layout; function entry, exit and calling. */ | |
1072 | ||
1073 | /* Define this if pushing a word on the stack | |
1074 | makes the stack pointer a smaller address. */ | |
1075 | #define STACK_GROWS_DOWNWARD 1 | |
1076 | ||
1077 | /* Define this if the nominal address of the stack frame | |
1078 | is at the high-address end of the local variables; | |
1079 | that is, each additional local variable allocated | |
1080 | goes at a more negative offset in the frame. */ | |
1081 | #define FRAME_GROWS_DOWNWARD 1 | |
1082 | ||
1083 | /* Offset within stack frame to start allocating local variables at. | |
1084 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1085 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1086 | of the first local allocated. */ | |
1087 | #define STARTING_FRAME_OFFSET 0 | |
1088 | ||
1089 | /* If we generate an insn to push BYTES bytes, | |
1090 | this says how many the stack pointer really advances by. */ | |
18543a22 ILT |
1091 | /* The push insns do not do this rounding implicitly. So don't define this. */ |
1092 | /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */ | |
1093 | ||
1094 | /* Define this if the maximum size of all the outgoing args is to be | |
1095 | accumulated and pushed during the prologue. The amount can be | |
1096 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1097 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1098 | |
1099 | /* Offset of first parameter from the argument pointer register value. */ | |
1100 | #define FIRST_PARM_OFFSET(FNDECL) 4 | |
1101 | ||
1102 | /* Value is the number of byte of arguments automatically | |
1103 | popped when returning from a subroutine call. | |
8b109b37 | 1104 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1105 | FUNTYPE is the data type of the function (as a tree), |
1106 | or for a library call it is an identifier node for the subroutine name. | |
1107 | SIZE is the number of bytes of arguments passed on the stack. | |
1108 | ||
1109 | On the ARM, the caller does not pop any of its arguments that were passed | |
1110 | on the stack. */ | |
6cfc7210 | 1111 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1112 | |
1113 | /* Define how to find the value returned by a library function | |
1114 | assuming the value has mode MODE. */ | |
1115 | #define LIBCALL_VALUE(MODE) \ | |
3ada8e17 | 1116 | (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \ |
43cffd11 RE |
1117 | ? gen_rtx_REG (MODE, 16) \ |
1118 | : gen_rtx_REG (MODE, 0)) | |
35d965d5 | 1119 | |
6cfc7210 NC |
1120 | /* Define how to find the value returned by a function. |
1121 | VALTYPE is the data type of the value (as a tree). | |
1122 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1123 | otherwise, FUNC is 0. */ | |
1124 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1125 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) | |
1126 | ||
35d965d5 RS |
1127 | /* 1 if N is a possible register number for a function value. |
1128 | On the ARM, only r0 and f0 can return results. */ | |
1129 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
aec3cfba | 1130 | ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT)) |
35d965d5 | 1131 | |
11c1a207 RE |
1132 | /* How large values are returned */ |
1133 | /* A C expression which can inhibit the returning of certain function values | |
1134 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1135 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1136 | |
1137 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1138 | values must be in memory. On the ARM, they need only do so if larger | |
1139 | than a word, or if they contain elements offset from zero in the struct. */ | |
1140 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1141 | ||
82e9d970 PB |
1142 | /* A C type for declaring a variable that is used as the first argument of |
1143 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1144 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1145 | typedef struct | |
1146 | { | |
1147 | /* This is the number of argument registers scanned so far. */ | |
1148 | int nregs; | |
1149 | /* instructions on how to process this call. */ | |
1150 | int call_cookie; | |
1151 | } | |
1152 | CUMULATIVE_ARGS; | |
1153 | ||
1154 | /* Flags for the call_cookie field of CUMULATIVE_ARGS. */ | |
1155 | #define CALL_NORMAL 0 /* No special processing. */ | |
1156 | #define CALL_LONG 1 /* Always call indirect. */ | |
1157 | #define CALL_SHORT 2 /* Never call indirect. */ | |
1158 | ||
35d965d5 RS |
1159 | /* Define where to put the arguments to a function. |
1160 | Value is zero to push the argument on the stack, | |
1161 | or a hard register in which to store the argument. | |
1162 | ||
1163 | MODE is the argument's machine mode. | |
1164 | TYPE is the data type of the argument (as a tree). | |
1165 | This is null for libcalls where that information may | |
1166 | not be available. | |
1167 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1168 | the preceding args and about the function being called. | |
1169 | NAMED is nonzero if this argument is a named parameter | |
1170 | (otherwise it is an extra parameter matching an ellipsis). | |
1171 | ||
1172 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1173 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1174 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1175 | passed in the stack (function_prologue will indeed make it pass in the | |
1176 | stack if necessary). */ | |
82e9d970 PB |
1177 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1178 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1179 | |
1180 | /* For an arg passed partly in registers and partly in memory, | |
1181 | this is the number of registers used. | |
1182 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1183 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 PB |
1184 | ( NUM_ARG_REGS > (CUM).nregs \ |
1185 | && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \ | |
1186 | ? NUM_ARG_REGS - (CUM).nregs : 0) | |
35d965d5 RS |
1187 | |
1188 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1189 | for a call to a function whose data type is FNTYPE. | |
1190 | For a library call, FNTYPE is 0. | |
1191 | On the ARM, the offset starts at 0. */ | |
82e9d970 PB |
1192 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1193 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) | |
35d965d5 RS |
1194 | |
1195 | /* Update the data in CUM to advance over an argument | |
1196 | of mode MODE and data type TYPE. | |
1197 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1198 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1199 | (CUM).nregs += NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1200 | |
1201 | /* 1 if N is a possible register number for function argument passing. | |
1202 | On the ARM, r0-r3 are used to pass args. */ | |
1203 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1204 | ((REGNO) >= 0 && (REGNO) <= 3) | |
1205 | ||
1206 | /* Perform any actions needed for a function that is receiving a variable | |
1207 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1208 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1209 | the amount of stack that must be pushed by the prolog to pretend that our | |
1210 | caller pushed it. | |
1211 | ||
1212 | Normally, this macro will push all remaining incoming registers on the | |
1213 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1214 | ||
1215 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1216 | named arg and all anonymous args onto the stack. | |
1217 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1218 | that way. */ | |
6cfc7210 | 1219 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 RS |
1220 | { \ |
1221 | extern int current_function_anonymous_args; \ | |
1222 | current_function_anonymous_args = 1; \ | |
82e9d970 PB |
1223 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1224 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1225 | } |
1226 | ||
1227 | /* Generate assembly output for the start of a function. */ | |
1228 | #define FUNCTION_PROLOGUE(STREAM, SIZE) \ | |
008cf58a | 1229 | output_func_prologue ((STREAM), (SIZE)) |
35d965d5 | 1230 | |
afef3d7a NC |
1231 | /* If your target environment doesn't prefix user functions with an |
1232 | underscore, you may wish to re-define this to prevent any conflicts. | |
1233 | e.g. AOF may prefix mcount with an underscore. */ | |
1234 | #ifndef ARM_MCOUNT_NAME | |
1235 | #define ARM_MCOUNT_NAME "*mcount" | |
1236 | #endif | |
1237 | ||
1238 | /* Call the function profiler with a given profile label. The Acorn | |
1239 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1240 | On the ARM the full profile code will look like: | |
1241 | .data | |
1242 | LP1 | |
1243 | .word 0 | |
1244 | .text | |
1245 | mov ip, lr | |
1246 | bl mcount | |
1247 | .word LP1 | |
1248 | ||
1249 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1250 | will output the .text section. | |
1251 | ||
1252 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
1253 | ``prof'' doesn't seem to mind about this! */ | |
6cfc7210 NC |
1254 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1255 | { \ | |
1256 | char temp[20]; \ | |
1257 | rtx sym; \ | |
1258 | \ | |
dd18ae56 NC |
1259 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
1260 | IP_REGNUM, LR_REGNUM); \ | |
6cfc7210 NC |
1261 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1262 | fputc ('\n', STREAM); \ | |
1263 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1264 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
1265 | ASM_OUTPUT_INT (STREAM, sym); \ | |
35d965d5 RS |
1266 | } |
1267 | ||
1268 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1269 | the stack pointer does not matter. The value is tested only in | |
1270 | functions that have frame pointers. | |
1271 | No definition is equivalent to always zero. | |
1272 | ||
1273 | On the ARM, the function epilogue recovers the stack pointer from the | |
1274 | frame. */ | |
1275 | #define EXIT_IGNORE_STACK 1 | |
1276 | ||
1277 | /* Generate the assembly code for function exit. */ | |
1278 | #define FUNCTION_EPILOGUE(STREAM, SIZE) \ | |
eb3921e8 | 1279 | output_func_epilogue (SIZE) |
35d965d5 RS |
1280 | |
1281 | /* Determine if the epilogue should be output as RTL. | |
1282 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
b36ba79f | 1283 | #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND) |
ff9940b0 RE |
1284 | |
1285 | /* Definitions for register eliminations. | |
1286 | ||
1287 | This is an array of structures. Each structure initializes one pair | |
1288 | of eliminable registers. The "from" register number is given first, | |
1289 | followed by "to". Eliminations of the same "from" register are listed | |
1290 | in order of preference. | |
1291 | ||
1292 | We have two registers that can be eliminated on the ARM. First, the | |
1293 | arg pointer register can often be eliminated in favor of the stack | |
1294 | pointer register. Secondly, the pseudo frame pointer register can always | |
1295 | be eliminated; it is replaced with either the stack or the real frame | |
1296 | pointer. */ | |
1297 | ||
1298 | #define ELIMINABLE_REGS \ | |
6cfc7210 NC |
1299 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ |
1300 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
1301 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
1302 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 RE |
1303 | |
1304 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1305 | Frame pointer elimination is automatically handled. | |
1306 | ||
1307 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1308 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 RE |
1309 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
1310 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ | |
1311 | #define CAN_ELIMINATE(FROM, TO) \ | |
1312 | (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) | |
1313 | ||
1314 | /* Define the offset between two registers, one to be eliminated, and the other | |
1315 | its replacement, at the start of a routine. */ | |
1316 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1317 | { \ | |
3967692c | 1318 | int volatile_func = arm_volatile_func (); \ |
ff9940b0 RE |
1319 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ |
1320 | (OFFSET) = 0; \ | |
18543a22 ILT |
1321 | else if ((FROM) == FRAME_POINTER_REGNUM \ |
1322 | && (TO) == STACK_POINTER_REGNUM) \ | |
9daca635 NC |
1323 | (OFFSET) = current_function_outgoing_args_size \ |
1324 | + ((get_frame_size () + 3) & ~3); \ | |
ff9940b0 RE |
1325 | else \ |
1326 | { \ | |
1327 | int regno; \ | |
1328 | int offset = 12; \ | |
008cf58a | 1329 | int saved_hard_reg = 0; \ |
ff9940b0 | 1330 | \ |
3967692c RE |
1331 | if (! volatile_func) \ |
1332 | { \ | |
1333 | for (regno = 0; regno <= 10; regno++) \ | |
1334 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1335 | saved_hard_reg = 1, offset += 4; \ | |
6ed30148 RE |
1336 | /* PIC register is a fixed reg, so call_used_regs set. */ \ |
1337 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \ | |
1338 | saved_hard_reg = 1, offset += 4; \ | |
3967692c RE |
1339 | for (regno = 16; regno <=23; regno++) \ |
1340 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1341 | offset += 12; \ | |
1342 | } \ | |
ff9940b0 RE |
1343 | if ((FROM) == FRAME_POINTER_REGNUM) \ |
1344 | (OFFSET) = -offset; \ | |
1345 | else \ | |
1346 | { \ | |
bd4d60ce | 1347 | if (! frame_pointer_needed) \ |
ff9940b0 | 1348 | offset -= 16; \ |
18543a22 | 1349 | if (! volatile_func \ |
62b10bbc | 1350 | && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \ |
ff9940b0 | 1351 | offset += 4; \ |
18543a22 | 1352 | offset += current_function_outgoing_args_size; \ |
9daca635 | 1353 | (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \ |
ff9940b0 RE |
1354 | } \ |
1355 | } \ | |
1356 | } | |
35d965d5 | 1357 | |
35d965d5 RS |
1358 | /* Output assembler code for a block containing the constant parts |
1359 | of a trampoline, leaving space for the variable parts. | |
1360 | ||
1361 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1362 | referencing pc adds an offset of 8) the trampoline looks like: | |
1363 | ldr r8, [pc, #0] | |
1364 | ldr pc, [pc] | |
1365 | .word static chain value | |
11c1a207 RE |
1366 | .word function's address |
1367 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
4eda77ec RE |
1368 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1369 | { \ | |
afef3d7a NC |
1370 | fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \ |
1371 | REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \ | |
1372 | REGISTER_PREFIX, reg_names[PC_REGNUM]); \ | |
1373 | fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \ | |
1374 | REGISTER_PREFIX, reg_names[PC_REGNUM], \ | |
1375 | REGISTER_PREFIX, reg_names[PC_REGNUM]); \ | |
1376 | ASM_OUTPUT_INT ((FILE), const0_rtx); \ | |
1377 | ASM_OUTPUT_INT ((FILE), const0_rtx); \ | |
35d965d5 RS |
1378 | } |
1379 | ||
1380 | /* Length in units of the trampoline for entering a nested function. */ | |
1381 | #define TRAMPOLINE_SIZE 16 | |
1382 | ||
1383 | /* Alignment required for a trampoline in units. */ | |
1384 | #define TRAMPOLINE_ALIGN 4 | |
1385 | ||
1386 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1387 | FNADDR is an RTX for the address of the function's pure code. | |
1388 | CXT is an RTX for the static chain value for the function. */ | |
1389 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1390 | { \ | |
43cffd11 | 1391 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \ |
35d965d5 | 1392 | (CXT)); \ |
43cffd11 | 1393 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \ |
35d965d5 RS |
1394 | (FNADDR)); \ |
1395 | } | |
1396 | ||
35d965d5 RS |
1397 | \f |
1398 | /* Addressing modes, and classification of registers for them. */ | |
1399 | ||
1400 | #define HAVE_POST_INCREMENT 1 | |
6cfc7210 | 1401 | #define HAVE_PRE_INCREMENT 1 |
35d965d5 | 1402 | #define HAVE_POST_DECREMENT 1 |
6cfc7210 | 1403 | #define HAVE_PRE_DECREMENT 1 |
35d965d5 RS |
1404 | |
1405 | /* Macros to check register numbers against specific register classes. */ | |
1406 | ||
1407 | /* These assume that REGNO is a hard or pseudo reg number. | |
1408 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1409 | or a pseudo reg currently allocated to a suitable hard reg. | |
1410 | Since they use reg_renumber, they are safe only once reg_renumber | |
1411 | has been allocated, which happens in local-alloc.c. | |
1412 | ||
1413 | On the ARM, don't allow the pc to be used. */ | |
ff9940b0 RE |
1414 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1415 | ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1416 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1417 | || (unsigned) reg_renumber[(REGNO)] < 15 \ | |
1418 | || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ | |
1419 | || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) | |
1420 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
35d965d5 RS |
1421 | REGNO_OK_FOR_BASE_P(REGNO) |
1422 | ||
1423 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 RE |
1424 | Shifts in addresses can't be by a register. */ |
1425 | ||
1426 | #define MAX_REGS_PER_ADDRESS 2 | |
35d965d5 RS |
1427 | |
1428 | /* Recognize any constant value that is a valid address. */ | |
1429 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1430 | |
1431 | #ifdef AOF_ASSEMBLER | |
1432 | ||
1433 | #define CONSTANT_ADDRESS_P(X) \ | |
1434 | (GET_CODE (X) == SYMBOL_REF \ | |
1435 | && CONSTANT_POOL_ADDRESS_P (X)) | |
1436 | ||
1437 | #else | |
35d965d5 | 1438 | |
008cf58a RE |
1439 | #define CONSTANT_ADDRESS_P(X) \ |
1440 | (GET_CODE (X) == SYMBOL_REF \ | |
1441 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
1442 | || (optimize > 0 && SYMBOL_REF_FLAG (X)))) | |
35d965d5 | 1443 | |
11c1a207 RE |
1444 | #endif /* AOF_ASSEMBLER */ |
1445 | ||
35d965d5 RS |
1446 | /* Nonzero if the constant value X is a legitimate general operand. |
1447 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1448 | ||
1449 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1450 | patterns), nice doubles and symbol_refs which refer to the function's | |
82e9d970 PB |
1451 | constant pool XXX. |
1452 | ||
1453 | When generating pic allow anything. */ | |
1454 | #define LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) | |
1455 | ||
ff9940b0 RE |
1456 | /* Symbols in the text segment can be accessed without indirecting via the |
1457 | constant pool; it may take an extra binary operation, but this is still | |
008cf58a RE |
1458 | faster than indirecting via memory. Don't do this when not optimizing, |
1459 | since we won't be calculating al of the offsets necessary to do this | |
1460 | simplification. */ | |
11c1a207 RE |
1461 | /* This doesn't work with AOF syntax, since the string table may be in |
1462 | a different AREA. */ | |
1463 | #ifndef AOF_ASSEMBLER | |
ff9940b0 RE |
1464 | #define ENCODE_SECTION_INFO(decl) \ |
1465 | { \ | |
008cf58a | 1466 | if (optimize > 0 && TREE_CONSTANT (decl) \ |
ff9940b0 | 1467 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ |
228b6a3f RS |
1468 | { \ |
1469 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ | |
1470 | ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ | |
1471 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ | |
1472 | } \ | |
ff9940b0 | 1473 | } |
11c1a207 | 1474 | #endif |
7a801826 | 1475 | |
35d965d5 RS |
1476 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1477 | and check its validity for a certain class. | |
1478 | We have two alternate definitions for each of them. | |
1479 | The usual definition accepts all pseudo regs; the other rejects | |
1480 | them unless they have been allocated suitable hard regs. | |
1481 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1482 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1483 | |
35d965d5 RS |
1484 | /* Nonzero if X is a hard reg that can be used as a base reg |
1485 | or if it is a pseudo reg. */ | |
ff9940b0 RE |
1486 | #define REG_OK_FOR_BASE_P(X) \ |
1487 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1488 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1489 | ||
35d965d5 RS |
1490 | /* Nonzero if X is a hard reg that can be used as an index |
1491 | or if it is a pseudo reg. */ | |
1492 | #define REG_OK_FOR_INDEX_P(X) \ | |
1493 | REG_OK_FOR_BASE_P(X) | |
ff9940b0 RE |
1494 | |
1495 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1496 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1497 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1498 | ||
35d965d5 | 1499 | #else |
ff9940b0 | 1500 | |
35d965d5 RS |
1501 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
1502 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1503 | |
35d965d5 RS |
1504 | /* Nonzero if X is a hard reg that can be used as an index. */ |
1505 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
ff9940b0 RE |
1506 | |
1507 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1508 | (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ | |
1509 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ | |
1510 | || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ | |
1511 | || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) | |
1512 | ||
35d965d5 RS |
1513 | #endif |
1514 | \f | |
1515 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1516 | that is a valid memory address for an instruction. | |
1517 | The MODE argument is the machine mode for the MEM expression | |
1518 | that wants to use this address. | |
1519 | ||
1520 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1521 | #define BASE_REGISTER_RTX_P(X) \ | |
1522 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
1523 | ||
1524 | #define INDEX_REGISTER_RTX_P(X) \ | |
1525 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
1526 | ||
1527 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
1528 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
1529 | only be small constants. */ | |
62b10bbc NC |
1530 | #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
1531 | do \ | |
1532 | { \ | |
1533 | HOST_WIDE_INT range; \ | |
1534 | enum rtx_code code = GET_CODE (INDEX); \ | |
1535 | \ | |
1536 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ | |
1537 | { \ | |
1538 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
1539 | && INTVAL (INDEX) > -1024 \ | |
1540 | && (INTVAL (INDEX) & 3) == 0) \ | |
1541 | goto LABEL; \ | |
1542 | } \ | |
1543 | else \ | |
1544 | { \ | |
1545 | if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ | |
1546 | goto LABEL; \ | |
1547 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ | |
1548 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1549 | { \ | |
1550 | rtx xiop0 = XEXP (INDEX, 0); \ | |
1551 | rtx xiop1 = XEXP (INDEX, 1); \ | |
1552 | if (INDEX_REGISTER_RTX_P (xiop0) \ | |
1553 | && power_of_two_operand (xiop1, SImode)) \ | |
1554 | goto LABEL; \ | |
1555 | if (INDEX_REGISTER_RTX_P (xiop1) \ | |
1556 | && power_of_two_operand (xiop0, SImode)) \ | |
1557 | goto LABEL; \ | |
1558 | } \ | |
1559 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
1560 | && (code == LSHIFTRT || code == ASHIFTRT \ | |
1561 | || code == ASHIFT || code == ROTATERT) \ | |
1562 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1563 | { \ | |
1564 | rtx op = XEXP (INDEX, 1); \ | |
1565 | if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
1566 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
1567 | && INTVAL (op) <= 31) \ | |
1568 | goto LABEL; \ | |
1569 | } \ | |
1570 | /* NASTY: Since this limits the addressing of unsigned byte loads */ \ | |
1571 | range = ((MODE) == HImode || (MODE) == QImode) \ | |
1572 | ? (arm_arch4 ? 256 : 4095) : 4096; \ | |
1573 | if (code == CONST_INT && INTVAL (INDEX) < range \ | |
1574 | && INTVAL (INDEX) > -range) \ | |
1575 | goto LABEL; \ | |
1576 | } \ | |
1577 | } \ | |
1578 | while (0) | |
35d965d5 RS |
1579 | |
1580 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
1581 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
1582 | the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, | |
1583 | INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. | |
ff9940b0 RE |
1584 | Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol |
1585 | refs must be forced though a static cell to ensure addressability. */ | |
11c1a207 | 1586 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
35d965d5 RS |
1587 | { \ |
1588 | if (BASE_REGISTER_RTX_P (X)) \ | |
1589 | goto LABEL; \ | |
1590 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
1591 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1592 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1593 | goto LABEL; \ | |
11c1a207 RE |
1594 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ |
1595 | && (GET_CODE (X) == LABEL_REF \ | |
1596 | || (GET_CODE (X) == CONST \ | |
1597 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
1598 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
1599 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
1600 | goto LABEL; \ | |
35d965d5 RS |
1601 | else if ((MODE) == TImode) \ |
1602 | ; \ | |
11c1a207 RE |
1603 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ |
1604 | { \ | |
1605 | if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
1606 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1607 | { \ | |
1608 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1609 | if (val == 4 || val == -4 || val == -8) \ | |
1610 | goto LABEL; \ | |
1611 | } \ | |
1612 | } \ | |
35d965d5 RS |
1613 | else if (GET_CODE (X) == PLUS) \ |
1614 | { \ | |
1615 | rtx xop0 = XEXP(X,0); \ | |
1616 | rtx xop1 = XEXP(X,1); \ | |
1617 | \ | |
1618 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1619 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
1620 | else if (BASE_REGISTER_RTX_P (xop1)) \ | |
1621 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
1622 | } \ | |
18543a22 ILT |
1623 | /* Reload currently can't handle MINUS, so disable this for now */ \ |
1624 | /* else if (GET_CODE (X) == MINUS) \ | |
35d965d5 RS |
1625 | { \ |
1626 | rtx xop0 = XEXP (X,0); \ | |
1627 | rtx xop1 = XEXP (X,1); \ | |
1628 | \ | |
1629 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1630 | GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
18543a22 | 1631 | } */ \ |
35d965d5 RS |
1632 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ |
1633 | && GET_CODE (X) == SYMBOL_REF \ | |
43cffd11 RE |
1634 | && CONSTANT_POOL_ADDRESS_P (X) \ |
1635 | && ! (flag_pic \ | |
1636 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
35d965d5 RS |
1637 | goto LABEL; \ |
1638 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
11c1a207 | 1639 | && (GET_MODE_SIZE (MODE) <= 4) \ |
35d965d5 RS |
1640 | && GET_CODE (XEXP (X, 0)) == REG \ |
1641 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1642 | goto LABEL; \ | |
1643 | } | |
1644 | \f | |
1645 | /* Try machine-dependent ways of modifying an illegitimate address | |
1646 | to be legitimate. If we find one, return the new, valid address. | |
1647 | This macro is used in only one place: `memory_address' in explow.c. | |
1648 | ||
1649 | OLDX is the address as it was before break_out_memory_refs was called. | |
1650 | In some cases it is useful to look at this to decide what needs to be done. | |
1651 | ||
1652 | MODE and WIN are passed so that this macro can use | |
1653 | GO_IF_LEGITIMATE_ADDRESS. | |
1654 | ||
1655 | It is always safe for this macro to do nothing. It exists to recognize | |
1656 | opportunities to optimize the output. | |
1657 | ||
1658 | On the ARM, try to convert [REG, #BIGCONST] | |
1659 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
1660 | where VALIDCONST == 0 in case of TImode. */ | |
3967692c RE |
1661 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1662 | { \ | |
1663 | if (GET_CODE (X) == PLUS) \ | |
1664 | { \ | |
1665 | rtx xop0 = XEXP (X, 0); \ | |
1666 | rtx xop1 = XEXP (X, 1); \ | |
1667 | \ | |
11c1a207 | 1668 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 1669 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 1670 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1671 | xop1 = force_reg (SImode, xop1); \ |
1672 | if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ | |
1673 | { \ | |
1674 | HOST_WIDE_INT n, low_n; \ | |
1675 | rtx base_reg, val; \ | |
1676 | n = INTVAL (xop1); \ | |
1677 | \ | |
11c1a207 | 1678 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
1679 | { \ |
1680 | low_n = n & 0x0f; \ | |
1681 | n &= ~0x0f; \ | |
1682 | if (low_n > 4) \ | |
1683 | { \ | |
1684 | n += 16; \ | |
1685 | low_n -= 16; \ | |
1686 | } \ | |
1687 | } \ | |
1688 | else \ | |
1689 | { \ | |
1690 | low_n = ((MODE) == TImode ? 0 \ | |
1691 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
1692 | n -= low_n; \ | |
1693 | } \ | |
1694 | base_reg = gen_reg_rtx (SImode); \ | |
43cffd11 RE |
1695 | val = force_operand (gen_rtx_PLUS (SImode, xop0, \ |
1696 | GEN_INT (n)), NULL_RTX); \ | |
3967692c RE |
1697 | emit_move_insn (base_reg, val); \ |
1698 | (X) = (low_n == 0 ? base_reg \ | |
43cffd11 | 1699 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ |
3967692c RE |
1700 | } \ |
1701 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
43cffd11 | 1702 | (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ |
3967692c RE |
1703 | } \ |
1704 | else if (GET_CODE (X) == MINUS) \ | |
1705 | { \ | |
1706 | rtx xop0 = XEXP (X, 0); \ | |
1707 | rtx xop1 = XEXP (X, 1); \ | |
1708 | \ | |
1709 | if (CONSTANT_P (xop0)) \ | |
1710 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 1711 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1712 | xop1 = force_reg (SImode, xop1); \ |
1713 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
43cffd11 | 1714 | (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ |
3967692c | 1715 | } \ |
7a801826 RE |
1716 | if (flag_pic) \ |
1717 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
1718 | if (memory_address_p (MODE, X)) \ |
1719 | goto WIN; \ | |
35d965d5 RS |
1720 | } |
1721 | ||
1722 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1723 | has an effect that depends on the machine mode it is used for. */ | |
1724 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1725 | { \ | |
1726 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ | |
1727 | || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ | |
1728 | goto LABEL; \ | |
1729 | } | |
1730 | \f | |
1731 | /* Specify the machine mode that this machine uses | |
1732 | for the index in the tablejump instruction. */ | |
1733 | #define CASE_VECTOR_MODE SImode | |
1734 | ||
18543a22 ILT |
1735 | /* Define as C expression which evaluates to nonzero if the tablejump |
1736 | instruction expects the table to contain offsets from the address of the | |
1737 | table. | |
1738 | Do not define this if the table should contain absolute addresses. */ | |
1739 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 RS |
1740 | |
1741 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1742 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1743 | ||
1744 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1745 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1746 | ||
ff9940b0 RE |
1747 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
1748 | unsigned is probably best, but may break some code. */ | |
1749 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 1750 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
1751 | #endif |
1752 | ||
1753 | /* Don't cse the address of the function being compiled. */ | |
1754 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
1755 | ||
1756 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
1757 | in one reasonably fast instruction. */ |
1758 | #define MOVE_MAX 4 | |
35d965d5 | 1759 | |
ff9940b0 RE |
1760 | /* Define if operations between registers always perform the operation |
1761 | on the full register even if a narrower mode is specified. */ | |
1762 | #define WORD_REGISTER_OPERATIONS | |
1763 | ||
1764 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1765 | will either zero-extend or sign-extend. The value of this macro should | |
1766 | be the code that says which one of the two operations is implicitly | |
1767 | done, NIL if none. */ | |
9c872872 | 1768 | #define LOAD_EXTEND_OP(MODE) \ |
11c1a207 | 1769 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ |
9c872872 | 1770 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) |
ff9940b0 | 1771 | |
35d965d5 RS |
1772 | /* Define this if zero-extension is slow (more than one real instruction). |
1773 | On the ARM, it is more than one instruction only if not fetching from | |
1774 | memory. */ | |
1775 | /* #define SLOW_ZERO_EXTEND */ | |
1776 | ||
1777 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1778 | #define SLOW_BYTE_ACCESS 0 | |
1779 | ||
1780 | /* Immediate shift counts are truncated by the output routines (or was it | |
1781 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
1782 | that the native compiler puts too large (> 32) immediate shift counts | |
1783 | into a register and shifts by the register, letting the ARM decide what | |
1784 | to do instead of doing that itself. */ | |
ff9940b0 RE |
1785 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
1786 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1787 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
1788 | rotates is modulo 32 used. */ | |
1789 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 1790 | |
35d965d5 RS |
1791 | /* All integers have the same format so truncation is easy. */ |
1792 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
1793 | ||
1794 | /* Calling from registers is a massive pain. */ | |
1795 | #define NO_FUNCTION_CSE 1 | |
1796 | ||
1797 | /* Chars and shorts should be passed as ints. */ | |
1798 | #define PROMOTE_PROTOTYPES 1 | |
1799 | ||
35d965d5 RS |
1800 | /* The machine modes of pointers and functions */ |
1801 | #define Pmode SImode | |
1802 | #define FUNCTION_MODE Pmode | |
1803 | ||
1804 | /* The structure type of the machine dependent info field of insns | |
1805 | No uses for this yet. */ | |
1806 | /* #define INSN_MACHINE_INFO struct machine_info */ | |
1807 | ||
1808 | /* The relative costs of various types of constants. Note that cse.c defines | |
1809 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
ff9940b0 RE |
1810 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
1811 | case CONST_INT: \ | |
1812 | if (const_ok_for_arm (INTVAL (RTX))) \ | |
1813 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1814 | else if (OUTER_CODE == AND \ | |
1815 | && const_ok_for_arm (~INTVAL (RTX))) \ | |
1816 | return -1; \ | |
1817 | else if ((OUTER_CODE == COMPARE \ | |
1818 | || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ | |
1819 | && const_ok_for_arm (-INTVAL (RTX))) \ | |
1820 | return -1; \ | |
1821 | else \ | |
1822 | return 5; \ | |
1823 | case CONST: \ | |
1824 | case LABEL_REF: \ | |
1825 | case SYMBOL_REF: \ | |
1826 | return 6; \ | |
1827 | case CONST_DOUBLE: \ | |
1828 | if (const_double_rtx_ok_for_fpu (RTX)) \ | |
1829 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1830 | else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ | |
1831 | && neg_const_double_rtx_ok_for_fpu (RTX)) \ | |
1832 | return -1; \ | |
1833 | return(7); | |
1834 | ||
3967692c RE |
1835 | #define ARM_FRAME_RTX(X) \ |
1836 | ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
1837 | || (X) == arg_pointer_rtx) | |
1838 | ||
62b10bbc | 1839 | #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ |
6cfc7210 | 1840 | return arm_rtx_costs (X, CODE); |
ff9940b0 RE |
1841 | |
1842 | /* Moves to and from memory are quite expensive */ | |
cbd5b9a2 | 1843 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10 |
ff9940b0 | 1844 | |
3967692c | 1845 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 1846 | the same for practically all of them. So we weight the different types |
3967692c RE |
1847 | of address here in the order (most pref first): |
1848 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
1849 | #define ADDRESS_COST(X) \ | |
1850 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ | |
1851 | || GET_CODE (X) == SYMBOL_REF) \ | |
1852 | ? 0 \ | |
1853 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
1854 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
1855 | ? 10 \ | |
1856 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
1857 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
1858 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
1859 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
1860 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
1861 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
1862 | ? 1 : 0)) \ | |
1863 | : 4))))) | |
ff9940b0 RE |
1864 | |
1865 | /* Try to generate sequences that don't involve branches, we can then use | |
1866 | conditional instructions */ | |
1867 | #define BRANCH_COST 4 | |
7a801826 RE |
1868 | |
1869 | /* A C statement to update the variable COST based on the relationship | |
1870 | between INSN that is dependent on DEP through dependence LINK. */ | |
6cfc7210 NC |
1871 | #define ADJUST_COST(INSN, LINK, DEP, COST) \ |
1872 | (COST) = arm_adjust_cost (INSN, LINK, DEP, COST) | |
7a801826 RE |
1873 | \f |
1874 | /* Position Independent Code. */ | |
1875 | /* We decide which register to use based on the compilation options and | |
1876 | the assembler in use; this is more general than the APCS restriction of | |
1877 | using sb (r9) all the time. */ | |
1878 | extern int arm_pic_register; | |
1879 | ||
ed0e6530 PB |
1880 | /* Used when parsing command line option -mpic-register=. */ |
1881 | extern const char * arm_pic_register_string; | |
1882 | ||
7a801826 RE |
1883 | /* The register number of the register used to address a table of static |
1884 | data addresses in memory. */ | |
1885 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
1886 | ||
1887 | #define FINALIZE_PIC arm_finalize_pic () | |
1888 | ||
f5a1b0d2 NC |
1889 | /* We can't directly access anything that contains a symbol, |
1890 | nor can we indirect via the constant pool. */ | |
82e9d970 PB |
1891 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1892 | ( ! symbol_mentioned_p (X) \ | |
1893 | && ! label_mentioned_p (X) \ | |
1894 | && (! CONSTANT_POOL_ADDRESS_P (X) \ | |
1895 | || ( ! symbol_mentioned_p (get_pool_constant (X))) \ | |
1896 | && ! label_mentioned_p (get_pool_constant (X)))) | |
13bd191d PB |
1897 | |
1898 | /* We need to know when we are making a constant pool; this determines | |
1899 | whether data needs to be in the GOT or can be referenced via a GOT | |
1900 | offset. */ | |
1901 | extern int making_const_table; | |
82e9d970 PB |
1902 | \f |
1903 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
1904 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
1905 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
1906 | #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ | |
1907 | (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) | |
1908 | ||
1909 | /* If defined, a C expression whose value is zero if the attributes on | |
1910 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
1911 | two if they are nearly compatible (which causes a warning to be | |
1912 | generated). */ | |
1913 | #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ | |
1914 | (arm_comp_type_attributes (TYPE1, TYPE2)) | |
35d965d5 | 1915 | \f |
ff9940b0 RE |
1916 | /* Condition code information. */ |
1917 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
1918 | return the mode to be used for the comparison. | |
ddd5a7c1 | 1919 | CCFPEmode should be used with floating inequalities, |
ff9940b0 | 1920 | CCFPmode should be used with floating equalities. |
ddd5a7c1 | 1921 | CC_NOOVmode should be used with SImode integer equalities. |
69fcc21d | 1922 | CC_Zmode should be used if only the Z flag is set correctly |
ff9940b0 RE |
1923 | CCmode should be used otherwise. */ |
1924 | ||
aa0b4465 ZW |
1925 | #define EXTRA_CC_MODES \ |
1926 | CC(CC_NOOVmode, "CC_NOOV") \ | |
1927 | CC(CC_Zmode, "CC_Z") \ | |
1928 | CC(CC_SWPmode, "CC_SWP") \ | |
1929 | CC(CCFPmode, "CCFP") \ | |
1930 | CC(CCFPEmode, "CCFPE") \ | |
1931 | CC(CC_DNEmode, "CC_DNE") \ | |
1932 | CC(CC_DEQmode, "CC_DEQ") \ | |
1933 | CC(CC_DLEmode, "CC_DLE") \ | |
1934 | CC(CC_DLTmode, "CC_DLT") \ | |
1935 | CC(CC_DGEmode, "CC_DGE") \ | |
1936 | CC(CC_DGTmode, "CC_DGT") \ | |
1937 | CC(CC_DLEUmode, "CC_DLEU") \ | |
1938 | CC(CC_DLTUmode, "CC_DLTU") \ | |
1939 | CC(CC_DGEUmode, "CC_DGEU") \ | |
1940 | CC(CC_DGTUmode, "CC_DGTU") \ | |
1941 | CC(CC_Cmode, "CC_C") | |
89c7ca52 | 1942 | |
89c7ca52 | 1943 | #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y)) |
ff9940b0 | 1944 | |
008cf58a RE |
1945 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
1946 | ||
62b10bbc NC |
1947 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
1948 | do \ | |
1949 | { \ | |
1950 | if (GET_CODE (OP1) == CONST_INT \ | |
1951 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
1952 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
1953 | { \ | |
1954 | rtx const_op = OP1; \ | |
1955 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
1956 | OP1 = const_op; \ | |
1957 | } \ | |
1958 | } \ | |
1959 | while (0) | |
62dd06ea | 1960 | |
ff9940b0 RE |
1961 | #define STORE_FLAG_VALUE 1 |
1962 | ||
1963 | /* Define the information needed to generate branch insns. This is | |
1964 | stored from the compare operation. Note that we can't use "rtx" here | |
1965 | since it hasn't been defined! */ | |
1966 | ||
62b10bbc NC |
1967 | extern struct rtx_def * arm_compare_op0; |
1968 | extern struct rtx_def * arm_compare_op1; | |
ff9940b0 RE |
1969 | |
1970 | /* Define the codes that are matched by predicates in arm.c */ | |
1971 | #define PREDICATE_CODES \ | |
1972 | {"s_register_operand", {SUBREG, REG}}, \ | |
71791e16 | 1973 | {"f_register_operand", {SUBREG, REG}}, \ |
ff9940b0 RE |
1974 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ |
1975 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1976 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
1977 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1978 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
69fcc21d | 1979 | {"offsettable_memory_operand", {MEM}}, \ |
4d818c85 | 1980 | {"bad_signed_byte_operand", {MEM}}, \ |
69fcc21d | 1981 | {"alignable_memory_operand", {MEM}}, \ |
ff9940b0 RE |
1982 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ |
1983 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
3967692c | 1984 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ |
ff9940b0 | 1985 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ |
c383667d | 1986 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ |
ff9940b0 RE |
1987 | {"load_multiple_operation", {PARALLEL}}, \ |
1988 | {"store_multiple_operation", {PARALLEL}}, \ | |
1989 | {"equality_operator", {EQ, NE}}, \ | |
1990 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ | |
1991 | {"const_shift_operand", {CONST_INT}}, \ | |
1992 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
3967692c RE |
1993 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ |
1994 | {"multi_register_push", {PARALLEL}}, \ | |
31e6408a | 1995 | {"cc_register", {REG}}, \ |
6ab589e0 | 1996 | {"logical_binary_operator", {AND, IOR, XOR}}, \ |
89c7ca52 | 1997 | {"dominant_cc_register", {REG}}, |
ff9940b0 | 1998 | |
35d965d5 | 1999 | \f |
35d965d5 | 2000 | |
11c1a207 RE |
2001 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
2002 | load addresses a limited distance around the pc. We do some | |
2003 | special munging to move the constant pool values to the correct | |
2004 | point in the code. */ | |
2005 | #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN)) | |
35d965d5 | 2006 | |
35d965d5 | 2007 | /* Output an internal label definition. */ |
b355a481 | 2008 | #ifndef ASM_OUTPUT_INTERNAL_LABEL |
62b10bbc NC |
2009 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ |
2010 | do \ | |
2011 | { \ | |
2a5307b1 | 2012 | char * s = (char *) alloca (40 + strlen (PREFIX)); \ |
62b10bbc NC |
2013 | \ |
2014 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ | |
2015 | && !strcmp (PREFIX, "L")) \ | |
18543a22 | 2016 | { \ |
62b10bbc | 2017 | arm_ccfsm_state = 0; \ |
18543a22 ILT |
2018 | arm_target_insn = NULL; \ |
2019 | } \ | |
62b10bbc NC |
2020 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
2021 | ASM_OUTPUT_LABEL (STREAM, s); \ | |
2022 | } \ | |
2023 | while (0) | |
b355a481 | 2024 | #endif |
2a5307b1 | 2025 | |
35d965d5 | 2026 | /* Output a push or a pop instruction (only used when profiling). */ |
6cfc7210 | 2027 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
dd18ae56 | 2028 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO) |
6cfc7210 NC |
2029 | |
2030 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
dd18ae56 | 2031 | asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO) |
35d965d5 | 2032 | |
6cfc7210 NC |
2033 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2034 | do \ | |
2035 | { \ | |
2036 | if (TARGET_POKE_FUNCTION_NAME) \ | |
2037 | arm_poke_function_name (STREAM, NAME); \ | |
2038 | } \ | |
2039 | while (0) | |
35d965d5 | 2040 | |
35d965d5 RS |
2041 | /* Target characters. */ |
2042 | #define TARGET_BELL 007 | |
2043 | #define TARGET_BS 010 | |
2044 | #define TARGET_TAB 011 | |
2045 | #define TARGET_NEWLINE 012 | |
2046 | #define TARGET_VT 013 | |
2047 | #define TARGET_FF 014 | |
2048 | #define TARGET_CR 015 | |
2049 | \f | |
35d965d5 RS |
2050 | /* Only perform branch elimination (by making instructions conditional) if |
2051 | we're optimising. Otherwise it's of no use anyway. */ | |
2052 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
2053 | if (optimize) \ | |
74bbc178 | 2054 | arm_final_prescan_insn (INSN) |
35d965d5 | 2055 | |
7bc7696c RE |
2056 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
2057 | ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') | |
6cfc7210 | 2058 | |
7bc7696c | 2059 | /* Output an operand of an instruction. */ |
35d965d5 | 2060 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2061 | arm_print_operand (STREAM, X, CODE) |
2062 | ||
2063 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
2064 | (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ | |
b39e1240 NC |
2065 | : (((x) & (unsigned HOST_WIDE_INT) 0xffffffffUL) | \ |
2066 | (((x) & (unsigned HOST_WIDE_INT) 0x80000000UL) \ | |
7bc7696c | 2067 | ? ((~ (HOST_WIDE_INT) 0) \ |
b39e1240 | 2068 | & ~ (unsigned HOST_WIDE_INT) 0xffffffffUL) \ |
7bc7696c | 2069 | : 0)))) |
35d965d5 RS |
2070 | |
2071 | /* Output the address of an operand. */ | |
2072 | #define PRINT_OPERAND_ADDRESS(STREAM,X) \ | |
2073 | { \ | |
2074 | int is_minus = GET_CODE (X) == MINUS; \ | |
2075 | \ | |
2076 | if (GET_CODE (X) == REG) \ | |
dd18ae56 | 2077 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ |
35d965d5 RS |
2078 | else if (GET_CODE (X) == PLUS || is_minus) \ |
2079 | { \ | |
2080 | rtx base = XEXP (X, 0); \ | |
2081 | rtx index = XEXP (X, 1); \ | |
dd18ae56 | 2082 | int base_reg; \ |
7bc7696c | 2083 | HOST_WIDE_INT offset = 0; \ |
35d965d5 RS |
2084 | if (GET_CODE (base) != REG) \ |
2085 | { \ | |
2086 | /* Ensure that BASE is a register (one of them must be). */ \ | |
2087 | rtx temp = base; \ | |
2088 | base = index; \ | |
2089 | index = temp; \ | |
2090 | } \ | |
dd18ae56 | 2091 | base_reg = REGNO (base); \ |
35d965d5 RS |
2092 | switch (GET_CODE (index)) \ |
2093 | { \ | |
2094 | case CONST_INT: \ | |
2095 | offset = INTVAL (index); \ | |
2096 | if (is_minus) \ | |
2097 | offset = -offset; \ | |
dd18ae56 | 2098 | asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \ |
35d965d5 RS |
2099 | break; \ |
2100 | \ | |
2101 | case REG: \ | |
dd18ae56 NC |
2102 | asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \ |
2103 | is_minus ? "-" : "", REGNO (index)); \ | |
35d965d5 RS |
2104 | break; \ |
2105 | \ | |
2106 | case MULT: \ | |
ff9940b0 RE |
2107 | case ASHIFTRT: \ |
2108 | case LSHIFTRT: \ | |
2109 | case ASHIFT: \ | |
ff9940b0 RE |
2110 | case ROTATERT: \ |
2111 | { \ | |
dd18ae56 NC |
2112 | asm_fprintf (STREAM, "[%r, %s%r", base_reg, \ |
2113 | is_minus ? "-" : "", REGNO (XEXP (index, 0))); \ | |
7bc7696c RE |
2114 | arm_print_operand (STREAM, index, 'S'); \ |
2115 | fputs ("]", STREAM); \ | |
ff9940b0 RE |
2116 | break; \ |
2117 | } \ | |
35d965d5 RS |
2118 | \ |
2119 | default: \ | |
2120 | abort(); \ | |
2121 | } \ | |
2122 | } \ | |
2123 | else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ | |
2124 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ | |
2125 | { \ | |
2126 | extern int output_memory_reference_mode; \ | |
2127 | \ | |
2128 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2129 | abort (); \ | |
2130 | \ | |
2131 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
dd18ae56 NC |
2132 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ |
2133 | REGNO (XEXP (X, 0)), \ | |
6cfc7210 NC |
2134 | GET_CODE (X) == PRE_DEC ? "-" : "", \ |
2135 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
35d965d5 | 2136 | else \ |
dd18ae56 NC |
2137 | asm_fprintf (STREAM, "[%r], #%s%d", \ |
2138 | REGNO (XEXP (X, 0)), \ | |
6cfc7210 NC |
2139 | GET_CODE (X) == POST_DEC ? "-" : "", \ |
2140 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
35d965d5 | 2141 | } \ |
13bd191d | 2142 | else output_addr_const (STREAM, X); \ |
35d965d5 | 2143 | } |
62dd06ea | 2144 | |
7a801826 | 2145 | /* Handles PIC addr specially */ |
13bd191d | 2146 | #define OUTPUT_INT_ADDR_CONST(STREAM,X) \ |
7a801826 | 2147 | { \ |
13bd191d | 2148 | if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \ |
7a801826 | 2149 | { \ |
13bd191d PB |
2150 | output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \ |
2151 | fputs (" - (", STREAM); \ | |
2152 | output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \ | |
2153 | fputs (")", STREAM); \ | |
7a801826 | 2154 | } \ |
13bd191d | 2155 | else output_addr_const (STREAM, X); \ |
687f77a1 NC |
2156 | \ |
2157 | /* Mark symbols as position independent. We only do this in the \ | |
2158 | .text segment, not in the .data segment. */ \ | |
ed0e6530 | 2159 | if (NEED_GOT_RELOC && flag_pic && making_const_table && \ |
687f77a1 NC |
2160 | (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \ |
2161 | { \ | |
2162 | if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \ | |
2163 | fprintf (STREAM, "(GOTOFF)"); \ | |
2164 | else if (GET_CODE (X) == LABEL_REF) \ | |
2165 | fprintf (STREAM, "(GOTOFF)"); \ | |
2166 | else \ | |
2167 | fprintf (STREAM, "(GOT)"); \ | |
2168 | } \ | |
7a801826 RE |
2169 | } |
2170 | ||
62dd06ea RE |
2171 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2172 | Used for C++ multiple inheritance. */ | |
62b10bbc NC |
2173 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2174 | do \ | |
2175 | { \ | |
2176 | int mi_delta = (DELTA); \ | |
2177 | char * mi_op = mi_delta < 0 ? "sub" : "add"; \ | |
2178 | int shift = 0; \ | |
2179 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ | |
2180 | ? 1 : 0); \ | |
2181 | if (mi_delta < 0) mi_delta = -mi_delta; \ | |
2182 | while (mi_delta != 0) \ | |
2183 | { \ | |
2184 | if (mi_delta & (3 << shift) == 0) \ | |
2185 | shift += 2; \ | |
2186 | else \ | |
2187 | { \ | |
dd18ae56 NC |
2188 | asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \ |
2189 | mi_op, this_regno, this_regno, \ | |
6cfc7210 | 2190 | mi_delta & (0xff << shift)); \ |
62b10bbc NC |
2191 | mi_delta &= ~(0xff << shift); \ |
2192 | shift += 8; \ | |
2193 | } \ | |
2194 | } \ | |
2195 | fputs ("\tb\t", FILE); \ | |
2196 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
dd18ae56 | 2197 | if (NEED_PLT_RELOC) \ |
62b10bbc NC |
2198 | fputs ("(PLT)", FILE); \ |
2199 | fputc ('\n', FILE); \ | |
2200 | } \ | |
2201 | while (0) | |
39950dff | 2202 | |
6a5d7526 MS |
2203 | /* A C expression whose value is RTL representing the value of the return |
2204 | address for the frame COUNT steps up from the current frame. */ | |
2205 | ||
2206 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
2207 | ((COUNT == 0) \ | |
43cffd11 | 2208 | ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \ |
18543a22 | 2209 | : NULL_RTX) |
6a5d7526 | 2210 | |
39950dff MS |
2211 | /* Used to mask out junk bits from the return address, such as |
2212 | processor state, interrupt status, condition codes and the like. */ | |
2213 | #define MASK_RETURN_ADDR \ | |
2214 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2215 | in 26 bit mode, the condition codes must be masked out of the \ | |
2216 | return address. This does not apply to ARM6 and later processors \ | |
2217 | when running in 32 bit mode. */ \ | |
7a801826 | 2218 | ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff))) |
71791e16 | 2219 | |
b355a481 | 2220 | #endif /* __ARM_H__ */ |