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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
16c484c7 | 3 | 2001, 2002 Free Software Foundation, Inc. |
35d965d5 | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 5 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
7 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
8 | ||
35d965d5 RS |
9 | This file is part of GNU CC. |
10 | ||
11 | GNU CC is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GNU CC is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, |
24 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 25 | |
88657302 RH |
26 | #ifndef GCC_ARM_H |
27 | #define GCC_ARM_H | |
b355a481 | 28 | |
e6471be6 NB |
29 | /* Target CPU builtins. */ |
30 | #define TARGET_CPU_CPP_BUILTINS() \ | |
31 | do \ | |
32 | { \ | |
48f6efae | 33 | if (TARGET_ARM) \ |
e6471be6 NB |
34 | builtin_define ("__arm__"); \ |
35 | else \ | |
36 | builtin_define ("__thumb__"); \ | |
37 | \ | |
38 | if (TARGET_BIG_END) \ | |
39 | { \ | |
40 | builtin_define ("__ARMEB__"); \ | |
41 | if (TARGET_THUMB) \ | |
42 | builtin_define ("__THUMBEB__"); \ | |
43 | if (TARGET_LITTLE_WORDS) \ | |
44 | builtin_define ("__ARMWEL__"); \ | |
45 | } \ | |
46 | else \ | |
47 | { \ | |
48 | builtin_define ("__ARMEL__"); \ | |
49 | if (TARGET_THUMB) \ | |
50 | builtin_define ("__THUMBEL__"); \ | |
51 | } \ | |
52 | \ | |
53 | if (TARGET_APCS_32) \ | |
54 | builtin_define ("__APCS_32__"); \ | |
55 | else \ | |
56 | builtin_define ("__APCS_26__"); \ | |
57 | \ | |
58 | if (TARGET_SOFT_FLOAT) \ | |
59 | builtin_define ("__SOFTFP__"); \ | |
60 | \ | |
b5b620a4 JT |
61 | /* FIXME: TARGET_HARD_FLOAT currently implies \ |
62 | FPA. */ \ | |
63 | if (TARGET_VFP && !TARGET_HARD_FLOAT) \ | |
64 | builtin_define ("__VFP_FP__"); \ | |
65 | \ | |
e6471be6 NB |
66 | /* Add a define for interworking. \ |
67 | Needed when building libgcc.a. */ \ | |
68 | if (TARGET_INTERWORK) \ | |
69 | builtin_define ("__THUMB_INTERWORK__"); \ | |
70 | \ | |
71 | builtin_assert ("cpu=arm"); \ | |
72 | builtin_assert ("machine=arm"); \ | |
73 | } while (0) | |
74 | ||
7a801826 RE |
75 | #define TARGET_CPU_arm2 0x0000 |
76 | #define TARGET_CPU_arm250 0x0000 | |
77 | #define TARGET_CPU_arm3 0x0000 | |
78 | #define TARGET_CPU_arm6 0x0001 | |
79 | #define TARGET_CPU_arm600 0x0001 | |
80 | #define TARGET_CPU_arm610 0x0002 | |
81 | #define TARGET_CPU_arm7 0x0001 | |
82 | #define TARGET_CPU_arm7m 0x0004 | |
83 | #define TARGET_CPU_arm7dm 0x0004 | |
84 | #define TARGET_CPU_arm7dmi 0x0004 | |
85 | #define TARGET_CPU_arm700 0x0001 | |
86 | #define TARGET_CPU_arm710 0x0002 | |
87 | #define TARGET_CPU_arm7100 0x0002 | |
88 | #define TARGET_CPU_arm7500 0x0002 | |
89 | #define TARGET_CPU_arm7500fe 0x1001 | |
90 | #define TARGET_CPU_arm7tdmi 0x0008 | |
91 | #define TARGET_CPU_arm8 0x0010 | |
92 | #define TARGET_CPU_arm810 0x0020 | |
93 | #define TARGET_CPU_strongarm 0x0040 | |
94 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 95 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
96 | #define TARGET_CPU_arm9 0x0080 |
97 | #define TARGET_CPU_arm9tdmi 0x0080 | |
d19fb8e3 | 98 | #define TARGET_CPU_xscale 0x0100 |
82e9d970 | 99 | /* Configure didn't specify. */ |
7a801826 | 100 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 101 | |
d5b7b3ae | 102 | typedef enum arm_cond_code |
89c7ca52 RE |
103 | { |
104 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
105 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
106 | } |
107 | arm_cc; | |
6cfc7210 | 108 | |
d5b7b3ae | 109 | extern arm_cc arm_current_cc; |
ff9940b0 | 110 | |
d5b7b3ae | 111 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 112 | |
6cfc7210 NC |
113 | extern int arm_target_label; |
114 | extern int arm_ccfsm_state; | |
e2500fed | 115 | extern GTY(()) rtx arm_target_insn; |
6cfc7210 NC |
116 | /* Run-time compilation parameters selecting different hardware subsets. */ |
117 | extern int target_flags; | |
118 | /* The floating point instruction architecture, can be 2 or 3 */ | |
119 | extern const char * target_fp_name; | |
d5b7b3ae | 120 | /* Define the information needed to generate branch insns. This is |
e2500fed GK |
121 | stored from the compare operation. */ |
122 | extern GTY(()) rtx arm_compare_op0; | |
123 | extern GTY(()) rtx arm_compare_op1; | |
d5b7b3ae | 124 | /* The label of the current constant pool. */ |
e2500fed | 125 | extern rtx pool_vector_label; |
d5b7b3ae RE |
126 | /* Set to 1 when a return insn is output, this means that the epilogue |
127 | is not needed. */ | |
128 | extern int return_used_this_function; | |
e2500fed GK |
129 | /* Used to produce AOF syntax assembler. */ |
130 | extern GTY(()) rtx aof_pic_label; | |
35d965d5 | 131 | \f |
7a801826 RE |
132 | /* Just in case configure has failed to define anything. */ |
133 | #ifndef TARGET_CPU_DEFAULT | |
134 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
135 | #endif | |
136 | ||
137 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
70f24e49 | 138 | override it. If it doesn't, then default to an ARM6. */ |
7a801826 RE |
139 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic |
140 | #undef TARGET_CPU_DEFAULT | |
70f24e49 | 141 | |
7a801826 RE |
142 | #ifdef SUBTARGET_CPU_DEFAULT |
143 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
144 | #else | |
145 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
146 | #endif | |
147 | #endif | |
148 | ||
149 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
150 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
151 | #else | |
18543a22 | 152 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
153 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
154 | #else | |
155 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
156 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
157 | #else | |
70f24e49 | 158 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi |
7a801826 RE |
159 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
160 | #else | |
dc60a41b | 161 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 |
7a801826 RE |
162 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" |
163 | #else | |
d19fb8e3 NC |
164 | #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale |
165 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" | |
166 | #else | |
7a801826 RE |
167 | Unrecognized value in TARGET_CPU_DEFAULT. |
168 | #endif | |
169 | #endif | |
170 | #endif | |
171 | #endif | |
172 | #endif | |
d19fb8e3 | 173 | #endif |
7a801826 | 174 | |
5742588d | 175 | #undef CPP_SPEC |
e6471be6 NB |
176 | #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ |
177 | %{mapcs-32:%{mapcs-26: \ | |
178 | %e-mapcs-26 and -mapcs-32 may not be used together}} \ | |
179 | %{msoft-float:%{mhard-float: \ | |
180 | %e-msoft-float and -mhard_float may not be used together}} \ | |
181 | %{mbig-endian:%{mlittle-endian: \ | |
182 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 183 | |
71791e16 RE |
184 | /* Set the architecture define -- if -march= is set, then it overrides |
185 | the -mcpu= setting. */ | |
7a801826 | 186 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
187 | %{march=arm2:-D__ARM_ARCH_2__} \ |
188 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
189 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
190 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
191 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
192 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
193 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
194 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
195 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 196 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
197 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
198 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
199 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
200 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
201 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
202 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
203 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
204 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
205 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 206 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
207 | %{march=arm920:-D__ARM_ARCH_4__} \ |
208 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 209 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
210 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
211 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 212 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
213 | %{march=xscale:-D__ARM_ARCH_5TE__} \ |
214 | %{march=xscale:-D__XSCALE__} \ | |
71791e16 RE |
215 | %{march=armv2:-D__ARM_ARCH_2__} \ |
216 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
217 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
218 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
219 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
220 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 221 | %{march=armv5:-D__ARM_ARCH_5__} \ |
d5b7b3ae RE |
222 | %{march=armv5t:-D__ARM_ARCH_5T__} \ |
223 | %{march=armv5e:-D__ARM_ARCH_5E__} \ | |
224 | %{march=armv5te:-D__ARM_ARCH_5TE__} \ | |
71791e16 RE |
225 | %{!march=*: \ |
226 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
227 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
228 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
229 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
230 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
231 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
232 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
233 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
234 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 235 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
236 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
237 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
238 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
239 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
240 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
241 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
242 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
243 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
244 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 245 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
246 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
247 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 248 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
249 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
250 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 251 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
252 | %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ |
253 | %{mcpu=xscale:-D__XSCALE__} \ | |
dfa08768 | 254 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 255 | " |
7a801826 | 256 | |
be393ecf | 257 | #ifndef CC1_SPEC |
dfa08768 | 258 | #define CC1_SPEC "" |
be393ecf | 259 | #endif |
7a801826 RE |
260 | |
261 | /* This macro defines names of additional specifications to put in the specs | |
262 | that can be used in various specifications like CC1_SPEC. Its definition | |
263 | is an initializer with a subgrouping for each command option. | |
264 | ||
265 | Each subgrouping contains a string constant, that defines the | |
266 | specification name, and a string constant that used by the GNU CC driver | |
267 | program. | |
268 | ||
269 | Do not define this macro if it does not need to do anything. */ | |
270 | #define EXTRA_SPECS \ | |
271 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
272 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
38fc909b | 273 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
274 | SUBTARGET_EXTRA_SPECS |
275 | ||
914a3b8c | 276 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 277 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
278 | #endif |
279 | ||
6cfc7210 | 280 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 281 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 282 | #endif |
35d965d5 RS |
283 | \f |
284 | /* Run-time Target Specification. */ | |
ff9940b0 | 285 | #ifndef TARGET_VERSION |
6cfc7210 | 286 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 287 | #endif |
35d965d5 | 288 | |
35d965d5 RS |
289 | /* Nonzero if the function prologue (and epilogue) should obey |
290 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 291 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
292 | |
293 | /* Nonzero if the function prologue should output the function name to enable | |
294 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
295 | unused on RISCiX). Specifying this flag also enables |
296 | -fno-omit-frame-pointer. | |
35d965d5 | 297 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 298 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
299 | |
300 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
301 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 302 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 303 | |
11c1a207 RE |
304 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
305 | that assume restoration of the condition flags when returning from a | |
306 | branch and link (ie a function). */ | |
6cfc7210 | 307 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 308 | |
dfa08768 RE |
309 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
310 | ||
11c1a207 RE |
311 | /* Nonzero if stack checking should be performed on entry to each function |
312 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 313 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
314 | |
315 | /* Nonzero if floating point parameters should be passed to functions in | |
316 | floating point registers. */ | |
6cfc7210 | 317 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
318 | |
319 | /* Nonzero if re-entrant, position independent code should be generated. | |
320 | This is equivalent to -fpic. */ | |
6cfc7210 | 321 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 322 | |
5f1e6755 NC |
323 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
324 | be loaded using either LDRH or LDRB instructions. */ | |
325 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
326 | |
327 | /* Nonzero if all floating point instructions are missing (and there is no | |
328 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 329 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
330 | |
331 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 332 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
333 | |
334 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 335 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 336 | |
ddee6aba RE |
337 | /* Nonzero if we should have little-endian words even when compiling for |
338 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 339 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 340 | |
f5a1b0d2 | 341 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 342 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 343 | |
c11145f6 | 344 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 345 | function tries to return. */ |
6cfc7210 | 346 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 347 | |
ed0e6530 | 348 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 349 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 350 | |
b020fd92 NC |
351 | /* Nonzero if all call instructions should be indirect. */ |
352 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
d5b7b3ae RE |
353 | |
354 | /* Nonzero means that the target ISA is the THUMB, not the ARM. */ | |
355 | #define ARM_FLAG_THUMB (1 << 16) | |
356 | ||
357 | /* Set if a TPCS style stack frame should be generated, for non-leaf | |
358 | functions, even if they do not need one. */ | |
359 | #define THUMB_FLAG_BACKTRACE (1 << 17) | |
b020fd92 | 360 | |
d5b7b3ae RE |
361 | /* Set if a TPCS style stack frame should be generated, for leaf |
362 | functions, even if they do not need one. */ | |
363 | #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) | |
364 | ||
365 | /* Set if externally visible functions should assume that they | |
366 | might be called in ARM mode, from a non-thumb aware code. */ | |
367 | #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) | |
368 | ||
369 | /* Set if calls via function pointers should assume that their | |
370 | destination is non-Thumb aware. */ | |
371 | #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) | |
372 | ||
b5b620a4 JT |
373 | /* Nonzero means target uses VFP FP. */ |
374 | #define ARM_FLAG_VFP (1 << 21) | |
375 | ||
dc0ba55a JT |
376 | /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ |
377 | #define ARM_FLAG_ATPCS (1 << 22) | |
378 | ||
d5b7b3ae | 379 | #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) |
11c1a207 RE |
380 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) |
381 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
382 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
383 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
384 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
385 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
dc0ba55a | 386 | #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS) |
5f1e6755 | 387 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
388 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
389 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
b5b620a4 | 390 | #define TARGET_VFP (target_flags & ARM_FLAG_VFP) |
11c1a207 | 391 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) |
6cfc7210 | 392 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 393 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 394 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 395 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 396 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 397 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
d5b7b3ae RE |
398 | #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) |
399 | #define TARGET_ARM (! TARGET_THUMB) | |
400 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
401 | #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) | |
402 | #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) | |
403 | #define TARGET_BACKTRACE (leaf_function_p () \ | |
404 | ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ | |
405 | : (target_flags & THUMB_FLAG_BACKTRACE)) | |
3ada8e17 | 406 | |
c7bdf0a6 | 407 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ |
3ada8e17 DE |
408 | #ifndef SUBTARGET_SWITCHES |
409 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
410 | #endif |
411 | ||
047142d3 PT |
412 | #define TARGET_SWITCHES \ |
413 | { \ | |
414 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
415 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
416 | N_("Generate APCS conformant stack frames") }, \ | |
417 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
418 | {"poke-function-name", ARM_FLAG_POKE, \ | |
419 | N_("Store function names in object code") }, \ | |
420 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
421 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
422 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
b605cfa8 | 423 | N_("Use the 32-bit version of the APCS") }, \ |
047142d3 | 424 | {"apcs-26", -ARM_FLAG_APCS_32, \ |
b605cfa8 | 425 | N_("Use the 26-bit version of the APCS") }, \ |
047142d3 PT |
426 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ |
427 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
428 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
429 | N_("Pass FP arguments in FP registers") }, \ | |
430 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
431 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
432 | N_("Generate re-entrant, PIC code") }, \ | |
433 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
434 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ | |
435 | N_("The MMU will trap on unaligned accesses") }, \ | |
436 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
437 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
438 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
439 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
440 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
441 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ | |
442 | N_("Use library calls to perform FP operations") }, \ | |
443 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
444 | N_("Use hardware floating point instructions") }, \ | |
445 | {"big-endian", ARM_FLAG_BIG_END, \ | |
446 | N_("Assume target CPU is configured as big endian") }, \ | |
447 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
448 | N_("Assume target CPU is configured as little endian") }, \ | |
449 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
450 | N_("Assume big endian bytes, little endian words") }, \ | |
451 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
b605cfa8 | 452 | N_("Support calls between Thumb and ARM instruction sets") }, \ |
047142d3 PT |
453 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ |
454 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
455 | N_("Generate a call to abort if a noreturn function returns")}, \ | |
456 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ | |
b605cfa8 | 457 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ |
047142d3 | 458 | N_("Do not move instructions into a function's prologue") }, \ |
b605cfa8 | 459 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ |
047142d3 PT |
460 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ |
461 | N_("Do not load the PIC register in function prologues") }, \ | |
462 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ | |
463 | {"long-calls", ARM_FLAG_LONG_CALLS, \ | |
464 | N_("Generate call insns as indirect calls, if necessary") }, \ | |
465 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ | |
466 | {"thumb", ARM_FLAG_THUMB, \ | |
467 | N_("Compile for the Thumb not the ARM") }, \ | |
468 | {"no-thumb", -ARM_FLAG_THUMB, "" }, \ | |
469 | {"arm", -ARM_FLAG_THUMB, "" }, \ | |
470 | {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ | |
471 | N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ | |
472 | {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ | |
473 | {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ | |
474 | N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ | |
475 | {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ | |
476 | {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
477 | N_("Thumb: Assume non-static functions may be called from ARM code") }, \ | |
478 | {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
479 | "" }, \ | |
480 | {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
481 | N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ | |
482 | {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
483 | "" }, \ | |
484 | SUBTARGET_SWITCHES \ | |
485 | {"", TARGET_DEFAULT, "" } \ | |
35d965d5 RS |
486 | } |
487 | ||
43cffd11 RE |
488 | #define TARGET_OPTIONS \ |
489 | { \ | |
f5a1b0d2 | 490 | {"cpu=", & arm_select[0].string, \ |
047142d3 | 491 | N_("Specify the name of the target CPU") }, \ |
f5a1b0d2 | 492 | {"arch=", & arm_select[1].string, \ |
047142d3 | 493 | N_("Specify the name of the target architecture") }, \ |
f5a1b0d2 NC |
494 | {"tune=", & arm_select[2].string, "" }, \ |
495 | {"fpe=", & target_fp_name, "" }, \ | |
496 | {"fp=", & target_fp_name, \ | |
047142d3 PT |
497 | N_("Specify the version of the floating point emulator") }, \ |
498 | {"structure-size-boundary=", & structure_size_string, \ | |
499 | N_("Specify the minimum bit alignment of structures") }, \ | |
500 | {"pic-register=", & arm_pic_register_string, \ | |
501 | N_("Specify the register to be used for PIC addressing") } \ | |
11c1a207 | 502 | } |
ff9940b0 | 503 | |
62dd06ea RE |
504 | struct arm_cpu_select |
505 | { | |
f9cc092a RE |
506 | const char * string; |
507 | const char * name; | |
508 | const struct processors * processors; | |
62dd06ea RE |
509 | }; |
510 | ||
f5a1b0d2 NC |
511 | /* This is a magic array. If the user specifies a command line switch |
512 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
513 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
514 | extern struct arm_cpu_select arm_select[]; |
515 | ||
11c1a207 RE |
516 | enum prog_mode_type |
517 | { | |
518 | prog_mode26, | |
519 | prog_mode32 | |
520 | }; | |
521 | ||
522 | /* Recast the program mode class to be the prog_mode attribute */ | |
523 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
524 | ||
525 | extern enum prog_mode_type arm_prgmode; | |
526 | ||
527 | /* What sort of floating point unit do we have? Hardware or software. | |
528 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
529 | enum floating_point_type |
530 | { | |
531 | FP_HARD, | |
11c1a207 RE |
532 | FP_SOFT2, |
533 | FP_SOFT3 | |
24f0c1b4 RE |
534 | }; |
535 | ||
536 | /* Recast the floating point class to be the floating point attribute. */ | |
537 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
538 | ||
71791e16 | 539 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
540 | extern enum floating_point_type arm_fpu; |
541 | ||
71791e16 RE |
542 | /* What type of floating point instructions are available */ |
543 | extern enum floating_point_type arm_fpu_arch; | |
544 | ||
18543a22 | 545 | /* Default floating point architecture. Override in sub-target if |
71791e16 | 546 | necessary. */ |
be393ecf | 547 | #ifndef FP_DEFAULT |
71791e16 | 548 | #define FP_DEFAULT FP_SOFT2 |
be393ecf | 549 | #endif |
71791e16 | 550 | |
11c1a207 RE |
551 | /* Nonzero if the processor has a fast multiply insn, and one that does |
552 | a 64-bit multiply of two 32-bit values. */ | |
553 | extern int arm_fast_multiply; | |
554 | ||
71791e16 | 555 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
556 | extern int arm_arch4; |
557 | ||
62b10bbc NC |
558 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
559 | extern int arm_arch5; | |
560 | ||
b15bca31 RE |
561 | /* Nonzero if this chip supports the ARM Architecture 5E extensions */ |
562 | extern int arm_arch5e; | |
563 | ||
f5a1b0d2 NC |
564 | /* Nonzero if this chip can benefit from load scheduling. */ |
565 | extern int arm_ld_sched; | |
566 | ||
0616531f RE |
567 | /* Nonzero if generating thumb code. */ |
568 | extern int thumb_code; | |
569 | ||
f5a1b0d2 NC |
570 | /* Nonzero if this chip is a StrongARM. */ |
571 | extern int arm_is_strong; | |
572 | ||
d19fb8e3 NC |
573 | /* Nonzero if this chip is an XScale. */ |
574 | extern int arm_is_xscale; | |
575 | ||
3569057d | 576 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 NC |
577 | extern int arm_is_6_or_7; |
578 | ||
2ce9c1b9 | 579 | #ifndef TARGET_DEFAULT |
d5b7b3ae | 580 | #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) |
2ce9c1b9 | 581 | #endif |
35d965d5 | 582 | |
11c1a207 RE |
583 | /* The frame pointer register used in gcc has nothing to do with debugging; |
584 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 585 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 586 | |
be393ecf | 587 | #undef TARGET_MEM_FUNCTIONS |
11c1a207 RE |
588 | #define TARGET_MEM_FUNCTIONS 1 |
589 | ||
590 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
591 | |
592 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
593 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
594 | Subtargets can override these if required. */ |
595 | #ifndef NEED_GOT_RELOC | |
596 | #define NEED_GOT_RELOC 0 | |
597 | #endif | |
598 | #ifndef NEED_PLT_RELOC | |
599 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 600 | #endif |
84306176 PB |
601 | |
602 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
603 | offset. In other words, generate | |
604 | ||
605 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
606 | ||
607 | rather than | |
608 | ||
609 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
610 | ||
611 | The default is true, which matches NetBSD. Subtargets can | |
612 | override this if required. */ | |
613 | #ifndef GOT_PCREL | |
614 | #define GOT_PCREL 1 | |
615 | #endif | |
35d965d5 RS |
616 | \f |
617 | /* Target machine storage Layout. */ | |
618 | ||
ff9940b0 RE |
619 | |
620 | /* Define this macro if it is advisable to hold scalars in registers | |
621 | in a wider mode than that declared by the program. In such cases, | |
622 | the value is constrained to be within the bounds of the declared | |
623 | type, but kept valid in the wider mode. The signedness of the | |
624 | extension may differ from that of the type. */ | |
625 | ||
626 | /* It is far faster to zero extend chars than to sign extend them */ | |
627 | ||
6cfc7210 | 628 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
629 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
630 | && GET_MODE_SIZE (MODE) < 4) \ | |
631 | { \ | |
632 | if (MODE == QImode) \ | |
633 | UNSIGNEDP = 1; \ | |
634 | else if (MODE == HImode) \ | |
5f1e6755 | 635 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 636 | (MODE) = SImode; \ |
ff9940b0 RE |
637 | } |
638 | ||
18543a22 ILT |
639 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
640 | should also be done for outgoing function arguments. */ | |
641 | /* This is required to ensure that push insns always push a word. */ | |
642 | #define PROMOTE_FUNCTION_ARGS | |
643 | ||
ff9940b0 RE |
644 | /* For the ARM: |
645 | I think I have added all the code to make this work. Unfortunately, | |
646 | early releases of the floating point emulation code on RISCiX used a | |
647 | different format for extended precision numbers. On my RISCiX box there | |
648 | is a bug somewhere which causes the machine to lock up when running enquire | |
649 | with long doubles. There is the additional aspect that Norcroft C | |
650 | treats long doubles as doubles and we ought to remain compatible. | |
651 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
652 | to try this someday. */ | |
653 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
654 | ||
655 | /* Disable XFmode patterns in md file */ | |
656 | #define ENABLE_XF_PATTERNS 0 | |
657 | ||
35d965d5 RS |
658 | /* Define this if most significant bit is lowest numbered |
659 | in instructions that operate on numbered bit-fields. */ | |
660 | #define BITS_BIG_ENDIAN 0 | |
661 | ||
9c872872 | 662 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
663 | Most ARM processors are run in little endian mode, so that is the default. |
664 | If you want to have it run-time selectable, change the definition in a | |
665 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 666 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
667 | |
668 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
669 | numbered. |
670 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
671 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
672 | ||
673 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
674 | on processor pre-defineds when compiling libgcc2.c. */ | |
675 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
676 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
677 | #else | |
678 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
679 | #endif | |
35d965d5 | 680 | |
11c1a207 | 681 | /* Define this if most significant word of doubles is the lowest numbered. |
b5b620a4 JT |
682 | The rules are different based on whether or not we use FPA-format or |
683 | VFP-format doubles. */ | |
684 | #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) | |
7fc6c9f0 | 685 | |
35d965d5 RS |
686 | #define UNITS_PER_WORD 4 |
687 | ||
35d965d5 RS |
688 | #define PARM_BOUNDARY 32 |
689 | ||
690 | #define STACK_BOUNDARY 32 | |
691 | ||
692 | #define FUNCTION_BOUNDARY 32 | |
693 | ||
92928d71 AO |
694 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
695 | vbit must go into the delta field of pointers to member | |
696 | functions. */ | |
697 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
698 | ||
35d965d5 RS |
699 | #define EMPTY_FIELD_BOUNDARY 32 |
700 | ||
701 | #define BIGGEST_ALIGNMENT 32 | |
702 | ||
ff9940b0 | 703 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
d19fb8e3 NC |
704 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) |
705 | ||
706 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
707 | ((TREE_CODE (EXP) == STRING_CST \ | |
708 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
709 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 710 | |
723ae7c1 NC |
711 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
712 | value set in previous versions of this toolchain was 8, which produces more | |
713 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 714 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 NC |
715 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
716 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
717 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
718 | extern int arm_structure_size_boundary; | |
723ae7c1 | 719 | |
4912a07c | 720 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 NC |
721 | particular arm target wants to change the default value it should change |
722 | the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h | |
723 | for an example of this. */ | |
724 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
725 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 726 | #endif |
2a5307b1 | 727 | |
b355a481 | 728 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 729 | extern const char * structure_size_string; |
b4ac57ab | 730 | |
ff9940b0 RE |
731 | /* Non-zero if move instructions will actually fail to work |
732 | when given unaligned data. */ | |
35d965d5 RS |
733 | #define STRICT_ALIGNMENT 1 |
734 | ||
ff9940b0 RE |
735 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
736 | ||
35d965d5 RS |
737 | \f |
738 | /* Standard register usage. */ | |
739 | ||
740 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
741 | (S - saved over call). | |
742 | ||
743 | r0 * argument word/integer result | |
744 | r1-r3 argument word | |
745 | ||
746 | r4-r8 S register variable | |
747 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
748 | |
749 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
750 | r11 F S (fp) argument pointer |
751 | r12 (ip) temp workspace | |
752 | r13 F S (sp) lower end of current stack frame | |
753 | r14 (lr) link address/workspace | |
754 | r15 F (pc) program counter | |
755 | ||
756 | f0 floating point result | |
757 | f1-f3 floating point scratch | |
758 | ||
759 | f4-f7 S floating point variable | |
760 | ||
ff9940b0 RE |
761 | cc This is NOT a real register, but is used internally |
762 | to represent things that use or set the condition | |
763 | codes. | |
764 | sfp This isn't either. It is used during rtl generation | |
765 | since the offset between the frame pointer and the | |
766 | auto's isn't known until after register allocation. | |
767 | afp Nor this, we only need this because of non-local | |
768 | goto. Without it fp appears to be used and the | |
769 | elimination code won't get rid of sfp. It tracks | |
770 | fp exactly at all times. | |
771 | ||
35d965d5 RS |
772 | *: See CONDITIONAL_REGISTER_USAGE */ |
773 | ||
ff9940b0 RE |
774 | /* The stack backtrace structure is as follows: |
775 | fp points to here: | save code pointer | [fp] | |
776 | | return link value | [fp, #-4] | |
777 | | return sp value | [fp, #-8] | |
778 | | return fp value | [fp, #-12] | |
779 | [| saved r10 value |] | |
780 | [| saved r9 value |] | |
781 | [| saved r8 value |] | |
782 | [| saved r7 value |] | |
783 | [| saved r6 value |] | |
784 | [| saved r5 value |] | |
785 | [| saved r4 value |] | |
786 | [| saved r3 value |] | |
787 | [| saved r2 value |] | |
788 | [| saved r1 value |] | |
789 | [| saved r0 value |] | |
790 | [| saved f7 value |] three words | |
791 | [| saved f6 value |] three words | |
792 | [| saved f5 value |] three words | |
793 | [| saved f4 value |] three words | |
794 | r0-r3 are not normally saved in a C function. */ | |
795 | ||
35d965d5 RS |
796 | /* 1 for registers that have pervasive standard uses |
797 | and are not available for the register allocator. */ | |
798 | #define FIXED_REGISTERS \ | |
799 | { \ | |
800 | 0,0,0,0,0,0,0,0, \ | |
d5b7b3ae | 801 | 0,0,0,0,0,1,0,1, \ |
ff9940b0 RE |
802 | 0,0,0,0,0,0,0,0, \ |
803 | 1,1,1 \ | |
35d965d5 RS |
804 | } |
805 | ||
806 | /* 1 for registers not available across function calls. | |
807 | These must include the FIXED_REGISTERS and also any | |
808 | registers that can be used without being saved. | |
809 | The latter must include the registers where values are returned | |
810 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
811 | Aside from that, you can include as many other registers as you like. |
812 | The CC is not preserved over function calls on the ARM 6, so it is | |
813 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
814 | #define CALL_USED_REGISTERS \ |
815 | { \ | |
816 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 817 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 RE |
818 | 1,1,1,1,0,0,0,0, \ |
819 | 1,1,1 \ | |
35d965d5 RS |
820 | } |
821 | ||
6cc8c0b3 NC |
822 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
823 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
824 | #endif | |
825 | ||
d5b7b3ae RE |
826 | #define CONDITIONAL_REGISTER_USAGE \ |
827 | { \ | |
4b02997f NC |
828 | int regno; \ |
829 | \ | |
d5b7b3ae RE |
830 | if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ |
831 | { \ | |
d5b7b3ae RE |
832 | for (regno = FIRST_ARM_FP_REGNUM; \ |
833 | regno <= LAST_ARM_FP_REGNUM; ++regno) \ | |
834 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
835 | } \ | |
5b43fed1 | 836 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
d5b7b3ae RE |
837 | { \ |
838 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
839 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
840 | } \ | |
841 | else if (TARGET_APCS_STACK) \ | |
842 | { \ | |
843 | fixed_regs[10] = 1; \ | |
844 | call_used_regs[10] = 1; \ | |
845 | } \ | |
846 | if (TARGET_APCS_FRAME) \ | |
847 | { \ | |
848 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
849 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
850 | } \ | |
851 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 852 | } |
d5b7b3ae | 853 | |
dd18ae56 NC |
854 | /* These are a couple of extensions to the formats accecpted |
855 | by asm_fprintf: | |
856 | %@ prints out ASM_COMMENT_START | |
857 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
858 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
859 | case '@': \ | |
860 | fputs (ASM_COMMENT_START, FILE); \ | |
861 | break; \ | |
862 | \ | |
863 | case 'r': \ | |
864 | fputs (REGISTER_PREFIX, FILE); \ | |
865 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
866 | break; | |
867 | ||
d5b7b3ae RE |
868 | /* Round X up to the nearest word. */ |
869 | #define ROUND_UP(X) (((X) + 3) & ~3) | |
870 | ||
6cfc7210 | 871 | /* Convert fron bytes to ints. */ |
e9d7b180 | 872 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 NC |
873 | |
874 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
e9d7b180 JD |
875 | #define ARM_NUM_REGS(MODE) \ |
876 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
877 | |
878 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
879 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
880 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 881 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
882 | |
883 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 884 | #define NUM_ARG_REGS 4 |
6cfc7210 NC |
885 | |
886 | /* Return the regiser number of the N'th (integer) argument. */ | |
d5b7b3ae | 887 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 888 | |
e04546dc NC |
889 | #if 0 /* FIXME: The ARM backend has special code to handle structure |
890 | returns, and will reserve its own hidden first argument. So | |
891 | if this macro is enabled a *second* hidden argument will be | |
d6a7951f | 892 | reserved, which will break binary compatibility with old |
e04546dc NC |
893 | toolchains and also thunk handling. One day this should be |
894 | fixed. */ | |
64a7723d | 895 | /* RTX for structure returns. NULL means use a hidden first argument. */ |
31448271 | 896 | #define STRUCT_VALUE 0 |
e04546dc NC |
897 | #else |
898 | /* Register in which address to store a structure value | |
899 | is passed to a function. */ | |
900 | #define STRUCT_VALUE_REGNUM ARG_REGISTER (1) | |
901 | #endif | |
6cfc7210 | 902 | |
d5b7b3ae RE |
903 | /* Specify the registers used for certain standard purposes. |
904 | The values of these macros are register numbers. */ | |
35d965d5 | 905 | |
d5b7b3ae RE |
906 | /* The number of the last argument register. */ |
907 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 908 | |
d5b7b3ae | 909 | /* The number of the last "lo" register (thumb). */ |
6d3d9133 NC |
910 | #define LAST_LO_REGNUM 7 |
911 | ||
912 | /* The register that holds the return address in exception handlers. */ | |
913 | #define EXCEPTION_LR_REGNUM 2 | |
35d965d5 | 914 | |
d5b7b3ae RE |
915 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
916 | as an invisible last argument (possible since varargs don't exist in | |
917 | Pascal), so the following is not true. */ | |
68dfd979 | 918 | #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) |
35d965d5 | 919 | |
d5b7b3ae RE |
920 | /* Define this to be where the real frame pointer is if it is not possible to |
921 | work out the offset between the frame pointer and the automatic variables | |
922 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
923 | should point to a special register that we will make sure is eliminated. | |
924 | ||
925 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
926 | as r11, and GCC belives that it is always possible to use the frame pointer | |
927 | as base register for addressing purposes. (See comments in | |
928 | find_reloads_address()). But - the Thumb does not allow high registers, | |
929 | including r11, to be used as base address registers. Hence our problem. | |
930 | ||
931 | The solution used here, and in the old thumb port is to use r7 instead of | |
932 | r11 as the hard frame pointer and to have special code to generate | |
933 | backtrace structures on the stack (if required to do so via a command line | |
934 | option) using r11. This is the only 'user visable' use of r11 as a frame | |
935 | pointer. */ | |
936 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
937 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 938 | |
b15bca31 RE |
939 | #define HARD_FRAME_POINTER_REGNUM \ |
940 | (TARGET_ARM \ | |
941 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
942 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 943 | |
b15bca31 | 944 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 945 | |
b15bca31 RE |
946 | /* Register to use for pushing function arguments. */ |
947 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
948 | |
949 | /* ARM floating pointer registers. */ | |
950 | #define FIRST_ARM_FP_REGNUM 16 | |
951 | #define LAST_ARM_FP_REGNUM 23 | |
952 | ||
35d965d5 | 953 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
954 | #define FRAME_POINTER_REGNUM 25 |
955 | ||
d5b7b3ae RE |
956 | /* Base register for access to arguments of the function. */ |
957 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 958 | |
d5b7b3ae RE |
959 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ |
960 | #define FIRST_PSEUDO_REGISTER 27 | |
62b10bbc | 961 | |
35d965d5 RS |
962 | /* Value should be nonzero if functions must have frame pointers. |
963 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
964 | via the stack pointer) in functions that seem suitable. |
965 | If we have to have a frame pointer we might as well make use of it. | |
966 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 967 | functions, or simple tail call functions. */ |
7b8b8ade NC |
968 | #define FRAME_POINTER_REQUIRED \ |
969 | (current_function_has_nonlocal_label \ | |
d5b7b3ae | 970 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) |
35d965d5 | 971 | |
d5b7b3ae RE |
972 | /* Return number of consecutive hard regs needed starting at reg REGNO |
973 | to hold something of mode MODE. | |
974 | This is ordinarily the length in words of a value of mode MODE | |
975 | but can be less for certain modes in special long registers. | |
35d965d5 | 976 | |
d5b7b3ae RE |
977 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP |
978 | mode. */ | |
979 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
980 | ((TARGET_ARM \ | |
981 | && REGNO >= FIRST_ARM_FP_REGNUM \ | |
982 | && REGNO != FRAME_POINTER_REGNUM \ | |
983 | && REGNO != ARG_POINTER_REGNUM) \ | |
e9d7b180 | 984 | ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 985 | |
4b02997f | 986 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 987 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 988 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 989 | |
d5b7b3ae RE |
990 | /* Value is 1 if it is a good idea to tie two pseudo registers |
991 | when one has mode MODE1 and one has mode MODE2. | |
992 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
993 | for any hard reg, then this must be 0 for correct output. */ | |
994 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
995 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 996 | |
35d965d5 | 997 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
998 | since no saving is required (though calls clobber it) and it never contains |
999 | function parameters. It is quite good to use lr since other calls may | |
1000 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
1001 | least likely to contain a function parameter; in addition results are | |
d5b7b3ae | 1002 | returned in r0. */ |
ff73fb53 | 1003 | #define REG_ALLOC_ORDER \ |
35d965d5 | 1004 | { \ |
ff73fb53 NC |
1005 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
1006 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 1007 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
ff73fb53 | 1008 | 24, 25, 26 \ |
35d965d5 | 1009 | } |
9338ffe6 PB |
1010 | |
1011 | /* Interrupt functions can only use registers that have already been | |
1012 | saved by the prologue, even if they would normally be | |
1013 | call-clobbered. */ | |
1014 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1015 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
1016 | regs_ever_live[DST]) | |
35d965d5 RS |
1017 | \f |
1018 | /* Register and constant classes. */ | |
1019 | ||
d5b7b3ae | 1020 | /* Register classes: used to be simple, just all ARM regs or all FPU regs |
d6a7951f | 1021 | Now that the Thumb is involved it has become more complicated. */ |
35d965d5 RS |
1022 | enum reg_class |
1023 | { | |
1024 | NO_REGS, | |
1025 | FPU_REGS, | |
d5b7b3ae RE |
1026 | LO_REGS, |
1027 | STACK_REG, | |
1028 | BASE_REGS, | |
1029 | HI_REGS, | |
1030 | CC_REG, | |
35d965d5 RS |
1031 | GENERAL_REGS, |
1032 | ALL_REGS, | |
1033 | LIM_REG_CLASSES | |
1034 | }; | |
1035 | ||
1036 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1037 | ||
1038 | /* Give names of register classes as strings for dump file. */ | |
1039 | #define REG_CLASS_NAMES \ | |
1040 | { \ | |
1041 | "NO_REGS", \ | |
1042 | "FPU_REGS", \ | |
d5b7b3ae RE |
1043 | "LO_REGS", \ |
1044 | "STACK_REG", \ | |
1045 | "BASE_REGS", \ | |
1046 | "HI_REGS", \ | |
1047 | "CC_REG", \ | |
35d965d5 RS |
1048 | "GENERAL_REGS", \ |
1049 | "ALL_REGS", \ | |
1050 | } | |
1051 | ||
1052 | /* Define which registers fit in which classes. | |
1053 | This is an initializer for a vector of HARD_REG_SET | |
1054 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
1055 | #define REG_CLASS_CONTENTS \ |
1056 | { \ | |
1057 | { 0x0000000 }, /* NO_REGS */ \ | |
1058 | { 0x0FF0000 }, /* FPU_REGS */ \ | |
d5b7b3ae RE |
1059 | { 0x00000FF }, /* LO_REGS */ \ |
1060 | { 0x0002000 }, /* STACK_REG */ \ | |
1061 | { 0x00020FF }, /* BASE_REGS */ \ | |
1062 | { 0x000FF00 }, /* HI_REGS */ \ | |
1063 | { 0x1000000 }, /* CC_REG */ \ | |
aec3cfba NC |
1064 | { 0x200FFFF }, /* GENERAL_REGS */ \ |
1065 | { 0x2FFFFFF } /* ALL_REGS */ \ | |
35d965d5 | 1066 | } |
4b02997f | 1067 | |
35d965d5 RS |
1068 | /* The same information, inverted: |
1069 | Return the class number of the smallest class containing | |
1070 | reg number REGNO. This could be a conditional expression | |
1071 | or could index an array. */ | |
d5b7b3ae | 1072 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1073 | |
1074 | /* The class value for index registers, and the one for base regs. */ | |
d5b7b3ae RE |
1075 | #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
1076 | #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS) | |
1077 | ||
3dcc68a4 NC |
1078 | /* For the Thumb the high registers cannot be used as base |
1079 | registers when addressing quanitities in QI or HI mode. */ | |
1080 | #define MODE_BASE_REG_CLASS(MODE) \ | |
1081 | (TARGET_ARM ? BASE_REGS : \ | |
1082 | (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \ | |
1083 | ? LO_REGS : BASE_REGS)) | |
1084 | ||
d5b7b3ae RE |
1085 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows |
1086 | registers explicitly used in the rtl to be used as spill registers | |
1087 | but prevents the compiler from extending the lifetime of these | |
1088 | registers. */ | |
1089 | #define SMALL_REGISTER_CLASSES TARGET_THUMB | |
35d965d5 RS |
1090 | |
1091 | /* Get reg_class from a letter such as appears in the machine description. | |
d5b7b3ae RE |
1092 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the |
1093 | ARM, but several more letters for the Thumb. */ | |
1094 | #define REG_CLASS_FROM_LETTER(C) \ | |
1095 | ( (C) == 'f' ? FPU_REGS \ | |
1096 | : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ | |
1097 | : TARGET_ARM ? NO_REGS \ | |
1098 | : (C) == 'h' ? HI_REGS \ | |
1099 | : (C) == 'b' ? BASE_REGS \ | |
1100 | : (C) == 'k' ? STACK_REG \ | |
1101 | : (C) == 'c' ? CC_REG \ | |
1102 | : NO_REGS) | |
35d965d5 RS |
1103 | |
1104 | /* The letters I, J, K, L and M in a register constraint string | |
1105 | can be used to stand for particular ranges of immediate operands. | |
1106 | This macro defines what the ranges are. | |
1107 | C is the letter, and VALUE is a constant value. | |
1108 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 1109 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 1110 | J: valid indexing constants. |
aef1764c | 1111 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
1112 | L: -value ok in rhs argument of data operand. |
1113 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
d5b7b3ae | 1114 | #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ |
aef1764c RE |
1115 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ |
1116 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
1117 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
1118 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
1119 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
1120 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
1121 | : 0) | |
ff9940b0 | 1122 | |
d5b7b3ae RE |
1123 | #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ |
1124 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ | |
1125 | (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ | |
1126 | (C) == 'K' ? thumb_shiftable_const (VAL) : \ | |
1127 | (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ | |
1128 | (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ | |
1129 | && ((VAL) & 3) == 0) : \ | |
1130 | (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ | |
1131 | (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ | |
1132 | : 0) | |
1133 | ||
1134 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1135 | (TARGET_ARM ? \ | |
1136 | CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) | |
1137 | ||
1138 | /* Constant letter 'G' for the FPU immediate constants. | |
1139 | 'H' means the same constant negated. */ | |
1140 | #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ | |
1141 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ | |
1142 | (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
1143 | ||
1144 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ | |
1145 | (TARGET_ARM ? \ | |
1146 | CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) | |
1147 | ||
ff9940b0 RE |
1148 | /* For the ARM, `Q' means that this is a memory operand that is just |
1149 | an offset from a register. | |
1150 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
1151 | address. This means that the symbol is in the text segment and can be | |
1152 | accessed without using a load. */ | |
1153 | ||
d5b7b3ae RE |
1154 | #define EXTRA_CONSTRAINT_ARM(OP, C) \ |
1155 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ | |
1156 | (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
1157 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
1158 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ | |
1159 | (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
7a801826 | 1160 | : 0) |
ff9940b0 | 1161 | |
d5b7b3ae RE |
1162 | #define EXTRA_CONSTRAINT_THUMB(X, C) \ |
1163 | ((C) == 'Q' ? (GET_CODE (X) == MEM \ | |
1164 | && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) | |
1165 | ||
1166 | #define EXTRA_CONSTRAINT(X, C) \ | |
1167 | (TARGET_ARM ? \ | |
1168 | EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) | |
35d965d5 RS |
1169 | |
1170 | /* Given an rtx X being reloaded into a reg required to be | |
1171 | in class CLASS, return the class of reg to actually use. | |
d5b7b3ae RE |
1172 | In general this is just CLASS, but for the Thumb we prefer |
1173 | a LO_REGS class or a subset. */ | |
1174 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1175 | (TARGET_ARM ? (CLASS) : \ | |
1176 | ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) | |
1177 | ||
1178 | /* Must leave BASE_REGS reloads alone */ | |
1179 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1180 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1181 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1182 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1183 | : NO_REGS)) \ | |
1184 | : NO_REGS) | |
1185 | ||
1186 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1187 | ((CLASS) != LO_REGS \ | |
1188 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1189 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1190 | : NO_REGS)) \ | |
1191 | : NO_REGS) | |
35d965d5 | 1192 | |
ff9940b0 RE |
1193 | /* Return the register class of a scratch register needed to copy IN into |
1194 | or out of a register in CLASS in MODE. If it can be done directly, | |
1195 | NO_REGS is returned. */ | |
d5b7b3ae RE |
1196 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1197 | (TARGET_ARM ? \ | |
1198 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
1199 | ? GENERAL_REGS : NO_REGS) \ | |
1200 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
1201 | ||
2ce9c1b9 | 1202 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae RE |
1203 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1204 | (TARGET_ARM ? \ | |
1205 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ | |
1206 | && (GET_CODE (X) == MEM \ | |
1207 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1208 | && true_regnum (X) == -1))) \ | |
1209 | ? GENERAL_REGS : NO_REGS) \ | |
1210 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
2ce9c1b9 | 1211 | |
6f734908 RE |
1212 | /* Try a machine-dependent way of reloading an illegitimate address |
1213 | operand. If we find one, push the reload and jump to WIN. This | |
1214 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1215 | ||
1216 | For the ARM, we wish to handle large displacements off a base | |
1217 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1218 | This can cut the number of reloads needed. */ |
1219 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1220 | do \ | |
1221 | { \ | |
1222 | if (GET_CODE (X) == PLUS \ | |
1223 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1224 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1225 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1226 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1227 | { \ | |
1228 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1229 | HOST_WIDE_INT low, high; \ | |
1230 | \ | |
1231 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1232 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
1233 | else if (MODE == SImode \ | |
1234 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1235 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1236 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1237 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1238 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1239 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1240 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1241 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1242 | && TARGET_HARD_FLOAT) \ | |
1243 | /* Need to be careful, -1024 is not a valid offset. */ \ | |
1244 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1245 | else \ | |
1246 | break; \ | |
1247 | \ | |
30cf4896 KG |
1248 | high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ |
1249 | ^ (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1250 | - (unsigned HOST_WIDE_INT) 0x80000000); \ | |
d5b7b3ae RE |
1251 | /* Check for overflow or zero */ \ |
1252 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1253 | break; \ | |
1254 | \ | |
1255 | /* Reload the high part into a base reg; leave the low part \ | |
1256 | in the mem. */ \ | |
1257 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1258 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1259 | GEN_INT (high)), \ | |
1260 | GEN_INT (low)); \ | |
df4ae160 | 1261 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
4a692617 NC |
1262 | MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ |
1263 | VOIDmode, 0, 0, OPNUM, TYPE); \ | |
d5b7b3ae RE |
1264 | goto WIN; \ |
1265 | } \ | |
1266 | } \ | |
62b10bbc | 1267 | while (0) |
6f734908 | 1268 | |
d5b7b3ae RE |
1269 | /* ??? If an HImode FP+large_offset address is converted to an HImode |
1270 | SP+large_offset address, then reload won't know how to fix it. It sees | |
1271 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1272 | register, but the resulting address is still invalid because the offset | |
1273 | is too big. We fix it here instead by reloading the entire address. */ | |
1274 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1275 | cope with the variances between the Thumb's signed and unsigned byte and | |
1276 | halfword load instructions. */ | |
1277 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1278 | { \ | |
1279 | if (GET_CODE (X) == PLUS \ | |
1280 | && GET_MODE_SIZE (MODE) < 4 \ | |
1281 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1282 | && XEXP (X, 0) == stack_pointer_rtx \ | |
1283 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 1284 | && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
1285 | { \ |
1286 | rtx orig_X = X; \ | |
1287 | X = copy_rtx (X); \ | |
df4ae160 | 1288 | push_reload (orig_X, NULL_RTX, &X, NULL, \ |
4a692617 | 1289 | MODE_BASE_REG_CLASS (MODE), \ |
d5b7b3ae RE |
1290 | Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ |
1291 | goto WIN; \ | |
1292 | } \ | |
1293 | } | |
1294 | ||
1295 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1296 | if (TARGET_ARM) \ | |
1297 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1298 | else \ | |
1299 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
1300 | ||
35d965d5 RS |
1301 | /* Return the maximum number of consecutive registers |
1302 | needed to represent mode MODE in a register of class CLASS. | |
1303 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
1304 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
e9d7b180 | 1305 | ((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 1306 | |
ff9940b0 | 1307 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
cf011243 | 1308 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
d5b7b3ae RE |
1309 | (TARGET_ARM ? \ |
1310 | ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ | |
1311 | (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ | |
1312 | : \ | |
1313 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 RS |
1314 | \f |
1315 | /* Stack layout; function entry, exit and calling. */ | |
1316 | ||
1317 | /* Define this if pushing a word on the stack | |
1318 | makes the stack pointer a smaller address. */ | |
1319 | #define STACK_GROWS_DOWNWARD 1 | |
1320 | ||
1321 | /* Define this if the nominal address of the stack frame | |
1322 | is at the high-address end of the local variables; | |
1323 | that is, each additional local variable allocated | |
1324 | goes at a more negative offset in the frame. */ | |
1325 | #define FRAME_GROWS_DOWNWARD 1 | |
1326 | ||
1327 | /* Offset within stack frame to start allocating local variables at. | |
1328 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1329 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1330 | of the first local allocated. */ | |
1331 | #define STARTING_FRAME_OFFSET 0 | |
1332 | ||
1333 | /* If we generate an insn to push BYTES bytes, | |
1334 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae RE |
1335 | /* The push insns do not do this rounding implicitly. |
1336 | So don't define this. */ | |
1337 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ | |
18543a22 ILT |
1338 | |
1339 | /* Define this if the maximum size of all the outgoing args is to be | |
1340 | accumulated and pushed during the prologue. The amount can be | |
1341 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1342 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1343 | |
1344 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1345 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1346 | |
1347 | /* Value is the number of byte of arguments automatically | |
1348 | popped when returning from a subroutine call. | |
8b109b37 | 1349 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1350 | FUNTYPE is the data type of the function (as a tree), |
1351 | or for a library call it is an identifier node for the subroutine name. | |
1352 | SIZE is the number of bytes of arguments passed on the stack. | |
1353 | ||
1354 | On the ARM, the caller does not pop any of its arguments that were passed | |
1355 | on the stack. */ | |
6cfc7210 | 1356 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1357 | |
1358 | /* Define how to find the value returned by a library function | |
1359 | assuming the value has mode MODE. */ | |
1360 | #define LIBCALL_VALUE(MODE) \ | |
d5b7b3ae RE |
1361 | (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1362 | ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ | |
1363 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) | |
35d965d5 | 1364 | |
6cfc7210 NC |
1365 | /* Define how to find the value returned by a function. |
1366 | VALTYPE is the data type of the value (as a tree). | |
1367 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1368 | otherwise, FUNC is 0. */ | |
d5b7b3ae | 1369 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
6cfc7210 NC |
1370 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
1371 | ||
35d965d5 RS |
1372 | /* 1 if N is a possible register number for a function value. |
1373 | On the ARM, only r0 and f0 can return results. */ | |
1374 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
d5b7b3ae RE |
1375 | ((REGNO) == ARG_REGISTER (1) \ |
1376 | || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) | |
35d965d5 | 1377 | |
11c1a207 RE |
1378 | /* How large values are returned */ |
1379 | /* A C expression which can inhibit the returning of certain function values | |
1380 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1381 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1382 | |
1383 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1384 | values must be in memory. On the ARM, they need only do so if larger | |
1385 | than a word, or if they contain elements offset from zero in the struct. */ | |
1386 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1387 | ||
d5b7b3ae RE |
1388 | /* Flags for the call/call_value rtl operations set up by function_arg. */ |
1389 | #define CALL_NORMAL 0x00000000 /* No special processing. */ | |
1390 | #define CALL_LONG 0x00000001 /* Always call indirect. */ | |
1391 | #define CALL_SHORT 0x00000002 /* Never call indirect. */ | |
1392 | ||
6d3d9133 NC |
1393 | /* These bits describe the different types of function supported |
1394 | by the ARM backend. They are exclusive. ie a function cannot be both a | |
1395 | normal function and an interworked function, for example. Knowing the | |
1396 | type of a function is important for determining its prologue and | |
1397 | epilogue sequences. | |
1398 | Note value 7 is currently unassigned. Also note that the interrupt | |
1399 | function types all have bit 2 set, so that they can be tested for easily. | |
1400 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1401 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1402 | default to unknown. This will force the first use of arm_current_func_type |
1403 | to call arm_compute_func_type. */ | |
1404 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1405 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1406 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
1407 | #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ | |
1408 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
1409 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1410 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1411 | ||
1412 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1413 | ||
1414 | /* In addition functions can have several type modifiers, | |
1415 | outlined by these bit masks: */ | |
1416 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1417 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1418 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
1419 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
1420 | ||
1421 | /* Some macros to test these flags. */ | |
1422 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1423 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1424 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1425 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1426 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
1427 | ||
1428 | /* A C structure for machine-specific, per-function data. | |
1429 | This is added to the cfun structure. */ | |
e2500fed | 1430 | typedef struct machine_function GTY(()) |
d5b7b3ae | 1431 | { |
d5b7b3ae | 1432 | /* Additionsl stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1433 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1434 | /* Records if LR has to be saved for far jumps. */ |
1435 | int far_jump_used; | |
1436 | /* Records if ARG_POINTER was ever live. */ | |
1437 | int arg_pointer_live; | |
6f7ebcbb NC |
1438 | /* Records if the save of LR has been eliminated. */ |
1439 | int lr_save_eliminated; | |
6d3d9133 NC |
1440 | /* Records the type of the current function. */ |
1441 | unsigned long func_type; | |
3cb66fd7 NC |
1442 | /* Record if the function has a variable argument list. */ |
1443 | int uses_anonymous_args; | |
6d3d9133 NC |
1444 | } |
1445 | machine_function; | |
d5b7b3ae | 1446 | |
82e9d970 PB |
1447 | /* A C type for declaring a variable that is used as the first argument of |
1448 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1449 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1450 | typedef struct | |
1451 | { | |
d5b7b3ae | 1452 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1453 | int nregs; |
d5b7b3ae | 1454 | /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ |
82e9d970 | 1455 | int call_cookie; |
d5b7b3ae | 1456 | } CUMULATIVE_ARGS; |
82e9d970 | 1457 | |
35d965d5 RS |
1458 | /* Define where to put the arguments to a function. |
1459 | Value is zero to push the argument on the stack, | |
1460 | or a hard register in which to store the argument. | |
1461 | ||
1462 | MODE is the argument's machine mode. | |
1463 | TYPE is the data type of the argument (as a tree). | |
1464 | This is null for libcalls where that information may | |
1465 | not be available. | |
1466 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1467 | the preceding args and about the function being called. | |
1468 | NAMED is nonzero if this argument is a named parameter | |
1469 | (otherwise it is an extra parameter matching an ellipsis). | |
1470 | ||
1471 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1472 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1473 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1474 | passed in the stack (function_prologue will indeed make it pass in the | |
1475 | stack if necessary). */ | |
82e9d970 PB |
1476 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1477 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1478 | |
1479 | /* For an arg passed partly in registers and partly in memory, | |
1480 | this is the number of registers used. | |
1481 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1482 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1483 | ( NUM_ARG_REGS > (CUM).nregs \ |
e9d7b180 | 1484 | && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ |
82e9d970 | 1485 | ? NUM_ARG_REGS - (CUM).nregs : 0) |
35d965d5 RS |
1486 | |
1487 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1488 | for a call to a function whose data type is FNTYPE. | |
1489 | For a library call, FNTYPE is 0. | |
1490 | On the ARM, the offset starts at 0. */ | |
82e9d970 PB |
1491 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1492 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) | |
35d965d5 RS |
1493 | |
1494 | /* Update the data in CUM to advance over an argument | |
1495 | of mode MODE and data type TYPE. | |
1496 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1497 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
e9d7b180 | 1498 | (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1499 | |
1500 | /* 1 if N is a possible register number for function argument passing. | |
1501 | On the ARM, r0-r3 are used to pass args. */ | |
5297e085 | 1502 | #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3)) |
35d965d5 | 1503 | |
f99fce0c RE |
1504 | \f |
1505 | /* Tail calling. */ | |
1506 | ||
1507 | /* A C expression that evaluates to true if it is ok to perform a sibling | |
1508 | call to DECL. */ | |
1509 | #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) | |
1510 | ||
35d965d5 RS |
1511 | /* Perform any actions needed for a function that is receiving a variable |
1512 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1513 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1514 | the amount of stack that must be pushed by the prolog to pretend that our | |
1515 | caller pushed it. | |
1516 | ||
1517 | Normally, this macro will push all remaining incoming registers on the | |
1518 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1519 | ||
1520 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1521 | named arg and all anonymous args onto the stack. | |
1522 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1523 | that way. */ | |
6cfc7210 | 1524 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 | 1525 | { \ |
3cb66fd7 | 1526 | cfun->machine->uses_anonymous_args = 1; \ |
82e9d970 PB |
1527 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1528 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1529 | } |
1530 | ||
afef3d7a NC |
1531 | /* If your target environment doesn't prefix user functions with an |
1532 | underscore, you may wish to re-define this to prevent any conflicts. | |
1533 | e.g. AOF may prefix mcount with an underscore. */ | |
1534 | #ifndef ARM_MCOUNT_NAME | |
1535 | #define ARM_MCOUNT_NAME "*mcount" | |
1536 | #endif | |
1537 | ||
1538 | /* Call the function profiler with a given profile label. The Acorn | |
1539 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1540 | On the ARM the full profile code will look like: | |
1541 | .data | |
1542 | LP1 | |
1543 | .word 0 | |
1544 | .text | |
1545 | mov ip, lr | |
1546 | bl mcount | |
1547 | .word LP1 | |
1548 | ||
1549 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1550 | will output the .text section. | |
1551 | ||
1552 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
1553 | ``prof'' doesn't seem to mind about this! */ | |
be393ecf | 1554 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1555 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1556 | { \ |
1557 | char temp[20]; \ | |
1558 | rtx sym; \ | |
1559 | \ | |
dd18ae56 | 1560 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1561 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1562 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1563 | fputc ('\n', STREAM); \ | |
1564 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1565 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
301d03af | 1566 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1567 | } |
be393ecf | 1568 | #endif |
35d965d5 | 1569 | |
cf8002d0 | 1570 | #ifndef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1571 | #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \ |
1572 | { \ | |
89632846 | 1573 | fprintf (STREAM, "\tmov\tip, lr\n"); \ |
d5b7b3ae RE |
1574 | fprintf (STREAM, "\tbl\tmcount\n"); \ |
1575 | fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \ | |
1576 | } | |
cf8002d0 | 1577 | #endif |
d5b7b3ae RE |
1578 | |
1579 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1580 | if (TARGET_ARM) \ | |
1581 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1582 | else \ | |
1583 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
1584 | ||
35d965d5 RS |
1585 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1586 | the stack pointer does not matter. The value is tested only in | |
1587 | functions that have frame pointers. | |
1588 | No definition is equivalent to always zero. | |
1589 | ||
1590 | On the ARM, the function epilogue recovers the stack pointer from the | |
1591 | frame. */ | |
1592 | #define EXIT_IGNORE_STACK 1 | |
1593 | ||
c7861455 RE |
1594 | #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) |
1595 | ||
35d965d5 RS |
1596 | /* Determine if the epilogue should be output as RTL. |
1597 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae RE |
1598 | #define USE_RETURN_INSN(ISCOND) \ |
1599 | (TARGET_ARM ? use_return_insn (ISCOND) : 0) | |
ff9940b0 RE |
1600 | |
1601 | /* Definitions for register eliminations. | |
1602 | ||
1603 | This is an array of structures. Each structure initializes one pair | |
1604 | of eliminable registers. The "from" register number is given first, | |
1605 | followed by "to". Eliminations of the same "from" register are listed | |
1606 | in order of preference. | |
1607 | ||
1608 | We have two registers that can be eliminated on the ARM. First, the | |
1609 | arg pointer register can often be eliminated in favor of the stack | |
1610 | pointer register. Secondly, the pseudo frame pointer register can always | |
1611 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1612 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1613 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1614 | |
d5b7b3ae RE |
1615 | #define ELIMINABLE_REGS \ |
1616 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1617 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1618 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1619 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1620 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1621 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1622 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1623 | |
d5b7b3ae RE |
1624 | /* Given FROM and TO register numbers, say whether this elimination is |
1625 | allowed. Frame pointer elimination is automatically handled. | |
ff9940b0 RE |
1626 | |
1627 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1628 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 | 1629 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
d5b7b3ae RE |
1630 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or |
1631 | ARG_POINTER_REGNUM. */ | |
1632 | #define CAN_ELIMINATE(FROM, TO) \ | |
1633 | (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ | |
1634 | ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ | |
1635 | ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ | |
1636 | ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ | |
1637 | 1) | |
aeaf4d25 AN |
1638 | |
1639 | #define THUMB_REG_PUSHED_P(reg) \ | |
1640 | (regs_ever_live [reg] \ | |
1641 | && (! call_used_regs [reg] \ | |
1642 | || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \ | |
1643 | && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register))) | |
1644 | ||
d5b7b3ae RE |
1645 | /* Define the offset between two registers, one to be eliminated, and the |
1646 | other its replacement, at the start of a routine. */ | |
1647 | #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
095bb276 | 1648 | do \ |
ff9940b0 | 1649 | { \ |
095bb276 | 1650 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
ff9940b0 | 1651 | } \ |
095bb276 | 1652 | while (0) |
35d965d5 | 1653 | |
d5b7b3ae RE |
1654 | /* Note: This macro must match the code in thumb_function_prologue(). */ |
1655 | #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1656 | { \ | |
1657 | (OFFSET) = 0; \ | |
1658 | if ((FROM) == ARG_POINTER_REGNUM) \ | |
1659 | { \ | |
1660 | int count_regs = 0; \ | |
1661 | int regno; \ | |
1662 | for (regno = 8; regno < 13; regno ++) \ | |
aeaf4d25 AN |
1663 | if (THUMB_REG_PUSHED_P (regno)) \ |
1664 | count_regs ++; \ | |
d5b7b3ae RE |
1665 | if (count_regs) \ |
1666 | (OFFSET) += 4 * count_regs; \ | |
1667 | count_regs = 0; \ | |
1668 | for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ | |
aeaf4d25 | 1669 | if (THUMB_REG_PUSHED_P (regno)) \ |
d5b7b3ae RE |
1670 | count_regs ++; \ |
1671 | if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ | |
1672 | (OFFSET) += 4 * (count_regs + 1); \ | |
1673 | if (TARGET_BACKTRACE) \ | |
1674 | { \ | |
1675 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ | |
1676 | (OFFSET) += 20; \ | |
1677 | else \ | |
1678 | (OFFSET) += 16; \ | |
1679 | } \ | |
1680 | } \ | |
1681 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1682 | { \ | |
1683 | (OFFSET) += current_function_outgoing_args_size; \ | |
1684 | (OFFSET) += ROUND_UP (get_frame_size ()); \ | |
1685 | } \ | |
1686 | } | |
1687 | ||
1688 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1689 | if (TARGET_ARM) \ | |
095bb276 | 1690 | ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ |
d5b7b3ae RE |
1691 | else \ |
1692 | THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) | |
1693 | ||
1694 | /* Special case handling of the location of arguments passed on the stack. */ | |
1695 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
1696 | ||
1697 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1698 | once for every function before code is generated. */ | |
1699 | #define INIT_EXPANDERS arm_init_expanders () | |
1700 | ||
35d965d5 RS |
1701 | /* Output assembler code for a block containing the constant parts |
1702 | of a trampoline, leaving space for the variable parts. | |
1703 | ||
1704 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1705 | referencing pc adds an offset of 8) the trampoline looks like: | |
1706 | ldr r8, [pc, #0] | |
1707 | ldr pc, [pc] | |
1708 | .word static chain value | |
11c1a207 RE |
1709 | .word function's address |
1710 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
301d03af RS |
1711 | #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ |
1712 | { \ | |
1713 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1714 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1715 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1716 | PC_REGNUM, PC_REGNUM); \ | |
1717 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
1718 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
d5b7b3ae RE |
1719 | } |
1720 | ||
1721 | /* On the Thumb we always switch into ARM mode to execute the trampoline. | |
1722 | Why - because it is easier. This code will always be branched to via | |
1723 | a BX instruction and since the compiler magically generates the address | |
1724 | of the function the linker has no opportunity to ensure that the | |
1725 | bottom bit is set. Thus the processor will be in ARM mode when it | |
1726 | reaches this code. So we duplicate the ARM trampoline code and add | |
1727 | a switch into Thumb mode as well. */ | |
1728 | #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ | |
1729 | { \ | |
1730 | fprintf (FILE, "\t.code 32\n"); \ | |
1731 | fprintf (FILE, ".Ltrampoline_start:\n"); \ | |
1732 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1733 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1734 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1735 | IP_REGNUM, PC_REGNUM); \ | |
1736 | asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ | |
1737 | IP_REGNUM, IP_REGNUM); \ | |
1738 | asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ | |
1739 | fprintf (FILE, "\t.word\t0\n"); \ | |
1740 | fprintf (FILE, "\t.word\t0\n"); \ | |
1741 | fprintf (FILE, "\t.code 16\n"); \ | |
35d965d5 RS |
1742 | } |
1743 | ||
d5b7b3ae RE |
1744 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1745 | if (TARGET_ARM) \ | |
1746 | ARM_TRAMPOLINE_TEMPLATE (FILE) \ | |
1747 | else \ | |
1748 | THUMB_TRAMPOLINE_TEMPLATE (FILE) | |
1749 | ||
35d965d5 | 1750 | /* Length in units of the trampoline for entering a nested function. */ |
d5b7b3ae | 1751 | #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) |
35d965d5 | 1752 | |
006946e4 JM |
1753 | /* Alignment required for a trampoline in bits. */ |
1754 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1755 | |
1756 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1757 | FNADDR is an RTX for the address of the function's pure code. | |
1758 | CXT is an RTX for the static chain value for the function. */ | |
d5b7b3ae RE |
1759 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1760 | { \ | |
1761 | emit_move_insn \ | |
1762 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ | |
1763 | emit_move_insn \ | |
1764 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ | |
35d965d5 RS |
1765 | } |
1766 | ||
35d965d5 RS |
1767 | \f |
1768 | /* Addressing modes, and classification of registers for them. */ | |
35d965d5 | 1769 | #define HAVE_POST_INCREMENT 1 |
d5b7b3ae RE |
1770 | #define HAVE_PRE_INCREMENT TARGET_ARM |
1771 | #define HAVE_POST_DECREMENT TARGET_ARM | |
1772 | #define HAVE_PRE_DECREMENT TARGET_ARM | |
35d965d5 RS |
1773 | |
1774 | /* Macros to check register numbers against specific register classes. */ | |
1775 | ||
1776 | /* These assume that REGNO is a hard or pseudo reg number. | |
1777 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1778 | or a pseudo reg currently allocated to a suitable hard reg. | |
1779 | Since they use reg_renumber, they are safe only once reg_renumber | |
d5b7b3ae RE |
1780 | has been allocated, which happens in local-alloc.c. */ |
1781 | #define TEST_REGNO(R, TEST, VALUE) \ | |
1782 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1783 | ||
1784 | /* On the ARM, don't allow the pc to be used. */ | |
f1008e52 RE |
1785 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1786 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1787 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1788 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1789 | ||
1790 | #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1791 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
1792 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1793 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1794 | ||
1795 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1796 | (TARGET_THUMB \ | |
1797 | ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
1798 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
1799 | ||
1800 | /* For ARM code, we don't care about the mode, but for Thumb, the index | |
1801 | must be suitable for use in a QImode load. */ | |
d5b7b3ae RE |
1802 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1803 | REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) | |
35d965d5 RS |
1804 | |
1805 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 | 1806 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1807 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1808 | |
1809 | /* Recognize any constant value that is a valid address. */ | |
1810 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1811 | |
1812 | #ifdef AOF_ASSEMBLER | |
1813 | ||
1814 | #define CONSTANT_ADDRESS_P(X) \ | |
d5b7b3ae | 1815 | (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) |
11c1a207 RE |
1816 | |
1817 | #else | |
35d965d5 | 1818 | |
008cf58a RE |
1819 | #define CONSTANT_ADDRESS_P(X) \ |
1820 | (GET_CODE (X) == SYMBOL_REF \ | |
1821 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1822 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1823 | |
11c1a207 RE |
1824 | #endif /* AOF_ASSEMBLER */ |
1825 | ||
35d965d5 RS |
1826 | /* Nonzero if the constant value X is a legitimate general operand. |
1827 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1828 | ||
1829 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1830 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1831 | constant pool XXX. |
82e9d970 PB |
1832 | |
1833 | When generating pic allow anything. */ | |
d5b7b3ae RE |
1834 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1835 | ||
1836 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1837 | ( GET_CODE (X) == CONST_INT \ | |
1838 | || GET_CODE (X) == CONST_DOUBLE \ | |
7b8781c8 PB |
1839 | || CONSTANT_ADDRESS_P (X) \ |
1840 | || flag_pic) | |
d5b7b3ae RE |
1841 | |
1842 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1843 | (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) | |
1844 | ||
c27ba912 DM |
1845 | /* Special characters prefixed to function names |
1846 | in order to encode attribute like information. | |
1847 | Note, '@' and '*' have already been taken. */ | |
1848 | #define SHORT_CALL_FLAG_CHAR '^' | |
1849 | #define LONG_CALL_FLAG_CHAR '#' | |
1850 | ||
1851 | #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ | |
1852 | (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) | |
1853 | ||
1854 | #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ | |
1855 | (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) | |
1856 | ||
1857 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
1858 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1859 | #endif | |
1860 | ||
1861 | /* This is a C fragement for the inside of a switch statement. | |
1862 | Each case label should return the number of characters to | |
1863 | be stripped from the start of a function's name, if that | |
1864 | name starts with the indicated character. */ | |
1865 | #define ARM_NAME_ENCODING_LENGTHS \ | |
1866 | case SHORT_CALL_FLAG_CHAR: return 1; \ | |
1867 | case LONG_CALL_FLAG_CHAR: return 1; \ | |
00fdafef | 1868 | case '*': return 1; \ |
c27ba912 DM |
1869 | SUBTARGET_NAME_ENCODING_LENGTHS |
1870 | ||
c27ba912 DM |
1871 | /* This is how to output a reference to a user-level label named NAME. |
1872 | `assemble_name' uses this. */ | |
e5951263 | 1873 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1874 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1875 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1876 | |
c27ba912 DM |
1877 | #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ |
1878 | arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) | |
1879 | ||
35d965d5 RS |
1880 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1881 | and check its validity for a certain class. | |
1882 | We have two alternate definitions for each of them. | |
1883 | The usual definition accepts all pseudo regs; the other rejects | |
1884 | them unless they have been allocated suitable hard regs. | |
1885 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1886 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1887 | |
f1008e52 RE |
1888 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1889 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1890 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1891 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1892 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1893 | |
f1008e52 RE |
1894 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1895 | (REGNO (X) <= LAST_LO_REGNUM \ | |
1896 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1897 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1898 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1899 | || (X) == hard_frame_pointer_rtx \ | |
1900 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1901 | |
d5b7b3ae | 1902 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1903 | |
f1008e52 RE |
1904 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1905 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1906 | |
f1008e52 RE |
1907 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1908 | THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 1909 | |
d5b7b3ae | 1910 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
1911 | |
1912 | /* Now define some helpers in terms of the above. */ | |
1913 | ||
1914 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
1915 | (TARGET_THUMB \ | |
1916 | ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
1917 | : ARM_REG_OK_FOR_BASE_P (X)) | |
1918 | ||
1919 | #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) | |
1920 | ||
1921 | /* For Thumb, a valid index register is anything that can be used in | |
1922 | a byte load instruction. */ | |
1923 | #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
1924 | ||
1925 | /* Nonzero if X is a hard reg that can be used as an index | |
1926 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
1927 | is not suitable. */ | |
1928 | #define REG_OK_FOR_INDEX_P(X) \ | |
1929 | (TARGET_THUMB \ | |
1930 | ? THUMB_REG_OK_FOR_INDEX_P (X) \ | |
1931 | : ARM_REG_OK_FOR_INDEX_P (X)) | |
1932 | ||
35d965d5 RS |
1933 | \f |
1934 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1935 | that is a valid memory address for an instruction. | |
1936 | The MODE argument is the machine mode for the MEM expression | |
1937 | that wants to use this address. | |
1938 | ||
d5b7b3ae RE |
1939 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ |
1940 | ||
1941 | /* --------------------------------arm version----------------------------- */ | |
f1008e52 RE |
1942 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
1943 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 1944 | |
f1008e52 RE |
1945 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
1946 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 RS |
1947 | |
1948 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
1949 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
1950 | only be small constants. */ | |
f1008e52 RE |
1951 | #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
1952 | do \ | |
35d965d5 | 1953 | { \ |
f1008e52 RE |
1954 | HOST_WIDE_INT range; \ |
1955 | enum rtx_code code = GET_CODE (INDEX); \ | |
35d965d5 | 1956 | \ |
f1008e52 RE |
1957 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
1958 | { \ | |
1959 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
1960 | && INTVAL (INDEX) > -1024 \ | |
1961 | && (INTVAL (INDEX) & 3) == 0) \ | |
1962 | goto LABEL; \ | |
1963 | } \ | |
1964 | else \ | |
1965 | { \ | |
1966 | if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ | |
1967 | && GET_MODE_SIZE (MODE) <= 4) \ | |
1968 | goto LABEL; \ | |
1969 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ | |
1970 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1971 | { \ | |
1972 | rtx xiop0 = XEXP (INDEX, 0); \ | |
1973 | rtx xiop1 = XEXP (INDEX, 1); \ | |
1974 | if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ | |
1975 | && power_of_two_operand (xiop1, SImode)) \ | |
1976 | goto LABEL; \ | |
1977 | if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ | |
1978 | && power_of_two_operand (xiop0, SImode)) \ | |
1979 | goto LABEL; \ | |
1980 | } \ | |
1981 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
1982 | && (code == LSHIFTRT || code == ASHIFTRT \ | |
1983 | || code == ASHIFT || code == ROTATERT) \ | |
1984 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1985 | { \ | |
1986 | rtx op = XEXP (INDEX, 1); \ | |
1987 | if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
1988 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
1989 | && INTVAL (op) <= 31) \ | |
1990 | goto LABEL; \ | |
1991 | } \ | |
1992 | /* NASTY: Since this limits the addressing of unsigned \ | |
1993 | byte loads. */ \ | |
1994 | range = ((MODE) == HImode || (MODE) == QImode) \ | |
1995 | ? (arm_arch4 ? 256 : 4095) : 4096; \ | |
1996 | if (code == CONST_INT && INTVAL (INDEX) < range \ | |
1997 | && INTVAL (INDEX) > -range) \ | |
1998 | goto LABEL; \ | |
1999 | } \ | |
35d965d5 | 2000 | } \ |
f1008e52 RE |
2001 | while (0) |
2002 | ||
2003 | /* Jump to LABEL if X is a valid address RTX. This must take | |
2004 | REG_OK_STRICT into account when deciding about valid registers. | |
2005 | ||
2006 | Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non | |
2007 | floating SYMBOL_REF to the constant pool. Allow REG-only and | |
2008 | AUTINC-REG if handling TImode or HImode. Other symbol refs must be | |
2009 | forced though a static cell to ensure addressability. */ | |
d19fb8e3 NC |
2010 | #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
2011 | { \ | |
2012 | if (ARM_BASE_REGISTER_RTX_P (X)) \ | |
2013 | goto LABEL; \ | |
2014 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
2015 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2016 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2017 | goto LABEL; \ | |
2018 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2019 | && (GET_CODE (X) == LABEL_REF \ | |
2020 | || (GET_CODE (X) == CONST \ | |
2021 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
2022 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
2023 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
2024 | goto LABEL; \ | |
2025 | else if ((MODE) == TImode) \ | |
2026 | ; \ | |
2027 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ | |
2028 | { \ | |
2029 | if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
2030 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2031 | { \ | |
2032 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
2033 | if (val == 4 || val == -4 || val == -8) \ | |
2034 | goto LABEL; \ | |
2035 | } \ | |
2036 | } \ | |
2037 | else if (GET_CODE (X) == PLUS) \ | |
2038 | { \ | |
2039 | rtx xop0 = XEXP (X, 0); \ | |
2040 | rtx xop1 = XEXP (X, 1); \ | |
2041 | \ | |
2042 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2043 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
2044 | else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ | |
2045 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
2046 | } \ | |
2047 | /* Reload currently can't handle MINUS, so disable this for now */ \ | |
2048 | /* else if (GET_CODE (X) == MINUS) \ | |
2049 | { \ | |
2050 | rtx xop0 = XEXP (X,0); \ | |
2051 | rtx xop1 = XEXP (X,1); \ | |
2052 | \ | |
2053 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2054 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
2055 | } */ \ | |
2056 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2057 | && GET_CODE (X) == SYMBOL_REF \ | |
2058 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2059 | && ! (flag_pic \ | |
2060 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2061 | goto LABEL; \ | |
2062 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
2063 | && (GET_MODE_SIZE (MODE) <= 4) \ | |
2064 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2065 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2066 | goto LABEL; \ | |
35d965d5 | 2067 | } |
d5b7b3ae RE |
2068 | |
2069 | /* ---------------------thumb version----------------------------------*/ | |
f1008e52 | 2070 | #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ |
d5b7b3ae RE |
2071 | (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ |
2072 | : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ | |
2073 | && ((VAL) & 1) == 0) \ | |
2074 | : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ | |
2075 | && ((VAL) & 3) == 0)) | |
2076 | ||
2077 | /* The AP may be eliminated to either the SP or the FP, so we use the | |
2078 | least common denominator, e.g. SImode, and offsets from 0 to 64. */ | |
2079 | ||
2080 | /* ??? Verify whether the above is the right approach. */ | |
2081 | ||
2082 | /* ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2083 | needs special handling also. */ | |
2084 | ||
2085 | /* ??? Look at how the mips16 port solves this problem. It probably uses | |
2086 | better ways to solve some of these problems. */ | |
2087 | ||
2088 | /* Although it is not incorrect, we don't accept QImode and HImode | |
f1008e52 RE |
2089 | addresses based on the frame pointer or arg pointer until the |
2090 | reload pass starts. This is so that eliminating such addresses | |
2091 | into stack based ones won't produce impossible code. */ | |
d5b7b3ae RE |
2092 | #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ |
2093 | { \ | |
2094 | /* ??? Not clear if this is right. Experiment. */ \ | |
2095 | if (GET_MODE_SIZE (MODE) < 4 \ | |
2096 | && ! (reload_in_progress || reload_completed) \ | |
2097 | && ( reg_mentioned_p (frame_pointer_rtx, X) \ | |
2098 | || reg_mentioned_p (arg_pointer_rtx, X) \ | |
2099 | || reg_mentioned_p (virtual_incoming_args_rtx, X) \ | |
2100 | || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ | |
2101 | || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ | |
2102 | || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ | |
2103 | ; \ | |
2104 | /* Accept any base register. SP only in SImode or larger. */ \ | |
f1008e52 RE |
2105 | else if (GET_CODE (X) == REG \ |
2106 | && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ | |
d5b7b3ae RE |
2107 | goto WIN; \ |
2108 | /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ | |
2109 | else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ | |
48f6efae NC |
2110 | && GET_CODE (X) == SYMBOL_REF \ |
2111 | && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ | |
d5b7b3ae RE |
2112 | goto WIN; \ |
2113 | /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ | |
2114 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2115 | && (GET_CODE (X) == LABEL_REF \ | |
2116 | || (GET_CODE (X) == CONST \ | |
2117 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
2118 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ | |
2119 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ | |
2120 | goto WIN; \ | |
2121 | /* Post-inc indexing only supported for SImode and larger. */ \ | |
2122 | else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ | |
2123 | && GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2124 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
d5b7b3ae RE |
2125 | goto WIN; \ |
2126 | else if (GET_CODE (X) == PLUS) \ | |
2127 | { \ | |
2128 | /* REG+REG address can be any two index registers. */ \ | |
2129 | /* We disallow FRAME+REG addressing since we know that FRAME \ | |
2130 | will be replaced with STACK, and SP relative addressing only \ | |
2131 | permits SP+OFFSET. */ \ | |
2132 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2133 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2134 | && GET_CODE (XEXP (X, 1)) == REG \ | |
2135 | && XEXP (X, 0) != frame_pointer_rtx \ | |
2136 | && XEXP (X, 1) != frame_pointer_rtx \ | |
2137 | && XEXP (X, 0) != virtual_stack_vars_rtx \ | |
2138 | && XEXP (X, 1) != virtual_stack_vars_rtx \ | |
f1008e52 RE |
2139 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
2140 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ | |
d5b7b3ae RE |
2141 | goto WIN; \ |
2142 | /* REG+const has 5-7 bit offset for non-SP registers. */ \ | |
2143 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2144 | && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
d5b7b3ae RE |
2145 | || XEXP (X, 0) == arg_pointer_rtx) \ |
2146 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 2147 | && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
2148 | goto WIN; \ |
2149 | /* REG+const has 10 bit offset for SP, but only SImode and \ | |
2150 | larger is supported. */ \ | |
2151 | /* ??? Should probably check for DI/DFmode overflow here \ | |
2152 | just like GO_IF_LEGITIMATE_OFFSET does. */ \ | |
2153 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2154 | && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ | |
2155 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2156 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2157 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ | |
2158 | + GET_MODE_SIZE (MODE)) <= 1024 \ | |
2159 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2160 | goto WIN; \ | |
2161 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2162 | && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ | |
2163 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2164 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2165 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2166 | goto WIN; \ | |
2167 | } \ | |
2168 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2169 | && GET_CODE (X) == SYMBOL_REF \ | |
2170 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2171 | && ! (flag_pic \ | |
2172 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2173 | goto WIN; \ | |
2174 | } | |
2175 | ||
2176 | /* ------------------------------------------------------------------- */ | |
2177 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
2178 | if (TARGET_ARM) \ | |
2179 | ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ | |
2180 | else /* if (TARGET_THUMB) */ \ | |
2181 | THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) | |
2182 | /* ------------------------------------------------------------------- */ | |
35d965d5 RS |
2183 | \f |
2184 | /* Try machine-dependent ways of modifying an illegitimate address | |
2185 | to be legitimate. If we find one, return the new, valid address. | |
2186 | This macro is used in only one place: `memory_address' in explow.c. | |
2187 | ||
2188 | OLDX is the address as it was before break_out_memory_refs was called. | |
2189 | In some cases it is useful to look at this to decide what needs to be done. | |
2190 | ||
2191 | MODE and WIN are passed so that this macro can use | |
2192 | GO_IF_LEGITIMATE_ADDRESS. | |
2193 | ||
2194 | It is always safe for this macro to do nothing. It exists to recognize | |
2195 | opportunities to optimize the output. | |
2196 | ||
2197 | On the ARM, try to convert [REG, #BIGCONST] | |
2198 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
2199 | where VALIDCONST == 0 in case of TImode. */ | |
d5b7b3ae | 2200 | #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
3967692c RE |
2201 | { \ |
2202 | if (GET_CODE (X) == PLUS) \ | |
2203 | { \ | |
2204 | rtx xop0 = XEXP (X, 0); \ | |
2205 | rtx xop1 = XEXP (X, 1); \ | |
2206 | \ | |
11c1a207 | 2207 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 2208 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 2209 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c | 2210 | xop1 = force_reg (SImode, xop1); \ |
f1008e52 RE |
2211 | if (ARM_BASE_REGISTER_RTX_P (xop0) \ |
2212 | && GET_CODE (xop1) == CONST_INT) \ | |
3967692c RE |
2213 | { \ |
2214 | HOST_WIDE_INT n, low_n; \ | |
2215 | rtx base_reg, val; \ | |
2216 | n = INTVAL (xop1); \ | |
2217 | \ | |
11c1a207 | 2218 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
2219 | { \ |
2220 | low_n = n & 0x0f; \ | |
2221 | n &= ~0x0f; \ | |
2222 | if (low_n > 4) \ | |
2223 | { \ | |
2224 | n += 16; \ | |
2225 | low_n -= 16; \ | |
2226 | } \ | |
2227 | } \ | |
2228 | else \ | |
2229 | { \ | |
2230 | low_n = ((MODE) == TImode ? 0 \ | |
2231 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
2232 | n -= low_n; \ | |
2233 | } \ | |
2234 | base_reg = gen_reg_rtx (SImode); \ | |
43cffd11 RE |
2235 | val = force_operand (gen_rtx_PLUS (SImode, xop0, \ |
2236 | GEN_INT (n)), NULL_RTX); \ | |
3967692c RE |
2237 | emit_move_insn (base_reg, val); \ |
2238 | (X) = (low_n == 0 ? base_reg \ | |
43cffd11 | 2239 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ |
3967692c RE |
2240 | } \ |
2241 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
43cffd11 | 2242 | (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ |
3967692c RE |
2243 | } \ |
2244 | else if (GET_CODE (X) == MINUS) \ | |
2245 | { \ | |
2246 | rtx xop0 = XEXP (X, 0); \ | |
2247 | rtx xop1 = XEXP (X, 1); \ | |
2248 | \ | |
2249 | if (CONSTANT_P (xop0)) \ | |
2250 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 2251 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
2252 | xop1 = force_reg (SImode, xop1); \ |
2253 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
43cffd11 | 2254 | (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ |
3967692c | 2255 | } \ |
7a801826 RE |
2256 | if (flag_pic) \ |
2257 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
2258 | if (memory_address_p (MODE, X)) \ |
2259 | goto WIN; \ | |
35d965d5 RS |
2260 | } |
2261 | ||
d5b7b3ae RE |
2262 | #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
2263 | if (flag_pic) \ | |
2264 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); | |
2265 | ||
2266 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2267 | if (TARGET_ARM) \ | |
2268 | ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ | |
2269 | else \ | |
2270 | THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) | |
2271 | ||
35d965d5 RS |
2272 | /* Go to LABEL if ADDR (a legitimate address expression) |
2273 | has an effect that depends on the machine mode it is used for. */ | |
d5b7b3ae | 2274 | #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
35d965d5 | 2275 | { \ |
d5b7b3ae RE |
2276 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ |
2277 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
35d965d5 RS |
2278 | goto LABEL; \ |
2279 | } | |
d5b7b3ae RE |
2280 | |
2281 | /* Nothing helpful to do for the Thumb */ | |
2282 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2283 | if (TARGET_ARM) \ | |
2284 | ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) | |
35d965d5 | 2285 | \f |
d5b7b3ae | 2286 | |
35d965d5 RS |
2287 | /* Specify the machine mode that this machine uses |
2288 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2289 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2290 | |
18543a22 ILT |
2291 | /* Define as C expression which evaluates to nonzero if the tablejump |
2292 | instruction expects the table to contain offsets from the address of the | |
2293 | table. | |
2294 | Do not define this if the table should contain absolute addresses. */ | |
2295 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 | 2296 | |
ff9940b0 RE |
2297 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2298 | unsigned is probably best, but may break some code. */ | |
2299 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2300 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2301 | #endif |
2302 | ||
2303 | /* Don't cse the address of the function being compiled. */ | |
2304 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
2305 | ||
2306 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
2307 | in one reasonably fast instruction. */ |
2308 | #define MOVE_MAX 4 | |
35d965d5 | 2309 | |
d19fb8e3 NC |
2310 | #undef MOVE_RATIO |
2311 | #define MOVE_RATIO (arm_is_xscale ? 4 : 2) | |
2312 | ||
ff9940b0 RE |
2313 | /* Define if operations between registers always perform the operation |
2314 | on the full register even if a narrower mode is specified. */ | |
2315 | #define WORD_REGISTER_OPERATIONS | |
2316 | ||
2317 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2318 | will either zero-extend or sign-extend. The value of this macro should | |
2319 | be the code that says which one of the two operations is implicitly | |
2320 | done, NIL if none. */ | |
9c872872 | 2321 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2322 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2323 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
2324 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) | |
ff9940b0 | 2325 | |
35d965d5 RS |
2326 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2327 | #define SLOW_BYTE_ACCESS 0 | |
2328 | ||
d5b7b3ae RE |
2329 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
2330 | ||
35d965d5 RS |
2331 | /* Immediate shift counts are truncated by the output routines (or was it |
2332 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2333 | that the native compiler puts too large (> 32) immediate shift counts | |
2334 | into a register and shifts by the register, letting the ARM decide what | |
2335 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2336 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2337 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2338 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
2339 | rotates is modulo 32 used. */ | |
2340 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 2341 | |
35d965d5 | 2342 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2343 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2344 | |
2345 | /* Calling from registers is a massive pain. */ | |
2346 | #define NO_FUNCTION_CSE 1 | |
2347 | ||
2348 | /* Chars and shorts should be passed as ints. */ | |
2349 | #define PROMOTE_PROTOTYPES 1 | |
2350 | ||
35d965d5 RS |
2351 | /* The machine modes of pointers and functions */ |
2352 | #define Pmode SImode | |
2353 | #define FUNCTION_MODE Pmode | |
2354 | ||
d5b7b3ae RE |
2355 | #define ARM_FRAME_RTX(X) \ |
2356 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2357 | || (X) == arg_pointer_rtx) |
2358 | ||
62b10bbc | 2359 | #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ |
d5b7b3ae | 2360 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
2361 | |
2362 | /* Moves to and from memory are quite expensive */ | |
d5b7b3ae RE |
2363 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
2364 | (TARGET_ARM ? 10 : \ | |
2365 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
2366 | * (CLASS == LO_REGS ? 1 : 2))) | |
2367 | ||
3967692c | 2368 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 2369 | the same for practically all of them. So we weight the different types |
3967692c RE |
2370 | of address here in the order (most pref first): |
2371 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
d5b7b3ae | 2372 | #define ARM_ADDRESS_COST(X) \ |
3967692c RE |
2373 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ |
2374 | || GET_CODE (X) == SYMBOL_REF) \ | |
2375 | ? 0 \ | |
2376 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
2377 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
2378 | ? 10 \ | |
2379 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
2380 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
2381 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
2382 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
2383 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
2384 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
2385 | ? 1 : 0)) \ | |
2386 | : 4))))) | |
d5b7b3ae RE |
2387 | |
2388 | #define THUMB_ADDRESS_COST(X) \ | |
2389 | ((GET_CODE (X) == REG \ | |
2390 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
2391 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
2392 | ? 1 : 2) | |
2393 | ||
2394 | #define ADDRESS_COST(X) \ | |
2395 | (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) | |
2396 | ||
ff9940b0 RE |
2397 | /* Try to generate sequences that don't involve branches, we can then use |
2398 | conditional instructions */ | |
d5b7b3ae RE |
2399 | #define BRANCH_COST \ |
2400 | (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) | |
7a801826 RE |
2401 | \f |
2402 | /* Position Independent Code. */ | |
2403 | /* We decide which register to use based on the compilation options and | |
2404 | the assembler in use; this is more general than the APCS restriction of | |
2405 | using sb (r9) all the time. */ | |
2406 | extern int arm_pic_register; | |
2407 | ||
ed0e6530 PB |
2408 | /* Used when parsing command line option -mpic-register=. */ |
2409 | extern const char * arm_pic_register_string; | |
2410 | ||
7a801826 RE |
2411 | /* The register number of the register used to address a table of static |
2412 | data addresses in memory. */ | |
2413 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2414 | ||
c1163e75 | 2415 | #define FINALIZE_PIC arm_finalize_pic (1) |
7a801826 | 2416 | |
f5a1b0d2 NC |
2417 | /* We can't directly access anything that contains a symbol, |
2418 | nor can we indirect via the constant pool. */ | |
82e9d970 | 2419 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2420 | (!(symbol_mentioned_p (X) \ |
2421 | || label_mentioned_p (X) \ | |
2422 | || (GET_CODE (X) == SYMBOL_REF \ | |
2423 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2424 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
2425 | || label_mentioned_p (get_pool_constant (X)))))) | |
2426 | ||
13bd191d PB |
2427 | /* We need to know when we are making a constant pool; this determines |
2428 | whether data needs to be in the GOT or can be referenced via a GOT | |
2429 | offset. */ | |
2430 | extern int making_const_table; | |
82e9d970 | 2431 | \f |
c27ba912 | 2432 | /* Handle pragmas for compatibility with Intel's compilers. */ |
8b97c5f8 ZW |
2433 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ |
2434 | cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ | |
2435 | cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ | |
2436 | cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ | |
2437 | } while (0) | |
2438 | ||
ff9940b0 RE |
2439 | /* Condition code information. */ |
2440 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
a5381466 | 2441 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2442 | |
2443 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2444 | |
008cf58a RE |
2445 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
2446 | ||
62b10bbc NC |
2447 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2448 | do \ | |
2449 | { \ | |
2450 | if (GET_CODE (OP1) == CONST_INT \ | |
2451 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2452 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2453 | { \ | |
2454 | rtx const_op = OP1; \ | |
2455 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
2456 | OP1 = const_op; \ | |
2457 | } \ | |
2458 | } \ | |
2459 | while (0) | |
62dd06ea | 2460 | |
ff9940b0 RE |
2461 | #define STORE_FLAG_VALUE 1 |
2462 | ||
35d965d5 | 2463 | \f |
35d965d5 | 2464 | |
11c1a207 RE |
2465 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
2466 | load addresses a limited distance around the pc. We do some | |
2467 | special munging to move the constant pool values to the correct | |
2468 | point in the code. */ | |
d5b7b3ae RE |
2469 | #define MACHINE_DEPENDENT_REORG(INSN) \ |
2470 | arm_reorg (INSN); \ | |
2471 | ||
2472 | #undef ASM_APP_OFF | |
2473 | #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") | |
35d965d5 | 2474 | |
35d965d5 | 2475 | /* Output an internal label definition. */ |
b355a481 | 2476 | #ifndef ASM_OUTPUT_INTERNAL_LABEL |
62b10bbc NC |
2477 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ |
2478 | do \ | |
2479 | { \ | |
2a5307b1 | 2480 | char * s = (char *) alloca (40 + strlen (PREFIX)); \ |
62b10bbc NC |
2481 | \ |
2482 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ | |
2483 | && !strcmp (PREFIX, "L")) \ | |
18543a22 | 2484 | { \ |
62b10bbc | 2485 | arm_ccfsm_state = 0; \ |
18543a22 ILT |
2486 | arm_target_insn = NULL; \ |
2487 | } \ | |
62b10bbc NC |
2488 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
2489 | ASM_OUTPUT_LABEL (STREAM, s); \ | |
2490 | } \ | |
2491 | while (0) | |
b355a481 | 2492 | #endif |
2a5307b1 | 2493 | |
35d965d5 | 2494 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae RE |
2495 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
2496 | if (TARGET_ARM) \ | |
2497 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2498 | STACK_POINTER_REGNUM, REGNO); \ | |
2499 | else \ | |
2500 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) | |
2501 | ||
2502 | ||
2503 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
2504 | if (TARGET_ARM) \ | |
2505 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2506 | STACK_POINTER_REGNUM, REGNO); \ | |
2507 | else \ | |
2508 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) | |
2509 | ||
2510 | /* This is how to output a label which precedes a jumptable. Since | |
2511 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
be393ecf | 2512 | #undef ASM_OUTPUT_CASE_LABEL |
d5b7b3ae RE |
2513 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ |
2514 | do \ | |
2515 | { \ | |
2516 | if (TARGET_THUMB) \ | |
2517 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2518 | ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ | |
2519 | } \ | |
2520 | while (0) | |
35d965d5 | 2521 | |
6cfc7210 NC |
2522 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2523 | do \ | |
2524 | { \ | |
d5b7b3ae RE |
2525 | if (TARGET_THUMB) \ |
2526 | { \ | |
2527 | if (is_called_in_ARM_mode (DECL)) \ | |
2528 | fprintf (STREAM, "\t.code 32\n") ; \ | |
2529 | else \ | |
2530 | fprintf (STREAM, "\t.thumb_func\n") ; \ | |
2531 | } \ | |
6cfc7210 | 2532 | if (TARGET_POKE_FUNCTION_NAME) \ |
6354dc9b | 2533 | arm_poke_function_name (STREAM, (char *) NAME); \ |
6cfc7210 NC |
2534 | } \ |
2535 | while (0) | |
35d965d5 | 2536 | |
d5b7b3ae RE |
2537 | /* For aliases of functions we use .thumb_set instead. */ |
2538 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2539 | do \ | |
2540 | { \ | |
91ea4f8d KG |
2541 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2542 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2543 | \ |
2544 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2545 | { \ | |
2546 | fprintf (FILE, "\t.thumb_set "); \ | |
2547 | assemble_name (FILE, LABEL1); \ | |
2548 | fprintf (FILE, ","); \ | |
2549 | assemble_name (FILE, LABEL2); \ | |
2550 | fprintf (FILE, "\n"); \ | |
2551 | } \ | |
2552 | else \ | |
2553 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2554 | } \ | |
2555 | while (0) | |
2556 | ||
fdc2d3b0 NC |
2557 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2558 | /* To support -falign-* switches we need to use .p2align so | |
2559 | that alignment directives in code sections will be padded | |
2560 | with no-op instructions, rather than zeroes. */ | |
2561 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ | |
2562 | if ((LOG) != 0) \ | |
2563 | { \ | |
2564 | if ((MAX_SKIP) == 0) \ | |
2565 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2566 | else \ | |
2567 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
2568 | (LOG), (MAX_SKIP)); \ | |
2569 | } | |
2570 | #endif | |
35d965d5 | 2571 | \f |
35d965d5 RS |
2572 | /* Only perform branch elimination (by making instructions conditional) if |
2573 | we're optimising. Otherwise it's of no use anyway. */ | |
d5b7b3ae RE |
2574 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2575 | if (TARGET_ARM && optimize) \ | |
2576 | arm_final_prescan_insn (INSN); \ | |
2577 | else if (TARGET_THUMB) \ | |
2578 | thumb_final_prescan_insn (INSN) | |
35d965d5 | 2579 | |
7bc7696c | 2580 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
d5b7b3ae RE |
2581 | (CODE == '@' || CODE == '|' \ |
2582 | || (TARGET_ARM && (CODE == '?')) \ | |
2583 | || (TARGET_THUMB && (CODE == '_'))) | |
6cfc7210 | 2584 | |
7bc7696c | 2585 | /* Output an operand of an instruction. */ |
35d965d5 | 2586 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2587 | arm_print_operand (STREAM, X, CODE) |
2588 | ||
7b8b8ade NC |
2589 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2590 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2591 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2592 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2593 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2594 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2595 | : 0)))) |
35d965d5 RS |
2596 | |
2597 | /* Output the address of an operand. */ | |
d5b7b3ae RE |
2598 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2599 | { \ | |
2600 | int is_minus = GET_CODE (X) == MINUS; \ | |
2601 | \ | |
2602 | if (GET_CODE (X) == REG) \ | |
2603 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2604 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2605 | { \ | |
2606 | rtx base = XEXP (X, 0); \ | |
2607 | rtx index = XEXP (X, 1); \ | |
2608 | HOST_WIDE_INT offset = 0; \ | |
2609 | if (GET_CODE (base) != REG) \ | |
2610 | { \ | |
2611 | /* Ensure that BASE is a register */ \ | |
2612 | /* (one of them must be). */ \ | |
2613 | rtx temp = base; \ | |
2614 | base = index; \ | |
2615 | index = temp; \ | |
2616 | } \ | |
2617 | switch (GET_CODE (index)) \ | |
2618 | { \ | |
2619 | case CONST_INT: \ | |
2620 | offset = INTVAL (index); \ | |
2621 | if (is_minus) \ | |
2622 | offset = -offset; \ | |
2623 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2624 | REGNO (base), offset); \ | |
2625 | break; \ | |
2626 | \ | |
2627 | case REG: \ | |
2628 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2629 | REGNO (base), is_minus ? "-" : "", \ | |
2630 | REGNO (index)); \ | |
2631 | break; \ | |
2632 | \ | |
2633 | case MULT: \ | |
2634 | case ASHIFTRT: \ | |
2635 | case LSHIFTRT: \ | |
2636 | case ASHIFT: \ | |
2637 | case ROTATERT: \ | |
2638 | { \ | |
2639 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2640 | REGNO (base), is_minus ? "-" : "", \ | |
2641 | REGNO (XEXP (index, 0))); \ | |
2642 | arm_print_operand (STREAM, index, 'S'); \ | |
2643 | fputs ("]", STREAM); \ | |
2644 | break; \ | |
2645 | } \ | |
2646 | \ | |
2647 | default: \ | |
2648 | abort(); \ | |
2649 | } \ | |
2650 | } \ | |
2651 | else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ | |
2652 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ | |
2653 | { \ | |
2654 | extern int output_memory_reference_mode; \ | |
2655 | \ | |
2656 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2657 | abort (); \ | |
2658 | \ | |
2659 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2660 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2661 | REGNO (XEXP (X, 0)), \ | |
2662 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2663 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2664 | else \ | |
2665 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2666 | REGNO (XEXP (X, 0)), \ | |
2667 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2668 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2669 | } \ | |
2670 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2671 | } |
62dd06ea | 2672 | |
d5b7b3ae RE |
2673 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2674 | { \ | |
2675 | if (GET_CODE (X) == REG) \ | |
2676 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2677 | else if (GET_CODE (X) == POST_INC) \ | |
2678 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2679 | else if (GET_CODE (X) == PLUS) \ | |
2680 | { \ | |
2681 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2682 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2683 | REGNO (XEXP (X, 0)), \ | |
2684 | (int) INTVAL (XEXP (X, 1))); \ | |
2685 | else \ | |
2686 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2687 | REGNO (XEXP (X, 0)), \ | |
2688 | REGNO (XEXP (X, 1))); \ | |
2689 | } \ | |
2690 | else \ | |
2691 | output_addr_const (STREAM, X); \ | |
2692 | } | |
2693 | ||
2694 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2695 | if (TARGET_ARM) \ | |
2696 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ | |
2697 | else \ | |
2698 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
2699 | ||
62dd06ea RE |
2700 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2701 | Used for C++ multiple inheritance. */ | |
62b10bbc NC |
2702 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2703 | do \ | |
2704 | { \ | |
2705 | int mi_delta = (DELTA); \ | |
27c38fbe | 2706 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \ |
62b10bbc NC |
2707 | int shift = 0; \ |
2708 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ | |
2709 | ? 1 : 0); \ | |
b1801c02 NC |
2710 | if (mi_delta < 0) \ |
2711 | mi_delta = - mi_delta; \ | |
62b10bbc NC |
2712 | while (mi_delta != 0) \ |
2713 | { \ | |
b1801c02 | 2714 | if ((mi_delta & (3 << shift)) == 0) \ |
62b10bbc NC |
2715 | shift += 2; \ |
2716 | else \ | |
2717 | { \ | |
dd18ae56 NC |
2718 | asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \ |
2719 | mi_op, this_regno, this_regno, \ | |
6cfc7210 | 2720 | mi_delta & (0xff << shift)); \ |
62b10bbc NC |
2721 | mi_delta &= ~(0xff << shift); \ |
2722 | shift += 8; \ | |
2723 | } \ | |
2724 | } \ | |
2725 | fputs ("\tb\t", FILE); \ | |
2726 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
dd18ae56 | 2727 | if (NEED_PLT_RELOC) \ |
62b10bbc NC |
2728 | fputs ("(PLT)", FILE); \ |
2729 | fputc ('\n', FILE); \ | |
2730 | } \ | |
2731 | while (0) | |
39950dff | 2732 | |
6a5d7526 MS |
2733 | /* A C expression whose value is RTL representing the value of the return |
2734 | address for the frame COUNT steps up from the current frame. */ | |
2735 | ||
d5b7b3ae RE |
2736 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2737 | arm_return_addr (COUNT, FRAME) | |
2738 | ||
2739 | /* Mask of the bits in the PC that contain the real return address | |
2740 | when running in 26-bit mode. */ | |
2741 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2742 | |
2c849145 JM |
2743 | /* Pick up the return address upon entry to a procedure. Used for |
2744 | dwarf2 unwind information. This also enables the table driven | |
2745 | mechanism. */ | |
2c849145 JM |
2746 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2747 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2748 | ||
39950dff MS |
2749 | /* Used to mask out junk bits from the return address, such as |
2750 | processor state, interrupt status, condition codes and the like. */ | |
2751 | #define MASK_RETURN_ADDR \ | |
2752 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2753 | in 26 bit mode, the condition codes must be masked out of the \ | |
2754 | return address. This does not apply to ARM6 and later processors \ | |
2755 | when running in 32 bit mode. */ \ | |
fcd53748 JT |
2756 | ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ |
2757 | : (arm_arch4 || TARGET_THUMB) ? \ | |
2758 | (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
2759 | : arm_gen_return_addr_mask ()) | |
d5b7b3ae RE |
2760 | |
2761 | \f | |
2762 | /* Define the codes that are matched by predicates in arm.c */ | |
2763 | #define PREDICATE_CODES \ | |
2764 | {"s_register_operand", {SUBREG, REG}}, \ | |
b15bca31 | 2765 | {"arm_hard_register_operand", {REG}}, \ |
d5b7b3ae RE |
2766 | {"f_register_operand", {SUBREG, REG}}, \ |
2767 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2768 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2769 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2770 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
2771 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
2772 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ | |
2773 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
2774 | {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ | |
2775 | {"offsettable_memory_operand", {MEM}}, \ | |
2776 | {"bad_signed_byte_operand", {MEM}}, \ | |
2777 | {"alignable_memory_operand", {MEM}}, \ | |
2778 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ | |
2779 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
2780 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ | |
2781 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ | |
2782 | {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ | |
2783 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ | |
2784 | {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ | |
2785 | {"load_multiple_operation", {PARALLEL}}, \ | |
2786 | {"store_multiple_operation", {PARALLEL}}, \ | |
2787 | {"equality_operator", {EQ, NE}}, \ | |
e45b72c4 RE |
2788 | {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ |
2789 | LTU, UNORDERED, ORDERED, UNLT, UNLE, \ | |
2790 | UNGE, UNGT}}, \ | |
d5b7b3ae RE |
2791 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2792 | {"const_shift_operand", {CONST_INT}}, \ | |
2793 | {"multi_register_push", {PARALLEL}}, \ | |
2794 | {"cc_register", {REG}}, \ | |
2795 | {"logical_binary_operator", {AND, IOR, XOR}}, \ | |
2796 | {"dominant_cc_register", {REG}}, | |
71791e16 | 2797 | |
ad027eae RE |
2798 | /* Define this if you have special predicates that know special things |
2799 | about modes. Genrecog will warn about certain forms of | |
2800 | match_operand without a mode; if the operand predicate is listed in | |
2801 | SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ | |
2802 | #define SPECIAL_MODE_PREDICATES \ | |
2803 | "cc_register", "dominant_cc_register", | |
2804 | ||
d19fb8e3 NC |
2805 | enum arm_builtins |
2806 | { | |
2807 | ARM_BUILTIN_CLZ, | |
d19fb8e3 NC |
2808 | ARM_BUILTIN_MAX |
2809 | }; | |
88657302 | 2810 | #endif /* ! GCC_ARM_H */ |