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s390.md ("prologue_tpf", [...]): Alter trace hooks calls to improve performance.
[thirdparty/gcc.git] / gcc / config / arm / arm.h
CommitLineData
f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
b12a00f1 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245
NC		 21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
35fd3193 29/* The architecture define. */
78011587
PB		 30extern char arm_arch_name[];
31
e6471be6
NB		 32/* Target CPU builtins. */
33#define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
9b66ebb1
PB		 36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
61f0ccff 39 builtin_define ("__APCS_32__"); \
9b66ebb1 40 if (TARGET_THUMB) \
e6471be6
NB		 41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
e6471be6
NB		 58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
9b66ebb1 61 if (TARGET_VFP) \
b5b620a4
JT		 62 builtin_define ("__VFP_FP__"); \
63 \
e6471be6
NB		 64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
2ad4dcf9 66 if (arm_cpp_interwork) \
e6471be6
NB		 67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
78011587
PB		 71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 81 } while (0)
82
9b66ebb1
PB		 83/* The various ARM cores. */
84enum processor_type
85{
d98a72fd
RE		 86#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
9b66ebb1
PB		 88#include "arm-cores.def"
89#undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92};
93
78011587
PB		 94enum target_cpus
95{
d98a72fd
RE		 96#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
78011587
PB		 98#include "arm-cores.def"
99#undef ARM_CORE
100 TARGET_CPU_generic
101};
102
9b66ebb1
PB		 103/* The processor for which instructions should be scheduled. */
104extern enum processor_type arm_tune;
105
d5b7b3ae 106typedef enum arm_cond_code
89c7ca52
RE		 107{
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 110}
111arm_cc;
6cfc7210 112
d5b7b3ae 113extern arm_cc arm_current_cc;
ff9940b0 114
d5b7b3ae 115#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 116
6cfc7210
NC		 117extern int arm_target_label;
118extern int arm_ccfsm_state;
e2500fed 119extern GTY(()) rtx arm_target_insn;
6cfc7210
NC		 120/* Run-time compilation parameters selecting different hardware subsets. */
121extern int target_flags;
9b66ebb1
PB		 122/* The floating point mode. */
123extern const char *target_fpu_name;
59b9a953 124/* For backwards compatibility. */
9b66ebb1
PB		 125extern const char *target_fpe_name;
126/* Whether to use floating point hardware. */
127extern const char *target_float_abi_name;
3d8532aa
PB		 128/* For -m{soft,hard}-float. */
129extern const char *target_float_switch;
5848830f
PB		 130/* Which ABI to use. */
131extern const char *target_abi_name;
d5b7b3ae 132/* Define the information needed to generate branch insns. This is
e2500fed
GK		 133 stored from the compare operation. */
134extern GTY(()) rtx arm_compare_op0;
135extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 136/* The label of the current constant pool. */
e2500fed 137extern rtx pool_vector_label;
d5b7b3ae 138/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 139 is not needed. */
d5b7b3ae 140extern int return_used_this_function;
e2500fed
GK		 141/* Used to produce AOF syntax assembler. */
142extern GTY(()) rtx aof_pic_label;
35d965d5 143\f
d6b4baa4 144/* Just in case configure has failed to define anything. */
7a801826
RE		 145#ifndef TARGET_CPU_DEFAULT
146#define TARGET_CPU_DEFAULT TARGET_CPU_generic
147#endif
148
7a801826 149
5742588d 150#undef CPP_SPEC
78011587 151#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 152%{msoft-float:%{mhard-float: \
153 %e-msoft-float and -mhard_float may not be used together}} \
154%{mbig-endian:%{mlittle-endian: \
155 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 156
be393ecf 157#ifndef CC1_SPEC
dfa08768 158#define CC1_SPEC ""
be393ecf 159#endif
7a801826
RE		 160
161/* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
164
165 Each subgrouping contains a string constant, that defines the
4f448245 166 specification name, and a string constant that used by the GCC driver
7a801826
RE		 167 program.
168
169 Do not define this macro if it does not need to do anything. */
170#define EXTRA_SPECS \
38fc909b 171 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 172 SUBTARGET_EXTRA_SPECS
173
914a3b8c 174#ifndef SUBTARGET_EXTRA_SPECS
7a801826 175#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 176#endif
177
6cfc7210 178#ifndef SUBTARGET_CPP_SPEC
38fc909b 179#define SUBTARGET_CPP_SPEC ""
6cfc7210 180#endif
35d965d5
RS		 181\f
182/* Run-time Target Specification. */
ff9940b0 183#ifndef TARGET_VERSION
6cfc7210 184#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 185#endif
35d965d5 186
35d965d5
RS		 187/* Nonzero if the function prologue (and epilogue) should obey
188 the ARM Procedure Call Standard. */
6cfc7210 189#define ARM_FLAG_APCS_FRAME (1 << 0)
35d965d5
RS		 190
191/* Nonzero if the function prologue should output the function name to enable
192 the post mortem debugger to print a backtrace (very useful on RISCOS,
11c1a207
RE		 193 unused on RISCiX). Specifying this flag also enables
194 -fno-omit-frame-pointer.
35d965d5 195 XXX Must still be implemented in the prologue. */
6cfc7210 196#define ARM_FLAG_POKE (1 << 1)
35d965d5
RS		 197
198/* Nonzero if floating point instructions are emulated by the FPE, in which
199 case instruction scheduling becomes very uninteresting. */
6cfc7210 200#define ARM_FLAG_FPE (1 << 2)
35d965d5 201
61f0ccff 202/* FLAG 0x0008 now spare (used to be apcs-32 selection). */
dfa08768 203
11c1a207
RE		 204/* Nonzero if stack checking should be performed on entry to each function
205 which allocates temporary variables on the stack. */
6cfc7210 206#define ARM_FLAG_APCS_STACK (1 << 4)
11c1a207
RE		 207
208/* Nonzero if floating point parameters should be passed to functions in
209 floating point registers. */
6cfc7210 210#define ARM_FLAG_APCS_FLOAT (1 << 5)
11c1a207
RE		 211
212/* Nonzero if re-entrant, position independent code should be generated.
213 This is equivalent to -fpic. */
6cfc7210 214#define ARM_FLAG_APCS_REENT (1 << 6)
11c1a207 215
61f0ccff 216 /* FLAG 0x0080 now spare (used to be alignment traps). */
3d8532aa 217 /* FLAG (1 << 8) is now spare (used to be soft-float). */
11c1a207
RE		 218
219/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
6cfc7210 220#define ARM_FLAG_BIG_END (1 << 9)
11c1a207
RE		 221
222/* Nonzero if we should compile for Thumb interworking. */
6cfc7210 223#define ARM_FLAG_INTERWORK (1 << 10)
11c1a207 224
ddee6aba
RE		 225/* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
6cfc7210 227#define ARM_FLAG_LITTLE_WORDS (1 << 11)
ddee6aba 228
f5a1b0d2 229/* Nonzero if we need to protect the prolog from scheduling */
6cfc7210 230#define ARM_FLAG_NO_SCHED_PRO (1 << 12)
f5a1b0d2 231
f676971a 232/* Nonzero if a call to abort should be generated if a noreturn
dd18ae56 233 function tries to return. */
6cfc7210 234#define ARM_FLAG_ABORT_NORETURN (1 << 13)
c11145f6 235
d6b4baa4 236/* Nonzero if function prologues should not load the PIC register. */
dd18ae56 237#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
ed0e6530 238
b020fd92
NC		 239/* Nonzero if all call instructions should be indirect. */
240#define ARM_FLAG_LONG_CALLS (1 << 15)
f676971a 241
d5b7b3ae
RE		 242/* Nonzero means that the target ISA is the THUMB, not the ARM. */
243#define ARM_FLAG_THUMB (1 << 16)
244
245/* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247#define THUMB_FLAG_BACKTRACE (1 << 17)
b020fd92 248
d5b7b3ae
RE		 249/* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253/* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257/* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
9b6b54e2 261/* Fix invalid Cirrus instruction combinations by inserting NOPs. */
5848830f 262#define CIRRUS_FIX_INVALID_INSNS (1 << 21)
9b6b54e2 263
d5b7b3ae 264#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
11c1a207
RE		 265#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266#define TARGET_FPE (target_flags & ARM_FLAG_FPE)
11c1a207
RE		 267#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
9b66ebb1 270#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 271/* Use hardware floating point instructions. */
272#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273/* Use hardware floating point calling convention. */
274#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 275#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef
NC		 278#define TARGET_IWMMXT (arm_arch_iwmmxt)
279#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
5848830f 280#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
11c1a207 281#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
6cfc7210 282#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
ddee6aba 283#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
f5a1b0d2 284#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
dd18ae56 285#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
ed0e6530 286#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
b020fd92 287#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
d5b7b3ae
RE		 288#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289#define TARGET_ARM (! TARGET_THUMB)
290#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293#define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
9b6b54e2 296#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
fdd695fd 297#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 298#define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 300
b3f8d95d
MM		 301/* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
305#ifndef TARGET_BPABI
306#define TARGET_BPABI false
f676971a 307#endif
b3f8d95d 308
c7bdf0a6 309/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
3ada8e17
DE		 310#ifndef SUBTARGET_SWITCHES
311#define SUBTARGET_SWITCHES
ff9940b0
RE		 312#endif
313
047142d3
PT		 314#define TARGET_SWITCHES \
315{ \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
047142d3
PT		 324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
047142d3
PT		 332 {"big-endian", ARM_FLAG_BIG_END, \
333 N_("Assume target CPU is configured as big endian") }, \
334 {"little-endian", -ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as little endian") }, \
336 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
337 N_("Assume big endian bytes, little endian words") }, \
338 {"thumb-interwork", ARM_FLAG_INTERWORK, \
b605cfa8 339 N_("Support calls between Thumb and ARM instruction sets") }, \
047142d3
PT		 340 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
341 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
342 N_("Generate a call to abort if a noreturn function returns")}, \
343 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
b605cfa8 344 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
047142d3 345 N_("Do not move instructions into a function's prologue") }, \
b605cfa8 346 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
047142d3
PT		 347 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
348 N_("Do not load the PIC register in function prologues") }, \
349 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
350 {"long-calls", ARM_FLAG_LONG_CALLS, \
351 N_("Generate call insns as indirect calls, if necessary") }, \
352 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
353 {"thumb", ARM_FLAG_THUMB, \
354 N_("Compile for the Thumb not the ARM") }, \
355 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
356 {"arm", -ARM_FLAG_THUMB, "" }, \
357 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
358 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
359 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
360 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
361 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
362 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
363 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
364 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
365 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
366 "" }, \
367 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
368 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
369 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
370 "" }, \
9b6b54e2
NC		 371 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
372 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
373 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
047142d3
PT		 375 SUBTARGET_SWITCHES \
376 {"", TARGET_DEFAULT, "" } \
35d965d5
RS		 377}
378
9b66ebb1
PB		 379#define TARGET_OPTIONS \
380{ \
381 {"cpu=", & arm_select[0].string, \
382 N_("Specify the name of the target CPU"), 0}, \
383 {"arch=", & arm_select[1].string, \
384 N_("Specify the name of the target architecture"), 0}, \
385 {"tune=", & arm_select[2].string, "", 0}, \
386 {"fpe=", & target_fpe_name, "", 0}, \
387 {"fp=", & target_fpe_name, "", 0}, \
388 {"fpu=", & target_fpu_name, \
389 N_("Specify the name of the target floating point hardware/format"), 0}, \
390 {"float-abi=", & target_float_abi_name, \
391 N_("Specify if floating point hardware should be used"), 0}, \
392 {"structure-size-boundary=", & structure_size_string, \
393 N_("Specify the minimum bit alignment of structures"), 0}, \
394 {"pic-register=", & arm_pic_register_string, \
5848830f 395 N_("Specify the register to be used for PIC addressing"), 0}, \
3d8532aa
PB		 396 {"abi=", &target_abi_name, N_("Specify an ABI"), 0}, \
397 {"soft-float", &target_float_switch, \
712ecf4d 398 N_("Alias for -mfloat-abi=soft"), "s"}, \
3d8532aa 399 {"hard-float", &target_float_switch, \
712ecf4d 400 N_("Alias for -mfloat-abi=hard"), "h"} \
11c1a207 401}
ff9940b0 402
7816bea0
DJ		 403/* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
406 by --with-arch.
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
408 by -march).
9b66ebb1
PB		 409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
410 specified.
5848830f
PB		 411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 413#define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 417 {"float", \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f
PB		 419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
7816bea0 421
62dd06ea
RE		 422struct arm_cpu_select
423{
f9cc092a
RE		 424 const char * string;
425 const char * name;
426 const struct processors * processors;
62dd06ea
RE		 427};
428
f5a1b0d2
NC		 429/* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
62dd06ea
RE		 432extern struct arm_cpu_select arm_select[];
433
9b66ebb1
PB		 434/* Which floating point model to use. */
435enum arm_fp_model
436{
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
439 ARM_FP_MODEL_FPA,
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
443 ARM_FP_MODEL_VFP
444};
445
446extern enum arm_fp_model arm_fp_model;
447
448/* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 450enum fputype
24f0c1b4 451{
9b66ebb1
PB		 452 /* No FP hardware. */
453 FPUTYPE_NONE,
29ad9694
RE		 454 /* Full FPA support. */
455 FPUTYPE_FPA,
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
457 FPUTYPE_FPA_EMU2,
458 /* Emulated FPA hardware, Issue 3 emulator. */
459 FPUTYPE_FPA_EMU3,
460 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 461 FPUTYPE_MAVERICK,
462 /* VFP. */
463 FPUTYPE_VFP
24f0c1b4
RE		 464};
465
466/* Recast the floating point class to be the floating point attribute. */
29ad9694 467#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 468
71791e16 469/* What type of floating point to tune for */
29ad9694 470extern enum fputype arm_fpu_tune;
24f0c1b4 471
71791e16 472/* What type of floating point instructions are available */
29ad9694 473extern enum fputype arm_fpu_arch;
71791e16 474
9b66ebb1
PB		 475enum float_abi_type
476{
477 ARM_FLOAT_ABI_SOFT,
478 ARM_FLOAT_ABI_SOFTFP,
479 ARM_FLOAT_ABI_HARD
480};
481
482extern enum float_abi_type arm_float_abi;
483
3d8532aa
PB		 484#ifndef TARGET_DEFAULT_FLOAT_ABI
485#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
486#endif
487
5848830f
PB		 488/* Which ABI to use. */
489enum arm_abi_type
490{
491 ARM_ABI_APCS,
492 ARM_ABI_ATPCS,
493 ARM_ABI_AAPCS,
494 ARM_ABI_IWMMXT
495};
496
497extern enum arm_abi_type arm_abi;
498
499#ifndef ARM_DEFAULT_ABI
500#define ARM_DEFAULT_ABI ARM_ABI_APCS
501#endif
502
9b66ebb1
PB		 503/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504extern int arm_arch3m;
11c1a207 505
9b66ebb1 506/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 507extern int arm_arch4;
508
68d560d4
RE		 509/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
510extern int arm_arch4t;
511
9b66ebb1 512/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 513extern int arm_arch5;
514
9b66ebb1 515/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 516extern int arm_arch5e;
517
9b66ebb1
PB		 518/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519extern int arm_arch6;
520
f5a1b0d2
NC		 521/* Nonzero if this chip can benefit from load scheduling. */
522extern int arm_ld_sched;
523
0616531f
RE		 524/* Nonzero if generating thumb code. */
525extern int thumb_code;
526
f5a1b0d2 527/* Nonzero if this chip is a StrongARM. */
abac3b49 528extern int arm_tune_strongarm;
f5a1b0d2 529
9b6b54e2 530/* Nonzero if this chip is a Cirrus variant. */
78011587 531extern int arm_arch_cirrus;
9b6b54e2 532
5a9335ef
NC		 533/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534extern int arm_arch_iwmmxt;
535
d19fb8e3 536/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 537extern int arm_arch_xscale;
538
abac3b49 539/* Nonzero if tuning for XScale. */
4b3c2e48 540extern int arm_tune_xscale;
d19fb8e3 541
abac3b49
RE		 542/* Nonzero if tuning for stores via the write buffer. */
543extern int arm_tune_wbuf;
f5a1b0d2 544
2ad4dcf9 545/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 546 preprocessor.
2ad4dcf9
RE		 547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550extern int arm_cpp_interwork;
551
2ce9c1b9 552#ifndef TARGET_DEFAULT
d5b7b3ae 553#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
2ce9c1b9 554#endif
35d965d5 555
11c1a207
RE		 556/* The frame pointer register used in gcc has nothing to do with debugging;
557 that is controlled by the APCS-FRAME option. */
d5b7b3ae 558#define CAN_DEBUG_WITHOUT_FP
35d965d5 559
11c1a207 560#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 561
562/* Nonzero if PIC code requires explicit qualifiers to generate
563 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 564 Subtargets can override these if required. */
565#ifndef NEED_GOT_RELOC
566#define NEED_GOT_RELOC 0
567#endif
568#ifndef NEED_PLT_RELOC
569#define NEED_PLT_RELOC 0
e2723c62 570#endif
84306176
PB		 571
572/* Nonzero if we need to refer to the GOT with a PC-relative
573 offset. In other words, generate
574
f676971a 575 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 576
577 rather than
578
579 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
580
f676971a 581 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 582 override this if required. */
583#ifndef GOT_PCREL
584#define GOT_PCREL 1
585#endif
35d965d5
RS		 586\f
587/* Target machine storage Layout. */
588
ff9940b0
RE		 589
590/* Define this macro if it is advisable to hold scalars in registers
591 in a wider mode than that declared by the program. In such cases,
592 the value is constrained to be within the bounds of the declared
593 type, but kept valid in the wider mode. The signedness of the
594 extension may differ from that of the type. */
595
596/* It is far faster to zero extend chars than to sign extend them */
597
6cfc7210 598#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 599 if (GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < 4) \
601 { \
602 if (MODE == QImode) \
603 UNSIGNEDP = 1; \
604 else if (MODE == HImode) \
61f0ccff 605 UNSIGNEDP = 1; \
2ce9c1b9 606 (MODE) = SImode; \
ff9940b0
RE		 607 }
608
d4453b7a 609#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
866af8a9
JB		 610 if ((GET_MODE_CLASS (MODE) == MODE_INT \
611 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
612 && GET_MODE_SIZE (MODE) < 4) \
613 (MODE) = SImode; \
d4453b7a 614
35d965d5
RS		 615/* Define this if most significant bit is lowest numbered
616 in instructions that operate on numbered bit-fields. */
617#define BITS_BIG_ENDIAN 0
618
f676971a 619/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 620 Most ARM processors are run in little endian mode, so that is the default.
621 If you want to have it run-time selectable, change the definition in a
622 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 623#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 624
625/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 626 numbered.
627 This is always false, even when in big-endian mode. */
ddee6aba
RE		 628#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
629
630/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
631 on processor pre-defineds when compiling libgcc2.c. */
632#if defined(__ARMEB__) && !defined(__ARMWEL__)
633#define LIBGCC2_WORDS_BIG_ENDIAN 1
634#else
635#define LIBGCC2_WORDS_BIG_ENDIAN 0
636#endif
35d965d5 637
11c1a207 638/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 639 The rules are different based on whether or not we use FPA-format,
640 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 641#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 642
35d965d5
RS		 643#define UNITS_PER_WORD 4
644
5848830f 645/* True if natural alignment is used for doubleword types. */
b6685939
PB		 646#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
647
5848830f 648#define DOUBLEWORD_ALIGNMENT 64
35d965d5 649
5848830f 650#define PARM_BOUNDARY 32
5a9335ef 651
5848830f 652#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 653
5848830f
PB		 654#define PREFERRED_STACK_BOUNDARY \
655 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 656
35d965d5
RS		 657#define FUNCTION_BOUNDARY 32
658
92928d71
AO		 659/* The lowest bit is used to indicate Thumb-mode functions, so the
660 vbit must go into the delta field of pointers to member
661 functions. */
662#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
663
35d965d5
RS		 664#define EMPTY_FIELD_BOUNDARY 32
665
5848830f 666#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 667
27847754
NC		 668/* XXX Blah -- this macro is used directly by libobjc. Since it
669 supports no vector modes, cut out the complexity and fall back
670 on BIGGEST_FIELD_ALIGNMENT. */
671#ifdef IN_TARGET_LIBS
8fca31a2 672#define BIGGEST_FIELD_ALIGNMENT 64
27847754 673#endif
5a9335ef 674
ff9940b0 675/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 676#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 677
d19fb8e3 678#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f
PB		 679 ((TREE_CODE (EXP) == STRING_CST \
680 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
681 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 682
723ae7c1
NC		 683/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
684 value set in previous versions of this toolchain was 8, which produces more
685 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 686 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 687 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 688 0020D) page 2-20 says "Structures are aligned on word boundaries".
689 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 690#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
691extern int arm_structure_size_boundary;
723ae7c1 692
4912a07c 693/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 694 particular arm target wants to change the default value it should change
6bc82793 695 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 696 for an example of this. */
697#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
698#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 699#endif
2a5307b1 700
b355a481 701/* Used when parsing command line option -mstructure_size_boundary. */
f9cc092a 702extern const char * structure_size_string;
b4ac57ab 703
825dda42 704/* Nonzero if move instructions will actually fail to work
ff9940b0 705 when given unaligned data. */
35d965d5 706#define STRICT_ALIGNMENT 1
b6685939
PB		 707
708/* wchar_t is unsigned under the AAPCS. */
709#ifndef WCHAR_TYPE
710#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
711
712#define WCHAR_TYPE_SIZE BITS_PER_WORD
713#endif
714
715#ifndef SIZE_TYPE
716#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
717#endif
d81d0bdd
PB		 718
719/* AAPCS requires that structure alignment is affected by bitfields. */
720#ifndef PCC_BITFIELD_TYPE_MATTERS
721#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
722#endif
723
35d965d5
RS		 724\f
725/* Standard register usage. */
726
727/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
728 (S - saved over call).
729
730 r0 * argument word/integer result
731 r1-r3 argument word
732
733 r4-r8 S register variable
734 r9 S (rfp) register variable (real frame pointer)
f676971a 735
f5a1b0d2 736 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 737 r11 F S (fp) argument pointer
738 r12 (ip) temp workspace
739 r13 F S (sp) lower end of current stack frame
740 r14 (lr) link address/workspace
741 r15 F (pc) program counter
742
743 f0 floating point result
744 f1-f3 floating point scratch
745
746 f4-f7 S floating point variable
747
ff9940b0
RE		 748 cc This is NOT a real register, but is used internally
749 to represent things that use or set the condition
750 codes.
751 sfp This isn't either. It is used during rtl generation
752 since the offset between the frame pointer and the
753 auto's isn't known until after register allocation.
754 afp Nor this, we only need this because of non-local
755 goto. Without it fp appears to be used and the
756 elimination code won't get rid of sfp. It tracks
757 fp exactly at all times.
758
35d965d5
RS		 759 *: See CONDITIONAL_REGISTER_USAGE */
760
9b6b54e2
NC		 761/*
762 mvf0 Cirrus floating point result
763 mvf1-mvf3 Cirrus floating point scratch
764 mvf4-mvf15 S Cirrus floating point variable. */
765
9b66ebb1
PB		 766/* s0-s15 VFP scratch (aka d0-d7).
767 s16-s31 S VFP variable (aka d8-d15).
768 vfpcc Not a real register. Represents the VFP condition
769 code flags. */
770
ff9940b0
RE		 771/* The stack backtrace structure is as follows:
772 fp points to here: | save code pointer | [fp]
773 | return link value | [fp, #-4]
774 | return sp value | [fp, #-8]
775 | return fp value | [fp, #-12]
776 [| saved r10 value |]
777 [| saved r9 value |]
778 [| saved r8 value |]
779 [| saved r7 value |]
780 [| saved r6 value |]
781 [| saved r5 value |]
782 [| saved r4 value |]
783 [| saved r3 value |]
784 [| saved r2 value |]
785 [| saved r1 value |]
786 [| saved r0 value |]
787 [| saved f7 value |] three words
788 [| saved f6 value |] three words
789 [| saved f5 value |] three words
790 [| saved f4 value |] three words
791 r0-r3 are not normally saved in a C function. */
792
35d965d5
RS		 793/* 1 for registers that have pervasive standard uses
794 and are not available for the register allocator. */
9b66ebb1
PB		 795#define FIXED_REGISTERS \
796{ \
797 0,0,0,0,0,0,0,0, \
798 0,0,0,0,0,1,0,1, \
799 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 800 1,1,1, \
801 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1,1,1,1,1, \
805 1,1,1,1, \
806 1,1,1,1,1,1,1,1, \
807 1,1,1,1,1,1,1,1, \
808 1,1,1,1,1,1,1,1, \
809 1,1,1,1,1,1,1,1, \
810 1 \
35d965d5
RS		 811}
812
813/* 1 for registers not available across function calls.
814 These must include the FIXED_REGISTERS and also any
815 registers that can be used without being saved.
816 The latter must include the registers where values are returned
817 and the register where structure-value addresses are passed.
ff9940b0 818 Aside from that, you can include as many other registers as you like.
f676971a 819 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 820 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 821#define CALL_USED_REGISTERS \
822{ \
823 1,1,1,1,0,0,0,0, \
d5b7b3ae 824 0,0,0,0,1,1,1,1, \
ff9940b0 825 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 826 1,1,1, \
827 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 828 1,1,1,1,1,1,1,1, \
829 1,1,1,1,1,1,1,1, \
830 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 831 1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1,1,1,1,1,1,1,1, \
836 1 \
35d965d5
RS		 837}
838
6cc8c0b3
NC		 839#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
840#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
841#endif
842
d5b7b3ae
RE		 843#define CONDITIONAL_REGISTER_USAGE \
844{ \
4b02997f
NC		 845 int regno; \
846 \
9b66ebb1 847 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
d5b7b3ae 848 { \
9b66ebb1
PB		 849 for (regno = FIRST_FPA_REGNUM; \
850 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 851 fixed_regs[regno] = call_used_regs[regno] = 1; \
852 } \
9b6b54e2 853 \
c769a35d
RE		 854 if (TARGET_THUMB && optimize_size) \
855 { \
856 /* When optimizing for size, it's better not to use \
857 the HI regs, because of the overhead of stacking \
d6b4baa4 858 them. */ \
c769a35d
RE		 859 for (regno = FIRST_HI_REGNUM; \
860 regno <= LAST_HI_REGNUM; ++regno) \
861 fixed_regs[regno] = call_used_regs[regno] = 1; \
862 } \
863 \
fb14bc89
RE		 864 /* The link register can be clobbered by any branch insn, \
865 but we have no way to track that at present, so mark \
866 it as unavailable. */ \
867 if (TARGET_THUMB) \
868 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
869 \
9b66ebb1 870 if (TARGET_ARM && TARGET_HARD_FLOAT) \
9b6b54e2 871 { \
9b66ebb1 872 if (TARGET_MAVERICK) \
9b6b54e2 873 { \
9b66ebb1
PB		 874 for (regno = FIRST_FPA_REGNUM; \
875 regno <= LAST_FPA_REGNUM; ++ regno) \
876 fixed_regs[regno] = call_used_regs[regno] = 1; \
877 for (regno = FIRST_CIRRUS_FP_REGNUM; \
878 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
879 { \
880 fixed_regs[regno] = 0; \
881 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
882 } \
883 } \
884 if (TARGET_VFP) \
885 { \
886 for (regno = FIRST_VFP_REGNUM; \
887 regno <= LAST_VFP_REGNUM; ++ regno) \
888 { \
889 fixed_regs[regno] = 0; \
890 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
891 } \
9b6b54e2
NC		 892 } \
893 } \
894 \
5a9335ef
NC		 895 if (TARGET_REALLY_IWMMXT) \
896 { \
897 regno = FIRST_IWMMXT_GR_REGNUM; \
898 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
899 and wCG1 as call-preserved registers. The 2002/11/21 \
900 revision changed this so that all wCG registers are \
901 scratch registers. */ \
902 for (regno = FIRST_IWMMXT_GR_REGNUM; \
903 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 904 fixed_regs[regno] = 0; \
5a9335ef
NC		 905 /* The XScale ABI has wR0 - wR9 as scratch registers, \
906 the rest as call-preserved registers. */ \
907 for (regno = FIRST_IWMMXT_REGNUM; \
908 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
909 { \
910 fixed_regs[regno] = 0; \
911 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
912 } \
913 } \
914 \
fc555370 915 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 916 { \
917 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
918 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
919 } \
920 else if (TARGET_APCS_STACK) \
921 { \
922 fixed_regs[10] = 1; \
923 call_used_regs[10] = 1; \
924 } \
a2503645
RS		 925 /* -mcaller-super-interworking reserves r11 for calls to \
926 _interwork_r11_call_via_rN(). Making the register global \
927 is an easy way of ensuring that it remains valid for all \
928 calls. */ \
685c9c11
NS		 929 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
930 || (target_flags & (THUMB_FLAG_LEAF_BACKTRACE \
931 | THUMB_FLAG_BACKTRACE))) \
d5b7b3ae
RE		 932 { \
933 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
934 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 935 if (TARGET_CALLER_INTERWORKING) \
936 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 937 } \
938 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 939}
f676971a 940
6bc82793 941/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 942 by asm_fprintf:
943 %@ prints out ASM_COMMENT_START
944 %r prints out REGISTER_PREFIX reg_names[arg] */
945#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
946 case '@': \
947 fputs (ASM_COMMENT_START, FILE); \
948 break; \
949 \
950 case 'r': \
951 fputs (REGISTER_PREFIX, FILE); \
952 fputs (reg_names [va_arg (ARGS, int)], FILE); \
953 break;
954
d5b7b3ae 955/* Round X up to the nearest word. */
0c2ca901 956#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 957
6cfc7210 958/* Convert fron bytes to ints. */
e9d7b180 959#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 960
9b66ebb1
PB		 961/* The number of (integer) registers required to hold a quantity of type MODE.
962 Also used for VFP registers. */
e9d7b180
JD		 963#define ARM_NUM_REGS(MODE) \
964 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 965
966/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 967#define ARM_NUM_REGS2(MODE, TYPE) \
968 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 969 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 970
971/* The number of (integer) argument register available. */
d5b7b3ae 972#define NUM_ARG_REGS 4
6cfc7210 973
093354e0 974/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 975#define ARG_REGISTER(N) (N - 1)
6cfc7210 976
d5b7b3ae
RE		 977/* Specify the registers used for certain standard purposes.
978 The values of these macros are register numbers. */
35d965d5 979
d5b7b3ae
RE		 980/* The number of the last argument register. */
981#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 982
c769a35d
RE		 983/* The numbers of the Thumb register ranges. */
984#define FIRST_LO_REGNUM 0
6d3d9133 985#define LAST_LO_REGNUM 7
c769a35d
RE		 986#define FIRST_HI_REGNUM 8
987#define LAST_HI_REGNUM 11
6d3d9133 988
c9ca9b88
PB		 989/* We use sjlj exceptions for backwards compatibility. */
990#define MUST_USE_SJLJ_EXCEPTIONS 1
991/* We can generate DWARF2 Unwind info, even though we don't use it. */
992#define DWARF2_UNWIND_INFO 1
f676971a 993
c9ca9b88
PB		 994/* Use r0 and r1 to pass exception handling information. */
995#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
996
6d3d9133 997/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 998#define ARM_EH_STACKADJ_REGNUM 2
999#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 1000
d5b7b3ae
RE		 1001/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1002 as an invisible last argument (possible since varargs don't exist in
1003 Pascal), so the following is not true. */
68dfd979 1004#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
35d965d5 1005
d5b7b3ae
RE		 1006/* Define this to be where the real frame pointer is if it is not possible to
1007 work out the offset between the frame pointer and the automatic variables
1008 until after register allocation has taken place. FRAME_POINTER_REGNUM
1009 should point to a special register that we will make sure is eliminated.
1010
1011 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 1012 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 1013 as base register for addressing purposes. (See comments in
1014 find_reloads_address()). But - the Thumb does not allow high registers,
1015 including r11, to be used as base address registers. Hence our problem.
1016
1017 The solution used here, and in the old thumb port is to use r7 instead of
1018 r11 as the hard frame pointer and to have special code to generate
1019 backtrace structures on the stack (if required to do so via a command line
6bc82793 1020 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 1021 pointer. */
1022#define ARM_HARD_FRAME_POINTER_REGNUM 11
1023#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 1024
b15bca31
RE		 1025#define HARD_FRAME_POINTER_REGNUM \
1026 (TARGET_ARM \
1027 ? ARM_HARD_FRAME_POINTER_REGNUM \
1028 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 1029
b15bca31 1030#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 1031
b15bca31
RE		 1032/* Register to use for pushing function arguments. */
1033#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 1034
1035/* ARM floating pointer registers. */
9b66ebb1
PB		 1036#define FIRST_FPA_REGNUM 16
1037#define LAST_FPA_REGNUM 23
2fa330b2
PB		 1038#define IS_FPA_REGNUM(REGNUM) \
1039 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 1040
5a9335ef
NC		 1041#define FIRST_IWMMXT_GR_REGNUM 43
1042#define LAST_IWMMXT_GR_REGNUM 46
1043#define FIRST_IWMMXT_REGNUM 47
1044#define LAST_IWMMXT_REGNUM 62
1045#define IS_IWMMXT_REGNUM(REGNUM) \
1046 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1047#define IS_IWMMXT_GR_REGNUM(REGNUM) \
1048 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1049
35d965d5 1050/* Base register for access to local variables of the function. */
ff9940b0
RE		 1051#define FRAME_POINTER_REGNUM 25
1052
d5b7b3ae
RE		 1053/* Base register for access to arguments of the function. */
1054#define ARG_POINTER_REGNUM 26
62b10bbc 1055
9b6b54e2
NC		 1056#define FIRST_CIRRUS_FP_REGNUM 27
1057#define LAST_CIRRUS_FP_REGNUM 42
1058#define IS_CIRRUS_REGNUM(REGNUM) \
1059 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1060
9b66ebb1
PB		 1061#define FIRST_VFP_REGNUM 63
1062#define LAST_VFP_REGNUM 94
1063#define IS_VFP_REGNUM(REGNUM) \
1064 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1065
6f8c9bd1
NC		 1066/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1067/* + 16 Cirrus registers take us up to 43. */
5a9335ef 1068/* Intel Wireless MMX Technology registers add 16 + 4 more. */
9b66ebb1
PB		 1069/* VFP adds 32 + 1 more. */
1070#define FIRST_PSEUDO_REGISTER 96
62b10bbc 1071
2fa330b2
PB		 1072#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1073
35d965d5
RS		 1074/* Value should be nonzero if functions must have frame pointers.
1075 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 1076 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 1077 If we have to have a frame pointer we might as well make use of it.
1078 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 1079 functions, or simple tail call functions. */
7b8b8ade
NC		 1080#define FRAME_POINTER_REQUIRED \
1081 (current_function_has_nonlocal_label \
d5b7b3ae 1082 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 1083
d5b7b3ae
RE		 1084/* Return number of consecutive hard regs needed starting at reg REGNO
1085 to hold something of mode MODE.
1086 This is ordinarily the length in words of a value of mode MODE
1087 but can be less for certain modes in special long registers.
35d965d5 1088
3b684012 1089 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 1090 mode. */
1091#define HARD_REGNO_NREGS(REGNO, MODE) \
1092 ((TARGET_ARM \
9b66ebb1 1093 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 1094 && REGNO != FRAME_POINTER_REGNUM \
1095 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1096 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1097 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1098
4b02997f 1099/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1100#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1101 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1102
d5b7b3ae
RE		 1103/* Value is 1 if it is a good idea to tie two pseudo registers
1104 when one has mode MODE1 and one has mode MODE2.
1105 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1106 for any hard reg, then this must be 0 for correct output. */
1107#define MODES_TIEABLE_P(MODE1, MODE2) \
1108 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 1109
5a9335ef 1110#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1111 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1112
35d965d5 1113/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1114 since no saving is required (though calls clobber it) and it never contains
1115 function parameters. It is quite good to use lr since other calls may
f676971a 1116 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1117 least likely to contain a function parameter; in addition results are
d5b7b3ae 1118 returned in r0. */
9b66ebb1 1119
ff73fb53 1120#define REG_ALLOC_ORDER \
35d965d5 1121{ \
ff73fb53
NC		 1122 3, 2, 1, 0, 12, 14, 4, 5, \
1123 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0 1124 16, 17, 18, 19, 20, 21, 22, 23, \
9b6b54e2
NC		 1125 27, 28, 29, 30, 31, 32, 33, 34, \
1126 35, 36, 37, 38, 39, 40, 41, 42, \
5a9335ef
NC		 1127 43, 44, 45, 46, 47, 48, 49, 50, \
1128 51, 52, 53, 54, 55, 56, 57, 58, \
1129 59, 60, 61, 62, \
9b66ebb1
PB		 1130 24, 25, 26, \
1131 78, 77, 76, 75, 74, 73, 72, 71, \
1132 70, 69, 68, 67, 66, 65, 64, 63, \
1133 79, 80, 81, 82, 83, 84, 85, 86, \
1134 87, 88, 89, 90, 91, 92, 93, 94, \
1135 95 \
35d965d5 1136}
9338ffe6
PB		 1137
1138/* Interrupt functions can only use registers that have already been
1139 saved by the prologue, even if they would normally be
1140 call-clobbered. */
1141#define HARD_REGNO_RENAME_OK(SRC, DST) \
1142 (! IS_INTERRUPT (cfun->machine->func_type) || \
1143 regs_ever_live[DST])
35d965d5
RS		 1144\f
1145/* Register and constant classes. */
1146
3b684012 1147/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 1148 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 1149enum reg_class
1150{
1151 NO_REGS,
3b684012 1152 FPA_REGS,
9b6b54e2 1153 CIRRUS_REGS,
9b66ebb1 1154 VFP_REGS,
5a9335ef
NC		 1155 IWMMXT_GR_REGS,
1156 IWMMXT_REGS,
d5b7b3ae
RE		 1157 LO_REGS,
1158 STACK_REG,
1159 BASE_REGS,
1160 HI_REGS,
1161 CC_REG,
9b66ebb1 1162 VFPCC_REG,
35d965d5
RS		 1163 GENERAL_REGS,
1164 ALL_REGS,
1165 LIM_REG_CLASSES
1166};
1167
1168#define N_REG_CLASSES (int) LIM_REG_CLASSES
1169
d6b4baa4 1170/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1171#define REG_CLASS_NAMES \
1172{ \
1173 "NO_REGS", \
3b684012 1174 "FPA_REGS", \
9b6b54e2 1175 "CIRRUS_REGS", \
9b66ebb1 1176 "VFP_REGS", \
5a9335ef
NC		 1177 "IWMMXT_GR_REGS", \
1178 "IWMMXT_REGS", \
d5b7b3ae
RE		 1179 "LO_REGS", \
1180 "STACK_REG", \
1181 "BASE_REGS", \
1182 "HI_REGS", \
1183 "CC_REG", \
5384443a 1184 "VFPCC_REG", \
35d965d5
RS		 1185 "GENERAL_REGS", \
1186 "ALL_REGS", \
1187}
1188
1189/* Define which registers fit in which classes.
1190 This is an initializer for a vector of HARD_REG_SET
1191 of length N_REG_CLASSES. */
9b66ebb1
PB		 1192#define REG_CLASS_CONTENTS \
1193{ \
1194 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1195 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1196 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1197 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1198 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1199 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1200 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1201 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1202 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1203 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1204 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1205 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1206 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1207 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1208}
4b02997f 1209
35d965d5
RS		 1210/* The same information, inverted:
1211 Return the class number of the smallest class containing
1212 reg number REGNO. This could be a conditional expression
1213 or could index an array. */
d5b7b3ae 1214#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1215
9b66ebb1 1216/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1217 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1218 were set. */
75d2580c
RE		 1219#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1220 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1221 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1222 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1223 : 0)
75d2580c 1224
cc81dde8
PB		 1225/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1226 using r0-r4 for function arguments, r7 for the stack frame and don't
1227 have enough left over to do doubleword arithmetic. */
1228#define CLASS_LIKELY_SPILLED_P(CLASS) \
1229 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1230 || (CLASS) == CC_REG)
f676971a 1231
35d965d5 1232/* The class value for index registers, and the one for base regs. */
d5b7b3ae 1233#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
b93a0fe6 1234#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1235
b93a0fe6 1236/* For the Thumb the high registers cannot be used as base registers
6bc82793 1237 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1238 mode, then we must be conservative. */
3dcc68a4 1239#define MODE_BASE_REG_CLASS(MODE) \
b93a0fe6 1240 (TARGET_ARM ? GENERAL_REGS : \
888d2cd6
DJ		 1241 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1242
1243/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1244 instead of BASE_REGS. */
1245#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1246
d5b7b3ae
RE		 1247/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1248 registers explicitly used in the rtl to be used as spill registers
1249 but prevents the compiler from extending the lifetime of these
d6b4baa4 1250 registers. */
d5b7b3ae 1251#define SMALL_REGISTER_CLASSES TARGET_THUMB
35d965d5
RS		 1252
1253/* Get reg_class from a letter such as appears in the machine description.
3b684012 1254 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
d5b7b3ae
RE		 1255 ARM, but several more letters for the Thumb. */
1256#define REG_CLASS_FROM_LETTER(C) \
3b684012 1257 ( (C) == 'f' ? FPA_REGS \
9b6b54e2 1258 : (C) == 'v' ? CIRRUS_REGS \
9b66ebb1 1259 : (C) == 'w' ? VFP_REGS \
5a9335ef
NC		 1260 : (C) == 'y' ? IWMMXT_REGS \
1261 : (C) == 'z' ? IWMMXT_GR_REGS \
d5b7b3ae
RE		 1262 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1263 : TARGET_ARM ? NO_REGS \
1264 : (C) == 'h' ? HI_REGS \
1265 : (C) == 'b' ? BASE_REGS \
1266 : (C) == 'k' ? STACK_REG \
1267 : (C) == 'c' ? CC_REG \
1268 : NO_REGS)
35d965d5
RS		 1269
1270/* The letters I, J, K, L and M in a register constraint string
1271 can be used to stand for particular ranges of immediate operands.
1272 This macro defines what the ranges are.
1273 C is the letter, and VALUE is a constant value.
1274 Return 1 if VALUE is in the range specified by C.
b4ac57ab 1275 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
f676971a 1276 J: valid indexing constants.
aef1764c 1277 K: ~value ok in rhs argument of data operand.
f676971a 1278 L: -value ok in rhs argument of data operand.
3967692c 1279 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
d5b7b3ae 1280#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
aef1764c
RE		 1281 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1282 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1283 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 1284 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1285 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1286 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1287 : 0)
ff9940b0 1288
d5b7b3ae
RE		 1289#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1290 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1291 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1292 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1293 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1294 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1295 && ((VAL) & 3) == 0) : \
1296 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1297 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1298 : 0)
1299
1300#define CONST_OK_FOR_LETTER_P(VALUE, C) \
1301 (TARGET_ARM ? \
1302 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
f676971a 1303
9b66ebb1 1304/* Constant letter 'G' for the FP immediate constants.
d5b7b3ae
RE		 1305 'H' means the same constant negated. */
1306#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
9b66ebb1 1307 ((C) == 'G' ? arm_const_double_rtx (X) : \
3b684012 1308 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
d5b7b3ae
RE		 1309
1310#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1311 (TARGET_ARM ? \
1312 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1313
ff9940b0 1314/* For the ARM, `Q' means that this is a memory operand that is just
f676971a 1315 an offset from a register.
ff9940b0
RE		 1316 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1317 address. This means that the symbol is in the text segment and can be
9b66ebb1 1318 accessed without using a load.
2075b05d
RE		 1319 'D' Prefixes a number of const_double operands where:
1320 'Da' is a constant that takes two ARM insns to load.
1321 'Db' takes three ARM insns.
1322 'Dc' takes four ARM insns, if we allow that in this compilation.
edc62122 1323 'U' Prefixes an extended memory constraint where:
f676971a
EC		 1324 'Uv' is an address valid for VFP load/store insns.
1325 'Uy' is an address valid for iwmmxt load/store insns.
edc62122 1326 'Uq' is an address valid for ldrsb. */
ff9940b0 1327
2075b05d 1328#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
9b901d50
RE		 1329 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1330 || GET_CODE (OP) == CONST_INT \
1331 || GET_CODE (OP) == CONST_VECTOR) \
2075b05d
RE		 1332 && (((STR)[1] == 'a' \
1333 && arm_const_double_inline_cost (OP) == 2) \
1334 || ((STR)[1] == 'b' \
1335 && arm_const_double_inline_cost (OP) == 3) \
1336 || ((STR)[1] == 'c' \
1337 && arm_const_double_inline_cost (OP) == 4 \
1338 && !(optimize_size || arm_ld_sched)))) : \
1339 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1340 && GET_CODE (XEXP (OP, 0)) == REG) : \
1341 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1342 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1343 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1344 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1345 ((C) == 'T') ? cirrus_memory_offset (OP) : \
fdd695fd
PB		 1346 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1347 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
2075b05d
RE		 1348 ((C) == 'U' && (STR)[1] == 'q') \
1349 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1350 : 0)
1e1ab407
RE		 1351
1352#define CONSTRAINT_LEN(C,STR) \
2075b05d 1353 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
ff9940b0 1354
d5b7b3ae
RE		 1355#define EXTRA_CONSTRAINT_THUMB(X, C) \
1356 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1357 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1358
1e1ab407
RE		 1359#define EXTRA_CONSTRAINT_STR(X, C, STR) \
1360 (TARGET_ARM \
1361 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1362 : EXTRA_CONSTRAINT_THUMB (X, C))
35d965d5 1363
9b66ebb1
PB		 1364#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1365
35d965d5
RS		 1366/* Given an rtx X being reloaded into a reg required to be
1367 in class CLASS, return the class of reg to actually use.
d5b7b3ae
RE		 1368 In general this is just CLASS, but for the Thumb we prefer
1369 a LO_REGS class or a subset. */
1370#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1371 (TARGET_ARM ? (CLASS) : \
1372 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1373
1374/* Must leave BASE_REGS reloads alone */
1375#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1376 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1377 ? ((true_regnum (X) == -1 ? LO_REGS \
1378 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1379 : NO_REGS)) \
1380 : NO_REGS)
1381
1382#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1383 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1384 ? ((true_regnum (X) == -1 ? LO_REGS \
1385 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1386 : NO_REGS)) \
1387 : NO_REGS)
35d965d5 1388
ff9940b0
RE		 1389/* Return the register class of a scratch register needed to copy IN into
1390 or out of a register in CLASS in MODE. If it can be done directly,
1391 NO_REGS is returned. */
d5b7b3ae 1392#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1393 /* Restrict which direct reloads are allowed for VFP regs. */ \
1394 ((TARGET_VFP && TARGET_HARD_FLOAT \
1395 && (CLASS) == VFP_REGS) \
1396 ? vfp_secondary_reload_class (MODE, X) \
1397 : TARGET_ARM \
1398 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1399 ? GENERAL_REGS : NO_REGS) \
1400 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1401
d6b4baa4 1402/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1403#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1404 /* Restrict which direct reloads are allowed for VFP regs. */ \
1405 ((TARGET_VFP && TARGET_HARD_FLOAT \
1406 && (CLASS) == VFP_REGS) \
1407 ? vfp_secondary_reload_class (MODE, X) : \
9b6b54e2 1408 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1409 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1410 && (CLASS) == CIRRUS_REGS \
1411 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1412 ? GENERAL_REGS : \
d5b7b3ae 1413 (TARGET_ARM ? \
5a9335ef
NC		 1414 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1415 && CONSTANT_P (X)) \
1416 ? GENERAL_REGS : \
61f0ccff 1417 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1418 && (GET_CODE (X) == MEM \
1419 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1420 && true_regnum (X) == -1))) \
1421 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1422 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1423
6f734908
RE		 1424/* Try a machine-dependent way of reloading an illegitimate address
1425 operand. If we find one, push the reload and jump to WIN. This
1426 macro is used in only one place: `find_reloads_address' in reload.c.
1427
1428 For the ARM, we wish to handle large displacements off a base
1429 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1430 This can cut the number of reloads needed. */
1431#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1432 do \
1433 { \
1434 if (GET_CODE (X) == PLUS \
1435 && GET_CODE (XEXP (X, 0)) == REG \
1436 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1437 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1438 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1439 { \
1440 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1441 HOST_WIDE_INT low, high; \
1442 \
de6f27a8 1443 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1444 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1445 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1446 /* Need to be careful, -256 is not a valid offset. */ \
1447 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1448 else if (MODE == SImode \
de6f27a8 1449 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1450 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1451 /* Need to be careful, -4096 is not a valid offset. */ \
1452 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1453 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1454 /* Need to be careful, -256 is not a valid offset. */ \
1455 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1456 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1457 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1458 /* Need to be careful, -1024 is not a valid offset. */ \
1459 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1460 else \
1461 break; \
1462 \
30cf4896
KG		 1463 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1464 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1465 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1466 /* Check for overflow or zero */ \
1467 if (low == 0 || high == 0 || (high + low != val)) \
1468 break; \
1469 \
1470 /* Reload the high part into a base reg; leave the low part \
1471 in the mem. */ \
1472 X = gen_rtx_PLUS (GET_MODE (X), \
1473 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1474 GEN_INT (high)), \
1475 GEN_INT (low)); \
df4ae160 1476 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1477 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1478 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1479 goto WIN; \
1480 } \
1481 } \
62b10bbc 1482 while (0)
6f734908 1483
27847754 1484/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1485 SP+large_offset address, then reload won't know how to fix it. It sees
1486 only that SP isn't valid for HImode, and so reloads the SP into an index
1487 register, but the resulting address is still invalid because the offset
1488 is too big. We fix it here instead by reloading the entire address. */
1489/* We could probably achieve better results by defining PROMOTE_MODE to help
1490 cope with the variances between the Thumb's signed and unsigned byte and
1491 halfword load instructions. */
1492#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1493{ \
1494 if (GET_CODE (X) == PLUS \
1495 && GET_MODE_SIZE (MODE) < 4 \
1496 && GET_CODE (XEXP (X, 0)) == REG \
1497 && XEXP (X, 0) == stack_pointer_rtx \
1498 && GET_CODE (XEXP (X, 1)) == CONST_INT \
76a318e9 1499 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
d5b7b3ae
RE		 1500 { \
1501 rtx orig_X = X; \
1502 X = copy_rtx (X); \
df4ae160 1503 push_reload (orig_X, NULL_RTX, &X, NULL, \
4a692617 1504 MODE_BASE_REG_CLASS (MODE), \
d5b7b3ae
RE		 1505 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1506 goto WIN; \
1507 } \
1508}
1509
1510#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1511 if (TARGET_ARM) \
1512 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1513 else \
1514 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1515
35d965d5
RS		 1516/* Return the maximum number of consecutive registers
1517 needed to represent mode MODE in a register of class CLASS.
3b684012 1518 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1519#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1520 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1521
1522/* If defined, gives a class of registers that cannot be used as the
1523 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1524
3b684012 1525/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1526#define REGISTER_MOVE_COST(MODE, FROM, TO) \
d5b7b3ae 1527 (TARGET_ARM ? \
3b684012
RE		 1528 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1529 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
9b66ebb1
PB		 1530 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1531 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
5a9335ef
NC		 1532 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1533 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1534 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1535 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1536 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1537 2) \
d5b7b3ae
RE		 1538 : \
1539 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1540\f
1541/* Stack layout; function entry, exit and calling. */
1542
1543/* Define this if pushing a word on the stack
1544 makes the stack pointer a smaller address. */
1545#define STACK_GROWS_DOWNWARD 1
1546
1547/* Define this if the nominal address of the stack frame
1548 is at the high-address end of the local variables;
1549 that is, each additional local variable allocated
1550 goes at a more negative offset in the frame. */
1551#define FRAME_GROWS_DOWNWARD 1
1552
a2503645
RS		 1553/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1554 When present, it is one word in size, and sits at the top of the frame,
1555 between the soft frame pointer and either r7 or r11.
1556
1557 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1558 and only then if some outgoing arguments are passed on the stack. It would
1559 be tempting to also check whether the stack arguments are passed by indirect
1560 calls, but there seems to be no reason in principle why a post-reload pass
1561 couldn't convert a direct call into an indirect one. */
1562#define CALLER_INTERWORKING_SLOT_SIZE \
1563 (TARGET_CALLER_INTERWORKING \
1564 && current_function_outgoing_args_size != 0 \
1565 ? UNITS_PER_WORD : 0)
1566
35d965d5
RS		 1567/* Offset within stack frame to start allocating local variables at.
1568 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1569 first local allocated. Otherwise, it is the offset to the BEGINNING
1570 of the first local allocated. */
1571#define STARTING_FRAME_OFFSET 0
1572
1573/* If we generate an insn to push BYTES bytes,
1574 this says how many the stack pointer really advances by. */
d5b7b3ae 1575/* The push insns do not do this rounding implicitly.
d6b4baa4 1576 So don't define this. */
0c2ca901 1577/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1578
1579/* Define this if the maximum size of all the outgoing args is to be
1580 accumulated and pushed during the prologue. The amount can be
1581 found in the variable current_function_outgoing_args_size. */
6cfc7210 1582#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1583
1584/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1585#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1586
1587/* Value is the number of byte of arguments automatically
1588 popped when returning from a subroutine call.
8b109b37 1589 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1590 FUNTYPE is the data type of the function (as a tree),
1591 or for a library call it is an identifier node for the subroutine name.
1592 SIZE is the number of bytes of arguments passed on the stack.
1593
1594 On the ARM, the caller does not pop any of its arguments that were passed
1595 on the stack. */
6cfc7210 1596#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1597
1598/* Define how to find the value returned by a library function
1599 assuming the value has mode MODE. */
1600#define LIBCALL_VALUE(MODE) \
72cdc543 1601 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1602 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1603 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
72cdc543 1604 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1605 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1606 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1607 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1608 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1609 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1610
6cfc7210
NC		 1611/* Define how to find the value returned by a function.
1612 VALTYPE is the data type of the value (as a tree).
1613 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1614 otherwise, FUNC is 0. */
d5b7b3ae 1615#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1616 arm_function_value (VALTYPE, FUNC);
6cfc7210 1617
35d965d5
RS		 1618/* 1 if N is a possible register number for a function value.
1619 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1620/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1621#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1622 ((REGNO) == ARG_REGISTER (1) \
9b66ebb1 1623 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1624 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1625 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
9b66ebb1 1626 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1627 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1628
9f7bf991
RE		 1629/* Amount of memory needed for an untyped call to save all possible return
1630 registers. */
1631#define APPLY_RESULT_SIZE arm_apply_result_size()
1632
11c1a207
RE		 1633/* How large values are returned */
1634/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1635 in registers, based on the type of value. */
f5a1b0d2 1636#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1637
1638/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1639 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1640 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1641#define DEFAULT_PCC_STRUCT_RETURN 0
1642
d5b7b3ae
RE		 1643/* Flags for the call/call_value rtl operations set up by function_arg. */
1644#define CALL_NORMAL 0x00000000 /* No special processing. */
1645#define CALL_LONG 0x00000001 /* Always call indirect. */
1646#define CALL_SHORT 0x00000002 /* Never call indirect. */
1647
6d3d9133 1648/* These bits describe the different types of function supported
112cdef5 1649 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1650 normal function and an interworked function, for example. Knowing the
1651 type of a function is important for determining its prologue and
1652 epilogue sequences.
1653 Note value 7 is currently unassigned. Also note that the interrupt
1654 function types all have bit 2 set, so that they can be tested for easily.
1655 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1656 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1657 default to unknown. This will force the first use of arm_current_func_type
1658 to call arm_compute_func_type. */
1659#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1660#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1661#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1662#define ARM_FT_ISR 4 /* An interrupt service routine. */
1663#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1664#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1665
1666#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1667
1668/* In addition functions can have several type modifiers,
1669 outlined by these bit masks: */
1670#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1671#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1672#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1673#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
6d3d9133
NC		 1674
1675/* Some macros to test these flags. */
1676#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1677#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1678#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1679#define IS_NAKED(t) (t & ARM_FT_NAKED)
1680#define IS_NESTED(t) (t & ARM_FT_NESTED)
1681
5848830f
PB		 1682
1683/* Structure used to hold the function stack frame layout. Offsets are
1684 relative to the stack pointer on function entry. Positive offsets are
1685 in the direction of stack growth.
1686 Only soft_frame is used in thumb mode. */
1687
1688typedef struct arm_stack_offsets GTY(())
1689{
1690 int saved_args; /* ARG_POINTER_REGNUM. */
1691 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1692 int saved_regs;
1693 int soft_frame; /* FRAME_POINTER_REGNUM. */
1694 int outgoing_args; /* STACK_POINTER_REGNUM. */
1695}
1696arm_stack_offsets;
1697
6d3d9133
NC		 1698/* A C structure for machine-specific, per-function data.
1699 This is added to the cfun structure. */
e2500fed 1700typedef struct machine_function GTY(())
d5b7b3ae 1701{
6bc82793 1702 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1703 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1704 /* Records if LR has to be saved for far jumps. */
1705 int far_jump_used;
1706 /* Records if ARG_POINTER was ever live. */
1707 int arg_pointer_live;
6f7ebcbb
NC		 1708 /* Records if the save of LR has been eliminated. */
1709 int lr_save_eliminated;
0977774b 1710 /* The size of the stack frame. Only valid after reload. */
5848830f 1711 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1712 /* Records the type of the current function. */
1713 unsigned long func_type;
3cb66fd7
NC		 1714 /* Record if the function has a variable argument list. */
1715 int uses_anonymous_args;
5a9335ef
NC		 1716 /* Records if sibcalls are blocked because an argument
1717 register is needed to preserve stack alignment. */
1718 int sibcall_blocked;
b12a00f1 1719 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1720 register. We can never call via LR or PC. We can call via SP if a
1721 trampoline happens to be on the top of the stack. */
1722 rtx call_via[14];
6d3d9133
NC		 1723}
1724machine_function;
d5b7b3ae 1725
b12a00f1
RE		 1726/* As in the machine_function, a global set of call-via labels, for code
1727 that is in text_section(). */
57ecec57 1728extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1729
82e9d970
PB		 1730/* A C type for declaring a variable that is used as the first argument of
1731 `FUNCTION_ARG' and other related values. For some target machines, the
1732 type `int' suffices and can hold the number of bytes of argument so far. */
1733typedef struct
1734{
d5b7b3ae 1735 /* This is the number of registers of arguments scanned so far. */
82e9d970 1736 int nregs;
5a9335ef
NC		 1737 /* This is the number of iWMMXt register arguments scanned so far. */
1738 int iwmmxt_nregs;
1739 int named_count;
1740 int nargs;
d6b4baa4 1741 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
82e9d970 1742 int call_cookie;
5848830f 1743 int can_split;
d5b7b3ae 1744} CUMULATIVE_ARGS;
82e9d970 1745
35d965d5
RS		 1746/* Define where to put the arguments to a function.
1747 Value is zero to push the argument on the stack,
1748 or a hard register in which to store the argument.
1749
1750 MODE is the argument's machine mode.
1751 TYPE is the data type of the argument (as a tree).
1752 This is null for libcalls where that information may
1753 not be available.
1754 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1755 the preceding args and about the function being called.
1756 NAMED is nonzero if this argument is a named parameter
1757 (otherwise it is an extra parameter matching an ellipsis).
1758
1759 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1760 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1761 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1762 defined), say it is passed in the stack (function_prologue will
1763 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1764#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1765 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1766
866af8a9
JB		 1767#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1768 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1769
1770#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1771 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1772
1773/* For AAPCS, padding should never be below the argument. For other ABIs,
1774 * mimic the default. */
1775#define PAD_VARARGS_DOWN \
1776 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1777
35d965d5
RS		 1778/* Initialize a variable CUM of type CUMULATIVE_ARGS
1779 for a call to a function whose data type is FNTYPE.
1780 For a library call, FNTYPE is 0.
1781 On the ARM, the offset starts at 0. */
0f6937fe 1782#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1783 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1784
1785/* Update the data in CUM to advance over an argument
1786 of mode MODE and data type TYPE.
1787 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1788#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1789 (CUM).nargs += 1; \
f676971a 1790 if (arm_vector_mode_supported_p (MODE) \
5848830f
PB		 1791 && (CUM).named_count > (CUM).nargs) \
1792 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1793 else \
5848830f 1794 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1795
5a9335ef
NC		 1796/* If defined, a C expression that gives the alignment boundary, in bits, of an
1797 argument with the specified mode and type. If it is not defined,
1798 `PARM_BOUNDARY' is used for all arguments. */
1799#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1800 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1801 ? DOUBLEWORD_ALIGNMENT \
1802 : PARM_BOUNDARY )
5a9335ef 1803
35d965d5
RS		 1804/* 1 if N is a possible register number for function argument passing.
1805 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1806#define FUNCTION_ARG_REGNO_P(REGNO) \
1807 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1808 || (TARGET_IWMMXT_ABI \
1809 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1810
f99fce0c 1811\f
afef3d7a
NC		 1812/* If your target environment doesn't prefix user functions with an
1813 underscore, you may wish to re-define this to prevent any conflicts.
1814 e.g. AOF may prefix mcount with an underscore. */
1815#ifndef ARM_MCOUNT_NAME
1816#define ARM_MCOUNT_NAME "*mcount"
1817#endif
1818
1819/* Call the function profiler with a given profile label. The Acorn
1820 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1821 On the ARM the full profile code will look like:
1822 .data
1823 LP1
1824 .word 0
1825 .text
1826 mov ip, lr
1827 bl mcount
1828 .word LP1
1829
1830 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1831 will output the .text section.
1832
1833 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1834 ``prof'' doesn't seem to mind about this!
1835
1836 Note - this version of the code is designed to work in both ARM and
1837 Thumb modes. */
be393ecf 1838#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1839#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1840{ \
1841 char temp[20]; \
1842 rtx sym; \
1843 \
dd18ae56 1844 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1845 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1846 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1847 fputc ('\n', STREAM); \
1848 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1849 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1850 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1851}
be393ecf 1852#endif
35d965d5 1853
59be6073 1854#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1855#define FUNCTION_PROFILER(STREAM, LABELNO) \
1856 if (TARGET_ARM) \
1857 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1858 else \
1859 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1860#else
1861#define FUNCTION_PROFILER(STREAM, LABELNO) \
1862 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1863#endif
d5b7b3ae 1864
35d965d5
RS		 1865/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1866 the stack pointer does not matter. The value is tested only in
1867 functions that have frame pointers.
1868 No definition is equivalent to always zero.
1869
1870 On the ARM, the function epilogue recovers the stack pointer from the
1871 frame. */
1872#define EXIT_IGNORE_STACK 1
1873
c7861455
RE		 1874#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1875
35d965d5
RS		 1876/* Determine if the epilogue should be output as RTL.
1877 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1878#define USE_RETURN_INSN(ISCOND) \
a72d4945 1879 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1880
1881/* Definitions for register eliminations.
1882
1883 This is an array of structures. Each structure initializes one pair
1884 of eliminable registers. The "from" register number is given first,
1885 followed by "to". Eliminations of the same "from" register are listed
1886 in order of preference.
1887
1888 We have two registers that can be eliminated on the ARM. First, the
1889 arg pointer register can often be eliminated in favor of the stack
1890 pointer register. Secondly, the pseudo frame pointer register can always
1891 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1892 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1893 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1894
d5b7b3ae
RE		 1895#define ELIMINABLE_REGS \
1896{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1897 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1898 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1899 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1900 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1901 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1902 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1903
d5b7b3ae
RE		 1904/* Given FROM and TO register numbers, say whether this elimination is
1905 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1906
1907 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1908 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1909 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1910 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1911 ARG_POINTER_REGNUM. */
1912#define CAN_ELIMINATE(FROM, TO) \
1913 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1914 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1915 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1916 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1917 1)
aeaf4d25 1918
d5b7b3ae
RE		 1919/* Define the offset between two registers, one to be eliminated, and the
1920 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1921#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1922 if (TARGET_ARM) \
5848830f 1923 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1924 else \
5848830f
PB		 1925 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1926
d5b7b3ae
RE		 1927/* Special case handling of the location of arguments passed on the stack. */
1928#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1929
d5b7b3ae
RE		 1930/* Initialize data used by insn expanders. This is called from insn_emit,
1931 once for every function before code is generated. */
1932#define INIT_EXPANDERS arm_init_expanders ()
1933
35d965d5
RS		 1934/* Output assembler code for a block containing the constant parts
1935 of a trampoline, leaving space for the variable parts.
1936
1937 On the ARM, (if r8 is the static chain regnum, and remembering that
1938 referencing pc adds an offset of 8) the trampoline looks like:
1939 ldr r8, [pc, #0]
1940 ldr pc, [pc]
1941 .word static chain value
11c1a207 1942 .word function's address
27847754 1943 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1944#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1945{ \
1946 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1947 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1948 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1949 PC_REGNUM, PC_REGNUM); \
1950 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1951 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1952}
1953
1954/* On the Thumb we always switch into ARM mode to execute the trampoline.
1955 Why - because it is easier. This code will always be branched to via
1956 a BX instruction and since the compiler magically generates the address
1957 of the function the linker has no opportunity to ensure that the
1958 bottom bit is set. Thus the processor will be in ARM mode when it
1959 reaches this code. So we duplicate the ARM trampoline code and add
1960 a switch into Thumb mode as well. */
1961#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1962{ \
1963 fprintf (FILE, "\t.code 32\n"); \
1964 fprintf (FILE, ".Ltrampoline_start:\n"); \
1965 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1966 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1967 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1968 IP_REGNUM, PC_REGNUM); \
1969 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1970 IP_REGNUM, IP_REGNUM); \
1971 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1972 fprintf (FILE, "\t.word\t0\n"); \
1973 fprintf (FILE, "\t.word\t0\n"); \
1974 fprintf (FILE, "\t.code 16\n"); \
35d965d5
RS		 1975}
1976
d5b7b3ae
RE		 1977#define TRAMPOLINE_TEMPLATE(FILE) \
1978 if (TARGET_ARM) \
1979 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1980 else \
1981 THUMB_TRAMPOLINE_TEMPLATE (FILE)
f676971a 1982
35d965d5 1983/* Length in units of the trampoline for entering a nested function. */
d5b7b3ae 1984#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
35d965d5 1985
006946e4
JM		 1986/* Alignment required for a trampoline in bits. */
1987#define TRAMPOLINE_ALIGNMENT 32
35d965d5
RS		 1988
1989/* Emit RTL insns to initialize the variable parts of a trampoline.
1990 FNADDR is an RTX for the address of the function's pure code.
1991 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1992#ifndef INITIALIZE_TRAMPOLINE
1993#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1994{ \
1995 emit_move_insn (gen_rtx_MEM (SImode, \
1996 plus_constant (TRAMP, \
1997 TARGET_ARM ? 8 : 16)), \
1998 CXT); \
1999 emit_move_insn (gen_rtx_MEM (SImode, \
2000 plus_constant (TRAMP, \
2001 TARGET_ARM ? 12 : 20)), \
2002 FNADDR); \
35d965d5 2003}
192c8d78 2004#endif
35d965d5 2005
35d965d5
RS		 2006\f
2007/* Addressing modes, and classification of registers for them. */
3cd45774
RE		 2008#define HAVE_POST_INCREMENT 1
2009#define HAVE_PRE_INCREMENT TARGET_ARM
2010#define HAVE_POST_DECREMENT TARGET_ARM
2011#define HAVE_PRE_DECREMENT TARGET_ARM
2012#define HAVE_PRE_MODIFY_DISP TARGET_ARM
2013#define HAVE_POST_MODIFY_DISP TARGET_ARM
2014#define HAVE_PRE_MODIFY_REG TARGET_ARM
2015#define HAVE_POST_MODIFY_REG TARGET_ARM
35d965d5
RS		 2016
2017/* Macros to check register numbers against specific register classes. */
2018
2019/* These assume that REGNO is a hard or pseudo reg number.
2020 They give nonzero only if REGNO is a hard reg of the suitable class
2021 or a pseudo reg currently allocated to a suitable hard reg.
2022 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 2023 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 2024#define TEST_REGNO(R, TEST, VALUE) \
2025 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2026
2027/* On the ARM, don't allow the pc to be used. */
f1008e52
RE		 2028#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2029 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2030 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2031 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2032
2033#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2034 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2035 || (GET_MODE_SIZE (MODE) >= 4 \
2036 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2037
2038#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2039 (TARGET_THUMB \
2040 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2041 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2042
888d2cd6
DJ		 2043/* Nonzero if X can be the base register in a reg+reg addressing mode.
2044 For Thumb, we can not use SP + reg, so reject SP. */
2045#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2046 REGNO_OK_FOR_INDEX_P (X)
2047
f1008e52
RE		 2048/* For ARM code, we don't care about the mode, but for Thumb, the index
2049 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 2050#define REGNO_OK_FOR_INDEX_P(REGNO) \
2051 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 2052
2053/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 2054 Shifts in addresses can't be by a register. */
ff9940b0 2055#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 2056
2057/* Recognize any constant value that is a valid address. */
2058/* XXX We can address any constant, eventually... */
11c1a207
RE		 2059
2060#ifdef AOF_ASSEMBLER
2061
2062#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 2063 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 2064
2065#else
35d965d5 2066
008cf58a
RE		 2067#define CONSTANT_ADDRESS_P(X) \
2068 (GET_CODE (X) == SYMBOL_REF \
2069 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 2070 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 2071
11c1a207
RE		 2072#endif /* AOF_ASSEMBLER */
2073
35d965d5
RS		 2074/* Nonzero if the constant value X is a legitimate general operand.
2075 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2076
2077 On the ARM, allow any integer (invalid ones are removed later by insn
2078 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 2079 constant pool XXX.
f676971a 2080
82e9d970 2081 When generating pic allow anything. */
d5b7b3ae
RE		 2082#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2083
2084#define THUMB_LEGITIMATE_CONSTANT_P(X) \
2085 ( GET_CODE (X) == CONST_INT \
2086 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 2087 || CONSTANT_ADDRESS_P (X) \
2088 || flag_pic)
d5b7b3ae
RE		 2089
2090#define LEGITIMATE_CONSTANT_P(X) \
2091 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2092
c27ba912
DM		 2093/* Special characters prefixed to function names
2094 in order to encode attribute like information.
2095 Note, '@' and '*' have already been taken. */
2096#define SHORT_CALL_FLAG_CHAR '^'
2097#define LONG_CALL_FLAG_CHAR '#'
2098
2099#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2100 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2101
2102#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2103 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2104
2105#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2106#define SUBTARGET_NAME_ENCODING_LENGTHS
2107#endif
2108
6bc82793 2109/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 2110 Each case label should return the number of characters to
2111 be stripped from the start of a function's name, if that
2112 name starts with the indicated character. */
2113#define ARM_NAME_ENCODING_LENGTHS \
2114 case SHORT_CALL_FLAG_CHAR: return 1; \
2115 case LONG_CALL_FLAG_CHAR: return 1; \
00fdafef 2116 case '*': return 1; \
f676971a 2117 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 2118
c27ba912
DM		 2119/* This is how to output a reference to a user-level label named NAME.
2120 `assemble_name' uses this. */
e5951263 2121#undef ASM_OUTPUT_LABELREF
c27ba912 2122#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 2123 arm_asm_output_labelref (FILE, NAME)
c27ba912 2124
7abc66b1
JB		 2125/* The EABI specifies that constructors should go in .init_array.
2126 Other targets use .ctors for compatibility. */
2127#define ARM_EABI_CTORS_SECTION_OP \
2128 "\t.section\t.init_array,\"aw\",%init_array"
2129#define ARM_EABI_DTORS_SECTION_OP \
2130 "\t.section\t.fini_array,\"aw\",%fini_array"
2131#define ARM_CTORS_SECTION_OP \
2132 "\t.section\t.ctors,\"aw\",%progbits"
2133#define ARM_DTORS_SECTION_OP \
2134 "\t.section\t.dtors,\"aw\",%progbits"
2135
2136/* Define CTORS_SECTION_ASM_OP. */
2137#undef CTORS_SECTION_ASM_OP
2138#undef DTORS_SECTION_ASM_OP
2139#ifndef IN_LIBGCC2
2140# define CTORS_SECTION_ASM_OP \
2141 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2142# define DTORS_SECTION_ASM_OP \
2143 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2144#else /* !defined (IN_LIBGCC2) */
2145/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2146 so we cannot use the definition above. */
2147# ifdef __ARM_EABI__
2148/* The .ctors section is not part of the EABI, so we do not define
2149 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2150 from trying to use it. We do define it when doing normal
2151 compilation, as .init_array can be used instead of .ctors. */
2152/* There is no need to emit begin or end markers when using
2153 init_array; the dynamic linker will compute the size of the
2154 array itself based on special symbols created by the static
2155 linker. However, we do need to arrange to set up
2156 exception-handling here. */
2157# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2158# define CTOR_LIST_END /* empty */
2159# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2160# define DTOR_LIST_END /* empty */
2161# else /* !defined (__ARM_EABI__) */
2162# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2163# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2164# endif /* !defined (__ARM_EABI__) */
2165#endif /* !defined (IN_LIBCC2) */
2166
1e731102
MM		 2167/* True if the operating system can merge entities with vague linkage
2168 (e.g., symbols in COMDAT group) during dynamic linking. */
2169#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2170#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2171#endif
2172
a77655b1
NC		 2173/* Set the short-call flag for any function compiled in the current
2174 compilation unit. We skip this for functions with the section
c112cf2b 2175 attribute when long-calls are in effect as this tells the compiler
a77655b1
NC		 2176 that the section might be placed a long way from the caller.
2177 See arm_is_longcall_p() for more information. */
c27ba912 2178#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
a77655b1
NC		 2179 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2180 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
c27ba912 2181
35d965d5
RS		 2182/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2183 and check its validity for a certain class.
2184 We have two alternate definitions for each of them.
2185 The usual definition accepts all pseudo regs; the other rejects
2186 them unless they have been allocated suitable hard regs.
2187 The symbol REG_OK_STRICT causes the latter definition to be used. */
2188#ifndef REG_OK_STRICT
ff9940b0 2189
f1008e52
RE		 2190#define ARM_REG_OK_FOR_BASE_P(X) \
2191 (REGNO (X) <= LAST_ARM_REGNUM \
2192 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2193 || REGNO (X) == FRAME_POINTER_REGNUM \
2194 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 2195
f1008e52
RE		 2196#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2197 (REGNO (X) <= LAST_LO_REGNUM \
2198 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2199 || (GET_MODE_SIZE (MODE) >= 4 \
2200 && (REGNO (X) == STACK_POINTER_REGNUM \
2201 || (X) == hard_frame_pointer_rtx \
2202 || (X) == arg_pointer_rtx)))
ff9940b0 2203
76a318e9
RE		 2204#define REG_STRICT_P 0
2205
d5b7b3ae 2206#else /* REG_OK_STRICT */
ff9940b0 2207
f1008e52
RE		 2208#define ARM_REG_OK_FOR_BASE_P(X) \
2209 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2210
f1008e52
RE		 2211#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2212 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2213
76a318e9
RE		 2214#define REG_STRICT_P 1
2215
d5b7b3ae 2216#endif /* REG_OK_STRICT */
f1008e52
RE		 2217
2218/* Now define some helpers in terms of the above. */
2219
2220#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2221 (TARGET_THUMB \
2222 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2223 : ARM_REG_OK_FOR_BASE_P (X))
2224
2225#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2226
2227/* For Thumb, a valid index register is anything that can be used in
2228 a byte load instruction. */
2229#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2230
2231/* Nonzero if X is a hard reg that can be used as an index
2232 or if it is a pseudo reg. On the Thumb, the stack pointer
2233 is not suitable. */
2234#define REG_OK_FOR_INDEX_P(X) \
2235 (TARGET_THUMB \
2236 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2237 : ARM_REG_OK_FOR_INDEX_P (X))
2238
888d2cd6
DJ		 2239/* Nonzero if X can be the base register in a reg+reg addressing mode.
2240 For Thumb, we can not use SP + reg, so reject SP. */
2241#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2242 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2243\f
2244/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2245 that is a valid memory address for an instruction.
2246 The MODE argument is the machine mode for the MEM expression
76a318e9 2247 that wants to use this address. */
f676971a 2248
f1008e52
RE		 2249#define ARM_BASE_REGISTER_RTX_P(X) \
2250 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2251
f1008e52
RE		 2252#define ARM_INDEX_REGISTER_RTX_P(X) \
2253 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2254
76a318e9
RE		 2255#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2256 { \
1e1ab407 2257 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2258 goto WIN; \
6b990f6b 2259 }
d5b7b3ae 2260
76a318e9
RE		 2261#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2262 { \
2263 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2264 goto WIN; \
2265 }
d5b7b3ae 2266
d5b7b3ae
RE		 2267#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2268 if (TARGET_ARM) \
2269 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2270 else /* if (TARGET_THUMB) */ \
f676971a 2271 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2272
35d965d5
RS		 2273\f
2274/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2275 to be legitimate. If we find one, return the new, valid address. */
2276#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2277do { \
2278 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2279} while (0)
2280
6f5b4f3e
RE		 2281#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2282do { \
2283 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2284} while (0)
2285
2286#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2287do { \
2288 if (TARGET_ARM) \
2289 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2290 else \
2291 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2292 \
2293 if (memory_address_p (MODE, X)) \
2294 goto WIN; \
ccf4d512 2295} while (0)
f676971a 2296
35d965d5
RS		 2297/* Go to LABEL if ADDR (a legitimate address expression)
2298 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2299#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2300{ \
d5b7b3ae
RE		 2301 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2302 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2303 goto LABEL; \
2304}
d5b7b3ae
RE		 2305
2306/* Nothing helpful to do for the Thumb */
2307#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2308 if (TARGET_ARM) \
f676971a 2309 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2310\f
d5b7b3ae 2311
35d965d5
RS		 2312/* Specify the machine mode that this machine uses
2313 for the index in the tablejump instruction. */
d5b7b3ae 2314#define CASE_VECTOR_MODE Pmode
35d965d5 2315
ff9940b0
RE		 2316/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2317 unsigned is probably best, but may break some code. */
2318#ifndef DEFAULT_SIGNED_CHAR
3967692c 2319#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2320#endif
2321
35d965d5 2322/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2323 in one reasonably fast instruction. */
2324#define MOVE_MAX 4
35d965d5 2325
d19fb8e3 2326#undef MOVE_RATIO
591af218 2327#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2328
ff9940b0
RE		 2329/* Define if operations between registers always perform the operation
2330 on the full register even if a narrower mode is specified. */
2331#define WORD_REGISTER_OPERATIONS
2332
2333/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2334 will either zero-extend or sign-extend. The value of this macro should
2335 be the code that says which one of the two operations is implicitly
f822d252 2336 done, UNKNOWN if none. */
9c872872 2337#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2338 (TARGET_THUMB ? ZERO_EXTEND : \
2339 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2340 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2341
35d965d5
RS		 2342/* Nonzero if access to memory by bytes is slow and undesirable. */
2343#define SLOW_BYTE_ACCESS 0
2344
d5b7b3ae 2345#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2346
35d965d5
RS		 2347/* Immediate shift counts are truncated by the output routines (or was it
2348 the assembler?). Shift counts in a register are truncated by ARM. Note
2349 that the native compiler puts too large (> 32) immediate shift counts
2350 into a register and shifts by the register, letting the ARM decide what
2351 to do instead of doing that itself. */
ff9940b0
RE		 2352/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2353 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2354 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2355 rotates is modulo 32 used. */
ff9940b0 2356/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2357
35d965d5 2358/* All integers have the same format so truncation is easy. */
d5b7b3ae 2359#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2360
2361/* Calling from registers is a massive pain. */
2362#define NO_FUNCTION_CSE 1
2363
35d965d5
RS		 2364/* The machine modes of pointers and functions */
2365#define Pmode SImode
2366#define FUNCTION_MODE Pmode
2367
d5b7b3ae
RE		 2368#define ARM_FRAME_RTX(X) \
2369 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2370 || (X) == arg_pointer_rtx)
2371
ff9940b0 2372/* Moves to and from memory are quite expensive */
d5b7b3ae
RE		 2373#define MEMORY_MOVE_COST(M, CLASS, IN) \
2374 (TARGET_ARM ? 10 : \
2375 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2376 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2377
ff9940b0
RE		 2378/* Try to generate sequences that don't involve branches, we can then use
2379 conditional instructions */
d5b7b3ae
RE		 2380#define BRANCH_COST \
2381 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
7a801826
RE		 2382\f
2383/* Position Independent Code. */
2384/* We decide which register to use based on the compilation options and
2385 the assembler in use; this is more general than the APCS restriction of
2386 using sb (r9) all the time. */
2387extern int arm_pic_register;
2388
ed0e6530
PB		 2389/* Used when parsing command line option -mpic-register=. */
2390extern const char * arm_pic_register_string;
2391
7a801826
RE		 2392/* The register number of the register used to address a table of static
2393 data addresses in memory. */
2394#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2395
f5a1b0d2
NC		 2396/* We can't directly access anything that contains a symbol,
2397 nor can we indirect via the constant pool. */
82e9d970 2398#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2399 (!(symbol_mentioned_p (X) \
2400 || label_mentioned_p (X) \
2401 || (GET_CODE (X) == SYMBOL_REF \
2402 && CONSTANT_POOL_ADDRESS_P (X) \
2403 && (symbol_mentioned_p (get_pool_constant (X)) \
2404 || label_mentioned_p (get_pool_constant (X))))))
2405
13bd191d
PB		 2406/* We need to know when we are making a constant pool; this determines
2407 whether data needs to be in the GOT or can be referenced via a GOT
2408 offset. */
2409extern int making_const_table;
82e9d970 2410\f
c27ba912 2411/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2412#define REGISTER_TARGET_PRAGMAS() do { \
2413 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2414 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2415 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2416} while (0)
2417
d6b4baa4 2418/* Condition code information. */
ff9940b0 2419/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2420 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2421
2422#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2423
880873be
RE		 2424#define REVERSIBLE_CC_MODE(MODE) 1
2425
2426#define REVERSE_CONDITION(CODE,MODE) \
2427 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2428 ? reverse_condition_maybe_unordered (code) \
2429 : reverse_condition (code))
008cf58a 2430
62b10bbc
NC		 2431#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2432 do \
2433 { \
2434 if (GET_CODE (OP1) == CONST_INT \
2435 && ! (const_ok_for_arm (INTVAL (OP1)) \
2436 || (const_ok_for_arm (- INTVAL (OP1))))) \
2437 { \
2438 rtx const_op = OP1; \
2439 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2440 OP1 = const_op; \
2441 } \
2442 } \
2443 while (0)
62dd06ea 2444
7dba8395
RH		 2445/* The arm5 clz instruction returns 32. */
2446#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2447\f
d5b7b3ae
RE		 2448#undef ASM_APP_OFF
2449#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
35d965d5 2450
35d965d5 2451/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2452#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2453 do \
2454 { \
2455 if (TARGET_ARM) \
2456 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2457 STACK_POINTER_REGNUM, REGNO); \
2458 else \
2459 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2460 } while (0)
d5b7b3ae
RE		 2461
2462
2463#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2464 do \
2465 { \
2466 if (TARGET_ARM) \
2467 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2468 STACK_POINTER_REGNUM, REGNO); \
2469 else \
2470 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2471 } while (0)
d5b7b3ae
RE		 2472
2473/* This is how to output a label which precedes a jumptable. Since
2474 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2475#undef ASM_OUTPUT_CASE_LABEL
d5b7b3ae
RE		 2476#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2477 do \
2478 { \
2479 if (TARGET_THUMB) \
2480 ASM_OUTPUT_ALIGN (FILE, 2); \
8a81cc45 2481 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
d5b7b3ae
RE		 2482 } \
2483 while (0)
35d965d5 2484
6cfc7210
NC		 2485#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2486 do \
2487 { \
d5b7b3ae
RE		 2488 if (TARGET_THUMB) \
2489 { \
9b66ebb1
PB		 2490 if (is_called_in_ARM_mode (DECL) \
2491 || current_function_is_thunk) \
d5b7b3ae
RE		 2492 fprintf (STREAM, "\t.code 32\n") ; \
2493 else \
9b66ebb1 2494 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
d5b7b3ae 2495 } \
6cfc7210 2496 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2497 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2498 } \
2499 while (0)
35d965d5 2500
d5b7b3ae
RE		 2501/* For aliases of functions we use .thumb_set instead. */
2502#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2503 do \
2504 { \
91ea4f8d
KG		 2505 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2506 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2507 \
2508 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2509 { \
2510 fprintf (FILE, "\t.thumb_set "); \
2511 assemble_name (FILE, LABEL1); \
2512 fprintf (FILE, ","); \
2513 assemble_name (FILE, LABEL2); \
2514 fprintf (FILE, "\n"); \
2515 } \
2516 else \
2517 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2518 } \
2519 while (0)
2520
fdc2d3b0
NC		 2521#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2522/* To support -falign-* switches we need to use .p2align so
2523 that alignment directives in code sections will be padded
2524 with no-op instructions, rather than zeroes. */
5a9335ef 2525#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2526 if ((LOG) != 0) \
2527 { \
2528 if ((MAX_SKIP) == 0) \
5a9335ef 2529 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2530 else \
2531 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2532 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2533 }
2534#endif
35d965d5 2535\f
35d965d5 2536/* Only perform branch elimination (by making instructions conditional) if
72ac76be 2537 we're optimizing. Otherwise it's of no use anyway. */
d5b7b3ae
RE		 2538#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2539 if (TARGET_ARM && optimize) \
2540 arm_final_prescan_insn (INSN); \
2541 else if (TARGET_THUMB) \
2542 thumb_final_prescan_insn (INSN)
35d965d5 2543
7bc7696c 2544#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
d5b7b3ae
RE		 2545 (CODE == '@' || CODE == '|' \
2546 || (TARGET_ARM && (CODE == '?')) \
2547 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2548
7bc7696c 2549/* Output an operand of an instruction. */
35d965d5 2550#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2551 arm_print_operand (STREAM, X, CODE)
2552
7b8b8ade
NC		 2553#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2554 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2555 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2556 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2557 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2558 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2559 : 0))))
35d965d5
RS		 2560
2561/* Output the address of an operand. */
3cd45774
RE		 2562#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2563{ \
2564 int is_minus = GET_CODE (X) == MINUS; \
2565 \
2566 if (GET_CODE (X) == REG) \
2567 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2568 else if (GET_CODE (X) == PLUS || is_minus) \
2569 { \
2570 rtx base = XEXP (X, 0); \
2571 rtx index = XEXP (X, 1); \
2572 HOST_WIDE_INT offset = 0; \
2573 if (GET_CODE (base) != REG) \
2574 { \
d6b4baa4
KH		 2575 /* Ensure that BASE is a register. */ \
2576 /* (one of them must be). */ \
3cd45774
RE		 2577 rtx temp = base; \
2578 base = index; \
2579 index = temp; \
2580 } \
2581 switch (GET_CODE (index)) \
2582 { \
2583 case CONST_INT: \
2584 offset = INTVAL (index); \
2585 if (is_minus) \
2586 offset = -offset; \
c53dddc2 2587 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2588 REGNO (base), offset); \
2589 break; \
2590 \
2591 case REG: \
2592 asm_fprintf (STREAM, "[%r, %s%r]", \
2593 REGNO (base), is_minus ? "-" : "", \
2594 REGNO (index)); \
2595 break; \
2596 \
2597 case MULT: \
2598 case ASHIFTRT: \
2599 case LSHIFTRT: \
2600 case ASHIFT: \
2601 case ROTATERT: \
2602 { \
2603 asm_fprintf (STREAM, "[%r, %s%r", \
2604 REGNO (base), is_minus ? "-" : "", \
2605 REGNO (XEXP (index, 0))); \
2606 arm_print_operand (STREAM, index, 'S'); \
2607 fputs ("]", STREAM); \
2608 break; \
2609 } \
2610 \
2611 default: \
e6d29d15 2612 gcc_unreachable (); \
3cd45774
RE		 2613 } \
2614 } \
2615 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2616 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2617 { \
2618 extern enum machine_mode output_memory_reference_mode; \
2619 \
e6d29d15 2620 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
3cd45774
RE		 2621 \
2622 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2623 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2624 REGNO (XEXP (X, 0)), \
2625 GET_CODE (X) == PRE_DEC ? "-" : "", \
2626 GET_MODE_SIZE (output_memory_reference_mode)); \
2627 else \
2628 asm_fprintf (STREAM, "[%r], #%s%d", \
2629 REGNO (XEXP (X, 0)), \
2630 GET_CODE (X) == POST_DEC ? "-" : "", \
2631 GET_MODE_SIZE (output_memory_reference_mode)); \
2632 } \
2633 else if (GET_CODE (X) == PRE_MODIFY) \
2634 { \
2635 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2636 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2637 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2638 INTVAL (XEXP (XEXP (X, 1), 1))); \
2639 else \
2640 asm_fprintf (STREAM, "%r]!", \
2641 REGNO (XEXP (XEXP (X, 1), 1))); \
2642 } \
2643 else if (GET_CODE (X) == POST_MODIFY) \
2644 { \
2645 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2646 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2647 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2648 INTVAL (XEXP (XEXP (X, 1), 1))); \
2649 else \
2650 asm_fprintf (STREAM, "%r", \
2651 REGNO (XEXP (XEXP (X, 1), 1))); \
2652 } \
2653 else output_addr_const (STREAM, X); \
35d965d5 2654}
62dd06ea 2655
d5b7b3ae
RE		 2656#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2657{ \
2658 if (GET_CODE (X) == REG) \
2659 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2660 else if (GET_CODE (X) == POST_INC) \
2661 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2662 else if (GET_CODE (X) == PLUS) \
2663 { \
e6d29d15 2664 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
d5b7b3ae 2665 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2666 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2667 REGNO (XEXP (X, 0)), \
659bdc68 2668 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2669 else \
2670 asm_fprintf (STREAM, "[%r, %r]", \
2671 REGNO (XEXP (X, 0)), \
2672 REGNO (XEXP (X, 1))); \
2673 } \
2674 else \
2675 output_addr_const (STREAM, X); \
2676}
2677
2678#define PRINT_OPERAND_ADDRESS(STREAM, X) \
2679 if (TARGET_ARM) \
2680 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2681 else \
2682 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef
NC		 2683
2684#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2685 if (GET_CODE (X) != CONST_VECTOR \
2686 || ! arm_emit_vector_const (FILE, X)) \
2687 goto FAIL;
2688
6a5d7526
MS		 2689/* A C expression whose value is RTL representing the value of the return
2690 address for the frame COUNT steps up from the current frame. */
2691
d5b7b3ae
RE		 2692#define RETURN_ADDR_RTX(COUNT, FRAME) \
2693 arm_return_addr (COUNT, FRAME)
2694
f676971a 2695/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2696 when running in 26-bit mode. */
2697#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2698
2c849145
JM		 2699/* Pick up the return address upon entry to a procedure. Used for
2700 dwarf2 unwind information. This also enables the table driven
2701 mechanism. */
2c849145
JM		 2702#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2703#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2704
39950dff
MS		 2705/* Used to mask out junk bits from the return address, such as
2706 processor state, interrupt status, condition codes and the like. */
2707#define MASK_RETURN_ADDR \
2708 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2709 in 26 bit mode, the condition codes must be masked out of the \
2710 return address. This does not apply to ARM6 and later processors \
2711 when running in 32 bit mode. */ \
61f0ccff
RE		 2712 ((arm_arch4 || TARGET_THUMB) \
2713 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2714 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2715
2716\f
5a9335ef
NC		 2717enum arm_builtins
2718{
2719 ARM_BUILTIN_GETWCX,
2720 ARM_BUILTIN_SETWCX,
2721
2722 ARM_BUILTIN_WZERO,
2723
2724 ARM_BUILTIN_WAVG2BR,
2725 ARM_BUILTIN_WAVG2HR,
2726 ARM_BUILTIN_WAVG2B,
2727 ARM_BUILTIN_WAVG2H,
2728
2729 ARM_BUILTIN_WACCB,
2730 ARM_BUILTIN_WACCH,
2731 ARM_BUILTIN_WACCW,
2732
2733 ARM_BUILTIN_WMACS,
2734 ARM_BUILTIN_WMACSZ,
2735 ARM_BUILTIN_WMACU,
2736 ARM_BUILTIN_WMACUZ,
2737
2738 ARM_BUILTIN_WSADB,
2739 ARM_BUILTIN_WSADBZ,
2740 ARM_BUILTIN_WSADH,
2741 ARM_BUILTIN_WSADHZ,
2742
2743 ARM_BUILTIN_WALIGN,
2744
2745 ARM_BUILTIN_TMIA,
2746 ARM_BUILTIN_TMIAPH,
2747 ARM_BUILTIN_TMIABB,
2748 ARM_BUILTIN_TMIABT,
2749 ARM_BUILTIN_TMIATB,
2750 ARM_BUILTIN_TMIATT,
2751
2752 ARM_BUILTIN_TMOVMSKB,
2753 ARM_BUILTIN_TMOVMSKH,
2754 ARM_BUILTIN_TMOVMSKW,
2755
2756 ARM_BUILTIN_TBCSTB,
2757 ARM_BUILTIN_TBCSTH,
2758 ARM_BUILTIN_TBCSTW,
2759
2760 ARM_BUILTIN_WMADDS,
2761 ARM_BUILTIN_WMADDU,
2762
2763 ARM_BUILTIN_WPACKHSS,
2764 ARM_BUILTIN_WPACKWSS,
2765 ARM_BUILTIN_WPACKDSS,
2766 ARM_BUILTIN_WPACKHUS,
2767 ARM_BUILTIN_WPACKWUS,
2768 ARM_BUILTIN_WPACKDUS,
2769
2770 ARM_BUILTIN_WADDB,
2771 ARM_BUILTIN_WADDH,
2772 ARM_BUILTIN_WADDW,
2773 ARM_BUILTIN_WADDSSB,
2774 ARM_BUILTIN_WADDSSH,
2775 ARM_BUILTIN_WADDSSW,
2776 ARM_BUILTIN_WADDUSB,
2777 ARM_BUILTIN_WADDUSH,
2778 ARM_BUILTIN_WADDUSW,
2779 ARM_BUILTIN_WSUBB,
2780 ARM_BUILTIN_WSUBH,
2781 ARM_BUILTIN_WSUBW,
2782 ARM_BUILTIN_WSUBSSB,
2783 ARM_BUILTIN_WSUBSSH,
2784 ARM_BUILTIN_WSUBSSW,
2785 ARM_BUILTIN_WSUBUSB,
2786 ARM_BUILTIN_WSUBUSH,
2787 ARM_BUILTIN_WSUBUSW,
2788
2789 ARM_BUILTIN_WAND,
2790 ARM_BUILTIN_WANDN,
2791 ARM_BUILTIN_WOR,
2792 ARM_BUILTIN_WXOR,
2793
2794 ARM_BUILTIN_WCMPEQB,
2795 ARM_BUILTIN_WCMPEQH,
2796 ARM_BUILTIN_WCMPEQW,
2797 ARM_BUILTIN_WCMPGTUB,
2798 ARM_BUILTIN_WCMPGTUH,
2799 ARM_BUILTIN_WCMPGTUW,
2800 ARM_BUILTIN_WCMPGTSB,
2801 ARM_BUILTIN_WCMPGTSH,
2802 ARM_BUILTIN_WCMPGTSW,
2803
2804 ARM_BUILTIN_TEXTRMSB,
2805 ARM_BUILTIN_TEXTRMSH,
2806 ARM_BUILTIN_TEXTRMSW,
2807 ARM_BUILTIN_TEXTRMUB,
2808 ARM_BUILTIN_TEXTRMUH,
2809 ARM_BUILTIN_TEXTRMUW,
2810 ARM_BUILTIN_TINSRB,
2811 ARM_BUILTIN_TINSRH,
2812 ARM_BUILTIN_TINSRW,
2813
2814 ARM_BUILTIN_WMAXSW,
2815 ARM_BUILTIN_WMAXSH,
2816 ARM_BUILTIN_WMAXSB,
2817 ARM_BUILTIN_WMAXUW,
2818 ARM_BUILTIN_WMAXUH,
2819 ARM_BUILTIN_WMAXUB,
2820 ARM_BUILTIN_WMINSW,
2821 ARM_BUILTIN_WMINSH,
2822 ARM_BUILTIN_WMINSB,
2823 ARM_BUILTIN_WMINUW,
2824 ARM_BUILTIN_WMINUH,
2825 ARM_BUILTIN_WMINUB,
2826
f07a6b21
BE		 2827 ARM_BUILTIN_WMULUM,
2828 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2829 ARM_BUILTIN_WMULUL,
2830
2831 ARM_BUILTIN_PSADBH,
2832 ARM_BUILTIN_WSHUFH,
2833
2834 ARM_BUILTIN_WSLLH,
2835 ARM_BUILTIN_WSLLW,
2836 ARM_BUILTIN_WSLLD,
2837 ARM_BUILTIN_WSRAH,
2838 ARM_BUILTIN_WSRAW,
2839 ARM_BUILTIN_WSRAD,
2840 ARM_BUILTIN_WSRLH,
2841 ARM_BUILTIN_WSRLW,
2842 ARM_BUILTIN_WSRLD,
2843 ARM_BUILTIN_WRORH,
2844 ARM_BUILTIN_WRORW,
2845 ARM_BUILTIN_WRORD,
2846 ARM_BUILTIN_WSLLHI,
2847 ARM_BUILTIN_WSLLWI,
2848 ARM_BUILTIN_WSLLDI,
2849 ARM_BUILTIN_WSRAHI,
2850 ARM_BUILTIN_WSRAWI,
2851 ARM_BUILTIN_WSRADI,
2852 ARM_BUILTIN_WSRLHI,
2853 ARM_BUILTIN_WSRLWI,
2854 ARM_BUILTIN_WSRLDI,
2855 ARM_BUILTIN_WRORHI,
2856 ARM_BUILTIN_WRORWI,
2857 ARM_BUILTIN_WRORDI,
2858
2859 ARM_BUILTIN_WUNPCKIHB,
2860 ARM_BUILTIN_WUNPCKIHH,
2861 ARM_BUILTIN_WUNPCKIHW,
2862 ARM_BUILTIN_WUNPCKILB,
2863 ARM_BUILTIN_WUNPCKILH,
2864 ARM_BUILTIN_WUNPCKILW,
2865
2866 ARM_BUILTIN_WUNPCKEHSB,
2867 ARM_BUILTIN_WUNPCKEHSH,
2868 ARM_BUILTIN_WUNPCKEHSW,
2869 ARM_BUILTIN_WUNPCKEHUB,
2870 ARM_BUILTIN_WUNPCKEHUH,
2871 ARM_BUILTIN_WUNPCKEHUW,
2872 ARM_BUILTIN_WUNPCKELSB,
2873 ARM_BUILTIN_WUNPCKELSH,
2874 ARM_BUILTIN_WUNPCKELSW,
2875 ARM_BUILTIN_WUNPCKELUB,
2876 ARM_BUILTIN_WUNPCKELUH,
2877 ARM_BUILTIN_WUNPCKELUW,
2878
2879 ARM_BUILTIN_MAX
2880};
88657302 2881#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git