]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/arm/arm.h
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pex-common.c: New file.
[thirdparty/gcc.git] / gcc / config / arm / arm.h
CommitLineData
f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
b12a00f1 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245
NC		 21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
35fd3193 29/* The architecture define. */
78011587
PB		 30extern char arm_arch_name[];
31
e6471be6
NB		 32/* Target CPU builtins. */
33#define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
9b66ebb1
PB		 36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
61f0ccff 39 builtin_define ("__APCS_32__"); \
9b66ebb1 40 if (TARGET_THUMB) \
e6471be6
NB		 41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
e6471be6
NB		 58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
9b66ebb1 61 if (TARGET_VFP) \
b5b620a4
JT		 62 builtin_define ("__VFP_FP__"); \
63 \
e6471be6
NB		 64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
2ad4dcf9 66 if (arm_cpp_interwork) \
e6471be6
NB		 67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
78011587
PB		 71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 81 } while (0)
82
9b66ebb1
PB		 83/* The various ARM cores. */
84enum processor_type
85{
d98a72fd
RE		 86#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
9b66ebb1
PB		 88#include "arm-cores.def"
89#undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92};
93
78011587
PB		 94enum target_cpus
95{
d98a72fd
RE		 96#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
78011587
PB		 98#include "arm-cores.def"
99#undef ARM_CORE
100 TARGET_CPU_generic
101};
102
9b66ebb1
PB		 103/* The processor for which instructions should be scheduled. */
104extern enum processor_type arm_tune;
105
d5b7b3ae 106typedef enum arm_cond_code
89c7ca52
RE		 107{
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 110}
111arm_cc;
6cfc7210 112
d5b7b3ae 113extern arm_cc arm_current_cc;
ff9940b0 114
d5b7b3ae 115#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 116
6cfc7210
NC		 117extern int arm_target_label;
118extern int arm_ccfsm_state;
e2500fed 119extern GTY(()) rtx arm_target_insn;
6cfc7210
NC		 120/* Run-time compilation parameters selecting different hardware subsets. */
121extern int target_flags;
9b66ebb1
PB		 122/* The floating point mode. */
123extern const char *target_fpu_name;
59b9a953 124/* For backwards compatibility. */
9b66ebb1
PB		 125extern const char *target_fpe_name;
126/* Whether to use floating point hardware. */
127extern const char *target_float_abi_name;
3d8532aa
PB		 128/* For -m{soft,hard}-float. */
129extern const char *target_float_switch;
5848830f
PB		 130/* Which ABI to use. */
131extern const char *target_abi_name;
d5b7b3ae 132/* Define the information needed to generate branch insns. This is
e2500fed
GK		 133 stored from the compare operation. */
134extern GTY(()) rtx arm_compare_op0;
135extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 136/* The label of the current constant pool. */
e2500fed 137extern rtx pool_vector_label;
d5b7b3ae 138/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 139 is not needed. */
d5b7b3ae 140extern int return_used_this_function;
e2500fed
GK		 141/* Used to produce AOF syntax assembler. */
142extern GTY(()) rtx aof_pic_label;
35d965d5 143\f
d6b4baa4 144/* Just in case configure has failed to define anything. */
7a801826
RE		 145#ifndef TARGET_CPU_DEFAULT
146#define TARGET_CPU_DEFAULT TARGET_CPU_generic
147#endif
148
7a801826 149
5742588d 150#undef CPP_SPEC
78011587 151#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 152%{msoft-float:%{mhard-float: \
153 %e-msoft-float and -mhard_float may not be used together}} \
154%{mbig-endian:%{mlittle-endian: \
155 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 156
be393ecf 157#ifndef CC1_SPEC
dfa08768 158#define CC1_SPEC ""
be393ecf 159#endif
7a801826
RE		 160
161/* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
164
165 Each subgrouping contains a string constant, that defines the
4f448245 166 specification name, and a string constant that used by the GCC driver
7a801826
RE		 167 program.
168
169 Do not define this macro if it does not need to do anything. */
170#define EXTRA_SPECS \
38fc909b 171 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 172 SUBTARGET_EXTRA_SPECS
173
914a3b8c 174#ifndef SUBTARGET_EXTRA_SPECS
7a801826 175#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 176#endif
177
6cfc7210 178#ifndef SUBTARGET_CPP_SPEC
38fc909b 179#define SUBTARGET_CPP_SPEC ""
6cfc7210 180#endif
35d965d5
RS		 181\f
182/* Run-time Target Specification. */
ff9940b0 183#ifndef TARGET_VERSION
6cfc7210 184#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 185#endif
35d965d5 186
35d965d5
RS		 187/* Nonzero if the function prologue (and epilogue) should obey
188 the ARM Procedure Call Standard. */
6cfc7210 189#define ARM_FLAG_APCS_FRAME (1 << 0)
35d965d5
RS		 190
191/* Nonzero if the function prologue should output the function name to enable
192 the post mortem debugger to print a backtrace (very useful on RISCOS,
11c1a207
RE		 193 unused on RISCiX). Specifying this flag also enables
194 -fno-omit-frame-pointer.
35d965d5 195 XXX Must still be implemented in the prologue. */
6cfc7210 196#define ARM_FLAG_POKE (1 << 1)
35d965d5
RS		 197
198/* Nonzero if floating point instructions are emulated by the FPE, in which
199 case instruction scheduling becomes very uninteresting. */
6cfc7210 200#define ARM_FLAG_FPE (1 << 2)
35d965d5 201
61f0ccff 202/* FLAG 0x0008 now spare (used to be apcs-32 selection). */
dfa08768 203
11c1a207
RE		 204/* Nonzero if stack checking should be performed on entry to each function
205 which allocates temporary variables on the stack. */
6cfc7210 206#define ARM_FLAG_APCS_STACK (1 << 4)
11c1a207
RE		 207
208/* Nonzero if floating point parameters should be passed to functions in
209 floating point registers. */
6cfc7210 210#define ARM_FLAG_APCS_FLOAT (1 << 5)
11c1a207
RE		 211
212/* Nonzero if re-entrant, position independent code should be generated.
213 This is equivalent to -fpic. */
6cfc7210 214#define ARM_FLAG_APCS_REENT (1 << 6)
11c1a207 215
61f0ccff 216 /* FLAG 0x0080 now spare (used to be alignment traps). */
3d8532aa 217 /* FLAG (1 << 8) is now spare (used to be soft-float). */
11c1a207
RE		 218
219/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
6cfc7210 220#define ARM_FLAG_BIG_END (1 << 9)
11c1a207
RE		 221
222/* Nonzero if we should compile for Thumb interworking. */
6cfc7210 223#define ARM_FLAG_INTERWORK (1 << 10)
11c1a207 224
ddee6aba
RE		 225/* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
6cfc7210 227#define ARM_FLAG_LITTLE_WORDS (1 << 11)
ddee6aba 228
f5a1b0d2 229/* Nonzero if we need to protect the prolog from scheduling */
6cfc7210 230#define ARM_FLAG_NO_SCHED_PRO (1 << 12)
f5a1b0d2 231
f676971a 232/* Nonzero if a call to abort should be generated if a noreturn
dd18ae56 233 function tries to return. */
6cfc7210 234#define ARM_FLAG_ABORT_NORETURN (1 << 13)
c11145f6 235
d6b4baa4 236/* Nonzero if function prologues should not load the PIC register. */
dd18ae56 237#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
ed0e6530 238
b020fd92
NC		 239/* Nonzero if all call instructions should be indirect. */
240#define ARM_FLAG_LONG_CALLS (1 << 15)
f676971a 241
d5b7b3ae
RE		 242/* Nonzero means that the target ISA is the THUMB, not the ARM. */
243#define ARM_FLAG_THUMB (1 << 16)
244
245/* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247#define THUMB_FLAG_BACKTRACE (1 << 17)
b020fd92 248
d5b7b3ae
RE		 249/* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253/* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257/* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
9b6b54e2 261/* Fix invalid Cirrus instruction combinations by inserting NOPs. */
5848830f 262#define CIRRUS_FIX_INVALID_INSNS (1 << 21)
9b6b54e2 263
d5b7b3ae 264#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
11c1a207
RE		 265#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266#define TARGET_FPE (target_flags & ARM_FLAG_FPE)
11c1a207
RE		 267#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
9b66ebb1 270#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 271/* Use hardware floating point instructions. */
272#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273/* Use hardware floating point calling convention. */
274#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 275#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef
NC		 278#define TARGET_IWMMXT (arm_arch_iwmmxt)
279#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
5848830f 280#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
11c1a207 281#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
6cfc7210 282#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
ddee6aba 283#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
f5a1b0d2 284#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
dd18ae56 285#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
ed0e6530 286#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
b020fd92 287#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
d5b7b3ae
RE		 288#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289#define TARGET_ARM (! TARGET_THUMB)
290#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293#define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
9b6b54e2 296#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
fdd695fd 297#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 298#define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 300
b3f8d95d
MM		 301/* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
305#ifndef TARGET_BPABI
306#define TARGET_BPABI false
f676971a 307#endif
b3f8d95d 308
c7bdf0a6 309/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
3ada8e17
DE		 310#ifndef SUBTARGET_SWITCHES
311#define SUBTARGET_SWITCHES
ff9940b0
RE		 312#endif
313
047142d3
PT		 314#define TARGET_SWITCHES \
315{ \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
047142d3
PT		 324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
047142d3
PT		 332 {"big-endian", ARM_FLAG_BIG_END, \
333 N_("Assume target CPU is configured as big endian") }, \
334 {"little-endian", -ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as little endian") }, \
336 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
337 N_("Assume big endian bytes, little endian words") }, \
338 {"thumb-interwork", ARM_FLAG_INTERWORK, \
b605cfa8 339 N_("Support calls between Thumb and ARM instruction sets") }, \
047142d3
PT		 340 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
341 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
342 N_("Generate a call to abort if a noreturn function returns")}, \
343 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
b605cfa8 344 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
047142d3 345 N_("Do not move instructions into a function's prologue") }, \
b605cfa8 346 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
047142d3
PT		 347 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
348 N_("Do not load the PIC register in function prologues") }, \
349 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
350 {"long-calls", ARM_FLAG_LONG_CALLS, \
351 N_("Generate call insns as indirect calls, if necessary") }, \
352 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
353 {"thumb", ARM_FLAG_THUMB, \
354 N_("Compile for the Thumb not the ARM") }, \
355 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
356 {"arm", -ARM_FLAG_THUMB, "" }, \
357 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
358 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
359 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
360 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
361 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
362 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
363 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
364 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
365 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
366 "" }, \
367 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
368 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
369 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
370 "" }, \
9b6b54e2
NC		 371 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
372 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
373 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
047142d3
PT		 375 SUBTARGET_SWITCHES \
376 {"", TARGET_DEFAULT, "" } \
35d965d5
RS		 377}
378
9b66ebb1
PB		 379#define TARGET_OPTIONS \
380{ \
381 {"cpu=", & arm_select[0].string, \
382 N_("Specify the name of the target CPU"), 0}, \
383 {"arch=", & arm_select[1].string, \
384 N_("Specify the name of the target architecture"), 0}, \
385 {"tune=", & arm_select[2].string, "", 0}, \
386 {"fpe=", & target_fpe_name, "", 0}, \
387 {"fp=", & target_fpe_name, "", 0}, \
388 {"fpu=", & target_fpu_name, \
389 N_("Specify the name of the target floating point hardware/format"), 0}, \
390 {"float-abi=", & target_float_abi_name, \
391 N_("Specify if floating point hardware should be used"), 0}, \
392 {"structure-size-boundary=", & structure_size_string, \
393 N_("Specify the minimum bit alignment of structures"), 0}, \
394 {"pic-register=", & arm_pic_register_string, \
5848830f 395 N_("Specify the register to be used for PIC addressing"), 0}, \
3d8532aa
PB		 396 {"abi=", &target_abi_name, N_("Specify an ABI"), 0}, \
397 {"soft-float", &target_float_switch, \
712ecf4d 398 N_("Alias for -mfloat-abi=soft"), "s"}, \
3d8532aa 399 {"hard-float", &target_float_switch, \
712ecf4d 400 N_("Alias for -mfloat-abi=hard"), "h"} \
11c1a207 401}
ff9940b0 402
7816bea0
DJ		 403/* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
406 by --with-arch.
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
408 by -march).
9b66ebb1
PB		 409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
410 specified.
5848830f
PB		 411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 413#define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 417 {"float", \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f
PB		 419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
7816bea0 421
62dd06ea
RE		 422struct arm_cpu_select
423{
f9cc092a
RE		 424 const char * string;
425 const char * name;
426 const struct processors * processors;
62dd06ea
RE		 427};
428
f5a1b0d2
NC		 429/* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
62dd06ea
RE		 432extern struct arm_cpu_select arm_select[];
433
9b66ebb1
PB		 434/* Which floating point model to use. */
435enum arm_fp_model
436{
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
439 ARM_FP_MODEL_FPA,
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
443 ARM_FP_MODEL_VFP
444};
445
446extern enum arm_fp_model arm_fp_model;
447
448/* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 450enum fputype
24f0c1b4 451{
9b66ebb1
PB		 452 /* No FP hardware. */
453 FPUTYPE_NONE,
29ad9694
RE		 454 /* Full FPA support. */
455 FPUTYPE_FPA,
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
457 FPUTYPE_FPA_EMU2,
458 /* Emulated FPA hardware, Issue 3 emulator. */
459 FPUTYPE_FPA_EMU3,
460 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 461 FPUTYPE_MAVERICK,
462 /* VFP. */
463 FPUTYPE_VFP
24f0c1b4
RE		 464};
465
466/* Recast the floating point class to be the floating point attribute. */
29ad9694 467#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 468
71791e16 469/* What type of floating point to tune for */
29ad9694 470extern enum fputype arm_fpu_tune;
24f0c1b4 471
71791e16 472/* What type of floating point instructions are available */
29ad9694 473extern enum fputype arm_fpu_arch;
71791e16 474
9b66ebb1
PB		 475enum float_abi_type
476{
477 ARM_FLOAT_ABI_SOFT,
478 ARM_FLOAT_ABI_SOFTFP,
479 ARM_FLOAT_ABI_HARD
480};
481
482extern enum float_abi_type arm_float_abi;
483
3d8532aa
PB		 484#ifndef TARGET_DEFAULT_FLOAT_ABI
485#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
486#endif
487
5848830f
PB		 488/* Which ABI to use. */
489enum arm_abi_type
490{
491 ARM_ABI_APCS,
492 ARM_ABI_ATPCS,
493 ARM_ABI_AAPCS,
494 ARM_ABI_IWMMXT
495};
496
497extern enum arm_abi_type arm_abi;
498
499#ifndef ARM_DEFAULT_ABI
500#define ARM_DEFAULT_ABI ARM_ABI_APCS
501#endif
502
9b66ebb1
PB		 503/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504extern int arm_arch3m;
11c1a207 505
9b66ebb1 506/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 507extern int arm_arch4;
508
68d560d4
RE		 509/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
510extern int arm_arch4t;
511
9b66ebb1 512/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 513extern int arm_arch5;
514
9b66ebb1 515/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 516extern int arm_arch5e;
517
9b66ebb1
PB		 518/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519extern int arm_arch6;
520
f5a1b0d2
NC		 521/* Nonzero if this chip can benefit from load scheduling. */
522extern int arm_ld_sched;
523
0616531f
RE		 524/* Nonzero if generating thumb code. */
525extern int thumb_code;
526
f5a1b0d2
NC		 527/* Nonzero if this chip is a StrongARM. */
528extern int arm_is_strong;
529
9b6b54e2 530/* Nonzero if this chip is a Cirrus variant. */
78011587 531extern int arm_arch_cirrus;
9b6b54e2 532
5a9335ef
NC		 533/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534extern int arm_arch_iwmmxt;
535
d19fb8e3 536/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 537extern int arm_arch_xscale;
538
539/* Nonzero if tuning for XScale */
540extern int arm_tune_xscale;
d19fb8e3 541
3569057d 542/* Nonzero if this chip is an ARM6 or an ARM7. */
f5a1b0d2
NC		 543extern int arm_is_6_or_7;
544
2ad4dcf9 545/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 546 preprocessor.
2ad4dcf9
RE		 547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550extern int arm_cpp_interwork;
551
2ce9c1b9 552#ifndef TARGET_DEFAULT
d5b7b3ae 553#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
2ce9c1b9 554#endif
35d965d5 555
11c1a207
RE		 556/* The frame pointer register used in gcc has nothing to do with debugging;
557 that is controlled by the APCS-FRAME option. */
d5b7b3ae 558#define CAN_DEBUG_WITHOUT_FP
35d965d5 559
11c1a207 560#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 561
562/* Nonzero if PIC code requires explicit qualifiers to generate
563 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 564 Subtargets can override these if required. */
565#ifndef NEED_GOT_RELOC
566#define NEED_GOT_RELOC 0
567#endif
568#ifndef NEED_PLT_RELOC
569#define NEED_PLT_RELOC 0
e2723c62 570#endif
84306176
PB		 571
572/* Nonzero if we need to refer to the GOT with a PC-relative
573 offset. In other words, generate
574
f676971a 575 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 576
577 rather than
578
579 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
580
f676971a 581 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 582 override this if required. */
583#ifndef GOT_PCREL
584#define GOT_PCREL 1
585#endif
35d965d5
RS		 586\f
587/* Target machine storage Layout. */
588
ff9940b0
RE		 589
590/* Define this macro if it is advisable to hold scalars in registers
591 in a wider mode than that declared by the program. In such cases,
592 the value is constrained to be within the bounds of the declared
593 type, but kept valid in the wider mode. The signedness of the
594 extension may differ from that of the type. */
595
596/* It is far faster to zero extend chars than to sign extend them */
597
6cfc7210 598#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 599 if (GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < 4) \
601 { \
602 if (MODE == QImode) \
603 UNSIGNEDP = 1; \
604 else if (MODE == HImode) \
61f0ccff 605 UNSIGNEDP = 1; \
2ce9c1b9 606 (MODE) = SImode; \
ff9940b0
RE		 607 }
608
d4453b7a
PB		 609#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
610 if (GET_MODE_CLASS (MODE) == MODE_INT \
611 && GET_MODE_SIZE (MODE) < 4) \
612 (MODE) = SImode; \
613
35d965d5
RS		 614/* Define this if most significant bit is lowest numbered
615 in instructions that operate on numbered bit-fields. */
616#define BITS_BIG_ENDIAN 0
617
f676971a 618/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 619 Most ARM processors are run in little endian mode, so that is the default.
620 If you want to have it run-time selectable, change the definition in a
621 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 622#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 623
624/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 625 numbered.
626 This is always false, even when in big-endian mode. */
ddee6aba
RE		 627#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
628
629/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
630 on processor pre-defineds when compiling libgcc2.c. */
631#if defined(__ARMEB__) && !defined(__ARMWEL__)
632#define LIBGCC2_WORDS_BIG_ENDIAN 1
633#else
634#define LIBGCC2_WORDS_BIG_ENDIAN 0
635#endif
35d965d5 636
11c1a207 637/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 638 The rules are different based on whether or not we use FPA-format,
639 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 640#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 641
35d965d5
RS		 642#define UNITS_PER_WORD 4
643
5848830f 644/* True if natural alignment is used for doubleword types. */
b6685939
PB		 645#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
646
5848830f 647#define DOUBLEWORD_ALIGNMENT 64
35d965d5 648
5848830f 649#define PARM_BOUNDARY 32
5a9335ef 650
5848830f 651#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 652
5848830f
PB		 653#define PREFERRED_STACK_BOUNDARY \
654 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 655
35d965d5
RS		 656#define FUNCTION_BOUNDARY 32
657
92928d71
AO		 658/* The lowest bit is used to indicate Thumb-mode functions, so the
659 vbit must go into the delta field of pointers to member
660 functions. */
661#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
662
35d965d5
RS		 663#define EMPTY_FIELD_BOUNDARY 32
664
5848830f 665#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 666
27847754
NC		 667/* XXX Blah -- this macro is used directly by libobjc. Since it
668 supports no vector modes, cut out the complexity and fall back
669 on BIGGEST_FIELD_ALIGNMENT. */
670#ifdef IN_TARGET_LIBS
8fca31a2 671#define BIGGEST_FIELD_ALIGNMENT 64
27847754 672#endif
5a9335ef 673
ff9940b0 674/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 675#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 676
d19fb8e3 677#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f
PB		 678 ((TREE_CODE (EXP) == STRING_CST \
679 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
680 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 681
723ae7c1
NC		 682/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
683 value set in previous versions of this toolchain was 8, which produces more
684 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 685 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 686 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 687 0020D) page 2-20 says "Structures are aligned on word boundaries".
688 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 689#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
690extern int arm_structure_size_boundary;
723ae7c1 691
4912a07c 692/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 693 particular arm target wants to change the default value it should change
6bc82793 694 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 695 for an example of this. */
696#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
697#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 698#endif
2a5307b1 699
b355a481 700/* Used when parsing command line option -mstructure_size_boundary. */
f9cc092a 701extern const char * structure_size_string;
b4ac57ab 702
825dda42 703/* Nonzero if move instructions will actually fail to work
ff9940b0 704 when given unaligned data. */
35d965d5 705#define STRICT_ALIGNMENT 1
b6685939
PB		 706
707/* wchar_t is unsigned under the AAPCS. */
708#ifndef WCHAR_TYPE
709#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
710
711#define WCHAR_TYPE_SIZE BITS_PER_WORD
712#endif
713
714#ifndef SIZE_TYPE
715#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
716#endif
d81d0bdd
PB		 717
718/* AAPCS requires that structure alignment is affected by bitfields. */
719#ifndef PCC_BITFIELD_TYPE_MATTERS
720#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
721#endif
722
35d965d5
RS		 723\f
724/* Standard register usage. */
725
726/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
727 (S - saved over call).
728
729 r0 * argument word/integer result
730 r1-r3 argument word
731
732 r4-r8 S register variable
733 r9 S (rfp) register variable (real frame pointer)
f676971a 734
f5a1b0d2 735 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 736 r11 F S (fp) argument pointer
737 r12 (ip) temp workspace
738 r13 F S (sp) lower end of current stack frame
739 r14 (lr) link address/workspace
740 r15 F (pc) program counter
741
742 f0 floating point result
743 f1-f3 floating point scratch
744
745 f4-f7 S floating point variable
746
ff9940b0
RE		 747 cc This is NOT a real register, but is used internally
748 to represent things that use or set the condition
749 codes.
750 sfp This isn't either. It is used during rtl generation
751 since the offset between the frame pointer and the
752 auto's isn't known until after register allocation.
753 afp Nor this, we only need this because of non-local
754 goto. Without it fp appears to be used and the
755 elimination code won't get rid of sfp. It tracks
756 fp exactly at all times.
757
35d965d5
RS		 758 *: See CONDITIONAL_REGISTER_USAGE */
759
9b6b54e2
NC		 760/*
761 mvf0 Cirrus floating point result
762 mvf1-mvf3 Cirrus floating point scratch
763 mvf4-mvf15 S Cirrus floating point variable. */
764
9b66ebb1
PB		 765/* s0-s15 VFP scratch (aka d0-d7).
766 s16-s31 S VFP variable (aka d8-d15).
767 vfpcc Not a real register. Represents the VFP condition
768 code flags. */
769
ff9940b0
RE		 770/* The stack backtrace structure is as follows:
771 fp points to here: | save code pointer | [fp]
772 | return link value | [fp, #-4]
773 | return sp value | [fp, #-8]
774 | return fp value | [fp, #-12]
775 [| saved r10 value |]
776 [| saved r9 value |]
777 [| saved r8 value |]
778 [| saved r7 value |]
779 [| saved r6 value |]
780 [| saved r5 value |]
781 [| saved r4 value |]
782 [| saved r3 value |]
783 [| saved r2 value |]
784 [| saved r1 value |]
785 [| saved r0 value |]
786 [| saved f7 value |] three words
787 [| saved f6 value |] three words
788 [| saved f5 value |] three words
789 [| saved f4 value |] three words
790 r0-r3 are not normally saved in a C function. */
791
35d965d5
RS		 792/* 1 for registers that have pervasive standard uses
793 and are not available for the register allocator. */
9b66ebb1
PB		 794#define FIXED_REGISTERS \
795{ \
796 0,0,0,0,0,0,0,0, \
797 0,0,0,0,0,1,0,1, \
798 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 799 1,1,1, \
800 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1, \
805 1,1,1,1,1,1,1,1, \
806 1,1,1,1,1,1,1,1, \
807 1,1,1,1,1,1,1,1, \
808 1,1,1,1,1,1,1,1, \
809 1 \
35d965d5
RS		 810}
811
812/* 1 for registers not available across function calls.
813 These must include the FIXED_REGISTERS and also any
814 registers that can be used without being saved.
815 The latter must include the registers where values are returned
816 and the register where structure-value addresses are passed.
ff9940b0 817 Aside from that, you can include as many other registers as you like.
f676971a 818 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 819 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 820#define CALL_USED_REGISTERS \
821{ \
822 1,1,1,1,0,0,0,0, \
d5b7b3ae 823 0,0,0,0,1,1,1,1, \
ff9940b0 824 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 825 1,1,1, \
826 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1, \
829 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 830 1,1,1,1, \
831 1,1,1,1,1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1 \
35d965d5
RS		 836}
837
6cc8c0b3
NC		 838#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
839#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
840#endif
841
d5b7b3ae
RE		 842#define CONDITIONAL_REGISTER_USAGE \
843{ \
4b02997f
NC		 844 int regno; \
845 \
9b66ebb1 846 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
d5b7b3ae 847 { \
9b66ebb1
PB		 848 for (regno = FIRST_FPA_REGNUM; \
849 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 850 fixed_regs[regno] = call_used_regs[regno] = 1; \
851 } \
9b6b54e2 852 \
c769a35d
RE		 853 if (TARGET_THUMB && optimize_size) \
854 { \
855 /* When optimizing for size, it's better not to use \
856 the HI regs, because of the overhead of stacking \
d6b4baa4 857 them. */ \
c769a35d
RE		 858 for (regno = FIRST_HI_REGNUM; \
859 regno <= LAST_HI_REGNUM; ++regno) \
860 fixed_regs[regno] = call_used_regs[regno] = 1; \
861 } \
862 \
fb14bc89
RE		 863 /* The link register can be clobbered by any branch insn, \
864 but we have no way to track that at present, so mark \
865 it as unavailable. */ \
866 if (TARGET_THUMB) \
867 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
868 \
9b66ebb1 869 if (TARGET_ARM && TARGET_HARD_FLOAT) \
9b6b54e2 870 { \
9b66ebb1 871 if (TARGET_MAVERICK) \
9b6b54e2 872 { \
9b66ebb1
PB		 873 for (regno = FIRST_FPA_REGNUM; \
874 regno <= LAST_FPA_REGNUM; ++ regno) \
875 fixed_regs[regno] = call_used_regs[regno] = 1; \
876 for (regno = FIRST_CIRRUS_FP_REGNUM; \
877 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
878 { \
879 fixed_regs[regno] = 0; \
880 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
881 } \
882 } \
883 if (TARGET_VFP) \
884 { \
885 for (regno = FIRST_VFP_REGNUM; \
886 regno <= LAST_VFP_REGNUM; ++ regno) \
887 { \
888 fixed_regs[regno] = 0; \
889 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
890 } \
9b6b54e2
NC		 891 } \
892 } \
893 \
5a9335ef
NC		 894 if (TARGET_REALLY_IWMMXT) \
895 { \
896 regno = FIRST_IWMMXT_GR_REGNUM; \
897 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
898 and wCG1 as call-preserved registers. The 2002/11/21 \
899 revision changed this so that all wCG registers are \
900 scratch registers. */ \
901 for (regno = FIRST_IWMMXT_GR_REGNUM; \
902 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 903 fixed_regs[regno] = 0; \
5a9335ef
NC		 904 /* The XScale ABI has wR0 - wR9 as scratch registers, \
905 the rest as call-preserved registers. */ \
906 for (regno = FIRST_IWMMXT_REGNUM; \
907 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
908 { \
909 fixed_regs[regno] = 0; \
910 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
911 } \
912 } \
913 \
fc555370 914 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 915 { \
916 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
917 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
918 } \
919 else if (TARGET_APCS_STACK) \
920 { \
921 fixed_regs[10] = 1; \
922 call_used_regs[10] = 1; \
923 } \
a2503645
RS		 924 /* -mcaller-super-interworking reserves r11 for calls to \
925 _interwork_r11_call_via_rN(). Making the register global \
926 is an easy way of ensuring that it remains valid for all \
927 calls. */ \
928 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING) \
d5b7b3ae
RE		 929 { \
930 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
931 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 932 if (TARGET_CALLER_INTERWORKING) \
933 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 934 } \
935 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 936}
f676971a 937
6bc82793 938/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 939 by asm_fprintf:
940 %@ prints out ASM_COMMENT_START
941 %r prints out REGISTER_PREFIX reg_names[arg] */
942#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
943 case '@': \
944 fputs (ASM_COMMENT_START, FILE); \
945 break; \
946 \
947 case 'r': \
948 fputs (REGISTER_PREFIX, FILE); \
949 fputs (reg_names [va_arg (ARGS, int)], FILE); \
950 break;
951
d5b7b3ae 952/* Round X up to the nearest word. */
0c2ca901 953#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 954
6cfc7210 955/* Convert fron bytes to ints. */
e9d7b180 956#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 957
9b66ebb1
PB		 958/* The number of (integer) registers required to hold a quantity of type MODE.
959 Also used for VFP registers. */
e9d7b180
JD		 960#define ARM_NUM_REGS(MODE) \
961 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 962
963/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 964#define ARM_NUM_REGS2(MODE, TYPE) \
965 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 966 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 967
968/* The number of (integer) argument register available. */
d5b7b3ae 969#define NUM_ARG_REGS 4
6cfc7210 970
093354e0 971/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 972#define ARG_REGISTER(N) (N - 1)
6cfc7210 973
d5b7b3ae
RE		 974/* Specify the registers used for certain standard purposes.
975 The values of these macros are register numbers. */
35d965d5 976
d5b7b3ae
RE		 977/* The number of the last argument register. */
978#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 979
c769a35d
RE		 980/* The numbers of the Thumb register ranges. */
981#define FIRST_LO_REGNUM 0
6d3d9133 982#define LAST_LO_REGNUM 7
c769a35d
RE		 983#define FIRST_HI_REGNUM 8
984#define LAST_HI_REGNUM 11
6d3d9133 985
c9ca9b88
PB		 986/* We use sjlj exceptions for backwards compatibility. */
987#define MUST_USE_SJLJ_EXCEPTIONS 1
988/* We can generate DWARF2 Unwind info, even though we don't use it. */
989#define DWARF2_UNWIND_INFO 1
f676971a 990
c9ca9b88
PB		 991/* Use r0 and r1 to pass exception handling information. */
992#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
993
6d3d9133 994/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 995#define ARM_EH_STACKADJ_REGNUM 2
996#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 997
d5b7b3ae
RE		 998/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
999 as an invisible last argument (possible since varargs don't exist in
1000 Pascal), so the following is not true. */
68dfd979 1001#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
35d965d5 1002
d5b7b3ae
RE		 1003/* Define this to be where the real frame pointer is if it is not possible to
1004 work out the offset between the frame pointer and the automatic variables
1005 until after register allocation has taken place. FRAME_POINTER_REGNUM
1006 should point to a special register that we will make sure is eliminated.
1007
1008 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 1009 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 1010 as base register for addressing purposes. (See comments in
1011 find_reloads_address()). But - the Thumb does not allow high registers,
1012 including r11, to be used as base address registers. Hence our problem.
1013
1014 The solution used here, and in the old thumb port is to use r7 instead of
1015 r11 as the hard frame pointer and to have special code to generate
1016 backtrace structures on the stack (if required to do so via a command line
6bc82793 1017 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 1018 pointer. */
1019#define ARM_HARD_FRAME_POINTER_REGNUM 11
1020#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 1021
b15bca31
RE		 1022#define HARD_FRAME_POINTER_REGNUM \
1023 (TARGET_ARM \
1024 ? ARM_HARD_FRAME_POINTER_REGNUM \
1025 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 1026
b15bca31 1027#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 1028
b15bca31
RE		 1029/* Register to use for pushing function arguments. */
1030#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 1031
1032/* ARM floating pointer registers. */
9b66ebb1
PB		 1033#define FIRST_FPA_REGNUM 16
1034#define LAST_FPA_REGNUM 23
d5b7b3ae 1035
5a9335ef
NC		 1036#define FIRST_IWMMXT_GR_REGNUM 43
1037#define LAST_IWMMXT_GR_REGNUM 46
1038#define FIRST_IWMMXT_REGNUM 47
1039#define LAST_IWMMXT_REGNUM 62
1040#define IS_IWMMXT_REGNUM(REGNUM) \
1041 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1042#define IS_IWMMXT_GR_REGNUM(REGNUM) \
1043 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1044
35d965d5 1045/* Base register for access to local variables of the function. */
ff9940b0
RE		 1046#define FRAME_POINTER_REGNUM 25
1047
d5b7b3ae
RE		 1048/* Base register for access to arguments of the function. */
1049#define ARG_POINTER_REGNUM 26
62b10bbc 1050
9b6b54e2
NC		 1051#define FIRST_CIRRUS_FP_REGNUM 27
1052#define LAST_CIRRUS_FP_REGNUM 42
1053#define IS_CIRRUS_REGNUM(REGNUM) \
1054 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1055
9b66ebb1
PB		 1056#define FIRST_VFP_REGNUM 63
1057#define LAST_VFP_REGNUM 94
1058#define IS_VFP_REGNUM(REGNUM) \
1059 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1060
6f8c9bd1
NC		 1061/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1062/* + 16 Cirrus registers take us up to 43. */
5a9335ef 1063/* Intel Wireless MMX Technology registers add 16 + 4 more. */
9b66ebb1
PB		 1064/* VFP adds 32 + 1 more. */
1065#define FIRST_PSEUDO_REGISTER 96
62b10bbc 1066
35d965d5
RS		 1067/* Value should be nonzero if functions must have frame pointers.
1068 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 1069 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 1070 If we have to have a frame pointer we might as well make use of it.
1071 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 1072 functions, or simple tail call functions. */
7b8b8ade
NC		 1073#define FRAME_POINTER_REQUIRED \
1074 (current_function_has_nonlocal_label \
d5b7b3ae 1075 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 1076
d5b7b3ae
RE		 1077/* Return number of consecutive hard regs needed starting at reg REGNO
1078 to hold something of mode MODE.
1079 This is ordinarily the length in words of a value of mode MODE
1080 but can be less for certain modes in special long registers.
35d965d5 1081
3b684012 1082 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 1083 mode. */
1084#define HARD_REGNO_NREGS(REGNO, MODE) \
1085 ((TARGET_ARM \
9b66ebb1 1086 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 1087 && REGNO != FRAME_POINTER_REGNUM \
1088 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1089 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1090 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1091
4b02997f 1092/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1093#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1094 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1095
d5b7b3ae
RE		 1096/* Value is 1 if it is a good idea to tie two pseudo registers
1097 when one has mode MODE1 and one has mode MODE2.
1098 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1099 for any hard reg, then this must be 0 for correct output. */
1100#define MODES_TIEABLE_P(MODE1, MODE2) \
1101 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 1102
5a9335ef 1103#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1104 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1105
35d965d5 1106/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1107 since no saving is required (though calls clobber it) and it never contains
1108 function parameters. It is quite good to use lr since other calls may
f676971a 1109 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1110 least likely to contain a function parameter; in addition results are
d5b7b3ae 1111 returned in r0. */
9b66ebb1 1112
ff73fb53 1113#define REG_ALLOC_ORDER \
35d965d5 1114{ \
ff73fb53
NC		 1115 3, 2, 1, 0, 12, 14, 4, 5, \
1116 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0 1117 16, 17, 18, 19, 20, 21, 22, 23, \
9b6b54e2
NC		 1118 27, 28, 29, 30, 31, 32, 33, 34, \
1119 35, 36, 37, 38, 39, 40, 41, 42, \
5a9335ef
NC		 1120 43, 44, 45, 46, 47, 48, 49, 50, \
1121 51, 52, 53, 54, 55, 56, 57, 58, \
1122 59, 60, 61, 62, \
9b66ebb1
PB		 1123 24, 25, 26, \
1124 78, 77, 76, 75, 74, 73, 72, 71, \
1125 70, 69, 68, 67, 66, 65, 64, 63, \
1126 79, 80, 81, 82, 83, 84, 85, 86, \
1127 87, 88, 89, 90, 91, 92, 93, 94, \
1128 95 \
35d965d5 1129}
9338ffe6
PB		 1130
1131/* Interrupt functions can only use registers that have already been
1132 saved by the prologue, even if they would normally be
1133 call-clobbered. */
1134#define HARD_REGNO_RENAME_OK(SRC, DST) \
1135 (! IS_INTERRUPT (cfun->machine->func_type) || \
1136 regs_ever_live[DST])
35d965d5
RS		 1137\f
1138/* Register and constant classes. */
1139
3b684012 1140/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 1141 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 1142enum reg_class
1143{
1144 NO_REGS,
3b684012 1145 FPA_REGS,
9b6b54e2 1146 CIRRUS_REGS,
9b66ebb1 1147 VFP_REGS,
5a9335ef
NC		 1148 IWMMXT_GR_REGS,
1149 IWMMXT_REGS,
d5b7b3ae
RE		 1150 LO_REGS,
1151 STACK_REG,
1152 BASE_REGS,
1153 HI_REGS,
1154 CC_REG,
9b66ebb1 1155 VFPCC_REG,
35d965d5
RS		 1156 GENERAL_REGS,
1157 ALL_REGS,
1158 LIM_REG_CLASSES
1159};
1160
1161#define N_REG_CLASSES (int) LIM_REG_CLASSES
1162
d6b4baa4 1163/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1164#define REG_CLASS_NAMES \
1165{ \
1166 "NO_REGS", \
3b684012 1167 "FPA_REGS", \
9b6b54e2 1168 "CIRRUS_REGS", \
9b66ebb1 1169 "VFP_REGS", \
5a9335ef
NC		 1170 "IWMMXT_GR_REGS", \
1171 "IWMMXT_REGS", \
d5b7b3ae
RE		 1172 "LO_REGS", \
1173 "STACK_REG", \
1174 "BASE_REGS", \
1175 "HI_REGS", \
1176 "CC_REG", \
5384443a 1177 "VFPCC_REG", \
35d965d5
RS		 1178 "GENERAL_REGS", \
1179 "ALL_REGS", \
1180}
1181
1182/* Define which registers fit in which classes.
1183 This is an initializer for a vector of HARD_REG_SET
1184 of length N_REG_CLASSES. */
9b66ebb1
PB		 1185#define REG_CLASS_CONTENTS \
1186{ \
1187 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1188 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1189 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1190 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1191 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1192 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1193 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1194 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1195 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1196 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1197 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1198 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1199 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1200 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1201}
4b02997f 1202
35d965d5
RS		 1203/* The same information, inverted:
1204 Return the class number of the smallest class containing
1205 reg number REGNO. This could be a conditional expression
1206 or could index an array. */
d5b7b3ae 1207#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1208
9b66ebb1 1209/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1210 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1211 were set. */
75d2580c
RE		 1212#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1213 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1214 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1215 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1216 : 0)
75d2580c 1217
cc81dde8
PB		 1218/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1219 using r0-r4 for function arguments, r7 for the stack frame and don't
1220 have enough left over to do doubleword arithmetic. */
1221#define CLASS_LIKELY_SPILLED_P(CLASS) \
1222 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1223 || (CLASS) == CC_REG)
f676971a 1224
35d965d5 1225/* The class value for index registers, and the one for base regs. */
d5b7b3ae 1226#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
b93a0fe6 1227#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1228
b93a0fe6 1229/* For the Thumb the high registers cannot be used as base registers
6bc82793 1230 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1231 mode, then we must be conservative. */
3dcc68a4 1232#define MODE_BASE_REG_CLASS(MODE) \
b93a0fe6 1233 (TARGET_ARM ? GENERAL_REGS : \
888d2cd6
DJ		 1234 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1235
1236/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1237 instead of BASE_REGS. */
1238#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1239
d5b7b3ae
RE		 1240/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1241 registers explicitly used in the rtl to be used as spill registers
1242 but prevents the compiler from extending the lifetime of these
d6b4baa4 1243 registers. */
d5b7b3ae 1244#define SMALL_REGISTER_CLASSES TARGET_THUMB
35d965d5
RS		 1245
1246/* Get reg_class from a letter such as appears in the machine description.
3b684012 1247 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
d5b7b3ae
RE		 1248 ARM, but several more letters for the Thumb. */
1249#define REG_CLASS_FROM_LETTER(C) \
3b684012 1250 ( (C) == 'f' ? FPA_REGS \
9b6b54e2 1251 : (C) == 'v' ? CIRRUS_REGS \
9b66ebb1 1252 : (C) == 'w' ? VFP_REGS \
5a9335ef
NC		 1253 : (C) == 'y' ? IWMMXT_REGS \
1254 : (C) == 'z' ? IWMMXT_GR_REGS \
d5b7b3ae
RE		 1255 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1256 : TARGET_ARM ? NO_REGS \
1257 : (C) == 'h' ? HI_REGS \
1258 : (C) == 'b' ? BASE_REGS \
1259 : (C) == 'k' ? STACK_REG \
1260 : (C) == 'c' ? CC_REG \
1261 : NO_REGS)
35d965d5
RS		 1262
1263/* The letters I, J, K, L and M in a register constraint string
1264 can be used to stand for particular ranges of immediate operands.
1265 This macro defines what the ranges are.
1266 C is the letter, and VALUE is a constant value.
1267 Return 1 if VALUE is in the range specified by C.
b4ac57ab 1268 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
f676971a 1269 J: valid indexing constants.
aef1764c 1270 K: ~value ok in rhs argument of data operand.
f676971a 1271 L: -value ok in rhs argument of data operand.
3967692c 1272 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
d5b7b3ae 1273#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
aef1764c
RE		 1274 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1275 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1276 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 1277 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1278 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1279 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1280 : 0)
ff9940b0 1281
d5b7b3ae
RE		 1282#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1283 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1284 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1285 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1286 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1287 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1288 && ((VAL) & 3) == 0) : \
1289 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1290 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1291 : 0)
1292
1293#define CONST_OK_FOR_LETTER_P(VALUE, C) \
1294 (TARGET_ARM ? \
1295 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
f676971a 1296
9b66ebb1 1297/* Constant letter 'G' for the FP immediate constants.
d5b7b3ae
RE		 1298 'H' means the same constant negated. */
1299#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
9b66ebb1 1300 ((C) == 'G' ? arm_const_double_rtx (X) : \
3b684012 1301 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
d5b7b3ae
RE		 1302
1303#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1304 (TARGET_ARM ? \
1305 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1306
ff9940b0 1307/* For the ARM, `Q' means that this is a memory operand that is just
f676971a 1308 an offset from a register.
ff9940b0
RE		 1309 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1310 address. This means that the symbol is in the text segment and can be
9b66ebb1 1311 accessed without using a load.
2075b05d
RE		 1312 'D' Prefixes a number of const_double operands where:
1313 'Da' is a constant that takes two ARM insns to load.
1314 'Db' takes three ARM insns.
1315 'Dc' takes four ARM insns, if we allow that in this compilation.
edc62122 1316 'U' Prefixes an extended memory constraint where:
f676971a
EC		 1317 'Uv' is an address valid for VFP load/store insns.
1318 'Uy' is an address valid for iwmmxt load/store insns.
edc62122 1319 'Uq' is an address valid for ldrsb. */
ff9940b0 1320
2075b05d
RE		 1321#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1322 (((C) == 'D') ? (GET_CODE (OP) == CONST_DOUBLE \
1323 && (((STR)[1] == 'a' \
1324 && arm_const_double_inline_cost (OP) == 2) \
1325 || ((STR)[1] == 'b' \
1326 && arm_const_double_inline_cost (OP) == 3) \
1327 || ((STR)[1] == 'c' \
1328 && arm_const_double_inline_cost (OP) == 4 \
1329 && !(optimize_size || arm_ld_sched)))) : \
1330 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1331 && GET_CODE (XEXP (OP, 0)) == REG) : \
1332 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1333 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1334 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1335 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1336 ((C) == 'T') ? cirrus_memory_offset (OP) : \
fdd695fd
PB		 1337 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1338 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
2075b05d
RE		 1339 ((C) == 'U' && (STR)[1] == 'q') \
1340 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1341 : 0)
1e1ab407
RE		 1342
1343#define CONSTRAINT_LEN(C,STR) \
2075b05d 1344 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
ff9940b0 1345
d5b7b3ae
RE		 1346#define EXTRA_CONSTRAINT_THUMB(X, C) \
1347 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1348 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1349
1e1ab407
RE		 1350#define EXTRA_CONSTRAINT_STR(X, C, STR) \
1351 (TARGET_ARM \
1352 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1353 : EXTRA_CONSTRAINT_THUMB (X, C))
35d965d5 1354
9b66ebb1
PB		 1355#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1356
35d965d5
RS		 1357/* Given an rtx X being reloaded into a reg required to be
1358 in class CLASS, return the class of reg to actually use.
d5b7b3ae
RE		 1359 In general this is just CLASS, but for the Thumb we prefer
1360 a LO_REGS class or a subset. */
1361#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1362 (TARGET_ARM ? (CLASS) : \
1363 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1364
1365/* Must leave BASE_REGS reloads alone */
1366#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1367 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1368 ? ((true_regnum (X) == -1 ? LO_REGS \
1369 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1370 : NO_REGS)) \
1371 : NO_REGS)
1372
1373#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1374 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1375 ? ((true_regnum (X) == -1 ? LO_REGS \
1376 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1377 : NO_REGS)) \
1378 : NO_REGS)
35d965d5 1379
ff9940b0
RE		 1380/* Return the register class of a scratch register needed to copy IN into
1381 or out of a register in CLASS in MODE. If it can be done directly,
1382 NO_REGS is returned. */
d5b7b3ae 1383#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1384 /* Restrict which direct reloads are allowed for VFP regs. */ \
1385 ((TARGET_VFP && TARGET_HARD_FLOAT \
1386 && (CLASS) == VFP_REGS) \
1387 ? vfp_secondary_reload_class (MODE, X) \
1388 : TARGET_ARM \
1389 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1390 ? GENERAL_REGS : NO_REGS) \
1391 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1392
d6b4baa4 1393/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1394#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1395 /* Restrict which direct reloads are allowed for VFP regs. */ \
1396 ((TARGET_VFP && TARGET_HARD_FLOAT \
1397 && (CLASS) == VFP_REGS) \
1398 ? vfp_secondary_reload_class (MODE, X) : \
9b6b54e2 1399 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1400 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1401 && (CLASS) == CIRRUS_REGS \
1402 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1403 ? GENERAL_REGS : \
d5b7b3ae 1404 (TARGET_ARM ? \
5a9335ef
NC		 1405 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1406 && CONSTANT_P (X)) \
1407 ? GENERAL_REGS : \
61f0ccff 1408 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1409 && (GET_CODE (X) == MEM \
1410 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1411 && true_regnum (X) == -1))) \
1412 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1413 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1414
6f734908
RE		 1415/* Try a machine-dependent way of reloading an illegitimate address
1416 operand. If we find one, push the reload and jump to WIN. This
1417 macro is used in only one place: `find_reloads_address' in reload.c.
1418
1419 For the ARM, we wish to handle large displacements off a base
1420 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1421 This can cut the number of reloads needed. */
1422#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1423 do \
1424 { \
1425 if (GET_CODE (X) == PLUS \
1426 && GET_CODE (XEXP (X, 0)) == REG \
1427 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1428 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1429 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1430 { \
1431 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1432 HOST_WIDE_INT low, high; \
1433 \
de6f27a8 1434 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1435 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1436 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1437 /* Need to be careful, -256 is not a valid offset. */ \
1438 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1439 else if (MODE == SImode \
de6f27a8 1440 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1441 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1442 /* Need to be careful, -4096 is not a valid offset. */ \
1443 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1444 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1445 /* Need to be careful, -256 is not a valid offset. */ \
1446 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1447 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1448 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1449 /* Need to be careful, -1024 is not a valid offset. */ \
1450 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1451 else \
1452 break; \
1453 \
30cf4896
KG		 1454 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1455 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1456 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1457 /* Check for overflow or zero */ \
1458 if (low == 0 || high == 0 || (high + low != val)) \
1459 break; \
1460 \
1461 /* Reload the high part into a base reg; leave the low part \
1462 in the mem. */ \
1463 X = gen_rtx_PLUS (GET_MODE (X), \
1464 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1465 GEN_INT (high)), \
1466 GEN_INT (low)); \
df4ae160 1467 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1468 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1469 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1470 goto WIN; \
1471 } \
1472 } \
62b10bbc 1473 while (0)
6f734908 1474
27847754 1475/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1476 SP+large_offset address, then reload won't know how to fix it. It sees
1477 only that SP isn't valid for HImode, and so reloads the SP into an index
1478 register, but the resulting address is still invalid because the offset
1479 is too big. We fix it here instead by reloading the entire address. */
1480/* We could probably achieve better results by defining PROMOTE_MODE to help
1481 cope with the variances between the Thumb's signed and unsigned byte and
1482 halfword load instructions. */
1483#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1484{ \
1485 if (GET_CODE (X) == PLUS \
1486 && GET_MODE_SIZE (MODE) < 4 \
1487 && GET_CODE (XEXP (X, 0)) == REG \
1488 && XEXP (X, 0) == stack_pointer_rtx \
1489 && GET_CODE (XEXP (X, 1)) == CONST_INT \
76a318e9 1490 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
d5b7b3ae
RE		 1491 { \
1492 rtx orig_X = X; \
1493 X = copy_rtx (X); \
df4ae160 1494 push_reload (orig_X, NULL_RTX, &X, NULL, \
4a692617 1495 MODE_BASE_REG_CLASS (MODE), \
d5b7b3ae
RE		 1496 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1497 goto WIN; \
1498 } \
1499}
1500
1501#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1502 if (TARGET_ARM) \
1503 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1504 else \
1505 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1506
35d965d5
RS		 1507/* Return the maximum number of consecutive registers
1508 needed to represent mode MODE in a register of class CLASS.
3b684012 1509 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1510#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1511 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1512
1513/* If defined, gives a class of registers that cannot be used as the
1514 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1515
3b684012 1516/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1517#define REGISTER_MOVE_COST(MODE, FROM, TO) \
d5b7b3ae 1518 (TARGET_ARM ? \
3b684012
RE		 1519 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1520 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
9b66ebb1
PB		 1521 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1522 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
5a9335ef
NC		 1523 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1524 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1525 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1526 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1527 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1528 2) \
d5b7b3ae
RE		 1529 : \
1530 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1531\f
1532/* Stack layout; function entry, exit and calling. */
1533
1534/* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536#define STACK_GROWS_DOWNWARD 1
1537
1538/* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542#define FRAME_GROWS_DOWNWARD 1
1543
a2503645
RS		 1544/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1545 When present, it is one word in size, and sits at the top of the frame,
1546 between the soft frame pointer and either r7 or r11.
1547
1548 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1549 and only then if some outgoing arguments are passed on the stack. It would
1550 be tempting to also check whether the stack arguments are passed by indirect
1551 calls, but there seems to be no reason in principle why a post-reload pass
1552 couldn't convert a direct call into an indirect one. */
1553#define CALLER_INTERWORKING_SLOT_SIZE \
1554 (TARGET_CALLER_INTERWORKING \
1555 && current_function_outgoing_args_size != 0 \
1556 ? UNITS_PER_WORD : 0)
1557
35d965d5
RS		 1558/* Offset within stack frame to start allocating local variables at.
1559 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1560 first local allocated. Otherwise, it is the offset to the BEGINNING
1561 of the first local allocated. */
1562#define STARTING_FRAME_OFFSET 0
1563
1564/* If we generate an insn to push BYTES bytes,
1565 this says how many the stack pointer really advances by. */
d5b7b3ae 1566/* The push insns do not do this rounding implicitly.
d6b4baa4 1567 So don't define this. */
0c2ca901 1568/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1569
1570/* Define this if the maximum size of all the outgoing args is to be
1571 accumulated and pushed during the prologue. The amount can be
1572 found in the variable current_function_outgoing_args_size. */
6cfc7210 1573#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1574
1575/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1576#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1577
1578/* Value is the number of byte of arguments automatically
1579 popped when returning from a subroutine call.
8b109b37 1580 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1581 FUNTYPE is the data type of the function (as a tree),
1582 or for a library call it is an identifier node for the subroutine name.
1583 SIZE is the number of bytes of arguments passed on the stack.
1584
1585 On the ARM, the caller does not pop any of its arguments that were passed
1586 on the stack. */
6cfc7210 1587#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1588
1589/* Define how to find the value returned by a library function
1590 assuming the value has mode MODE. */
1591#define LIBCALL_VALUE(MODE) \
72cdc543 1592 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1593 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1594 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
72cdc543 1595 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1596 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1597 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1598 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1599 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1600 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1601
6cfc7210
NC		 1602/* Define how to find the value returned by a function.
1603 VALTYPE is the data type of the value (as a tree).
1604 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1605 otherwise, FUNC is 0. */
d5b7b3ae 1606#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1607 arm_function_value (VALTYPE, FUNC);
6cfc7210 1608
35d965d5
RS		 1609/* 1 if N is a possible register number for a function value.
1610 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1611/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1612#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1613 ((REGNO) == ARG_REGISTER (1) \
9b66ebb1 1614 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1615 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1616 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
9b66ebb1 1617 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1618 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1619
9f7bf991
RE		 1620/* Amount of memory needed for an untyped call to save all possible return
1621 registers. */
1622#define APPLY_RESULT_SIZE arm_apply_result_size()
1623
11c1a207
RE		 1624/* How large values are returned */
1625/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1626 in registers, based on the type of value. */
f5a1b0d2 1627#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1628
1629/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1630 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1631 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1632#define DEFAULT_PCC_STRUCT_RETURN 0
1633
d5b7b3ae
RE		 1634/* Flags for the call/call_value rtl operations set up by function_arg. */
1635#define CALL_NORMAL 0x00000000 /* No special processing. */
1636#define CALL_LONG 0x00000001 /* Always call indirect. */
1637#define CALL_SHORT 0x00000002 /* Never call indirect. */
1638
6d3d9133 1639/* These bits describe the different types of function supported
112cdef5 1640 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1641 normal function and an interworked function, for example. Knowing the
1642 type of a function is important for determining its prologue and
1643 epilogue sequences.
1644 Note value 7 is currently unassigned. Also note that the interrupt
1645 function types all have bit 2 set, so that they can be tested for easily.
1646 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1647 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1648 default to unknown. This will force the first use of arm_current_func_type
1649 to call arm_compute_func_type. */
1650#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1651#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1652#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1653#define ARM_FT_ISR 4 /* An interrupt service routine. */
1654#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1655#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1656
1657#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1658
1659/* In addition functions can have several type modifiers,
1660 outlined by these bit masks: */
1661#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1662#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1663#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1664#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
6d3d9133
NC		 1665
1666/* Some macros to test these flags. */
1667#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1668#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1669#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1670#define IS_NAKED(t) (t & ARM_FT_NAKED)
1671#define IS_NESTED(t) (t & ARM_FT_NESTED)
1672
5848830f
PB		 1673
1674/* Structure used to hold the function stack frame layout. Offsets are
1675 relative to the stack pointer on function entry. Positive offsets are
1676 in the direction of stack growth.
1677 Only soft_frame is used in thumb mode. */
1678
1679typedef struct arm_stack_offsets GTY(())
1680{
1681 int saved_args; /* ARG_POINTER_REGNUM. */
1682 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1683 int saved_regs;
1684 int soft_frame; /* FRAME_POINTER_REGNUM. */
1685 int outgoing_args; /* STACK_POINTER_REGNUM. */
1686}
1687arm_stack_offsets;
1688
6d3d9133
NC		 1689/* A C structure for machine-specific, per-function data.
1690 This is added to the cfun structure. */
e2500fed 1691typedef struct machine_function GTY(())
d5b7b3ae 1692{
6bc82793 1693 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1694 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1695 /* Records if LR has to be saved for far jumps. */
1696 int far_jump_used;
1697 /* Records if ARG_POINTER was ever live. */
1698 int arg_pointer_live;
6f7ebcbb
NC		 1699 /* Records if the save of LR has been eliminated. */
1700 int lr_save_eliminated;
0977774b 1701 /* The size of the stack frame. Only valid after reload. */
5848830f 1702 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1703 /* Records the type of the current function. */
1704 unsigned long func_type;
3cb66fd7
NC		 1705 /* Record if the function has a variable argument list. */
1706 int uses_anonymous_args;
5a9335ef
NC		 1707 /* Records if sibcalls are blocked because an argument
1708 register is needed to preserve stack alignment. */
1709 int sibcall_blocked;
b12a00f1
RE		 1710 /* Labels for per-function Thumb call-via stubs. One per potential calling
1711 register. We can never call via SP, LR or PC. */
1712 rtx call_via[13];
6d3d9133
NC		 1713}
1714machine_function;
d5b7b3ae 1715
b12a00f1
RE		 1716/* As in the machine_function, a global set of call-via labels, for code
1717 that is in text_section(). */
1718extern GTY(()) rtx thumb_call_via_label[13];
1719
82e9d970
PB		 1720/* A C type for declaring a variable that is used as the first argument of
1721 `FUNCTION_ARG' and other related values. For some target machines, the
1722 type `int' suffices and can hold the number of bytes of argument so far. */
1723typedef struct
1724{
d5b7b3ae 1725 /* This is the number of registers of arguments scanned so far. */
82e9d970 1726 int nregs;
5a9335ef
NC		 1727 /* This is the number of iWMMXt register arguments scanned so far. */
1728 int iwmmxt_nregs;
1729 int named_count;
1730 int nargs;
d6b4baa4 1731 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
82e9d970 1732 int call_cookie;
5848830f 1733 int can_split;
d5b7b3ae 1734} CUMULATIVE_ARGS;
82e9d970 1735
35d965d5
RS		 1736/* Define where to put the arguments to a function.
1737 Value is zero to push the argument on the stack,
1738 or a hard register in which to store the argument.
1739
1740 MODE is the argument's machine mode.
1741 TYPE is the data type of the argument (as a tree).
1742 This is null for libcalls where that information may
1743 not be available.
1744 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1745 the preceding args and about the function being called.
1746 NAMED is nonzero if this argument is a named parameter
1747 (otherwise it is an extra parameter matching an ellipsis).
1748
1749 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1750 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1751 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1752 defined), say it is passed in the stack (function_prologue will
1753 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1754#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1755 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1756
35d965d5
RS		 1757/* Initialize a variable CUM of type CUMULATIVE_ARGS
1758 for a call to a function whose data type is FNTYPE.
1759 For a library call, FNTYPE is 0.
1760 On the ARM, the offset starts at 0. */
0f6937fe 1761#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1762 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1763
1764/* Update the data in CUM to advance over an argument
1765 of mode MODE and data type TYPE.
1766 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1767#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1768 (CUM).nargs += 1; \
f676971a 1769 if (arm_vector_mode_supported_p (MODE) \
5848830f
PB		 1770 && (CUM).named_count > (CUM).nargs) \
1771 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1772 else \
5848830f 1773 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1774
5a9335ef
NC		 1775/* If defined, a C expression that gives the alignment boundary, in bits, of an
1776 argument with the specified mode and type. If it is not defined,
1777 `PARM_BOUNDARY' is used for all arguments. */
1778#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1779 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1780 ? DOUBLEWORD_ALIGNMENT \
1781 : PARM_BOUNDARY )
5a9335ef 1782
35d965d5
RS		 1783/* 1 if N is a possible register number for function argument passing.
1784 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1785#define FUNCTION_ARG_REGNO_P(REGNO) \
1786 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1787 || (TARGET_IWMMXT_ABI \
1788 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1789
f99fce0c 1790\f
afef3d7a
NC		 1791/* If your target environment doesn't prefix user functions with an
1792 underscore, you may wish to re-define this to prevent any conflicts.
1793 e.g. AOF may prefix mcount with an underscore. */
1794#ifndef ARM_MCOUNT_NAME
1795#define ARM_MCOUNT_NAME "*mcount"
1796#endif
1797
1798/* Call the function profiler with a given profile label. The Acorn
1799 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1800 On the ARM the full profile code will look like:
1801 .data
1802 LP1
1803 .word 0
1804 .text
1805 mov ip, lr
1806 bl mcount
1807 .word LP1
1808
1809 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1810 will output the .text section.
1811
1812 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1813 ``prof'' doesn't seem to mind about this!
1814
1815 Note - this version of the code is designed to work in both ARM and
1816 Thumb modes. */
be393ecf 1817#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1818#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1819{ \
1820 char temp[20]; \
1821 rtx sym; \
1822 \
dd18ae56 1823 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1824 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1825 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1826 fputc ('\n', STREAM); \
1827 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1828 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1829 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1830}
be393ecf 1831#endif
35d965d5 1832
59be6073 1833#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1834#define FUNCTION_PROFILER(STREAM, LABELNO) \
1835 if (TARGET_ARM) \
1836 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1837 else \
1838 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1839#else
1840#define FUNCTION_PROFILER(STREAM, LABELNO) \
1841 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1842#endif
d5b7b3ae 1843
35d965d5
RS		 1844/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1845 the stack pointer does not matter. The value is tested only in
1846 functions that have frame pointers.
1847 No definition is equivalent to always zero.
1848
1849 On the ARM, the function epilogue recovers the stack pointer from the
1850 frame. */
1851#define EXIT_IGNORE_STACK 1
1852
c7861455
RE		 1853#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1854
35d965d5
RS		 1855/* Determine if the epilogue should be output as RTL.
1856 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1857#define USE_RETURN_INSN(ISCOND) \
a72d4945 1858 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1859
1860/* Definitions for register eliminations.
1861
1862 This is an array of structures. Each structure initializes one pair
1863 of eliminable registers. The "from" register number is given first,
1864 followed by "to". Eliminations of the same "from" register are listed
1865 in order of preference.
1866
1867 We have two registers that can be eliminated on the ARM. First, the
1868 arg pointer register can often be eliminated in favor of the stack
1869 pointer register. Secondly, the pseudo frame pointer register can always
1870 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1871 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1872 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1873
d5b7b3ae
RE		 1874#define ELIMINABLE_REGS \
1875{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1876 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1877 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1878 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1879 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1880 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1881 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1882
d5b7b3ae
RE		 1883/* Given FROM and TO register numbers, say whether this elimination is
1884 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1885
1886 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1887 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1888 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1889 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1890 ARG_POINTER_REGNUM. */
1891#define CAN_ELIMINATE(FROM, TO) \
1892 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1893 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1894 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1895 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1896 1)
aeaf4d25 1897
d5b7b3ae
RE		 1898/* Define the offset between two registers, one to be eliminated, and the
1899 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1900#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1901 if (TARGET_ARM) \
5848830f 1902 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1903 else \
5848830f
PB		 1904 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1905
d5b7b3ae
RE		 1906/* Special case handling of the location of arguments passed on the stack. */
1907#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1908
d5b7b3ae
RE		 1909/* Initialize data used by insn expanders. This is called from insn_emit,
1910 once for every function before code is generated. */
1911#define INIT_EXPANDERS arm_init_expanders ()
1912
35d965d5
RS		 1913/* Output assembler code for a block containing the constant parts
1914 of a trampoline, leaving space for the variable parts.
1915
1916 On the ARM, (if r8 is the static chain regnum, and remembering that
1917 referencing pc adds an offset of 8) the trampoline looks like:
1918 ldr r8, [pc, #0]
1919 ldr pc, [pc]
1920 .word static chain value
11c1a207 1921 .word function's address
27847754 1922 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1923#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1924{ \
1925 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1926 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1927 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1928 PC_REGNUM, PC_REGNUM); \
1929 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1930 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1931}
1932
1933/* On the Thumb we always switch into ARM mode to execute the trampoline.
1934 Why - because it is easier. This code will always be branched to via
1935 a BX instruction and since the compiler magically generates the address
1936 of the function the linker has no opportunity to ensure that the
1937 bottom bit is set. Thus the processor will be in ARM mode when it
1938 reaches this code. So we duplicate the ARM trampoline code and add
1939 a switch into Thumb mode as well. */
1940#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1941{ \
1942 fprintf (FILE, "\t.code 32\n"); \
1943 fprintf (FILE, ".Ltrampoline_start:\n"); \
1944 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1945 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1946 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1947 IP_REGNUM, PC_REGNUM); \
1948 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1949 IP_REGNUM, IP_REGNUM); \
1950 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1951 fprintf (FILE, "\t.word\t0\n"); \
1952 fprintf (FILE, "\t.word\t0\n"); \
1953 fprintf (FILE, "\t.code 16\n"); \
35d965d5
RS		 1954}
1955
d5b7b3ae
RE		 1956#define TRAMPOLINE_TEMPLATE(FILE) \
1957 if (TARGET_ARM) \
1958 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1959 else \
1960 THUMB_TRAMPOLINE_TEMPLATE (FILE)
f676971a 1961
35d965d5 1962/* Length in units of the trampoline for entering a nested function. */
d5b7b3ae 1963#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
35d965d5 1964
006946e4
JM		 1965/* Alignment required for a trampoline in bits. */
1966#define TRAMPOLINE_ALIGNMENT 32
35d965d5
RS		 1967
1968/* Emit RTL insns to initialize the variable parts of a trampoline.
1969 FNADDR is an RTX for the address of the function's pure code.
1970 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1971#ifndef INITIALIZE_TRAMPOLINE
1972#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1973{ \
1974 emit_move_insn (gen_rtx_MEM (SImode, \
1975 plus_constant (TRAMP, \
1976 TARGET_ARM ? 8 : 16)), \
1977 CXT); \
1978 emit_move_insn (gen_rtx_MEM (SImode, \
1979 plus_constant (TRAMP, \
1980 TARGET_ARM ? 12 : 20)), \
1981 FNADDR); \
35d965d5 1982}
192c8d78 1983#endif
35d965d5 1984
35d965d5
RS		 1985\f
1986/* Addressing modes, and classification of registers for them. */
3cd45774
RE		 1987#define HAVE_POST_INCREMENT 1
1988#define HAVE_PRE_INCREMENT TARGET_ARM
1989#define HAVE_POST_DECREMENT TARGET_ARM
1990#define HAVE_PRE_DECREMENT TARGET_ARM
1991#define HAVE_PRE_MODIFY_DISP TARGET_ARM
1992#define HAVE_POST_MODIFY_DISP TARGET_ARM
1993#define HAVE_PRE_MODIFY_REG TARGET_ARM
1994#define HAVE_POST_MODIFY_REG TARGET_ARM
35d965d5
RS		 1995
1996/* Macros to check register numbers against specific register classes. */
1997
1998/* These assume that REGNO is a hard or pseudo reg number.
1999 They give nonzero only if REGNO is a hard reg of the suitable class
2000 or a pseudo reg currently allocated to a suitable hard reg.
2001 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 2002 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 2003#define TEST_REGNO(R, TEST, VALUE) \
2004 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2005
2006/* On the ARM, don't allow the pc to be used. */
f1008e52
RE		 2007#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2008 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2009 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2010 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2011
2012#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2013 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2014 || (GET_MODE_SIZE (MODE) >= 4 \
2015 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2016
2017#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2018 (TARGET_THUMB \
2019 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2020 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2021
888d2cd6
DJ		 2022/* Nonzero if X can be the base register in a reg+reg addressing mode.
2023 For Thumb, we can not use SP + reg, so reject SP. */
2024#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2025 REGNO_OK_FOR_INDEX_P (X)
2026
f1008e52
RE		 2027/* For ARM code, we don't care about the mode, but for Thumb, the index
2028 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 2029#define REGNO_OK_FOR_INDEX_P(REGNO) \
2030 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 2031
2032/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 2033 Shifts in addresses can't be by a register. */
ff9940b0 2034#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 2035
2036/* Recognize any constant value that is a valid address. */
2037/* XXX We can address any constant, eventually... */
11c1a207
RE		 2038
2039#ifdef AOF_ASSEMBLER
2040
2041#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 2042 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 2043
2044#else
35d965d5 2045
008cf58a
RE		 2046#define CONSTANT_ADDRESS_P(X) \
2047 (GET_CODE (X) == SYMBOL_REF \
2048 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 2049 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 2050
11c1a207
RE		 2051#endif /* AOF_ASSEMBLER */
2052
35d965d5
RS		 2053/* Nonzero if the constant value X is a legitimate general operand.
2054 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2055
2056 On the ARM, allow any integer (invalid ones are removed later by insn
2057 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 2058 constant pool XXX.
f676971a 2059
82e9d970 2060 When generating pic allow anything. */
d5b7b3ae
RE		 2061#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2062
2063#define THUMB_LEGITIMATE_CONSTANT_P(X) \
2064 ( GET_CODE (X) == CONST_INT \
2065 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 2066 || CONSTANT_ADDRESS_P (X) \
2067 || flag_pic)
d5b7b3ae
RE		 2068
2069#define LEGITIMATE_CONSTANT_P(X) \
2070 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2071
c27ba912
DM		 2072/* Special characters prefixed to function names
2073 in order to encode attribute like information.
2074 Note, '@' and '*' have already been taken. */
2075#define SHORT_CALL_FLAG_CHAR '^'
2076#define LONG_CALL_FLAG_CHAR '#'
2077
2078#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2079 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2080
2081#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2082 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2083
2084#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2085#define SUBTARGET_NAME_ENCODING_LENGTHS
2086#endif
2087
6bc82793 2088/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 2089 Each case label should return the number of characters to
2090 be stripped from the start of a function's name, if that
2091 name starts with the indicated character. */
2092#define ARM_NAME_ENCODING_LENGTHS \
2093 case SHORT_CALL_FLAG_CHAR: return 1; \
2094 case LONG_CALL_FLAG_CHAR: return 1; \
00fdafef 2095 case '*': return 1; \
f676971a 2096 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 2097
c27ba912
DM		 2098/* This is how to output a reference to a user-level label named NAME.
2099 `assemble_name' uses this. */
e5951263 2100#undef ASM_OUTPUT_LABELREF
c27ba912 2101#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 2102 arm_asm_output_labelref (FILE, NAME)
c27ba912 2103
a77655b1
NC		 2104/* Set the short-call flag for any function compiled in the current
2105 compilation unit. We skip this for functions with the section
c112cf2b 2106 attribute when long-calls are in effect as this tells the compiler
a77655b1
NC		 2107 that the section might be placed a long way from the caller.
2108 See arm_is_longcall_p() for more information. */
c27ba912 2109#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
a77655b1
NC		 2110 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2111 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
c27ba912 2112
35d965d5
RS		 2113/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2114 and check its validity for a certain class.
2115 We have two alternate definitions for each of them.
2116 The usual definition accepts all pseudo regs; the other rejects
2117 them unless they have been allocated suitable hard regs.
2118 The symbol REG_OK_STRICT causes the latter definition to be used. */
2119#ifndef REG_OK_STRICT
ff9940b0 2120
f1008e52
RE		 2121#define ARM_REG_OK_FOR_BASE_P(X) \
2122 (REGNO (X) <= LAST_ARM_REGNUM \
2123 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2124 || REGNO (X) == FRAME_POINTER_REGNUM \
2125 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 2126
f1008e52
RE		 2127#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2128 (REGNO (X) <= LAST_LO_REGNUM \
2129 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2130 || (GET_MODE_SIZE (MODE) >= 4 \
2131 && (REGNO (X) == STACK_POINTER_REGNUM \
2132 || (X) == hard_frame_pointer_rtx \
2133 || (X) == arg_pointer_rtx)))
ff9940b0 2134
76a318e9
RE		 2135#define REG_STRICT_P 0
2136
d5b7b3ae 2137#else /* REG_OK_STRICT */
ff9940b0 2138
f1008e52
RE		 2139#define ARM_REG_OK_FOR_BASE_P(X) \
2140 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2141
f1008e52
RE		 2142#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2143 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2144
76a318e9
RE		 2145#define REG_STRICT_P 1
2146
d5b7b3ae 2147#endif /* REG_OK_STRICT */
f1008e52
RE		 2148
2149/* Now define some helpers in terms of the above. */
2150
2151#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2152 (TARGET_THUMB \
2153 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2154 : ARM_REG_OK_FOR_BASE_P (X))
2155
2156#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2157
2158/* For Thumb, a valid index register is anything that can be used in
2159 a byte load instruction. */
2160#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2161
2162/* Nonzero if X is a hard reg that can be used as an index
2163 or if it is a pseudo reg. On the Thumb, the stack pointer
2164 is not suitable. */
2165#define REG_OK_FOR_INDEX_P(X) \
2166 (TARGET_THUMB \
2167 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2168 : ARM_REG_OK_FOR_INDEX_P (X))
2169
888d2cd6
DJ		 2170/* Nonzero if X can be the base register in a reg+reg addressing mode.
2171 For Thumb, we can not use SP + reg, so reject SP. */
2172#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2173 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2174\f
2175/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2176 that is a valid memory address for an instruction.
2177 The MODE argument is the machine mode for the MEM expression
76a318e9 2178 that wants to use this address. */
f676971a 2179
f1008e52
RE		 2180#define ARM_BASE_REGISTER_RTX_P(X) \
2181 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2182
f1008e52
RE		 2183#define ARM_INDEX_REGISTER_RTX_P(X) \
2184 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2185
76a318e9
RE		 2186#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2187 { \
1e1ab407 2188 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2189 goto WIN; \
6b990f6b 2190 }
d5b7b3ae 2191
76a318e9
RE		 2192#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2193 { \
2194 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2195 goto WIN; \
2196 }
d5b7b3ae 2197
d5b7b3ae
RE		 2198#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2199 if (TARGET_ARM) \
2200 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2201 else /* if (TARGET_THUMB) */ \
f676971a 2202 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2203
35d965d5
RS		 2204\f
2205/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2206 to be legitimate. If we find one, return the new, valid address. */
2207#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2208do { \
2209 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2210} while (0)
2211
6f5b4f3e
RE		 2212#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2213do { \
2214 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2215} while (0)
2216
2217#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2218do { \
2219 if (TARGET_ARM) \
2220 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2221 else \
2222 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2223 \
2224 if (memory_address_p (MODE, X)) \
2225 goto WIN; \
ccf4d512 2226} while (0)
f676971a 2227
35d965d5
RS		 2228/* Go to LABEL if ADDR (a legitimate address expression)
2229 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2230#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2231{ \
d5b7b3ae
RE		 2232 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2233 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2234 goto LABEL; \
2235}
d5b7b3ae
RE		 2236
2237/* Nothing helpful to do for the Thumb */
2238#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2239 if (TARGET_ARM) \
f676971a 2240 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2241\f
d5b7b3ae 2242
35d965d5
RS		 2243/* Specify the machine mode that this machine uses
2244 for the index in the tablejump instruction. */
d5b7b3ae 2245#define CASE_VECTOR_MODE Pmode
35d965d5 2246
ff9940b0
RE		 2247/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2248 unsigned is probably best, but may break some code. */
2249#ifndef DEFAULT_SIGNED_CHAR
3967692c 2250#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2251#endif
2252
35d965d5 2253/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2254 in one reasonably fast instruction. */
2255#define MOVE_MAX 4
35d965d5 2256
d19fb8e3 2257#undef MOVE_RATIO
591af218 2258#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2259
ff9940b0
RE		 2260/* Define if operations between registers always perform the operation
2261 on the full register even if a narrower mode is specified. */
2262#define WORD_REGISTER_OPERATIONS
2263
2264/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2265 will either zero-extend or sign-extend. The value of this macro should
2266 be the code that says which one of the two operations is implicitly
f822d252 2267 done, UNKNOWN if none. */
9c872872 2268#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2269 (TARGET_THUMB ? ZERO_EXTEND : \
2270 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2271 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2272
35d965d5
RS		 2273/* Nonzero if access to memory by bytes is slow and undesirable. */
2274#define SLOW_BYTE_ACCESS 0
2275
d5b7b3ae 2276#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2277
35d965d5
RS		 2278/* Immediate shift counts are truncated by the output routines (or was it
2279 the assembler?). Shift counts in a register are truncated by ARM. Note
2280 that the native compiler puts too large (> 32) immediate shift counts
2281 into a register and shifts by the register, letting the ARM decide what
2282 to do instead of doing that itself. */
ff9940b0
RE		 2283/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2284 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2285 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2286 rotates is modulo 32 used. */
ff9940b0 2287/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2288
35d965d5 2289/* All integers have the same format so truncation is easy. */
d5b7b3ae 2290#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2291
2292/* Calling from registers is a massive pain. */
2293#define NO_FUNCTION_CSE 1
2294
35d965d5
RS		 2295/* The machine modes of pointers and functions */
2296#define Pmode SImode
2297#define FUNCTION_MODE Pmode
2298
d5b7b3ae
RE		 2299#define ARM_FRAME_RTX(X) \
2300 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2301 || (X) == arg_pointer_rtx)
2302
ff9940b0 2303/* Moves to and from memory are quite expensive */
d5b7b3ae
RE		 2304#define MEMORY_MOVE_COST(M, CLASS, IN) \
2305 (TARGET_ARM ? 10 : \
2306 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2307 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2308
ff9940b0
RE		 2309/* Try to generate sequences that don't involve branches, we can then use
2310 conditional instructions */
d5b7b3ae
RE		 2311#define BRANCH_COST \
2312 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
7a801826
RE		 2313\f
2314/* Position Independent Code. */
2315/* We decide which register to use based on the compilation options and
2316 the assembler in use; this is more general than the APCS restriction of
2317 using sb (r9) all the time. */
2318extern int arm_pic_register;
2319
ed0e6530
PB		 2320/* Used when parsing command line option -mpic-register=. */
2321extern const char * arm_pic_register_string;
2322
7a801826
RE		 2323/* The register number of the register used to address a table of static
2324 data addresses in memory. */
2325#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2326
f5a1b0d2
NC		 2327/* We can't directly access anything that contains a symbol,
2328 nor can we indirect via the constant pool. */
82e9d970 2329#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2330 (!(symbol_mentioned_p (X) \
2331 || label_mentioned_p (X) \
2332 || (GET_CODE (X) == SYMBOL_REF \
2333 && CONSTANT_POOL_ADDRESS_P (X) \
2334 && (symbol_mentioned_p (get_pool_constant (X)) \
2335 || label_mentioned_p (get_pool_constant (X))))))
2336
13bd191d
PB		 2337/* We need to know when we are making a constant pool; this determines
2338 whether data needs to be in the GOT or can be referenced via a GOT
2339 offset. */
2340extern int making_const_table;
82e9d970 2341\f
c27ba912 2342/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2343#define REGISTER_TARGET_PRAGMAS() do { \
2344 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2345 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2346 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2347} while (0)
2348
d6b4baa4 2349/* Condition code information. */
ff9940b0 2350/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2351 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2352
2353#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2354
880873be
RE		 2355#define REVERSIBLE_CC_MODE(MODE) 1
2356
2357#define REVERSE_CONDITION(CODE,MODE) \
2358 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2359 ? reverse_condition_maybe_unordered (code) \
2360 : reverse_condition (code))
008cf58a 2361
62b10bbc
NC		 2362#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2363 do \
2364 { \
2365 if (GET_CODE (OP1) == CONST_INT \
2366 && ! (const_ok_for_arm (INTVAL (OP1)) \
2367 || (const_ok_for_arm (- INTVAL (OP1))))) \
2368 { \
2369 rtx const_op = OP1; \
2370 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2371 OP1 = const_op; \
2372 } \
2373 } \
2374 while (0)
62dd06ea 2375
7dba8395
RH		 2376/* The arm5 clz instruction returns 32. */
2377#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2378\f
d5b7b3ae
RE		 2379#undef ASM_APP_OFF
2380#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
35d965d5 2381
35d965d5 2382/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2383#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2384 do \
2385 { \
2386 if (TARGET_ARM) \
2387 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2388 STACK_POINTER_REGNUM, REGNO); \
2389 else \
2390 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2391 } while (0)
d5b7b3ae
RE		 2392
2393
2394#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2395 do \
2396 { \
2397 if (TARGET_ARM) \
2398 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2399 STACK_POINTER_REGNUM, REGNO); \
2400 else \
2401 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2402 } while (0)
d5b7b3ae
RE		 2403
2404/* This is how to output a label which precedes a jumptable. Since
2405 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2406#undef ASM_OUTPUT_CASE_LABEL
d5b7b3ae
RE		 2407#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2408 do \
2409 { \
2410 if (TARGET_THUMB) \
2411 ASM_OUTPUT_ALIGN (FILE, 2); \
8a81cc45 2412 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
d5b7b3ae
RE		 2413 } \
2414 while (0)
35d965d5 2415
6cfc7210
NC		 2416#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2417 do \
2418 { \
d5b7b3ae
RE		 2419 if (TARGET_THUMB) \
2420 { \
9b66ebb1
PB		 2421 if (is_called_in_ARM_mode (DECL) \
2422 || current_function_is_thunk) \
d5b7b3ae
RE		 2423 fprintf (STREAM, "\t.code 32\n") ; \
2424 else \
9b66ebb1 2425 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
d5b7b3ae 2426 } \
6cfc7210 2427 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2428 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2429 } \
2430 while (0)
35d965d5 2431
d5b7b3ae
RE		 2432/* For aliases of functions we use .thumb_set instead. */
2433#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2434 do \
2435 { \
91ea4f8d
KG		 2436 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2437 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2438 \
2439 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2440 { \
2441 fprintf (FILE, "\t.thumb_set "); \
2442 assemble_name (FILE, LABEL1); \
2443 fprintf (FILE, ","); \
2444 assemble_name (FILE, LABEL2); \
2445 fprintf (FILE, "\n"); \
2446 } \
2447 else \
2448 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2449 } \
2450 while (0)
2451
fdc2d3b0
NC		 2452#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2453/* To support -falign-* switches we need to use .p2align so
2454 that alignment directives in code sections will be padded
2455 with no-op instructions, rather than zeroes. */
5a9335ef 2456#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2457 if ((LOG) != 0) \
2458 { \
2459 if ((MAX_SKIP) == 0) \
5a9335ef 2460 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2461 else \
2462 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2463 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2464 }
2465#endif
35d965d5 2466\f
35d965d5 2467/* Only perform branch elimination (by making instructions conditional) if
72ac76be 2468 we're optimizing. Otherwise it's of no use anyway. */
d5b7b3ae
RE		 2469#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2470 if (TARGET_ARM && optimize) \
2471 arm_final_prescan_insn (INSN); \
2472 else if (TARGET_THUMB) \
2473 thumb_final_prescan_insn (INSN)
35d965d5 2474
7bc7696c 2475#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
d5b7b3ae
RE		 2476 (CODE == '@' || CODE == '|' \
2477 || (TARGET_ARM && (CODE == '?')) \
2478 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2479
7bc7696c 2480/* Output an operand of an instruction. */
35d965d5 2481#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2482 arm_print_operand (STREAM, X, CODE)
2483
7b8b8ade
NC		 2484#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2485 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2486 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2487 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2488 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2489 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2490 : 0))))
35d965d5
RS		 2491
2492/* Output the address of an operand. */
3cd45774
RE		 2493#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2494{ \
2495 int is_minus = GET_CODE (X) == MINUS; \
2496 \
2497 if (GET_CODE (X) == REG) \
2498 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2499 else if (GET_CODE (X) == PLUS || is_minus) \
2500 { \
2501 rtx base = XEXP (X, 0); \
2502 rtx index = XEXP (X, 1); \
2503 HOST_WIDE_INT offset = 0; \
2504 if (GET_CODE (base) != REG) \
2505 { \
d6b4baa4
KH		 2506 /* Ensure that BASE is a register. */ \
2507 /* (one of them must be). */ \
3cd45774
RE		 2508 rtx temp = base; \
2509 base = index; \
2510 index = temp; \
2511 } \
2512 switch (GET_CODE (index)) \
2513 { \
2514 case CONST_INT: \
2515 offset = INTVAL (index); \
2516 if (is_minus) \
2517 offset = -offset; \
c53dddc2 2518 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2519 REGNO (base), offset); \
2520 break; \
2521 \
2522 case REG: \
2523 asm_fprintf (STREAM, "[%r, %s%r]", \
2524 REGNO (base), is_minus ? "-" : "", \
2525 REGNO (index)); \
2526 break; \
2527 \
2528 case MULT: \
2529 case ASHIFTRT: \
2530 case LSHIFTRT: \
2531 case ASHIFT: \
2532 case ROTATERT: \
2533 { \
2534 asm_fprintf (STREAM, "[%r, %s%r", \
2535 REGNO (base), is_minus ? "-" : "", \
2536 REGNO (XEXP (index, 0))); \
2537 arm_print_operand (STREAM, index, 'S'); \
2538 fputs ("]", STREAM); \
2539 break; \
2540 } \
2541 \
2542 default: \
2543 abort(); \
2544 } \
2545 } \
2546 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2547 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2548 { \
2549 extern enum machine_mode output_memory_reference_mode; \
2550 \
2551 if (GET_CODE (XEXP (X, 0)) != REG) \
2552 abort (); \
2553 \
2554 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2555 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2556 REGNO (XEXP (X, 0)), \
2557 GET_CODE (X) == PRE_DEC ? "-" : "", \
2558 GET_MODE_SIZE (output_memory_reference_mode)); \
2559 else \
2560 asm_fprintf (STREAM, "[%r], #%s%d", \
2561 REGNO (XEXP (X, 0)), \
2562 GET_CODE (X) == POST_DEC ? "-" : "", \
2563 GET_MODE_SIZE (output_memory_reference_mode)); \
2564 } \
2565 else if (GET_CODE (X) == PRE_MODIFY) \
2566 { \
2567 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2568 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2569 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2570 INTVAL (XEXP (XEXP (X, 1), 1))); \
2571 else \
2572 asm_fprintf (STREAM, "%r]!", \
2573 REGNO (XEXP (XEXP (X, 1), 1))); \
2574 } \
2575 else if (GET_CODE (X) == POST_MODIFY) \
2576 { \
2577 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2578 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2579 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2580 INTVAL (XEXP (XEXP (X, 1), 1))); \
2581 else \
2582 asm_fprintf (STREAM, "%r", \
2583 REGNO (XEXP (XEXP (X, 1), 1))); \
2584 } \
2585 else output_addr_const (STREAM, X); \
35d965d5 2586}
62dd06ea 2587
d5b7b3ae
RE		 2588#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2589{ \
2590 if (GET_CODE (X) == REG) \
2591 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2592 else if (GET_CODE (X) == POST_INC) \
2593 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2594 else if (GET_CODE (X) == PLUS) \
2595 { \
27847754
NC		 2596 if (GET_CODE (XEXP (X, 0)) != REG) \
2597 abort (); \
d5b7b3ae 2598 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2599 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2600 REGNO (XEXP (X, 0)), \
659bdc68 2601 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2602 else \
2603 asm_fprintf (STREAM, "[%r, %r]", \
2604 REGNO (XEXP (X, 0)), \
2605 REGNO (XEXP (X, 1))); \
2606 } \
2607 else \
2608 output_addr_const (STREAM, X); \
2609}
2610
2611#define PRINT_OPERAND_ADDRESS(STREAM, X) \
2612 if (TARGET_ARM) \
2613 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2614 else \
2615 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef
NC		 2616
2617#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2618 if (GET_CODE (X) != CONST_VECTOR \
2619 || ! arm_emit_vector_const (FILE, X)) \
2620 goto FAIL;
2621
6a5d7526
MS		 2622/* A C expression whose value is RTL representing the value of the return
2623 address for the frame COUNT steps up from the current frame. */
2624
d5b7b3ae
RE		 2625#define RETURN_ADDR_RTX(COUNT, FRAME) \
2626 arm_return_addr (COUNT, FRAME)
2627
f676971a 2628/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2629 when running in 26-bit mode. */
2630#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2631
2c849145
JM		 2632/* Pick up the return address upon entry to a procedure. Used for
2633 dwarf2 unwind information. This also enables the table driven
2634 mechanism. */
2c849145
JM		 2635#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2636#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2637
39950dff
MS		 2638/* Used to mask out junk bits from the return address, such as
2639 processor state, interrupt status, condition codes and the like. */
2640#define MASK_RETURN_ADDR \
2641 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2642 in 26 bit mode, the condition codes must be masked out of the \
2643 return address. This does not apply to ARM6 and later processors \
2644 when running in 32 bit mode. */ \
61f0ccff
RE		 2645 ((arm_arch4 || TARGET_THUMB) \
2646 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2647 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2648
2649\f
5a9335ef
NC		 2650enum arm_builtins
2651{
2652 ARM_BUILTIN_GETWCX,
2653 ARM_BUILTIN_SETWCX,
2654
2655 ARM_BUILTIN_WZERO,
2656
2657 ARM_BUILTIN_WAVG2BR,
2658 ARM_BUILTIN_WAVG2HR,
2659 ARM_BUILTIN_WAVG2B,
2660 ARM_BUILTIN_WAVG2H,
2661
2662 ARM_BUILTIN_WACCB,
2663 ARM_BUILTIN_WACCH,
2664 ARM_BUILTIN_WACCW,
2665
2666 ARM_BUILTIN_WMACS,
2667 ARM_BUILTIN_WMACSZ,
2668 ARM_BUILTIN_WMACU,
2669 ARM_BUILTIN_WMACUZ,
2670
2671 ARM_BUILTIN_WSADB,
2672 ARM_BUILTIN_WSADBZ,
2673 ARM_BUILTIN_WSADH,
2674 ARM_BUILTIN_WSADHZ,
2675
2676 ARM_BUILTIN_WALIGN,
2677
2678 ARM_BUILTIN_TMIA,
2679 ARM_BUILTIN_TMIAPH,
2680 ARM_BUILTIN_TMIABB,
2681 ARM_BUILTIN_TMIABT,
2682 ARM_BUILTIN_TMIATB,
2683 ARM_BUILTIN_TMIATT,
2684
2685 ARM_BUILTIN_TMOVMSKB,
2686 ARM_BUILTIN_TMOVMSKH,
2687 ARM_BUILTIN_TMOVMSKW,
2688
2689 ARM_BUILTIN_TBCSTB,
2690 ARM_BUILTIN_TBCSTH,
2691 ARM_BUILTIN_TBCSTW,
2692
2693 ARM_BUILTIN_WMADDS,
2694 ARM_BUILTIN_WMADDU,
2695
2696 ARM_BUILTIN_WPACKHSS,
2697 ARM_BUILTIN_WPACKWSS,
2698 ARM_BUILTIN_WPACKDSS,
2699 ARM_BUILTIN_WPACKHUS,
2700 ARM_BUILTIN_WPACKWUS,
2701 ARM_BUILTIN_WPACKDUS,
2702
2703 ARM_BUILTIN_WADDB,
2704 ARM_BUILTIN_WADDH,
2705 ARM_BUILTIN_WADDW,
2706 ARM_BUILTIN_WADDSSB,
2707 ARM_BUILTIN_WADDSSH,
2708 ARM_BUILTIN_WADDSSW,
2709 ARM_BUILTIN_WADDUSB,
2710 ARM_BUILTIN_WADDUSH,
2711 ARM_BUILTIN_WADDUSW,
2712 ARM_BUILTIN_WSUBB,
2713 ARM_BUILTIN_WSUBH,
2714 ARM_BUILTIN_WSUBW,
2715 ARM_BUILTIN_WSUBSSB,
2716 ARM_BUILTIN_WSUBSSH,
2717 ARM_BUILTIN_WSUBSSW,
2718 ARM_BUILTIN_WSUBUSB,
2719 ARM_BUILTIN_WSUBUSH,
2720 ARM_BUILTIN_WSUBUSW,
2721
2722 ARM_BUILTIN_WAND,
2723 ARM_BUILTIN_WANDN,
2724 ARM_BUILTIN_WOR,
2725 ARM_BUILTIN_WXOR,
2726
2727 ARM_BUILTIN_WCMPEQB,
2728 ARM_BUILTIN_WCMPEQH,
2729 ARM_BUILTIN_WCMPEQW,
2730 ARM_BUILTIN_WCMPGTUB,
2731 ARM_BUILTIN_WCMPGTUH,
2732 ARM_BUILTIN_WCMPGTUW,
2733 ARM_BUILTIN_WCMPGTSB,
2734 ARM_BUILTIN_WCMPGTSH,
2735 ARM_BUILTIN_WCMPGTSW,
2736
2737 ARM_BUILTIN_TEXTRMSB,
2738 ARM_BUILTIN_TEXTRMSH,
2739 ARM_BUILTIN_TEXTRMSW,
2740 ARM_BUILTIN_TEXTRMUB,
2741 ARM_BUILTIN_TEXTRMUH,
2742 ARM_BUILTIN_TEXTRMUW,
2743 ARM_BUILTIN_TINSRB,
2744 ARM_BUILTIN_TINSRH,
2745 ARM_BUILTIN_TINSRW,
2746
2747 ARM_BUILTIN_WMAXSW,
2748 ARM_BUILTIN_WMAXSH,
2749 ARM_BUILTIN_WMAXSB,
2750 ARM_BUILTIN_WMAXUW,
2751 ARM_BUILTIN_WMAXUH,
2752 ARM_BUILTIN_WMAXUB,
2753 ARM_BUILTIN_WMINSW,
2754 ARM_BUILTIN_WMINSH,
2755 ARM_BUILTIN_WMINSB,
2756 ARM_BUILTIN_WMINUW,
2757 ARM_BUILTIN_WMINUH,
2758 ARM_BUILTIN_WMINUB,
2759
f07a6b21
BE		 2760 ARM_BUILTIN_WMULUM,
2761 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2762 ARM_BUILTIN_WMULUL,
2763
2764 ARM_BUILTIN_PSADBH,
2765 ARM_BUILTIN_WSHUFH,
2766
2767 ARM_BUILTIN_WSLLH,
2768 ARM_BUILTIN_WSLLW,
2769 ARM_BUILTIN_WSLLD,
2770 ARM_BUILTIN_WSRAH,
2771 ARM_BUILTIN_WSRAW,
2772 ARM_BUILTIN_WSRAD,
2773 ARM_BUILTIN_WSRLH,
2774 ARM_BUILTIN_WSRLW,
2775 ARM_BUILTIN_WSRLD,
2776 ARM_BUILTIN_WRORH,
2777 ARM_BUILTIN_WRORW,
2778 ARM_BUILTIN_WRORD,
2779 ARM_BUILTIN_WSLLHI,
2780 ARM_BUILTIN_WSLLWI,
2781 ARM_BUILTIN_WSLLDI,
2782 ARM_BUILTIN_WSRAHI,
2783 ARM_BUILTIN_WSRAWI,
2784 ARM_BUILTIN_WSRADI,
2785 ARM_BUILTIN_WSRLHI,
2786 ARM_BUILTIN_WSRLWI,
2787 ARM_BUILTIN_WSRLDI,
2788 ARM_BUILTIN_WRORHI,
2789 ARM_BUILTIN_WRORWI,
2790 ARM_BUILTIN_WRORDI,
2791
2792 ARM_BUILTIN_WUNPCKIHB,
2793 ARM_BUILTIN_WUNPCKIHH,
2794 ARM_BUILTIN_WUNPCKIHW,
2795 ARM_BUILTIN_WUNPCKILB,
2796 ARM_BUILTIN_WUNPCKILH,
2797 ARM_BUILTIN_WUNPCKILW,
2798
2799 ARM_BUILTIN_WUNPCKEHSB,
2800 ARM_BUILTIN_WUNPCKEHSH,
2801 ARM_BUILTIN_WUNPCKEHSW,
2802 ARM_BUILTIN_WUNPCKEHUB,
2803 ARM_BUILTIN_WUNPCKEHUH,
2804 ARM_BUILTIN_WUNPCKEHUW,
2805 ARM_BUILTIN_WUNPCKELSB,
2806 ARM_BUILTIN_WUNPCKELSH,
2807 ARM_BUILTIN_WUNPCKELSW,
2808 ARM_BUILTIN_WUNPCKELUB,
2809 ARM_BUILTIN_WUNPCKELUH,
2810 ARM_BUILTIN_WUNPCKELUW,
2811
2812 ARM_BUILTIN_MAX
2813};
88657302 2814#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git