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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
23a5b65a | 2 | Copyright (C) 1991-2014 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 5 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
6 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
7 | ||
4f448245 | 8 | This file is part of GCC. |
35d965d5 | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 12 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 13 | option) any later version. |
35d965d5 | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
35d965d5 | 19 | |
4f448245 | 20 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
35d965d5 | 23 | |
88657302 RH |
24 | #ifndef GCC_ARM_H |
25 | #define GCC_ARM_H | |
b355a481 | 26 | |
46107b99 RE |
27 | /* We can't use enum machine_mode inside a generator file because it |
28 | hasn't been created yet; we shouldn't be using any code that | |
29 | needs the real definition though, so this ought to be safe. */ | |
30 | #ifdef GENERATOR_FILE | |
31 | #define MACHMODE int | |
32 | #else | |
33 | #include "insn-modes.h" | |
34 | #define MACHMODE enum machine_mode | |
35 | #endif | |
36 | ||
9403b7f7 RS |
37 | #include "config/vxworks-dummy.h" |
38 | ||
35fd3193 | 39 | /* The architecture define. */ |
78011587 PB |
40 | extern char arm_arch_name[]; |
41 | ||
e6471be6 NB |
42 | /* Target CPU builtins. */ |
43 | #define TARGET_CPU_CPP_BUILTINS() \ | |
44 | do \ | |
45 | { \ | |
c884924f JG |
46 | if (TARGET_DSP_MULTIPLY) \ |
47 | builtin_define ("__ARM_FEATURE_DSP"); \ | |
9e94a7fc MGD |
48 | if (TARGET_ARM_QBIT) \ |
49 | builtin_define ("__ARM_FEATURE_QBIT"); \ | |
50 | if (TARGET_ARM_SAT) \ | |
51 | builtin_define ("__ARM_FEATURE_SAT"); \ | |
021b5e6b KT |
52 | if (TARGET_CRYPTO) \ |
53 | builtin_define ("__ARM_FEATURE_CRYPTO"); \ | |
5d248b41 JG |
54 | if (unaligned_access) \ |
55 | builtin_define ("__ARM_FEATURE_UNALIGNED"); \ | |
582e2e43 KT |
56 | if (TARGET_CRC32) \ |
57 | builtin_define ("__ARM_FEATURE_CRC32"); \ | |
58 | if (TARGET_32BIT) \ | |
59 | builtin_define ("__ARM_32BIT_STATE"); \ | |
9e94a7fc MGD |
60 | if (TARGET_ARM_FEATURE_LDREX) \ |
61 | builtin_define_with_int_value ( \ | |
62 | "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ | |
63 | if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ | |
64 | || TARGET_ARM_ARCH_ISA_THUMB >=2) \ | |
65 | builtin_define ("__ARM_FEATURE_CLZ"); \ | |
66 | if (TARGET_INT_SIMD) \ | |
67 | builtin_define ("__ARM_FEATURE_SIMD32"); \ | |
68 | \ | |
69 | builtin_define_with_int_value ( \ | |
70 | "__ARM_SIZEOF_MINIMAL_ENUM", \ | |
71 | flag_short_enums ? 1 : 4); \ | |
72 | builtin_define_with_int_value ( \ | |
73 | "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \ | |
74 | if (TARGET_ARM_ARCH_PROFILE) \ | |
75 | builtin_define_with_int_value ( \ | |
76 | "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ | |
77 | \ | |
9b66ebb1 PB |
78 | /* Define __arm__ even when in thumb mode, for \ |
79 | consistency with armcc. */ \ | |
80 | builtin_define ("__arm__"); \ | |
9e94a7fc MGD |
81 | if (TARGET_ARM_ARCH) \ |
82 | builtin_define_with_int_value ( \ | |
83 | "__ARM_ARCH", TARGET_ARM_ARCH); \ | |
84 | if (arm_arch_notm) \ | |
85 | builtin_define ("__ARM_ARCH_ISA_ARM"); \ | |
61f0ccff | 86 | builtin_define ("__APCS_32__"); \ |
9b66ebb1 | 87 | if (TARGET_THUMB) \ |
e6471be6 | 88 | builtin_define ("__thumb__"); \ |
5b3e6663 PB |
89 | if (TARGET_THUMB2) \ |
90 | builtin_define ("__thumb2__"); \ | |
9e94a7fc MGD |
91 | if (TARGET_ARM_ARCH_ISA_THUMB) \ |
92 | builtin_define_with_int_value ( \ | |
93 | "__ARM_ARCH_ISA_THUMB", \ | |
94 | TARGET_ARM_ARCH_ISA_THUMB); \ | |
e6471be6 NB |
95 | \ |
96 | if (TARGET_BIG_END) \ | |
97 | { \ | |
98 | builtin_define ("__ARMEB__"); \ | |
9e94a7fc | 99 | builtin_define ("__ARM_BIG_ENDIAN"); \ |
e6471be6 NB |
100 | if (TARGET_THUMB) \ |
101 | builtin_define ("__THUMBEB__"); \ | |
102 | if (TARGET_LITTLE_WORDS) \ | |
103 | builtin_define ("__ARMWEL__"); \ | |
104 | } \ | |
105 | else \ | |
106 | { \ | |
107 | builtin_define ("__ARMEL__"); \ | |
108 | if (TARGET_THUMB) \ | |
109 | builtin_define ("__THUMBEL__"); \ | |
110 | } \ | |
111 | \ | |
e6471be6 NB |
112 | if (TARGET_SOFT_FLOAT) \ |
113 | builtin_define ("__SOFTFP__"); \ | |
114 | \ | |
9b66ebb1 | 115 | if (TARGET_VFP) \ |
b5b620a4 JT |
116 | builtin_define ("__VFP_FP__"); \ |
117 | \ | |
9e94a7fc MGD |
118 | if (TARGET_ARM_FP) \ |
119 | builtin_define_with_int_value ( \ | |
120 | "__ARM_FP", TARGET_ARM_FP); \ | |
121 | if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ | |
122 | builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ | |
123 | if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ | |
124 | builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ | |
125 | if (TARGET_FMA) \ | |
126 | builtin_define ("__ARM_FEATURE_FMA"); \ | |
127 | \ | |
88f77cba | 128 | if (TARGET_NEON) \ |
9e94a7fc MGD |
129 | { \ |
130 | builtin_define ("__ARM_NEON__"); \ | |
131 | builtin_define ("__ARM_NEON"); \ | |
132 | } \ | |
133 | if (TARGET_NEON_FP) \ | |
134 | builtin_define_with_int_value ( \ | |
135 | "__ARM_NEON_FP", TARGET_NEON_FP); \ | |
88f77cba | 136 | \ |
e6471be6 NB |
137 | /* Add a define for interworking. \ |
138 | Needed when building libgcc.a. */ \ | |
2ad4dcf9 | 139 | if (arm_cpp_interwork) \ |
e6471be6 NB |
140 | builtin_define ("__THUMB_INTERWORK__"); \ |
141 | \ | |
142 | builtin_assert ("cpu=arm"); \ | |
143 | builtin_assert ("machine=arm"); \ | |
78011587 PB |
144 | \ |
145 | builtin_define (arm_arch_name); \ | |
78011587 PB |
146 | if (arm_arch_xscale) \ |
147 | builtin_define ("__XSCALE__"); \ | |
148 | if (arm_arch_iwmmxt) \ | |
9e94a7fc MGD |
149 | { \ |
150 | builtin_define ("__IWMMXT__"); \ | |
151 | builtin_define ("__ARM_WMMX"); \ | |
152 | } \ | |
8fd03515 XQ |
153 | if (arm_arch_iwmmxt2) \ |
154 | builtin_define ("__IWMMXT2__"); \ | |
4adf3e34 | 155 | if (TARGET_AAPCS_BASED) \ |
12ffc7d5 CLT |
156 | { \ |
157 | if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ | |
158 | builtin_define ("__ARM_PCS_VFP"); \ | |
159 | else if (arm_pcs_default == ARM_PCS_AAPCS) \ | |
160 | builtin_define ("__ARM_PCS"); \ | |
161 | builtin_define ("__ARM_EABI__"); \ | |
162 | } \ | |
572070ef PB |
163 | if (TARGET_IDIV) \ |
164 | builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ | |
e6471be6 NB |
165 | } while (0) |
166 | ||
ad7be009 | 167 | #include "config/arm/arm-opts.h" |
9b66ebb1 | 168 | |
78011587 PB |
169 | enum target_cpus |
170 | { | |
c0e25e65 JG |
171 | #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ |
172 | TARGET_CPU_##INTERNAL_IDENT, | |
78011587 PB |
173 | #include "arm-cores.def" |
174 | #undef ARM_CORE | |
175 | TARGET_CPU_generic | |
176 | }; | |
177 | ||
9b66ebb1 PB |
178 | /* The processor for which instructions should be scheduled. */ |
179 | extern enum processor_type arm_tune; | |
180 | ||
d5b7b3ae | 181 | typedef enum arm_cond_code |
89c7ca52 RE |
182 | { |
183 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
184 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
185 | } |
186 | arm_cc; | |
6cfc7210 | 187 | |
d5b7b3ae | 188 | extern arm_cc arm_current_cc; |
ff9940b0 | 189 | |
d5b7b3ae | 190 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 191 | |
b24a2ce5 GY |
192 | /* The maximaum number of instructions that is beneficial to |
193 | conditionally execute. */ | |
194 | #undef MAX_CONDITIONAL_EXECUTE | |
195 | #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () | |
196 | ||
6cfc7210 NC |
197 | extern int arm_target_label; |
198 | extern int arm_ccfsm_state; | |
e2500fed | 199 | extern GTY(()) rtx arm_target_insn; |
d5b7b3ae | 200 | /* The label of the current constant pool. */ |
e2500fed | 201 | extern rtx pool_vector_label; |
d5b7b3ae | 202 | /* Set to 1 when a return insn is output, this means that the epilogue |
d6b4baa4 | 203 | is not needed. */ |
d5b7b3ae | 204 | extern int return_used_this_function; |
b76c3c4b PB |
205 | /* Callback to output language specific object attributes. */ |
206 | extern void (*arm_lang_output_object_attributes_hook)(void); | |
35d965d5 | 207 | \f |
d6b4baa4 | 208 | /* Just in case configure has failed to define anything. */ |
7a801826 RE |
209 | #ifndef TARGET_CPU_DEFAULT |
210 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
211 | #endif | |
212 | ||
7a801826 | 213 | |
5742588d | 214 | #undef CPP_SPEC |
78011587 | 215 | #define CPP_SPEC "%(subtarget_cpp_spec) \ |
5e1b4d5a JM |
216 | %{mfloat-abi=soft:%{mfloat-abi=hard: \ |
217 | %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ | |
e6471be6 NB |
218 | %{mbig-endian:%{mlittle-endian: \ |
219 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 220 | |
be393ecf | 221 | #ifndef CC1_SPEC |
dfa08768 | 222 | #define CC1_SPEC "" |
be393ecf | 223 | #endif |
7a801826 RE |
224 | |
225 | /* This macro defines names of additional specifications to put in the specs | |
226 | that can be used in various specifications like CC1_SPEC. Its definition | |
227 | is an initializer with a subgrouping for each command option. | |
228 | ||
229 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 230 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
231 | program. |
232 | ||
233 | Do not define this macro if it does not need to do anything. */ | |
234 | #define EXTRA_SPECS \ | |
38fc909b | 235 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
54e73f88 | 236 | { "asm_cpu_spec", ASM_CPU_SPEC }, \ |
7a801826 RE |
237 | SUBTARGET_EXTRA_SPECS |
238 | ||
914a3b8c | 239 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 240 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
241 | #endif |
242 | ||
6cfc7210 | 243 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 244 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 245 | #endif |
35d965d5 RS |
246 | \f |
247 | /* Run-time Target Specification. */ | |
9b66ebb1 | 248 | #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) |
72cdc543 PB |
249 | /* Use hardware floating point instructions. */ |
250 | #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
251 | /* Use hardware floating point calling convention. */ | |
252 | #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
d79f3032 | 253 | #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) |
5a9335ef | 254 | #define TARGET_IWMMXT (arm_arch_iwmmxt) |
8fd03515 | 255 | #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) |
5b3e6663 | 256 | #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) |
8fd03515 | 257 | #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) |
5b3e6663 | 258 | #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) |
d5b7b3ae RE |
259 | #define TARGET_ARM (! TARGET_THUMB) |
260 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
c54c7322 RS |
261 | #define TARGET_BACKTRACE (leaf_function_p () \ |
262 | ? TARGET_TPCS_LEAF_FRAME \ | |
263 | : TARGET_TPCS_FRAME) | |
b6685939 PB |
264 | #define TARGET_AAPCS_BASED \ |
265 | (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
3ada8e17 | 266 | |
d3585b76 DJ |
267 | #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) |
268 | #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
ccdc2164 | 269 | #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) |
d3585b76 | 270 | |
5b3e6663 PB |
271 | /* Only 16-bit thumb code. */ |
272 | #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
273 | /* Arm or Thumb-2 32-bit code. */ | |
274 | #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
275 | /* 32-bit Thumb-2 code. */ | |
276 | #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
bf98ec6c PB |
277 | /* Thumb-1 only. */ |
278 | #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
5b3e6663 | 279 | |
3383b7fa GY |
280 | #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ |
281 | && !TARGET_THUMB1) | |
282 | ||
582e2e43 KT |
283 | #define TARGET_CRC32 (arm_arch_crc) |
284 | ||
88f77cba | 285 | /* The following two macros concern the ability to execute coprocessor |
302c3d8e PB |
286 | instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently |
287 | only ever tested when we know we are generating for VFP hardware; we need | |
288 | to be more careful with TARGET_NEON as noted below. */ | |
88f77cba | 289 | |
302c3d8e | 290 | /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ |
d79f3032 | 291 | #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) |
302c3d8e PB |
292 | |
293 | /* FPU supports VFPv3 instructions. */ | |
d79f3032 | 294 | #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) |
302c3d8e | 295 | |
e0dc3601 PB |
296 | /* FPU only supports VFP single-precision instructions. */ |
297 | #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) | |
298 | ||
299 | /* FPU supports VFP double-precision instructions. */ | |
300 | #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) | |
301 | ||
302 | /* FPU supports half-precision floating-point with NEON element load/store. */ | |
d79f3032 PB |
303 | #define TARGET_NEON_FP16 \ |
304 | (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) | |
0fd8c3ad | 305 | |
e0dc3601 PB |
306 | /* FPU supports VFP half-precision floating-point. */ |
307 | #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) | |
308 | ||
9e94a7fc MGD |
309 | /* FPU supports fused-multiply-add operations. */ |
310 | #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) | |
311 | ||
1dd4fe1f KT |
312 | /* FPU is ARMv8 compatible. */ |
313 | #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) | |
314 | ||
595fefee MGD |
315 | /* FPU supports Crypto extensions. */ |
316 | #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) | |
317 | ||
88f77cba JB |
318 | /* FPU supports Neon instructions. The setting of this macro gets |
319 | revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
320 | and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
321 | available. */ | |
322 | #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ | |
d79f3032 | 323 | && TARGET_VFP && arm_fpu_desc->neon) |
f1adb0a9 | 324 | |
9e94a7fc MGD |
325 | /* Q-bit is present. */ |
326 | #define TARGET_ARM_QBIT \ | |
327 | (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) | |
328 | /* Saturation operation, e.g. SSAT. */ | |
329 | #define TARGET_ARM_SAT \ | |
330 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) | |
5b3e6663 PB |
331 | /* "DSP" multiply instructions, eg. SMULxy. */ |
332 | #define TARGET_DSP_MULTIPLY \ | |
60bd3528 | 333 | (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) |
5b3e6663 PB |
334 | /* Integer SIMD instructions, and extend-accumulate instructions. */ |
335 | #define TARGET_INT_SIMD \ | |
60bd3528 | 336 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) |
5b3e6663 | 337 | |
571191af | 338 | /* Should MOVW/MOVT be used in preference to a constant pool. */ |
7ec70105 | 339 | #define TARGET_USE_MOVT \ |
02231c13 TG |
340 | (arm_arch_thumb2 \ |
341 | && (arm_disable_literal_pool \ | |
342 | || (!optimize_size && !current_tune->prefer_constant_pool))) | |
571191af | 343 | |
5b3e6663 PB |
344 | /* We could use unified syntax for arm mode, but for now we just use it |
345 | for Thumb-2. */ | |
346 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | |
347 | ||
029e79eb | 348 | /* Nonzero if this chip provides the DMB instruction. */ |
9e2a6301 | 349 | #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) |
029e79eb MS |
350 | |
351 | /* Nonzero if this chip implements a memory barrier via CP15. */ | |
80651d8e DAG |
352 | #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ |
353 | && ! TARGET_THUMB1) | |
029e79eb MS |
354 | |
355 | /* Nonzero if this chip implements a memory barrier instruction. */ | |
356 | #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | |
357 | ||
358 | /* Nonzero if this chip supports ldrex and strex */ | |
359 | #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) | |
360 | ||
cfe52743 DAG |
361 | /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ |
362 | #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) | |
363 | ||
364 | /* Nonzero if this chip supports ldrexd and strexd. */ | |
365 | #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ | |
366 | && arm_arch_notm) | |
5b3e6663 | 367 | |
5ad29f12 KT |
368 | /* Nonzero if this chip supports load-acquire and store-release. */ |
369 | #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) | |
370 | ||
572070ef PB |
371 | /* Nonzero if integer division instructions supported. */ |
372 | #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ | |
373 | || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) | |
374 | ||
65074f54 CL |
375 | /* Should NEON be used for 64-bits bitops. */ |
376 | #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) | |
377 | ||
b3f8d95d MM |
378 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, |
379 | then TARGET_AAPCS_BASED must be true -- but the converse does not | |
380 | hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
381 | etc., in addition to just the AAPCS calling conventions. */ | |
382 | #ifndef TARGET_BPABI | |
383 | #define TARGET_BPABI false | |
f676971a | 384 | #endif |
b3f8d95d | 385 | |
7816bea0 DJ |
386 | /* Support for a compile-time default CPU, et cetera. The rules are: |
387 | --with-arch is ignored if -march or -mcpu are specified. | |
388 | --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
389 | by --with-arch. | |
390 | --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
391 | by -march). | |
5e1b4d5a | 392 | --with-float is ignored if -mfloat-abi is specified. |
5848830f | 393 | --with-fpu is ignored if -mfpu is specified. |
ccdc2164 NS |
394 | --with-abi is ignored if -mabi is specified. |
395 | --with-tls is ignored if -mtls-dialect is specified. */ | |
7816bea0 DJ |
396 | #define OPTION_DEFAULT_SPECS \ |
397 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
398 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
399 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
5e1b4d5a | 400 | {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ |
5848830f | 401 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
3cf94279 | 402 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ |
ccdc2164 | 403 | {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ |
7cf13d1f | 404 | {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, |
7816bea0 | 405 | |
9b66ebb1 PB |
406 | /* Which floating point model to use. */ |
407 | enum arm_fp_model | |
408 | { | |
409 | ARM_FP_MODEL_UNKNOWN, | |
9b66ebb1 PB |
410 | /* VFP floating point model. */ |
411 | ARM_FP_MODEL_VFP | |
412 | }; | |
413 | ||
d79f3032 | 414 | enum vfp_reg_type |
24f0c1b4 | 415 | { |
70dd156a | 416 | VFP_NONE = 0, |
d79f3032 PB |
417 | VFP_REG_D16, |
418 | VFP_REG_D32, | |
419 | VFP_REG_SINGLE | |
24f0c1b4 RE |
420 | }; |
421 | ||
d79f3032 PB |
422 | extern const struct arm_fpu_desc |
423 | { | |
424 | const char *name; | |
425 | enum arm_fp_model model; | |
426 | int rev; | |
427 | enum vfp_reg_type regs; | |
428 | int neon; | |
429 | int fp16; | |
595fefee | 430 | int crypto; |
d79f3032 PB |
431 | } *arm_fpu_desc; |
432 | ||
433 | /* Which floating point hardware to schedule for. */ | |
434 | extern int arm_fpu_attr; | |
71791e16 | 435 | |
3d8532aa PB |
436 | #ifndef TARGET_DEFAULT_FLOAT_ABI |
437 | #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
438 | #endif | |
439 | ||
0fd8c3ad SL |
440 | #define LARGEST_EXPONENT_IS_NORMAL(bits) \ |
441 | ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) | |
442 | ||
5848830f PB |
443 | #ifndef ARM_DEFAULT_ABI |
444 | #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
445 | #endif | |
446 | ||
9e94a7fc MGD |
447 | /* Map each of the micro-architecture variants to their corresponding |
448 | major architecture revision. */ | |
449 | ||
450 | enum base_architecture | |
451 | { | |
452 | BASE_ARCH_0 = 0, | |
453 | BASE_ARCH_2 = 2, | |
454 | BASE_ARCH_3 = 3, | |
455 | BASE_ARCH_3M = 3, | |
456 | BASE_ARCH_4 = 4, | |
457 | BASE_ARCH_4T = 4, | |
458 | BASE_ARCH_5 = 5, | |
459 | BASE_ARCH_5E = 5, | |
460 | BASE_ARCH_5T = 5, | |
461 | BASE_ARCH_5TE = 5, | |
462 | BASE_ARCH_5TEJ = 5, | |
463 | BASE_ARCH_6 = 6, | |
464 | BASE_ARCH_6J = 6, | |
465 | BASE_ARCH_6ZK = 6, | |
466 | BASE_ARCH_6K = 6, | |
467 | BASE_ARCH_6T2 = 6, | |
468 | BASE_ARCH_6M = 6, | |
469 | BASE_ARCH_6Z = 6, | |
470 | BASE_ARCH_7 = 7, | |
471 | BASE_ARCH_7A = 7, | |
472 | BASE_ARCH_7R = 7, | |
473 | BASE_ARCH_7M = 7, | |
595fefee MGD |
474 | BASE_ARCH_7EM = 7, |
475 | BASE_ARCH_8A = 8 | |
9e94a7fc MGD |
476 | }; |
477 | ||
478 | /* The major revision number of the ARM Architecture implemented by the target. */ | |
479 | extern enum base_architecture arm_base_arch; | |
480 | ||
9b66ebb1 PB |
481 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
482 | extern int arm_arch3m; | |
11c1a207 | 483 | |
9b66ebb1 | 484 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
11c1a207 RE |
485 | extern int arm_arch4; |
486 | ||
68d560d4 RE |
487 | /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ |
488 | extern int arm_arch4t; | |
489 | ||
9b66ebb1 | 490 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
491 | extern int arm_arch5; |
492 | ||
9b66ebb1 | 493 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
b15bca31 RE |
494 | extern int arm_arch5e; |
495 | ||
9b66ebb1 PB |
496 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
497 | extern int arm_arch6; | |
498 | ||
029e79eb MS |
499 | /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ |
500 | extern int arm_arch6k; | |
501 | ||
9e2a6301 TG |
502 | /* Nonzero if instructions present in ARMv6-M can be used. */ |
503 | extern int arm_arch6m; | |
504 | ||
029e79eb MS |
505 | /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ |
506 | extern int arm_arch7; | |
507 | ||
5b3e6663 PB |
508 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
509 | extern int arm_arch_notm; | |
510 | ||
60bd3528 PB |
511 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
512 | extern int arm_arch7em; | |
513 | ||
595fefee MGD |
514 | /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ |
515 | extern int arm_arch8; | |
516 | ||
f5a1b0d2 NC |
517 | /* Nonzero if this chip can benefit from load scheduling. */ |
518 | extern int arm_ld_sched; | |
519 | ||
906668bb | 520 | /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ |
0616531f RE |
521 | extern int thumb_code; |
522 | ||
906668bb BS |
523 | /* Nonzero if generating Thumb-1 code. */ |
524 | extern int thumb1_code; | |
525 | ||
f5a1b0d2 | 526 | /* Nonzero if this chip is a StrongARM. */ |
abac3b49 | 527 | extern int arm_tune_strongarm; |
f5a1b0d2 | 528 | |
5a9335ef NC |
529 | /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ |
530 | extern int arm_arch_iwmmxt; | |
531 | ||
8fd03515 XQ |
532 | /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ |
533 | extern int arm_arch_iwmmxt2; | |
534 | ||
d19fb8e3 | 535 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
536 | extern int arm_arch_xscale; |
537 | ||
abac3b49 | 538 | /* Nonzero if tuning for XScale. */ |
4b3c2e48 | 539 | extern int arm_tune_xscale; |
d19fb8e3 | 540 | |
abac3b49 RE |
541 | /* Nonzero if tuning for stores via the write buffer. */ |
542 | extern int arm_tune_wbuf; | |
f5a1b0d2 | 543 | |
7612f14d PB |
544 | /* Nonzero if tuning for Cortex-A9. */ |
545 | extern int arm_tune_cortex_a9; | |
546 | ||
2ad4dcf9 | 547 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 548 | preprocessor. |
2ad4dcf9 RE |
549 | XXX This is a bit of a hack, it's intended to help work around |
550 | problems in GLD which doesn't understand that armv5t code is | |
551 | interworking clean. */ | |
552 | extern int arm_cpp_interwork; | |
553 | ||
5b3e6663 PB |
554 | /* Nonzero if chip supports Thumb 2. */ |
555 | extern int arm_arch_thumb2; | |
556 | ||
572070ef PB |
557 | /* Nonzero if chip supports integer division instruction in ARM mode. */ |
558 | extern int arm_arch_arm_hwdiv; | |
559 | ||
560 | /* Nonzero if chip supports integer division instruction in Thumb mode. */ | |
561 | extern int arm_arch_thumb_hwdiv; | |
5b3e6663 | 562 | |
65074f54 CL |
563 | /* Nonzero if we should use Neon to handle 64-bits operations rather |
564 | than core registers. */ | |
565 | extern int prefer_neon_for_64bits; | |
566 | ||
02231c13 TG |
567 | /* Nonzero if we shouldn't use literal pools. */ |
568 | #ifndef USED_FOR_TARGET | |
569 | extern bool arm_disable_literal_pool; | |
570 | #endif | |
571 | ||
582e2e43 KT |
572 | /* Nonzero if chip supports the ARMv8 CRC instructions. */ |
573 | extern int arm_arch_crc; | |
574 | ||
2ce9c1b9 | 575 | #ifndef TARGET_DEFAULT |
c54c7322 | 576 | #define TARGET_DEFAULT (MASK_APCS_FRAME) |
2ce9c1b9 | 577 | #endif |
35d965d5 | 578 | |
86efdc8e PB |
579 | /* Nonzero if PIC code requires explicit qualifiers to generate |
580 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
581 | Subtargets can override these if required. */ |
582 | #ifndef NEED_GOT_RELOC | |
583 | #define NEED_GOT_RELOC 0 | |
584 | #endif | |
585 | #ifndef NEED_PLT_RELOC | |
586 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 587 | #endif |
84306176 | 588 | |
32d6e6c0 JY |
589 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
590 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
591 | #endif | |
592 | ||
84306176 PB |
593 | /* Nonzero if we need to refer to the GOT with a PC-relative |
594 | offset. In other words, generate | |
595 | ||
f676971a | 596 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] |
84306176 PB |
597 | |
598 | rather than | |
599 | ||
600 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
601 | ||
f676971a | 602 | The default is true, which matches NetBSD. Subtargets can |
84306176 PB |
603 | override this if required. */ |
604 | #ifndef GOT_PCREL | |
605 | #define GOT_PCREL 1 | |
606 | #endif | |
35d965d5 RS |
607 | \f |
608 | /* Target machine storage Layout. */ | |
609 | ||
ff9940b0 RE |
610 | |
611 | /* Define this macro if it is advisable to hold scalars in registers | |
612 | in a wider mode than that declared by the program. In such cases, | |
613 | the value is constrained to be within the bounds of the declared | |
614 | type, but kept valid in the wider mode. The signedness of the | |
615 | extension may differ from that of the type. */ | |
616 | ||
617 | /* It is far faster to zero extend chars than to sign extend them */ | |
618 | ||
6cfc7210 | 619 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
620 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
621 | && GET_MODE_SIZE (MODE) < 4) \ | |
622 | { \ | |
623 | if (MODE == QImode) \ | |
624 | UNSIGNEDP = 1; \ | |
625 | else if (MODE == HImode) \ | |
61f0ccff | 626 | UNSIGNEDP = 1; \ |
2ce9c1b9 | 627 | (MODE) = SImode; \ |
ff9940b0 RE |
628 | } |
629 | ||
35d965d5 RS |
630 | /* Define this if most significant bit is lowest numbered |
631 | in instructions that operate on numbered bit-fields. */ | |
632 | #define BITS_BIG_ENDIAN 0 | |
633 | ||
f676971a | 634 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
635 | Most ARM processors are run in little endian mode, so that is the default. |
636 | If you want to have it run-time selectable, change the definition in a | |
637 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 638 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
639 | |
640 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
641 | numbered. |
642 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
643 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
644 | ||
35d965d5 RS |
645 | #define UNITS_PER_WORD 4 |
646 | ||
5848830f | 647 | /* True if natural alignment is used for doubleword types. */ |
b6685939 PB |
648 | #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED |
649 | ||
5848830f | 650 | #define DOUBLEWORD_ALIGNMENT 64 |
35d965d5 | 651 | |
5848830f | 652 | #define PARM_BOUNDARY 32 |
5a9335ef | 653 | |
5848830f | 654 | #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
35d965d5 | 655 | |
5848830f PB |
656 | #define PREFERRED_STACK_BOUNDARY \ |
657 | (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
0977774b | 658 | |
f711a87a | 659 | #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) |
35d965d5 | 660 | |
92928d71 AO |
661 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
662 | vbit must go into the delta field of pointers to member | |
663 | functions. */ | |
664 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
665 | ||
35d965d5 RS |
666 | #define EMPTY_FIELD_BOUNDARY 32 |
667 | ||
5848830f | 668 | #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
5a9335ef | 669 | |
f276d31d BE |
670 | #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT |
671 | ||
27847754 NC |
672 | /* XXX Blah -- this macro is used directly by libobjc. Since it |
673 | supports no vector modes, cut out the complexity and fall back | |
674 | on BIGGEST_FIELD_ALIGNMENT. */ | |
675 | #ifdef IN_TARGET_LIBS | |
8fca31a2 | 676 | #define BIGGEST_FIELD_ALIGNMENT 64 |
27847754 | 677 | #endif |
5a9335ef | 678 | |
ff9940b0 | 679 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
591af218 | 680 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) |
f676971a | 681 | |
d19fb8e3 | 682 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
5848830f | 683 | ((TREE_CODE (EXP) == STRING_CST \ |
36b15ad0 | 684 | && !optimize_size \ |
5848830f PB |
685 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ |
686 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 687 | |
96339268 RE |
688 | /* Align definitions of arrays, unions and structures so that |
689 | initializations and copies can be made more efficient. This is not | |
690 | ABI-changing, so it only affects places where we can see the | |
0c86e0dd CLT |
691 | definition. Increasing the alignment tends to introduce padding, |
692 | so don't do this when optimizing for size/conserving stack space. */ | |
693 | #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
694 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
96339268 RE |
695 | && (TREE_CODE (EXP) == ARRAY_TYPE \ |
696 | || TREE_CODE (EXP) == UNION_TYPE \ | |
697 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
698 | ||
0c86e0dd CLT |
699 | /* Align global data. */ |
700 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
701 | ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) | |
702 | ||
96339268 | 703 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ |
0c86e0dd CLT |
704 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ |
705 | ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) | |
96339268 | 706 | |
723ae7c1 NC |
707 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
708 | value set in previous versions of this toolchain was 8, which produces more | |
709 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 710 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 | 711 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
5848830f PB |
712 | 0020D) page 2-20 says "Structures are aligned on word boundaries". |
713 | The AAPCS specifies a value of 8. */ | |
6ead9ba5 | 714 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
723ae7c1 | 715 | |
4912a07c | 716 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 717 | particular arm target wants to change the default value it should change |
6bc82793 | 718 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
719 | for an example of this. */ |
720 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
721 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 722 | #endif |
2a5307b1 | 723 | |
825dda42 | 724 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 725 | when given unaligned data. */ |
35d965d5 | 726 | #define STRICT_ALIGNMENT 1 |
b6685939 PB |
727 | |
728 | /* wchar_t is unsigned under the AAPCS. */ | |
729 | #ifndef WCHAR_TYPE | |
730 | #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
731 | ||
732 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
733 | #endif | |
734 | ||
655b30bf JB |
735 | /* Sized for fixed-point types. */ |
736 | ||
737 | #define SHORT_FRACT_TYPE_SIZE 8 | |
738 | #define FRACT_TYPE_SIZE 16 | |
739 | #define LONG_FRACT_TYPE_SIZE 32 | |
740 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
741 | ||
742 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
743 | #define ACCUM_TYPE_SIZE 32 | |
744 | #define LONG_ACCUM_TYPE_SIZE 64 | |
745 | #define LONG_LONG_ACCUM_TYPE_SIZE 64 | |
746 | ||
747 | #define MAX_FIXED_MODE_SIZE 64 | |
748 | ||
b6685939 PB |
749 | #ifndef SIZE_TYPE |
750 | #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
751 | #endif | |
d81d0bdd | 752 | |
077fc835 KH |
753 | #ifndef PTRDIFF_TYPE |
754 | #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
755 | #endif | |
756 | ||
d81d0bdd PB |
757 | /* AAPCS requires that structure alignment is affected by bitfields. */ |
758 | #ifndef PCC_BITFIELD_TYPE_MATTERS | |
759 | #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
760 | #endif | |
761 | ||
35d965d5 RS |
762 | \f |
763 | /* Standard register usage. */ | |
764 | ||
0be8bd1a | 765 | /* Register allocation in ARM Procedure Call Standard |
35d965d5 RS |
766 | (S - saved over call). |
767 | ||
768 | r0 * argument word/integer result | |
769 | r1-r3 argument word | |
770 | ||
771 | r4-r8 S register variable | |
772 | r9 S (rfp) register variable (real frame pointer) | |
f676971a | 773 | |
f5a1b0d2 | 774 | r10 F S (sl) stack limit (used by -mapcs-stack-check) |
35d965d5 RS |
775 | r11 F S (fp) argument pointer |
776 | r12 (ip) temp workspace | |
777 | r13 F S (sp) lower end of current stack frame | |
778 | r14 (lr) link address/workspace | |
779 | r15 F (pc) program counter | |
780 | ||
ff9940b0 RE |
781 | cc This is NOT a real register, but is used internally |
782 | to represent things that use or set the condition | |
783 | codes. | |
784 | sfp This isn't either. It is used during rtl generation | |
785 | since the offset between the frame pointer and the | |
786 | auto's isn't known until after register allocation. | |
787 | afp Nor this, we only need this because of non-local | |
788 | goto. Without it fp appears to be used and the | |
789 | elimination code won't get rid of sfp. It tracks | |
790 | fp exactly at all times. | |
791 | ||
5efd84c5 | 792 | *: See TARGET_CONDITIONAL_REGISTER_USAGE */ |
35d965d5 | 793 | |
9b66ebb1 PB |
794 | /* s0-s15 VFP scratch (aka d0-d7). |
795 | s16-s31 S VFP variable (aka d8-d15). | |
796 | vfpcc Not a real register. Represents the VFP condition | |
797 | code flags. */ | |
798 | ||
ff9940b0 RE |
799 | /* The stack backtrace structure is as follows: |
800 | fp points to here: | save code pointer | [fp] | |
801 | | return link value | [fp, #-4] | |
802 | | return sp value | [fp, #-8] | |
803 | | return fp value | [fp, #-12] | |
804 | [| saved r10 value |] | |
805 | [| saved r9 value |] | |
806 | [| saved r8 value |] | |
807 | [| saved r7 value |] | |
808 | [| saved r6 value |] | |
809 | [| saved r5 value |] | |
810 | [| saved r4 value |] | |
811 | [| saved r3 value |] | |
812 | [| saved r2 value |] | |
813 | [| saved r1 value |] | |
814 | [| saved r0 value |] | |
ff9940b0 RE |
815 | r0-r3 are not normally saved in a C function. */ |
816 | ||
35d965d5 RS |
817 | /* 1 for registers that have pervasive standard uses |
818 | and are not available for the register allocator. */ | |
0be8bd1a RE |
819 | #define FIXED_REGISTERS \ |
820 | { \ | |
821 | /* Core regs. */ \ | |
822 | 0,0,0,0,0,0,0,0, \ | |
823 | 0,0,0,0,0,1,0,1, \ | |
824 | /* VFP regs. */ \ | |
825 | 1,1,1,1,1,1,1,1, \ | |
826 | 1,1,1,1,1,1,1,1, \ | |
827 | 1,1,1,1,1,1,1,1, \ | |
828 | 1,1,1,1,1,1,1,1, \ | |
829 | 1,1,1,1,1,1,1,1, \ | |
830 | 1,1,1,1,1,1,1,1, \ | |
831 | 1,1,1,1,1,1,1,1, \ | |
832 | 1,1,1,1,1,1,1,1, \ | |
833 | /* IWMMXT regs. */ \ | |
834 | 1,1,1,1,1,1,1,1, \ | |
835 | 1,1,1,1,1,1,1,1, \ | |
836 | 1,1,1,1, \ | |
837 | /* Specials. */ \ | |
838 | 1,1,1,1 \ | |
35d965d5 RS |
839 | } |
840 | ||
841 | /* 1 for registers not available across function calls. | |
842 | These must include the FIXED_REGISTERS and also any | |
843 | registers that can be used without being saved. | |
844 | The latter must include the registers where values are returned | |
845 | and the register where structure-value addresses are passed. | |
ff9940b0 | 846 | Aside from that, you can include as many other registers as you like. |
f676971a | 847 | The CC is not preserved over function calls on the ARM 6, so it is |
d6b4baa4 | 848 | easier to assume this for all. SFP is preserved, since FP is. */ |
0be8bd1a RE |
849 | #define CALL_USED_REGISTERS \ |
850 | { \ | |
851 | /* Core regs. */ \ | |
852 | 1,1,1,1,0,0,0,0, \ | |
853 | 0,0,0,0,1,1,1,1, \ | |
854 | /* VFP Regs. */ \ | |
855 | 1,1,1,1,1,1,1,1, \ | |
856 | 1,1,1,1,1,1,1,1, \ | |
857 | 1,1,1,1,1,1,1,1, \ | |
858 | 1,1,1,1,1,1,1,1, \ | |
859 | 1,1,1,1,1,1,1,1, \ | |
860 | 1,1,1,1,1,1,1,1, \ | |
861 | 1,1,1,1,1,1,1,1, \ | |
862 | 1,1,1,1,1,1,1,1, \ | |
863 | /* IWMMXT regs. */ \ | |
864 | 1,1,1,1,1,1,1,1, \ | |
865 | 1,1,1,1,1,1,1,1, \ | |
866 | 1,1,1,1, \ | |
867 | /* Specials. */ \ | |
868 | 1,1,1,1 \ | |
35d965d5 RS |
869 | } |
870 | ||
6cc8c0b3 NC |
871 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
872 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
873 | #endif | |
874 | ||
6bc82793 | 875 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
876 | by asm_fprintf: |
877 | %@ prints out ASM_COMMENT_START | |
878 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
879 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
880 | case '@': \ | |
881 | fputs (ASM_COMMENT_START, FILE); \ | |
882 | break; \ | |
883 | \ | |
884 | case 'r': \ | |
885 | fputs (REGISTER_PREFIX, FILE); \ | |
886 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
887 | break; | |
888 | ||
d5b7b3ae | 889 | /* Round X up to the nearest word. */ |
0c2ca901 | 890 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 891 | |
6cfc7210 | 892 | /* Convert fron bytes to ints. */ |
e9d7b180 | 893 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 | 894 | |
9b66ebb1 PB |
895 | /* The number of (integer) registers required to hold a quantity of type MODE. |
896 | Also used for VFP registers. */ | |
e9d7b180 JD |
897 | #define ARM_NUM_REGS(MODE) \ |
898 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
899 | |
900 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
901 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
902 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 903 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
904 | |
905 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 906 | #define NUM_ARG_REGS 4 |
6cfc7210 | 907 | |
390b17c2 RE |
908 | /* And similarly for the VFP. */ |
909 | #define NUM_VFP_ARG_REGS 16 | |
910 | ||
093354e0 | 911 | /* Return the register number of the N'th (integer) argument. */ |
d5b7b3ae | 912 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 913 | |
d5b7b3ae RE |
914 | /* Specify the registers used for certain standard purposes. |
915 | The values of these macros are register numbers. */ | |
35d965d5 | 916 | |
d5b7b3ae RE |
917 | /* The number of the last argument register. */ |
918 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 919 | |
c769a35d RE |
920 | /* The numbers of the Thumb register ranges. */ |
921 | #define FIRST_LO_REGNUM 0 | |
6d3d9133 | 922 | #define LAST_LO_REGNUM 7 |
c769a35d RE |
923 | #define FIRST_HI_REGNUM 8 |
924 | #define LAST_HI_REGNUM 11 | |
6d3d9133 | 925 | |
f0a0390e RH |
926 | /* Overridden by config/arm/bpabi.h. */ |
927 | #ifndef ARM_UNWIND_INFO | |
928 | #define ARM_UNWIND_INFO 0 | |
617a1b71 PB |
929 | #endif |
930 | ||
c9ca9b88 PB |
931 | /* Use r0 and r1 to pass exception handling information. */ |
932 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
933 | ||
6d3d9133 | 934 | /* The register that holds the return address in exception handlers. */ |
c9ca9b88 PB |
935 | #define ARM_EH_STACKADJ_REGNUM 2 |
936 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
35d965d5 | 937 | |
1e874273 PB |
938 | #ifndef ARM_TARGET2_DWARF_FORMAT |
939 | #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel | |
940 | ||
941 | /* ttype entries (the only interesting data references used) | |
942 | use TARGET2 relocations. */ | |
943 | #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ | |
944 | (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ | |
945 | : DW_EH_PE_absptr) | |
946 | #endif | |
947 | ||
d5b7b3ae RE |
948 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
949 | as an invisible last argument (possible since varargs don't exist in | |
950 | Pascal), so the following is not true. */ | |
5b3e6663 | 951 | #define STATIC_CHAIN_REGNUM 12 |
35d965d5 | 952 | |
d5b7b3ae RE |
953 | /* Define this to be where the real frame pointer is if it is not possible to |
954 | work out the offset between the frame pointer and the automatic variables | |
955 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
956 | should point to a special register that we will make sure is eliminated. | |
957 | ||
958 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 959 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
960 | as base register for addressing purposes. (See comments in |
961 | find_reloads_address()). But - the Thumb does not allow high registers, | |
962 | including r11, to be used as base address registers. Hence our problem. | |
963 | ||
964 | The solution used here, and in the old thumb port is to use r7 instead of | |
965 | r11 as the hard frame pointer and to have special code to generate | |
966 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 967 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
968 | pointer. */ |
969 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
970 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 971 | |
b15bca31 RE |
972 | #define HARD_FRAME_POINTER_REGNUM \ |
973 | (TARGET_ARM \ | |
974 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
975 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 976 | |
e3339d0f JM |
977 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
978 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
979 | ||
b15bca31 | 980 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 981 | |
b15bca31 RE |
982 | /* Register to use for pushing function arguments. */ |
983 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae | 984 | |
0be8bd1a RE |
985 | #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) |
986 | #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) | |
a76213b9 XQ |
987 | |
988 | /* Need to sync with WCGR in iwmmxt.md. */ | |
0be8bd1a RE |
989 | #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) |
990 | #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) | |
d5b7b3ae | 991 | |
5a9335ef NC |
992 | #define IS_IWMMXT_REGNUM(REGNUM) \ |
993 | (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
994 | #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
995 | (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
996 | ||
35d965d5 | 997 | /* Base register for access to local variables of the function. */ |
0be8bd1a | 998 | #define FRAME_POINTER_REGNUM 102 |
ff9940b0 | 999 | |
d5b7b3ae | 1000 | /* Base register for access to arguments of the function. */ |
0be8bd1a | 1001 | #define ARG_POINTER_REGNUM 103 |
62b10bbc | 1002 | |
0be8bd1a RE |
1003 | #define FIRST_VFP_REGNUM 16 |
1004 | #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) | |
f1adb0a9 | 1005 | #define LAST_VFP_REGNUM \ |
302c3d8e | 1006 | (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) |
f1adb0a9 | 1007 | |
9b66ebb1 PB |
1008 | #define IS_VFP_REGNUM(REGNUM) \ |
1009 | (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
1010 | ||
f1adb0a9 JB |
1011 | /* VFP registers are split into two types: those defined by VFP versions < 3 |
1012 | have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
1013 | defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
1014 | in various parts of the backend, we implement as "fake" single-precision | |
1015 | registers (which would be S32-S63, but cannot be used in that way). The | |
1016 | following macros define these ranges of registers. */ | |
0be8bd1a RE |
1017 | #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) |
1018 | #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) | |
1019 | #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) | |
f1adb0a9 JB |
1020 | |
1021 | #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
1022 | ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
1023 | ||
1024 | /* DFmode values are only valid in even register pairs. */ | |
1025 | #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
1026 | ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
1027 | ||
88f77cba JB |
1028 | /* Neon Quad values must start at a multiple of four registers. */ |
1029 | #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
1030 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
1031 | ||
1032 | /* Neon structures of vectors must be in even register pairs and there | |
1033 | must be enough registers available. Because of various patterns | |
1034 | requiring quad registers, we require them to start at a multiple of | |
1035 | four. */ | |
1036 | #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
1037 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
1038 | && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
1039 | ||
0be8bd1a | 1040 | /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ |
5a9335ef | 1041 | /* Intel Wireless MMX Technology registers add 16 + 4 more. */ |
0be8bd1a RE |
1042 | /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ |
1043 | #define FIRST_PSEUDO_REGISTER 104 | |
62b10bbc | 1044 | |
2fa330b2 PB |
1045 | #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) |
1046 | ||
35d965d5 RS |
1047 | /* Value should be nonzero if functions must have frame pointers. |
1048 | Zero means the frame pointer need not be set up (and parms may be accessed | |
f676971a | 1049 | via the stack pointer) in functions that seem suitable. |
ff9940b0 RE |
1050 | If we have to have a frame pointer we might as well make use of it. |
1051 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 1052 | functions, or simple tail call functions. */ |
a15900b5 DJ |
1053 | |
1054 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1055 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1056 | #endif | |
1057 | ||
d5b7b3ae RE |
1058 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1059 | to hold something of mode MODE. | |
1060 | This is ordinarily the length in words of a value of mode MODE | |
1061 | but can be less for certain modes in special long registers. | |
35d965d5 | 1062 | |
0be8bd1a | 1063 | On the ARM core regs are UNITS_PER_WORD bits wide. */ |
d5b7b3ae | 1064 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
5b3e6663 | 1065 | ((TARGET_32BIT \ |
0be8bd1a | 1066 | && REGNO > PC_REGNUM \ |
d5b7b3ae RE |
1067 | && REGNO != FRAME_POINTER_REGNUM \ |
1068 | && REGNO != ARG_POINTER_REGNUM) \ | |
9b66ebb1 | 1069 | && !IS_VFP_REGNUM (REGNO) \ |
e9d7b180 | 1070 | ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 1071 | |
4b02997f | 1072 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 1073 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 1074 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 1075 | |
2af8e257 | 1076 | #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) |
ff9940b0 | 1077 | |
5a9335ef | 1078 | #define VALID_IWMMXT_REG_MODE(MODE) \ |
f676971a | 1079 | (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) |
5a9335ef | 1080 | |
88f77cba JB |
1081 | /* Modes valid for Neon D registers. */ |
1082 | #define VALID_NEON_DREG_MODE(MODE) \ | |
1083 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
5819f96f | 1084 | || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) |
88f77cba JB |
1085 | |
1086 | /* Modes valid for Neon Q registers. */ | |
1087 | #define VALID_NEON_QREG_MODE(MODE) \ | |
1088 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
1089 | || (MODE) == V4SFmode || (MODE) == V2DImode) | |
1090 | ||
1091 | /* Structure modes valid for Neon registers. */ | |
1092 | #define VALID_NEON_STRUCT_MODE(MODE) \ | |
1093 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
1094 | || (MODE) == CImode || (MODE) == XImode) | |
1095 | ||
37119410 BS |
1096 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
1097 | extern int arm_regs_in_sequence[]; | |
1098 | ||
35d965d5 | 1099 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1100 | since no saving is required (though calls clobber it) and it never contains |
1101 | function parameters. It is quite good to use lr since other calls may | |
f676971a | 1102 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is |
ff9940b0 | 1103 | least likely to contain a function parameter; in addition results are |
f1adb0a9 JB |
1104 | returned in r0. |
1105 | For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
1106 | then D8-D15. The reason for doing this is to attempt to reduce register | |
1107 | pressure when both single- and double-precision registers are used in a | |
1108 | function. */ | |
1109 | ||
0be8bd1a RE |
1110 | #define VREG(X) (FIRST_VFP_REGNUM + (X)) |
1111 | #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) | |
1112 | #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) | |
1113 | ||
f1adb0a9 JB |
1114 | #define REG_ALLOC_ORDER \ |
1115 | { \ | |
0be8bd1a RE |
1116 | /* General registers. */ \ |
1117 | 3, 2, 1, 0, 12, 14, 4, 5, \ | |
1118 | 6, 7, 8, 9, 10, 11, \ | |
1119 | /* High VFP registers. */ \ | |
1120 | VREG(32), VREG(33), VREG(34), VREG(35), \ | |
1121 | VREG(36), VREG(37), VREG(38), VREG(39), \ | |
1122 | VREG(40), VREG(41), VREG(42), VREG(43), \ | |
1123 | VREG(44), VREG(45), VREG(46), VREG(47), \ | |
1124 | VREG(48), VREG(49), VREG(50), VREG(51), \ | |
1125 | VREG(52), VREG(53), VREG(54), VREG(55), \ | |
1126 | VREG(56), VREG(57), VREG(58), VREG(59), \ | |
1127 | VREG(60), VREG(61), VREG(62), VREG(63), \ | |
1128 | /* VFP argument registers. */ \ | |
1129 | VREG(15), VREG(14), VREG(13), VREG(12), \ | |
1130 | VREG(11), VREG(10), VREG(9), VREG(8), \ | |
1131 | VREG(7), VREG(6), VREG(5), VREG(4), \ | |
1132 | VREG(3), VREG(2), VREG(1), VREG(0), \ | |
1133 | /* VFP call-saved registers. */ \ | |
1134 | VREG(16), VREG(17), VREG(18), VREG(19), \ | |
1135 | VREG(20), VREG(21), VREG(22), VREG(23), \ | |
1136 | VREG(24), VREG(25), VREG(26), VREG(27), \ | |
1137 | VREG(28), VREG(29), VREG(30), VREG(31), \ | |
1138 | /* IWMMX registers. */ \ | |
1139 | WREG(0), WREG(1), WREG(2), WREG(3), \ | |
1140 | WREG(4), WREG(5), WREG(6), WREG(7), \ | |
1141 | WREG(8), WREG(9), WREG(10), WREG(11), \ | |
1142 | WREG(12), WREG(13), WREG(14), WREG(15), \ | |
1143 | WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ | |
1144 | /* Registers not for general use. */ \ | |
1145 | CC_REGNUM, VFPCC_REGNUM, \ | |
1146 | FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ | |
1147 | SP_REGNUM, PC_REGNUM \ | |
35d965d5 | 1148 | } |
9338ffe6 | 1149 | |
795dc4fc | 1150 | /* Use different register alloc ordering for Thumb. */ |
5a733826 BS |
1151 | #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () |
1152 | ||
1153 | /* Tell IRA to use the order we define rather than messing it up with its | |
1154 | own cost calculations. */ | |
1155 | #define HONOR_REG_ALLOC_ORDER | |
795dc4fc | 1156 | |
9338ffe6 PB |
1157 | /* Interrupt functions can only use registers that have already been |
1158 | saved by the prologue, even if they would normally be | |
1159 | call-clobbered. */ | |
1160 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1161 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
6fb5fa3c | 1162 | df_regs_ever_live_p (DST)) |
35d965d5 RS |
1163 | \f |
1164 | /* Register and constant classes. */ | |
1165 | ||
0be8bd1a | 1166 | /* Register classes. */ |
35d965d5 RS |
1167 | enum reg_class |
1168 | { | |
1169 | NO_REGS, | |
0be8bd1a RE |
1170 | LO_REGS, |
1171 | STACK_REG, | |
1172 | BASE_REGS, | |
1173 | HI_REGS, | |
9adcfa3c | 1174 | CALLER_SAVE_REGS, |
0be8bd1a RE |
1175 | GENERAL_REGS, |
1176 | CORE_REGS, | |
f1adb0a9 JB |
1177 | VFP_D0_D7_REGS, |
1178 | VFP_LO_REGS, | |
1179 | VFP_HI_REGS, | |
9b66ebb1 | 1180 | VFP_REGS, |
5a9335ef | 1181 | IWMMXT_REGS, |
0be8bd1a | 1182 | IWMMXT_GR_REGS, |
d5b7b3ae | 1183 | CC_REG, |
9b66ebb1 | 1184 | VFPCC_REG, |
0be8bd1a RE |
1185 | SFP_REG, |
1186 | AFP_REG, | |
35d965d5 RS |
1187 | ALL_REGS, |
1188 | LIM_REG_CLASSES | |
1189 | }; | |
1190 | ||
1191 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1192 | ||
d6b4baa4 | 1193 | /* Give names of register classes as strings for dump file. */ |
35d965d5 RS |
1194 | #define REG_CLASS_NAMES \ |
1195 | { \ | |
1196 | "NO_REGS", \ | |
0be8bd1a RE |
1197 | "LO_REGS", \ |
1198 | "STACK_REG", \ | |
1199 | "BASE_REGS", \ | |
1200 | "HI_REGS", \ | |
9adcfa3c | 1201 | "CALLER_SAVE_REGS", \ |
0be8bd1a RE |
1202 | "GENERAL_REGS", \ |
1203 | "CORE_REGS", \ | |
f1adb0a9 JB |
1204 | "VFP_D0_D7_REGS", \ |
1205 | "VFP_LO_REGS", \ | |
1206 | "VFP_HI_REGS", \ | |
9b66ebb1 | 1207 | "VFP_REGS", \ |
5a9335ef | 1208 | "IWMMXT_REGS", \ |
0be8bd1a | 1209 | "IWMMXT_GR_REGS", \ |
d5b7b3ae | 1210 | "CC_REG", \ |
5384443a | 1211 | "VFPCC_REG", \ |
9f4f1735 JJ |
1212 | "SFP_REG", \ |
1213 | "AFP_REG", \ | |
1214 | "ALL_REGS" \ | |
35d965d5 RS |
1215 | } |
1216 | ||
1217 | /* Define which registers fit in which classes. | |
1218 | This is an initializer for a vector of HARD_REG_SET | |
1219 | of length N_REG_CLASSES. */ | |
f1adb0a9 JB |
1220 | #define REG_CLASS_CONTENTS \ |
1221 | { \ | |
1222 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
f1adb0a9 JB |
1223 | { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ |
1224 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
1225 | { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
0be8bd1a | 1226 | { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ |
9adcfa3c | 1227 | { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ |
0be8bd1a RE |
1228 | { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
1229 | { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | |
1230 | { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
1231 | { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ | |
1232 | { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ | |
1233 | { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ | |
1234 | { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
1235 | { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ | |
1236 | { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ | |
1237 | { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ | |
1238 | { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ | |
1239 | { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ | |
d8484d41 | 1240 | { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ |
35d965d5 | 1241 | } |
4b02997f | 1242 | |
f1adb0a9 JB |
1243 | /* Any of the VFP register classes. */ |
1244 | #define IS_VFP_CLASS(X) \ | |
1245 | ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
1246 | || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
1247 | ||
35d965d5 RS |
1248 | /* The same information, inverted: |
1249 | Return the class number of the smallest class containing | |
1250 | reg number REGNO. This could be a conditional expression | |
1251 | or could index an array. */ | |
d5b7b3ae | 1252 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 | 1253 | |
0be8bd1a RE |
1254 | /* In VFPv1, VFP registers could only be accessed in the mode they |
1255 | were set, so subregs would be invalid there. However, we don't | |
1256 | support VFPv1 at the moment, and the restriction was lifted in | |
e81bf2ce JB |
1257 | VFPv2. |
1258 | In big-endian mode, modes greater than word size (i.e. DFmode) are stored in | |
1259 | VFP registers in little-endian order. We can't describe that accurately to | |
1260 | GCC, so avoid taking subregs of such values. */ | |
1261 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1262 | (TARGET_VFP && TARGET_BIG_END \ | |
1263 | && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ | |
1264 | || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ | |
1265 | && reg_classes_intersect_p (VFP_REGS, (CLASS))) | |
75d2580c | 1266 | |
35d965d5 | 1267 | /* The class value for index registers, and the one for base regs. */ |
5b3e6663 | 1268 | #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) |
f5c630c3 | 1269 | #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) |
d5b7b3ae | 1270 | |
b93a0fe6 | 1271 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1272 | when addressing quantities in QI or HI mode; if we don't know the |
888d2cd6 | 1273 | mode, then we must be conservative. */ |
3dcc68a4 | 1274 | #define MODE_BASE_REG_CLASS(MODE) \ |
9adc580c | 1275 | (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ |
888d2cd6 DJ |
1276 | (((MODE) == SImode) ? BASE_REGS : LO_REGS)) |
1277 | ||
1278 | /* For Thumb we can not support SP+reg addressing, so we return LO_REGS | |
1279 | instead of BASE_REGS. */ | |
1280 | #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
3dcc68a4 | 1281 | |
42db504c | 1282 | /* When this hook returns true for MODE, the compiler allows |
d5b7b3ae RE |
1283 | registers explicitly used in the rtl to be used as spill registers |
1284 | but prevents the compiler from extending the lifetime of these | |
d6b4baa4 | 1285 | registers. */ |
42db504c SB |
1286 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
1287 | arm_small_register_classes_for_mode_p | |
35d965d5 | 1288 | |
d5b7b3ae RE |
1289 | /* Must leave BASE_REGS reloads alone */ |
1290 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
78a14aa8 YR |
1291 | (lra_in_progress ? NO_REGS \ |
1292 | : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1293 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1294 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1295 | : NO_REGS)) \ | |
1296 | : NO_REGS)) | |
d5b7b3ae RE |
1297 | |
1298 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1fc017b6 VM |
1299 | (lra_in_progress ? NO_REGS \ |
1300 | : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1301 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1302 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1303 | : NO_REGS)) \ | |
1304 | : NO_REGS) | |
35d965d5 | 1305 | |
ff9940b0 RE |
1306 | /* Return the register class of a scratch register needed to copy IN into |
1307 | or out of a register in CLASS in MODE. If it can be done directly, | |
1308 | NO_REGS is returned. */ | |
d5b7b3ae | 1309 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1310 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1311 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1312 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1313 | ? coproc_secondary_reload_class (MODE, X, FALSE) \ |
1314 | : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
1315 | ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
5b3e6663 | 1316 | : TARGET_32BIT \ |
9b66ebb1 | 1317 | ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ |
d5b7b3ae RE |
1318 | ? GENERAL_REGS : NO_REGS) \ |
1319 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
f676971a | 1320 | |
d6b4baa4 | 1321 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1322 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1323 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1324 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1325 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1326 | ? coproc_secondary_reload_class (MODE, X, FALSE) : \ |
1327 | (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
1328 | coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
0be8bd1a RE |
1329 | (TARGET_32BIT ? \ |
1330 | (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ | |
1331 | && CONSTANT_P (X)) \ | |
9b6b54e2 | 1332 | ? GENERAL_REGS : \ |
0be8bd1a | 1333 | (((MODE) == HImode && ! arm_arch4 \ |
d435a4be KT |
1334 | && (MEM_P (X) \ |
1335 | || ((REG_P (X) || GET_CODE (X) == SUBREG) \ | |
0be8bd1a RE |
1336 | && true_regnum (X) == -1))) \ |
1337 | ? GENERAL_REGS : NO_REGS) \ | |
1338 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) | |
2ce9c1b9 | 1339 | |
6f734908 RE |
1340 | /* Try a machine-dependent way of reloading an illegitimate address |
1341 | operand. If we find one, push the reload and jump to WIN. This | |
1342 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1343 | ||
1344 | For the ARM, we wish to handle large displacements off a base | |
1345 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1346 | This can cut the number of reloads needed. */ |
1347 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1348 | do \ | |
1349 | { \ | |
0cd98787 JZ |
1350 | if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ |
1351 | goto WIN; \ | |
d5b7b3ae | 1352 | } \ |
62b10bbc | 1353 | while (0) |
6f734908 | 1354 | |
27847754 | 1355 | /* XXX If an HImode FP+large_offset address is converted to an HImode |
d5b7b3ae RE |
1356 | SP+large_offset address, then reload won't know how to fix it. It sees |
1357 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1358 | register, but the resulting address is still invalid because the offset | |
1359 | is too big. We fix it here instead by reloading the entire address. */ | |
1360 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1361 | cope with the variances between the Thumb's signed and unsigned byte and | |
1362 | halfword load instructions. */ | |
5b3e6663 | 1363 | /* ??? This should be safe for thumb2, but we may be able to do better. */ |
a132dad6 RE |
1364 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ |
1365 | do { \ | |
1366 | rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ | |
1367 | if (new_x) \ | |
1368 | { \ | |
1369 | X = new_x; \ | |
1370 | goto WIN; \ | |
1371 | } \ | |
1372 | } while (0) | |
d5b7b3ae RE |
1373 | |
1374 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1375 | if (TARGET_ARM) \ | |
1376 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1377 | else \ | |
1378 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
f676971a | 1379 | |
35d965d5 RS |
1380 | /* Return the maximum number of consecutive registers |
1381 | needed to represent mode MODE in a register of class CLASS. | |
0be8bd1a RE |
1382 | ARM regs are UNITS_PER_WORD bits. |
1383 | FIXME: Is this true for iWMMX? */ | |
35d965d5 | 1384 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
0be8bd1a | 1385 | (ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1386 | |
1387 | /* If defined, gives a class of registers that cannot be used as the | |
1388 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 RS |
1389 | \f |
1390 | /* Stack layout; function entry, exit and calling. */ | |
1391 | ||
1392 | /* Define this if pushing a word on the stack | |
1393 | makes the stack pointer a smaller address. */ | |
1394 | #define STACK_GROWS_DOWNWARD 1 | |
1395 | ||
a4d05547 | 1396 | /* Define this to nonzero if the nominal address of the stack frame |
35d965d5 RS |
1397 | is at the high-address end of the local variables; |
1398 | that is, each additional local variable allocated | |
1399 | goes at a more negative offset in the frame. */ | |
1400 | #define FRAME_GROWS_DOWNWARD 1 | |
1401 | ||
a2503645 RS |
1402 | /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). |
1403 | When present, it is one word in size, and sits at the top of the frame, | |
1404 | between the soft frame pointer and either r7 or r11. | |
1405 | ||
1406 | We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
1407 | and only then if some outgoing arguments are passed on the stack. It would | |
1408 | be tempting to also check whether the stack arguments are passed by indirect | |
1409 | calls, but there seems to be no reason in principle why a post-reload pass | |
1410 | couldn't convert a direct call into an indirect one. */ | |
1411 | #define CALLER_INTERWORKING_SLOT_SIZE \ | |
1412 | (TARGET_CALLER_INTERWORKING \ | |
38173d38 | 1413 | && crtl->outgoing_args_size != 0 \ |
a2503645 RS |
1414 | ? UNITS_PER_WORD : 0) |
1415 | ||
35d965d5 RS |
1416 | /* Offset within stack frame to start allocating local variables at. |
1417 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1418 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1419 | of the first local allocated. */ | |
1420 | #define STARTING_FRAME_OFFSET 0 | |
1421 | ||
1422 | /* If we generate an insn to push BYTES bytes, | |
1423 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae | 1424 | /* The push insns do not do this rounding implicitly. |
d6b4baa4 | 1425 | So don't define this. */ |
0c2ca901 | 1426 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1427 | |
1428 | /* Define this if the maximum size of all the outgoing args is to be | |
1429 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1430 | found in the variable crtl->outgoing_args_size. */ |
6cfc7210 | 1431 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1432 | |
1433 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1434 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 | 1435 | |
9f7bf991 RE |
1436 | /* Amount of memory needed for an untyped call to save all possible return |
1437 | registers. */ | |
1438 | #define APPLY_RESULT_SIZE arm_apply_result_size() | |
1439 | ||
11c1a207 RE |
1440 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return |
1441 | values must be in memory. On the ARM, they need only do so if larger | |
d6b4baa4 | 1442 | than a word, or if they contain elements offset from zero in the struct. */ |
11c1a207 RE |
1443 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
1444 | ||
6d3d9133 | 1445 | /* These bits describe the different types of function supported |
112cdef5 | 1446 | by the ARM backend. They are exclusive. i.e. a function cannot be both a |
6d3d9133 NC |
1447 | normal function and an interworked function, for example. Knowing the |
1448 | type of a function is important for determining its prologue and | |
1449 | epilogue sequences. | |
1450 | Note value 7 is currently unassigned. Also note that the interrupt | |
1451 | function types all have bit 2 set, so that they can be tested for easily. | |
1452 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1453 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1454 | default to unknown. This will force the first use of arm_current_func_type |
1455 | to call arm_compute_func_type. */ | |
1456 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1457 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1458 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
6d3d9133 NC |
1459 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ |
1460 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1461 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1462 | ||
1463 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1464 | ||
1465 | /* In addition functions can have several type modifiers, | |
1466 | outlined by these bit masks: */ | |
1467 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1468 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1469 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
d6b4baa4 | 1470 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ |
5b3e6663 | 1471 | #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ |
6d3d9133 NC |
1472 | |
1473 | /* Some macros to test these flags. */ | |
1474 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1475 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1476 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1477 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1478 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
5b3e6663 | 1479 | #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) |
6d3d9133 | 1480 | |
5848830f PB |
1481 | |
1482 | /* Structure used to hold the function stack frame layout. Offsets are | |
1483 | relative to the stack pointer on function entry. Positive offsets are | |
1484 | in the direction of stack growth. | |
1485 | Only soft_frame is used in thumb mode. */ | |
1486 | ||
d1b38208 | 1487 | typedef struct GTY(()) arm_stack_offsets |
5848830f PB |
1488 | { |
1489 | int saved_args; /* ARG_POINTER_REGNUM. */ | |
1490 | int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
1491 | int saved_regs; | |
1492 | int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
2591db65 | 1493 | int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ |
5848830f | 1494 | int outgoing_args; /* STACK_POINTER_REGNUM. */ |
954954d1 | 1495 | unsigned int saved_regs_mask; |
5848830f PB |
1496 | } |
1497 | arm_stack_offsets; | |
1498 | ||
906668bb | 1499 | #ifndef GENERATOR_FILE |
6d3d9133 NC |
1500 | /* A C structure for machine-specific, per-function data. |
1501 | This is added to the cfun structure. */ | |
d1b38208 | 1502 | typedef struct GTY(()) machine_function |
d5b7b3ae | 1503 | { |
6bc82793 | 1504 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1505 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1506 | /* Records if LR has to be saved for far jumps. */ |
1507 | int far_jump_used; | |
1508 | /* Records if ARG_POINTER was ever live. */ | |
1509 | int arg_pointer_live; | |
6f7ebcbb NC |
1510 | /* Records if the save of LR has been eliminated. */ |
1511 | int lr_save_eliminated; | |
0977774b | 1512 | /* The size of the stack frame. Only valid after reload. */ |
5848830f | 1513 | arm_stack_offsets stack_offsets; |
6d3d9133 NC |
1514 | /* Records the type of the current function. */ |
1515 | unsigned long func_type; | |
3cb66fd7 NC |
1516 | /* Record if the function has a variable argument list. */ |
1517 | int uses_anonymous_args; | |
5a9335ef NC |
1518 | /* Records if sibcalls are blocked because an argument |
1519 | register is needed to preserve stack alignment. */ | |
1520 | int sibcall_blocked; | |
020a4035 RE |
1521 | /* The PIC register for this function. This might be a pseudo. */ |
1522 | rtx pic_reg; | |
b12a00f1 | 1523 | /* Labels for per-function Thumb call-via stubs. One per potential calling |
57ecec57 PB |
1524 | register. We can never call via LR or PC. We can call via SP if a |
1525 | trampoline happens to be on the top of the stack. */ | |
1526 | rtx call_via[14]; | |
934c2060 RR |
1527 | /* Set to 1 when a return insn is output, this means that the epilogue |
1528 | is not needed. */ | |
1529 | int return_used_this_function; | |
906668bb BS |
1530 | /* When outputting Thumb-1 code, record the last insn that provides |
1531 | information about condition codes, and the comparison operands. */ | |
1532 | rtx thumb1_cc_insn; | |
1533 | rtx thumb1_cc_op0; | |
1534 | rtx thumb1_cc_op1; | |
1535 | /* Also record the CC mode that is supported. */ | |
1536 | enum machine_mode thumb1_cc_mode; | |
6d3d9133 NC |
1537 | } |
1538 | machine_function; | |
906668bb | 1539 | #endif |
d5b7b3ae | 1540 | |
b12a00f1 | 1541 | /* As in the machine_function, a global set of call-via labels, for code |
d6b5193b | 1542 | that is in text_section. */ |
57ecec57 | 1543 | extern GTY(()) rtx thumb_call_via_label[14]; |
b12a00f1 | 1544 | |
390b17c2 RE |
1545 | /* The number of potential ways of assigning to a co-processor. */ |
1546 | #define ARM_NUM_COPROC_SLOTS 1 | |
1547 | ||
1548 | /* Enumeration of procedure calling standard variants. We don't really | |
1549 | support all of these yet. */ | |
1550 | enum arm_pcs | |
1551 | { | |
1552 | ARM_PCS_AAPCS, /* Base standard AAPCS. */ | |
1553 | ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ | |
1554 | ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ | |
1555 | /* This must be the last AAPCS variant. */ | |
1556 | ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ | |
1557 | ARM_PCS_ATPCS, /* ATPCS. */ | |
1558 | ARM_PCS_APCS, /* APCS (legacy Linux etc). */ | |
1559 | ARM_PCS_UNKNOWN | |
1560 | }; | |
1561 | ||
12ffc7d5 CLT |
1562 | /* Default procedure calling standard of current compilation unit. */ |
1563 | extern enum arm_pcs arm_pcs_default; | |
1564 | ||
82e9d970 | 1565 | /* A C type for declaring a variable that is used as the first argument of |
390b17c2 | 1566 | `FUNCTION_ARG' and other related values. */ |
82e9d970 PB |
1567 | typedef struct |
1568 | { | |
d5b7b3ae | 1569 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1570 | int nregs; |
5a9335ef NC |
1571 | /* This is the number of iWMMXt register arguments scanned so far. */ |
1572 | int iwmmxt_nregs; | |
1573 | int named_count; | |
1574 | int nargs; | |
390b17c2 RE |
1575 | /* Which procedure call variant to use for this call. */ |
1576 | enum arm_pcs pcs_variant; | |
1577 | ||
1578 | /* AAPCS related state tracking. */ | |
1579 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
1580 | int aapcs_cprc_slot; /* Index of co-processor rules to handle | |
1581 | this argument, or -1 if using core | |
1582 | registers. */ | |
1583 | int aapcs_ncrn; | |
1584 | int aapcs_next_ncrn; | |
1585 | rtx aapcs_reg; /* Register assigned to this argument. */ | |
1586 | int aapcs_partial; /* How many bytes are passed in regs (if | |
1587 | split between core regs and stack. | |
1588 | Zero otherwise. */ | |
1589 | int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; | |
1590 | int can_split; /* Argument can be split between core regs | |
1591 | and the stack. */ | |
1592 | /* Private data for tracking VFP register allocation */ | |
1593 | unsigned aapcs_vfp_regs_free; | |
1594 | unsigned aapcs_vfp_reg_alloc; | |
1595 | int aapcs_vfp_rcount; | |
46107b99 | 1596 | MACHMODE aapcs_vfp_rmode; |
d5b7b3ae | 1597 | } CUMULATIVE_ARGS; |
82e9d970 | 1598 | |
866af8a9 JB |
1599 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1600 | (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
1601 | ||
1602 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
1603 | (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
1604 | ||
1605 | /* For AAPCS, padding should never be below the argument. For other ABIs, | |
1606 | * mimic the default. */ | |
1607 | #define PAD_VARARGS_DOWN \ | |
1608 | ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
1609 | ||
35d965d5 RS |
1610 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1611 | for a call to a function whose data type is FNTYPE. | |
1612 | For a library call, FNTYPE is 0. | |
1613 | On the ARM, the offset starts at 0. */ | |
0f6937fe | 1614 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1615 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
35d965d5 | 1616 | |
35d965d5 RS |
1617 | /* 1 if N is a possible register number for function argument passing. |
1618 | On the ARM, r0-r3 are used to pass args. */ | |
390b17c2 RE |
1619 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
1620 | (IN_RANGE ((REGNO), 0, 3) \ | |
1621 | || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ | |
1622 | && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ | |
1623 | || (TARGET_IWMMXT_ABI \ | |
5848830f | 1624 | && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
35d965d5 | 1625 | |
f99fce0c | 1626 | \f |
afef3d7a | 1627 | /* If your target environment doesn't prefix user functions with an |
96a3900d | 1628 | underscore, you may wish to re-define this to prevent any conflicts. */ |
afef3d7a NC |
1629 | #ifndef ARM_MCOUNT_NAME |
1630 | #define ARM_MCOUNT_NAME "*mcount" | |
1631 | #endif | |
1632 | ||
1633 | /* Call the function profiler with a given profile label. The Acorn | |
1634 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1635 | On the ARM the full profile code will look like: | |
1636 | .data | |
1637 | LP1 | |
1638 | .word 0 | |
1639 | .text | |
1640 | mov ip, lr | |
1641 | bl mcount | |
1642 | .word LP1 | |
1643 | ||
1644 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1645 | will output the .text section. | |
1646 | ||
1647 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1648 | ``prof'' doesn't seem to mind about this! |
1649 | ||
1650 | Note - this version of the code is designed to work in both ARM and | |
1651 | Thumb modes. */ | |
be393ecf | 1652 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1653 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1654 | { \ |
1655 | char temp[20]; \ | |
1656 | rtx sym; \ | |
1657 | \ | |
dd18ae56 | 1658 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1659 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1660 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1661 | fputc ('\n', STREAM); \ | |
1662 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
f1c25d3b | 1663 | sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ |
301d03af | 1664 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1665 | } |
be393ecf | 1666 | #endif |
35d965d5 | 1667 | |
59be6073 | 1668 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1669 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1670 | if (TARGET_ARM) \ | |
1671 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1672 | else \ | |
1673 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1674 | #else |
1675 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1676 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1677 | #endif | |
d5b7b3ae | 1678 | |
35d965d5 RS |
1679 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1680 | the stack pointer does not matter. The value is tested only in | |
1681 | functions that have frame pointers. | |
1682 | No definition is equivalent to always zero. | |
1683 | ||
1684 | On the ARM, the function epilogue recovers the stack pointer from the | |
1685 | frame. */ | |
1686 | #define EXIT_IGNORE_STACK 1 | |
1687 | ||
2b261262 | 1688 | #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) |
c7861455 | 1689 | |
35d965d5 RS |
1690 | /* Determine if the epilogue should be output as RTL. |
1691 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae | 1692 | #define USE_RETURN_INSN(ISCOND) \ |
7c19c715 | 1693 | (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) |
ff9940b0 RE |
1694 | |
1695 | /* Definitions for register eliminations. | |
1696 | ||
1697 | This is an array of structures. Each structure initializes one pair | |
1698 | of eliminable registers. The "from" register number is given first, | |
1699 | followed by "to". Eliminations of the same "from" register are listed | |
1700 | in order of preference. | |
1701 | ||
1702 | We have two registers that can be eliminated on the ARM. First, the | |
1703 | arg pointer register can often be eliminated in favor of the stack | |
1704 | pointer register. Secondly, the pseudo frame pointer register can always | |
1705 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1706 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1707 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1708 | |
d5b7b3ae RE |
1709 | #define ELIMINABLE_REGS \ |
1710 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1711 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1712 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1713 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1714 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1715 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1716 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1717 | |
d5b7b3ae RE |
1718 | /* Define the offset between two registers, one to be eliminated, and the |
1719 | other its replacement, at the start of a routine. */ | |
d5b7b3ae RE |
1720 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1721 | if (TARGET_ARM) \ | |
5848830f | 1722 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
d5b7b3ae | 1723 | else \ |
5848830f PB |
1724 | (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) |
1725 | ||
d5b7b3ae RE |
1726 | /* Special case handling of the location of arguments passed on the stack. */ |
1727 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
f676971a | 1728 | |
d5b7b3ae RE |
1729 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1730 | once for every function before code is generated. */ | |
1731 | #define INIT_EXPANDERS arm_init_expanders () | |
1732 | ||
35d965d5 | 1733 | /* Length in units of the trampoline for entering a nested function. */ |
5b3e6663 | 1734 | #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) |
35d965d5 | 1735 | |
006946e4 JM |
1736 | /* Alignment required for a trampoline in bits. */ |
1737 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1738 | \f |
1739 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 | 1740 | #define HAVE_POST_INCREMENT 1 |
5b3e6663 PB |
1741 | #define HAVE_PRE_INCREMENT TARGET_32BIT |
1742 | #define HAVE_POST_DECREMENT TARGET_32BIT | |
1743 | #define HAVE_PRE_DECREMENT TARGET_32BIT | |
1744 | #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
1745 | #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
1746 | #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
1747 | #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
35d965d5 | 1748 | |
8875e939 RR |
1749 | enum arm_auto_incmodes |
1750 | { | |
1751 | ARM_POST_INC, | |
1752 | ARM_PRE_INC, | |
1753 | ARM_POST_DEC, | |
1754 | ARM_PRE_DEC | |
1755 | }; | |
1756 | ||
1757 | #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ | |
1758 | (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) | |
1759 | #define USE_LOAD_POST_INCREMENT(mode) \ | |
1760 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) | |
1761 | #define USE_LOAD_PRE_INCREMENT(mode) \ | |
1762 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) | |
1763 | #define USE_LOAD_POST_DECREMENT(mode) \ | |
1764 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) | |
1765 | #define USE_LOAD_PRE_DECREMENT(mode) \ | |
1766 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) | |
1767 | ||
1768 | #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) | |
1769 | #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) | |
1770 | #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) | |
1771 | #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) | |
1772 | ||
35d965d5 RS |
1773 | /* Macros to check register numbers against specific register classes. */ |
1774 | ||
1775 | /* These assume that REGNO is a hard or pseudo reg number. | |
1776 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1777 | or a pseudo reg currently allocated to a suitable hard reg. | |
1778 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1779 | has been allocated, which happens in reginfo.c during register |
1780 | allocation. */ | |
d5b7b3ae RE |
1781 | #define TEST_REGNO(R, TEST, VALUE) \ |
1782 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1783 | ||
5b3e6663 | 1784 | /* Don't allow the pc to be used. */ |
f1008e52 RE |
1785 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1786 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1787 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1788 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1789 | ||
5b3e6663 | 1790 | #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
f1008e52 RE |
1791 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ |
1792 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1793 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1794 | ||
1795 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
5b3e6663 PB |
1796 | (TARGET_THUMB1 \ |
1797 | ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
f1008e52 RE |
1798 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) |
1799 | ||
888d2cd6 DJ |
1800 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
1801 | For Thumb, we can not use SP + reg, so reject SP. */ | |
1802 | #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
f5c630c3 | 1803 | REGNO_MODE_OK_FOR_BASE_P (X, QImode) |
888d2cd6 | 1804 | |
f1008e52 RE |
1805 | /* For ARM code, we don't care about the mode, but for Thumb, the index |
1806 | must be suitable for use in a QImode load. */ | |
d5b7b3ae | 1807 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
f5c630c3 PB |
1808 | (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ |
1809 | && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
35d965d5 RS |
1810 | |
1811 | /* Maximum number of registers that can appear in a valid memory address. | |
d6b4baa4 | 1812 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1813 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1814 | |
1815 | /* Recognize any constant value that is a valid address. */ | |
1816 | /* XXX We can address any constant, eventually... */ | |
5b3e6663 | 1817 | /* ??? Should the TARGET_ARM here also apply to thumb2? */ |
008cf58a RE |
1818 | #define CONSTANT_ADDRESS_P(X) \ |
1819 | (GET_CODE (X) == SYMBOL_REF \ | |
1820 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1821 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1822 | |
8426b956 RS |
1823 | /* True if SYMBOL + OFFSET constants must refer to something within |
1824 | SYMBOL's section. */ | |
1825 | #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
1826 | ||
571191af PB |
1827 | /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ |
1828 | #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
1829 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
1830 | #endif | |
1831 | ||
c27ba912 DM |
1832 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS |
1833 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1834 | #endif | |
1835 | ||
6bc82793 | 1836 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1837 | Each case label should return the number of characters to |
1838 | be stripped from the start of a function's name, if that | |
1839 | name starts with the indicated character. */ | |
1840 | #define ARM_NAME_ENCODING_LENGTHS \ | |
00fdafef | 1841 | case '*': return 1; \ |
f676971a | 1842 | SUBTARGET_NAME_ENCODING_LENGTHS |
c27ba912 | 1843 | |
c27ba912 DM |
1844 | /* This is how to output a reference to a user-level label named NAME. |
1845 | `assemble_name' uses this. */ | |
e5951263 | 1846 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1847 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1848 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1849 | |
7a085dce | 1850 | /* Output IT instructions for conditionally executed Thumb-2 instructions. */ |
5b3e6663 PB |
1851 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ |
1852 | if (TARGET_THUMB2) \ | |
1853 | thumb2_asm_output_opcode (STREAM); | |
1854 | ||
7abc66b1 JB |
1855 | /* The EABI specifies that constructors should go in .init_array. |
1856 | Other targets use .ctors for compatibility. */ | |
88c6057f | 1857 | #ifndef ARM_EABI_CTORS_SECTION_OP |
7abc66b1 JB |
1858 | #define ARM_EABI_CTORS_SECTION_OP \ |
1859 | "\t.section\t.init_array,\"aw\",%init_array" | |
88c6057f MM |
1860 | #endif |
1861 | #ifndef ARM_EABI_DTORS_SECTION_OP | |
7abc66b1 JB |
1862 | #define ARM_EABI_DTORS_SECTION_OP \ |
1863 | "\t.section\t.fini_array,\"aw\",%fini_array" | |
88c6057f | 1864 | #endif |
7abc66b1 JB |
1865 | #define ARM_CTORS_SECTION_OP \ |
1866 | "\t.section\t.ctors,\"aw\",%progbits" | |
1867 | #define ARM_DTORS_SECTION_OP \ | |
1868 | "\t.section\t.dtors,\"aw\",%progbits" | |
1869 | ||
1870 | /* Define CTORS_SECTION_ASM_OP. */ | |
1871 | #undef CTORS_SECTION_ASM_OP | |
1872 | #undef DTORS_SECTION_ASM_OP | |
1873 | #ifndef IN_LIBGCC2 | |
1874 | # define CTORS_SECTION_ASM_OP \ | |
1875 | (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
1876 | # define DTORS_SECTION_ASM_OP \ | |
1877 | (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
1878 | #else /* !defined (IN_LIBGCC2) */ | |
1879 | /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
1880 | so we cannot use the definition above. */ | |
1881 | # ifdef __ARM_EABI__ | |
1882 | /* The .ctors section is not part of the EABI, so we do not define | |
1883 | CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
1884 | from trying to use it. We do define it when doing normal | |
1885 | compilation, as .init_array can be used instead of .ctors. */ | |
1886 | /* There is no need to emit begin or end markers when using | |
1887 | init_array; the dynamic linker will compute the size of the | |
1888 | array itself based on special symbols created by the static | |
1889 | linker. However, we do need to arrange to set up | |
1890 | exception-handling here. */ | |
1891 | # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
1892 | # define CTOR_LIST_END /* empty */ | |
1893 | # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
1894 | # define DTOR_LIST_END /* empty */ | |
1895 | # else /* !defined (__ARM_EABI__) */ | |
1896 | # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
1897 | # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
1898 | # endif /* !defined (__ARM_EABI__) */ | |
1899 | #endif /* !defined (IN_LIBCC2) */ | |
1900 | ||
1e731102 MM |
1901 | /* True if the operating system can merge entities with vague linkage |
1902 | (e.g., symbols in COMDAT group) during dynamic linking. */ | |
1903 | #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
1904 | #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
1905 | #endif | |
1906 | ||
617a1b71 PB |
1907 | #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) |
1908 | ||
35d965d5 RS |
1909 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1910 | and check its validity for a certain class. | |
1911 | We have two alternate definitions for each of them. | |
1912 | The usual definition accepts all pseudo regs; the other rejects | |
1913 | them unless they have been allocated suitable hard regs. | |
5b3e6663 | 1914 | The symbol REG_OK_STRICT causes the latter definition to be used. |
7a085dce | 1915 | Thumb-2 has the same restrictions as arm. */ |
35d965d5 | 1916 | #ifndef REG_OK_STRICT |
ff9940b0 | 1917 | |
f1008e52 RE |
1918 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1919 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1920 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1921 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1922 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1923 | |
f5c630c3 PB |
1924 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1925 | ((REGNO (X) <= LAST_ARM_REGNUM \ | |
1926 | && REGNO (X) != STACK_POINTER_REGNUM) \ | |
1927 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1928 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1929 | || REGNO (X) == ARG_POINTER_REGNUM) | |
1930 | ||
5b3e6663 | 1931 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
f1008e52 RE |
1932 | (REGNO (X) <= LAST_LO_REGNUM \ |
1933 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1934 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1935 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1936 | || (X) == hard_frame_pointer_rtx \ | |
1937 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1938 | |
76a318e9 RE |
1939 | #define REG_STRICT_P 0 |
1940 | ||
d5b7b3ae | 1941 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1942 | |
f1008e52 RE |
1943 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1944 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1945 | |
f5c630c3 PB |
1946 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1947 | ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1948 | ||
5b3e6663 PB |
1949 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1950 | THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 1951 | |
76a318e9 RE |
1952 | #define REG_STRICT_P 1 |
1953 | ||
d5b7b3ae | 1954 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
1955 | |
1956 | /* Now define some helpers in terms of the above. */ | |
1957 | ||
1958 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
5b3e6663 PB |
1959 | (TARGET_THUMB1 \ |
1960 | ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
f1008e52 RE |
1961 | : ARM_REG_OK_FOR_BASE_P (X)) |
1962 | ||
5b3e6663 | 1963 | /* For 16-bit Thumb, a valid index register is anything that can be used in |
f1008e52 | 1964 | a byte load instruction. */ |
5b3e6663 PB |
1965 | #define THUMB1_REG_OK_FOR_INDEX_P(X) \ |
1966 | THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
f1008e52 RE |
1967 | |
1968 | /* Nonzero if X is a hard reg that can be used as an index | |
1969 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
1970 | is not suitable. */ | |
1971 | #define REG_OK_FOR_INDEX_P(X) \ | |
5b3e6663 PB |
1972 | (TARGET_THUMB1 \ |
1973 | ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
f1008e52 RE |
1974 | : ARM_REG_OK_FOR_INDEX_P (X)) |
1975 | ||
888d2cd6 DJ |
1976 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
1977 | For Thumb, we can not use SP + reg, so reject SP. */ | |
1978 | #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
1979 | REG_OK_FOR_INDEX_P (X) | |
35d965d5 | 1980 | \f |
f1008e52 | 1981 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
d435a4be | 1982 | (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) |
35d965d5 | 1983 | |
f1008e52 | 1984 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
d435a4be | 1985 | (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) |
35d965d5 | 1986 | \f |
35d965d5 RS |
1987 | /* Specify the machine mode that this machine uses |
1988 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 1989 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 1990 | |
907dd0c7 | 1991 | #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ |
83c3a2d8 | 1992 | || (TARGET_THUMB1 \ |
907dd0c7 RE |
1993 | && (optimize_size || flag_pic))) |
1994 | ||
1995 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
83c3a2d8 | 1996 | (TARGET_THUMB1 \ |
907dd0c7 RE |
1997 | ? (min >= 0 && max < 512 \ |
1998 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ | |
1999 | : min >= -256 && max < 256 \ | |
2000 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ | |
2001 | : min >= 0 && max < 8192 \ | |
2002 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ | |
2003 | : min >= -4096 && max < 4096 \ | |
2004 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ | |
2005 | : SImode) \ | |
10c241af | 2006 | : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ |
907dd0c7 RE |
2007 | : (max >= 0x200) ? HImode \ |
2008 | : QImode)) | |
5b3e6663 | 2009 | |
ff9940b0 RE |
2010 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2011 | unsigned is probably best, but may break some code. */ | |
2012 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2013 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2014 | #endif |
2015 | ||
35d965d5 | 2016 | /* Max number of bytes we can move from memory to memory |
d17ce9af TG |
2017 | in one reasonably fast instruction. */ |
2018 | #define MOVE_MAX 4 | |
35d965d5 | 2019 | |
d19fb8e3 | 2020 | #undef MOVE_RATIO |
e04ad03d | 2021 | #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) |
d19fb8e3 | 2022 | |
ff9940b0 RE |
2023 | /* Define if operations between registers always perform the operation |
2024 | on the full register even if a narrower mode is specified. */ | |
2025 | #define WORD_REGISTER_OPERATIONS | |
2026 | ||
2027 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2028 | will either zero-extend or sign-extend. The value of this macro should | |
2029 | be the code that says which one of the two operations is implicitly | |
f822d252 | 2030 | done, UNKNOWN if none. */ |
9c872872 | 2031 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2032 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2033 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
f822d252 | 2034 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) |
ff9940b0 | 2035 | |
35d965d5 RS |
2036 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2037 | #define SLOW_BYTE_ACCESS 0 | |
2038 | ||
d5b7b3ae | 2039 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
f676971a | 2040 | |
35d965d5 RS |
2041 | /* Immediate shift counts are truncated by the output routines (or was it |
2042 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2043 | that the native compiler puts too large (> 32) immediate shift counts | |
2044 | into a register and shifts by the register, letting the ARM decide what | |
2045 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2046 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2047 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2048 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
d6b4baa4 | 2049 | rotates is modulo 32 used. */ |
ff9940b0 | 2050 | /* #define SHIFT_COUNT_TRUNCATED 1 */ |
35d965d5 | 2051 | |
35d965d5 | 2052 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2053 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2054 | |
2055 | /* Calling from registers is a massive pain. */ | |
2056 | #define NO_FUNCTION_CSE 1 | |
2057 | ||
35d965d5 RS |
2058 | /* The machine modes of pointers and functions */ |
2059 | #define Pmode SImode | |
2060 | #define FUNCTION_MODE Pmode | |
2061 | ||
d5b7b3ae RE |
2062 | #define ARM_FRAME_RTX(X) \ |
2063 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2064 | || (X) == arg_pointer_rtx) |
2065 | ||
ff9940b0 | 2066 | /* Try to generate sequences that don't involve branches, we can then use |
a51fb17f | 2067 | conditional instructions. */ |
3a4fd356 | 2068 | #define BRANCH_COST(speed_p, predictable_p) \ |
153668ec JB |
2069 | (current_tune->branch_cost (speed_p, predictable_p)) |
2070 | ||
a51fb17f BC |
2071 | /* False if short circuit operation is preferred. */ |
2072 | #define LOGICAL_OP_NON_SHORT_CIRCUIT \ | |
2073 | ((optimize_size) \ | |
2074 | ? (TARGET_THUMB ? false : true) \ | |
2075 | : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) | |
2076 | ||
7a801826 RE |
2077 | \f |
2078 | /* Position Independent Code. */ | |
2079 | /* We decide which register to use based on the compilation options and | |
2080 | the assembler in use; this is more general than the APCS restriction of | |
2081 | using sb (r9) all the time. */ | |
020a4035 | 2082 | extern unsigned arm_pic_register; |
7a801826 RE |
2083 | |
2084 | /* The register number of the register used to address a table of static | |
2085 | data addresses in memory. */ | |
2086 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2087 | ||
f5a1b0d2 | 2088 | /* We can't directly access anything that contains a symbol, |
d3585b76 DJ |
2089 | nor can we indirect via the constant pool. One exception is |
2090 | UNSPEC_TLS, which is always PIC. */ | |
82e9d970 | 2091 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2092 | (!(symbol_mentioned_p (X) \ |
2093 | || label_mentioned_p (X) \ | |
2094 | || (GET_CODE (X) == SYMBOL_REF \ | |
2095 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2096 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
d3585b76 DJ |
2097 | || label_mentioned_p (get_pool_constant (X))))) \ |
2098 | || tls_mentioned_p (X)) | |
1575c31e | 2099 | |
13bd191d PB |
2100 | /* We need to know when we are making a constant pool; this determines |
2101 | whether data needs to be in the GOT or can be referenced via a GOT | |
2102 | offset. */ | |
2103 | extern int making_const_table; | |
82e9d970 | 2104 | \f |
c27ba912 | 2105 | /* Handle pragmas for compatibility with Intel's compilers. */ |
b76c3c4b | 2106 | /* Also abuse this to register additional C specific EABI attributes. */ |
c58b209a NB |
2107 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2108 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
2109 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
2110 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
b76c3c4b | 2111 | arm_lang_object_attributes_init(); \ |
8b97c5f8 ZW |
2112 | } while (0) |
2113 | ||
d6b4baa4 | 2114 | /* Condition code information. */ |
ff9940b0 | 2115 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
a5381466 | 2116 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2117 | |
2118 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2119 | |
880873be RE |
2120 | #define REVERSIBLE_CC_MODE(MODE) 1 |
2121 | ||
2122 | #define REVERSE_CONDITION(CODE,MODE) \ | |
2123 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
2124 | ? reverse_condition_maybe_unordered (code) \ | |
2125 | : reverse_condition (code)) | |
008cf58a | 2126 | |
7dba8395 RH |
2127 | /* The arm5 clz instruction returns 32. */ |
2128 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
ca96ed43 | 2129 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
35d965d5 | 2130 | \f |
906668bb BS |
2131 | #define CC_STATUS_INIT \ |
2132 | do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) | |
2133 | ||
d5b7b3ae | 2134 | #undef ASM_APP_OFF |
5b3e6663 PB |
2135 | #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ |
2136 | TARGET_THUMB2 ? "\t.thumb\n" : "") | |
35d965d5 | 2137 | |
2ee67fbb JB |
2138 | /* Output a push or a pop instruction (only used when profiling). |
2139 | We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know | |
2140 | that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and | |
2141 | that r7 isn't used by the function profiler, so we can use it as a | |
2142 | scratch reg. WARNING: This isn't safe in the general case! It may be | |
2143 | sensitive to future changes in final.c:profile_function. */ | |
d5b7b3ae | 2144 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
8a81cc45 RE |
2145 | do \ |
2146 | { \ | |
2147 | if (TARGET_ARM) \ | |
2148 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2149 | STACK_POINTER_REGNUM, REGNO); \ | |
2ee67fbb JB |
2150 | else if (TARGET_THUMB1 \ |
2151 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2152 | { \ | |
2153 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2154 | asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ | |
2155 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2156 | } \ | |
8a81cc45 RE |
2157 | else \ |
2158 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
2159 | } while (0) | |
d5b7b3ae RE |
2160 | |
2161 | ||
2ee67fbb | 2162 | /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ |
d5b7b3ae | 2163 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
8a81cc45 RE |
2164 | do \ |
2165 | { \ | |
2166 | if (TARGET_ARM) \ | |
2167 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2168 | STACK_POINTER_REGNUM, REGNO); \ | |
2ee67fbb JB |
2169 | else if (TARGET_THUMB1 \ |
2170 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2171 | { \ | |
2172 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2173 | asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ | |
2174 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2175 | } \ | |
8a81cc45 RE |
2176 | else \ |
2177 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
2178 | } while (0) | |
d5b7b3ae | 2179 | |
b0fe107e JM |
2180 | #define ADDR_VEC_ALIGN(JUMPTABLE) \ |
2181 | ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) | |
2182 | ||
2183 | /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the | |
2184 | default alignment from elfos.h. */ | |
2185 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
2186 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ | |
5b3e6663 PB |
2187 | |
2188 | /* Make sure subsequent insns are aligned after a TBB. */ | |
2189 | #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
2190 | do \ | |
2191 | { \ | |
2192 | if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ | |
2193 | ASM_OUTPUT_ALIGN (FILE, 1); \ | |
2194 | } \ | |
d5b7b3ae | 2195 | while (0) |
35d965d5 | 2196 | |
6cfc7210 NC |
2197 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2198 | do \ | |
2199 | { \ | |
d5b7b3ae RE |
2200 | if (TARGET_THUMB) \ |
2201 | { \ | |
5b3e6663 | 2202 | if (is_called_in_ARM_mode (DECL) \ |
bf98ec6c | 2203 | || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ |
3c072c6b | 2204 | && cfun->is_thunk)) \ |
d5b7b3ae | 2205 | fprintf (STREAM, "\t.code 32\n") ; \ |
5b3e6663 PB |
2206 | else if (TARGET_THUMB1) \ |
2207 | fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ | |
d5b7b3ae | 2208 | else \ |
5b3e6663 | 2209 | fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ |
d5b7b3ae | 2210 | } \ |
6cfc7210 | 2211 | if (TARGET_POKE_FUNCTION_NAME) \ |
586de218 | 2212 | arm_poke_function_name (STREAM, (const char *) NAME); \ |
6cfc7210 NC |
2213 | } \ |
2214 | while (0) | |
35d965d5 | 2215 | |
d5b7b3ae RE |
2216 | /* For aliases of functions we use .thumb_set instead. */ |
2217 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2218 | do \ | |
2219 | { \ | |
91ea4f8d KG |
2220 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2221 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2222 | \ |
2223 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2224 | { \ | |
2225 | fprintf (FILE, "\t.thumb_set "); \ | |
2226 | assemble_name (FILE, LABEL1); \ | |
2227 | fprintf (FILE, ","); \ | |
2228 | assemble_name (FILE, LABEL2); \ | |
2229 | fprintf (FILE, "\n"); \ | |
2230 | } \ | |
2231 | else \ | |
2232 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2233 | } \ | |
2234 | while (0) | |
2235 | ||
fdc2d3b0 NC |
2236 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2237 | /* To support -falign-* switches we need to use .p2align so | |
2238 | that alignment directives in code sections will be padded | |
2239 | with no-op instructions, rather than zeroes. */ | |
5a9335ef | 2240 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ |
fdc2d3b0 NC |
2241 | if ((LOG) != 0) \ |
2242 | { \ | |
2243 | if ((MAX_SKIP) == 0) \ | |
5a9335ef | 2244 | fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ |
fdc2d3b0 NC |
2245 | else \ |
2246 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
5a9335ef | 2247 | (int) (LOG), (int) (MAX_SKIP)); \ |
fdc2d3b0 NC |
2248 | } |
2249 | #endif | |
35d965d5 | 2250 | \f |
5b3e6663 PB |
2251 | /* Add two bytes to the length of conditionally executed Thumb-2 |
2252 | instructions for the IT instruction. */ | |
2253 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
2254 | if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
2255 | length += 2; | |
2256 | ||
35d965d5 | 2257 | /* Only perform branch elimination (by making instructions conditional) if |
5b3e6663 PB |
2258 | we're optimizing. For Thumb-2 check if any IT instructions need |
2259 | outputting. */ | |
d5b7b3ae RE |
2260 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2261 | if (TARGET_ARM && optimize) \ | |
2262 | arm_final_prescan_insn (INSN); \ | |
5b3e6663 PB |
2263 | else if (TARGET_THUMB2) \ |
2264 | thumb2_final_prescan_insn (INSN); \ | |
2265 | else if (TARGET_THUMB1) \ | |
2266 | thumb1_final_prescan_insn (INSN) | |
35d965d5 | 2267 | |
7b8b8ade NC |
2268 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2269 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2270 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2271 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2272 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2273 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2274 | : 0)))) |
35d965d5 | 2275 | |
6a5d7526 MS |
2276 | /* A C expression whose value is RTL representing the value of the return |
2277 | address for the frame COUNT steps up from the current frame. */ | |
2278 | ||
d5b7b3ae RE |
2279 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2280 | arm_return_addr (COUNT, FRAME) | |
2281 | ||
f676971a | 2282 | /* Mask of the bits in the PC that contain the real return address |
d5b7b3ae RE |
2283 | when running in 26-bit mode. */ |
2284 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2285 | |
2c849145 JM |
2286 | /* Pick up the return address upon entry to a procedure. Used for |
2287 | dwarf2 unwind information. This also enables the table driven | |
2288 | mechanism. */ | |
2c849145 JM |
2289 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2290 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2291 | ||
39950dff MS |
2292 | /* Used to mask out junk bits from the return address, such as |
2293 | processor state, interrupt status, condition codes and the like. */ | |
2294 | #define MASK_RETURN_ADDR \ | |
2295 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2296 | in 26 bit mode, the condition codes must be masked out of the \ | |
2297 | return address. This does not apply to ARM6 and later processors \ | |
2298 | when running in 32 bit mode. */ \ | |
61f0ccff RE |
2299 | ((arm_arch4 || TARGET_THUMB) \ |
2300 | ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
fcd53748 | 2301 | : arm_gen_return_addr_mask ()) |
d5b7b3ae RE |
2302 | |
2303 | \f | |
978e411f CD |
2304 | /* Do not emit .note.GNU-stack by default. */ |
2305 | #ifndef NEED_INDICATE_EXEC_STACK | |
2306 | #define NEED_INDICATE_EXEC_STACK 0 | |
2307 | #endif | |
2308 | ||
9e94a7fc MGD |
2309 | #define TARGET_ARM_ARCH \ |
2310 | (arm_base_arch) \ | |
2311 | ||
2312 | #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) | |
2313 | #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) | |
2314 | ||
2315 | /* The highest Thumb instruction set version supported by the chip. */ | |
2316 | #define TARGET_ARM_ARCH_ISA_THUMB \ | |
2317 | (arm_arch_thumb2 ? 2 \ | |
2318 | : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) | |
2319 | ||
2320 | /* Expands to an upper-case char of the target's architectural | |
2321 | profile. */ | |
2322 | #define TARGET_ARM_ARCH_PROFILE \ | |
2323 | (!arm_arch_notm \ | |
2324 | ? 'M' \ | |
2325 | : (arm_arch7 \ | |
2326 | ? (strlen (arm_arch_name) >=3 \ | |
2327 | ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ | |
2328 | : 0) \ | |
2329 | : 0)) | |
2330 | ||
2331 | /* Bit-field indicating what size LDREX/STREX loads/stores are available. | |
2332 | Bit 0 for bytes, up to bit 3 for double-words. */ | |
2333 | #define TARGET_ARM_FEATURE_LDREX \ | |
2334 | ((TARGET_HAVE_LDREX ? 4 : 0) \ | |
2335 | | (TARGET_HAVE_LDREXBH ? 3 : 0) \ | |
2336 | | (TARGET_HAVE_LDREXD ? 8 : 0)) | |
2337 | ||
2338 | /* Set as a bit mask indicating the available widths of hardware floating | |
2339 | point types. Where bit 1 indicates 16-bit support, bit 2 indicates | |
2340 | 32-bit support, bit 3 indicates 64-bit support. */ | |
2341 | #define TARGET_ARM_FP \ | |
2342 | (TARGET_VFP_SINGLE ? 4 \ | |
2343 | : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) | |
2344 | ||
2345 | ||
2346 | /* Set as a bit mask indicating the available widths of floating point | |
2347 | types for hardware NEON floating point. This is the same as | |
2348 | TARGET_ARM_FP without the 64-bit bit set. */ | |
2349 | #ifdef TARGET_NEON | |
2350 | #define TARGET_NEON_FP \ | |
2351 | (TARGET_ARM_FP & (0xff ^ 0x08)) | |
2352 | #endif | |
2353 | ||
93b338c3 BS |
2354 | /* The maximum number of parallel loads or stores we support in an ldm/stm |
2355 | instruction. */ | |
2356 | #define MAX_LDM_STM_OPS 4 | |
2357 | ||
b848e289 JG |
2358 | #define BIG_LITTLE_SPEC \ |
2359 | " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" \ | |
2360 | ||
2361 | extern const char *arm_rewrite_mcpu (int argc, const char **argv); | |
2362 | #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ | |
2363 | { "rewrite_mcpu", arm_rewrite_mcpu }, | |
2364 | ||
54e73f88 AS |
2365 | #define ASM_CPU_SPEC \ |
2366 | " %{mcpu=generic-*:-march=%*;" \ | |
b848e289 JG |
2367 | " :%{march=*:-march=%*}}" \ |
2368 | BIG_LITTLE_SPEC | |
54e73f88 | 2369 | |
33aa08b3 AS |
2370 | /* -mcpu=native handling only makes sense with compiler running on |
2371 | an ARM chip. */ | |
2372 | #if defined(__arm__) | |
2373 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
2374 | # define EXTRA_SPEC_FUNCTIONS \ | |
b848e289 JG |
2375 | { "local_cpu_detect", host_detect_local_cpu }, \ |
2376 | BIG_LITTLE_CPU_SPEC_FUNCTIONS | |
33aa08b3 AS |
2377 | |
2378 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
2379 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
2380 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
2381 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
2382 | #else | |
2383 | # define MCPU_MTUNE_NATIVE_SPECS "" | |
b848e289 | 2384 | # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS |
33aa08b3 AS |
2385 | #endif |
2386 | ||
2387 | #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS | |
2388 | ||
88657302 | 2389 | #endif /* ! GCC_ARM_H */ |