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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
c58b209a | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
35d965d5 | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 5 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
7 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
8 | ||
4f448245 | 9 | This file is part of GCC. |
35d965d5 | 10 | |
4f448245 NC |
11 | GCC is free software; you can redistribute it and/or modify it |
12 | under the terms of the GNU General Public License as published | |
13 | by the Free Software Foundation; either version 2, or (at your | |
14 | option) any later version. | |
35d965d5 | 15 | |
4f448245 NC |
16 | GCC is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
35d965d5 | 20 | |
4f448245 NC |
21 | You should have received a copy of the GNU General Public License |
22 | along with GCC; see the file COPYING. If not, write to | |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
24 | MA 02111-1307, USA. */ | |
35d965d5 | 25 | |
88657302 RH |
26 | #ifndef GCC_ARM_H |
27 | #define GCC_ARM_H | |
b355a481 | 28 | |
e6471be6 NB |
29 | /* Target CPU builtins. */ |
30 | #define TARGET_CPU_CPP_BUILTINS() \ | |
31 | do \ | |
32 | { \ | |
48f6efae | 33 | if (TARGET_ARM) \ |
e6471be6 NB |
34 | builtin_define ("__arm__"); \ |
35 | else \ | |
36 | builtin_define ("__thumb__"); \ | |
37 | \ | |
38 | if (TARGET_BIG_END) \ | |
39 | { \ | |
40 | builtin_define ("__ARMEB__"); \ | |
41 | if (TARGET_THUMB) \ | |
42 | builtin_define ("__THUMBEB__"); \ | |
43 | if (TARGET_LITTLE_WORDS) \ | |
44 | builtin_define ("__ARMWEL__"); \ | |
45 | } \ | |
46 | else \ | |
47 | { \ | |
48 | builtin_define ("__ARMEL__"); \ | |
49 | if (TARGET_THUMB) \ | |
50 | builtin_define ("__THUMBEL__"); \ | |
51 | } \ | |
52 | \ | |
53 | if (TARGET_APCS_32) \ | |
54 | builtin_define ("__APCS_32__"); \ | |
55 | else \ | |
56 | builtin_define ("__APCS_26__"); \ | |
57 | \ | |
58 | if (TARGET_SOFT_FLOAT) \ | |
59 | builtin_define ("__SOFTFP__"); \ | |
60 | \ | |
b5b620a4 JT |
61 | /* FIXME: TARGET_HARD_FLOAT currently implies \ |
62 | FPA. */ \ | |
63 | if (TARGET_VFP && !TARGET_HARD_FLOAT) \ | |
64 | builtin_define ("__VFP_FP__"); \ | |
65 | \ | |
e6471be6 NB |
66 | /* Add a define for interworking. \ |
67 | Needed when building libgcc.a. */ \ | |
68 | if (TARGET_INTERWORK) \ | |
69 | builtin_define ("__THUMB_INTERWORK__"); \ | |
70 | \ | |
71 | builtin_assert ("cpu=arm"); \ | |
72 | builtin_assert ("machine=arm"); \ | |
73 | } while (0) | |
74 | ||
7a801826 RE |
75 | #define TARGET_CPU_arm2 0x0000 |
76 | #define TARGET_CPU_arm250 0x0000 | |
77 | #define TARGET_CPU_arm3 0x0000 | |
78 | #define TARGET_CPU_arm6 0x0001 | |
79 | #define TARGET_CPU_arm600 0x0001 | |
80 | #define TARGET_CPU_arm610 0x0002 | |
81 | #define TARGET_CPU_arm7 0x0001 | |
82 | #define TARGET_CPU_arm7m 0x0004 | |
83 | #define TARGET_CPU_arm7dm 0x0004 | |
84 | #define TARGET_CPU_arm7dmi 0x0004 | |
85 | #define TARGET_CPU_arm700 0x0001 | |
86 | #define TARGET_CPU_arm710 0x0002 | |
87 | #define TARGET_CPU_arm7100 0x0002 | |
88 | #define TARGET_CPU_arm7500 0x0002 | |
89 | #define TARGET_CPU_arm7500fe 0x1001 | |
90 | #define TARGET_CPU_arm7tdmi 0x0008 | |
91 | #define TARGET_CPU_arm8 0x0010 | |
92 | #define TARGET_CPU_arm810 0x0020 | |
93 | #define TARGET_CPU_strongarm 0x0040 | |
94 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 95 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
96 | #define TARGET_CPU_arm9 0x0080 |
97 | #define TARGET_CPU_arm9tdmi 0x0080 | |
d19fb8e3 | 98 | #define TARGET_CPU_xscale 0x0100 |
9b6b54e2 | 99 | #define TARGET_CPU_ep9312 0x0200 |
82e9d970 | 100 | /* Configure didn't specify. */ |
7a801826 | 101 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 102 | |
d5b7b3ae | 103 | typedef enum arm_cond_code |
89c7ca52 RE |
104 | { |
105 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
106 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
107 | } |
108 | arm_cc; | |
6cfc7210 | 109 | |
d5b7b3ae | 110 | extern arm_cc arm_current_cc; |
ff9940b0 | 111 | |
d5b7b3ae | 112 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 113 | |
6cfc7210 NC |
114 | extern int arm_target_label; |
115 | extern int arm_ccfsm_state; | |
e2500fed | 116 | extern GTY(()) rtx arm_target_insn; |
6cfc7210 NC |
117 | /* Run-time compilation parameters selecting different hardware subsets. */ |
118 | extern int target_flags; | |
119 | /* The floating point instruction architecture, can be 2 or 3 */ | |
120 | extern const char * target_fp_name; | |
d5b7b3ae | 121 | /* Define the information needed to generate branch insns. This is |
e2500fed GK |
122 | stored from the compare operation. */ |
123 | extern GTY(()) rtx arm_compare_op0; | |
124 | extern GTY(()) rtx arm_compare_op1; | |
d5b7b3ae | 125 | /* The label of the current constant pool. */ |
e2500fed | 126 | extern rtx pool_vector_label; |
d5b7b3ae RE |
127 | /* Set to 1 when a return insn is output, this means that the epilogue |
128 | is not needed. */ | |
129 | extern int return_used_this_function; | |
e2500fed GK |
130 | /* Used to produce AOF syntax assembler. */ |
131 | extern GTY(()) rtx aof_pic_label; | |
35d965d5 | 132 | \f |
7a801826 RE |
133 | /* Just in case configure has failed to define anything. */ |
134 | #ifndef TARGET_CPU_DEFAULT | |
135 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
136 | #endif | |
137 | ||
138 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
70f24e49 | 139 | override it. If it doesn't, then default to an ARM6. */ |
7a801826 RE |
140 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic |
141 | #undef TARGET_CPU_DEFAULT | |
70f24e49 | 142 | |
7a801826 RE |
143 | #ifdef SUBTARGET_CPU_DEFAULT |
144 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
145 | #else | |
146 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
147 | #endif | |
148 | #endif | |
149 | ||
150 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
151 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
152 | #else | |
18543a22 | 153 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
154 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
155 | #else | |
156 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
157 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
158 | #else | |
70f24e49 | 159 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi |
7a801826 RE |
160 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
161 | #else | |
dc60a41b | 162 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 |
7a801826 RE |
163 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" |
164 | #else | |
d19fb8e3 NC |
165 | #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale |
166 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" | |
167 | #else | |
9b6b54e2 NC |
168 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 |
169 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__" | |
170 | /* Set TARGET_DEFAULT to the default, but without soft-float. */ | |
171 | #ifdef TARGET_DEFAULT | |
172 | #undef TARGET_DEFAULT | |
173 | #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) | |
174 | #endif /* TARGET_CPU_DEFAULT */ | |
175 | #else | |
7a801826 RE |
176 | Unrecognized value in TARGET_CPU_DEFAULT. |
177 | #endif | |
178 | #endif | |
179 | #endif | |
180 | #endif | |
181 | #endif | |
d19fb8e3 | 182 | #endif |
9b6b54e2 | 183 | #endif |
7a801826 | 184 | |
5742588d | 185 | #undef CPP_SPEC |
e6471be6 NB |
186 | #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ |
187 | %{mapcs-32:%{mapcs-26: \ | |
188 | %e-mapcs-26 and -mapcs-32 may not be used together}} \ | |
189 | %{msoft-float:%{mhard-float: \ | |
190 | %e-msoft-float and -mhard_float may not be used together}} \ | |
191 | %{mbig-endian:%{mlittle-endian: \ | |
192 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 193 | |
71791e16 RE |
194 | /* Set the architecture define -- if -march= is set, then it overrides |
195 | the -mcpu= setting. */ | |
7a801826 | 196 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
197 | %{march=arm2:-D__ARM_ARCH_2__} \ |
198 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
199 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
200 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
201 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
202 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
203 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
204 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
205 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 206 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
207 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
208 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
209 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
210 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
211 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
212 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
213 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
214 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
215 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 216 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
217 | %{march=arm920:-D__ARM_ARCH_4__} \ |
218 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 219 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
220 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
221 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 222 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
223 | %{march=xscale:-D__ARM_ARCH_5TE__} \ |
224 | %{march=xscale:-D__XSCALE__} \ | |
9b6b54e2 NC |
225 | %{march=ep9312:-D__ARM_ARCH_4T__} \ |
226 | %{march=ep9312:-D__MAVERICK__} \ | |
71791e16 RE |
227 | %{march=armv2:-D__ARM_ARCH_2__} \ |
228 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
229 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
230 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
231 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
232 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 233 | %{march=armv5:-D__ARM_ARCH_5__} \ |
d5b7b3ae RE |
234 | %{march=armv5t:-D__ARM_ARCH_5T__} \ |
235 | %{march=armv5e:-D__ARM_ARCH_5E__} \ | |
236 | %{march=armv5te:-D__ARM_ARCH_5TE__} \ | |
71791e16 RE |
237 | %{!march=*: \ |
238 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
239 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
240 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
241 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
242 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
243 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
244 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
245 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
246 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 247 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
248 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
249 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
250 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
251 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
252 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
253 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
254 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
255 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
256 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 257 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
258 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
259 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 260 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
261 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
262 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 263 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
264 | %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ |
265 | %{mcpu=xscale:-D__XSCALE__} \ | |
9b6b54e2 NC |
266 | %{mcpu=ep9312:-D__ARM_ARCH_4T__} \ |
267 | %{mcpu=ep9312:-D__MAVERICK__} \ | |
dfa08768 | 268 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 269 | " |
7a801826 | 270 | |
be393ecf | 271 | #ifndef CC1_SPEC |
dfa08768 | 272 | #define CC1_SPEC "" |
be393ecf | 273 | #endif |
7a801826 RE |
274 | |
275 | /* This macro defines names of additional specifications to put in the specs | |
276 | that can be used in various specifications like CC1_SPEC. Its definition | |
277 | is an initializer with a subgrouping for each command option. | |
278 | ||
279 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 280 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
281 | program. |
282 | ||
283 | Do not define this macro if it does not need to do anything. */ | |
284 | #define EXTRA_SPECS \ | |
285 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
286 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
38fc909b | 287 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
288 | SUBTARGET_EXTRA_SPECS |
289 | ||
914a3b8c | 290 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 291 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
292 | #endif |
293 | ||
6cfc7210 | 294 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 295 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 296 | #endif |
35d965d5 RS |
297 | \f |
298 | /* Run-time Target Specification. */ | |
ff9940b0 | 299 | #ifndef TARGET_VERSION |
6cfc7210 | 300 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 301 | #endif |
35d965d5 | 302 | |
35d965d5 RS |
303 | /* Nonzero if the function prologue (and epilogue) should obey |
304 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 305 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
306 | |
307 | /* Nonzero if the function prologue should output the function name to enable | |
308 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
309 | unused on RISCiX). Specifying this flag also enables |
310 | -fno-omit-frame-pointer. | |
35d965d5 | 311 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 312 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
313 | |
314 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
315 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 316 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 317 | |
11c1a207 RE |
318 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
319 | that assume restoration of the condition flags when returning from a | |
320 | branch and link (ie a function). */ | |
6cfc7210 | 321 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 322 | |
dfa08768 RE |
323 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
324 | ||
11c1a207 RE |
325 | /* Nonzero if stack checking should be performed on entry to each function |
326 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 327 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
328 | |
329 | /* Nonzero if floating point parameters should be passed to functions in | |
330 | floating point registers. */ | |
6cfc7210 | 331 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
332 | |
333 | /* Nonzero if re-entrant, position independent code should be generated. | |
334 | This is equivalent to -fpic. */ | |
6cfc7210 | 335 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 336 | |
5f1e6755 NC |
337 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
338 | be loaded using either LDRH or LDRB instructions. */ | |
339 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
340 | |
341 | /* Nonzero if all floating point instructions are missing (and there is no | |
342 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 343 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
344 | |
345 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 346 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
347 | |
348 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 349 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 350 | |
ddee6aba RE |
351 | /* Nonzero if we should have little-endian words even when compiling for |
352 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 353 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 354 | |
f5a1b0d2 | 355 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 356 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 357 | |
c11145f6 | 358 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 359 | function tries to return. */ |
6cfc7210 | 360 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 361 | |
ed0e6530 | 362 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 363 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 364 | |
b020fd92 NC |
365 | /* Nonzero if all call instructions should be indirect. */ |
366 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
d5b7b3ae RE |
367 | |
368 | /* Nonzero means that the target ISA is the THUMB, not the ARM. */ | |
369 | #define ARM_FLAG_THUMB (1 << 16) | |
370 | ||
371 | /* Set if a TPCS style stack frame should be generated, for non-leaf | |
372 | functions, even if they do not need one. */ | |
373 | #define THUMB_FLAG_BACKTRACE (1 << 17) | |
b020fd92 | 374 | |
d5b7b3ae RE |
375 | /* Set if a TPCS style stack frame should be generated, for leaf |
376 | functions, even if they do not need one. */ | |
377 | #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) | |
378 | ||
379 | /* Set if externally visible functions should assume that they | |
380 | might be called in ARM mode, from a non-thumb aware code. */ | |
381 | #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) | |
382 | ||
383 | /* Set if calls via function pointers should assume that their | |
384 | destination is non-Thumb aware. */ | |
385 | #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) | |
386 | ||
b5b620a4 JT |
387 | /* Nonzero means target uses VFP FP. */ |
388 | #define ARM_FLAG_VFP (1 << 21) | |
389 | ||
dc0ba55a JT |
390 | /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ |
391 | #define ARM_FLAG_ATPCS (1 << 22) | |
392 | ||
9b6b54e2 NC |
393 | /* Fix invalid Cirrus instruction combinations by inserting NOPs. */ |
394 | #define CIRRUS_FIX_INVALID_INSNS (1 << 23) | |
395 | ||
d5b7b3ae | 396 | #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) |
11c1a207 RE |
397 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) |
398 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
399 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
400 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
401 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
402 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
dc0ba55a | 403 | #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS) |
5f1e6755 | 404 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
405 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
406 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
9b6b54e2 NC |
407 | #define TARGET_CIRRUS (arm_is_cirrus) |
408 | #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS) | |
b5b620a4 | 409 | #define TARGET_VFP (target_flags & ARM_FLAG_VFP) |
11c1a207 | 410 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) |
6cfc7210 | 411 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 412 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 413 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 414 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 415 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 416 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
d5b7b3ae RE |
417 | #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) |
418 | #define TARGET_ARM (! TARGET_THUMB) | |
419 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
420 | #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) | |
421 | #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) | |
422 | #define TARGET_BACKTRACE (leaf_function_p () \ | |
423 | ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ | |
424 | : (target_flags & THUMB_FLAG_BACKTRACE)) | |
9b6b54e2 | 425 | #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS) |
3ada8e17 | 426 | |
c7bdf0a6 | 427 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ |
3ada8e17 DE |
428 | #ifndef SUBTARGET_SWITCHES |
429 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
430 | #endif |
431 | ||
047142d3 PT |
432 | #define TARGET_SWITCHES \ |
433 | { \ | |
434 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
435 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
436 | N_("Generate APCS conformant stack frames") }, \ | |
437 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
438 | {"poke-function-name", ARM_FLAG_POKE, \ | |
439 | N_("Store function names in object code") }, \ | |
440 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
441 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
442 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
b605cfa8 | 443 | N_("Use the 32-bit version of the APCS") }, \ |
047142d3 | 444 | {"apcs-26", -ARM_FLAG_APCS_32, \ |
b605cfa8 | 445 | N_("Use the 26-bit version of the APCS") }, \ |
047142d3 PT |
446 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ |
447 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
448 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
449 | N_("Pass FP arguments in FP registers") }, \ | |
450 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
451 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
452 | N_("Generate re-entrant, PIC code") }, \ | |
453 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
454 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ | |
455 | N_("The MMU will trap on unaligned accesses") }, \ | |
456 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
457 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
458 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
459 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
460 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
461 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ | |
462 | N_("Use library calls to perform FP operations") }, \ | |
463 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
464 | N_("Use hardware floating point instructions") }, \ | |
465 | {"big-endian", ARM_FLAG_BIG_END, \ | |
466 | N_("Assume target CPU is configured as big endian") }, \ | |
467 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
468 | N_("Assume target CPU is configured as little endian") }, \ | |
469 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
470 | N_("Assume big endian bytes, little endian words") }, \ | |
471 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
b605cfa8 | 472 | N_("Support calls between Thumb and ARM instruction sets") }, \ |
047142d3 PT |
473 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ |
474 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
475 | N_("Generate a call to abort if a noreturn function returns")}, \ | |
476 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ | |
b605cfa8 | 477 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ |
047142d3 | 478 | N_("Do not move instructions into a function's prologue") }, \ |
b605cfa8 | 479 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ |
047142d3 PT |
480 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ |
481 | N_("Do not load the PIC register in function prologues") }, \ | |
482 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ | |
483 | {"long-calls", ARM_FLAG_LONG_CALLS, \ | |
484 | N_("Generate call insns as indirect calls, if necessary") }, \ | |
485 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ | |
486 | {"thumb", ARM_FLAG_THUMB, \ | |
487 | N_("Compile for the Thumb not the ARM") }, \ | |
488 | {"no-thumb", -ARM_FLAG_THUMB, "" }, \ | |
489 | {"arm", -ARM_FLAG_THUMB, "" }, \ | |
490 | {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ | |
491 | N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ | |
492 | {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ | |
493 | {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ | |
494 | N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ | |
495 | {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ | |
496 | {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
497 | N_("Thumb: Assume non-static functions may be called from ARM code") }, \ | |
498 | {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
499 | "" }, \ | |
500 | {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
501 | N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ | |
502 | {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
503 | "" }, \ | |
9b6b54e2 NC |
504 | {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \ |
505 | N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \ | |
506 | {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \ | |
507 | N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\ | |
047142d3 PT |
508 | SUBTARGET_SWITCHES \ |
509 | {"", TARGET_DEFAULT, "" } \ | |
35d965d5 RS |
510 | } |
511 | ||
43cffd11 RE |
512 | #define TARGET_OPTIONS \ |
513 | { \ | |
f5a1b0d2 | 514 | {"cpu=", & arm_select[0].string, \ |
7052a099 | 515 | N_("Specify the name of the target CPU"), 0}, \ |
f5a1b0d2 | 516 | {"arch=", & arm_select[1].string, \ |
7052a099 RE |
517 | N_("Specify the name of the target architecture"), 0}, \ |
518 | {"tune=", & arm_select[2].string, "", 0}, \ | |
519 | {"fpe=", & target_fp_name, "" , 0}, \ | |
f5a1b0d2 | 520 | {"fp=", & target_fp_name, \ |
7052a099 | 521 | N_("Specify the version of the floating point emulator"), 0},\ |
047142d3 | 522 | {"structure-size-boundary=", & structure_size_string, \ |
7052a099 | 523 | N_("Specify the minimum bit alignment of structures"), 0}, \ |
047142d3 | 524 | {"pic-register=", & arm_pic_register_string, \ |
7052a099 | 525 | N_("Specify the register to be used for PIC addressing"), 0} \ |
11c1a207 | 526 | } |
ff9940b0 | 527 | |
62dd06ea RE |
528 | struct arm_cpu_select |
529 | { | |
f9cc092a RE |
530 | const char * string; |
531 | const char * name; | |
532 | const struct processors * processors; | |
62dd06ea RE |
533 | }; |
534 | ||
f5a1b0d2 NC |
535 | /* This is a magic array. If the user specifies a command line switch |
536 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
537 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
538 | extern struct arm_cpu_select arm_select[]; |
539 | ||
11c1a207 RE |
540 | enum prog_mode_type |
541 | { | |
542 | prog_mode26, | |
543 | prog_mode32 | |
544 | }; | |
545 | ||
546 | /* Recast the program mode class to be the prog_mode attribute */ | |
547 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
548 | ||
549 | extern enum prog_mode_type arm_prgmode; | |
550 | ||
551 | /* What sort of floating point unit do we have? Hardware or software. | |
552 | If software, is it issue 2 or issue 3? */ | |
29ad9694 | 553 | enum fputype |
24f0c1b4 | 554 | { |
29ad9694 RE |
555 | /* Software floating point, FPA style double fmt. */ |
556 | FPUTYPE_SOFT_FPA, | |
557 | /* Full FPA support. */ | |
558 | FPUTYPE_FPA, | |
559 | /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ | |
560 | FPUTYPE_FPA_EMU2, | |
561 | /* Emulated FPA hardware, Issue 3 emulator. */ | |
562 | FPUTYPE_FPA_EMU3, | |
563 | /* Cirrus Maverick floating point co-processor. */ | |
564 | FPUTYPE_MAVERICK | |
24f0c1b4 RE |
565 | }; |
566 | ||
567 | /* Recast the floating point class to be the floating point attribute. */ | |
29ad9694 | 568 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) |
24f0c1b4 | 569 | |
71791e16 | 570 | /* What type of floating point to tune for */ |
29ad9694 | 571 | extern enum fputype arm_fpu_tune; |
24f0c1b4 | 572 | |
71791e16 | 573 | /* What type of floating point instructions are available */ |
29ad9694 | 574 | extern enum fputype arm_fpu_arch; |
71791e16 | 575 | |
18543a22 | 576 | /* Default floating point architecture. Override in sub-target if |
71791e16 | 577 | necessary. */ |
29ad9694 RE |
578 | #ifndef FPUTYPE_DEFAULT |
579 | #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2 | |
be393ecf | 580 | #endif |
71791e16 | 581 | |
9b6b54e2 | 582 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 |
29ad9694 RE |
583 | #undef FPUTYPE_DEFAULT |
584 | #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK | |
9b6b54e2 NC |
585 | #endif |
586 | ||
11c1a207 RE |
587 | /* Nonzero if the processor has a fast multiply insn, and one that does |
588 | a 64-bit multiply of two 32-bit values. */ | |
589 | extern int arm_fast_multiply; | |
590 | ||
71791e16 | 591 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
592 | extern int arm_arch4; |
593 | ||
62b10bbc NC |
594 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
595 | extern int arm_arch5; | |
596 | ||
b15bca31 RE |
597 | /* Nonzero if this chip supports the ARM Architecture 5E extensions */ |
598 | extern int arm_arch5e; | |
599 | ||
f5a1b0d2 NC |
600 | /* Nonzero if this chip can benefit from load scheduling. */ |
601 | extern int arm_ld_sched; | |
602 | ||
0616531f RE |
603 | /* Nonzero if generating thumb code. */ |
604 | extern int thumb_code; | |
605 | ||
f5a1b0d2 NC |
606 | /* Nonzero if this chip is a StrongARM. */ |
607 | extern int arm_is_strong; | |
608 | ||
9b6b54e2 NC |
609 | /* Nonzero if this chip is a Cirrus variant. */ |
610 | extern int arm_is_cirrus; | |
611 | ||
d19fb8e3 NC |
612 | /* Nonzero if this chip is an XScale. */ |
613 | extern int arm_is_xscale; | |
614 | ||
3569057d | 615 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 NC |
616 | extern int arm_is_6_or_7; |
617 | ||
2ce9c1b9 | 618 | #ifndef TARGET_DEFAULT |
d5b7b3ae | 619 | #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) |
2ce9c1b9 | 620 | #endif |
35d965d5 | 621 | |
11c1a207 RE |
622 | /* The frame pointer register used in gcc has nothing to do with debugging; |
623 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 624 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 625 | |
be393ecf | 626 | #undef TARGET_MEM_FUNCTIONS |
11c1a207 RE |
627 | #define TARGET_MEM_FUNCTIONS 1 |
628 | ||
629 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
630 | |
631 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
632 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
633 | Subtargets can override these if required. */ |
634 | #ifndef NEED_GOT_RELOC | |
635 | #define NEED_GOT_RELOC 0 | |
636 | #endif | |
637 | #ifndef NEED_PLT_RELOC | |
638 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 639 | #endif |
84306176 PB |
640 | |
641 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
642 | offset. In other words, generate | |
643 | ||
644 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
645 | ||
646 | rather than | |
647 | ||
648 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
649 | ||
650 | The default is true, which matches NetBSD. Subtargets can | |
651 | override this if required. */ | |
652 | #ifndef GOT_PCREL | |
653 | #define GOT_PCREL 1 | |
654 | #endif | |
35d965d5 RS |
655 | \f |
656 | /* Target machine storage Layout. */ | |
657 | ||
ff9940b0 RE |
658 | |
659 | /* Define this macro if it is advisable to hold scalars in registers | |
660 | in a wider mode than that declared by the program. In such cases, | |
661 | the value is constrained to be within the bounds of the declared | |
662 | type, but kept valid in the wider mode. The signedness of the | |
663 | extension may differ from that of the type. */ | |
664 | ||
665 | /* It is far faster to zero extend chars than to sign extend them */ | |
666 | ||
6cfc7210 | 667 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
668 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
669 | && GET_MODE_SIZE (MODE) < 4) \ | |
670 | { \ | |
671 | if (MODE == QImode) \ | |
672 | UNSIGNEDP = 1; \ | |
673 | else if (MODE == HImode) \ | |
5f1e6755 | 674 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 675 | (MODE) = SImode; \ |
ff9940b0 RE |
676 | } |
677 | ||
18543a22 ILT |
678 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
679 | should also be done for outgoing function arguments. */ | |
680 | /* This is required to ensure that push insns always push a word. */ | |
681 | #define PROMOTE_FUNCTION_ARGS | |
682 | ||
35d965d5 RS |
683 | /* Define this if most significant bit is lowest numbered |
684 | in instructions that operate on numbered bit-fields. */ | |
685 | #define BITS_BIG_ENDIAN 0 | |
686 | ||
9c872872 | 687 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
688 | Most ARM processors are run in little endian mode, so that is the default. |
689 | If you want to have it run-time selectable, change the definition in a | |
690 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 691 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
692 | |
693 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
694 | numbered. |
695 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
696 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
697 | ||
698 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
699 | on processor pre-defineds when compiling libgcc2.c. */ | |
700 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
701 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
702 | #else | |
703 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
704 | #endif | |
35d965d5 | 705 | |
11c1a207 | 706 | /* Define this if most significant word of doubles is the lowest numbered. |
f0375c66 NC |
707 | The rules are different based on whether or not we use FPA-format, |
708 | VFP-format or some other floating point co-processor's format doubles. */ | |
b5b620a4 | 709 | #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) |
7fc6c9f0 | 710 | |
35d965d5 RS |
711 | #define UNITS_PER_WORD 4 |
712 | ||
35d965d5 RS |
713 | #define PARM_BOUNDARY 32 |
714 | ||
715 | #define STACK_BOUNDARY 32 | |
716 | ||
0977774b JT |
717 | #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32) |
718 | ||
35d965d5 RS |
719 | #define FUNCTION_BOUNDARY 32 |
720 | ||
92928d71 AO |
721 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
722 | vbit must go into the delta field of pointers to member | |
723 | functions. */ | |
724 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
725 | ||
35d965d5 RS |
726 | #define EMPTY_FIELD_BOUNDARY 32 |
727 | ||
728 | #define BIGGEST_ALIGNMENT 32 | |
729 | ||
ff9940b0 | 730 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
d19fb8e3 NC |
731 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) |
732 | ||
733 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
734 | ((TREE_CODE (EXP) == STRING_CST \ | |
735 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
736 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 737 | |
723ae7c1 NC |
738 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
739 | value set in previous versions of this toolchain was 8, which produces more | |
740 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 741 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 NC |
742 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
743 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
744 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
745 | extern int arm_structure_size_boundary; | |
723ae7c1 | 746 | |
4912a07c | 747 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 748 | particular arm target wants to change the default value it should change |
6bc82793 | 749 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
750 | for an example of this. */ |
751 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
752 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 753 | #endif |
2a5307b1 | 754 | |
b355a481 | 755 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 756 | extern const char * structure_size_string; |
b4ac57ab | 757 | |
825dda42 | 758 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 759 | when given unaligned data. */ |
35d965d5 | 760 | #define STRICT_ALIGNMENT 1 |
35d965d5 RS |
761 | \f |
762 | /* Standard register usage. */ | |
763 | ||
764 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
765 | (S - saved over call). | |
766 | ||
767 | r0 * argument word/integer result | |
768 | r1-r3 argument word | |
769 | ||
770 | r4-r8 S register variable | |
771 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
772 | |
773 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
774 | r11 F S (fp) argument pointer |
775 | r12 (ip) temp workspace | |
776 | r13 F S (sp) lower end of current stack frame | |
777 | r14 (lr) link address/workspace | |
778 | r15 F (pc) program counter | |
779 | ||
780 | f0 floating point result | |
781 | f1-f3 floating point scratch | |
782 | ||
783 | f4-f7 S floating point variable | |
784 | ||
ff9940b0 RE |
785 | cc This is NOT a real register, but is used internally |
786 | to represent things that use or set the condition | |
787 | codes. | |
788 | sfp This isn't either. It is used during rtl generation | |
789 | since the offset between the frame pointer and the | |
790 | auto's isn't known until after register allocation. | |
791 | afp Nor this, we only need this because of non-local | |
792 | goto. Without it fp appears to be used and the | |
793 | elimination code won't get rid of sfp. It tracks | |
794 | fp exactly at all times. | |
795 | ||
35d965d5 RS |
796 | *: See CONDITIONAL_REGISTER_USAGE */ |
797 | ||
9b6b54e2 NC |
798 | /* |
799 | mvf0 Cirrus floating point result | |
800 | mvf1-mvf3 Cirrus floating point scratch | |
801 | mvf4-mvf15 S Cirrus floating point variable. */ | |
802 | ||
ff9940b0 RE |
803 | /* The stack backtrace structure is as follows: |
804 | fp points to here: | save code pointer | [fp] | |
805 | | return link value | [fp, #-4] | |
806 | | return sp value | [fp, #-8] | |
807 | | return fp value | [fp, #-12] | |
808 | [| saved r10 value |] | |
809 | [| saved r9 value |] | |
810 | [| saved r8 value |] | |
811 | [| saved r7 value |] | |
812 | [| saved r6 value |] | |
813 | [| saved r5 value |] | |
814 | [| saved r4 value |] | |
815 | [| saved r3 value |] | |
816 | [| saved r2 value |] | |
817 | [| saved r1 value |] | |
818 | [| saved r0 value |] | |
819 | [| saved f7 value |] three words | |
820 | [| saved f6 value |] three words | |
821 | [| saved f5 value |] three words | |
822 | [| saved f4 value |] three words | |
823 | r0-r3 are not normally saved in a C function. */ | |
824 | ||
35d965d5 RS |
825 | /* 1 for registers that have pervasive standard uses |
826 | and are not available for the register allocator. */ | |
827 | #define FIXED_REGISTERS \ | |
828 | { \ | |
829 | 0,0,0,0,0,0,0,0, \ | |
d5b7b3ae | 830 | 0,0,0,0,0,1,0,1, \ |
ff9940b0 | 831 | 0,0,0,0,0,0,0,0, \ |
9b6b54e2 NC |
832 | 1,1,1, \ |
833 | 1,1,1,1,1,1,1,1, \ | |
834 | 1,1,1,1,1,1,1,1 \ | |
35d965d5 RS |
835 | } |
836 | ||
837 | /* 1 for registers not available across function calls. | |
838 | These must include the FIXED_REGISTERS and also any | |
839 | registers that can be used without being saved. | |
840 | The latter must include the registers where values are returned | |
841 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
842 | Aside from that, you can include as many other registers as you like. |
843 | The CC is not preserved over function calls on the ARM 6, so it is | |
844 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
845 | #define CALL_USED_REGISTERS \ |
846 | { \ | |
847 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 848 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 | 849 | 1,1,1,1,0,0,0,0, \ |
9b6b54e2 NC |
850 | 1,1,1, \ |
851 | 1,1,1,1,1,1,1,1, \ | |
852 | 1,1,1,1,1,1,1,1 \ | |
35d965d5 RS |
853 | } |
854 | ||
6cc8c0b3 NC |
855 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
856 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
857 | #endif | |
858 | ||
d5b7b3ae RE |
859 | #define CONDITIONAL_REGISTER_USAGE \ |
860 | { \ | |
4b02997f NC |
861 | int regno; \ |
862 | \ | |
d5b7b3ae RE |
863 | if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ |
864 | { \ | |
d5b7b3ae RE |
865 | for (regno = FIRST_ARM_FP_REGNUM; \ |
866 | regno <= LAST_ARM_FP_REGNUM; ++regno) \ | |
867 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
868 | } \ | |
9b6b54e2 NC |
869 | \ |
870 | if (TARGET_CIRRUS) \ | |
871 | { \ | |
872 | for (regno = FIRST_ARM_FP_REGNUM; \ | |
873 | regno <= LAST_ARM_FP_REGNUM; ++ regno) \ | |
874 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
875 | for (regno = FIRST_CIRRUS_FP_REGNUM; \ | |
876 | regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ | |
877 | { \ | |
878 | fixed_regs[regno] = 0; \ | |
879 | call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ | |
880 | } \ | |
881 | } \ | |
882 | \ | |
fc555370 | 883 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
d5b7b3ae RE |
884 | { \ |
885 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
886 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
887 | } \ | |
888 | else if (TARGET_APCS_STACK) \ | |
889 | { \ | |
890 | fixed_regs[10] = 1; \ | |
891 | call_used_regs[10] = 1; \ | |
892 | } \ | |
893 | if (TARGET_APCS_FRAME) \ | |
894 | { \ | |
895 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
896 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
897 | } \ | |
898 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 899 | } |
d5b7b3ae | 900 | |
6bc82793 | 901 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
902 | by asm_fprintf: |
903 | %@ prints out ASM_COMMENT_START | |
904 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
905 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
906 | case '@': \ | |
907 | fputs (ASM_COMMENT_START, FILE); \ | |
908 | break; \ | |
909 | \ | |
910 | case 'r': \ | |
911 | fputs (REGISTER_PREFIX, FILE); \ | |
912 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
913 | break; | |
914 | ||
d5b7b3ae | 915 | /* Round X up to the nearest word. */ |
0c2ca901 | 916 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 917 | |
6cfc7210 | 918 | /* Convert fron bytes to ints. */ |
e9d7b180 | 919 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 NC |
920 | |
921 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
e9d7b180 JD |
922 | #define ARM_NUM_REGS(MODE) \ |
923 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
924 | |
925 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
926 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
927 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 928 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
929 | |
930 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 931 | #define NUM_ARG_REGS 4 |
6cfc7210 NC |
932 | |
933 | /* Return the regiser number of the N'th (integer) argument. */ | |
d5b7b3ae | 934 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 935 | |
e04546dc NC |
936 | #if 0 /* FIXME: The ARM backend has special code to handle structure |
937 | returns, and will reserve its own hidden first argument. So | |
938 | if this macro is enabled a *second* hidden argument will be | |
d6a7951f | 939 | reserved, which will break binary compatibility with old |
e04546dc NC |
940 | toolchains and also thunk handling. One day this should be |
941 | fixed. */ | |
64a7723d | 942 | /* RTX for structure returns. NULL means use a hidden first argument. */ |
31448271 | 943 | #define STRUCT_VALUE 0 |
e04546dc NC |
944 | #else |
945 | /* Register in which address to store a structure value | |
946 | is passed to a function. */ | |
947 | #define STRUCT_VALUE_REGNUM ARG_REGISTER (1) | |
948 | #endif | |
6cfc7210 | 949 | |
d5b7b3ae RE |
950 | /* Specify the registers used for certain standard purposes. |
951 | The values of these macros are register numbers. */ | |
35d965d5 | 952 | |
d5b7b3ae RE |
953 | /* The number of the last argument register. */ |
954 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 955 | |
d5b7b3ae | 956 | /* The number of the last "lo" register (thumb). */ |
6d3d9133 NC |
957 | #define LAST_LO_REGNUM 7 |
958 | ||
959 | /* The register that holds the return address in exception handlers. */ | |
960 | #define EXCEPTION_LR_REGNUM 2 | |
35d965d5 | 961 | |
d5b7b3ae RE |
962 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
963 | as an invisible last argument (possible since varargs don't exist in | |
964 | Pascal), so the following is not true. */ | |
68dfd979 | 965 | #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) |
35d965d5 | 966 | |
d5b7b3ae RE |
967 | /* Define this to be where the real frame pointer is if it is not possible to |
968 | work out the offset between the frame pointer and the automatic variables | |
969 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
970 | should point to a special register that we will make sure is eliminated. | |
971 | ||
972 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 973 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
974 | as base register for addressing purposes. (See comments in |
975 | find_reloads_address()). But - the Thumb does not allow high registers, | |
976 | including r11, to be used as base address registers. Hence our problem. | |
977 | ||
978 | The solution used here, and in the old thumb port is to use r7 instead of | |
979 | r11 as the hard frame pointer and to have special code to generate | |
980 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 981 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
982 | pointer. */ |
983 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
984 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 985 | |
b15bca31 RE |
986 | #define HARD_FRAME_POINTER_REGNUM \ |
987 | (TARGET_ARM \ | |
988 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
989 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 990 | |
b15bca31 | 991 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 992 | |
b15bca31 RE |
993 | /* Register to use for pushing function arguments. */ |
994 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
995 | |
996 | /* ARM floating pointer registers. */ | |
997 | #define FIRST_ARM_FP_REGNUM 16 | |
998 | #define LAST_ARM_FP_REGNUM 23 | |
999 | ||
35d965d5 | 1000 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
1001 | #define FRAME_POINTER_REGNUM 25 |
1002 | ||
d5b7b3ae RE |
1003 | /* Base register for access to arguments of the function. */ |
1004 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 1005 | |
9b6b54e2 NC |
1006 | #define FIRST_CIRRUS_FP_REGNUM 27 |
1007 | #define LAST_CIRRUS_FP_REGNUM 42 | |
1008 | #define IS_CIRRUS_REGNUM(REGNUM) \ | |
1009 | (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) | |
1010 | ||
6f8c9bd1 NC |
1011 | /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ |
1012 | /* + 16 Cirrus registers take us up to 43. */ | |
9b6b54e2 | 1013 | #define FIRST_PSEUDO_REGISTER 43 |
62b10bbc | 1014 | |
35d965d5 RS |
1015 | /* Value should be nonzero if functions must have frame pointers. |
1016 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
1017 | via the stack pointer) in functions that seem suitable. |
1018 | If we have to have a frame pointer we might as well make use of it. | |
1019 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 1020 | functions, or simple tail call functions. */ |
7b8b8ade NC |
1021 | #define FRAME_POINTER_REQUIRED \ |
1022 | (current_function_has_nonlocal_label \ | |
d5b7b3ae | 1023 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) |
35d965d5 | 1024 | |
d5b7b3ae RE |
1025 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1026 | to hold something of mode MODE. | |
1027 | This is ordinarily the length in words of a value of mode MODE | |
1028 | but can be less for certain modes in special long registers. | |
35d965d5 | 1029 | |
3b684012 | 1030 | On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP |
d5b7b3ae RE |
1031 | mode. */ |
1032 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
1033 | ((TARGET_ARM \ | |
1034 | && REGNO >= FIRST_ARM_FP_REGNUM \ | |
1035 | && REGNO != FRAME_POINTER_REGNUM \ | |
1036 | && REGNO != ARG_POINTER_REGNUM) \ | |
e9d7b180 | 1037 | ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 1038 | |
4b02997f | 1039 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 1040 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 1041 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 1042 | |
d5b7b3ae RE |
1043 | /* Value is 1 if it is a good idea to tie two pseudo registers |
1044 | when one has mode MODE1 and one has mode MODE2. | |
1045 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1046 | for any hard reg, then this must be 0 for correct output. */ | |
1047 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1048 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 1049 | |
35d965d5 | 1050 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1051 | since no saving is required (though calls clobber it) and it never contains |
1052 | function parameters. It is quite good to use lr since other calls may | |
1053 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
1054 | least likely to contain a function parameter; in addition results are | |
d5b7b3ae | 1055 | returned in r0. */ |
ff73fb53 | 1056 | #define REG_ALLOC_ORDER \ |
35d965d5 | 1057 | { \ |
ff73fb53 NC |
1058 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
1059 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 1060 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
9b6b54e2 NC |
1061 | 27, 28, 29, 30, 31, 32, 33, 34, \ |
1062 | 35, 36, 37, 38, 39, 40, 41, 42, \ | |
ff73fb53 | 1063 | 24, 25, 26 \ |
35d965d5 | 1064 | } |
9338ffe6 PB |
1065 | |
1066 | /* Interrupt functions can only use registers that have already been | |
1067 | saved by the prologue, even if they would normally be | |
1068 | call-clobbered. */ | |
1069 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1070 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
1071 | regs_ever_live[DST]) | |
35d965d5 RS |
1072 | \f |
1073 | /* Register and constant classes. */ | |
1074 | ||
3b684012 | 1075 | /* Register classes: used to be simple, just all ARM regs or all FPA regs |
d6a7951f | 1076 | Now that the Thumb is involved it has become more complicated. */ |
35d965d5 RS |
1077 | enum reg_class |
1078 | { | |
1079 | NO_REGS, | |
3b684012 | 1080 | FPA_REGS, |
9b6b54e2 | 1081 | CIRRUS_REGS, |
d5b7b3ae RE |
1082 | LO_REGS, |
1083 | STACK_REG, | |
1084 | BASE_REGS, | |
1085 | HI_REGS, | |
1086 | CC_REG, | |
35d965d5 RS |
1087 | GENERAL_REGS, |
1088 | ALL_REGS, | |
1089 | LIM_REG_CLASSES | |
1090 | }; | |
1091 | ||
1092 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1093 | ||
1094 | /* Give names of register classes as strings for dump file. */ | |
1095 | #define REG_CLASS_NAMES \ | |
1096 | { \ | |
1097 | "NO_REGS", \ | |
3b684012 | 1098 | "FPA_REGS", \ |
9b6b54e2 | 1099 | "CIRRUS_REGS", \ |
d5b7b3ae RE |
1100 | "LO_REGS", \ |
1101 | "STACK_REG", \ | |
1102 | "BASE_REGS", \ | |
1103 | "HI_REGS", \ | |
1104 | "CC_REG", \ | |
35d965d5 RS |
1105 | "GENERAL_REGS", \ |
1106 | "ALL_REGS", \ | |
1107 | } | |
1108 | ||
1109 | /* Define which registers fit in which classes. | |
1110 | This is an initializer for a vector of HARD_REG_SET | |
1111 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
1112 | #define REG_CLASS_CONTENTS \ |
1113 | { \ | |
9b6b54e2 | 1114 | { 0x00000000, 0x0 }, /* NO_REGS */ \ |
3b684012 | 1115 | { 0x00FF0000, 0x0 }, /* FPA_REGS */ \ |
9b6b54e2 NC |
1116 | { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \ |
1117 | { 0x000000FF, 0x0 }, /* LO_REGS */ \ | |
1118 | { 0x00002000, 0x0 }, /* STACK_REG */ \ | |
1119 | { 0x000020FF, 0x0 }, /* BASE_REGS */ \ | |
1120 | { 0x0000FF00, 0x0 }, /* HI_REGS */ \ | |
1121 | { 0x01000000, 0x0 }, /* CC_REG */ \ | |
1122 | { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\ | |
1123 | { 0xFAFFFFFF, 0x000007FF } /* ALL_REGS */ \ | |
35d965d5 | 1124 | } |
4b02997f | 1125 | |
35d965d5 RS |
1126 | /* The same information, inverted: |
1127 | Return the class number of the smallest class containing | |
1128 | reg number REGNO. This could be a conditional expression | |
1129 | or could index an array. */ | |
d5b7b3ae | 1130 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1131 | |
1132 | /* The class value for index registers, and the one for base regs. */ | |
d5b7b3ae | 1133 | #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
b93a0fe6 | 1134 | #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
d5b7b3ae | 1135 | |
b93a0fe6 | 1136 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1137 | when addressing quantities in QI or HI mode; if we don't know the |
b93a0fe6 RE |
1138 | mode, then we must be conservative. After reload we must also be |
1139 | conservative, since we can't support SP+reg addressing, and we | |
1140 | can't fix up any bad substitutions. */ | |
3dcc68a4 | 1141 | #define MODE_BASE_REG_CLASS(MODE) \ |
b93a0fe6 RE |
1142 | (TARGET_ARM ? GENERAL_REGS : \ |
1143 | (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) | |
3dcc68a4 | 1144 | |
d5b7b3ae RE |
1145 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows |
1146 | registers explicitly used in the rtl to be used as spill registers | |
1147 | but prevents the compiler from extending the lifetime of these | |
1148 | registers. */ | |
1149 | #define SMALL_REGISTER_CLASSES TARGET_THUMB | |
35d965d5 RS |
1150 | |
1151 | /* Get reg_class from a letter such as appears in the machine description. | |
3b684012 | 1152 | We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the |
d5b7b3ae RE |
1153 | ARM, but several more letters for the Thumb. */ |
1154 | #define REG_CLASS_FROM_LETTER(C) \ | |
3b684012 | 1155 | ( (C) == 'f' ? FPA_REGS \ |
9b6b54e2 | 1156 | : (C) == 'v' ? CIRRUS_REGS \ |
d5b7b3ae RE |
1157 | : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ |
1158 | : TARGET_ARM ? NO_REGS \ | |
1159 | : (C) == 'h' ? HI_REGS \ | |
1160 | : (C) == 'b' ? BASE_REGS \ | |
1161 | : (C) == 'k' ? STACK_REG \ | |
1162 | : (C) == 'c' ? CC_REG \ | |
1163 | : NO_REGS) | |
35d965d5 RS |
1164 | |
1165 | /* The letters I, J, K, L and M in a register constraint string | |
1166 | can be used to stand for particular ranges of immediate operands. | |
1167 | This macro defines what the ranges are. | |
1168 | C is the letter, and VALUE is a constant value. | |
1169 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 1170 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 1171 | J: valid indexing constants. |
aef1764c | 1172 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
1173 | L: -value ok in rhs argument of data operand. |
1174 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
d5b7b3ae | 1175 | #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ |
aef1764c RE |
1176 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ |
1177 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
1178 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
1179 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
1180 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
1181 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
1182 | : 0) | |
ff9940b0 | 1183 | |
d5b7b3ae RE |
1184 | #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ |
1185 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ | |
1186 | (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ | |
1187 | (C) == 'K' ? thumb_shiftable_const (VAL) : \ | |
1188 | (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ | |
1189 | (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ | |
1190 | && ((VAL) & 3) == 0) : \ | |
1191 | (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ | |
1192 | (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ | |
1193 | : 0) | |
1194 | ||
1195 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1196 | (TARGET_ARM ? \ | |
1197 | CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) | |
1198 | ||
3b684012 | 1199 | /* Constant letter 'G' for the FPA immediate constants. |
d5b7b3ae RE |
1200 | 'H' means the same constant negated. */ |
1201 | #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ | |
3b684012 RE |
1202 | ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \ |
1203 | (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0) | |
d5b7b3ae RE |
1204 | |
1205 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ | |
1206 | (TARGET_ARM ? \ | |
1207 | CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) | |
1208 | ||
ff9940b0 RE |
1209 | /* For the ARM, `Q' means that this is a memory operand that is just |
1210 | an offset from a register. | |
1211 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
1212 | address. This means that the symbol is in the text segment and can be | |
1213 | accessed without using a load. */ | |
1214 | ||
d5b7b3ae RE |
1215 | #define EXTRA_CONSTRAINT_ARM(OP, C) \ |
1216 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ | |
1217 | (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
1218 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
1219 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ | |
9b6b54e2 NC |
1220 | (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ |
1221 | (C) == 'T' ? cirrus_memory_offset (OP) : \ | |
1222 | 0) | |
ff9940b0 | 1223 | |
d5b7b3ae RE |
1224 | #define EXTRA_CONSTRAINT_THUMB(X, C) \ |
1225 | ((C) == 'Q' ? (GET_CODE (X) == MEM \ | |
1226 | && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) | |
1227 | ||
1228 | #define EXTRA_CONSTRAINT(X, C) \ | |
1229 | (TARGET_ARM ? \ | |
1230 | EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) | |
35d965d5 RS |
1231 | |
1232 | /* Given an rtx X being reloaded into a reg required to be | |
1233 | in class CLASS, return the class of reg to actually use. | |
d5b7b3ae RE |
1234 | In general this is just CLASS, but for the Thumb we prefer |
1235 | a LO_REGS class or a subset. */ | |
1236 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1237 | (TARGET_ARM ? (CLASS) : \ | |
1238 | ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) | |
1239 | ||
1240 | /* Must leave BASE_REGS reloads alone */ | |
1241 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1242 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1243 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1244 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1245 | : NO_REGS)) \ | |
1246 | : NO_REGS) | |
1247 | ||
1248 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1249 | ((CLASS) != LO_REGS \ | |
1250 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1251 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1252 | : NO_REGS)) \ | |
1253 | : NO_REGS) | |
35d965d5 | 1254 | |
ff9940b0 RE |
1255 | /* Return the register class of a scratch register needed to copy IN into |
1256 | or out of a register in CLASS in MODE. If it can be done directly, | |
1257 | NO_REGS is returned. */ | |
d5b7b3ae RE |
1258 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1259 | (TARGET_ARM ? \ | |
1260 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
1261 | ? GENERAL_REGS : NO_REGS) \ | |
1262 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
1263 | ||
2ce9c1b9 | 1264 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1265 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
9b6b54e2 NC |
1266 | /* Cannot load constants into Cirrus registers. */ \ |
1267 | ((TARGET_CIRRUS \ | |
1268 | && (CLASS) == CIRRUS_REGS \ | |
1269 | && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ | |
1270 | ? GENERAL_REGS : \ | |
d5b7b3ae RE |
1271 | (TARGET_ARM ? \ |
1272 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ | |
1273 | && (GET_CODE (X) == MEM \ | |
1274 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1275 | && true_regnum (X) == -1))) \ | |
1276 | ? GENERAL_REGS : NO_REGS) \ | |
9b6b54e2 | 1277 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) |
2ce9c1b9 | 1278 | |
6f734908 RE |
1279 | /* Try a machine-dependent way of reloading an illegitimate address |
1280 | operand. If we find one, push the reload and jump to WIN. This | |
1281 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1282 | ||
1283 | For the ARM, we wish to handle large displacements off a base | |
1284 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1285 | This can cut the number of reloads needed. */ |
1286 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1287 | do \ | |
1288 | { \ | |
1289 | if (GET_CODE (X) == PLUS \ | |
1290 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1291 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1292 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1293 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1294 | { \ | |
1295 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1296 | HOST_WIDE_INT low, high; \ | |
1297 | \ | |
1298 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1299 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
9b6b54e2 NC |
1300 | else if (TARGET_CIRRUS) \ |
1301 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1302 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
d5b7b3ae RE |
1303 | else if (MODE == SImode \ |
1304 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1305 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1306 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1307 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1308 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1309 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1310 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1311 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1312 | && TARGET_HARD_FLOAT) \ | |
1313 | /* Need to be careful, -1024 is not a valid offset. */ \ | |
1314 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1315 | else \ | |
1316 | break; \ | |
1317 | \ | |
30cf4896 KG |
1318 | high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ |
1319 | ^ (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1320 | - (unsigned HOST_WIDE_INT) 0x80000000); \ | |
d5b7b3ae RE |
1321 | /* Check for overflow or zero */ \ |
1322 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1323 | break; \ | |
1324 | \ | |
1325 | /* Reload the high part into a base reg; leave the low part \ | |
1326 | in the mem. */ \ | |
1327 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1328 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1329 | GEN_INT (high)), \ | |
1330 | GEN_INT (low)); \ | |
df4ae160 | 1331 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
4a692617 NC |
1332 | MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ |
1333 | VOIDmode, 0, 0, OPNUM, TYPE); \ | |
d5b7b3ae RE |
1334 | goto WIN; \ |
1335 | } \ | |
1336 | } \ | |
62b10bbc | 1337 | while (0) |
6f734908 | 1338 | |
d5b7b3ae RE |
1339 | /* ??? If an HImode FP+large_offset address is converted to an HImode |
1340 | SP+large_offset address, then reload won't know how to fix it. It sees | |
1341 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1342 | register, but the resulting address is still invalid because the offset | |
1343 | is too big. We fix it here instead by reloading the entire address. */ | |
1344 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1345 | cope with the variances between the Thumb's signed and unsigned byte and | |
1346 | halfword load instructions. */ | |
1347 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1348 | { \ | |
1349 | if (GET_CODE (X) == PLUS \ | |
1350 | && GET_MODE_SIZE (MODE) < 4 \ | |
1351 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1352 | && XEXP (X, 0) == stack_pointer_rtx \ | |
1353 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
76a318e9 | 1354 | && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
1355 | { \ |
1356 | rtx orig_X = X; \ | |
1357 | X = copy_rtx (X); \ | |
df4ae160 | 1358 | push_reload (orig_X, NULL_RTX, &X, NULL, \ |
4a692617 | 1359 | MODE_BASE_REG_CLASS (MODE), \ |
d5b7b3ae RE |
1360 | Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ |
1361 | goto WIN; \ | |
1362 | } \ | |
1363 | } | |
1364 | ||
1365 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1366 | if (TARGET_ARM) \ | |
1367 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1368 | else \ | |
1369 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
1370 | ||
35d965d5 RS |
1371 | /* Return the maximum number of consecutive registers |
1372 | needed to represent mode MODE in a register of class CLASS. | |
3b684012 | 1373 | ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ |
35d965d5 | 1374 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
3b684012 | 1375 | (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1376 | |
1377 | /* If defined, gives a class of registers that cannot be used as the | |
1378 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 | 1379 | |
3b684012 | 1380 | /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */ |
cf011243 | 1381 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
d5b7b3ae | 1382 | (TARGET_ARM ? \ |
3b684012 RE |
1383 | ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ |
1384 | (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ | |
9b6b54e2 NC |
1385 | (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ |
1386 | (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ | |
1387 | 2) \ | |
d5b7b3ae RE |
1388 | : \ |
1389 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 RS |
1390 | \f |
1391 | /* Stack layout; function entry, exit and calling. */ | |
1392 | ||
1393 | /* Define this if pushing a word on the stack | |
1394 | makes the stack pointer a smaller address. */ | |
1395 | #define STACK_GROWS_DOWNWARD 1 | |
1396 | ||
1397 | /* Define this if the nominal address of the stack frame | |
1398 | is at the high-address end of the local variables; | |
1399 | that is, each additional local variable allocated | |
1400 | goes at a more negative offset in the frame. */ | |
1401 | #define FRAME_GROWS_DOWNWARD 1 | |
1402 | ||
1403 | /* Offset within stack frame to start allocating local variables at. | |
1404 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1405 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1406 | of the first local allocated. */ | |
1407 | #define STARTING_FRAME_OFFSET 0 | |
1408 | ||
1409 | /* If we generate an insn to push BYTES bytes, | |
1410 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae RE |
1411 | /* The push insns do not do this rounding implicitly. |
1412 | So don't define this. */ | |
0c2ca901 | 1413 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1414 | |
1415 | /* Define this if the maximum size of all the outgoing args is to be | |
1416 | accumulated and pushed during the prologue. The amount can be | |
1417 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1418 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1419 | |
1420 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1421 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1422 | |
1423 | /* Value is the number of byte of arguments automatically | |
1424 | popped when returning from a subroutine call. | |
8b109b37 | 1425 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1426 | FUNTYPE is the data type of the function (as a tree), |
1427 | or for a library call it is an identifier node for the subroutine name. | |
1428 | SIZE is the number of bytes of arguments passed on the stack. | |
1429 | ||
1430 | On the ARM, the caller does not pop any of its arguments that were passed | |
1431 | on the stack. */ | |
6cfc7210 | 1432 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1433 | |
1434 | /* Define how to find the value returned by a library function | |
1435 | assuming the value has mode MODE. */ | |
1436 | #define LIBCALL_VALUE(MODE) \ | |
d5b7b3ae RE |
1437 | (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1438 | ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ | |
9b6b54e2 NC |
1439 | : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1440 | ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ | |
d5b7b3ae | 1441 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) |
35d965d5 | 1442 | |
6cfc7210 NC |
1443 | /* Define how to find the value returned by a function. |
1444 | VALTYPE is the data type of the value (as a tree). | |
1445 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1446 | otherwise, FUNC is 0. */ | |
d5b7b3ae | 1447 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
6cfc7210 NC |
1448 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
1449 | ||
35d965d5 RS |
1450 | /* 1 if N is a possible register number for a function value. |
1451 | On the ARM, only r0 and f0 can return results. */ | |
9b6b54e2 | 1452 | /* On a Cirrus chip, mvf0 can return results. */ |
35d965d5 | 1453 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ |
d5b7b3ae | 1454 | ((REGNO) == ARG_REGISTER (1) \ |
9b6b54e2 | 1455 | || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \ |
d5b7b3ae | 1456 | || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) |
35d965d5 | 1457 | |
11c1a207 RE |
1458 | /* How large values are returned */ |
1459 | /* A C expression which can inhibit the returning of certain function values | |
1460 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1461 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1462 | |
1463 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1464 | values must be in memory. On the ARM, they need only do so if larger | |
1465 | than a word, or if they contain elements offset from zero in the struct. */ | |
1466 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1467 | ||
d5b7b3ae RE |
1468 | /* Flags for the call/call_value rtl operations set up by function_arg. */ |
1469 | #define CALL_NORMAL 0x00000000 /* No special processing. */ | |
1470 | #define CALL_LONG 0x00000001 /* Always call indirect. */ | |
1471 | #define CALL_SHORT 0x00000002 /* Never call indirect. */ | |
1472 | ||
6d3d9133 NC |
1473 | /* These bits describe the different types of function supported |
1474 | by the ARM backend. They are exclusive. ie a function cannot be both a | |
1475 | normal function and an interworked function, for example. Knowing the | |
1476 | type of a function is important for determining its prologue and | |
1477 | epilogue sequences. | |
1478 | Note value 7 is currently unassigned. Also note that the interrupt | |
1479 | function types all have bit 2 set, so that they can be tested for easily. | |
1480 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1481 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1482 | default to unknown. This will force the first use of arm_current_func_type |
1483 | to call arm_compute_func_type. */ | |
1484 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1485 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1486 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
1487 | #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ | |
1488 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
1489 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1490 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1491 | ||
1492 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1493 | ||
1494 | /* In addition functions can have several type modifiers, | |
1495 | outlined by these bit masks: */ | |
1496 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1497 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1498 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
1499 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
1500 | ||
1501 | /* Some macros to test these flags. */ | |
1502 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1503 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1504 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1505 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1506 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
1507 | ||
1508 | /* A C structure for machine-specific, per-function data. | |
1509 | This is added to the cfun structure. */ | |
e2500fed | 1510 | typedef struct machine_function GTY(()) |
d5b7b3ae | 1511 | { |
6bc82793 | 1512 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1513 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1514 | /* Records if LR has to be saved for far jumps. */ |
1515 | int far_jump_used; | |
1516 | /* Records if ARG_POINTER was ever live. */ | |
1517 | int arg_pointer_live; | |
6f7ebcbb NC |
1518 | /* Records if the save of LR has been eliminated. */ |
1519 | int lr_save_eliminated; | |
0977774b JT |
1520 | /* The size of the stack frame. Only valid after reload. */ |
1521 | int frame_size; | |
6d3d9133 NC |
1522 | /* Records the type of the current function. */ |
1523 | unsigned long func_type; | |
3cb66fd7 NC |
1524 | /* Record if the function has a variable argument list. */ |
1525 | int uses_anonymous_args; | |
6d3d9133 NC |
1526 | } |
1527 | machine_function; | |
d5b7b3ae | 1528 | |
82e9d970 PB |
1529 | /* A C type for declaring a variable that is used as the first argument of |
1530 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1531 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1532 | typedef struct | |
1533 | { | |
d5b7b3ae | 1534 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1535 | int nregs; |
d5b7b3ae | 1536 | /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ |
82e9d970 | 1537 | int call_cookie; |
d5b7b3ae | 1538 | } CUMULATIVE_ARGS; |
82e9d970 | 1539 | |
35d965d5 RS |
1540 | /* Define where to put the arguments to a function. |
1541 | Value is zero to push the argument on the stack, | |
1542 | or a hard register in which to store the argument. | |
1543 | ||
1544 | MODE is the argument's machine mode. | |
1545 | TYPE is the data type of the argument (as a tree). | |
1546 | This is null for libcalls where that information may | |
1547 | not be available. | |
1548 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1549 | the preceding args and about the function being called. | |
1550 | NAMED is nonzero if this argument is a named parameter | |
1551 | (otherwise it is an extra parameter matching an ellipsis). | |
1552 | ||
1553 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1554 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1555 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1556 | passed in the stack (function_prologue will indeed make it pass in the | |
1557 | stack if necessary). */ | |
82e9d970 PB |
1558 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1559 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1560 | |
1561 | /* For an arg passed partly in registers and partly in memory, | |
1562 | this is the number of registers used. | |
1563 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1564 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1565 | ( NUM_ARG_REGS > (CUM).nregs \ |
e9d7b180 | 1566 | && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ |
82e9d970 | 1567 | ? NUM_ARG_REGS - (CUM).nregs : 0) |
35d965d5 | 1568 | |
1741620c JD |
1569 | /* A C expression that indicates when an argument must be passed by |
1570 | reference. If nonzero for an argument, a copy of that argument is | |
1571 | made in memory and a pointer to the argument is passed instead of | |
1572 | the argument itself. The pointer is passed in whatever way is | |
1573 | appropriate for passing a pointer to that type. */ | |
1574 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1575 | arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) | |
1576 | ||
35d965d5 RS |
1577 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1578 | for a call to a function whose data type is FNTYPE. | |
1579 | For a library call, FNTYPE is 0. | |
1580 | On the ARM, the offset starts at 0. */ | |
563a317a JH |
1581 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \ |
1582 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) | |
35d965d5 RS |
1583 | |
1584 | /* Update the data in CUM to advance over an argument | |
1585 | of mode MODE and data type TYPE. | |
1586 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1587 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
e9d7b180 | 1588 | (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1589 | |
1590 | /* 1 if N is a possible register number for function argument passing. | |
1591 | On the ARM, r0-r3 are used to pass args. */ | |
5297e085 | 1592 | #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3)) |
35d965d5 | 1593 | |
1741620c JD |
1594 | /* Implement `va_arg'. */ |
1595 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1596 | arm_va_arg (valist, type) | |
1597 | ||
f99fce0c | 1598 | \f |
35d965d5 RS |
1599 | /* Perform any actions needed for a function that is receiving a variable |
1600 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1601 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1602 | the amount of stack that must be pushed by the prolog to pretend that our | |
1603 | caller pushed it. | |
1604 | ||
1605 | Normally, this macro will push all remaining incoming registers on the | |
1606 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1607 | ||
1608 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1609 | named arg and all anonymous args onto the stack. | |
1610 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1611 | that way. */ | |
6cfc7210 | 1612 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 | 1613 | { \ |
3cb66fd7 | 1614 | cfun->machine->uses_anonymous_args = 1; \ |
82e9d970 PB |
1615 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1616 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1617 | } |
1618 | ||
afef3d7a NC |
1619 | /* If your target environment doesn't prefix user functions with an |
1620 | underscore, you may wish to re-define this to prevent any conflicts. | |
1621 | e.g. AOF may prefix mcount with an underscore. */ | |
1622 | #ifndef ARM_MCOUNT_NAME | |
1623 | #define ARM_MCOUNT_NAME "*mcount" | |
1624 | #endif | |
1625 | ||
1626 | /* Call the function profiler with a given profile label. The Acorn | |
1627 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1628 | On the ARM the full profile code will look like: | |
1629 | .data | |
1630 | LP1 | |
1631 | .word 0 | |
1632 | .text | |
1633 | mov ip, lr | |
1634 | bl mcount | |
1635 | .word LP1 | |
1636 | ||
1637 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1638 | will output the .text section. | |
1639 | ||
1640 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1641 | ``prof'' doesn't seem to mind about this! |
1642 | ||
1643 | Note - this version of the code is designed to work in both ARM and | |
1644 | Thumb modes. */ | |
be393ecf | 1645 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1646 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1647 | { \ |
1648 | char temp[20]; \ | |
1649 | rtx sym; \ | |
1650 | \ | |
dd18ae56 | 1651 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1652 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1653 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1654 | fputc ('\n', STREAM); \ | |
1655 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1656 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
301d03af | 1657 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1658 | } |
be393ecf | 1659 | #endif |
35d965d5 | 1660 | |
59be6073 | 1661 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1662 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1663 | if (TARGET_ARM) \ | |
1664 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1665 | else \ | |
1666 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1667 | #else |
1668 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1669 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1670 | #endif | |
d5b7b3ae | 1671 | |
35d965d5 RS |
1672 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1673 | the stack pointer does not matter. The value is tested only in | |
1674 | functions that have frame pointers. | |
1675 | No definition is equivalent to always zero. | |
1676 | ||
1677 | On the ARM, the function epilogue recovers the stack pointer from the | |
1678 | frame. */ | |
1679 | #define EXIT_IGNORE_STACK 1 | |
1680 | ||
c7861455 RE |
1681 | #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) |
1682 | ||
35d965d5 RS |
1683 | /* Determine if the epilogue should be output as RTL. |
1684 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae RE |
1685 | #define USE_RETURN_INSN(ISCOND) \ |
1686 | (TARGET_ARM ? use_return_insn (ISCOND) : 0) | |
ff9940b0 RE |
1687 | |
1688 | /* Definitions for register eliminations. | |
1689 | ||
1690 | This is an array of structures. Each structure initializes one pair | |
1691 | of eliminable registers. The "from" register number is given first, | |
1692 | followed by "to". Eliminations of the same "from" register are listed | |
1693 | in order of preference. | |
1694 | ||
1695 | We have two registers that can be eliminated on the ARM. First, the | |
1696 | arg pointer register can often be eliminated in favor of the stack | |
1697 | pointer register. Secondly, the pseudo frame pointer register can always | |
1698 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1699 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1700 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1701 | |
d5b7b3ae RE |
1702 | #define ELIMINABLE_REGS \ |
1703 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1704 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1705 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1706 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1707 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1708 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1709 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1710 | |
d5b7b3ae RE |
1711 | /* Given FROM and TO register numbers, say whether this elimination is |
1712 | allowed. Frame pointer elimination is automatically handled. | |
ff9940b0 RE |
1713 | |
1714 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1715 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 | 1716 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
d5b7b3ae RE |
1717 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or |
1718 | ARG_POINTER_REGNUM. */ | |
1719 | #define CAN_ELIMINATE(FROM, TO) \ | |
1720 | (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ | |
1721 | ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ | |
1722 | ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ | |
1723 | ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ | |
1724 | 1) | |
aeaf4d25 AN |
1725 | |
1726 | #define THUMB_REG_PUSHED_P(reg) \ | |
1727 | (regs_ever_live [reg] \ | |
1728 | && (! call_used_regs [reg] \ | |
1729 | || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \ | |
1730 | && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register))) | |
1731 | ||
d5b7b3ae RE |
1732 | /* Define the offset between two registers, one to be eliminated, and the |
1733 | other its replacement, at the start of a routine. */ | |
1734 | #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
095bb276 | 1735 | do \ |
ff9940b0 | 1736 | { \ |
095bb276 | 1737 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
ff9940b0 | 1738 | } \ |
095bb276 | 1739 | while (0) |
35d965d5 | 1740 | |
d5b7b3ae RE |
1741 | /* Note: This macro must match the code in thumb_function_prologue(). */ |
1742 | #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1743 | { \ | |
1744 | (OFFSET) = 0; \ | |
1745 | if ((FROM) == ARG_POINTER_REGNUM) \ | |
1746 | { \ | |
1747 | int count_regs = 0; \ | |
1748 | int regno; \ | |
1749 | for (regno = 8; regno < 13; regno ++) \ | |
aeaf4d25 AN |
1750 | if (THUMB_REG_PUSHED_P (regno)) \ |
1751 | count_regs ++; \ | |
d5b7b3ae RE |
1752 | if (count_regs) \ |
1753 | (OFFSET) += 4 * count_regs; \ | |
1754 | count_regs = 0; \ | |
1755 | for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ | |
aeaf4d25 | 1756 | if (THUMB_REG_PUSHED_P (regno)) \ |
d5b7b3ae RE |
1757 | count_regs ++; \ |
1758 | if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ | |
1759 | (OFFSET) += 4 * (count_regs + 1); \ | |
1760 | if (TARGET_BACKTRACE) \ | |
1761 | { \ | |
1762 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ | |
1763 | (OFFSET) += 20; \ | |
1764 | else \ | |
1765 | (OFFSET) += 16; \ | |
1766 | } \ | |
1767 | } \ | |
1768 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1769 | { \ | |
1770 | (OFFSET) += current_function_outgoing_args_size; \ | |
0977774b | 1771 | (OFFSET) += thumb_get_frame_size (); \ |
d5b7b3ae RE |
1772 | } \ |
1773 | } | |
1774 | ||
1775 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1776 | if (TARGET_ARM) \ | |
095bb276 | 1777 | ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ |
d5b7b3ae RE |
1778 | else \ |
1779 | THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) | |
1780 | ||
1781 | /* Special case handling of the location of arguments passed on the stack. */ | |
1782 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
1783 | ||
1784 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1785 | once for every function before code is generated. */ | |
1786 | #define INIT_EXPANDERS arm_init_expanders () | |
1787 | ||
35d965d5 RS |
1788 | /* Output assembler code for a block containing the constant parts |
1789 | of a trampoline, leaving space for the variable parts. | |
1790 | ||
1791 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1792 | referencing pc adds an offset of 8) the trampoline looks like: | |
1793 | ldr r8, [pc, #0] | |
1794 | ldr pc, [pc] | |
1795 | .word static chain value | |
11c1a207 RE |
1796 | .word function's address |
1797 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
301d03af RS |
1798 | #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ |
1799 | { \ | |
1800 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1801 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1802 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1803 | PC_REGNUM, PC_REGNUM); \ | |
1804 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
1805 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
d5b7b3ae RE |
1806 | } |
1807 | ||
1808 | /* On the Thumb we always switch into ARM mode to execute the trampoline. | |
1809 | Why - because it is easier. This code will always be branched to via | |
1810 | a BX instruction and since the compiler magically generates the address | |
1811 | of the function the linker has no opportunity to ensure that the | |
1812 | bottom bit is set. Thus the processor will be in ARM mode when it | |
1813 | reaches this code. So we duplicate the ARM trampoline code and add | |
1814 | a switch into Thumb mode as well. */ | |
1815 | #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ | |
1816 | { \ | |
1817 | fprintf (FILE, "\t.code 32\n"); \ | |
1818 | fprintf (FILE, ".Ltrampoline_start:\n"); \ | |
1819 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1820 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1821 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1822 | IP_REGNUM, PC_REGNUM); \ | |
1823 | asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ | |
1824 | IP_REGNUM, IP_REGNUM); \ | |
1825 | asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ | |
1826 | fprintf (FILE, "\t.word\t0\n"); \ | |
1827 | fprintf (FILE, "\t.word\t0\n"); \ | |
1828 | fprintf (FILE, "\t.code 16\n"); \ | |
35d965d5 RS |
1829 | } |
1830 | ||
d5b7b3ae RE |
1831 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1832 | if (TARGET_ARM) \ | |
1833 | ARM_TRAMPOLINE_TEMPLATE (FILE) \ | |
1834 | else \ | |
1835 | THUMB_TRAMPOLINE_TEMPLATE (FILE) | |
1836 | ||
35d965d5 | 1837 | /* Length in units of the trampoline for entering a nested function. */ |
d5b7b3ae | 1838 | #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) |
35d965d5 | 1839 | |
006946e4 JM |
1840 | /* Alignment required for a trampoline in bits. */ |
1841 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1842 | |
1843 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1844 | FNADDR is an RTX for the address of the function's pure code. | |
1845 | CXT is an RTX for the static chain value for the function. */ | |
d5b7b3ae RE |
1846 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1847 | { \ | |
1848 | emit_move_insn \ | |
1849 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ | |
1850 | emit_move_insn \ | |
1851 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ | |
35d965d5 RS |
1852 | } |
1853 | ||
35d965d5 RS |
1854 | \f |
1855 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 RE |
1856 | #define HAVE_POST_INCREMENT 1 |
1857 | #define HAVE_PRE_INCREMENT TARGET_ARM | |
1858 | #define HAVE_POST_DECREMENT TARGET_ARM | |
1859 | #define HAVE_PRE_DECREMENT TARGET_ARM | |
1860 | #define HAVE_PRE_MODIFY_DISP TARGET_ARM | |
1861 | #define HAVE_POST_MODIFY_DISP TARGET_ARM | |
1862 | #define HAVE_PRE_MODIFY_REG TARGET_ARM | |
1863 | #define HAVE_POST_MODIFY_REG TARGET_ARM | |
35d965d5 RS |
1864 | |
1865 | /* Macros to check register numbers against specific register classes. */ | |
1866 | ||
1867 | /* These assume that REGNO is a hard or pseudo reg number. | |
1868 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1869 | or a pseudo reg currently allocated to a suitable hard reg. | |
1870 | Since they use reg_renumber, they are safe only once reg_renumber | |
d5b7b3ae RE |
1871 | has been allocated, which happens in local-alloc.c. */ |
1872 | #define TEST_REGNO(R, TEST, VALUE) \ | |
1873 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1874 | ||
1875 | /* On the ARM, don't allow the pc to be used. */ | |
f1008e52 RE |
1876 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1877 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1878 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1879 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1880 | ||
1881 | #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1882 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
1883 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1884 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1885 | ||
1886 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1887 | (TARGET_THUMB \ | |
1888 | ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
1889 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
1890 | ||
1891 | /* For ARM code, we don't care about the mode, but for Thumb, the index | |
1892 | must be suitable for use in a QImode load. */ | |
d5b7b3ae RE |
1893 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1894 | REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) | |
35d965d5 RS |
1895 | |
1896 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 | 1897 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1898 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1899 | |
1900 | /* Recognize any constant value that is a valid address. */ | |
1901 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1902 | |
1903 | #ifdef AOF_ASSEMBLER | |
1904 | ||
1905 | #define CONSTANT_ADDRESS_P(X) \ | |
d5b7b3ae | 1906 | (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) |
11c1a207 RE |
1907 | |
1908 | #else | |
35d965d5 | 1909 | |
008cf58a RE |
1910 | #define CONSTANT_ADDRESS_P(X) \ |
1911 | (GET_CODE (X) == SYMBOL_REF \ | |
1912 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1913 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1914 | |
11c1a207 RE |
1915 | #endif /* AOF_ASSEMBLER */ |
1916 | ||
35d965d5 RS |
1917 | /* Nonzero if the constant value X is a legitimate general operand. |
1918 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1919 | ||
1920 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1921 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1922 | constant pool XXX. |
82e9d970 PB |
1923 | |
1924 | When generating pic allow anything. */ | |
d5b7b3ae RE |
1925 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1926 | ||
1927 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1928 | ( GET_CODE (X) == CONST_INT \ | |
1929 | || GET_CODE (X) == CONST_DOUBLE \ | |
7b8781c8 PB |
1930 | || CONSTANT_ADDRESS_P (X) \ |
1931 | || flag_pic) | |
d5b7b3ae RE |
1932 | |
1933 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1934 | (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) | |
1935 | ||
c27ba912 DM |
1936 | /* Special characters prefixed to function names |
1937 | in order to encode attribute like information. | |
1938 | Note, '@' and '*' have already been taken. */ | |
1939 | #define SHORT_CALL_FLAG_CHAR '^' | |
1940 | #define LONG_CALL_FLAG_CHAR '#' | |
1941 | ||
1942 | #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ | |
1943 | (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) | |
1944 | ||
1945 | #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ | |
1946 | (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) | |
1947 | ||
1948 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
1949 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1950 | #endif | |
1951 | ||
6bc82793 | 1952 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1953 | Each case label should return the number of characters to |
1954 | be stripped from the start of a function's name, if that | |
1955 | name starts with the indicated character. */ | |
1956 | #define ARM_NAME_ENCODING_LENGTHS \ | |
1957 | case SHORT_CALL_FLAG_CHAR: return 1; \ | |
1958 | case LONG_CALL_FLAG_CHAR: return 1; \ | |
00fdafef | 1959 | case '*': return 1; \ |
c27ba912 DM |
1960 | SUBTARGET_NAME_ENCODING_LENGTHS |
1961 | ||
c27ba912 DM |
1962 | /* This is how to output a reference to a user-level label named NAME. |
1963 | `assemble_name' uses this. */ | |
e5951263 | 1964 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1965 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1966 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1967 | |
c27ba912 DM |
1968 | #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ |
1969 | arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) | |
1970 | ||
35d965d5 RS |
1971 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1972 | and check its validity for a certain class. | |
1973 | We have two alternate definitions for each of them. | |
1974 | The usual definition accepts all pseudo regs; the other rejects | |
1975 | them unless they have been allocated suitable hard regs. | |
1976 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1977 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1978 | |
f1008e52 RE |
1979 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1980 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1981 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1982 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1983 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1984 | |
f1008e52 RE |
1985 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1986 | (REGNO (X) <= LAST_LO_REGNUM \ | |
1987 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1988 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1989 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1990 | || (X) == hard_frame_pointer_rtx \ | |
1991 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1992 | |
76a318e9 RE |
1993 | #define REG_STRICT_P 0 |
1994 | ||
d5b7b3ae | 1995 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1996 | |
f1008e52 RE |
1997 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1998 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1999 | |
f1008e52 RE |
2000 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2001 | THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 2002 | |
76a318e9 RE |
2003 | #define REG_STRICT_P 1 |
2004 | ||
d5b7b3ae | 2005 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
2006 | |
2007 | /* Now define some helpers in terms of the above. */ | |
2008 | ||
2009 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
2010 | (TARGET_THUMB \ | |
2011 | ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
2012 | : ARM_REG_OK_FOR_BASE_P (X)) | |
2013 | ||
2014 | #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) | |
2015 | ||
2016 | /* For Thumb, a valid index register is anything that can be used in | |
2017 | a byte load instruction. */ | |
2018 | #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
2019 | ||
2020 | /* Nonzero if X is a hard reg that can be used as an index | |
2021 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
2022 | is not suitable. */ | |
2023 | #define REG_OK_FOR_INDEX_P(X) \ | |
2024 | (TARGET_THUMB \ | |
2025 | ? THUMB_REG_OK_FOR_INDEX_P (X) \ | |
2026 | : ARM_REG_OK_FOR_INDEX_P (X)) | |
2027 | ||
35d965d5 RS |
2028 | \f |
2029 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
2030 | that is a valid memory address for an instruction. | |
2031 | The MODE argument is the machine mode for the MEM expression | |
76a318e9 | 2032 | that wants to use this address. */ |
d5b7b3ae | 2033 | |
f1008e52 RE |
2034 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
2035 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 2036 | |
f1008e52 RE |
2037 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
2038 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 | 2039 | |
76a318e9 RE |
2040 | #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ |
2041 | { \ | |
2042 | if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \ | |
2043 | goto WIN; \ | |
6b990f6b | 2044 | } |
d5b7b3ae | 2045 | |
76a318e9 RE |
2046 | #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ |
2047 | { \ | |
2048 | if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \ | |
2049 | goto WIN; \ | |
2050 | } | |
d5b7b3ae | 2051 | |
d5b7b3ae RE |
2052 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ |
2053 | if (TARGET_ARM) \ | |
2054 | ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ | |
2055 | else /* if (TARGET_THUMB) */ \ | |
2056 | THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) | |
76a318e9 | 2057 | |
35d965d5 RS |
2058 | \f |
2059 | /* Try machine-dependent ways of modifying an illegitimate address | |
ccf4d512 RE |
2060 | to be legitimate. If we find one, return the new, valid address. */ |
2061 | #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2062 | do { \ | |
2063 | X = arm_legitimize_address (X, OLDX, MODE); \ | |
2064 | \ | |
2065 | if (memory_address_p (MODE, X)) \ | |
2066 | goto WIN; \ | |
2067 | } while (0) | |
2068 | ||
2069 | #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2070 | do { \ | |
2071 | if (flag_pic) \ | |
2072 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
2073 | } while (0) | |
2074 | ||
2075 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2076 | do { \ | |
2077 | if (TARGET_ARM) \ | |
2078 | ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ | |
2079 | else \ | |
2080 | THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ | |
2081 | } while (0) | |
d5b7b3ae | 2082 | |
35d965d5 RS |
2083 | /* Go to LABEL if ADDR (a legitimate address expression) |
2084 | has an effect that depends on the machine mode it is used for. */ | |
d5b7b3ae | 2085 | #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
35d965d5 | 2086 | { \ |
d5b7b3ae RE |
2087 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ |
2088 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
35d965d5 RS |
2089 | goto LABEL; \ |
2090 | } | |
d5b7b3ae RE |
2091 | |
2092 | /* Nothing helpful to do for the Thumb */ | |
2093 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2094 | if (TARGET_ARM) \ | |
2095 | ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) | |
35d965d5 | 2096 | \f |
d5b7b3ae | 2097 | |
35d965d5 RS |
2098 | /* Specify the machine mode that this machine uses |
2099 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2100 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2101 | |
18543a22 ILT |
2102 | /* Define as C expression which evaluates to nonzero if the tablejump |
2103 | instruction expects the table to contain offsets from the address of the | |
2104 | table. | |
2105 | Do not define this if the table should contain absolute addresses. */ | |
2106 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 | 2107 | |
ff9940b0 RE |
2108 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2109 | unsigned is probably best, but may break some code. */ | |
2110 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2111 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2112 | #endif |
2113 | ||
2114 | /* Don't cse the address of the function being compiled. */ | |
2115 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
2116 | ||
2117 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
2118 | in one reasonably fast instruction. */ |
2119 | #define MOVE_MAX 4 | |
35d965d5 | 2120 | |
d19fb8e3 NC |
2121 | #undef MOVE_RATIO |
2122 | #define MOVE_RATIO (arm_is_xscale ? 4 : 2) | |
2123 | ||
ff9940b0 RE |
2124 | /* Define if operations between registers always perform the operation |
2125 | on the full register even if a narrower mode is specified. */ | |
2126 | #define WORD_REGISTER_OPERATIONS | |
2127 | ||
2128 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2129 | will either zero-extend or sign-extend. The value of this macro should | |
2130 | be the code that says which one of the two operations is implicitly | |
2131 | done, NIL if none. */ | |
9c872872 | 2132 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2133 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2134 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
2135 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) | |
ff9940b0 | 2136 | |
35d965d5 RS |
2137 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2138 | #define SLOW_BYTE_ACCESS 0 | |
2139 | ||
d5b7b3ae RE |
2140 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
2141 | ||
35d965d5 RS |
2142 | /* Immediate shift counts are truncated by the output routines (or was it |
2143 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2144 | that the native compiler puts too large (> 32) immediate shift counts | |
2145 | into a register and shifts by the register, letting the ARM decide what | |
2146 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2147 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2148 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2149 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
2150 | rotates is modulo 32 used. */ | |
2151 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 2152 | |
35d965d5 | 2153 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2154 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2155 | |
2156 | /* Calling from registers is a massive pain. */ | |
2157 | #define NO_FUNCTION_CSE 1 | |
2158 | ||
2159 | /* Chars and shorts should be passed as ints. */ | |
2160 | #define PROMOTE_PROTOTYPES 1 | |
2161 | ||
35d965d5 RS |
2162 | /* The machine modes of pointers and functions */ |
2163 | #define Pmode SImode | |
2164 | #define FUNCTION_MODE Pmode | |
2165 | ||
d5b7b3ae RE |
2166 | #define ARM_FRAME_RTX(X) \ |
2167 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2168 | || (X) == arg_pointer_rtx) |
2169 | ||
ff9940b0 | 2170 | /* Moves to and from memory are quite expensive */ |
d5b7b3ae RE |
2171 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
2172 | (TARGET_ARM ? 10 : \ | |
2173 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
2174 | * (CLASS == LO_REGS ? 1 : 2))) | |
2175 | ||
ff9940b0 RE |
2176 | /* Try to generate sequences that don't involve branches, we can then use |
2177 | conditional instructions */ | |
d5b7b3ae RE |
2178 | #define BRANCH_COST \ |
2179 | (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) | |
7a801826 RE |
2180 | \f |
2181 | /* Position Independent Code. */ | |
2182 | /* We decide which register to use based on the compilation options and | |
2183 | the assembler in use; this is more general than the APCS restriction of | |
2184 | using sb (r9) all the time. */ | |
2185 | extern int arm_pic_register; | |
2186 | ||
ed0e6530 PB |
2187 | /* Used when parsing command line option -mpic-register=. */ |
2188 | extern const char * arm_pic_register_string; | |
2189 | ||
7a801826 RE |
2190 | /* The register number of the register used to address a table of static |
2191 | data addresses in memory. */ | |
2192 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2193 | ||
c1163e75 | 2194 | #define FINALIZE_PIC arm_finalize_pic (1) |
7a801826 | 2195 | |
f5a1b0d2 NC |
2196 | /* We can't directly access anything that contains a symbol, |
2197 | nor can we indirect via the constant pool. */ | |
82e9d970 | 2198 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2199 | (!(symbol_mentioned_p (X) \ |
2200 | || label_mentioned_p (X) \ | |
2201 | || (GET_CODE (X) == SYMBOL_REF \ | |
2202 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2203 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
2204 | || label_mentioned_p (get_pool_constant (X)))))) | |
2205 | ||
13bd191d PB |
2206 | /* We need to know when we are making a constant pool; this determines |
2207 | whether data needs to be in the GOT or can be referenced via a GOT | |
2208 | offset. */ | |
2209 | extern int making_const_table; | |
82e9d970 | 2210 | \f |
c27ba912 | 2211 | /* Handle pragmas for compatibility with Intel's compilers. */ |
c58b209a NB |
2212 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2213 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
2214 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
2215 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
8b97c5f8 ZW |
2216 | } while (0) |
2217 | ||
ff9940b0 RE |
2218 | /* Condition code information. */ |
2219 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
a5381466 | 2220 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2221 | |
2222 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2223 | |
008cf58a RE |
2224 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
2225 | ||
62b10bbc NC |
2226 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2227 | do \ | |
2228 | { \ | |
2229 | if (GET_CODE (OP1) == CONST_INT \ | |
2230 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2231 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2232 | { \ | |
2233 | rtx const_op = OP1; \ | |
2234 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
2235 | OP1 = const_op; \ | |
2236 | } \ | |
2237 | } \ | |
2238 | while (0) | |
62dd06ea | 2239 | |
ff9940b0 RE |
2240 | #define STORE_FLAG_VALUE 1 |
2241 | ||
7dba8395 RH |
2242 | /* The arm5 clz instruction returns 32. */ |
2243 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
35d965d5 | 2244 | \f |
d5b7b3ae RE |
2245 | #undef ASM_APP_OFF |
2246 | #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") | |
35d965d5 | 2247 | |
35d965d5 | 2248 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae RE |
2249 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
2250 | if (TARGET_ARM) \ | |
2251 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2252 | STACK_POINTER_REGNUM, REGNO); \ | |
2253 | else \ | |
2254 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) | |
2255 | ||
2256 | ||
2257 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
2258 | if (TARGET_ARM) \ | |
2259 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2260 | STACK_POINTER_REGNUM, REGNO); \ | |
2261 | else \ | |
2262 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) | |
2263 | ||
2264 | /* This is how to output a label which precedes a jumptable. Since | |
2265 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
be393ecf | 2266 | #undef ASM_OUTPUT_CASE_LABEL |
d5b7b3ae RE |
2267 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ |
2268 | do \ | |
2269 | { \ | |
2270 | if (TARGET_THUMB) \ | |
2271 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
4977bab6 | 2272 | (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ |
d5b7b3ae RE |
2273 | } \ |
2274 | while (0) | |
35d965d5 | 2275 | |
6cfc7210 NC |
2276 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2277 | do \ | |
2278 | { \ | |
d5b7b3ae RE |
2279 | if (TARGET_THUMB) \ |
2280 | { \ | |
2281 | if (is_called_in_ARM_mode (DECL)) \ | |
2282 | fprintf (STREAM, "\t.code 32\n") ; \ | |
2283 | else \ | |
2284 | fprintf (STREAM, "\t.thumb_func\n") ; \ | |
2285 | } \ | |
6cfc7210 | 2286 | if (TARGET_POKE_FUNCTION_NAME) \ |
6354dc9b | 2287 | arm_poke_function_name (STREAM, (char *) NAME); \ |
6cfc7210 NC |
2288 | } \ |
2289 | while (0) | |
35d965d5 | 2290 | |
d5b7b3ae RE |
2291 | /* For aliases of functions we use .thumb_set instead. */ |
2292 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2293 | do \ | |
2294 | { \ | |
91ea4f8d KG |
2295 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2296 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2297 | \ |
2298 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2299 | { \ | |
2300 | fprintf (FILE, "\t.thumb_set "); \ | |
2301 | assemble_name (FILE, LABEL1); \ | |
2302 | fprintf (FILE, ","); \ | |
2303 | assemble_name (FILE, LABEL2); \ | |
2304 | fprintf (FILE, "\n"); \ | |
2305 | } \ | |
2306 | else \ | |
2307 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2308 | } \ | |
2309 | while (0) | |
2310 | ||
fdc2d3b0 NC |
2311 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2312 | /* To support -falign-* switches we need to use .p2align so | |
2313 | that alignment directives in code sections will be padded | |
2314 | with no-op instructions, rather than zeroes. */ | |
2315 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ | |
2316 | if ((LOG) != 0) \ | |
2317 | { \ | |
2318 | if ((MAX_SKIP) == 0) \ | |
2319 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2320 | else \ | |
2321 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
2322 | (LOG), (MAX_SKIP)); \ | |
2323 | } | |
2324 | #endif | |
35d965d5 | 2325 | \f |
35d965d5 RS |
2326 | /* Only perform branch elimination (by making instructions conditional) if |
2327 | we're optimising. Otherwise it's of no use anyway. */ | |
d5b7b3ae RE |
2328 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2329 | if (TARGET_ARM && optimize) \ | |
2330 | arm_final_prescan_insn (INSN); \ | |
2331 | else if (TARGET_THUMB) \ | |
2332 | thumb_final_prescan_insn (INSN) | |
35d965d5 | 2333 | |
7bc7696c | 2334 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
d5b7b3ae RE |
2335 | (CODE == '@' || CODE == '|' \ |
2336 | || (TARGET_ARM && (CODE == '?')) \ | |
2337 | || (TARGET_THUMB && (CODE == '_'))) | |
6cfc7210 | 2338 | |
7bc7696c | 2339 | /* Output an operand of an instruction. */ |
35d965d5 | 2340 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2341 | arm_print_operand (STREAM, X, CODE) |
2342 | ||
7b8b8ade NC |
2343 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2344 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2345 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2346 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2347 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2348 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2349 | : 0)))) |
35d965d5 RS |
2350 | |
2351 | /* Output the address of an operand. */ | |
3cd45774 RE |
2352 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2353 | { \ | |
2354 | int is_minus = GET_CODE (X) == MINUS; \ | |
2355 | \ | |
2356 | if (GET_CODE (X) == REG) \ | |
2357 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2358 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2359 | { \ | |
2360 | rtx base = XEXP (X, 0); \ | |
2361 | rtx index = XEXP (X, 1); \ | |
2362 | HOST_WIDE_INT offset = 0; \ | |
2363 | if (GET_CODE (base) != REG) \ | |
2364 | { \ | |
2365 | /* Ensure that BASE is a register */ \ | |
2366 | /* (one of them must be). */ \ | |
2367 | rtx temp = base; \ | |
2368 | base = index; \ | |
2369 | index = temp; \ | |
2370 | } \ | |
2371 | switch (GET_CODE (index)) \ | |
2372 | { \ | |
2373 | case CONST_INT: \ | |
2374 | offset = INTVAL (index); \ | |
2375 | if (is_minus) \ | |
2376 | offset = -offset; \ | |
2377 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2378 | REGNO (base), offset); \ | |
2379 | break; \ | |
2380 | \ | |
2381 | case REG: \ | |
2382 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2383 | REGNO (base), is_minus ? "-" : "", \ | |
2384 | REGNO (index)); \ | |
2385 | break; \ | |
2386 | \ | |
2387 | case MULT: \ | |
2388 | case ASHIFTRT: \ | |
2389 | case LSHIFTRT: \ | |
2390 | case ASHIFT: \ | |
2391 | case ROTATERT: \ | |
2392 | { \ | |
2393 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2394 | REGNO (base), is_minus ? "-" : "", \ | |
2395 | REGNO (XEXP (index, 0))); \ | |
2396 | arm_print_operand (STREAM, index, 'S'); \ | |
2397 | fputs ("]", STREAM); \ | |
2398 | break; \ | |
2399 | } \ | |
2400 | \ | |
2401 | default: \ | |
2402 | abort(); \ | |
2403 | } \ | |
2404 | } \ | |
2405 | else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ | |
2406 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ | |
2407 | { \ | |
2408 | extern enum machine_mode output_memory_reference_mode; \ | |
2409 | \ | |
2410 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2411 | abort (); \ | |
2412 | \ | |
2413 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2414 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2415 | REGNO (XEXP (X, 0)), \ | |
2416 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2417 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
2418 | else \ | |
2419 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2420 | REGNO (XEXP (X, 0)), \ | |
2421 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2422 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
2423 | } \ | |
2424 | else if (GET_CODE (X) == PRE_MODIFY) \ | |
2425 | { \ | |
2426 | asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ | |
2427 | if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ | |
2428 | asm_fprintf (STREAM, "#%d]!", \ | |
2429 | INTVAL (XEXP (XEXP (X, 1), 1))); \ | |
2430 | else \ | |
2431 | asm_fprintf (STREAM, "%r]!", \ | |
2432 | REGNO (XEXP (XEXP (X, 1), 1))); \ | |
2433 | } \ | |
2434 | else if (GET_CODE (X) == POST_MODIFY) \ | |
2435 | { \ | |
2436 | asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ | |
2437 | if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ | |
2438 | asm_fprintf (STREAM, "#%d", \ | |
2439 | INTVAL (XEXP (XEXP (X, 1), 1))); \ | |
2440 | else \ | |
2441 | asm_fprintf (STREAM, "%r", \ | |
2442 | REGNO (XEXP (XEXP (X, 1), 1))); \ | |
2443 | } \ | |
2444 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2445 | } |
62dd06ea | 2446 | |
d5b7b3ae RE |
2447 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2448 | { \ | |
2449 | if (GET_CODE (X) == REG) \ | |
2450 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2451 | else if (GET_CODE (X) == POST_INC) \ | |
2452 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2453 | else if (GET_CODE (X) == PLUS) \ | |
2454 | { \ | |
2455 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2456 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2457 | REGNO (XEXP (X, 0)), \ | |
2458 | (int) INTVAL (XEXP (X, 1))); \ | |
2459 | else \ | |
2460 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2461 | REGNO (XEXP (X, 0)), \ | |
2462 | REGNO (XEXP (X, 1))); \ | |
2463 | } \ | |
2464 | else \ | |
2465 | output_addr_const (STREAM, X); \ | |
2466 | } | |
2467 | ||
2468 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2469 | if (TARGET_ARM) \ | |
2470 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ | |
2471 | else \ | |
2472 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
2473 | ||
6a5d7526 MS |
2474 | /* A C expression whose value is RTL representing the value of the return |
2475 | address for the frame COUNT steps up from the current frame. */ | |
2476 | ||
d5b7b3ae RE |
2477 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2478 | arm_return_addr (COUNT, FRAME) | |
2479 | ||
2480 | /* Mask of the bits in the PC that contain the real return address | |
2481 | when running in 26-bit mode. */ | |
2482 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2483 | |
2c849145 JM |
2484 | /* Pick up the return address upon entry to a procedure. Used for |
2485 | dwarf2 unwind information. This also enables the table driven | |
2486 | mechanism. */ | |
2c849145 JM |
2487 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2488 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2489 | ||
39950dff MS |
2490 | /* Used to mask out junk bits from the return address, such as |
2491 | processor state, interrupt status, condition codes and the like. */ | |
2492 | #define MASK_RETURN_ADDR \ | |
2493 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2494 | in 26 bit mode, the condition codes must be masked out of the \ | |
2495 | return address. This does not apply to ARM6 and later processors \ | |
2496 | when running in 32 bit mode. */ \ | |
fcd53748 JT |
2497 | ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ |
2498 | : (arm_arch4 || TARGET_THUMB) ? \ | |
2499 | (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
2500 | : arm_gen_return_addr_mask ()) | |
d5b7b3ae RE |
2501 | |
2502 | \f | |
2503 | /* Define the codes that are matched by predicates in arm.c */ | |
2504 | #define PREDICATE_CODES \ | |
2505 | {"s_register_operand", {SUBREG, REG}}, \ | |
b15bca31 | 2506 | {"arm_hard_register_operand", {REG}}, \ |
d5b7b3ae RE |
2507 | {"f_register_operand", {SUBREG, REG}}, \ |
2508 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
3b684012 RE |
2509 | {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |
2510 | {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
d5b7b3ae RE |
2511 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ |
2512 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
2513 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ | |
2514 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
2515 | {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ | |
2516 | {"offsettable_memory_operand", {MEM}}, \ | |
2517 | {"bad_signed_byte_operand", {MEM}}, \ | |
2518 | {"alignable_memory_operand", {MEM}}, \ | |
2519 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ | |
2520 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
2521 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ | |
2522 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ | |
2523 | {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ | |
2524 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ | |
2525 | {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ | |
2526 | {"load_multiple_operation", {PARALLEL}}, \ | |
2527 | {"store_multiple_operation", {PARALLEL}}, \ | |
2528 | {"equality_operator", {EQ, NE}}, \ | |
e45b72c4 RE |
2529 | {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ |
2530 | LTU, UNORDERED, ORDERED, UNLT, UNLE, \ | |
2531 | UNGE, UNGT}}, \ | |
d5b7b3ae RE |
2532 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2533 | {"const_shift_operand", {CONST_INT}}, \ | |
2534 | {"multi_register_push", {PARALLEL}}, \ | |
2535 | {"cc_register", {REG}}, \ | |
2536 | {"logical_binary_operator", {AND, IOR, XOR}}, \ | |
9b6b54e2 NC |
2537 | {"cirrus_register_operand", {REG}}, \ |
2538 | {"cirrus_fp_register", {REG}}, \ | |
2539 | {"cirrus_shift_const", {CONST_INT}}, \ | |
d5b7b3ae | 2540 | {"dominant_cc_register", {REG}}, |
71791e16 | 2541 | |
ad027eae RE |
2542 | /* Define this if you have special predicates that know special things |
2543 | about modes. Genrecog will warn about certain forms of | |
2544 | match_operand without a mode; if the operand predicate is listed in | |
2545 | SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ | |
2546 | #define SPECIAL_MODE_PREDICATES \ | |
2547 | "cc_register", "dominant_cc_register", | |
2548 | ||
88657302 | 2549 | #endif /* ! GCC_ARM_H */ |