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[thirdparty/gcc.git] / gcc / config / arm / arm.h
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f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
5b3e6663 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245
NC		 21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
39d14dda
KC		 23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
35fd3193 29/* The architecture define. */
78011587
PB		 30extern char arm_arch_name[];
31
e6471be6
NB		 32/* Target CPU builtins. */
33#define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
9b66ebb1
PB		 36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
61f0ccff 39 builtin_define ("__APCS_32__"); \
9b66ebb1 40 if (TARGET_THUMB) \
e6471be6 41 builtin_define ("__thumb__"); \
5b3e6663
PB		 42 if (TARGET_THUMB2) \
43 builtin_define ("__thumb2__"); \
e6471be6
NB		 44 \
45 if (TARGET_BIG_END) \
46 { \
47 builtin_define ("__ARMEB__"); \
48 if (TARGET_THUMB) \
49 builtin_define ("__THUMBEB__"); \
50 if (TARGET_LITTLE_WORDS) \
51 builtin_define ("__ARMWEL__"); \
52 } \
53 else \
54 { \
55 builtin_define ("__ARMEL__"); \
56 if (TARGET_THUMB) \
57 builtin_define ("__THUMBEL__"); \
58 } \
59 \
e6471be6
NB		 60 if (TARGET_SOFT_FLOAT) \
61 builtin_define ("__SOFTFP__"); \
62 \
9b66ebb1 63 if (TARGET_VFP) \
b5b620a4
JT		 64 builtin_define ("__VFP_FP__"); \
65 \
e6471be6
NB		 66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
2ad4dcf9 68 if (arm_cpp_interwork) \
e6471be6
NB		 69 builtin_define ("__THUMB_INTERWORK__"); \
70 \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
78011587
PB		 73 \
74 builtin_define (arm_arch_name); \
75 if (arm_arch_cirrus) \
76 builtin_define ("__MAVERICK__"); \
77 if (arm_arch_xscale) \
78 builtin_define ("__XSCALE__"); \
79 if (arm_arch_iwmmxt) \
80 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 81 if (TARGET_AAPCS_BASED) \
82 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 83 } while (0)
84
9b66ebb1
PB		 85/* The various ARM cores. */
86enum processor_type
87{
d98a72fd
RE		 88#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
89 IDENT,
9b66ebb1
PB		 90#include "arm-cores.def"
91#undef ARM_CORE
92 /* Used to indicate that no processor has been specified. */
93 arm_none
94};
95
78011587
PB		 96enum target_cpus
97{
d98a72fd
RE		 98#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
99 TARGET_CPU_##IDENT,
78011587
PB		 100#include "arm-cores.def"
101#undef ARM_CORE
102 TARGET_CPU_generic
103};
104
9b66ebb1
PB		 105/* The processor for which instructions should be scheduled. */
106extern enum processor_type arm_tune;
107
d5b7b3ae 108typedef enum arm_cond_code
89c7ca52
RE		 109{
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 112}
113arm_cc;
6cfc7210 114
d5b7b3ae 115extern arm_cc arm_current_cc;
ff9940b0 116
d5b7b3ae 117#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 118
6cfc7210
NC		 119extern int arm_target_label;
120extern int arm_ccfsm_state;
e2500fed 121extern GTY(()) rtx arm_target_insn;
d5b7b3ae 122/* Define the information needed to generate branch insns. This is
e2500fed
GK		 123 stored from the compare operation. */
124extern GTY(()) rtx arm_compare_op0;
125extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 126/* The label of the current constant pool. */
e2500fed 127extern rtx pool_vector_label;
d5b7b3ae 128/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 129 is not needed. */
d5b7b3ae 130extern int return_used_this_function;
e2500fed
GK		 131/* Used to produce AOF syntax assembler. */
132extern GTY(()) rtx aof_pic_label;
35d965d5 133\f
d6b4baa4 134/* Just in case configure has failed to define anything. */
7a801826
RE		 135#ifndef TARGET_CPU_DEFAULT
136#define TARGET_CPU_DEFAULT TARGET_CPU_generic
137#endif
138
7a801826 139
5742588d 140#undef CPP_SPEC
78011587 141#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 142%{msoft-float:%{mhard-float: \
143 %e-msoft-float and -mhard_float may not be used together}} \
144%{mbig-endian:%{mlittle-endian: \
145 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 146
be393ecf 147#ifndef CC1_SPEC
dfa08768 148#define CC1_SPEC ""
be393ecf 149#endif
7a801826
RE		 150
151/* This macro defines names of additional specifications to put in the specs
152 that can be used in various specifications like CC1_SPEC. Its definition
153 is an initializer with a subgrouping for each command option.
154
155 Each subgrouping contains a string constant, that defines the
4f448245 156 specification name, and a string constant that used by the GCC driver
7a801826
RE		 157 program.
158
159 Do not define this macro if it does not need to do anything. */
160#define EXTRA_SPECS \
38fc909b 161 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 162 SUBTARGET_EXTRA_SPECS
163
914a3b8c 164#ifndef SUBTARGET_EXTRA_SPECS
7a801826 165#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 166#endif
167
6cfc7210 168#ifndef SUBTARGET_CPP_SPEC
38fc909b 169#define SUBTARGET_CPP_SPEC ""
6cfc7210 170#endif
35d965d5
RS		 171\f
172/* Run-time Target Specification. */
ff9940b0 173#ifndef TARGET_VERSION
6cfc7210 174#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 175#endif
35d965d5 176
9b66ebb1 177#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 178/* Use hardware floating point instructions. */
179#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
180/* Use hardware floating point calling convention. */
181#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 182#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
183#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
184#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef 185#define TARGET_IWMMXT (arm_arch_iwmmxt)
5b3e6663
PB		 186#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
187#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 188#define TARGET_ARM (! TARGET_THUMB)
189#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 190#define TARGET_BACKTRACE (leaf_function_p () \
191 ? TARGET_TPCS_LEAF_FRAME \
192 : TARGET_TPCS_FRAME)
fdd695fd 193#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 194#define TARGET_AAPCS_BASED \
195 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 196
d3585b76
DJ		 197#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
198#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
199
5b3e6663
PB		 200/* Only 16-bit thumb code. */
201#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
202/* Arm or Thumb-2 32-bit code. */
203#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
204/* 32-bit Thumb-2 code. */
205#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
206
207/* "DSP" multiply instructions, eg. SMULxy. */
208#define TARGET_DSP_MULTIPLY \
209 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
210/* Integer SIMD instructions, and extend-accumulate instructions. */
211#define TARGET_INT_SIMD \
212 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
213
214/* We could use unified syntax for arm mode, but for now we just use it
215 for Thumb-2. */
216#define TARGET_UNIFIED_ASM TARGET_THUMB2
217
218
b3f8d95d
MM		 219/* True iff the full BPABI is being used. If TARGET_BPABI is true,
220 then TARGET_AAPCS_BASED must be true -- but the converse does not
221 hold. TARGET_BPABI implies the use of the BPABI runtime library,
222 etc., in addition to just the AAPCS calling conventions. */
223#ifndef TARGET_BPABI
224#define TARGET_BPABI false
f676971a 225#endif
b3f8d95d 226
7816bea0
DJ		 227/* Support for a compile-time default CPU, et cetera. The rules are:
228 --with-arch is ignored if -march or -mcpu are specified.
229 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
230 by --with-arch.
231 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
232 by -march).
9b66ebb1
PB		 233 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
234 specified.
5848830f
PB		 235 --with-fpu is ignored if -mfpu is specified.
236 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 237#define OPTION_DEFAULT_SPECS \
238 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
239 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
240 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 241 {"float", \
242 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f 243 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
3cf94279
PB		 244 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
245 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
7816bea0 246
9b66ebb1
PB		 247/* Which floating point model to use. */
248enum arm_fp_model
249{
250 ARM_FP_MODEL_UNKNOWN,
251 /* FPA model (Hardware or software). */
252 ARM_FP_MODEL_FPA,
253 /* Cirrus Maverick floating point model. */
254 ARM_FP_MODEL_MAVERICK,
255 /* VFP floating point model. */
256 ARM_FP_MODEL_VFP
257};
258
259extern enum arm_fp_model arm_fp_model;
260
261/* Which floating point hardware is available. Also update
262 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 263enum fputype
24f0c1b4 264{
9b66ebb1
PB		 265 /* No FP hardware. */
266 FPUTYPE_NONE,
29ad9694
RE		 267 /* Full FPA support. */
268 FPUTYPE_FPA,
269 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
270 FPUTYPE_FPA_EMU2,
271 /* Emulated FPA hardware, Issue 3 emulator. */
272 FPUTYPE_FPA_EMU3,
273 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 274 FPUTYPE_MAVERICK,
275 /* VFP. */
276 FPUTYPE_VFP
24f0c1b4
RE		 277};
278
279/* Recast the floating point class to be the floating point attribute. */
29ad9694 280#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 281
71791e16 282/* What type of floating point to tune for */
29ad9694 283extern enum fputype arm_fpu_tune;
24f0c1b4 284
71791e16 285/* What type of floating point instructions are available */
29ad9694 286extern enum fputype arm_fpu_arch;
71791e16 287
9b66ebb1
PB		 288enum float_abi_type
289{
290 ARM_FLOAT_ABI_SOFT,
291 ARM_FLOAT_ABI_SOFTFP,
292 ARM_FLOAT_ABI_HARD
293};
294
295extern enum float_abi_type arm_float_abi;
296
3d8532aa
PB		 297#ifndef TARGET_DEFAULT_FLOAT_ABI
298#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
299#endif
300
5848830f
PB		 301/* Which ABI to use. */
302enum arm_abi_type
303{
304 ARM_ABI_APCS,
305 ARM_ABI_ATPCS,
306 ARM_ABI_AAPCS,
077fc835
KH		 307 ARM_ABI_IWMMXT,
308 ARM_ABI_AAPCS_LINUX
5848830f
PB		 309};
310
311extern enum arm_abi_type arm_abi;
312
313#ifndef ARM_DEFAULT_ABI
314#define ARM_DEFAULT_ABI ARM_ABI_APCS
315#endif
316
d3585b76
DJ		 317/* Which thread pointer access sequence to use. */
318enum arm_tp_type {
319 TP_AUTO,
320 TP_SOFT,
321 TP_CP15
322};
323
324extern enum arm_tp_type target_thread_pointer;
325
9b66ebb1
PB		 326/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
327extern int arm_arch3m;
11c1a207 328
9b66ebb1 329/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 330extern int arm_arch4;
331
68d560d4
RE		 332/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
333extern int arm_arch4t;
334
9b66ebb1 335/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 336extern int arm_arch5;
337
9b66ebb1 338/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 339extern int arm_arch5e;
340
9b66ebb1
PB		 341/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
342extern int arm_arch6;
343
5b3e6663
PB		 344/* Nonzero if instructions not present in the 'M' profile can be used. */
345extern int arm_arch_notm;
346
f5a1b0d2
NC		 347/* Nonzero if this chip can benefit from load scheduling. */
348extern int arm_ld_sched;
349
0616531f
RE		 350/* Nonzero if generating thumb code. */
351extern int thumb_code;
352
f5a1b0d2 353/* Nonzero if this chip is a StrongARM. */
abac3b49 354extern int arm_tune_strongarm;
f5a1b0d2 355
9b6b54e2 356/* Nonzero if this chip is a Cirrus variant. */
78011587 357extern int arm_arch_cirrus;
9b6b54e2 358
5a9335ef
NC		 359/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
360extern int arm_arch_iwmmxt;
361
d19fb8e3 362/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 363extern int arm_arch_xscale;
364
abac3b49 365/* Nonzero if tuning for XScale. */
4b3c2e48 366extern int arm_tune_xscale;
d19fb8e3 367
abac3b49
RE		 368/* Nonzero if tuning for stores via the write buffer. */
369extern int arm_tune_wbuf;
f5a1b0d2 370
2ad4dcf9 371/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 372 preprocessor.
2ad4dcf9
RE		 373 XXX This is a bit of a hack, it's intended to help work around
374 problems in GLD which doesn't understand that armv5t code is
375 interworking clean. */
376extern int arm_cpp_interwork;
377
5b3e6663
PB		 378/* Nonzero if chip supports Thumb 2. */
379extern int arm_arch_thumb2;
380
381/* Nonzero if chip supports integer division instruction. */
382extern int arm_arch_hwdiv;
383
2ce9c1b9 384#ifndef TARGET_DEFAULT
c54c7322 385#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 386#endif
35d965d5 387
11c1a207
RE		 388/* The frame pointer register used in gcc has nothing to do with debugging;
389 that is controlled by the APCS-FRAME option. */
d5b7b3ae 390#define CAN_DEBUG_WITHOUT_FP
35d965d5 391
11c1a207 392#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 393
394/* Nonzero if PIC code requires explicit qualifiers to generate
395 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 396 Subtargets can override these if required. */
397#ifndef NEED_GOT_RELOC
398#define NEED_GOT_RELOC 0
399#endif
400#ifndef NEED_PLT_RELOC
401#define NEED_PLT_RELOC 0
e2723c62 402#endif
84306176
PB		 403
404/* Nonzero if we need to refer to the GOT with a PC-relative
405 offset. In other words, generate
406
f676971a 407 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 408
409 rather than
410
411 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
412
f676971a 413 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 414 override this if required. */
415#ifndef GOT_PCREL
416#define GOT_PCREL 1
417#endif
35d965d5
RS		 418\f
419/* Target machine storage Layout. */
420
ff9940b0
RE		 421
422/* Define this macro if it is advisable to hold scalars in registers
423 in a wider mode than that declared by the program. In such cases,
424 the value is constrained to be within the bounds of the declared
425 type, but kept valid in the wider mode. The signedness of the
426 extension may differ from that of the type. */
427
428/* It is far faster to zero extend chars than to sign extend them */
429
6cfc7210 430#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 431 if (GET_MODE_CLASS (MODE) == MODE_INT \
432 && GET_MODE_SIZE (MODE) < 4) \
433 { \
434 if (MODE == QImode) \
435 UNSIGNEDP = 1; \
436 else if (MODE == HImode) \
61f0ccff 437 UNSIGNEDP = 1; \
2ce9c1b9 438 (MODE) = SImode; \
ff9940b0
RE		 439 }
440
d4453b7a 441#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
866af8a9
JB		 442 if ((GET_MODE_CLASS (MODE) == MODE_INT \
443 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
444 && GET_MODE_SIZE (MODE) < 4) \
445 (MODE) = SImode; \
d4453b7a 446
35d965d5
RS		 447/* Define this if most significant bit is lowest numbered
448 in instructions that operate on numbered bit-fields. */
449#define BITS_BIG_ENDIAN 0
450
f676971a 451/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 452 Most ARM processors are run in little endian mode, so that is the default.
453 If you want to have it run-time selectable, change the definition in a
454 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 455#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 456
457/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 458 numbered.
459 This is always false, even when in big-endian mode. */
ddee6aba
RE		 460#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
461
462/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
463 on processor pre-defineds when compiling libgcc2.c. */
464#if defined(__ARMEB__) && !defined(__ARMWEL__)
465#define LIBGCC2_WORDS_BIG_ENDIAN 1
466#else
467#define LIBGCC2_WORDS_BIG_ENDIAN 0
468#endif
35d965d5 469
11c1a207 470/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 471 The rules are different based on whether or not we use FPA-format,
472 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 473#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 474
35d965d5
RS		 475#define UNITS_PER_WORD 4
476
5848830f 477/* True if natural alignment is used for doubleword types. */
b6685939
PB		 478#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
479
5848830f 480#define DOUBLEWORD_ALIGNMENT 64
35d965d5 481
5848830f 482#define PARM_BOUNDARY 32
5a9335ef 483
5848830f 484#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 485
5848830f
PB		 486#define PREFERRED_STACK_BOUNDARY \
487 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 488
35d965d5
RS		 489#define FUNCTION_BOUNDARY 32
490
92928d71
AO		 491/* The lowest bit is used to indicate Thumb-mode functions, so the
492 vbit must go into the delta field of pointers to member
493 functions. */
494#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
495
35d965d5
RS		 496#define EMPTY_FIELD_BOUNDARY 32
497
5848830f 498#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 499
27847754
NC		 500/* XXX Blah -- this macro is used directly by libobjc. Since it
501 supports no vector modes, cut out the complexity and fall back
502 on BIGGEST_FIELD_ALIGNMENT. */
503#ifdef IN_TARGET_LIBS
8fca31a2 504#define BIGGEST_FIELD_ALIGNMENT 64
27847754 505#endif
5a9335ef 506
ff9940b0 507/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 508#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 509
d19fb8e3 510#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f 511 ((TREE_CODE (EXP) == STRING_CST \
36b15ad0 512 && !optimize_size \
5848830f
PB		 513 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
514 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 515
723ae7c1
NC		 516/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
517 value set in previous versions of this toolchain was 8, which produces more
518 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 519 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 520 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 521 0020D) page 2-20 says "Structures are aligned on word boundaries".
522 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 523#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
524extern int arm_structure_size_boundary;
723ae7c1 525
4912a07c 526/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 527 particular arm target wants to change the default value it should change
6bc82793 528 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 529 for an example of this. */
530#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
531#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 532#endif
2a5307b1 533
825dda42 534/* Nonzero if move instructions will actually fail to work
ff9940b0 535 when given unaligned data. */
35d965d5 536#define STRICT_ALIGNMENT 1
b6685939
PB		 537
538/* wchar_t is unsigned under the AAPCS. */
539#ifndef WCHAR_TYPE
540#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
541
542#define WCHAR_TYPE_SIZE BITS_PER_WORD
543#endif
544
545#ifndef SIZE_TYPE
546#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
547#endif
d81d0bdd 548
077fc835
KH		 549#ifndef PTRDIFF_TYPE
550#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
551#endif
552
d81d0bdd
PB		 553/* AAPCS requires that structure alignment is affected by bitfields. */
554#ifndef PCC_BITFIELD_TYPE_MATTERS
555#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
556#endif
557
35d965d5
RS		 558\f
559/* Standard register usage. */
560
561/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
562 (S - saved over call).
563
564 r0 * argument word/integer result
565 r1-r3 argument word
566
567 r4-r8 S register variable
568 r9 S (rfp) register variable (real frame pointer)
f676971a 569
f5a1b0d2 570 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 571 r11 F S (fp) argument pointer
572 r12 (ip) temp workspace
573 r13 F S (sp) lower end of current stack frame
574 r14 (lr) link address/workspace
575 r15 F (pc) program counter
576
577 f0 floating point result
578 f1-f3 floating point scratch
579
580 f4-f7 S floating point variable
581
ff9940b0
RE		 582 cc This is NOT a real register, but is used internally
583 to represent things that use or set the condition
584 codes.
585 sfp This isn't either. It is used during rtl generation
586 since the offset between the frame pointer and the
587 auto's isn't known until after register allocation.
588 afp Nor this, we only need this because of non-local
589 goto. Without it fp appears to be used and the
590 elimination code won't get rid of sfp. It tracks
591 fp exactly at all times.
592
35d965d5
RS		 593 *: See CONDITIONAL_REGISTER_USAGE */
594
9b6b54e2
NC		 595/*
596 mvf0 Cirrus floating point result
597 mvf1-mvf3 Cirrus floating point scratch
598 mvf4-mvf15 S Cirrus floating point variable. */
599
9b66ebb1
PB		 600/* s0-s15 VFP scratch (aka d0-d7).
601 s16-s31 S VFP variable (aka d8-d15).
602 vfpcc Not a real register. Represents the VFP condition
603 code flags. */
604
ff9940b0
RE		 605/* The stack backtrace structure is as follows:
606 fp points to here: | save code pointer | [fp]
607 | return link value | [fp, #-4]
608 | return sp value | [fp, #-8]
609 | return fp value | [fp, #-12]
610 [| saved r10 value |]
611 [| saved r9 value |]
612 [| saved r8 value |]
613 [| saved r7 value |]
614 [| saved r6 value |]
615 [| saved r5 value |]
616 [| saved r4 value |]
617 [| saved r3 value |]
618 [| saved r2 value |]
619 [| saved r1 value |]
620 [| saved r0 value |]
621 [| saved f7 value |] three words
622 [| saved f6 value |] three words
623 [| saved f5 value |] three words
624 [| saved f4 value |] three words
625 r0-r3 are not normally saved in a C function. */
626
35d965d5
RS		 627/* 1 for registers that have pervasive standard uses
628 and are not available for the register allocator. */
9b66ebb1
PB		 629#define FIXED_REGISTERS \
630{ \
631 0,0,0,0,0,0,0,0, \
632 0,0,0,0,0,1,0,1, \
633 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 634 1,1,1, \
635 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 636 1,1,1,1,1,1,1,1, \
637 1,1,1,1,1,1,1,1, \
638 1,1,1,1,1,1,1,1, \
639 1,1,1,1, \
640 1,1,1,1,1,1,1,1, \
641 1,1,1,1,1,1,1,1, \
642 1,1,1,1,1,1,1,1, \
643 1,1,1,1,1,1,1,1, \
644 1 \
35d965d5
RS		 645}
646
647/* 1 for registers not available across function calls.
648 These must include the FIXED_REGISTERS and also any
649 registers that can be used without being saved.
650 The latter must include the registers where values are returned
651 and the register where structure-value addresses are passed.
ff9940b0 652 Aside from that, you can include as many other registers as you like.
f676971a 653 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 654 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 655#define CALL_USED_REGISTERS \
656{ \
657 1,1,1,1,0,0,0,0, \
d5b7b3ae 658 0,0,0,0,1,1,1,1, \
ff9940b0 659 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 660 1,1,1, \
661 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 662 1,1,1,1,1,1,1,1, \
663 1,1,1,1,1,1,1,1, \
664 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 665 1,1,1,1, \
666 1,1,1,1,1,1,1,1, \
667 1,1,1,1,1,1,1,1, \
668 1,1,1,1,1,1,1,1, \
669 1,1,1,1,1,1,1,1, \
670 1 \
35d965d5
RS		 671}
672
6cc8c0b3
NC		 673#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
674#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
675#endif
676
d5b7b3ae
RE		 677#define CONDITIONAL_REGISTER_USAGE \
678{ \
4b02997f
NC		 679 int regno; \
680 \
5b3e6663 681 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
d5b7b3ae 682 { \
9b66ebb1
PB		 683 for (regno = FIRST_FPA_REGNUM; \
684 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 685 fixed_regs[regno] = call_used_regs[regno] = 1; \
686 } \
9b6b54e2 687 \
c769a35d
RE		 688 if (TARGET_THUMB && optimize_size) \
689 { \
690 /* When optimizing for size, it's better not to use \
691 the HI regs, because of the overhead of stacking \
d6b4baa4 692 them. */ \
5b3e6663 693 /* ??? Is this still true for thumb2? */ \
c769a35d
RE		 694 for (regno = FIRST_HI_REGNUM; \
695 regno <= LAST_HI_REGNUM; ++regno) \
696 fixed_regs[regno] = call_used_regs[regno] = 1; \
697 } \
698 \
fb14bc89
RE		 699 /* The link register can be clobbered by any branch insn, \
700 but we have no way to track that at present, so mark \
701 it as unavailable. */ \
5b3e6663 702 if (TARGET_THUMB1) \
fb14bc89
RE		 703 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
704 \
5b3e6663 705 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
9b6b54e2 706 { \
9b66ebb1 707 if (TARGET_MAVERICK) \
9b6b54e2 708 { \
9b66ebb1
PB		 709 for (regno = FIRST_FPA_REGNUM; \
710 regno <= LAST_FPA_REGNUM; ++ regno) \
711 fixed_regs[regno] = call_used_regs[regno] = 1; \
712 for (regno = FIRST_CIRRUS_FP_REGNUM; \
713 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
714 { \
715 fixed_regs[regno] = 0; \
716 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
717 } \
718 } \
719 if (TARGET_VFP) \
720 { \
721 for (regno = FIRST_VFP_REGNUM; \
722 regno <= LAST_VFP_REGNUM; ++ regno) \
723 { \
724 fixed_regs[regno] = 0; \
725 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
726 } \
9b6b54e2
NC		 727 } \
728 } \
729 \
5a9335ef
NC		 730 if (TARGET_REALLY_IWMMXT) \
731 { \
732 regno = FIRST_IWMMXT_GR_REGNUM; \
733 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
734 and wCG1 as call-preserved registers. The 2002/11/21 \
735 revision changed this so that all wCG registers are \
736 scratch registers. */ \
737 for (regno = FIRST_IWMMXT_GR_REGNUM; \
738 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 739 fixed_regs[regno] = 0; \
5a9335ef
NC		 740 /* The XScale ABI has wR0 - wR9 as scratch registers, \
741 the rest as call-preserved registers. */ \
742 for (regno = FIRST_IWMMXT_REGNUM; \
743 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
744 { \
745 fixed_regs[regno] = 0; \
746 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
747 } \
748 } \
749 \
fc555370 750 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 751 { \
752 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
753 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
754 } \
755 else if (TARGET_APCS_STACK) \
756 { \
757 fixed_regs[10] = 1; \
758 call_used_regs[10] = 1; \
759 } \
a2503645
RS		 760 /* -mcaller-super-interworking reserves r11 for calls to \
761 _interwork_r11_call_via_rN(). Making the register global \
762 is an easy way of ensuring that it remains valid for all \
763 calls. */ \
685c9c11 764 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
c54c7322 765 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
d5b7b3ae
RE		 766 { \
767 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
768 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 769 if (TARGET_CALLER_INTERWORKING) \
770 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 771 } \
772 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 773}
f676971a 774
6bc82793 775/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 776 by asm_fprintf:
777 %@ prints out ASM_COMMENT_START
778 %r prints out REGISTER_PREFIX reg_names[arg] */
779#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
780 case '@': \
781 fputs (ASM_COMMENT_START, FILE); \
782 break; \
783 \
784 case 'r': \
785 fputs (REGISTER_PREFIX, FILE); \
786 fputs (reg_names [va_arg (ARGS, int)], FILE); \
787 break;
788
d5b7b3ae 789/* Round X up to the nearest word. */
0c2ca901 790#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 791
6cfc7210 792/* Convert fron bytes to ints. */
e9d7b180 793#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 794
9b66ebb1
PB		 795/* The number of (integer) registers required to hold a quantity of type MODE.
796 Also used for VFP registers. */
e9d7b180
JD		 797#define ARM_NUM_REGS(MODE) \
798 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 799
800/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 801#define ARM_NUM_REGS2(MODE, TYPE) \
802 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 803 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 804
805/* The number of (integer) argument register available. */
d5b7b3ae 806#define NUM_ARG_REGS 4
6cfc7210 807
093354e0 808/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 809#define ARG_REGISTER(N) (N - 1)
6cfc7210 810
d5b7b3ae
RE		 811/* Specify the registers used for certain standard purposes.
812 The values of these macros are register numbers. */
35d965d5 813
d5b7b3ae
RE		 814/* The number of the last argument register. */
815#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 816
c769a35d
RE		 817/* The numbers of the Thumb register ranges. */
818#define FIRST_LO_REGNUM 0
6d3d9133 819#define LAST_LO_REGNUM 7
c769a35d
RE		 820#define FIRST_HI_REGNUM 8
821#define LAST_HI_REGNUM 11
6d3d9133 822
617a1b71 823#ifndef TARGET_UNWIND_INFO
c9ca9b88
PB		 824/* We use sjlj exceptions for backwards compatibility. */
825#define MUST_USE_SJLJ_EXCEPTIONS 1
617a1b71
PB		 826#endif
827
c9ca9b88
PB		 828/* We can generate DWARF2 Unwind info, even though we don't use it. */
829#define DWARF2_UNWIND_INFO 1
f676971a 830
c9ca9b88
PB		 831/* Use r0 and r1 to pass exception handling information. */
832#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
833
6d3d9133 834/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 835#define ARM_EH_STACKADJ_REGNUM 2
836#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 837
d5b7b3ae
RE		 838/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
839 as an invisible last argument (possible since varargs don't exist in
840 Pascal), so the following is not true. */
5b3e6663 841#define STATIC_CHAIN_REGNUM 12
35d965d5 842
d5b7b3ae
RE		 843/* Define this to be where the real frame pointer is if it is not possible to
844 work out the offset between the frame pointer and the automatic variables
845 until after register allocation has taken place. FRAME_POINTER_REGNUM
846 should point to a special register that we will make sure is eliminated.
847
848 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 849 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 850 as base register for addressing purposes. (See comments in
851 find_reloads_address()). But - the Thumb does not allow high registers,
852 including r11, to be used as base address registers. Hence our problem.
853
854 The solution used here, and in the old thumb port is to use r7 instead of
855 r11 as the hard frame pointer and to have special code to generate
856 backtrace structures on the stack (if required to do so via a command line
6bc82793 857 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 858 pointer. */
859#define ARM_HARD_FRAME_POINTER_REGNUM 11
860#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 861
b15bca31
RE		 862#define HARD_FRAME_POINTER_REGNUM \
863 (TARGET_ARM \
864 ? ARM_HARD_FRAME_POINTER_REGNUM \
865 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 866
b15bca31 867#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 868
b15bca31
RE		 869/* Register to use for pushing function arguments. */
870#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 871
872/* ARM floating pointer registers. */
9b66ebb1
PB		 873#define FIRST_FPA_REGNUM 16
874#define LAST_FPA_REGNUM 23
2fa330b2
PB		 875#define IS_FPA_REGNUM(REGNUM) \
876 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 877
5a9335ef
NC		 878#define FIRST_IWMMXT_GR_REGNUM 43
879#define LAST_IWMMXT_GR_REGNUM 46
880#define FIRST_IWMMXT_REGNUM 47
881#define LAST_IWMMXT_REGNUM 62
882#define IS_IWMMXT_REGNUM(REGNUM) \
883 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
884#define IS_IWMMXT_GR_REGNUM(REGNUM) \
885 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
886
35d965d5 887/* Base register for access to local variables of the function. */
ff9940b0
RE		 888#define FRAME_POINTER_REGNUM 25
889
d5b7b3ae
RE		 890/* Base register for access to arguments of the function. */
891#define ARG_POINTER_REGNUM 26
62b10bbc 892
9b6b54e2
NC		 893#define FIRST_CIRRUS_FP_REGNUM 27
894#define LAST_CIRRUS_FP_REGNUM 42
895#define IS_CIRRUS_REGNUM(REGNUM) \
896 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
897
9b66ebb1
PB		 898#define FIRST_VFP_REGNUM 63
899#define LAST_VFP_REGNUM 94
900#define IS_VFP_REGNUM(REGNUM) \
901 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
902
6f8c9bd1
NC		 903/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
904/* + 16 Cirrus registers take us up to 43. */
5a9335ef 905/* Intel Wireless MMX Technology registers add 16 + 4 more. */
9b66ebb1
PB		 906/* VFP adds 32 + 1 more. */
907#define FIRST_PSEUDO_REGISTER 96
62b10bbc 908
2fa330b2
PB		 909#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
910
35d965d5
RS		 911/* Value should be nonzero if functions must have frame pointers.
912 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 913 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 914 If we have to have a frame pointer we might as well make use of it.
915 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 916 functions, or simple tail call functions. */
a15900b5
DJ		 917
918#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
919#define SUBTARGET_FRAME_POINTER_REQUIRED 0
920#endif
921
7b8b8ade
NC		 922#define FRAME_POINTER_REQUIRED \
923 (current_function_has_nonlocal_label \
a15900b5 924 || SUBTARGET_FRAME_POINTER_REQUIRED \
d5b7b3ae 925 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 926
d5b7b3ae
RE		 927/* Return number of consecutive hard regs needed starting at reg REGNO
928 to hold something of mode MODE.
929 This is ordinarily the length in words of a value of mode MODE
930 but can be less for certain modes in special long registers.
35d965d5 931
3b684012 932 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 933 mode. */
934#define HARD_REGNO_NREGS(REGNO, MODE) \
5b3e6663 935 ((TARGET_32BIT \
9b66ebb1 936 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 937 && REGNO != FRAME_POINTER_REGNUM \
938 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 939 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 940 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 941
4b02997f 942/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 943#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 944 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 945
d5b7b3ae
RE		 946/* Value is 1 if it is a good idea to tie two pseudo registers
947 when one has mode MODE1 and one has mode MODE2.
948 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
949 for any hard reg, then this must be 0 for correct output. */
950#define MODES_TIEABLE_P(MODE1, MODE2) \
951 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 952
5a9335ef 953#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 954 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 955
35d965d5 956/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 957 since no saving is required (though calls clobber it) and it never contains
958 function parameters. It is quite good to use lr since other calls may
f676971a 959 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 960 least likely to contain a function parameter; in addition results are
d5b7b3ae 961 returned in r0. */
9b66ebb1 962
ff73fb53 963#define REG_ALLOC_ORDER \
35d965d5 964{ \
ff73fb53
NC		 965 3, 2, 1, 0, 12, 14, 4, 5, \
966 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0 967 16, 17, 18, 19, 20, 21, 22, 23, \
9b6b54e2
NC		 968 27, 28, 29, 30, 31, 32, 33, 34, \
969 35, 36, 37, 38, 39, 40, 41, 42, \
5a9335ef
NC		 970 43, 44, 45, 46, 47, 48, 49, 50, \
971 51, 52, 53, 54, 55, 56, 57, 58, \
972 59, 60, 61, 62, \
9b66ebb1
PB		 973 24, 25, 26, \
974 78, 77, 76, 75, 74, 73, 72, 71, \
975 70, 69, 68, 67, 66, 65, 64, 63, \
976 79, 80, 81, 82, 83, 84, 85, 86, \
977 87, 88, 89, 90, 91, 92, 93, 94, \
978 95 \
35d965d5 979}
9338ffe6
PB		 980
981/* Interrupt functions can only use registers that have already been
982 saved by the prologue, even if they would normally be
983 call-clobbered. */
984#define HARD_REGNO_RENAME_OK(SRC, DST) \
985 (! IS_INTERRUPT (cfun->machine->func_type) || \
986 regs_ever_live[DST])
35d965d5
RS		 987\f
988/* Register and constant classes. */
989
3b684012 990/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 991 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 992enum reg_class
993{
994 NO_REGS,
3b684012 995 FPA_REGS,
9b6b54e2 996 CIRRUS_REGS,
9b66ebb1 997 VFP_REGS,
5a9335ef
NC		 998 IWMMXT_GR_REGS,
999 IWMMXT_REGS,
d5b7b3ae
RE		 1000 LO_REGS,
1001 STACK_REG,
1002 BASE_REGS,
1003 HI_REGS,
1004 CC_REG,
9b66ebb1 1005 VFPCC_REG,
35d965d5
RS		 1006 GENERAL_REGS,
1007 ALL_REGS,
1008 LIM_REG_CLASSES
1009};
1010
1011#define N_REG_CLASSES (int) LIM_REG_CLASSES
1012
d6b4baa4 1013/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1014#define REG_CLASS_NAMES \
1015{ \
1016 "NO_REGS", \
3b684012 1017 "FPA_REGS", \
9b6b54e2 1018 "CIRRUS_REGS", \
9b66ebb1 1019 "VFP_REGS", \
5a9335ef
NC		 1020 "IWMMXT_GR_REGS", \
1021 "IWMMXT_REGS", \
d5b7b3ae
RE		 1022 "LO_REGS", \
1023 "STACK_REG", \
1024 "BASE_REGS", \
1025 "HI_REGS", \
1026 "CC_REG", \
5384443a 1027 "VFPCC_REG", \
35d965d5
RS		 1028 "GENERAL_REGS", \
1029 "ALL_REGS", \
1030}
1031
1032/* Define which registers fit in which classes.
1033 This is an initializer for a vector of HARD_REG_SET
1034 of length N_REG_CLASSES. */
9b66ebb1
PB		 1035#define REG_CLASS_CONTENTS \
1036{ \
1037 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1038 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1039 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1040 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1041 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1042 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1043 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1044 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1045 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1046 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1047 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1048 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1049 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1050 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1051}
4b02997f 1052
35d965d5
RS		 1053/* The same information, inverted:
1054 Return the class number of the smallest class containing
1055 reg number REGNO. This could be a conditional expression
1056 or could index an array. */
d5b7b3ae 1057#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1058
9b66ebb1 1059/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1060 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1061 were set. */
75d2580c
RE		 1062#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1063 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1064 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1065 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1066 : 0)
75d2580c 1067
cc81dde8
PB		 1068/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1069 using r0-r4 for function arguments, r7 for the stack frame and don't
1070 have enough left over to do doubleword arithmetic. */
1071#define CLASS_LIKELY_SPILLED_P(CLASS) \
1072 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1073 || (CLASS) == CC_REG)
f676971a 1074
35d965d5 1075/* The class value for index registers, and the one for base regs. */
5b3e6663
PB		 1076#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1077#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1078
b93a0fe6 1079/* For the Thumb the high registers cannot be used as base registers
6bc82793 1080 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1081 mode, then we must be conservative. */
3dcc68a4 1082#define MODE_BASE_REG_CLASS(MODE) \
5b3e6663 1083 (TARGET_32BIT ? GENERAL_REGS : \
888d2cd6
DJ		 1084 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1085
1086/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1087 instead of BASE_REGS. */
1088#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1089
d5b7b3ae
RE		 1090/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1091 registers explicitly used in the rtl to be used as spill registers
1092 but prevents the compiler from extending the lifetime of these
d6b4baa4 1093 registers. */
5b3e6663 1094#define SMALL_REGISTER_CLASSES TARGET_THUMB1
35d965d5 1095
35d965d5
RS		 1096/* Given an rtx X being reloaded into a reg required to be
1097 in class CLASS, return the class of reg to actually use.
5b3e6663
PB		 1098 In general this is just CLASS, but for the Thumb core registers and
1099 immediate constants we prefer a LO_REGS class or a subset. */
1100#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1101 (TARGET_ARM ? (CLASS) : \
1102 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1103 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
d5b7b3ae
RE		 1104
1105/* Must leave BASE_REGS reloads alone */
1106#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1107 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1108 ? ((true_regnum (X) == -1 ? LO_REGS \
1109 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1110 : NO_REGS)) \
1111 : NO_REGS)
1112
1113#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1114 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1115 ? ((true_regnum (X) == -1 ? LO_REGS \
1116 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1117 : NO_REGS)) \
1118 : NO_REGS)
35d965d5 1119
ff9940b0
RE		 1120/* Return the register class of a scratch register needed to copy IN into
1121 or out of a register in CLASS in MODE. If it can be done directly,
1122 NO_REGS is returned. */
d5b7b3ae 1123#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1124 /* Restrict which direct reloads are allowed for VFP regs. */ \
1125 ((TARGET_VFP && TARGET_HARD_FLOAT \
1126 && (CLASS) == VFP_REGS) \
1127 ? vfp_secondary_reload_class (MODE, X) \
5b3e6663 1128 : TARGET_32BIT \
9b66ebb1 1129 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1130 ? GENERAL_REGS : NO_REGS) \
1131 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1132
d6b4baa4 1133/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1134#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1135 /* Restrict which direct reloads are allowed for VFP regs. */ \
1136 ((TARGET_VFP && TARGET_HARD_FLOAT \
1137 && (CLASS) == VFP_REGS) \
1138 ? vfp_secondary_reload_class (MODE, X) : \
9b6b54e2 1139 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1140 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1141 && (CLASS) == CIRRUS_REGS \
1142 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1143 ? GENERAL_REGS : \
5b3e6663 1144 (TARGET_32BIT ? \
5a9335ef
NC		 1145 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1146 && CONSTANT_P (X)) \
1147 ? GENERAL_REGS : \
61f0ccff 1148 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1149 && (GET_CODE (X) == MEM \
1150 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1151 && true_regnum (X) == -1))) \
1152 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1153 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1154
6f734908
RE		 1155/* Try a machine-dependent way of reloading an illegitimate address
1156 operand. If we find one, push the reload and jump to WIN. This
1157 macro is used in only one place: `find_reloads_address' in reload.c.
1158
1159 For the ARM, we wish to handle large displacements off a base
1160 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1161 This can cut the number of reloads needed. */
1162#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1163 do \
1164 { \
1165 if (GET_CODE (X) == PLUS \
1166 && GET_CODE (XEXP (X, 0)) == REG \
1167 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1168 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1169 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1170 { \
1171 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1172 HOST_WIDE_INT low, high; \
1173 \
de6f27a8 1174 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1175 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1176 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1177 /* Need to be careful, -256 is not a valid offset. */ \
1178 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1179 else if (MODE == SImode \
de6f27a8 1180 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1181 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1182 /* Need to be careful, -4096 is not a valid offset. */ \
1183 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1184 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1185 /* Need to be careful, -256 is not a valid offset. */ \
1186 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1187 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1188 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1189 /* Need to be careful, -1024 is not a valid offset. */ \
1190 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1191 else \
1192 break; \
1193 \
30cf4896
KG		 1194 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1195 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1196 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1197 /* Check for overflow or zero */ \
1198 if (low == 0 || high == 0 || (high + low != val)) \
1199 break; \
1200 \
1201 /* Reload the high part into a base reg; leave the low part \
1202 in the mem. */ \
1203 X = gen_rtx_PLUS (GET_MODE (X), \
1204 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1205 GEN_INT (high)), \
1206 GEN_INT (low)); \
df4ae160 1207 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1208 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1209 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1210 goto WIN; \
1211 } \
1212 } \
62b10bbc 1213 while (0)
6f734908 1214
27847754 1215/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1216 SP+large_offset address, then reload won't know how to fix it. It sees
1217 only that SP isn't valid for HImode, and so reloads the SP into an index
1218 register, but the resulting address is still invalid because the offset
1219 is too big. We fix it here instead by reloading the entire address. */
1220/* We could probably achieve better results by defining PROMOTE_MODE to help
1221 cope with the variances between the Thumb's signed and unsigned byte and
1222 halfword load instructions. */
5b3e6663 1223/* ??? This should be safe for thumb2, but we may be able to do better. */
a132dad6
RE		 1224#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1225do { \
1226 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1227 if (new_x) \
1228 { \
1229 X = new_x; \
1230 goto WIN; \
1231 } \
1232} while (0)
d5b7b3ae
RE		 1233
1234#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1235 if (TARGET_ARM) \
1236 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1237 else \
1238 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1239
35d965d5
RS		 1240/* Return the maximum number of consecutive registers
1241 needed to represent mode MODE in a register of class CLASS.
3b684012 1242 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1243#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1244 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1245
1246/* If defined, gives a class of registers that cannot be used as the
1247 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1248
3b684012 1249/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1250#define REGISTER_MOVE_COST(MODE, FROM, TO) \
5b3e6663 1251 (TARGET_32BIT ? \
3b684012
RE		 1252 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1253 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
9b66ebb1
PB		 1254 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1255 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
5a9335ef
NC		 1256 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1257 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1258 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1259 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1260 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1261 2) \
d5b7b3ae
RE		 1262 : \
1263 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1264\f
1265/* Stack layout; function entry, exit and calling. */
1266
1267/* Define this if pushing a word on the stack
1268 makes the stack pointer a smaller address. */
1269#define STACK_GROWS_DOWNWARD 1
1270
a4d05547 1271/* Define this to nonzero if the nominal address of the stack frame
35d965d5
RS		 1272 is at the high-address end of the local variables;
1273 that is, each additional local variable allocated
1274 goes at a more negative offset in the frame. */
1275#define FRAME_GROWS_DOWNWARD 1
1276
a2503645
RS		 1277/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1278 When present, it is one word in size, and sits at the top of the frame,
1279 between the soft frame pointer and either r7 or r11.
1280
1281 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1282 and only then if some outgoing arguments are passed on the stack. It would
1283 be tempting to also check whether the stack arguments are passed by indirect
1284 calls, but there seems to be no reason in principle why a post-reload pass
1285 couldn't convert a direct call into an indirect one. */
1286#define CALLER_INTERWORKING_SLOT_SIZE \
1287 (TARGET_CALLER_INTERWORKING \
1288 && current_function_outgoing_args_size != 0 \
1289 ? UNITS_PER_WORD : 0)
1290
35d965d5
RS		 1291/* Offset within stack frame to start allocating local variables at.
1292 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1293 first local allocated. Otherwise, it is the offset to the BEGINNING
1294 of the first local allocated. */
1295#define STARTING_FRAME_OFFSET 0
1296
1297/* If we generate an insn to push BYTES bytes,
1298 this says how many the stack pointer really advances by. */
d5b7b3ae 1299/* The push insns do not do this rounding implicitly.
d6b4baa4 1300 So don't define this. */
0c2ca901 1301/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1302
1303/* Define this if the maximum size of all the outgoing args is to be
1304 accumulated and pushed during the prologue. The amount can be
1305 found in the variable current_function_outgoing_args_size. */
6cfc7210 1306#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1307
1308/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1309#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1310
1311/* Value is the number of byte of arguments automatically
1312 popped when returning from a subroutine call.
8b109b37 1313 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1314 FUNTYPE is the data type of the function (as a tree),
1315 or for a library call it is an identifier node for the subroutine name.
1316 SIZE is the number of bytes of arguments passed on the stack.
1317
1318 On the ARM, the caller does not pop any of its arguments that were passed
1319 on the stack. */
6cfc7210 1320#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1321
1322/* Define how to find the value returned by a library function
1323 assuming the value has mode MODE. */
1324#define LIBCALL_VALUE(MODE) \
5b3e6663 1325 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1326 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1327 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
5b3e6663 1328 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1329 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1330 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1331 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1332 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1333 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1334
6cfc7210
NC		 1335/* Define how to find the value returned by a function.
1336 VALTYPE is the data type of the value (as a tree).
1337 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1338 otherwise, FUNC is 0. */
d5b7b3ae 1339#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1340 arm_function_value (VALTYPE, FUNC);
6cfc7210 1341
35d965d5
RS		 1342/* 1 if N is a possible register number for a function value.
1343 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1344/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1345#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1346 ((REGNO) == ARG_REGISTER (1) \
5b3e6663 1347 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1348 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1349 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
5b3e6663 1350 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1351 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1352
9f7bf991
RE		 1353/* Amount of memory needed for an untyped call to save all possible return
1354 registers. */
1355#define APPLY_RESULT_SIZE arm_apply_result_size()
1356
11c1a207
RE		 1357/* How large values are returned */
1358/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1359 in registers, based on the type of value. */
f5a1b0d2 1360#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1361
1362/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1363 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1364 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1365#define DEFAULT_PCC_STRUCT_RETURN 0
1366
d5b7b3ae
RE		 1367/* Flags for the call/call_value rtl operations set up by function_arg. */
1368#define CALL_NORMAL 0x00000000 /* No special processing. */
1369#define CALL_LONG 0x00000001 /* Always call indirect. */
1370#define CALL_SHORT 0x00000002 /* Never call indirect. */
1371
6d3d9133 1372/* These bits describe the different types of function supported
112cdef5 1373 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1374 normal function and an interworked function, for example. Knowing the
1375 type of a function is important for determining its prologue and
1376 epilogue sequences.
1377 Note value 7 is currently unassigned. Also note that the interrupt
1378 function types all have bit 2 set, so that they can be tested for easily.
1379 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1380 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1381 default to unknown. This will force the first use of arm_current_func_type
1382 to call arm_compute_func_type. */
1383#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1384#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1385#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1386#define ARM_FT_ISR 4 /* An interrupt service routine. */
1387#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1388#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1389
1390#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1391
1392/* In addition functions can have several type modifiers,
1393 outlined by these bit masks: */
1394#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1395#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1396#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1397#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
5b3e6663 1398#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
6d3d9133
NC		 1399
1400/* Some macros to test these flags. */
1401#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1402#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1403#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1404#define IS_NAKED(t) (t & ARM_FT_NAKED)
1405#define IS_NESTED(t) (t & ARM_FT_NESTED)
5b3e6663 1406#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
6d3d9133 1407
5848830f
PB		 1408
1409/* Structure used to hold the function stack frame layout. Offsets are
1410 relative to the stack pointer on function entry. Positive offsets are
1411 in the direction of stack growth.
1412 Only soft_frame is used in thumb mode. */
1413
1414typedef struct arm_stack_offsets GTY(())
1415{
1416 int saved_args; /* ARG_POINTER_REGNUM. */
1417 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1418 int saved_regs;
1419 int soft_frame; /* FRAME_POINTER_REGNUM. */
2591db65 1420 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
5848830f
PB		 1421 int outgoing_args; /* STACK_POINTER_REGNUM. */
1422}
1423arm_stack_offsets;
1424
6d3d9133
NC		 1425/* A C structure for machine-specific, per-function data.
1426 This is added to the cfun structure. */
e2500fed 1427typedef struct machine_function GTY(())
d5b7b3ae 1428{
6bc82793 1429 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1430 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1431 /* Records if LR has to be saved for far jumps. */
1432 int far_jump_used;
1433 /* Records if ARG_POINTER was ever live. */
1434 int arg_pointer_live;
6f7ebcbb
NC		 1435 /* Records if the save of LR has been eliminated. */
1436 int lr_save_eliminated;
0977774b 1437 /* The size of the stack frame. Only valid after reload. */
5848830f 1438 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1439 /* Records the type of the current function. */
1440 unsigned long func_type;
3cb66fd7
NC		 1441 /* Record if the function has a variable argument list. */
1442 int uses_anonymous_args;
5a9335ef
NC		 1443 /* Records if sibcalls are blocked because an argument
1444 register is needed to preserve stack alignment. */
1445 int sibcall_blocked;
020a4035
RE		 1446 /* The PIC register for this function. This might be a pseudo. */
1447 rtx pic_reg;
b12a00f1 1448 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1449 register. We can never call via LR or PC. We can call via SP if a
1450 trampoline happens to be on the top of the stack. */
1451 rtx call_via[14];
6d3d9133
NC		 1452}
1453machine_function;
d5b7b3ae 1454
b12a00f1 1455/* As in the machine_function, a global set of call-via labels, for code
d6b5193b 1456 that is in text_section. */
57ecec57 1457extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1458
82e9d970
PB		 1459/* A C type for declaring a variable that is used as the first argument of
1460 `FUNCTION_ARG' and other related values. For some target machines, the
1461 type `int' suffices and can hold the number of bytes of argument so far. */
1462typedef struct
1463{
d5b7b3ae 1464 /* This is the number of registers of arguments scanned so far. */
82e9d970 1465 int nregs;
5a9335ef
NC		 1466 /* This is the number of iWMMXt register arguments scanned so far. */
1467 int iwmmxt_nregs;
1468 int named_count;
1469 int nargs;
d6b4baa4 1470 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
82e9d970 1471 int call_cookie;
5848830f 1472 int can_split;
d5b7b3ae 1473} CUMULATIVE_ARGS;
82e9d970 1474
35d965d5
RS		 1475/* Define where to put the arguments to a function.
1476 Value is zero to push the argument on the stack,
1477 or a hard register in which to store the argument.
1478
1479 MODE is the argument's machine mode.
1480 TYPE is the data type of the argument (as a tree).
1481 This is null for libcalls where that information may
1482 not be available.
1483 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1484 the preceding args and about the function being called.
1485 NAMED is nonzero if this argument is a named parameter
1486 (otherwise it is an extra parameter matching an ellipsis).
1487
1488 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1489 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1490 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1491 defined), say it is passed in the stack (function_prologue will
1492 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1493#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1494 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1495
866af8a9
JB		 1496#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1497 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1498
1499#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1500 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1501
1502/* For AAPCS, padding should never be below the argument. For other ABIs,
1503 * mimic the default. */
1504#define PAD_VARARGS_DOWN \
1505 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1506
35d965d5
RS		 1507/* Initialize a variable CUM of type CUMULATIVE_ARGS
1508 for a call to a function whose data type is FNTYPE.
1509 For a library call, FNTYPE is 0.
1510 On the ARM, the offset starts at 0. */
0f6937fe 1511#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1512 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1513
1514/* Update the data in CUM to advance over an argument
1515 of mode MODE and data type TYPE.
1516 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1517#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1518 (CUM).nargs += 1; \
f0c1ebb7
JM		 1519 if (arm_vector_mode_supported_p (MODE) \
1520 && (CUM).named_count > (CUM).nargs \
1521 && TARGET_IWMMXT_ABI) \
5848830f 1522 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1523 else \
5848830f 1524 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1525
5a9335ef
NC		 1526/* If defined, a C expression that gives the alignment boundary, in bits, of an
1527 argument with the specified mode and type. If it is not defined,
1528 `PARM_BOUNDARY' is used for all arguments. */
1529#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1530 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1531 ? DOUBLEWORD_ALIGNMENT \
1532 : PARM_BOUNDARY )
5a9335ef 1533
35d965d5
RS		 1534/* 1 if N is a possible register number for function argument passing.
1535 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1536#define FUNCTION_ARG_REGNO_P(REGNO) \
1537 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1538 || (TARGET_IWMMXT_ABI \
1539 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1540
f99fce0c 1541\f
afef3d7a
NC		 1542/* If your target environment doesn't prefix user functions with an
1543 underscore, you may wish to re-define this to prevent any conflicts.
1544 e.g. AOF may prefix mcount with an underscore. */
1545#ifndef ARM_MCOUNT_NAME
1546#define ARM_MCOUNT_NAME "*mcount"
1547#endif
1548
1549/* Call the function profiler with a given profile label. The Acorn
1550 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1551 On the ARM the full profile code will look like:
1552 .data
1553 LP1
1554 .word 0
1555 .text
1556 mov ip, lr
1557 bl mcount
1558 .word LP1
1559
1560 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1561 will output the .text section.
1562
1563 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1564 ``prof'' doesn't seem to mind about this!
1565
1566 Note - this version of the code is designed to work in both ARM and
1567 Thumb modes. */
be393ecf 1568#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1569#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1570{ \
1571 char temp[20]; \
1572 rtx sym; \
1573 \
dd18ae56 1574 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1575 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1576 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1577 fputc ('\n', STREAM); \
1578 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1579 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1580 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1581}
be393ecf 1582#endif
35d965d5 1583
59be6073 1584#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1585#define FUNCTION_PROFILER(STREAM, LABELNO) \
1586 if (TARGET_ARM) \
1587 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1588 else \
1589 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1590#else
1591#define FUNCTION_PROFILER(STREAM, LABELNO) \
1592 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1593#endif
d5b7b3ae 1594
35d965d5
RS		 1595/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1596 the stack pointer does not matter. The value is tested only in
1597 functions that have frame pointers.
1598 No definition is equivalent to always zero.
1599
1600 On the ARM, the function epilogue recovers the stack pointer from the
1601 frame. */
1602#define EXIT_IGNORE_STACK 1
1603
c7861455
RE		 1604#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1605
35d965d5
RS		 1606/* Determine if the epilogue should be output as RTL.
1607 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
5b3e6663
PB		 1608/* This is disabled for Thumb-2 because it will confuse the
1609 conditional insn counter. */
d5b7b3ae 1610#define USE_RETURN_INSN(ISCOND) \
a72d4945 1611 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1612
1613/* Definitions for register eliminations.
1614
1615 This is an array of structures. Each structure initializes one pair
1616 of eliminable registers. The "from" register number is given first,
1617 followed by "to". Eliminations of the same "from" register are listed
1618 in order of preference.
1619
1620 We have two registers that can be eliminated on the ARM. First, the
1621 arg pointer register can often be eliminated in favor of the stack
1622 pointer register. Secondly, the pseudo frame pointer register can always
1623 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1624 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1625 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1626
d5b7b3ae
RE		 1627#define ELIMINABLE_REGS \
1628{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1629 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1630 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1631 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1632 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1633 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1634 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1635
d5b7b3ae
RE		 1636/* Given FROM and TO register numbers, say whether this elimination is
1637 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1638
1639 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1640 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1641 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1642 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1643 ARG_POINTER_REGNUM. */
1644#define CAN_ELIMINATE(FROM, TO) \
1645 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1646 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1647 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1648 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1649 1)
aeaf4d25 1650
d5b7b3ae
RE		 1651/* Define the offset between two registers, one to be eliminated, and the
1652 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1653#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1654 if (TARGET_ARM) \
5848830f 1655 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1656 else \
5848830f
PB		 1657 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1658
d5b7b3ae
RE		 1659/* Special case handling of the location of arguments passed on the stack. */
1660#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1661
d5b7b3ae
RE		 1662/* Initialize data used by insn expanders. This is called from insn_emit,
1663 once for every function before code is generated. */
1664#define INIT_EXPANDERS arm_init_expanders ()
1665
35d965d5
RS		 1666/* Output assembler code for a block containing the constant parts
1667 of a trampoline, leaving space for the variable parts.
1668
1669 On the ARM, (if r8 is the static chain regnum, and remembering that
1670 referencing pc adds an offset of 8) the trampoline looks like:
1671 ldr r8, [pc, #0]
1672 ldr pc, [pc]
1673 .word static chain value
11c1a207 1674 .word function's address
27847754 1675 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1676#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1677{ \
1678 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1679 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1680 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1681 PC_REGNUM, PC_REGNUM); \
1682 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1683 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1684}
1685
5b3e6663
PB		 1686/* The Thumb-2 trampoline is similar to the arm implementation.
1687 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1688#define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1689{ \
1690 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1691 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1692 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1693 PC_REGNUM, PC_REGNUM); \
1694 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1695 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1696}
1697
1698#define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
d5b7b3ae 1699{ \
5b3e6663
PB		 1700 ASM_OUTPUT_ALIGN(FILE, 2); \
1701 fprintf (FILE, "\t.code\t16\n"); \
d5b7b3ae 1702 fprintf (FILE, ".Ltrampoline_start:\n"); \
5b3e6663
PB		 1703 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1704 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1705 PC_REGNUM); \
1706 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1707 STATIC_CHAIN_REGNUM); \
1708 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1709 PC_REGNUM); \
1710 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1711 SP_REGNUM); \
1712 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1713 PC_REGNUM); \
1714 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1715 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
35d965d5
RS		 1716}
1717
d5b7b3ae
RE		 1718#define TRAMPOLINE_TEMPLATE(FILE) \
1719 if (TARGET_ARM) \
1720 ARM_TRAMPOLINE_TEMPLATE (FILE) \
5b3e6663
PB		 1721 else if (TARGET_THUMB2) \
1722 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
d5b7b3ae 1723 else \
5b3e6663
PB		 1724 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1725
1726/* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1727 of the address. */
1728#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1729{ \
1730 if (TARGET_THUMB) \
1731 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1732 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1733} while(0)
f676971a 1734
35d965d5 1735/* Length in units of the trampoline for entering a nested function. */
5b3e6663 1736#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
35d965d5 1737
006946e4
JM		 1738/* Alignment required for a trampoline in bits. */
1739#define TRAMPOLINE_ALIGNMENT 32
35d965d5 1740
2a86f515 1741
35d965d5
RS		 1742/* Emit RTL insns to initialize the variable parts of a trampoline.
1743 FNADDR is an RTX for the address of the function's pure code.
1744 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1745#ifndef INITIALIZE_TRAMPOLINE
1746#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1747{ \
1748 emit_move_insn (gen_rtx_MEM (SImode, \
1749 plus_constant (TRAMP, \
5b3e6663 1750 TARGET_32BIT ? 8 : 12)), \
192c8d78
RE		 1751 CXT); \
1752 emit_move_insn (gen_rtx_MEM (SImode, \
1753 plus_constant (TRAMP, \
5b3e6663 1754 TARGET_32BIT ? 12 : 16)), \
192c8d78 1755 FNADDR); \
49755603
RE		 1756 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1757 0, VOIDmode, 2, TRAMP, Pmode, \
1758 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
35d965d5 1759}
192c8d78 1760#endif
35d965d5 1761
35d965d5
RS		 1762\f
1763/* Addressing modes, and classification of registers for them. */
3cd45774 1764#define HAVE_POST_INCREMENT 1
5b3e6663
PB		 1765#define HAVE_PRE_INCREMENT TARGET_32BIT
1766#define HAVE_POST_DECREMENT TARGET_32BIT
1767#define HAVE_PRE_DECREMENT TARGET_32BIT
1768#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1769#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1770#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1771#define HAVE_POST_MODIFY_REG TARGET_32BIT
35d965d5
RS		 1772
1773/* Macros to check register numbers against specific register classes. */
1774
1775/* These assume that REGNO is a hard or pseudo reg number.
1776 They give nonzero only if REGNO is a hard reg of the suitable class
1777 or a pseudo reg currently allocated to a suitable hard reg.
1778 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 1779 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 1780#define TEST_REGNO(R, TEST, VALUE) \
1781 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1782
5b3e6663 1783/* Don't allow the pc to be used. */
f1008e52
RE		 1784#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1785 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1786 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1787 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1788
5b3e6663 1789#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
f1008e52
RE		 1790 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1791 || (GET_MODE_SIZE (MODE) >= 4 \
1792 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1793
1794#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
5b3e6663
PB		 1795 (TARGET_THUMB1 \
1796 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
f1008e52
RE		 1797 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1798
888d2cd6
DJ		 1799/* Nonzero if X can be the base register in a reg+reg addressing mode.
1800 For Thumb, we can not use SP + reg, so reject SP. */
1801#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1802 REGNO_OK_FOR_INDEX_P (X)
1803
f1008e52
RE		 1804/* For ARM code, we don't care about the mode, but for Thumb, the index
1805 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 1806#define REGNO_OK_FOR_INDEX_P(REGNO) \
1807 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 1808
1809/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1810 Shifts in addresses can't be by a register. */
ff9940b0 1811#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1812
1813/* Recognize any constant value that is a valid address. */
1814/* XXX We can address any constant, eventually... */
11c1a207
RE		 1815
1816#ifdef AOF_ASSEMBLER
1817
1818#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 1819 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 1820
1821#else
35d965d5 1822
5b3e6663 1823/* ??? Should the TARGET_ARM here also apply to thumb2? */
008cf58a
RE		 1824#define CONSTANT_ADDRESS_P(X) \
1825 (GET_CODE (X) == SYMBOL_REF \
1826 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1827 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1828
11c1a207
RE		 1829#endif /* AOF_ASSEMBLER */
1830
35d965d5
RS		 1831/* Nonzero if the constant value X is a legitimate general operand.
1832 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1833
1834 On the ARM, allow any integer (invalid ones are removed later by insn
1835 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 1836 constant pool XXX.
f676971a 1837
82e9d970 1838 When generating pic allow anything. */
d5b7b3ae
RE		 1839#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1840
1841#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1842 ( GET_CODE (X) == CONST_INT \
1843 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 1844 || CONSTANT_ADDRESS_P (X) \
1845 || flag_pic)
d5b7b3ae 1846
d3585b76
DJ		 1847#define LEGITIMATE_CONSTANT_P(X) \
1848 (!arm_tls_referenced_p (X) \
5b3e6663
PB		 1849 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1850 : THUMB_LEGITIMATE_CONSTANT_P (X)))
d5b7b3ae 1851
c27ba912
DM		 1852/* Special characters prefixed to function names
1853 in order to encode attribute like information.
1854 Note, '@' and '*' have already been taken. */
1855#define SHORT_CALL_FLAG_CHAR '^'
1856#define LONG_CALL_FLAG_CHAR '#'
1857
1858#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1859 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1860
1861#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1862 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1863
1864#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1865#define SUBTARGET_NAME_ENCODING_LENGTHS
1866#endif
1867
6bc82793 1868/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1869 Each case label should return the number of characters to
1870 be stripped from the start of a function's name, if that
1871 name starts with the indicated character. */
1872#define ARM_NAME_ENCODING_LENGTHS \
1873 case SHORT_CALL_FLAG_CHAR: return 1; \
1874 case LONG_CALL_FLAG_CHAR: return 1; \
00fdafef 1875 case '*': return 1; \
f676971a 1876 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1877
c27ba912
DM		 1878/* This is how to output a reference to a user-level label named NAME.
1879 `assemble_name' uses this. */
e5951263 1880#undef ASM_OUTPUT_LABELREF
c27ba912 1881#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1882 arm_asm_output_labelref (FILE, NAME)
c27ba912 1883
5b3e6663
PB		 1884/* Output IT instructions for conditonally executed Thumb-2 instructions. */
1885#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1886 if (TARGET_THUMB2) \
1887 thumb2_asm_output_opcode (STREAM);
1888
7abc66b1
JB		 1889/* The EABI specifies that constructors should go in .init_array.
1890 Other targets use .ctors for compatibility. */
88c6057f 1891#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1892#define ARM_EABI_CTORS_SECTION_OP \
1893 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1894#endif
1895#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1896#define ARM_EABI_DTORS_SECTION_OP \
1897 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1898#endif
7abc66b1
JB		 1899#define ARM_CTORS_SECTION_OP \
1900 "\t.section\t.ctors,\"aw\",%progbits"
1901#define ARM_DTORS_SECTION_OP \
1902 "\t.section\t.dtors,\"aw\",%progbits"
1903
1904/* Define CTORS_SECTION_ASM_OP. */
1905#undef CTORS_SECTION_ASM_OP
1906#undef DTORS_SECTION_ASM_OP
1907#ifndef IN_LIBGCC2
1908# define CTORS_SECTION_ASM_OP \
1909 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1910# define DTORS_SECTION_ASM_OP \
1911 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1912#else /* !defined (IN_LIBGCC2) */
1913/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1914 so we cannot use the definition above. */
1915# ifdef __ARM_EABI__
1916/* The .ctors section is not part of the EABI, so we do not define
1917 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1918 from trying to use it. We do define it when doing normal
1919 compilation, as .init_array can be used instead of .ctors. */
1920/* There is no need to emit begin or end markers when using
1921 init_array; the dynamic linker will compute the size of the
1922 array itself based on special symbols created by the static
1923 linker. However, we do need to arrange to set up
1924 exception-handling here. */
1925# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1926# define CTOR_LIST_END /* empty */
1927# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1928# define DTOR_LIST_END /* empty */
1929# else /* !defined (__ARM_EABI__) */
1930# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1931# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1932# endif /* !defined (__ARM_EABI__) */
1933#endif /* !defined (IN_LIBCC2) */
1934
1e731102
MM		 1935/* True if the operating system can merge entities with vague linkage
1936 (e.g., symbols in COMDAT group) during dynamic linking. */
1937#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1938#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1939#endif
1940
a77655b1
NC		 1941/* Set the short-call flag for any function compiled in the current
1942 compilation unit. We skip this for functions with the section
c112cf2b 1943 attribute when long-calls are in effect as this tells the compiler
a77655b1
NC		 1944 that the section might be placed a long way from the caller.
1945 See arm_is_longcall_p() for more information. */
c27ba912 1946#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
a77655b1
NC		 1947 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1948 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
c27ba912 1949
617a1b71
PB		 1950#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1951
1952#ifdef TARGET_UNWIND_INFO
1953#define ARM_EABI_UNWIND_TABLES \
1954 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1955#else
1956#define ARM_EABI_UNWIND_TABLES 0
1957#endif
1958
35d965d5
RS		 1959/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1960 and check its validity for a certain class.
1961 We have two alternate definitions for each of them.
1962 The usual definition accepts all pseudo regs; the other rejects
1963 them unless they have been allocated suitable hard regs.
5b3e6663
PB		 1964 The symbol REG_OK_STRICT causes the latter definition to be used.
1965 Thumb-2 has the same restictions as arm. */
35d965d5 1966#ifndef REG_OK_STRICT
ff9940b0 1967
f1008e52
RE		 1968#define ARM_REG_OK_FOR_BASE_P(X) \
1969 (REGNO (X) <= LAST_ARM_REGNUM \
1970 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1971 || REGNO (X) == FRAME_POINTER_REGNUM \
1972 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 1973
5b3e6663 1974#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
f1008e52
RE		 1975 (REGNO (X) <= LAST_LO_REGNUM \
1976 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1977 || (GET_MODE_SIZE (MODE) >= 4 \
1978 && (REGNO (X) == STACK_POINTER_REGNUM \
1979 || (X) == hard_frame_pointer_rtx \
1980 || (X) == arg_pointer_rtx)))
ff9940b0 1981
76a318e9
RE		 1982#define REG_STRICT_P 0
1983
d5b7b3ae 1984#else /* REG_OK_STRICT */
ff9940b0 1985
f1008e52
RE		 1986#define ARM_REG_OK_FOR_BASE_P(X) \
1987 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 1988
5b3e6663
PB		 1989#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1990 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 1991
76a318e9
RE		 1992#define REG_STRICT_P 1
1993
d5b7b3ae 1994#endif /* REG_OK_STRICT */
f1008e52
RE		 1995
1996/* Now define some helpers in terms of the above. */
1997
1998#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
5b3e6663
PB		 1999 (TARGET_THUMB1 \
2000 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
f1008e52
RE		 2001 : ARM_REG_OK_FOR_BASE_P (X))
2002
2003#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2004
5b3e6663 2005/* For 16-bit Thumb, a valid index register is anything that can be used in
f1008e52 2006 a byte load instruction. */
5b3e6663
PB		 2007#define THUMB1_REG_OK_FOR_INDEX_P(X) \
2008 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
f1008e52
RE		 2009
2010/* Nonzero if X is a hard reg that can be used as an index
2011 or if it is a pseudo reg. On the Thumb, the stack pointer
2012 is not suitable. */
2013#define REG_OK_FOR_INDEX_P(X) \
5b3e6663
PB		 2014 (TARGET_THUMB1 \
2015 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
f1008e52
RE		 2016 : ARM_REG_OK_FOR_INDEX_P (X))
2017
888d2cd6
DJ		 2018/* Nonzero if X can be the base register in a reg+reg addressing mode.
2019 For Thumb, we can not use SP + reg, so reject SP. */
2020#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2021 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2022\f
2023/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2024 that is a valid memory address for an instruction.
2025 The MODE argument is the machine mode for the MEM expression
76a318e9 2026 that wants to use this address. */
f676971a 2027
f1008e52
RE		 2028#define ARM_BASE_REGISTER_RTX_P(X) \
2029 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2030
f1008e52
RE		 2031#define ARM_INDEX_REGISTER_RTX_P(X) \
2032 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2033
76a318e9
RE		 2034#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2035 { \
1e1ab407 2036 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2037 goto WIN; \
6b990f6b 2038 }
d5b7b3ae 2039
5b3e6663 2040#define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
76a318e9 2041 { \
5b3e6663
PB		 2042 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2043 goto WIN; \
2044 }
2045
2046#define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2047 { \
2048 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
76a318e9
RE		 2049 goto WIN; \
2050 }
d5b7b3ae 2051
d5b7b3ae
RE		 2052#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2053 if (TARGET_ARM) \
2054 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
5b3e6663
PB		 2055 else if (TARGET_THUMB2) \
2056 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2057 else /* if (TARGET_THUMB1) */ \
2058 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2059
35d965d5
RS		 2060\f
2061/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2062 to be legitimate. If we find one, return the new, valid address. */
2063#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2064do { \
2065 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2066} while (0)
2067
5b3e6663
PB		 2068/* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2069#define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2070do { \
2071} while (0)
2072
2073#define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
6f5b4f3e
RE		 2074do { \
2075 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2076} while (0)
2077
2078#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2079do { \
2080 if (TARGET_ARM) \
2081 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
5b3e6663
PB		 2082 else if (TARGET_THUMB2) \
2083 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
ccf4d512 2084 else \
5b3e6663 2085 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2086 \
2087 if (memory_address_p (MODE, X)) \
2088 goto WIN; \
ccf4d512 2089} while (0)
f676971a 2090
35d965d5
RS		 2091/* Go to LABEL if ADDR (a legitimate address expression)
2092 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2093#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2094{ \
d5b7b3ae
RE		 2095 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2096 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2097 goto LABEL; \
2098}
d5b7b3ae
RE		 2099
2100/* Nothing helpful to do for the Thumb */
2101#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
5b3e6663 2102 if (TARGET_32BIT) \
f676971a 2103 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2104\f
d5b7b3ae 2105
35d965d5
RS		 2106/* Specify the machine mode that this machine uses
2107 for the index in the tablejump instruction. */
d5b7b3ae 2108#define CASE_VECTOR_MODE Pmode
35d965d5 2109
5b3e6663
PB		 2110#define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2111
2112#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2113 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2114 : (max >= 0x200) ? HImode \
2115 : QImode)
2116
ff9940b0
RE		 2117/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2118 unsigned is probably best, but may break some code. */
2119#ifndef DEFAULT_SIGNED_CHAR
3967692c 2120#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2121#endif
2122
35d965d5 2123/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2124 in one reasonably fast instruction. */
2125#define MOVE_MAX 4
35d965d5 2126
d19fb8e3 2127#undef MOVE_RATIO
591af218 2128#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2129
ff9940b0
RE		 2130/* Define if operations between registers always perform the operation
2131 on the full register even if a narrower mode is specified. */
2132#define WORD_REGISTER_OPERATIONS
2133
2134/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2135 will either zero-extend or sign-extend. The value of this macro should
2136 be the code that says which one of the two operations is implicitly
f822d252 2137 done, UNKNOWN if none. */
9c872872 2138#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2139 (TARGET_THUMB ? ZERO_EXTEND : \
2140 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2141 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2142
35d965d5
RS		 2143/* Nonzero if access to memory by bytes is slow and undesirable. */
2144#define SLOW_BYTE_ACCESS 0
2145
d5b7b3ae 2146#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2147
35d965d5
RS		 2148/* Immediate shift counts are truncated by the output routines (or was it
2149 the assembler?). Shift counts in a register are truncated by ARM. Note
2150 that the native compiler puts too large (> 32) immediate shift counts
2151 into a register and shifts by the register, letting the ARM decide what
2152 to do instead of doing that itself. */
ff9940b0
RE		 2153/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2154 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2155 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2156 rotates is modulo 32 used. */
ff9940b0 2157/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2158
35d965d5 2159/* All integers have the same format so truncation is easy. */
d5b7b3ae 2160#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2161
2162/* Calling from registers is a massive pain. */
2163#define NO_FUNCTION_CSE 1
2164
35d965d5
RS		 2165/* The machine modes of pointers and functions */
2166#define Pmode SImode
2167#define FUNCTION_MODE Pmode
2168
d5b7b3ae
RE		 2169#define ARM_FRAME_RTX(X) \
2170 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2171 || (X) == arg_pointer_rtx)
2172
ff9940b0 2173/* Moves to and from memory are quite expensive */
d5b7b3ae 2174#define MEMORY_MOVE_COST(M, CLASS, IN) \
5b3e6663 2175 (TARGET_32BIT ? 10 : \
d5b7b3ae
RE		 2176 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2177 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2178
ff9940b0
RE		 2179/* Try to generate sequences that don't involve branches, we can then use
2180 conditional instructions */
d5b7b3ae 2181#define BRANCH_COST \
5b3e6663 2182 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
7a801826
RE		 2183\f
2184/* Position Independent Code. */
2185/* We decide which register to use based on the compilation options and
2186 the assembler in use; this is more general than the APCS restriction of
2187 using sb (r9) all the time. */
020a4035 2188extern unsigned arm_pic_register;
7a801826
RE		 2189
2190/* The register number of the register used to address a table of static
2191 data addresses in memory. */
2192#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2193
f5a1b0d2 2194/* We can't directly access anything that contains a symbol,
d3585b76
DJ		 2195 nor can we indirect via the constant pool. One exception is
2196 UNSPEC_TLS, which is always PIC. */
82e9d970 2197#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2198 (!(symbol_mentioned_p (X) \
2199 || label_mentioned_p (X) \
2200 || (GET_CODE (X) == SYMBOL_REF \
2201 && CONSTANT_POOL_ADDRESS_P (X) \
2202 && (symbol_mentioned_p (get_pool_constant (X)) \
d3585b76
DJ		 2203 || label_mentioned_p (get_pool_constant (X))))) \
2204 || tls_mentioned_p (X))
1575c31e 2205
13bd191d
PB		 2206/* We need to know when we are making a constant pool; this determines
2207 whether data needs to be in the GOT or can be referenced via a GOT
2208 offset. */
2209extern int making_const_table;
82e9d970 2210\f
c27ba912 2211/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2212#define REGISTER_TARGET_PRAGMAS() do { \
2213 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2214 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2215 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2216} while (0)
2217
d6b4baa4 2218/* Condition code information. */
ff9940b0 2219/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2220 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2221
2222#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2223
880873be
RE		 2224#define REVERSIBLE_CC_MODE(MODE) 1
2225
2226#define REVERSE_CONDITION(CODE,MODE) \
2227 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2228 ? reverse_condition_maybe_unordered (code) \
2229 : reverse_condition (code))
008cf58a 2230
62b10bbc
NC		 2231#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2232 do \
2233 { \
2234 if (GET_CODE (OP1) == CONST_INT \
2235 && ! (const_ok_for_arm (INTVAL (OP1)) \
2236 || (const_ok_for_arm (- INTVAL (OP1))))) \
2237 { \
2238 rtx const_op = OP1; \
a14b88bb
PB		 2239 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2240 &const_op); \
62b10bbc
NC		 2241 OP1 = const_op; \
2242 } \
2243 } \
2244 while (0)
62dd06ea 2245
7dba8395
RH		 2246/* The arm5 clz instruction returns 32. */
2247#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2248\f
d5b7b3ae 2249#undef ASM_APP_OFF
5b3e6663
PB		 2250#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2251 TARGET_THUMB2 ? "\t.thumb\n" : "")
35d965d5 2252
35d965d5 2253/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2254#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2255 do \
2256 { \
2257 if (TARGET_ARM) \
2258 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2259 STACK_POINTER_REGNUM, REGNO); \
2260 else \
2261 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2262 } while (0)
d5b7b3ae
RE		 2263
2264
2265#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2266 do \
2267 { \
2268 if (TARGET_ARM) \
2269 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2270 STACK_POINTER_REGNUM, REGNO); \
2271 else \
2272 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2273 } while (0)
d5b7b3ae 2274
5b3e6663
PB		 2275/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2276#define ADDR_VEC_ALIGN(JUMPTABLE) 0
2277
d5b7b3ae
RE		 2278/* This is how to output a label which precedes a jumptable. Since
2279 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2280#undef ASM_OUTPUT_CASE_LABEL
5b3e6663
PB		 2281#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2282 do \
2283 { \
2284 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2285 ASM_OUTPUT_ALIGN (FILE, 2); \
2286 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2287 } \
2288 while (0)
2289
2290/* Make sure subsequent insns are aligned after a TBB. */
2291#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2292 do \
2293 { \
2294 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2295 ASM_OUTPUT_ALIGN (FILE, 1); \
2296 } \
d5b7b3ae 2297 while (0)
35d965d5 2298
6cfc7210
NC		 2299#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2300 do \
2301 { \
d5b7b3ae
RE		 2302 if (TARGET_THUMB) \
2303 { \
5b3e6663
PB		 2304 if (is_called_in_ARM_mode (DECL) \
2305 || (TARGET_THUMB1 && current_function_is_thunk)) \
d5b7b3ae 2306 fprintf (STREAM, "\t.code 32\n") ; \
5b3e6663
PB		 2307 else if (TARGET_THUMB1) \
2308 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
d5b7b3ae 2309 else \
5b3e6663 2310 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
d5b7b3ae 2311 } \
6cfc7210 2312 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2313 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2314 } \
2315 while (0)
35d965d5 2316
d5b7b3ae
RE		 2317/* For aliases of functions we use .thumb_set instead. */
2318#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2319 do \
2320 { \
91ea4f8d
KG		 2321 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2322 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2323 \
2324 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2325 { \
2326 fprintf (FILE, "\t.thumb_set "); \
2327 assemble_name (FILE, LABEL1); \
2328 fprintf (FILE, ","); \
2329 assemble_name (FILE, LABEL2); \
2330 fprintf (FILE, "\n"); \
2331 } \
2332 else \
2333 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2334 } \
2335 while (0)
2336
fdc2d3b0
NC		 2337#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2338/* To support -falign-* switches we need to use .p2align so
2339 that alignment directives in code sections will be padded
2340 with no-op instructions, rather than zeroes. */
5a9335ef 2341#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2342 if ((LOG) != 0) \
2343 { \
2344 if ((MAX_SKIP) == 0) \
5a9335ef 2345 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2346 else \
2347 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2348 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2349 }
2350#endif
35d965d5 2351\f
5b3e6663
PB		 2352/* Add two bytes to the length of conditionally executed Thumb-2
2353 instructions for the IT instruction. */
2354#define ADJUST_INSN_LENGTH(insn, length) \
2355 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2356 length += 2;
2357
35d965d5 2358/* Only perform branch elimination (by making instructions conditional) if
5b3e6663
PB		 2359 we're optimizing. For Thumb-2 check if any IT instructions need
2360 outputting. */
d5b7b3ae
RE		 2361#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2362 if (TARGET_ARM && optimize) \
2363 arm_final_prescan_insn (INSN); \
5b3e6663
PB		 2364 else if (TARGET_THUMB2) \
2365 thumb2_final_prescan_insn (INSN); \
2366 else if (TARGET_THUMB1) \
2367 thumb1_final_prescan_insn (INSN)
35d965d5 2368
7bc7696c 2369#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
5b3e6663
PB		 2370 (CODE == '@' || CODE == '|' || CODE == '.' \
2371 || CODE == '(' || CODE == ')' \
2372 || (TARGET_32BIT && (CODE == '?')) \
2373 || (TARGET_THUMB2 && (CODE == '!')) \
d5b7b3ae 2374 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2375
7bc7696c 2376/* Output an operand of an instruction. */
35d965d5 2377#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2378 arm_print_operand (STREAM, X, CODE)
2379
7b8b8ade
NC		 2380#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2381 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2382 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2383 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2384 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2385 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2386 : 0))))
35d965d5
RS		 2387
2388/* Output the address of an operand. */
3cd45774
RE		 2389#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2390{ \
2391 int is_minus = GET_CODE (X) == MINUS; \
2392 \
2393 if (GET_CODE (X) == REG) \
2394 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2395 else if (GET_CODE (X) == PLUS || is_minus) \
2396 { \
2397 rtx base = XEXP (X, 0); \
2398 rtx index = XEXP (X, 1); \
2399 HOST_WIDE_INT offset = 0; \
2400 if (GET_CODE (base) != REG) \
2401 { \
d6b4baa4
KH		 2402 /* Ensure that BASE is a register. */ \
2403 /* (one of them must be). */ \
3cd45774
RE		 2404 rtx temp = base; \
2405 base = index; \
2406 index = temp; \
2407 } \
2408 switch (GET_CODE (index)) \
2409 { \
2410 case CONST_INT: \
2411 offset = INTVAL (index); \
2412 if (is_minus) \
2413 offset = -offset; \
c53dddc2 2414 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2415 REGNO (base), offset); \
2416 break; \
2417 \
2418 case REG: \
2419 asm_fprintf (STREAM, "[%r, %s%r]", \
2420 REGNO (base), is_minus ? "-" : "", \
2421 REGNO (index)); \
2422 break; \
2423 \
2424 case MULT: \
2425 case ASHIFTRT: \
2426 case LSHIFTRT: \
2427 case ASHIFT: \
2428 case ROTATERT: \
2429 { \
2430 asm_fprintf (STREAM, "[%r, %s%r", \
2431 REGNO (base), is_minus ? "-" : "", \
2432 REGNO (XEXP (index, 0))); \
2433 arm_print_operand (STREAM, index, 'S'); \
2434 fputs ("]", STREAM); \
2435 break; \
2436 } \
2437 \
2438 default: \
e6d29d15 2439 gcc_unreachable (); \
3cd45774
RE		 2440 } \
2441 } \
2442 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2443 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2444 { \
2445 extern enum machine_mode output_memory_reference_mode; \
2446 \
e6d29d15 2447 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
3cd45774
RE		 2448 \
2449 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2450 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2451 REGNO (XEXP (X, 0)), \
2452 GET_CODE (X) == PRE_DEC ? "-" : "", \
2453 GET_MODE_SIZE (output_memory_reference_mode)); \
2454 else \
2455 asm_fprintf (STREAM, "[%r], #%s%d", \
2456 REGNO (XEXP (X, 0)), \
2457 GET_CODE (X) == POST_DEC ? "-" : "", \
2458 GET_MODE_SIZE (output_memory_reference_mode)); \
2459 } \
2460 else if (GET_CODE (X) == PRE_MODIFY) \
2461 { \
2462 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2463 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2464 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2465 INTVAL (XEXP (XEXP (X, 1), 1))); \
2466 else \
2467 asm_fprintf (STREAM, "%r]!", \
2468 REGNO (XEXP (XEXP (X, 1), 1))); \
2469 } \
2470 else if (GET_CODE (X) == POST_MODIFY) \
2471 { \
2472 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2473 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2474 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2475 INTVAL (XEXP (XEXP (X, 1), 1))); \
2476 else \
2477 asm_fprintf (STREAM, "%r", \
2478 REGNO (XEXP (XEXP (X, 1), 1))); \
2479 } \
2480 else output_addr_const (STREAM, X); \
35d965d5 2481}
62dd06ea 2482
d5b7b3ae
RE		 2483#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2484{ \
2485 if (GET_CODE (X) == REG) \
2486 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2487 else if (GET_CODE (X) == POST_INC) \
2488 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2489 else if (GET_CODE (X) == PLUS) \
2490 { \
e6d29d15 2491 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
d5b7b3ae 2492 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2493 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2494 REGNO (XEXP (X, 0)), \
659bdc68 2495 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2496 else \
2497 asm_fprintf (STREAM, "[%r, %r]", \
2498 REGNO (XEXP (X, 0)), \
2499 REGNO (XEXP (X, 1))); \
2500 } \
2501 else \
2502 output_addr_const (STREAM, X); \
2503}
2504
2505#define PRINT_OPERAND_ADDRESS(STREAM, X) \
5b3e6663 2506 if (TARGET_32BIT) \
d5b7b3ae
RE		 2507 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2508 else \
2509 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef 2510
d3585b76
DJ		 2511#define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2512 if (arm_output_addr_const_extra (file, x) == FALSE) \
2513 goto fail
5a9335ef 2514
6a5d7526
MS		 2515/* A C expression whose value is RTL representing the value of the return
2516 address for the frame COUNT steps up from the current frame. */
2517
d5b7b3ae
RE		 2518#define RETURN_ADDR_RTX(COUNT, FRAME) \
2519 arm_return_addr (COUNT, FRAME)
2520
f676971a 2521/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2522 when running in 26-bit mode. */
2523#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2524
2c849145
JM		 2525/* Pick up the return address upon entry to a procedure. Used for
2526 dwarf2 unwind information. This also enables the table driven
2527 mechanism. */
2c849145
JM		 2528#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2529#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2530
39950dff
MS		 2531/* Used to mask out junk bits from the return address, such as
2532 processor state, interrupt status, condition codes and the like. */
2533#define MASK_RETURN_ADDR \
2534 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2535 in 26 bit mode, the condition codes must be masked out of the \
2536 return address. This does not apply to ARM6 and later processors \
2537 when running in 32 bit mode. */ \
61f0ccff
RE		 2538 ((arm_arch4 || TARGET_THUMB) \
2539 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2540 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2541
2542\f
5a9335ef
NC		 2543enum arm_builtins
2544{
2545 ARM_BUILTIN_GETWCX,
2546 ARM_BUILTIN_SETWCX,
2547
2548 ARM_BUILTIN_WZERO,
2549
2550 ARM_BUILTIN_WAVG2BR,
2551 ARM_BUILTIN_WAVG2HR,
2552 ARM_BUILTIN_WAVG2B,
2553 ARM_BUILTIN_WAVG2H,
2554
2555 ARM_BUILTIN_WACCB,
2556 ARM_BUILTIN_WACCH,
2557 ARM_BUILTIN_WACCW,
2558
2559 ARM_BUILTIN_WMACS,
2560 ARM_BUILTIN_WMACSZ,
2561 ARM_BUILTIN_WMACU,
2562 ARM_BUILTIN_WMACUZ,
2563
2564 ARM_BUILTIN_WSADB,
2565 ARM_BUILTIN_WSADBZ,
2566 ARM_BUILTIN_WSADH,
2567 ARM_BUILTIN_WSADHZ,
2568
2569 ARM_BUILTIN_WALIGN,
2570
2571 ARM_BUILTIN_TMIA,
2572 ARM_BUILTIN_TMIAPH,
2573 ARM_BUILTIN_TMIABB,
2574 ARM_BUILTIN_TMIABT,
2575 ARM_BUILTIN_TMIATB,
2576 ARM_BUILTIN_TMIATT,
2577
2578 ARM_BUILTIN_TMOVMSKB,
2579 ARM_BUILTIN_TMOVMSKH,
2580 ARM_BUILTIN_TMOVMSKW,
2581
2582 ARM_BUILTIN_TBCSTB,
2583 ARM_BUILTIN_TBCSTH,
2584 ARM_BUILTIN_TBCSTW,
2585
2586 ARM_BUILTIN_WMADDS,
2587 ARM_BUILTIN_WMADDU,
2588
2589 ARM_BUILTIN_WPACKHSS,
2590 ARM_BUILTIN_WPACKWSS,
2591 ARM_BUILTIN_WPACKDSS,
2592 ARM_BUILTIN_WPACKHUS,
2593 ARM_BUILTIN_WPACKWUS,
2594 ARM_BUILTIN_WPACKDUS,
2595
2596 ARM_BUILTIN_WADDB,
2597 ARM_BUILTIN_WADDH,
2598 ARM_BUILTIN_WADDW,
2599 ARM_BUILTIN_WADDSSB,
2600 ARM_BUILTIN_WADDSSH,
2601 ARM_BUILTIN_WADDSSW,
2602 ARM_BUILTIN_WADDUSB,
2603 ARM_BUILTIN_WADDUSH,
2604 ARM_BUILTIN_WADDUSW,
2605 ARM_BUILTIN_WSUBB,
2606 ARM_BUILTIN_WSUBH,
2607 ARM_BUILTIN_WSUBW,
2608 ARM_BUILTIN_WSUBSSB,
2609 ARM_BUILTIN_WSUBSSH,
2610 ARM_BUILTIN_WSUBSSW,
2611 ARM_BUILTIN_WSUBUSB,
2612 ARM_BUILTIN_WSUBUSH,
2613 ARM_BUILTIN_WSUBUSW,
2614
2615 ARM_BUILTIN_WAND,
2616 ARM_BUILTIN_WANDN,
2617 ARM_BUILTIN_WOR,
2618 ARM_BUILTIN_WXOR,
2619
2620 ARM_BUILTIN_WCMPEQB,
2621 ARM_BUILTIN_WCMPEQH,
2622 ARM_BUILTIN_WCMPEQW,
2623 ARM_BUILTIN_WCMPGTUB,
2624 ARM_BUILTIN_WCMPGTUH,
2625 ARM_BUILTIN_WCMPGTUW,
2626 ARM_BUILTIN_WCMPGTSB,
2627 ARM_BUILTIN_WCMPGTSH,
2628 ARM_BUILTIN_WCMPGTSW,
2629
2630 ARM_BUILTIN_TEXTRMSB,
2631 ARM_BUILTIN_TEXTRMSH,
2632 ARM_BUILTIN_TEXTRMSW,
2633 ARM_BUILTIN_TEXTRMUB,
2634 ARM_BUILTIN_TEXTRMUH,
2635 ARM_BUILTIN_TEXTRMUW,
2636 ARM_BUILTIN_TINSRB,
2637 ARM_BUILTIN_TINSRH,
2638 ARM_BUILTIN_TINSRW,
2639
2640 ARM_BUILTIN_WMAXSW,
2641 ARM_BUILTIN_WMAXSH,
2642 ARM_BUILTIN_WMAXSB,
2643 ARM_BUILTIN_WMAXUW,
2644 ARM_BUILTIN_WMAXUH,
2645 ARM_BUILTIN_WMAXUB,
2646 ARM_BUILTIN_WMINSW,
2647 ARM_BUILTIN_WMINSH,
2648 ARM_BUILTIN_WMINSB,
2649 ARM_BUILTIN_WMINUW,
2650 ARM_BUILTIN_WMINUH,
2651 ARM_BUILTIN_WMINUB,
2652
f07a6b21
BE		 2653 ARM_BUILTIN_WMULUM,
2654 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2655 ARM_BUILTIN_WMULUL,
2656
2657 ARM_BUILTIN_PSADBH,
2658 ARM_BUILTIN_WSHUFH,
2659
2660 ARM_BUILTIN_WSLLH,
2661 ARM_BUILTIN_WSLLW,
2662 ARM_BUILTIN_WSLLD,
2663 ARM_BUILTIN_WSRAH,
2664 ARM_BUILTIN_WSRAW,
2665 ARM_BUILTIN_WSRAD,
2666 ARM_BUILTIN_WSRLH,
2667 ARM_BUILTIN_WSRLW,
2668 ARM_BUILTIN_WSRLD,
2669 ARM_BUILTIN_WRORH,
2670 ARM_BUILTIN_WRORW,
2671 ARM_BUILTIN_WRORD,
2672 ARM_BUILTIN_WSLLHI,
2673 ARM_BUILTIN_WSLLWI,
2674 ARM_BUILTIN_WSLLDI,
2675 ARM_BUILTIN_WSRAHI,
2676 ARM_BUILTIN_WSRAWI,
2677 ARM_BUILTIN_WSRADI,
2678 ARM_BUILTIN_WSRLHI,
2679 ARM_BUILTIN_WSRLWI,
2680 ARM_BUILTIN_WSRLDI,
2681 ARM_BUILTIN_WRORHI,
2682 ARM_BUILTIN_WRORWI,
2683 ARM_BUILTIN_WRORDI,
2684
2685 ARM_BUILTIN_WUNPCKIHB,
2686 ARM_BUILTIN_WUNPCKIHH,
2687 ARM_BUILTIN_WUNPCKIHW,
2688 ARM_BUILTIN_WUNPCKILB,
2689 ARM_BUILTIN_WUNPCKILH,
2690 ARM_BUILTIN_WUNPCKILW,
2691
2692 ARM_BUILTIN_WUNPCKEHSB,
2693 ARM_BUILTIN_WUNPCKEHSH,
2694 ARM_BUILTIN_WUNPCKEHSW,
2695 ARM_BUILTIN_WUNPCKEHUB,
2696 ARM_BUILTIN_WUNPCKEHUH,
2697 ARM_BUILTIN_WUNPCKEHUW,
2698 ARM_BUILTIN_WUNPCKELSB,
2699 ARM_BUILTIN_WUNPCKELSH,
2700 ARM_BUILTIN_WUNPCKELSW,
2701 ARM_BUILTIN_WUNPCKELUB,
2702 ARM_BUILTIN_WUNPCKELUH,
2703 ARM_BUILTIN_WUNPCKELUW,
2704
d3585b76
DJ		 2705 ARM_BUILTIN_THREAD_POINTER,
2706
5a9335ef
NC		 2707 ARM_BUILTIN_MAX
2708};
978e411f
CD		 2709
2710/* Do not emit .note.GNU-stack by default. */
2711#ifndef NEED_INDICATE_EXEC_STACK
2712#define NEED_INDICATE_EXEC_STACK 0
2713#endif
2714
88657302 2715#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git