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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
7adcbafe | 2 | Copyright (C) 1991-2022 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 5 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
6 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
7 | ||
4f448245 | 8 | This file is part of GCC. |
35d965d5 | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 12 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 13 | option) any later version. |
35d965d5 | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
35d965d5 | 19 | |
999db125 GJL |
20 | Under Section 7 of GPL version 3, you are granted additional |
21 | permissions described in the GCC Runtime Library Exception, version | |
22 | 3.1, as published by the Free Software Foundation. | |
23 | ||
c7eca9fe GJL |
24 | You should have received a copy of the GNU General Public License and |
25 | a copy of the GCC Runtime Library Exception along with this program; | |
26 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 27 | <http://www.gnu.org/licenses/>. */ |
35d965d5 | 28 | |
88657302 RH |
29 | #ifndef GCC_ARM_H |
30 | #define GCC_ARM_H | |
b355a481 | 31 | |
ef4bddc2 | 32 | /* We can't use machine_mode inside a generator file because it |
46107b99 RE |
33 | hasn't been created yet; we shouldn't be using any code that |
34 | needs the real definition though, so this ought to be safe. */ | |
35 | #ifdef GENERATOR_FILE | |
36 | #define MACHMODE int | |
37 | #else | |
38 | #include "insn-modes.h" | |
2c0122c9 | 39 | #define MACHMODE machine_mode |
46107b99 RE |
40 | #endif |
41 | ||
9403b7f7 RS |
42 | #include "config/vxworks-dummy.h" |
43 | ||
35fd3193 | 44 | /* The architecture define. */ |
78011587 PB |
45 | extern char arm_arch_name[]; |
46 | ||
e6471be6 | 47 | /* Target CPU builtins. */ |
7049e4eb | 48 | #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) |
e6471be6 | 49 | |
3785d2b2 | 50 | /* Target hooks for D language. */ |
b4c522fa | 51 | #define TARGET_D_CPU_VERSIONS arm_d_target_versions |
3785d2b2 | 52 | #define TARGET_D_REGISTER_CPU_TARGET_INFO arm_d_register_target_info |
b4c522fa | 53 | |
ad7be009 | 54 | #include "config/arm/arm-opts.h" |
9b66ebb1 PB |
55 | |
56 | /* The processor for which instructions should be scheduled. */ | |
57 | extern enum processor_type arm_tune; | |
58 | ||
d5b7b3ae | 59 | typedef enum arm_cond_code |
89c7ca52 RE |
60 | { |
61 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
62 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
63 | } |
64 | arm_cc; | |
6cfc7210 | 65 | |
d5b7b3ae | 66 | extern arm_cc arm_current_cc; |
ff9940b0 | 67 | |
d5b7b3ae | 68 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 69 | |
cd794ed4 | 70 | /* The maximum number of instructions that is beneficial to |
b24a2ce5 GY |
71 | conditionally execute. */ |
72 | #undef MAX_CONDITIONAL_EXECUTE | |
73 | #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () | |
74 | ||
6cfc7210 NC |
75 | extern int arm_target_label; |
76 | extern int arm_ccfsm_state; | |
e2500fed | 77 | extern GTY(()) rtx arm_target_insn; |
b76c3c4b PB |
78 | /* Callback to output language specific object attributes. */ |
79 | extern void (*arm_lang_output_object_attributes_hook)(void); | |
5774b1fa JG |
80 | |
81 | /* This type is the user-visible __fp16. We need it in a few places in | |
e53b6e56 | 82 | the backend. Defined in arm-builtins.cc. */ |
5774b1fa JG |
83 | extern tree arm_fp16_type_node; |
84 | ||
2e87b2f4 | 85 | /* This type is the user-visible __bf16. We need it in a few places in |
e53b6e56 | 86 | the backend. Defined in arm-builtins.cc. */ |
2e87b2f4 SMW |
87 | extern tree arm_bf16_type_node; |
88 | extern tree arm_bf16_ptr_type_node; | |
89 | ||
35d965d5 | 90 | \f |
5742588d | 91 | #undef CPP_SPEC |
4a322345 | 92 | #define CPP_SPEC "%(subtarget_cpp_spec)" |
7a801826 | 93 | |
be393ecf | 94 | #ifndef CC1_SPEC |
dfa08768 | 95 | #define CC1_SPEC "" |
be393ecf | 96 | #endif |
7a801826 RE |
97 | |
98 | /* This macro defines names of additional specifications to put in the specs | |
99 | that can be used in various specifications like CC1_SPEC. Its definition | |
100 | is an initializer with a subgrouping for each command option. | |
101 | ||
102 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 103 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
104 | program. |
105 | ||
106 | Do not define this macro if it does not need to do anything. */ | |
107 | #define EXTRA_SPECS \ | |
38fc909b | 108 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
54e73f88 | 109 | { "asm_cpu_spec", ASM_CPU_SPEC }, \ |
7a801826 RE |
110 | SUBTARGET_EXTRA_SPECS |
111 | ||
914a3b8c | 112 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 113 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
114 | #endif |
115 | ||
6cfc7210 | 116 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 117 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 118 | #endif |
35d965d5 | 119 | \f |
1a7ae4ce | 120 | /* Tree Target Specification. */ |
08793a38 CB |
121 | #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) |
122 | #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) | |
123 | #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) | |
5797378a | 124 | #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) |
08793a38 | 125 | |
35d965d5 | 126 | /* Run-time Target Specification. */ |
48528842 RR |
127 | /* Use hardware floating point instructions. -mgeneral-regs-only prevents |
128 | the use of floating point instructions and registers but does not prevent | |
129 | emission of floating point pcs attributes. */ | |
130 | #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ | |
2e17e319 | 131 | && bitmap_bit_p (arm_active_target.isa, \ |
ec5e6814 TP |
132 | isa_bit_vfpv2) \ |
133 | && TARGET_32BIT) | |
48528842 RR |
134 | |
135 | #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ | |
136 | && !TARGET_GENERAL_REGS_ONLY) | |
137 | ||
138 | #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) | |
2e17e319 RE |
139 | /* User has permitted use of FP instructions, if they exist for this |
140 | target. */ | |
141 | #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
72cdc543 PB |
142 | /* Use hardware floating point calling convention. */ |
143 | #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
5a9335ef | 144 | #define TARGET_IWMMXT (arm_arch_iwmmxt) |
8fd03515 | 145 | #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) |
48528842 RR |
146 | #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ |
147 | && !TARGET_GENERAL_REGS_ONLY) | |
148 | #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ | |
149 | && !TARGET_GENERAL_REGS_ONLY) | |
5b3e6663 | 150 | #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) |
d5b7b3ae RE |
151 | #define TARGET_ARM (! TARGET_THUMB) |
152 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
a3038e19 | 153 | #define TARGET_BACKTRACE (crtl->is_leaf \ |
c54c7322 RS |
154 | ? TARGET_TPCS_LEAF_FRAME \ |
155 | : TARGET_TPCS_FRAME) | |
b6685939 PB |
156 | #define TARGET_AAPCS_BASED \ |
157 | (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
3ada8e17 | 158 | |
d3585b76 DJ |
159 | #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) |
160 | #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
ccdc2164 | 161 | #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) |
d3585b76 | 162 | |
5b3e6663 PB |
163 | /* Only 16-bit thumb code. */ |
164 | #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
165 | /* Arm or Thumb-2 32-bit code. */ | |
166 | #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
167 | /* 32-bit Thumb-2 code. */ | |
168 | #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
bf98ec6c PB |
169 | /* Thumb-1 only. */ |
170 | #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
5b3e6663 | 171 | |
c3f808d3 | 172 | #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ |
3383b7fa GY |
173 | && !TARGET_THUMB1) |
174 | ||
582e2e43 KT |
175 | #define TARGET_CRC32 (arm_arch_crc) |
176 | ||
c2bb84be SD |
177 | /* Thumb-2 but also has some conditional arithmetic instructions like csinc, |
178 | csinv, etc. */ | |
179 | #define TARGET_COND_ARITH (arm_arch8_1m_main) | |
180 | ||
88f77cba | 181 | /* The following two macros concern the ability to execute coprocessor |
302c3d8e PB |
182 | instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently |
183 | only ever tested when we know we are generating for VFP hardware; we need | |
184 | to be more careful with TARGET_NEON as noted below. */ | |
88f77cba | 185 | |
302c3d8e | 186 | /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ |
091df649 | 187 | #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) |
302c3d8e PB |
188 | |
189 | /* FPU supports VFPv3 instructions. */ | |
bdb0828f | 190 | #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) |
302c3d8e | 191 | |
2f6403f1 | 192 | /* FPU supports FPv5 instructions. */ |
bdb0828f | 193 | #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) |
2f6403f1 | 194 | |
e0dc3601 | 195 | /* FPU only supports VFP single-precision instructions. */ |
091df649 | 196 | #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) |
e0dc3601 PB |
197 | |
198 | /* FPU supports VFP double-precision instructions. */ | |
091df649 | 199 | #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) |
e0dc3601 PB |
200 | |
201 | /* FPU supports half-precision floating-point with NEON element load/store. */ | |
00ea1506 | 202 | #define TARGET_NEON_FP16 \ |
091df649 RE |
203 | (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ |
204 | && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) | |
0fd8c3ad | 205 | |
091df649 RE |
206 | /* FPU supports VFP half-precision floating-point conversions. */ |
207 | #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) | |
e0dc3601 | 208 | |
5e0f10a0 JG |
209 | /* FPU supports converting between HFmode and DFmode in a single hardware |
210 | step. */ | |
211 | #define TARGET_FP16_TO_DOUBLE \ | |
f65112f6 | 212 | (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) |
5e0f10a0 | 213 | |
9e94a7fc | 214 | /* FPU supports fused-multiply-add operations. */ |
bdb0828f | 215 | #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) |
9e94a7fc | 216 | |
595fefee | 217 | /* FPU supports Crypto extensions. */ |
091df649 | 218 | #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) |
595fefee | 219 | |
88f77cba JB |
220 | /* FPU supports Neon instructions. The setting of this macro gets |
221 | revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
222 | and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
223 | available. */ | |
cafd2e45 | 224 | #define TARGET_NEON \ |
00ea1506 | 225 | (TARGET_32BIT && TARGET_HARD_FLOAT \ |
091df649 | 226 | && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) |
cafd2e45 | 227 | |
252e03b5 MW |
228 | /* FPU supports ARMv8.1 Adv.SIMD extensions. */ |
229 | #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) | |
230 | ||
82896b22 | 231 | /* Supports the Dot Product AdvSIMD extensions. */ |
427071d4 | 232 | #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ |
ba09dd21 | 233 | && bitmap_bit_p (arm_active_target.isa, \ |
82896b22 TC |
234 | isa_bit_dotprod) \ |
235 | && arm_arch8_2) | |
ba09dd21 | 236 | |
c2b7062d TC |
237 | /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ |
238 | #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) | |
239 | ||
06e95715 KT |
240 | /* FPU supports the floating point FP16 instructions for ARMv8.2-A |
241 | and later. */ | |
4040b89a | 242 | #define TARGET_VFP_FP16INST \ |
c8d61ab8 | 243 | (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) |
4040b89a | 244 | |
06e95715 KT |
245 | /* Target supports the floating point FP16 instructions from ARMv8.2-A |
246 | and later. */ | |
247 | #define TARGET_FP16FML (TARGET_NEON \ | |
248 | && bitmap_bit_p (arm_active_target.isa, \ | |
249 | isa_bit_fp16fml) \ | |
250 | && arm_arch8_2) | |
251 | ||
4040b89a MW |
252 | /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ |
253 | #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) | |
254 | ||
f782b667 DZ |
255 | /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ |
256 | #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) | |
257 | ||
258 | /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ | |
259 | #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ | |
260 | && arm_arch8_2 && arm_arch_bf16) | |
261 | #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ | |
262 | && arm_arch8_2 && arm_arch_bf16) | |
263 | ||
9e94a7fc | 264 | /* Q-bit is present. */ |
c8b6aa7c | 265 | #define TARGET_ARM_QBIT \ |
c3f808d3 | 266 | (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) |
9e94a7fc | 267 | /* Saturation operation, e.g. SSAT. */ |
c8b6aa7c CB |
268 | #define TARGET_ARM_SAT \ |
269 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) | |
5b3e6663 | 270 | /* "DSP" multiply instructions, eg. SMULxy. */ |
c8b6aa7c | 271 | #define TARGET_DSP_MULTIPLY \ |
c3f808d3 | 272 | (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) |
5b3e6663 | 273 | /* Integer SIMD instructions, and extend-accumulate instructions. */ |
c8b6aa7c CB |
274 | #define TARGET_INT_SIMD \ |
275 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) | |
5b3e6663 | 276 | |
571191af | 277 | /* Should MOVW/MOVT be used in preference to a constant pool. */ |
7ec70105 | 278 | #define TARGET_USE_MOVT \ |
33427b46 | 279 | (TARGET_HAVE_MOVT \ |
02231c13 TG |
280 | && (arm_disable_literal_pool \ |
281 | || (!optimize_size && !current_tune->prefer_constant_pool))) | |
571191af | 282 | |
029e79eb | 283 | /* Nonzero if this chip provides the DMB instruction. */ |
9e2a6301 | 284 | #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) |
029e79eb MS |
285 | |
286 | /* Nonzero if this chip implements a memory barrier via CP15. */ | |
80651d8e DAG |
287 | #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ |
288 | && ! TARGET_THUMB1) | |
029e79eb MS |
289 | |
290 | /* Nonzero if this chip implements a memory barrier instruction. */ | |
291 | #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | |
292 | ||
293 | /* Nonzero if this chip supports ldrex and strex */ | |
ddb92ab9 TP |
294 | #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ |
295 | || arm_arch7 \ | |
296 | || (arm_arch8 && !arm_arch_notm)) | |
029e79eb | 297 | |
74a00288 | 298 | /* Nonzero if this chip supports LPAE. */ |
bf634d1c | 299 | #define TARGET_HAVE_LPAE (arm_arch_lpae) |
74a00288 | 300 | |
cfe52743 | 301 | /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ |
ddb92ab9 TP |
302 | #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ |
303 | || arm_arch7 \ | |
304 | || (arm_arch8 && !arm_arch_notm)) | |
cfe52743 DAG |
305 | |
306 | /* Nonzero if this chip supports ldrexd and strexd. */ | |
c8b6aa7c CB |
307 | #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ |
308 | || arm_arch7) && arm_arch_notm) | |
5b3e6663 | 309 | |
5ad29f12 | 310 | /* Nonzero if this chip supports load-acquire and store-release. */ |
ddb92ab9 | 311 | #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) |
d62b809c TP |
312 | |
313 | /* Nonzero if this chip supports LDAEXD and STLEXD. */ | |
314 | #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ | |
315 | && TARGET_32BIT \ | |
316 | && arm_arch_notm) | |
5ad29f12 | 317 | |
2b9509a3 TP |
318 | /* Nonzero if this chip provides the MOVW and MOVT instructions. */ |
319 | #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) | |
33427b46 | 320 | |
5ce15300 TP |
321 | /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ |
322 | #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) | |
323 | ||
e0e4be48 MI |
324 | /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions |
325 | instructions (most are floating-point related). */ | |
326 | #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) | |
327 | ||
63c8f7d6 SP |
328 | #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ |
329 | && bitmap_bit_p (arm_active_target.isa, \ | |
330 | isa_bit_mve) \ | |
331 | && !TARGET_GENERAL_REGS_ONLY) | |
7b4c373b | 332 | |
63c8f7d6 SP |
333 | #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ |
334 | && bitmap_bit_p (arm_active_target.isa, \ | |
335 | isa_bit_mve_float) \ | |
336 | && !TARGET_GENERAL_REGS_ONLY) | |
7b4c373b | 337 | |
c7be0832 SP |
338 | /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM |
339 | alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few | |
340 | registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All | |
341 | the VFP instructions, RTL patterns and register are guarded by | |
342 | TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers | |
343 | between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE | |
344 | hereafter. */ | |
345 | ||
346 | #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ | |
347 | && bitmap_bit_p (arm_active_target.isa, \ | |
348 | isa_bit_vfp_base) \ | |
349 | && !TARGET_GENERAL_REGS_ONLY) | |
350 | ||
572070ef | 351 | /* Nonzero if integer division instructions supported. */ |
c8b6aa7c | 352 | #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ |
5ce15300 | 353 | || (TARGET_THUMB && arm_arch_thumb_hwdiv)) |
572070ef | 354 | |
afe006ad TG |
355 | /* Nonzero if disallow volatile memory access in IT block. */ |
356 | #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) | |
357 | ||
975e6670 DZ |
358 | /* Nonzero if chip supports the Custom Datapath Extension. */ |
359 | #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) | |
360 | ||
26c66656 KV |
361 | /* Should constant I be slplit for OP. */ |
362 | #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ | |
363 | ((optimize >= 2) \ | |
364 | && can_create_pseudo_p () \ | |
365 | && !const_ok_for_op (i, op)) | |
366 | ||
b3f8d95d MM |
367 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, |
368 | then TARGET_AAPCS_BASED must be true -- but the converse does not | |
369 | hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
370 | etc., in addition to just the AAPCS calling conventions. */ | |
371 | #ifndef TARGET_BPABI | |
372 | #define TARGET_BPABI false | |
f676971a | 373 | #endif |
b3f8d95d | 374 | |
2f7d18dd CB |
375 | /* Transform lane numbers on big endian targets. This is used to allow for the |
376 | endianness difference between NEON architectural lane numbers and those | |
377 | used in RTL */ | |
378 | #define NEON_ENDIAN_LANE_N(mode, n) \ | |
379 | (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) | |
380 | ||
7816bea0 DJ |
381 | /* Support for a compile-time default CPU, et cetera. The rules are: |
382 | --with-arch is ignored if -march or -mcpu are specified. | |
383 | --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
384 | by --with-arch. | |
385 | --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
386 | by -march). | |
5e1b4d5a | 387 | --with-float is ignored if -mfloat-abi is specified. |
5848830f | 388 | --with-fpu is ignored if -mfpu is specified. |
ccdc2164 | 389 | --with-abi is ignored if -mabi is specified. |
15cf7fe3 RE |
390 | --with-tls is ignored if -mtls-dialect is specified. |
391 | Note: --with-mode is not handled here, that has a special rule | |
392 | TARGET_MODE_CHECK that also takes into account the selected CPU and | |
393 | architecture. */ | |
7816bea0 DJ |
394 | #define OPTION_DEFAULT_SPECS \ |
395 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
396 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
397 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
5e1b4d5a | 398 | {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ |
5848830f | 399 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
3cf94279 | 400 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ |
7cf13d1f | 401 | {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, |
7816bea0 | 402 | |
d79f3032 PB |
403 | extern const struct arm_fpu_desc |
404 | { | |
405 | const char *name; | |
066416da | 406 | enum isa_feature isa_bits[isa_num_bits]; |
19708abc CB |
407 | } all_fpus[]; |
408 | ||
d79f3032 PB |
409 | /* Which floating point hardware to schedule for. */ |
410 | extern int arm_fpu_attr; | |
71791e16 | 411 | |
3d8532aa PB |
412 | #ifndef TARGET_DEFAULT_FLOAT_ABI |
413 | #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
414 | #endif | |
415 | ||
5848830f PB |
416 | #ifndef ARM_DEFAULT_ABI |
417 | #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
418 | #endif | |
419 | ||
1ca92bdc SH |
420 | /* AAPCS based ABIs use short enums by default. */ |
421 | #ifndef ARM_DEFAULT_SHORT_ENUMS | |
422 | #define ARM_DEFAULT_SHORT_ENUMS \ | |
423 | (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) | |
424 | #endif | |
425 | ||
9e94a7fc MGD |
426 | /* Map each of the micro-architecture variants to their corresponding |
427 | major architecture revision. */ | |
428 | ||
429 | enum base_architecture | |
430 | { | |
431 | BASE_ARCH_0 = 0, | |
432 | BASE_ARCH_2 = 2, | |
433 | BASE_ARCH_3 = 3, | |
434 | BASE_ARCH_3M = 3, | |
435 | BASE_ARCH_4 = 4, | |
436 | BASE_ARCH_4T = 4, | |
9e94a7fc MGD |
437 | BASE_ARCH_5T = 5, |
438 | BASE_ARCH_5TE = 5, | |
439 | BASE_ARCH_5TEJ = 5, | |
440 | BASE_ARCH_6 = 6, | |
441 | BASE_ARCH_6J = 6, | |
39c12541 | 442 | BASE_ARCH_6KZ = 6, |
9e94a7fc MGD |
443 | BASE_ARCH_6K = 6, |
444 | BASE_ARCH_6T2 = 6, | |
445 | BASE_ARCH_6M = 6, | |
446 | BASE_ARCH_6Z = 6, | |
447 | BASE_ARCH_7 = 7, | |
448 | BASE_ARCH_7A = 7, | |
449 | BASE_ARCH_7R = 7, | |
450 | BASE_ARCH_7M = 7, | |
595fefee | 451 | BASE_ARCH_7EM = 7, |
05a437c1 TP |
452 | BASE_ARCH_8A = 8, |
453 | BASE_ARCH_8M_BASE = 8, | |
9296dd9b | 454 | BASE_ARCH_8M_MAIN = 8, |
32ba7860 PW |
455 | BASE_ARCH_8R = 8, |
456 | BASE_ARCH_9A = 9 | |
9e94a7fc MGD |
457 | }; |
458 | ||
459 | /* The major revision number of the ARM Architecture implemented by the target. */ | |
460 | extern enum base_architecture arm_base_arch; | |
461 | ||
9b66ebb1 | 462 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
11c1a207 RE |
463 | extern int arm_arch4; |
464 | ||
68d560d4 RE |
465 | /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ |
466 | extern int arm_arch4t; | |
467 | ||
c3f808d3 KT |
468 | /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ |
469 | extern int arm_arch5t; | |
62b10bbc | 470 | |
c3f808d3 KT |
471 | /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ |
472 | extern int arm_arch5te; | |
b15bca31 | 473 | |
9b66ebb1 PB |
474 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
475 | extern int arm_arch6; | |
476 | ||
029e79eb MS |
477 | /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ |
478 | extern int arm_arch6k; | |
479 | ||
9e2a6301 TG |
480 | /* Nonzero if instructions present in ARMv6-M can be used. */ |
481 | extern int arm_arch6m; | |
482 | ||
029e79eb MS |
483 | /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ |
484 | extern int arm_arch7; | |
485 | ||
5b3e6663 PB |
486 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
487 | extern int arm_arch_notm; | |
488 | ||
60bd3528 PB |
489 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
490 | extern int arm_arch7em; | |
491 | ||
595fefee MGD |
492 | /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ |
493 | extern int arm_arch8; | |
494 | ||
252e03b5 MW |
495 | /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ |
496 | extern int arm_arch8_1; | |
497 | ||
4040b89a MW |
498 | /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ |
499 | extern int arm_arch8_2; | |
500 | ||
c2b7062d TC |
501 | /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ |
502 | extern int arm_arch8_3; | |
503 | ||
504 | /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ | |
505 | extern int arm_arch8_4; | |
506 | ||
e27cf2e3 MI |
507 | /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline |
508 | extensions. */ | |
509 | extern int arm_arch8_1m_main; | |
510 | ||
4040b89a MW |
511 | /* Nonzero if this chip supports the FP16 instructions extension of ARM |
512 | Architecture 8.2. */ | |
513 | extern int arm_fp16_inst; | |
514 | ||
f5a1b0d2 NC |
515 | /* Nonzero if this chip can benefit from load scheduling. */ |
516 | extern int arm_ld_sched; | |
517 | ||
518 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 519 | extern int arm_tune_strongarm; |
f5a1b0d2 | 520 | |
5a9335ef NC |
521 | /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ |
522 | extern int arm_arch_iwmmxt; | |
523 | ||
8fd03515 XQ |
524 | /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ |
525 | extern int arm_arch_iwmmxt2; | |
526 | ||
d19fb8e3 | 527 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
528 | extern int arm_arch_xscale; |
529 | ||
abac3b49 | 530 | /* Nonzero if tuning for XScale. */ |
4b3c2e48 | 531 | extern int arm_tune_xscale; |
d19fb8e3 | 532 | |
abac3b49 RE |
533 | /* Nonzero if tuning for stores via the write buffer. */ |
534 | extern int arm_tune_wbuf; | |
f5a1b0d2 | 535 | |
7612f14d PB |
536 | /* Nonzero if tuning for Cortex-A9. */ |
537 | extern int arm_tune_cortex_a9; | |
538 | ||
2ad4dcf9 | 539 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 540 | preprocessor. |
2ad4dcf9 RE |
541 | XXX This is a bit of a hack, it's intended to help work around |
542 | problems in GLD which doesn't understand that armv5t code is | |
543 | interworking clean. */ | |
544 | extern int arm_cpp_interwork; | |
545 | ||
52545641 TP |
546 | /* Nonzero if chip supports Thumb 1. */ |
547 | extern int arm_arch_thumb1; | |
548 | ||
5b3e6663 PB |
549 | /* Nonzero if chip supports Thumb 2. */ |
550 | extern int arm_arch_thumb2; | |
551 | ||
572070ef PB |
552 | /* Nonzero if chip supports integer division instruction in ARM mode. */ |
553 | extern int arm_arch_arm_hwdiv; | |
554 | ||
555 | /* Nonzero if chip supports integer division instruction in Thumb mode. */ | |
556 | extern int arm_arch_thumb_hwdiv; | |
5b3e6663 | 557 | |
afe006ad TG |
558 | /* Nonzero if chip disallows volatile memory access in IT block. */ |
559 | extern int arm_arch_no_volatile_ce; | |
560 | ||
02231c13 TG |
561 | /* Nonzero if we shouldn't use literal pools. */ |
562 | #ifndef USED_FOR_TARGET | |
563 | extern bool arm_disable_literal_pool; | |
564 | #endif | |
565 | ||
582e2e43 KT |
566 | /* Nonzero if chip supports the ARMv8 CRC instructions. */ |
567 | extern int arm_arch_crc; | |
568 | ||
de7b5723 AV |
569 | /* Nonzero if chip supports the ARMv8-M Security Extensions. */ |
570 | extern int arm_arch_cmse; | |
571 | ||
f782b667 DZ |
572 | /* Nonzero if chip supports the I8MM instructions. */ |
573 | extern int arm_arch_i8mm; | |
574 | ||
575 | /* Nonzero if chip supports the BFloat16 instructions. */ | |
576 | extern int arm_arch_bf16; | |
577 | ||
975e6670 DZ |
578 | /* Nonzero if chip supports the Custom Datapath Extension. */ |
579 | extern int arm_arch_cde; | |
580 | extern int arm_arch_cde_coproc; | |
581 | extern const int arm_arch_cde_coproc_bits[]; | |
07b9bfd0 | 582 | #define ARM_CDE_CONST_COPROC 7 |
a5f3c89e MM |
583 | #define ARM_CCDE_CONST_1 ((1 << 13) - 1) |
584 | #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) | |
585 | #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) | |
07b9bfd0 DZ |
586 | #define ARM_VCDE_CONST_1 ((1 << 11) - 1) |
587 | #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) | |
588 | #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) | |
78bf9163 MM |
589 | #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) |
590 | #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) | |
591 | #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) | |
975e6670 | 592 | |
2ce9c1b9 | 593 | #ifndef TARGET_DEFAULT |
c54c7322 | 594 | #define TARGET_DEFAULT (MASK_APCS_FRAME) |
2ce9c1b9 | 595 | #endif |
35d965d5 | 596 | |
86efdc8e PB |
597 | /* Nonzero if PIC code requires explicit qualifiers to generate |
598 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
599 | Subtargets can override these if required. */ |
600 | #ifndef NEED_GOT_RELOC | |
601 | #define NEED_GOT_RELOC 0 | |
602 | #endif | |
603 | #ifndef NEED_PLT_RELOC | |
604 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 605 | #endif |
84306176 | 606 | |
32d6e6c0 JY |
607 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
608 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
609 | #endif | |
610 | ||
84306176 PB |
611 | /* Nonzero if we need to refer to the GOT with a PC-relative |
612 | offset. In other words, generate | |
613 | ||
f676971a | 614 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] |
84306176 PB |
615 | |
616 | rather than | |
617 | ||
618 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
619 | ||
f676971a | 620 | The default is true, which matches NetBSD. Subtargets can |
84306176 PB |
621 | override this if required. */ |
622 | #ifndef GOT_PCREL | |
623 | #define GOT_PCREL 1 | |
624 | #endif | |
35d965d5 RS |
625 | \f |
626 | /* Target machine storage Layout. */ | |
627 | ||
d2ed233c AC |
628 | /* Nonzero if this chip provides Armv8.1-M Mainline |
629 | LOB (low overhead branch features) extension instructions. */ | |
630 | #define TARGET_HAVE_LOB (arm_arch8_1m_main) | |
ff9940b0 RE |
631 | |
632 | /* Define this macro if it is advisable to hold scalars in registers | |
633 | in a wider mode than that declared by the program. In such cases, | |
634 | the value is constrained to be within the bounds of the declared | |
635 | type, but kept valid in the wider mode. The signedness of the | |
636 | extension may differ from that of the type. */ | |
637 | ||
6cfc7210 | 638 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
639 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
640 | && GET_MODE_SIZE (MODE) < 4) \ | |
641 | { \ | |
2ce9c1b9 | 642 | (MODE) = SImode; \ |
ff9940b0 RE |
643 | } |
644 | ||
35d965d5 RS |
645 | /* Define this if most significant bit is lowest numbered |
646 | in instructions that operate on numbered bit-fields. */ | |
647 | #define BITS_BIG_ENDIAN 0 | |
648 | ||
f676971a | 649 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
650 | Most ARM processors are run in little endian mode, so that is the default. |
651 | If you want to have it run-time selectable, change the definition in a | |
652 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 653 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
654 | |
655 | /* Define this if most significant word of a multiword number is the lowest | |
8adb5dc7 KT |
656 | numbered. */ |
657 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
ddee6aba | 658 | |
35d965d5 RS |
659 | #define UNITS_PER_WORD 4 |
660 | ||
5848830f | 661 | /* True if natural alignment is used for doubleword types. */ |
b6685939 PB |
662 | #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED |
663 | ||
5848830f | 664 | #define DOUBLEWORD_ALIGNMENT 64 |
35d965d5 | 665 | |
5848830f | 666 | #define PARM_BOUNDARY 32 |
5a9335ef | 667 | |
5848830f | 668 | #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
35d965d5 | 669 | |
5848830f PB |
670 | #define PREFERRED_STACK_BOUNDARY \ |
671 | (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
0977774b | 672 | |
63b0cb04 CB |
673 | #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) |
674 | #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) | |
35d965d5 | 675 | |
92928d71 AO |
676 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
677 | vbit must go into the delta field of pointers to member | |
678 | functions. */ | |
679 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
680 | ||
35d965d5 RS |
681 | #define EMPTY_FIELD_BOUNDARY 32 |
682 | ||
5848830f | 683 | #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
5a9335ef | 684 | |
f276d31d BE |
685 | #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT |
686 | ||
27847754 NC |
687 | /* XXX Blah -- this macro is used directly by libobjc. Since it |
688 | supports no vector modes, cut out the complexity and fall back | |
689 | on BIGGEST_FIELD_ALIGNMENT. */ | |
690 | #ifdef IN_TARGET_LIBS | |
8fca31a2 | 691 | #define BIGGEST_FIELD_ALIGNMENT 64 |
27847754 | 692 | #endif |
5a9335ef | 693 | |
96339268 RE |
694 | /* Align definitions of arrays, unions and structures so that |
695 | initializations and copies can be made more efficient. This is not | |
696 | ABI-changing, so it only affects places where we can see the | |
0c86e0dd CLT |
697 | definition. Increasing the alignment tends to introduce padding, |
698 | so don't do this when optimizing for size/conserving stack space. */ | |
699 | #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
700 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
96339268 RE |
701 | && (TREE_CODE (EXP) == ARRAY_TYPE \ |
702 | || TREE_CODE (EXP) == UNION_TYPE \ | |
703 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
704 | ||
0c86e0dd CLT |
705 | /* Align global data. */ |
706 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
707 | ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) | |
708 | ||
96339268 | 709 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ |
0c86e0dd CLT |
710 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ |
711 | ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) | |
96339268 | 712 | |
723ae7c1 NC |
713 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
714 | value set in previous versions of this toolchain was 8, which produces more | |
715 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 716 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 | 717 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
5848830f PB |
718 | 0020D) page 2-20 says "Structures are aligned on word boundaries". |
719 | The AAPCS specifies a value of 8. */ | |
6ead9ba5 | 720 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
723ae7c1 | 721 | |
4912a07c | 722 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 723 | particular arm target wants to change the default value it should change |
6bc82793 | 724 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
725 | for an example of this. */ |
726 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
727 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 728 | #endif |
2a5307b1 | 729 | |
825dda42 | 730 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 731 | when given unaligned data. */ |
35d965d5 | 732 | #define STRICT_ALIGNMENT 1 |
b6685939 PB |
733 | |
734 | /* wchar_t is unsigned under the AAPCS. */ | |
735 | #ifndef WCHAR_TYPE | |
736 | #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
737 | ||
738 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
739 | #endif | |
740 | ||
655b30bf JB |
741 | /* Sized for fixed-point types. */ |
742 | ||
743 | #define SHORT_FRACT_TYPE_SIZE 8 | |
744 | #define FRACT_TYPE_SIZE 16 | |
745 | #define LONG_FRACT_TYPE_SIZE 32 | |
746 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
747 | ||
748 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
749 | #define ACCUM_TYPE_SIZE 32 | |
750 | #define LONG_ACCUM_TYPE_SIZE 64 | |
751 | #define LONG_LONG_ACCUM_TYPE_SIZE 64 | |
752 | ||
753 | #define MAX_FIXED_MODE_SIZE 64 | |
754 | ||
b6685939 PB |
755 | #ifndef SIZE_TYPE |
756 | #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
757 | #endif | |
d81d0bdd | 758 | |
077fc835 KH |
759 | #ifndef PTRDIFF_TYPE |
760 | #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
761 | #endif | |
762 | ||
d81d0bdd PB |
763 | /* AAPCS requires that structure alignment is affected by bitfields. */ |
764 | #ifndef PCC_BITFIELD_TYPE_MATTERS | |
765 | #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
766 | #endif | |
767 | ||
82a19768 AT |
768 | /* The maximum size of the sync library functions supported. */ |
769 | #ifndef MAX_SYNC_LIBFUNC_SIZE | |
5357406f | 770 | #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) |
82a19768 AT |
771 | #endif |
772 | ||
35d965d5 RS |
773 | \f |
774 | /* Standard register usage. */ | |
775 | ||
0be8bd1a | 776 | /* Register allocation in ARM Procedure Call Standard |
3c5a5b93 | 777 | (S - saved over call, F - Frame-related). |
35d965d5 RS |
778 | |
779 | r0 * argument word/integer result | |
780 | r1-r3 argument word | |
781 | ||
782 | r4-r8 S register variable | |
783 | r9 S (rfp) register variable (real frame pointer) | |
f676971a | 784 | |
f5a1b0d2 | 785 | r10 F S (sl) stack limit (used by -mapcs-stack-check) |
35d965d5 RS |
786 | r11 F S (fp) argument pointer |
787 | r12 (ip) temp workspace | |
788 | r13 F S (sp) lower end of current stack frame | |
789 | r14 (lr) link address/workspace | |
790 | r15 F (pc) program counter | |
791 | ||
ff9940b0 RE |
792 | cc This is NOT a real register, but is used internally |
793 | to represent things that use or set the condition | |
794 | codes. | |
795 | sfp This isn't either. It is used during rtl generation | |
796 | since the offset between the frame pointer and the | |
797 | auto's isn't known until after register allocation. | |
798 | afp Nor this, we only need this because of non-local | |
799 | goto. Without it fp appears to be used and the | |
800 | elimination code won't get rid of sfp. It tracks | |
801 | fp exactly at all times. | |
cf16f980 KT |
802 | apsrq Nor this, it is used to track operations on the Q bit |
803 | of APSR by ACLE saturating intrinsics. | |
16155ccf KT |
804 | apsrge Nor this, it is used to track operations on the GE bits |
805 | of APSR by ACLE SIMD32 intrinsics | |
ff9940b0 | 806 | |
5efd84c5 | 807 | *: See TARGET_CONDITIONAL_REGISTER_USAGE */ |
35d965d5 | 808 | |
9b66ebb1 PB |
809 | /* s0-s15 VFP scratch (aka d0-d7). |
810 | s16-s31 S VFP variable (aka d8-d15). | |
811 | vfpcc Not a real register. Represents the VFP condition | |
63c8f7d6 SP |
812 | code flags. |
813 | vpr Used to represent MVE VPR predication. */ | |
9b66ebb1 | 814 | |
ff9940b0 RE |
815 | /* The stack backtrace structure is as follows: |
816 | fp points to here: | save code pointer | [fp] | |
817 | | return link value | [fp, #-4] | |
818 | | return sp value | [fp, #-8] | |
819 | | return fp value | [fp, #-12] | |
820 | [| saved r10 value |] | |
821 | [| saved r9 value |] | |
822 | [| saved r8 value |] | |
823 | [| saved r7 value |] | |
824 | [| saved r6 value |] | |
825 | [| saved r5 value |] | |
826 | [| saved r4 value |] | |
827 | [| saved r3 value |] | |
828 | [| saved r2 value |] | |
829 | [| saved r1 value |] | |
830 | [| saved r0 value |] | |
ff9940b0 RE |
831 | r0-r3 are not normally saved in a C function. */ |
832 | ||
35d965d5 RS |
833 | /* 1 for registers that have pervasive standard uses |
834 | and are not available for the register allocator. */ | |
0be8bd1a RE |
835 | #define FIXED_REGISTERS \ |
836 | { \ | |
837 | /* Core regs. */ \ | |
838 | 0,0,0,0,0,0,0,0, \ | |
839 | 0,0,0,0,0,1,0,1, \ | |
840 | /* VFP regs. */ \ | |
841 | 1,1,1,1,1,1,1,1, \ | |
842 | 1,1,1,1,1,1,1,1, \ | |
843 | 1,1,1,1,1,1,1,1, \ | |
844 | 1,1,1,1,1,1,1,1, \ | |
845 | 1,1,1,1,1,1,1,1, \ | |
846 | 1,1,1,1,1,1,1,1, \ | |
847 | 1,1,1,1,1,1,1,1, \ | |
848 | 1,1,1,1,1,1,1,1, \ | |
849 | /* IWMMXT regs. */ \ | |
850 | 1,1,1,1,1,1,1,1, \ | |
851 | 1,1,1,1,1,1,1,1, \ | |
852 | 1,1,1,1, \ | |
853 | /* Specials. */ \ | |
63c8f7d6 | 854 | 1,1,1,1,1,1,1 \ |
35d965d5 RS |
855 | } |
856 | ||
857 | /* 1 for registers not available across function calls. | |
858 | These must include the FIXED_REGISTERS and also any | |
859 | registers that can be used without being saved. | |
860 | The latter must include the registers where values are returned | |
861 | and the register where structure-value addresses are passed. | |
ff9940b0 | 862 | Aside from that, you can include as many other registers as you like. |
f676971a | 863 | The CC is not preserved over function calls on the ARM 6, so it is |
d6b4baa4 | 864 | easier to assume this for all. SFP is preserved, since FP is. */ |
0be8bd1a RE |
865 | #define CALL_USED_REGISTERS \ |
866 | { \ | |
867 | /* Core regs. */ \ | |
868 | 1,1,1,1,0,0,0,0, \ | |
869 | 0,0,0,0,1,1,1,1, \ | |
870 | /* VFP Regs. */ \ | |
871 | 1,1,1,1,1,1,1,1, \ | |
872 | 1,1,1,1,1,1,1,1, \ | |
873 | 1,1,1,1,1,1,1,1, \ | |
874 | 1,1,1,1,1,1,1,1, \ | |
875 | 1,1,1,1,1,1,1,1, \ | |
876 | 1,1,1,1,1,1,1,1, \ | |
877 | 1,1,1,1,1,1,1,1, \ | |
878 | 1,1,1,1,1,1,1,1, \ | |
879 | /* IWMMXT regs. */ \ | |
880 | 1,1,1,1,1,1,1,1, \ | |
881 | 1,1,1,1,1,1,1,1, \ | |
882 | 1,1,1,1, \ | |
883 | /* Specials. */ \ | |
63c8f7d6 | 884 | 1,1,1,1,1,1,1 \ |
35d965d5 RS |
885 | } |
886 | ||
6cc8c0b3 NC |
887 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
888 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
889 | #endif | |
890 | ||
6bc82793 | 891 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
892 | by asm_fprintf: |
893 | %@ prints out ASM_COMMENT_START | |
894 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
895 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
896 | case '@': \ | |
897 | fputs (ASM_COMMENT_START, FILE); \ | |
898 | break; \ | |
899 | \ | |
900 | case 'r': \ | |
901 | fputs (REGISTER_PREFIX, FILE); \ | |
902 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
903 | break; | |
904 | ||
d5b7b3ae | 905 | /* Round X up to the nearest word. */ |
0c2ca901 | 906 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 907 | |
6cfc7210 | 908 | /* Convert fron bytes to ints. */ |
e9d7b180 | 909 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 | 910 | |
9b66ebb1 PB |
911 | /* The number of (integer) registers required to hold a quantity of type MODE. |
912 | Also used for VFP registers. */ | |
e9d7b180 JD |
913 | #define ARM_NUM_REGS(MODE) \ |
914 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
915 | |
916 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
917 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
918 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 919 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
920 | |
921 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 922 | #define NUM_ARG_REGS 4 |
6cfc7210 | 923 | |
390b17c2 RE |
924 | /* And similarly for the VFP. */ |
925 | #define NUM_VFP_ARG_REGS 16 | |
926 | ||
093354e0 | 927 | /* Return the register number of the N'th (integer) argument. */ |
d5b7b3ae | 928 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 929 | |
d5b7b3ae RE |
930 | /* Specify the registers used for certain standard purposes. |
931 | The values of these macros are register numbers. */ | |
35d965d5 | 932 | |
d5b7b3ae RE |
933 | /* The number of the last argument register. */ |
934 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 935 | |
c769a35d RE |
936 | /* The numbers of the Thumb register ranges. */ |
937 | #define FIRST_LO_REGNUM 0 | |
6d3d9133 | 938 | #define LAST_LO_REGNUM 7 |
c769a35d RE |
939 | #define FIRST_HI_REGNUM 8 |
940 | #define LAST_HI_REGNUM 11 | |
6d3d9133 | 941 | |
f0a0390e RH |
942 | /* Overridden by config/arm/bpabi.h. */ |
943 | #ifndef ARM_UNWIND_INFO | |
944 | #define ARM_UNWIND_INFO 0 | |
617a1b71 PB |
945 | #endif |
946 | ||
c9ca9b88 PB |
947 | /* Use r0 and r1 to pass exception handling information. */ |
948 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
949 | ||
6d3d9133 | 950 | /* The register that holds the return address in exception handlers. */ |
c9ca9b88 PB |
951 | #define ARM_EH_STACKADJ_REGNUM 2 |
952 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
35d965d5 | 953 | |
1e874273 PB |
954 | #ifndef ARM_TARGET2_DWARF_FORMAT |
955 | #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel | |
3f2f838e | 956 | #endif |
1e874273 PB |
957 | |
958 | /* ttype entries (the only interesting data references used) | |
959 | use TARGET2 relocations. */ | |
960 | #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ | |
961 | (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ | |
962 | : DW_EH_PE_absptr) | |
1e874273 | 963 | |
d5b7b3ae RE |
964 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
965 | as an invisible last argument (possible since varargs don't exist in | |
966 | Pascal), so the following is not true. */ | |
5b3e6663 | 967 | #define STATIC_CHAIN_REGNUM 12 |
35d965d5 | 968 | |
8b63716e CL |
969 | /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ |
970 | #define FDPIC_REGNUM 9 | |
971 | ||
d5b7b3ae RE |
972 | /* Define this to be where the real frame pointer is if it is not possible to |
973 | work out the offset between the frame pointer and the automatic variables | |
974 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
975 | should point to a special register that we will make sure is eliminated. | |
976 | ||
977 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 978 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
979 | as base register for addressing purposes. (See comments in |
980 | find_reloads_address()). But - the Thumb does not allow high registers, | |
981 | including r11, to be used as base address registers. Hence our problem. | |
982 | ||
983 | The solution used here, and in the old thumb port is to use r7 instead of | |
984 | r11 as the hard frame pointer and to have special code to generate | |
985 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 986 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
987 | pointer. */ |
988 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
989 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 990 | |
b15bca31 RE |
991 | #define HARD_FRAME_POINTER_REGNUM \ |
992 | (TARGET_ARM \ | |
993 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
994 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 995 | |
e3339d0f JM |
996 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
997 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
998 | ||
b15bca31 | 999 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 1000 | |
b15bca31 RE |
1001 | /* Register to use for pushing function arguments. */ |
1002 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae | 1003 | |
0be8bd1a RE |
1004 | #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) |
1005 | #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) | |
a76213b9 XQ |
1006 | |
1007 | /* Need to sync with WCGR in iwmmxt.md. */ | |
0be8bd1a RE |
1008 | #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) |
1009 | #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) | |
d5b7b3ae | 1010 | |
5a9335ef NC |
1011 | #define IS_IWMMXT_REGNUM(REGNUM) \ |
1012 | (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
1013 | #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
1014 | (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
1015 | ||
35d965d5 | 1016 | /* Base register for access to local variables of the function. */ |
0be8bd1a | 1017 | #define FRAME_POINTER_REGNUM 102 |
ff9940b0 | 1018 | |
d5b7b3ae | 1019 | /* Base register for access to arguments of the function. */ |
0be8bd1a | 1020 | #define ARG_POINTER_REGNUM 103 |
62b10bbc | 1021 | |
0be8bd1a RE |
1022 | #define FIRST_VFP_REGNUM 16 |
1023 | #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) | |
f1adb0a9 | 1024 | #define LAST_VFP_REGNUM \ |
302c3d8e | 1025 | (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) |
f1adb0a9 | 1026 | |
9b66ebb1 PB |
1027 | #define IS_VFP_REGNUM(REGNUM) \ |
1028 | (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
1029 | ||
f1adb0a9 JB |
1030 | /* VFP registers are split into two types: those defined by VFP versions < 3 |
1031 | have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
1032 | defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
1033 | in various parts of the backend, we implement as "fake" single-precision | |
1034 | registers (which would be S32-S63, but cannot be used in that way). The | |
1035 | following macros define these ranges of registers. */ | |
0be8bd1a RE |
1036 | #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) |
1037 | #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) | |
1038 | #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) | |
f1adb0a9 JB |
1039 | |
1040 | #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
1041 | ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
1042 | ||
1043 | /* DFmode values are only valid in even register pairs. */ | |
1044 | #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
1045 | ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
1046 | ||
88f77cba JB |
1047 | /* Neon Quad values must start at a multiple of four registers. */ |
1048 | #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
1049 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
1050 | ||
1051 | /* Neon structures of vectors must be in even register pairs and there | |
1052 | must be enough registers available. Because of various patterns | |
1053 | requiring quad registers, we require them to start at a multiple of | |
1054 | four. */ | |
1055 | #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
1056 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
1057 | && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
1058 | ||
16155ccf | 1059 | /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP |
63c8f7d6 | 1060 | + 1 APSRQ + 1 APSRGE + 1 VPR. */ |
5a9335ef | 1061 | /* Intel Wireless MMX Technology registers add 16 + 4 more. */ |
0be8bd1a | 1062 | /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ |
63c8f7d6 | 1063 | #define FIRST_PSEUDO_REGISTER 107 |
62b10bbc | 1064 | |
2fa330b2 PB |
1065 | #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) |
1066 | ||
35d965d5 RS |
1067 | /* Value should be nonzero if functions must have frame pointers. |
1068 | Zero means the frame pointer need not be set up (and parms may be accessed | |
f676971a | 1069 | via the stack pointer) in functions that seem suitable. |
ff9940b0 RE |
1070 | If we have to have a frame pointer we might as well make use of it. |
1071 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 1072 | functions, or simple tail call functions. */ |
a15900b5 DJ |
1073 | |
1074 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1075 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1076 | #endif | |
1077 | ||
5a9335ef | 1078 | #define VALID_IWMMXT_REG_MODE(MODE) \ |
f676971a | 1079 | (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) |
5a9335ef | 1080 | |
88f77cba JB |
1081 | /* Modes valid for Neon D registers. */ |
1082 | #define VALID_NEON_DREG_MODE(MODE) \ | |
1083 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
2e87b2f4 SMW |
1084 | || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ |
1085 | || (MODE) == V4BFmode) | |
88f77cba JB |
1086 | |
1087 | /* Modes valid for Neon Q registers. */ | |
1088 | #define VALID_NEON_QREG_MODE(MODE) \ | |
1089 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
2e87b2f4 SMW |
1090 | || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ |
1091 | || (MODE) == V8BFmode) | |
88f77cba | 1092 | |
63c8f7d6 SP |
1093 | #define VALID_MVE_MODE(MODE) \ |
1094 | ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ | |
1095 | || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ | |
1096 | || (MODE) == V2DFmode) | |
1097 | ||
1098 | #define VALID_MVE_SI_MODE(MODE) \ | |
1099 | ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ | |
1100 | || (MODE) == V16QImode) | |
1101 | ||
1102 | #define VALID_MVE_SF_MODE(MODE) \ | |
1103 | ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) | |
1104 | ||
88f77cba JB |
1105 | /* Structure modes valid for Neon registers. */ |
1106 | #define VALID_NEON_STRUCT_MODE(MODE) \ | |
1107 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
1108 | || (MODE) == CImode || (MODE) == XImode) | |
1109 | ||
63c8f7d6 SP |
1110 | #define VALID_MVE_STRUCT_MODE(MODE) \ |
1111 | ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) | |
1112 | ||
95e10b8a RS |
1113 | /* The conditions under which vector modes are supported for general |
1114 | arithmetic using Neon. */ | |
1115 | ||
1116 | #define ARM_HAVE_NEON_V8QI_ARITH TARGET_NEON | |
1117 | #define ARM_HAVE_NEON_V4HI_ARITH TARGET_NEON | |
1118 | #define ARM_HAVE_NEON_V2SI_ARITH TARGET_NEON | |
1119 | ||
1120 | #define ARM_HAVE_NEON_V16QI_ARITH TARGET_NEON | |
1121 | #define ARM_HAVE_NEON_V8HI_ARITH TARGET_NEON | |
1122 | #define ARM_HAVE_NEON_V4SI_ARITH TARGET_NEON | |
1123 | #define ARM_HAVE_NEON_V2DI_ARITH TARGET_NEON | |
1124 | ||
1125 | /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */ | |
1126 | #define ARM_HAVE_NEON_V4HF_ARITH TARGET_NEON_FP16INST | |
1127 | #define ARM_HAVE_NEON_V8HF_ARITH TARGET_NEON_FP16INST | |
1128 | ||
1129 | /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can | |
1130 | only use them for general arithmetic when -funsafe-math-optimizations | |
1131 | is in effect. */ | |
1132 | #define ARM_HAVE_NEON_V2SF_ARITH \ | |
1133 | (TARGET_NEON && flag_unsafe_math_optimizations) | |
1134 | #define ARM_HAVE_NEON_V4SF_ARITH ARM_HAVE_NEON_V2SF_ARITH | |
1135 | ||
1136 | /* The conditions under which vector modes are supported for general | |
1137 | arithmetic by any vector extension. */ | |
1138 | ||
1139 | #define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) | |
1140 | #define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) | |
1141 | #define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) | |
1142 | ||
1143 | #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) | |
1144 | #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) | |
1145 | #define ARM_HAVE_V4SI_ARITH (ARM_HAVE_NEON_V4SI_ARITH || TARGET_HAVE_MVE) | |
1146 | #define ARM_HAVE_V2DI_ARITH ARM_HAVE_NEON_V2DI_ARITH | |
1147 | ||
1148 | #define ARM_HAVE_V4HF_ARITH ARM_HAVE_NEON_V4HF_ARITH | |
1149 | #define ARM_HAVE_V2SF_ARITH ARM_HAVE_NEON_V2SF_ARITH | |
1150 | ||
1151 | #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT) | |
1152 | #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT) | |
1153 | ||
25bef689 CL |
1154 | /* The conditions under which vector modes are supported by load/store |
1155 | instructions using Neon. */ | |
1156 | ||
1157 | #define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON | |
1158 | #define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON | |
1159 | #define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON | |
1160 | #define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON | |
1161 | #define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON | |
1162 | #define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON | |
1163 | #define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST | |
1164 | #define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST | |
1165 | #define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD | |
1166 | #define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD | |
1167 | #define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON | |
1168 | #define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON | |
1169 | #define ARM_HAVE_NEON_DI_LDST TARGET_NEON | |
1170 | #define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON | |
1171 | ||
1172 | /* The conditions under which vector modes are supported by load/store | |
1173 | instructions by any vector extension. */ | |
1174 | ||
1175 | #define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) | |
1176 | #define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) | |
1177 | #define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) | |
1178 | ||
1179 | #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) | |
1180 | #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) | |
1181 | #define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE) | |
1182 | #define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST | |
1183 | #define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST | |
1184 | ||
1185 | #define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST | |
1186 | #define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST | |
1187 | ||
1188 | #define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST | |
1189 | #define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST | |
1190 | ||
1191 | #define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT) | |
1192 | #define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT) | |
1193 | ||
37119410 BS |
1194 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
1195 | extern int arm_regs_in_sequence[]; | |
1196 | ||
35d965d5 | 1197 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1198 | since no saving is required (though calls clobber it) and it never contains |
1199 | function parameters. It is quite good to use lr since other calls may | |
f676971a | 1200 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is |
ff9940b0 | 1201 | least likely to contain a function parameter; in addition results are |
f1adb0a9 JB |
1202 | returned in r0. |
1203 | For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
1204 | then D8-D15. The reason for doing this is to attempt to reduce register | |
1205 | pressure when both single- and double-precision registers are used in a | |
1206 | function. */ | |
1207 | ||
0be8bd1a RE |
1208 | #define VREG(X) (FIRST_VFP_REGNUM + (X)) |
1209 | #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) | |
1210 | #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) | |
1211 | ||
f1adb0a9 JB |
1212 | #define REG_ALLOC_ORDER \ |
1213 | { \ | |
0be8bd1a RE |
1214 | /* General registers. */ \ |
1215 | 3, 2, 1, 0, 12, 14, 4, 5, \ | |
1216 | 6, 7, 8, 9, 10, 11, \ | |
1217 | /* High VFP registers. */ \ | |
1218 | VREG(32), VREG(33), VREG(34), VREG(35), \ | |
1219 | VREG(36), VREG(37), VREG(38), VREG(39), \ | |
1220 | VREG(40), VREG(41), VREG(42), VREG(43), \ | |
1221 | VREG(44), VREG(45), VREG(46), VREG(47), \ | |
1222 | VREG(48), VREG(49), VREG(50), VREG(51), \ | |
1223 | VREG(52), VREG(53), VREG(54), VREG(55), \ | |
1224 | VREG(56), VREG(57), VREG(58), VREG(59), \ | |
1225 | VREG(60), VREG(61), VREG(62), VREG(63), \ | |
1226 | /* VFP argument registers. */ \ | |
1227 | VREG(15), VREG(14), VREG(13), VREG(12), \ | |
1228 | VREG(11), VREG(10), VREG(9), VREG(8), \ | |
1229 | VREG(7), VREG(6), VREG(5), VREG(4), \ | |
1230 | VREG(3), VREG(2), VREG(1), VREG(0), \ | |
1231 | /* VFP call-saved registers. */ \ | |
1232 | VREG(16), VREG(17), VREG(18), VREG(19), \ | |
1233 | VREG(20), VREG(21), VREG(22), VREG(23), \ | |
1234 | VREG(24), VREG(25), VREG(26), VREG(27), \ | |
1235 | VREG(28), VREG(29), VREG(30), VREG(31), \ | |
1236 | /* IWMMX registers. */ \ | |
1237 | WREG(0), WREG(1), WREG(2), WREG(3), \ | |
1238 | WREG(4), WREG(5), WREG(6), WREG(7), \ | |
1239 | WREG(8), WREG(9), WREG(10), WREG(11), \ | |
1240 | WREG(12), WREG(13), WREG(14), WREG(15), \ | |
1241 | WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ | |
1242 | /* Registers not for general use. */ \ | |
1243 | CC_REGNUM, VFPCC_REGNUM, \ | |
1244 | FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ | |
63c8f7d6 SP |
1245 | SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ |
1246 | APSRGE_REGNUM, VPR_REGNUM \ | |
35d965d5 | 1247 | } |
9338ffe6 | 1248 | |
63c8f7d6 SP |
1249 | #define IS_VPR_REGNUM(REGNUM) \ |
1250 | ((REGNUM) == VPR_REGNUM) | |
1251 | ||
795dc4fc | 1252 | /* Use different register alloc ordering for Thumb. */ |
5a733826 BS |
1253 | #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () |
1254 | ||
3635c2bf WD |
1255 | /* Tell IRA to use the order we define when optimizing for size. */ |
1256 | #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) | |
795dc4fc | 1257 | |
9338ffe6 PB |
1258 | /* Interrupt functions can only use registers that have already been |
1259 | saved by the prologue, even if they would normally be | |
1260 | call-clobbered. */ | |
1261 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1262 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
6fb5fa3c | 1263 | df_regs_ever_live_p (DST)) |
35d965d5 RS |
1264 | \f |
1265 | /* Register and constant classes. */ | |
1266 | ||
0be8bd1a | 1267 | /* Register classes. */ |
35d965d5 RS |
1268 | enum reg_class |
1269 | { | |
1270 | NO_REGS, | |
0be8bd1a RE |
1271 | LO_REGS, |
1272 | STACK_REG, | |
1273 | BASE_REGS, | |
1274 | HI_REGS, | |
9adcfa3c | 1275 | CALLER_SAVE_REGS, |
6df4618c | 1276 | EVEN_REG, |
0be8bd1a RE |
1277 | GENERAL_REGS, |
1278 | CORE_REGS, | |
f1adb0a9 JB |
1279 | VFP_D0_D7_REGS, |
1280 | VFP_LO_REGS, | |
1281 | VFP_HI_REGS, | |
9b66ebb1 | 1282 | VFP_REGS, |
5a9335ef | 1283 | IWMMXT_REGS, |
0be8bd1a | 1284 | IWMMXT_GR_REGS, |
d5b7b3ae | 1285 | CC_REG, |
9b66ebb1 | 1286 | VFPCC_REG, |
0be8bd1a RE |
1287 | SFP_REG, |
1288 | AFP_REG, | |
63c8f7d6 | 1289 | VPR_REG, |
35d965d5 RS |
1290 | ALL_REGS, |
1291 | LIM_REG_CLASSES | |
1292 | }; | |
1293 | ||
1294 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1295 | ||
d6b4baa4 | 1296 | /* Give names of register classes as strings for dump file. */ |
63c8f7d6 | 1297 | #define REG_CLASS_NAMES \ |
35d965d5 RS |
1298 | { \ |
1299 | "NO_REGS", \ | |
0be8bd1a RE |
1300 | "LO_REGS", \ |
1301 | "STACK_REG", \ | |
1302 | "BASE_REGS", \ | |
1303 | "HI_REGS", \ | |
9adcfa3c | 1304 | "CALLER_SAVE_REGS", \ |
6df4618c | 1305 | "EVEN_REG", \ |
0be8bd1a RE |
1306 | "GENERAL_REGS", \ |
1307 | "CORE_REGS", \ | |
f1adb0a9 JB |
1308 | "VFP_D0_D7_REGS", \ |
1309 | "VFP_LO_REGS", \ | |
1310 | "VFP_HI_REGS", \ | |
9b66ebb1 | 1311 | "VFP_REGS", \ |
5a9335ef | 1312 | "IWMMXT_REGS", \ |
0be8bd1a | 1313 | "IWMMXT_GR_REGS", \ |
d5b7b3ae | 1314 | "CC_REG", \ |
5384443a | 1315 | "VFPCC_REG", \ |
9f4f1735 JJ |
1316 | "SFP_REG", \ |
1317 | "AFP_REG", \ | |
63c8f7d6 | 1318 | "VPR_REG", \ |
9f4f1735 | 1319 | "ALL_REGS" \ |
35d965d5 RS |
1320 | } |
1321 | ||
1322 | /* Define which registers fit in which classes. | |
1323 | This is an initializer for a vector of HARD_REG_SET | |
1324 | of length N_REG_CLASSES. */ | |
f1adb0a9 JB |
1325 | #define REG_CLASS_CONTENTS \ |
1326 | { \ | |
1327 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
f1adb0a9 JB |
1328 | { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ |
1329 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
1330 | { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
0be8bd1a | 1331 | { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ |
9adcfa3c | 1332 | { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ |
6df4618c | 1333 | { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ |
0be8bd1a RE |
1334 | { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
1335 | { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | |
1336 | { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
1337 | { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ | |
1338 | { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ | |
1339 | { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ | |
1340 | { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
1341 | { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ | |
1342 | { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ | |
1343 | { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ | |
1344 | { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ | |
1345 | { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ | |
63c8f7d6 SP |
1346 | { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ |
1347 | { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ | |
35d965d5 | 1348 | } |
4b02997f | 1349 | |
e0e4be48 MI |
1350 | #define FP_SYSREGS \ |
1351 | DEF_FP_SYSREG (FPSCR) \ | |
1352 | DEF_FP_SYSREG (FPSCR_nzcvqc) \ | |
1353 | DEF_FP_SYSREG (VPR) \ | |
1354 | DEF_FP_SYSREG (P0) \ | |
1355 | DEF_FP_SYSREG (FPCXTNS) \ | |
1356 | DEF_FP_SYSREG (FPCXTS) | |
1357 | ||
1358 | #define DEF_FP_SYSREG(reg) reg ## _ENUM, | |
1359 | enum vfp_sysregs_encoding { | |
1360 | FP_SYSREGS | |
1361 | NB_FP_SYSREGS | |
1362 | }; | |
1363 | #undef DEF_FP_SYSREG | |
1364 | extern const char *fp_sysreg_names[NB_FP_SYSREGS]; | |
1365 | ||
f1adb0a9 JB |
1366 | /* Any of the VFP register classes. */ |
1367 | #define IS_VFP_CLASS(X) \ | |
1368 | ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
1369 | || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
1370 | ||
35d965d5 RS |
1371 | /* The same information, inverted: |
1372 | Return the class number of the smallest class containing | |
1373 | reg number REGNO. This could be a conditional expression | |
1374 | or could index an array. */ | |
d5b7b3ae | 1375 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1376 | |
1377 | /* The class value for index registers, and the one for base regs. */ | |
5b3e6663 | 1378 | #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) |
f5c630c3 | 1379 | #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) |
d5b7b3ae | 1380 | |
b93a0fe6 | 1381 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1382 | when addressing quantities in QI or HI mode; if we don't know the |
d91524d5 SP |
1383 | mode, then we must be conservative. For MVE we need to load from |
1384 | memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ | |
c896d4b4 | 1385 | #define MODE_BASE_REG_CLASS(MODE) \ |
d91524d5 SP |
1386 | (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ |
1387 | :(TARGET_32BIT ? CORE_REGS \ | |
c896d4b4 | 1388 | : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ |
d91524d5 | 1389 | : LO_REGS)) |
888d2cd6 | 1390 | |
67914693 | 1391 | /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS |
888d2cd6 DJ |
1392 | instead of BASE_REGS. */ |
1393 | #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
3dcc68a4 | 1394 | |
42db504c | 1395 | /* When this hook returns true for MODE, the compiler allows |
d5b7b3ae RE |
1396 | registers explicitly used in the rtl to be used as spill registers |
1397 | but prevents the compiler from extending the lifetime of these | |
d6b4baa4 | 1398 | registers. */ |
42db504c SB |
1399 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
1400 | arm_small_register_classes_for_mode_p | |
35d965d5 | 1401 | |
d5b7b3ae RE |
1402 | /* Must leave BASE_REGS reloads alone */ |
1403 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
78a14aa8 YR |
1404 | (lra_in_progress ? NO_REGS \ |
1405 | : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1406 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
a93072ca | 1407 | : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ |
78a14aa8 YR |
1408 | : NO_REGS)) \ |
1409 | : NO_REGS)) | |
d5b7b3ae RE |
1410 | |
1411 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1fc017b6 VM |
1412 | (lra_in_progress ? NO_REGS \ |
1413 | : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1414 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
a93072ca | 1415 | : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ |
1fc017b6 VM |
1416 | : NO_REGS)) \ |
1417 | : NO_REGS) | |
35d965d5 | 1418 | |
ff9940b0 RE |
1419 | /* Return the register class of a scratch register needed to copy IN into |
1420 | or out of a register in CLASS in MODE. If it can be done directly, | |
1421 | NO_REGS is returned. */ | |
d5b7b3ae | 1422 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1423 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
00ea1506 | 1424 | ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1425 | ? coproc_secondary_reload_class (MODE, X, FALSE) \ |
1426 | : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
1427 | ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
5b3e6663 | 1428 | : TARGET_32BIT \ |
9b66ebb1 | 1429 | ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ |
d5b7b3ae RE |
1430 | ? GENERAL_REGS : NO_REGS) \ |
1431 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
f676971a | 1432 | |
d6b4baa4 | 1433 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1434 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1435 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
00ea1506 | 1436 | ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1437 | ? coproc_secondary_reload_class (MODE, X, FALSE) : \ |
1438 | (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
1439 | coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
0be8bd1a RE |
1440 | (TARGET_32BIT ? \ |
1441 | (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ | |
1442 | && CONSTANT_P (X)) \ | |
9b6b54e2 | 1443 | ? GENERAL_REGS : \ |
0be8bd1a | 1444 | (((MODE) == HImode && ! arm_arch4 \ |
d435a4be KT |
1445 | && (MEM_P (X) \ |
1446 | || ((REG_P (X) || GET_CODE (X) == SUBREG) \ | |
0be8bd1a RE |
1447 | && true_regnum (X) == -1))) \ |
1448 | ? GENERAL_REGS : NO_REGS) \ | |
1449 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) | |
2ce9c1b9 | 1450 | |
35d965d5 RS |
1451 | /* Return the maximum number of consecutive registers |
1452 | needed to represent mode MODE in a register of class CLASS. | |
0be8bd1a RE |
1453 | ARM regs are UNITS_PER_WORD bits. |
1454 | FIXME: Is this true for iWMMX? */ | |
35d965d5 | 1455 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
0be8bd1a | 1456 | (ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1457 | |
1458 | /* If defined, gives a class of registers that cannot be used as the | |
1459 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 RS |
1460 | \f |
1461 | /* Stack layout; function entry, exit and calling. */ | |
1462 | ||
1463 | /* Define this if pushing a word on the stack | |
1464 | makes the stack pointer a smaller address. */ | |
1465 | #define STACK_GROWS_DOWNWARD 1 | |
1466 | ||
a4d05547 | 1467 | /* Define this to nonzero if the nominal address of the stack frame |
35d965d5 RS |
1468 | is at the high-address end of the local variables; |
1469 | that is, each additional local variable allocated | |
1470 | goes at a more negative offset in the frame. */ | |
1471 | #define FRAME_GROWS_DOWNWARD 1 | |
1472 | ||
a2503645 RS |
1473 | /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). |
1474 | When present, it is one word in size, and sits at the top of the frame, | |
1475 | between the soft frame pointer and either r7 or r11. | |
1476 | ||
1477 | We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
1478 | and only then if some outgoing arguments are passed on the stack. It would | |
1479 | be tempting to also check whether the stack arguments are passed by indirect | |
1480 | calls, but there seems to be no reason in principle why a post-reload pass | |
1481 | couldn't convert a direct call into an indirect one. */ | |
1482 | #define CALLER_INTERWORKING_SLOT_SIZE \ | |
1483 | (TARGET_CALLER_INTERWORKING \ | |
a20c5714 | 1484 | && maybe_ne (crtl->outgoing_args_size, 0) \ |
a2503645 RS |
1485 | ? UNITS_PER_WORD : 0) |
1486 | ||
35d965d5 RS |
1487 | /* If we generate an insn to push BYTES bytes, |
1488 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae | 1489 | /* The push insns do not do this rounding implicitly. |
d6b4baa4 | 1490 | So don't define this. */ |
0c2ca901 | 1491 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1492 | |
1493 | /* Define this if the maximum size of all the outgoing args is to be | |
1494 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1495 | found in the variable crtl->outgoing_args_size. */ |
6cfc7210 | 1496 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1497 | |
1498 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1499 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 | 1500 | |
9f7bf991 RE |
1501 | /* Amount of memory needed for an untyped call to save all possible return |
1502 | registers. */ | |
1503 | #define APPLY_RESULT_SIZE arm_apply_result_size() | |
1504 | ||
11c1a207 RE |
1505 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return |
1506 | values must be in memory. On the ARM, they need only do so if larger | |
d6b4baa4 | 1507 | than a word, or if they contain elements offset from zero in the struct. */ |
11c1a207 RE |
1508 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
1509 | ||
6d3d9133 | 1510 | /* These bits describe the different types of function supported |
112cdef5 | 1511 | by the ARM backend. They are exclusive. i.e. a function cannot be both a |
6d3d9133 NC |
1512 | normal function and an interworked function, for example. Knowing the |
1513 | type of a function is important for determining its prologue and | |
1514 | epilogue sequences. | |
1515 | Note value 7 is currently unassigned. Also note that the interrupt | |
1516 | function types all have bit 2 set, so that they can be tested for easily. | |
1517 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1518 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1519 | default to unknown. This will force the first use of arm_current_func_type |
1520 | to call arm_compute_func_type. */ | |
1521 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1522 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1523 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
6d3d9133 NC |
1524 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ |
1525 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1526 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1527 | ||
1528 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1529 | ||
1530 | /* In addition functions can have several type modifiers, | |
1531 | outlined by these bit masks: */ | |
1532 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1533 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1534 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
d6b4baa4 | 1535 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ |
5b3e6663 | 1536 | #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ |
97b0656d | 1537 | #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ |
6d3d9133 NC |
1538 | |
1539 | /* Some macros to test these flags. */ | |
1540 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1541 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1542 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1543 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1544 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
5b3e6663 | 1545 | #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) |
97b0656d | 1546 | #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) |
6d3d9133 | 1547 | |
5848830f PB |
1548 | |
1549 | /* Structure used to hold the function stack frame layout. Offsets are | |
1550 | relative to the stack pointer on function entry. Positive offsets are | |
1551 | in the direction of stack growth. | |
1552 | Only soft_frame is used in thumb mode. */ | |
1553 | ||
d1b38208 | 1554 | typedef struct GTY(()) arm_stack_offsets |
5848830f PB |
1555 | { |
1556 | int saved_args; /* ARG_POINTER_REGNUM. */ | |
1557 | int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
1558 | int saved_regs; | |
1559 | int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
2591db65 | 1560 | int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ |
5848830f | 1561 | int outgoing_args; /* STACK_POINTER_REGNUM. */ |
954954d1 | 1562 | unsigned int saved_regs_mask; |
5848830f PB |
1563 | } |
1564 | arm_stack_offsets; | |
1565 | ||
2c0122c9 | 1566 | #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) |
6d3d9133 NC |
1567 | /* A C structure for machine-specific, per-function data. |
1568 | This is added to the cfun structure. */ | |
d1b38208 | 1569 | typedef struct GTY(()) machine_function |
d5b7b3ae | 1570 | { |
6bc82793 | 1571 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1572 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1573 | /* Records if LR has to be saved for far jumps. */ |
1574 | int far_jump_used; | |
1575 | /* Records if ARG_POINTER was ever live. */ | |
1576 | int arg_pointer_live; | |
6f7ebcbb NC |
1577 | /* Records if the save of LR has been eliminated. */ |
1578 | int lr_save_eliminated; | |
0977774b | 1579 | /* The size of the stack frame. Only valid after reload. */ |
5848830f | 1580 | arm_stack_offsets stack_offsets; |
6d3d9133 NC |
1581 | /* Records the type of the current function. */ |
1582 | unsigned long func_type; | |
3cb66fd7 NC |
1583 | /* Record if the function has a variable argument list. */ |
1584 | int uses_anonymous_args; | |
5a9335ef NC |
1585 | /* Records if sibcalls are blocked because an argument |
1586 | register is needed to preserve stack alignment. */ | |
1587 | int sibcall_blocked; | |
020a4035 RE |
1588 | /* The PIC register for this function. This might be a pseudo. */ |
1589 | rtx pic_reg; | |
b12a00f1 | 1590 | /* Labels for per-function Thumb call-via stubs. One per potential calling |
57ecec57 PB |
1591 | register. We can never call via LR or PC. We can call via SP if a |
1592 | trampoline happens to be on the top of the stack. */ | |
1593 | rtx call_via[14]; | |
934c2060 RR |
1594 | /* Set to 1 when a return insn is output, this means that the epilogue |
1595 | is not needed. */ | |
1596 | int return_used_this_function; | |
906668bb BS |
1597 | /* When outputting Thumb-1 code, record the last insn that provides |
1598 | information about condition codes, and the comparison operands. */ | |
1599 | rtx thumb1_cc_insn; | |
1600 | rtx thumb1_cc_op0; | |
1601 | rtx thumb1_cc_op1; | |
1602 | /* Also record the CC mode that is supported. */ | |
ef4bddc2 | 1603 | machine_mode thumb1_cc_mode; |
b0419491 TG |
1604 | /* Set to 1 after arm_reorg has started. */ |
1605 | int after_arm_reorg; | |
bb4ac03b SD |
1606 | /* The number of bytes used to store the static chain register on the |
1607 | stack, above the stack frame. */ | |
1608 | int static_chain_stack_bytes; | |
6d3d9133 NC |
1609 | } |
1610 | machine_function; | |
906668bb | 1611 | #endif |
d5b7b3ae | 1612 | |
cf16f980 | 1613 | #define ARM_Q_BIT_READ (arm_q_bit_access ()) |
16155ccf | 1614 | #define ARM_GE_BITS_READ (arm_ge_bits_access ()) |
cf16f980 | 1615 | |
b12a00f1 | 1616 | /* As in the machine_function, a global set of call-via labels, for code |
d6b5193b | 1617 | that is in text_section. */ |
57ecec57 | 1618 | extern GTY(()) rtx thumb_call_via_label[14]; |
b12a00f1 | 1619 | |
390b17c2 RE |
1620 | /* The number of potential ways of assigning to a co-processor. */ |
1621 | #define ARM_NUM_COPROC_SLOTS 1 | |
1622 | ||
1623 | /* Enumeration of procedure calling standard variants. We don't really | |
1624 | support all of these yet. */ | |
1625 | enum arm_pcs | |
1626 | { | |
1627 | ARM_PCS_AAPCS, /* Base standard AAPCS. */ | |
1628 | ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ | |
1629 | ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ | |
1630 | /* This must be the last AAPCS variant. */ | |
1631 | ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ | |
1632 | ARM_PCS_ATPCS, /* ATPCS. */ | |
1633 | ARM_PCS_APCS, /* APCS (legacy Linux etc). */ | |
1634 | ARM_PCS_UNKNOWN | |
1635 | }; | |
1636 | ||
12ffc7d5 CLT |
1637 | /* Default procedure calling standard of current compilation unit. */ |
1638 | extern enum arm_pcs arm_pcs_default; | |
1639 | ||
2c0122c9 | 1640 | #if !defined (USED_FOR_TARGET) |
82e9d970 | 1641 | /* A C type for declaring a variable that is used as the first argument of |
390b17c2 | 1642 | `FUNCTION_ARG' and other related values. */ |
82e9d970 PB |
1643 | typedef struct |
1644 | { | |
d5b7b3ae | 1645 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1646 | int nregs; |
5a9335ef NC |
1647 | /* This is the number of iWMMXt register arguments scanned so far. */ |
1648 | int iwmmxt_nregs; | |
1649 | int named_count; | |
1650 | int nargs; | |
390b17c2 RE |
1651 | /* Which procedure call variant to use for this call. */ |
1652 | enum arm_pcs pcs_variant; | |
1653 | ||
1654 | /* AAPCS related state tracking. */ | |
1655 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
1656 | int aapcs_cprc_slot; /* Index of co-processor rules to handle | |
1657 | this argument, or -1 if using core | |
1658 | registers. */ | |
1659 | int aapcs_ncrn; | |
1660 | int aapcs_next_ncrn; | |
1661 | rtx aapcs_reg; /* Register assigned to this argument. */ | |
1662 | int aapcs_partial; /* How many bytes are passed in regs (if | |
1663 | split between core regs and stack. | |
1664 | Zero otherwise. */ | |
1665 | int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; | |
1666 | int can_split; /* Argument can be split between core regs | |
1667 | and the stack. */ | |
1668 | /* Private data for tracking VFP register allocation */ | |
1669 | unsigned aapcs_vfp_regs_free; | |
1670 | unsigned aapcs_vfp_reg_alloc; | |
1671 | int aapcs_vfp_rcount; | |
46107b99 | 1672 | MACHMODE aapcs_vfp_rmode; |
d5b7b3ae | 1673 | } CUMULATIVE_ARGS; |
2c0122c9 | 1674 | #endif |
82e9d970 | 1675 | |
866af8a9 | 1676 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
76b0cbf8 | 1677 | (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) |
866af8a9 JB |
1678 | |
1679 | /* For AAPCS, padding should never be below the argument. For other ABIs, | |
1680 | * mimic the default. */ | |
1681 | #define PAD_VARARGS_DOWN \ | |
1682 | ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
1683 | ||
35d965d5 RS |
1684 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1685 | for a call to a function whose data type is FNTYPE. | |
1686 | For a library call, FNTYPE is 0. | |
1687 | On the ARM, the offset starts at 0. */ | |
0f6937fe | 1688 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1689 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
35d965d5 | 1690 | |
35d965d5 RS |
1691 | /* 1 if N is a possible register number for function argument passing. |
1692 | On the ARM, r0-r3 are used to pass args. */ | |
390b17c2 RE |
1693 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
1694 | (IN_RANGE ((REGNO), 0, 3) \ | |
00ea1506 | 1695 | || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ |
390b17c2 RE |
1696 | && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ |
1697 | || (TARGET_IWMMXT_ABI \ | |
5848830f | 1698 | && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
35d965d5 | 1699 | |
f99fce0c | 1700 | \f |
afef3d7a | 1701 | /* If your target environment doesn't prefix user functions with an |
96a3900d | 1702 | underscore, you may wish to re-define this to prevent any conflicts. */ |
afef3d7a NC |
1703 | #ifndef ARM_MCOUNT_NAME |
1704 | #define ARM_MCOUNT_NAME "*mcount" | |
1705 | #endif | |
1706 | ||
1707 | /* Call the function profiler with a given profile label. The Acorn | |
1708 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1709 | On the ARM the full profile code will look like: | |
1710 | .data | |
1711 | LP1 | |
1712 | .word 0 | |
1713 | .text | |
1714 | mov ip, lr | |
1715 | bl mcount | |
1716 | .word LP1 | |
1717 | ||
e53b6e56 | 1718 | profile_function() in final.cc outputs the .data section, FUNCTION_PROFILER |
afef3d7a NC |
1719 | will output the .text section. |
1720 | ||
1721 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1722 | ``prof'' doesn't seem to mind about this! |
1723 | ||
1724 | Note - this version of the code is designed to work in both ARM and | |
1725 | Thumb modes. */ | |
be393ecf | 1726 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1727 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1728 | { \ |
1729 | char temp[20]; \ | |
1730 | rtx sym; \ | |
1731 | \ | |
dd18ae56 | 1732 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1733 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1734 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1735 | fputc ('\n', STREAM); \ | |
1736 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
f1c25d3b | 1737 | sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ |
301d03af | 1738 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1739 | } |
be393ecf | 1740 | #endif |
35d965d5 | 1741 | |
59be6073 | 1742 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1743 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1744 | if (TARGET_ARM) \ | |
1745 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1746 | else \ | |
1747 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1748 | #else |
1749 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1750 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1751 | #endif | |
d5b7b3ae | 1752 | |
35d965d5 RS |
1753 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1754 | the stack pointer does not matter. The value is tested only in | |
1755 | functions that have frame pointers. | |
1756 | No definition is equivalent to always zero. | |
1757 | ||
1758 | On the ARM, the function epilogue recovers the stack pointer from the | |
1759 | frame. */ | |
1760 | #define EXIT_IGNORE_STACK 1 | |
1761 | ||
2b261262 | 1762 | #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) |
c7861455 | 1763 | |
35d965d5 RS |
1764 | /* Determine if the epilogue should be output as RTL. |
1765 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae | 1766 | #define USE_RETURN_INSN(ISCOND) \ |
7c19c715 | 1767 | (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) |
ff9940b0 RE |
1768 | |
1769 | /* Definitions for register eliminations. | |
1770 | ||
1771 | This is an array of structures. Each structure initializes one pair | |
1772 | of eliminable registers. The "from" register number is given first, | |
1773 | followed by "to". Eliminations of the same "from" register are listed | |
1774 | in order of preference. | |
1775 | ||
1776 | We have two registers that can be eliminated on the ARM. First, the | |
1777 | arg pointer register can often be eliminated in favor of the stack | |
1778 | pointer register. Secondly, the pseudo frame pointer register can always | |
1779 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1780 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1781 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1782 | |
d5b7b3ae RE |
1783 | #define ELIMINABLE_REGS \ |
1784 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1785 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1786 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1787 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1788 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1789 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1790 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1791 | |
d5b7b3ae RE |
1792 | /* Define the offset between two registers, one to be eliminated, and the |
1793 | other its replacement, at the start of a routine. */ | |
d5b7b3ae RE |
1794 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1795 | if (TARGET_ARM) \ | |
5848830f | 1796 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
d5b7b3ae | 1797 | else \ |
5848830f PB |
1798 | (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) |
1799 | ||
d5b7b3ae RE |
1800 | /* Special case handling of the location of arguments passed on the stack. */ |
1801 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
f676971a | 1802 | |
d5b7b3ae RE |
1803 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1804 | once for every function before code is generated. */ | |
1805 | #define INIT_EXPANDERS arm_init_expanders () | |
1806 | ||
35d965d5 | 1807 | /* Length in units of the trampoline for entering a nested function. */ |
bc87cffb | 1808 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) |
35d965d5 | 1809 | |
006946e4 JM |
1810 | /* Alignment required for a trampoline in bits. */ |
1811 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1812 | \f |
1813 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 | 1814 | #define HAVE_POST_INCREMENT 1 |
5b3e6663 PB |
1815 | #define HAVE_PRE_INCREMENT TARGET_32BIT |
1816 | #define HAVE_POST_DECREMENT TARGET_32BIT | |
1817 | #define HAVE_PRE_DECREMENT TARGET_32BIT | |
1818 | #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
1819 | #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
1820 | #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
1821 | #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
35d965d5 | 1822 | |
8875e939 RR |
1823 | enum arm_auto_incmodes |
1824 | { | |
1825 | ARM_POST_INC, | |
1826 | ARM_PRE_INC, | |
1827 | ARM_POST_DEC, | |
1828 | ARM_PRE_DEC | |
1829 | }; | |
1830 | ||
1831 | #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ | |
1832 | (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) | |
1833 | #define USE_LOAD_POST_INCREMENT(mode) \ | |
1834 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) | |
1835 | #define USE_LOAD_PRE_INCREMENT(mode) \ | |
1836 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) | |
1837 | #define USE_LOAD_POST_DECREMENT(mode) \ | |
1838 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) | |
1839 | #define USE_LOAD_PRE_DECREMENT(mode) \ | |
1840 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) | |
1841 | ||
1842 | #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) | |
1843 | #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) | |
1844 | #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) | |
1845 | #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) | |
1846 | ||
35d965d5 RS |
1847 | /* Macros to check register numbers against specific register classes. */ |
1848 | ||
1849 | /* These assume that REGNO is a hard or pseudo reg number. | |
1850 | They give nonzero only if REGNO is a hard reg of the suitable class | |
378056b2 | 1851 | or a pseudo reg currently allocated to a suitable hard reg. */ |
d5b7b3ae | 1852 | #define TEST_REGNO(R, TEST, VALUE) \ |
3a3a8086 KT |
1853 | ((R TEST VALUE) \ |
1854 | || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) | |
d5b7b3ae | 1855 | |
5b3e6663 | 1856 | /* Don't allow the pc to be used. */ |
f1008e52 RE |
1857 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1858 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1859 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1860 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1861 | ||
5b3e6663 | 1862 | #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
f1008e52 RE |
1863 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ |
1864 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1865 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1866 | ||
1867 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
5b3e6663 PB |
1868 | (TARGET_THUMB1 \ |
1869 | ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
f1008e52 RE |
1870 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) |
1871 | ||
888d2cd6 | 1872 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
67914693 | 1873 | For Thumb, we cannot use SP + reg, so reject SP. */ |
888d2cd6 | 1874 | #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ |
f5c630c3 | 1875 | REGNO_MODE_OK_FOR_BASE_P (X, QImode) |
888d2cd6 | 1876 | |
f1008e52 RE |
1877 | /* For ARM code, we don't care about the mode, but for Thumb, the index |
1878 | must be suitable for use in a QImode load. */ | |
d5b7b3ae | 1879 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
f5c630c3 PB |
1880 | (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ |
1881 | && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
35d965d5 RS |
1882 | |
1883 | /* Maximum number of registers that can appear in a valid memory address. | |
d6b4baa4 | 1884 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1885 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1886 | |
1887 | /* Recognize any constant value that is a valid address. */ | |
1888 | /* XXX We can address any constant, eventually... */ | |
5b3e6663 | 1889 | /* ??? Should the TARGET_ARM here also apply to thumb2? */ |
008cf58a RE |
1890 | #define CONSTANT_ADDRESS_P(X) \ |
1891 | (GET_CODE (X) == SYMBOL_REF \ | |
1892 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1893 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1894 | |
8426b956 RS |
1895 | /* True if SYMBOL + OFFSET constants must refer to something within |
1896 | SYMBOL's section. */ | |
1897 | #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
1898 | ||
571191af PB |
1899 | /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ |
1900 | #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
1901 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
1902 | #endif | |
1903 | ||
c27ba912 DM |
1904 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS |
1905 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1906 | #endif | |
1907 | ||
6bc82793 | 1908 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1909 | Each case label should return the number of characters to |
1910 | be stripped from the start of a function's name, if that | |
1911 | name starts with the indicated character. */ | |
1912 | #define ARM_NAME_ENCODING_LENGTHS \ | |
00fdafef | 1913 | case '*': return 1; \ |
f676971a | 1914 | SUBTARGET_NAME_ENCODING_LENGTHS |
c27ba912 | 1915 | |
c27ba912 DM |
1916 | /* This is how to output a reference to a user-level label named NAME. |
1917 | `assemble_name' uses this. */ | |
e5951263 | 1918 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1919 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1920 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1921 | |
7a085dce | 1922 | /* Output IT instructions for conditionally executed Thumb-2 instructions. */ |
5b3e6663 PB |
1923 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ |
1924 | if (TARGET_THUMB2) \ | |
1925 | thumb2_asm_output_opcode (STREAM); | |
1926 | ||
7abc66b1 JB |
1927 | /* The EABI specifies that constructors should go in .init_array. |
1928 | Other targets use .ctors for compatibility. */ | |
88c6057f | 1929 | #ifndef ARM_EABI_CTORS_SECTION_OP |
7abc66b1 JB |
1930 | #define ARM_EABI_CTORS_SECTION_OP \ |
1931 | "\t.section\t.init_array,\"aw\",%init_array" | |
88c6057f MM |
1932 | #endif |
1933 | #ifndef ARM_EABI_DTORS_SECTION_OP | |
7abc66b1 JB |
1934 | #define ARM_EABI_DTORS_SECTION_OP \ |
1935 | "\t.section\t.fini_array,\"aw\",%fini_array" | |
88c6057f | 1936 | #endif |
7abc66b1 JB |
1937 | #define ARM_CTORS_SECTION_OP \ |
1938 | "\t.section\t.ctors,\"aw\",%progbits" | |
1939 | #define ARM_DTORS_SECTION_OP \ | |
1940 | "\t.section\t.dtors,\"aw\",%progbits" | |
1941 | ||
1942 | /* Define CTORS_SECTION_ASM_OP. */ | |
1943 | #undef CTORS_SECTION_ASM_OP | |
1944 | #undef DTORS_SECTION_ASM_OP | |
1945 | #ifndef IN_LIBGCC2 | |
1946 | # define CTORS_SECTION_ASM_OP \ | |
1947 | (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
1948 | # define DTORS_SECTION_ASM_OP \ | |
1949 | (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
1950 | #else /* !defined (IN_LIBGCC2) */ | |
1951 | /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
1952 | so we cannot use the definition above. */ | |
1953 | # ifdef __ARM_EABI__ | |
1954 | /* The .ctors section is not part of the EABI, so we do not define | |
1955 | CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
1956 | from trying to use it. We do define it when doing normal | |
1957 | compilation, as .init_array can be used instead of .ctors. */ | |
1958 | /* There is no need to emit begin or end markers when using | |
1959 | init_array; the dynamic linker will compute the size of the | |
1960 | array itself based on special symbols created by the static | |
1961 | linker. However, we do need to arrange to set up | |
1962 | exception-handling here. */ | |
1963 | # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
1964 | # define CTOR_LIST_END /* empty */ | |
1965 | # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
1966 | # define DTOR_LIST_END /* empty */ | |
1967 | # else /* !defined (__ARM_EABI__) */ | |
1968 | # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
1969 | # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
1970 | # endif /* !defined (__ARM_EABI__) */ | |
1971 | #endif /* !defined (IN_LIBCC2) */ | |
1972 | ||
1e731102 MM |
1973 | /* True if the operating system can merge entities with vague linkage |
1974 | (e.g., symbols in COMDAT group) during dynamic linking. */ | |
1975 | #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
1976 | #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
1977 | #endif | |
1978 | ||
617a1b71 PB |
1979 | #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) |
1980 | ||
35d965d5 RS |
1981 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1982 | and check its validity for a certain class. | |
1983 | We have two alternate definitions for each of them. | |
1984 | The usual definition accepts all pseudo regs; the other rejects | |
1985 | them unless they have been allocated suitable hard regs. | |
5b3e6663 | 1986 | The symbol REG_OK_STRICT causes the latter definition to be used. |
7a085dce | 1987 | Thumb-2 has the same restrictions as arm. */ |
35d965d5 | 1988 | #ifndef REG_OK_STRICT |
ff9940b0 | 1989 | |
f1008e52 RE |
1990 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1991 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1992 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1993 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1994 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1995 | |
f5c630c3 PB |
1996 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1997 | ((REGNO (X) <= LAST_ARM_REGNUM \ | |
1998 | && REGNO (X) != STACK_POINTER_REGNUM) \ | |
1999 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2000 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
2001 | || REGNO (X) == ARG_POINTER_REGNUM) | |
2002 | ||
5b3e6663 | 2003 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
f1008e52 RE |
2004 | (REGNO (X) <= LAST_LO_REGNUM \ |
2005 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2006 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
2007 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
2008 | || (X) == hard_frame_pointer_rtx \ | |
2009 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 2010 | |
76a318e9 RE |
2011 | #define REG_STRICT_P 0 |
2012 | ||
d5b7b3ae | 2013 | #else /* REG_OK_STRICT */ |
ff9940b0 | 2014 | |
f1008e52 RE |
2015 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2016 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 2017 | |
f5c630c3 PB |
2018 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
2019 | ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
2020 | ||
5b3e6663 PB |
2021 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2022 | THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 2023 | |
76a318e9 RE |
2024 | #define REG_STRICT_P 1 |
2025 | ||
d5b7b3ae | 2026 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
2027 | |
2028 | /* Now define some helpers in terms of the above. */ | |
2029 | ||
2030 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
5b3e6663 PB |
2031 | (TARGET_THUMB1 \ |
2032 | ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
f1008e52 RE |
2033 | : ARM_REG_OK_FOR_BASE_P (X)) |
2034 | ||
5b3e6663 | 2035 | /* For 16-bit Thumb, a valid index register is anything that can be used in |
f1008e52 | 2036 | a byte load instruction. */ |
5b3e6663 PB |
2037 | #define THUMB1_REG_OK_FOR_INDEX_P(X) \ |
2038 | THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
f1008e52 RE |
2039 | |
2040 | /* Nonzero if X is a hard reg that can be used as an index | |
2041 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
2042 | is not suitable. */ | |
2043 | #define REG_OK_FOR_INDEX_P(X) \ | |
5b3e6663 PB |
2044 | (TARGET_THUMB1 \ |
2045 | ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
f1008e52 RE |
2046 | : ARM_REG_OK_FOR_INDEX_P (X)) |
2047 | ||
888d2cd6 | 2048 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
67914693 | 2049 | For Thumb, we cannot use SP + reg, so reject SP. */ |
888d2cd6 DJ |
2050 | #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ |
2051 | REG_OK_FOR_INDEX_P (X) | |
35d965d5 | 2052 | \f |
f1008e52 | 2053 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
d435a4be | 2054 | (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) |
35d965d5 | 2055 | |
f1008e52 | 2056 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
d435a4be | 2057 | (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) |
35d965d5 | 2058 | \f |
35d965d5 RS |
2059 | /* Specify the machine mode that this machine uses |
2060 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2061 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2062 | |
e24f6408 CL |
2063 | #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ |
2064 | || (TARGET_THUMB1 \ | |
2065 | && (optimize_size || flag_pic))) \ | |
2066 | && (!target_pure_code)) | |
2067 | ||
907dd0c7 RE |
2068 | |
2069 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
83c3a2d8 | 2070 | (TARGET_THUMB1 \ |
907dd0c7 RE |
2071 | ? (min >= 0 && max < 512 \ |
2072 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ | |
2073 | : min >= -256 && max < 256 \ | |
2074 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ | |
2075 | : min >= 0 && max < 8192 \ | |
2076 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ | |
2077 | : min >= -4096 && max < 4096 \ | |
2078 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ | |
2079 | : SImode) \ | |
10c241af | 2080 | : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ |
907dd0c7 RE |
2081 | : (max >= 0x200) ? HImode \ |
2082 | : QImode)) | |
5b3e6663 | 2083 | |
ff9940b0 RE |
2084 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2085 | unsigned is probably best, but may break some code. */ | |
2086 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2087 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2088 | #endif |
2089 | ||
35d965d5 | 2090 | /* Max number of bytes we can move from memory to memory |
d17ce9af TG |
2091 | in one reasonably fast instruction. */ |
2092 | #define MOVE_MAX 4 | |
35d965d5 | 2093 | |
d19fb8e3 | 2094 | #undef MOVE_RATIO |
e04ad03d | 2095 | #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) |
d19fb8e3 | 2096 | |
ff9940b0 RE |
2097 | /* Define if operations between registers always perform the operation |
2098 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 2099 | #define WORD_REGISTER_OPERATIONS 1 |
ff9940b0 RE |
2100 | |
2101 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2102 | will either zero-extend or sign-extend. The value of this macro should | |
2103 | be the code that says which one of the two operations is implicitly | |
f822d252 | 2104 | done, UNKNOWN if none. */ |
9c872872 | 2105 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2106 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2107 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
f822d252 | 2108 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) |
ff9940b0 | 2109 | |
35d965d5 RS |
2110 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2111 | #define SLOW_BYTE_ACCESS 0 | |
2112 | ||
2113 | /* Immediate shift counts are truncated by the output routines (or was it | |
2114 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2115 | that the native compiler puts too large (> 32) immediate shift counts | |
2116 | into a register and shifts by the register, letting the ARM decide what | |
2117 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2118 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2119 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2120 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
d6b4baa4 | 2121 | rotates is modulo 32 used. */ |
ff9940b0 | 2122 | /* #define SHIFT_COUNT_TRUNCATED 1 */ |
35d965d5 | 2123 | |
35d965d5 RS |
2124 | /* Calling from registers is a massive pain. */ |
2125 | #define NO_FUNCTION_CSE 1 | |
2126 | ||
35d965d5 RS |
2127 | /* The machine modes of pointers and functions */ |
2128 | #define Pmode SImode | |
2129 | #define FUNCTION_MODE Pmode | |
2130 | ||
d5b7b3ae RE |
2131 | #define ARM_FRAME_RTX(X) \ |
2132 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2133 | || (X) == arg_pointer_rtx) |
2134 | ||
ff9940b0 | 2135 | /* Try to generate sequences that don't involve branches, we can then use |
a51fb17f | 2136 | conditional instructions. */ |
227e5798 CL |
2137 | #define BRANCH_COST(speed_p, predictable_p) \ |
2138 | ((arm_branch_cost != -1) ? arm_branch_cost : \ | |
2139 | (current_tune->branch_cost (speed_p, predictable_p))) | |
153668ec | 2140 | |
a51fb17f | 2141 | /* False if short circuit operation is preferred. */ |
52c266ba RE |
2142 | #define LOGICAL_OP_NON_SHORT_CIRCUIT \ |
2143 | ((optimize_size) \ | |
2144 | ? (TARGET_THUMB ? false : true) \ | |
4cbd1e61 RR |
2145 | : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ |
2146 | : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) | |
a51fb17f | 2147 | |
7a801826 RE |
2148 | \f |
2149 | /* Position Independent Code. */ | |
2150 | /* We decide which register to use based on the compilation options and | |
2151 | the assembler in use; this is more general than the APCS restriction of | |
2152 | using sb (r9) all the time. */ | |
020a4035 | 2153 | extern unsigned arm_pic_register; |
7a801826 RE |
2154 | |
2155 | /* The register number of the register used to address a table of static | |
2156 | data addresses in memory. */ | |
2157 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2158 | ||
8b63716e CL |
2159 | /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT |
2160 | entries would need to handle saving and restoring it). */ | |
2161 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC | |
2162 | ||
f5a1b0d2 | 2163 | /* We can't directly access anything that contains a symbol, |
d3585b76 DJ |
2164 | nor can we indirect via the constant pool. One exception is |
2165 | UNSPEC_TLS, which is always PIC. */ | |
82e9d970 | 2166 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2167 | (!(symbol_mentioned_p (X) \ |
2168 | || label_mentioned_p (X) \ | |
2169 | || (GET_CODE (X) == SYMBOL_REF \ | |
2170 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2171 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
d3585b76 DJ |
2172 | || label_mentioned_p (get_pool_constant (X))))) \ |
2173 | || tls_mentioned_p (X)) | |
1575c31e | 2174 | |
4997c9ae CL |
2175 | /* We may want to save the PIC register if it is a dedicated one. */ |
2176 | #define PIC_REGISTER_MAY_NEED_SAVING \ | |
2177 | (flag_pic \ | |
2178 | && !TARGET_SINGLE_PIC_BASE \ | |
2179 | && !TARGET_FDPIC \ | |
2180 | && arm_pic_register != INVALID_REGNUM) | |
2181 | ||
13bd191d PB |
2182 | /* We need to know when we are making a constant pool; this determines |
2183 | whether data needs to be in the GOT or can be referenced via a GOT | |
2184 | offset. */ | |
2185 | extern int making_const_table; | |
82e9d970 | 2186 | \f |
c27ba912 | 2187 | /* Handle pragmas for compatibility with Intel's compilers. */ |
b76c3c4b | 2188 | /* Also abuse this to register additional C specific EABI attributes. */ |
c58b209a NB |
2189 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2190 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
2191 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
2192 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
c84f825c CB |
2193 | arm_lang_object_attributes_init(); \ |
2194 | arm_register_target_pragmas(); \ | |
8b97c5f8 ZW |
2195 | } while (0) |
2196 | ||
d6b4baa4 | 2197 | /* Condition code information. */ |
ff9940b0 | 2198 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
a5381466 | 2199 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2200 | |
2201 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2202 | |
880873be RE |
2203 | #define REVERSIBLE_CC_MODE(MODE) 1 |
2204 | ||
2205 | #define REVERSE_CONDITION(CODE,MODE) \ | |
2206 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
2207 | ? reverse_condition_maybe_unordered (code) \ | |
2208 | : reverse_condition (code)) | |
008cf58a | 2209 | |
9b227e35 | 2210 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
41197ad4 | 2211 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
9b227e35 | 2212 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
41197ad4 | 2213 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
35d965d5 | 2214 | \f |
906668bb BS |
2215 | #define CC_STATUS_INIT \ |
2216 | do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) | |
2217 | ||
decfc6e1 TG |
2218 | #undef ASM_APP_ON |
2219 | #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ | |
2220 | "\t.syntax divided\n") | |
2221 | ||
d5b7b3ae | 2222 | #undef ASM_APP_OFF |
41d14659 RR |
2223 | #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ |
2224 | "\t.thumb\n\t.syntax unified\n") | |
35d965d5 | 2225 | |
2ee67fbb JB |
2226 | /* Output a push or a pop instruction (only used when profiling). |
2227 | We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know | |
2228 | that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and | |
2229 | that r7 isn't used by the function profiler, so we can use it as a | |
2230 | scratch reg. WARNING: This isn't safe in the general case! It may be | |
e53b6e56 | 2231 | sensitive to future changes in final.cc:profile_function. */ |
d5b7b3ae | 2232 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
8a81cc45 RE |
2233 | do \ |
2234 | { \ | |
bae4ce0f | 2235 | if (TARGET_THUMB1 \ |
2ee67fbb JB |
2236 | && (REGNO) == STATIC_CHAIN_REGNUM) \ |
2237 | { \ | |
2238 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2239 | asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ | |
2240 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2241 | } \ | |
8a81cc45 RE |
2242 | else \ |
2243 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
2244 | } while (0) | |
d5b7b3ae RE |
2245 | |
2246 | ||
2ee67fbb | 2247 | /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ |
d5b7b3ae | 2248 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
8a81cc45 RE |
2249 | do \ |
2250 | { \ | |
bae4ce0f RR |
2251 | if (TARGET_THUMB1 \ |
2252 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2ee67fbb JB |
2253 | { \ |
2254 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2255 | asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ | |
2256 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2257 | } \ | |
8a81cc45 RE |
2258 | else \ |
2259 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
2260 | } while (0) | |
d5b7b3ae | 2261 | |
b0fe107e JM |
2262 | #define ADDR_VEC_ALIGN(JUMPTABLE) \ |
2263 | ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) | |
2264 | ||
2265 | /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the | |
2266 | default alignment from elfos.h. */ | |
2267 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
2268 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ | |
5b3e6663 | 2269 | |
e75c1617 CB |
2270 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ |
2271 | (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ | |
2272 | ? 1 : 0) | |
35d965d5 | 2273 | |
6cfc7210 | 2274 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
258619bb | 2275 | arm_declare_function_name ((STREAM), (NAME), (DECL)); |
35d965d5 | 2276 | |
d5b7b3ae RE |
2277 | /* For aliases of functions we use .thumb_set instead. */ |
2278 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2279 | do \ | |
2280 | { \ | |
91ea4f8d KG |
2281 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2282 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2283 | \ |
2284 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2285 | { \ | |
2286 | fprintf (FILE, "\t.thumb_set "); \ | |
2287 | assemble_name (FILE, LABEL1); \ | |
2288 | fprintf (FILE, ","); \ | |
2289 | assemble_name (FILE, LABEL2); \ | |
2290 | fprintf (FILE, "\n"); \ | |
2291 | } \ | |
2292 | else \ | |
2293 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2294 | } \ | |
2295 | while (0) | |
2296 | ||
fdc2d3b0 NC |
2297 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2298 | /* To support -falign-* switches we need to use .p2align so | |
2299 | that alignment directives in code sections will be padded | |
2300 | with no-op instructions, rather than zeroes. */ | |
5a9335ef | 2301 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ |
fdc2d3b0 NC |
2302 | if ((LOG) != 0) \ |
2303 | { \ | |
2304 | if ((MAX_SKIP) == 0) \ | |
5a9335ef | 2305 | fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ |
fdc2d3b0 NC |
2306 | else \ |
2307 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
5a9335ef | 2308 | (int) (LOG), (int) (MAX_SKIP)); \ |
fdc2d3b0 NC |
2309 | } |
2310 | #endif | |
35d965d5 | 2311 | \f |
5b3e6663 PB |
2312 | /* Add two bytes to the length of conditionally executed Thumb-2 |
2313 | instructions for the IT instruction. */ | |
2314 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
2315 | if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
2316 | length += 2; | |
2317 | ||
35d965d5 | 2318 | /* Only perform branch elimination (by making instructions conditional) if |
5b3e6663 PB |
2319 | we're optimizing. For Thumb-2 check if any IT instructions need |
2320 | outputting. */ | |
d5b7b3ae RE |
2321 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2322 | if (TARGET_ARM && optimize) \ | |
2323 | arm_final_prescan_insn (INSN); \ | |
5b3e6663 PB |
2324 | else if (TARGET_THUMB2) \ |
2325 | thumb2_final_prescan_insn (INSN); \ | |
2326 | else if (TARGET_THUMB1) \ | |
2327 | thumb1_final_prescan_insn (INSN) | |
35d965d5 | 2328 | |
7b8b8ade NC |
2329 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2330 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2331 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2332 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2333 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2334 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2335 | : 0)))) |
35d965d5 | 2336 | |
6a5d7526 MS |
2337 | /* A C expression whose value is RTL representing the value of the return |
2338 | address for the frame COUNT steps up from the current frame. */ | |
2339 | ||
d5b7b3ae RE |
2340 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2341 | arm_return_addr (COUNT, FRAME) | |
2342 | ||
f676971a | 2343 | /* Mask of the bits in the PC that contain the real return address |
d5b7b3ae RE |
2344 | when running in 26-bit mode. */ |
2345 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2346 | |
2c849145 JM |
2347 | /* Pick up the return address upon entry to a procedure. Used for |
2348 | dwarf2 unwind information. This also enables the table driven | |
2349 | mechanism. */ | |
2c849145 JM |
2350 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2351 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2352 | ||
39950dff MS |
2353 | /* Used to mask out junk bits from the return address, such as |
2354 | processor state, interrupt status, condition codes and the like. */ | |
2355 | #define MASK_RETURN_ADDR \ | |
2356 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2357 | in 26 bit mode, the condition codes must be masked out of the \ | |
2358 | return address. This does not apply to ARM6 and later processors \ | |
2359 | when running in 32 bit mode. */ \ | |
61f0ccff RE |
2360 | ((arm_arch4 || TARGET_THUMB) \ |
2361 | ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
fcd53748 | 2362 | : arm_gen_return_addr_mask ()) |
d5b7b3ae RE |
2363 | |
2364 | \f | |
978e411f CD |
2365 | /* Do not emit .note.GNU-stack by default. */ |
2366 | #ifndef NEED_INDICATE_EXEC_STACK | |
2367 | #define NEED_INDICATE_EXEC_STACK 0 | |
2368 | #endif | |
2369 | ||
9e94a7fc MGD |
2370 | #define TARGET_ARM_ARCH \ |
2371 | (arm_base_arch) \ | |
2372 | ||
9e94a7fc | 2373 | /* The highest Thumb instruction set version supported by the chip. */ |
52545641 TP |
2374 | #define TARGET_ARM_ARCH_ISA_THUMB \ |
2375 | (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) | |
9e94a7fc MGD |
2376 | |
2377 | /* Expands to an upper-case char of the target's architectural | |
2378 | profile. */ | |
2379 | #define TARGET_ARM_ARCH_PROFILE \ | |
8afb5358 | 2380 | (arm_active_target.profile) |
9e94a7fc MGD |
2381 | |
2382 | /* Bit-field indicating what size LDREX/STREX loads/stores are available. | |
2383 | Bit 0 for bytes, up to bit 3 for double-words. */ | |
2384 | #define TARGET_ARM_FEATURE_LDREX \ | |
2385 | ((TARGET_HAVE_LDREX ? 4 : 0) \ | |
2386 | | (TARGET_HAVE_LDREXBH ? 3 : 0) \ | |
2387 | | (TARGET_HAVE_LDREXD ? 8 : 0)) | |
2388 | ||
2389 | /* Set as a bit mask indicating the available widths of hardware floating | |
2390 | point types. Where bit 1 indicates 16-bit support, bit 2 indicates | |
2391 | 32-bit support, bit 3 indicates 64-bit support. */ | |
2392 | #define TARGET_ARM_FP \ | |
29e1d31b MM |
2393 | (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ |
2394 | : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ | |
2395 | : 0) | |
9e94a7fc MGD |
2396 | |
2397 | ||
2398 | /* Set as a bit mask indicating the available widths of floating point | |
2399 | types for hardware NEON floating point. This is the same as | |
2400 | TARGET_ARM_FP without the 64-bit bit set. */ | |
29e1d31b MM |
2401 | #define TARGET_NEON_FP \ |
2402 | (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ | |
2403 | : 0) | |
9e94a7fc | 2404 | |
11389610 RE |
2405 | /* Name of the automatic fpu-selection option. */ |
2406 | #define FPUTYPE_AUTO "auto" | |
2407 | ||
93b338c3 BS |
2408 | /* The maximum number of parallel loads or stores we support in an ldm/stm |
2409 | instruction. */ | |
2410 | #define MAX_LDM_STM_OPS 4 | |
2411 | ||
b848e289 | 2412 | extern const char *arm_rewrite_mcpu (int argc, const char **argv); |
86794453 | 2413 | extern const char *arm_rewrite_march (int argc, const char **argv); |
940269b6 | 2414 | extern const char *arm_asm_auto_mfpu (int argc, const char **argv); |
86794453 RE |
2415 | #define ASM_CPU_SPEC_FUNCTIONS \ |
2416 | { "rewrite_mcpu", arm_rewrite_mcpu }, \ | |
940269b6 RE |
2417 | { "rewrite_march", arm_rewrite_march }, \ |
2418 | { "asm_auto_mfpu", arm_asm_auto_mfpu }, | |
b848e289 | 2419 | |
86794453 | 2420 | #define ASM_CPU_SPEC \ |
940269b6 | 2421 | " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ |
86794453 | 2422 | " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ |
940269b6 | 2423 | " march=*:-march=%:rewrite_march(%{march=*:%*});" \ |
86794453 RE |
2424 | " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ |
2425 | " }" | |
54e73f88 | 2426 | |
15cf7fe3 | 2427 | extern const char *arm_target_mode (int argc, const char **argv); |
86794453 | 2428 | #define TARGET_MODE_SPEC_FUNCTIONS \ |
15cf7fe3 | 2429 | { "target_mode_check", arm_target_mode }, |
70e73d3c | 2430 | |
33aa08b3 AS |
2431 | /* -mcpu=native handling only makes sense with compiler running on |
2432 | an ARM chip. */ | |
2433 | #if defined(__arm__) | |
2434 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
a646fe9c | 2435 | #define HAVE_LOCAL_CPU_DETECT |
86794453 RE |
2436 | # define MCPU_MTUNE_NATIVE_FUNCTIONS \ |
2437 | { "local_cpu_detect", host_detect_local_cpu }, | |
2438 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
2439 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
2440 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
33aa08b3 AS |
2441 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" |
2442 | #else | |
86794453 | 2443 | # define MCPU_MTUNE_NATIVE_FUNCTIONS |
33aa08b3 AS |
2444 | # define MCPU_MTUNE_NATIVE_SPECS "" |
2445 | #endif | |
2446 | ||
0b97b8f8 | 2447 | const char *arm_canon_arch_option (int argc, const char **argv); |
f58d03b5 | 2448 | const char *arm_canon_arch_multilib_option (int argc, const char **argv); |
0b97b8f8 RE |
2449 | |
2450 | #define CANON_ARCH_SPEC_FUNCTION \ | |
2451 | { "canon_arch", arm_canon_arch_option }, | |
2452 | ||
f58d03b5 SP |
2453 | #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ |
2454 | { "canon_arch_multilib", arm_canon_arch_multilib_option }, | |
2455 | ||
63d03dce RE |
2456 | const char *arm_be8_option (int argc, const char **argv); |
2457 | #define BE8_SPEC_FUNCTION \ | |
2458 | { "be8_linkopt", arm_be8_option }, | |
2459 | ||
86794453 RE |
2460 | # define EXTRA_SPEC_FUNCTIONS \ |
2461 | MCPU_MTUNE_NATIVE_FUNCTIONS \ | |
2462 | ASM_CPU_SPEC_FUNCTIONS \ | |
0b97b8f8 | 2463 | CANON_ARCH_SPEC_FUNCTION \ |
f58d03b5 | 2464 | CANON_ARCH_MULTILIB_SPEC_FUNCTION \ |
63d03dce RE |
2465 | TARGET_MODE_SPEC_FUNCTIONS \ |
2466 | BE8_SPEC_FUNCTION | |
86794453 | 2467 | |
70e73d3c TP |
2468 | /* Automatically add -mthumb for Thumb-only targets if mode isn't specified |
2469 | via the configuration option --with-mode or via the command line. The | |
2470 | function target_mode_check is called to do the check with either: | |
2471 | - an array of -march values if any is given; | |
2472 | - an array of -mcpu values if any is given; | |
2473 | - an empty array. */ | |
2474 | #define TARGET_MODE_SPECS \ | |
e53993ef | 2475 | " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" |
70e73d3c | 2476 | |
0b97b8f8 RE |
2477 | /* Generate a canonical string to represent the architecture selected. */ |
2478 | #define ARCH_CANONICAL_SPECS \ | |
2479 | " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ | |
2480 | " %{march=*: arch %*} " \ | |
2481 | " %{mfpu=*: fpu %*} " \ | |
2482 | " %{mfloat-abi=*: abi %*}" \ | |
2483 | " %<march=*) " | |
2484 | ||
f58d03b5 SP |
2485 | /* Generate a canonical string to represent the architecture selected ignoring |
2486 | the options not required for multilib linking. */ | |
2487 | #define MULTILIB_ARCH_CANONICAL_SPECS \ | |
2488 | "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ | |
2489 | " %{march=*: arch %*} " \ | |
2490 | " %{mfpu=*: fpu %*} " \ | |
2491 | " %{mfloat-abi=*: abi %*}" \ | |
2492 | " %<mlibarch=*) " | |
2493 | ||
59aab79a RE |
2494 | /* Complete set of specs for the driver. Commas separate the |
2495 | individual rules so that any option suppression (%<opt...)is | |
2496 | completed before starting subsequent rules. */ | |
0b97b8f8 | 2497 | #define DRIVER_SELF_SPECS \ |
59aab79a RE |
2498 | MCPU_MTUNE_NATIVE_SPECS, \ |
2499 | TARGET_MODE_SPECS, \ | |
f58d03b5 | 2500 | MULTILIB_ARCH_CANONICAL_SPECS, \ |
0b97b8f8 RE |
2501 | ARCH_CANONICAL_SPECS |
2502 | ||
27e83a44 | 2503 | #define TARGET_SUPPORTS_WIDE_INT 1 |
d5524d52 CB |
2504 | |
2505 | /* For switching between functions with different target attributes. */ | |
2506 | #define SWITCHABLE_TARGET 1 | |
2507 | ||
0ee70cc0 AV |
2508 | /* Define SECTION_ARM_PURECODE as the ARM specific section attribute |
2509 | representation for SHF_ARM_PURECODE in GCC. */ | |
2510 | #define SECTION_ARM_PURECODE SECTION_MACH_DEP | |
2511 | ||
88657302 | 2512 | #endif /* ! GCC_ARM_H */ |