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35d965d5 1/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
996a5f59 2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
35d965d5
RS		 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
ff9940b0
RE		 5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
35d965d5
RS		 7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
21the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
ea7273ae 23/* Sometimes the directive `riscos' is checked. This does not imply that this
35d965d5
RS		 24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
7bc7696c
RE		 27extern void output_func_prologue ();
28extern void output_func_epilogue ();
35d965d5
RS		 29extern char *output_add_immediate ();
30extern char *output_call ();
ff9940b0 31extern char *output_call_mem ();
35d965d5
RS		 32extern char *output_move_double ();
33extern char *output_mov_double_fpu_from_arm ();
34extern char *output_mov_double_arm_from_fpu ();
7fc6c9f0
RK		 35extern char *output_mov_long_double_fpu_from_arm ();
36extern char *output_mov_long_double_arm_from_fpu ();
37extern char *output_mov_long_double_arm_from_arm ();
35d965d5
RS		 38extern char *output_mov_immediate ();
39extern char *output_multi_immediate ();
ff9940b0
RE		 40extern char *output_return_instruction ();
41extern char *output_load_symbol ();
42extern char *fp_immediate_constant ();
43extern struct rtx_def *gen_compare_reg ();
44extern struct rtx_def *arm_gen_store_multiple ();
45extern struct rtx_def *arm_gen_load_multiple ();
46
47extern char *arm_condition_codes[];
48
49/* This is needed by the tail-calling peepholes */
50extern int frame_pointer_needed;
51
35d965d5 52\f
ff9940b0
RE		 53#ifndef CPP_PREDEFINES
54#define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55#endif
35d965d5 56
ff9940b0
RE		 57#ifndef CPP_SPEC
58#define CPP_SPEC "%{m6:-D__arm6__}"
35d965d5
RS		 59#endif
60\f
61/* Run-time Target Specification. */
ff9940b0 62#ifndef TARGET_VERSION
35d965d5 63#define TARGET_VERSION \
ff9940b0
RE		 64 fputs (" (ARM/generic)", stderr);
65#endif
35d965d5
RS		 66
67/* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69extern int target_flags;
70
71/* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73#define TARGET_APCS (target_flags & 1)
74
75/* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79#define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81/* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83#define TARGET_FPE (target_flags & 4)
84
ff9940b0
RE		 85/* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87#define TARGET_6 (target_flags & 8)
88
89/* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
90 are passed to the preprocessor and the assembler post-processor. They
91 aren't needed in the main pass of the compiler, but if we don't define
92 them in target switches cc1 complains about them. For the sake of
93 argument lets allocate bit 31 of target flags for such options. */
94
95#ifndef ARM_EXTRA_TARGET_SWITCHES
96#define ARM_EXTRA_TARGET_SWITCHES
97#endif
98
35d965d5
RS		 99#define TARGET_SWITCHES \
100{ \
101 {"apcs", 1}, \
102 {"poke-function-name", 2}, \
103 {"fpe", 4}, \
ff9940b0
RE		 104 {"6", 8}, \
105 {"2", -8}, \
106 {"3", -8}, \
107 ARM_EXTRA_TARGET_SWITCHES \
35d965d5
RS		 108 {"", TARGET_DEFAULT } \
109}
110
ff9940b0
RE		 111/* Which processor we are running on. Currently this is only used to
112 get the condition code clobbering attribute right when we are running on
113 an arm 6 */
114
115enum processor_type
116{
117 PROCESSOR_ARM2,
118 PROCESSOR_ARM3,
119 PROCESSOR_ARM6
120};
121
122/* Recast the cpu class to be the cpu attribute. */
123
124/* Recast the cpu class to be the cpu attribute. */
125#define arm_cpu_attr ((enum attr_cpu)arm_cpu)
126
127extern enum processor_type arm_cpu;
128
35d965d5
RS		 129#define TARGET_DEFAULT 0
130
131#define TARGET_MEM_FUNCTIONS 1
132
133/* OVERRIDE_OPTIONS takes care of the following:
134 - if -mpoke-function-name, then -mapcs.
135 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
136 - if floating point is done by emulation, forget about instruction
137 scheduling. Note that this only saves compilation time; it doesn't
138 matter for the final code. */
ff9940b0 139#ifndef TARGET_WHEN_DEBUGGING
b4ac57ab 140#define TARGET_WHEN_DEBUGGING 1
35d965d5
RS		 141#endif
142
143#define OVERRIDE_OPTIONS \
144{ \
ff9940b0
RE		 145 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
146 warning ("-g without a frame pointer may not give sensible debugging");\
147 if (TARGET_POKE_FUNCTION_NAME) \
35d965d5
RS		 148 target_flags |= 1; \
149 if (TARGET_FPE) \
150 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
ff9940b0 151 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
35d965d5 152}
35d965d5
RS		 153\f
154/* Target machine storage Layout. */
155
ff9940b0
RE		 156
157/* Define this macro if it is advisable to hold scalars in registers
158 in a wider mode than that declared by the program. In such cases,
159 the value is constrained to be within the bounds of the declared
160 type, but kept valid in the wider mode. The signedness of the
161 extension may differ from that of the type. */
162
163/* It is far faster to zero extend chars than to sign extend them */
164
165#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
166 if (GET_MODE_CLASS (MODE) == MODE_INT \
167 && GET_MODE_SIZE (MODE) < 4) \
168 { \
169 if (MODE == QImode) \
170 UNSIGNEDP = 1; \
9c872872
RE		 171 else if (MODE == HImode) \
172 UNSIGNEDP = 0; \
ff9940b0
RE		 173 (MODE) = SImode; \
174 }
175
176/* Define for XFmode extended real floating point support.
177 This will automatically cause REAL_ARITHMETIC to be defined. */
178/* For the ARM:
179 I think I have added all the code to make this work. Unfortunately,
180 early releases of the floating point emulation code on RISCiX used a
181 different format for extended precision numbers. On my RISCiX box there
182 is a bug somewhere which causes the machine to lock up when running enquire
183 with long doubles. There is the additional aspect that Norcroft C
184 treats long doubles as doubles and we ought to remain compatible.
185 Perhaps someone with an FPA coprocessor and not running RISCiX would like
186 to try this someday. */
187/* #define LONG_DOUBLE_TYPE_SIZE 96 */
188
189/* Disable XFmode patterns in md file */
190#define ENABLE_XF_PATTERNS 0
191
192/* Define if you don't want extended real, but do want to use the
193 software floating point emulator for REAL_ARITHMETIC and
194 decimal <-> binary conversion. */
195/* See comment above */
196#define REAL_ARITHMETIC
197
35d965d5
RS		 198/* Define this if most significant bit is lowest numbered
199 in instructions that operate on numbered bit-fields. */
200#define BITS_BIG_ENDIAN 0
201
9c872872
RE		 202/* Define this if most significant byte of a word is the lowest numbered.
203 Most ARM processors are run in little endian mode, but it should now be
204 possible to build the compiler to support big endian code. (Note: This
205 is currently a compiler-build-time option, not a run-time one. */
206#ifndef BYTES_BIG_ENDIAN
35d965d5 207#define BYTES_BIG_ENDIAN 0
9c872872 208#endif
35d965d5
RS		 209
210/* Define this if most significant word of a multiword number is the lowest
211 numbered. */
212#define WORDS_BIG_ENDIAN 0
213
7fc6c9f0
RK		 214/* Define this if most significant word of doubles is the lowest numbered */
215#define FLOAT_WORDS_BIG_ENDIAN 1
216
b4ac57ab 217/* Number of bits in an addressable storage unit */
35d965d5
RS		 218#define BITS_PER_UNIT 8
219
220#define BITS_PER_WORD 32
221
222#define UNITS_PER_WORD 4
223
224#define POINTER_SIZE 32
225
226#define PARM_BOUNDARY 32
227
228#define STACK_BOUNDARY 32
229
230#define FUNCTION_BOUNDARY 32
231
232#define EMPTY_FIELD_BOUNDARY 32
233
234#define BIGGEST_ALIGNMENT 32
235
ff9940b0
RE		 236/* Make strings word-aligned so strcpy from constants will be faster. */
237#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
238 (TREE_CODE (EXP) == STRING_CST \
239 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
240
b4ac57ab
RS		 241/* Every structures size must be a multiple of 32 bits. */
242#define STRUCTURE_SIZE_BOUNDARY 32
243
ff9940b0
RE		 244/* Non-zero if move instructions will actually fail to work
245 when given unaligned data. */
35d965d5
RS		 246#define STRICT_ALIGNMENT 1
247
ff9940b0
RE		 248#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
249
35d965d5
RS		 250/* Define number of bits in most basic integer type.
251 (If undefined, default is BITS_PER_WORD). */
252/* #define INT_TYPE_SIZE */
253\f
254/* Standard register usage. */
255
256/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
257 (S - saved over call).
258
259 r0 * argument word/integer result
260 r1-r3 argument word
261
262 r4-r8 S register variable
263 r9 S (rfp) register variable (real frame pointer)
264
265 r10 F S (sl) stack limit (not currently used)
266 r11 F S (fp) argument pointer
267 r12 (ip) temp workspace
268 r13 F S (sp) lower end of current stack frame
269 r14 (lr) link address/workspace
270 r15 F (pc) program counter
271
272 f0 floating point result
273 f1-f3 floating point scratch
274
275 f4-f7 S floating point variable
276
ff9940b0
RE		 277 cc This is NOT a real register, but is used internally
278 to represent things that use or set the condition
279 codes.
280 sfp This isn't either. It is used during rtl generation
281 since the offset between the frame pointer and the
282 auto's isn't known until after register allocation.
283 afp Nor this, we only need this because of non-local
284 goto. Without it fp appears to be used and the
285 elimination code won't get rid of sfp. It tracks
286 fp exactly at all times.
287
35d965d5
RS		 288 *: See CONDITIONAL_REGISTER_USAGE */
289
ff9940b0
RE		 290/* The stack backtrace structure is as follows:
291 fp points to here: | save code pointer | [fp]
292 | return link value | [fp, #-4]
293 | return sp value | [fp, #-8]
294 | return fp value | [fp, #-12]
295 [| saved r10 value |]
296 [| saved r9 value |]
297 [| saved r8 value |]
298 [| saved r7 value |]
299 [| saved r6 value |]
300 [| saved r5 value |]
301 [| saved r4 value |]
302 [| saved r3 value |]
303 [| saved r2 value |]
304 [| saved r1 value |]
305 [| saved r0 value |]
306 [| saved f7 value |] three words
307 [| saved f6 value |] three words
308 [| saved f5 value |] three words
309 [| saved f4 value |] three words
310 r0-r3 are not normally saved in a C function. */
311
312/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
313#define FIRST_PSEUDO_REGISTER 27
35d965d5
RS		 314
315/* 1 for registers that have pervasive standard uses
316 and are not available for the register allocator. */
317#define FIXED_REGISTERS \
318{ \
319 0,0,0,0,0,0,0,0, \
320 0,0,1,1,0,1,0,1, \
ff9940b0
RE		 321 0,0,0,0,0,0,0,0, \
322 1,1,1 \
35d965d5
RS		 323}
324
325/* 1 for registers not available across function calls.
326 These must include the FIXED_REGISTERS and also any
327 registers that can be used without being saved.
328 The latter must include the registers where values are returned
329 and the register where structure-value addresses are passed.
ff9940b0
RE		 330 Aside from that, you can include as many other registers as you like.
331 The CC is not preserved over function calls on the ARM 6, so it is
332 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 333#define CALL_USED_REGISTERS \
334{ \
335 1,1,1,1,0,0,0,0, \
336 0,0,1,1,1,1,1,1, \
ff9940b0
RE		 337 1,1,1,1,0,0,0,0, \
338 1,1,1 \
35d965d5
RS		 339}
340
341/* If doing stupid life analysis, avoid a bug causing a return value r0 to be
342 trampled. This effectively reduces the number of available registers by 1.
343 XXX It is a hack, I know.
344 XXX Is this still needed? */
345#define CONDITIONAL_REGISTER_USAGE \
346{ \
347 if (obey_regdecls) \
348 fixed_regs[0] = 1; \
349}
350
351/* Return number of consecutive hard regs needed starting at reg REGNO
352 to hold something of mode MODE.
353 This is ordinarily the length in words of a value of mode MODE
354 but can be less for certain modes in special long registers.
355
356 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
357 mode. */
ff9940b0
RE		 358#define HARD_REGNO_NREGS(REGNO, MODE) \
359 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
360 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
35d965d5
RS		 361 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
362
363/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
364 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
365 regs holding FP. */
ff9940b0
RE		 366#define HARD_REGNO_MODE_OK(REGNO, MODE) \
367 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
368 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
369 || REGNO == ARG_POINTER_REGNUM \
370 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
35d965d5
RS		 371
372/* Value is 1 if it is a good idea to tie two pseudo registers
373 when one has mode MODE1 and one has mode MODE2.
374 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
375 for any hard reg, then this must be 0 for correct output. */
376#define MODES_TIEABLE_P(MODE1, MODE2) \
377 (((MODE1) == SFmode || (MODE1) == DFmode) \
378 == ((MODE2) == SFmode || (MODE2) == DFmode))
379
380/* Specify the registers used for certain standard purposes.
381 The values of these macros are register numbers. */
382
383/* Define this if the program counter is overloaded on a register. */
384#define PC_REGNUM 15
385
386/* Register to use for pushing function arguments. */
387#define STACK_POINTER_REGNUM 13
388
389/* Base register for access to local variables of the function. */
ff9940b0
RE		 390#define FRAME_POINTER_REGNUM 25
391
392/* Define this to be where the real frame pointer is if it is not possible to
393 work out the offset between the frame pointer and the automatic variables
394 until after register allocation has taken place. FRAME_POINTER_REGNUM
395 should point to a special register that we will make sure is eliminated. */
396#define HARD_FRAME_POINTER_REGNUM 11
35d965d5
RS		 397
398/* Value should be nonzero if functions must have frame pointers.
399 Zero means the frame pointer need not be set up (and parms may be accessed
ff9940b0
RE		 400 via the stack pointer) in functions that seem suitable.
401 If we have to have a frame pointer we might as well make use of it.
402 APCS says that the frame pointer does not need to be pushed in leaf
403 functions. */
404#define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
35d965d5
RS		 405
406/* Base register for access to arguments of the function. */
ff9940b0 407#define ARG_POINTER_REGNUM 26
35d965d5
RS		 408
409/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
410 as an invisible last argument (possible since varargs don't exist in
411 Pascal), so the following is not true. */
412#define STATIC_CHAIN_REGNUM 8
413
414/* Register in which address to store a structure value
415 is passed to a function. */
416#define STRUCT_VALUE_REGNUM 0
417
ff9940b0
RE		 418/* Internal, so that we don't need to refer to a raw number */
419#define CC_REGNUM 24
420
35d965d5 421/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 422 since no saving is required (though calls clobber it) and it never contains
423 function parameters. It is quite good to use lr since other calls may
424 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
425 least likely to contain a function parameter; in addition results are
426 returned in r0.
427 */
35d965d5
RS		 428#define REG_ALLOC_ORDER \
429{ \
ff9940b0 430 3, 2, 1, 0, 12, 14, 4, 5, \
35d965d5 431 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0
RE		 432 16, 17, 18, 19, 20, 21, 22, 23, \
433 24, 25 \
35d965d5
RS		 434}
435\f
436/* Register and constant classes. */
437
438/* Register classes: all ARM regs or all FPU regs---simple! */
439enum reg_class
440{
441 NO_REGS,
442 FPU_REGS,
443 GENERAL_REGS,
444 ALL_REGS,
445 LIM_REG_CLASSES
446};
447
448#define N_REG_CLASSES (int) LIM_REG_CLASSES
449
450/* Give names of register classes as strings for dump file. */
451#define REG_CLASS_NAMES \
452{ \
453 "NO_REGS", \
454 "FPU_REGS", \
455 "GENERAL_REGS", \
456 "ALL_REGS", \
457}
458
459/* Define which registers fit in which classes.
460 This is an initializer for a vector of HARD_REG_SET
461 of length N_REG_CLASSES. */
462#define REG_CLASS_CONTENTS \
463{ \
ff9940b0
RE		 464 0x0000000, /* NO_REGS */ \
465 0x0FF0000, /* FPU_REGS */ \
466 0x200FFFF, /* GENERAL_REGS */ \
467 0x2FFFFFF /* ALL_REGS */ \
35d965d5
RS		 468}
469
470/* The same information, inverted:
471 Return the class number of the smallest class containing
472 reg number REGNO. This could be a conditional expression
473 or could index an array. */
ff9940b0
RE		 474#define REGNO_REG_CLASS(REGNO) \
475 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
476 || REGNO == ARG_POINTER_REGNUM) \
477 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
478 ? NO_REGS : FPU_REGS)
35d965d5
RS		 479
480/* The class value for index registers, and the one for base regs. */
481#define INDEX_REG_CLASS GENERAL_REGS
482#define BASE_REG_CLASS GENERAL_REGS
483
484/* Get reg_class from a letter such as appears in the machine description.
485 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
486#define REG_CLASS_FROM_LETTER(C) \
487 ((C)=='f' ? FPU_REGS : NO_REGS)
488
489/* The letters I, J, K, L and M in a register constraint string
490 can be used to stand for particular ranges of immediate operands.
491 This macro defines what the ranges are.
492 C is the letter, and VALUE is a constant value.
493 Return 1 if VALUE is in the range specified by C.
b4ac57ab 494 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
ff9940b0 495 J: valid indexing constants.
aef1764c
RE		 496 K: ~value ok in rhs argument of data operand.
497 L: -value ok in rhs argument of data operand. */
498#define CONST_OK_FOR_LETTER_P(VALUE, C) \
499 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
500 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
501 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
502 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : 0)
ff9940b0
RE		 503
504/* For the ARM, `Q' means that this is a memory operand that is just
505 an offset from a register.
506 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
507 address. This means that the symbol is in the text segment and can be
508 accessed without using a load. */
509
510#define EXTRA_CONSTRAINT(OP, C) \
511 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
008cf58a
RE		 512 : (C) == 'R' ? (GET_CODE (OP) == MEM \
513 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
514 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
515 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
ff9940b0
RE		 516
517/* Constant letter 'G' for the FPU immediate constants.
518 'H' means the same constant negated. */
519#define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
520 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
521 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
35d965d5
RS		 522
523/* Given an rtx X being reloaded into a reg required to be
524 in class CLASS, return the class of reg to actually use.
525 In general this is just CLASS; but on some machines
526 in some cases it is preferable to use a more restrictive class. */
527#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
528
ff9940b0
RE		 529/* Return the register class of a scratch register needed to copy IN into
530 or out of a register in CLASS in MODE. If it can be done directly,
531 NO_REGS is returned. */
532#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
533 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
534 && true_regnum (X) == -1) ? GENERAL_REGS \
7fc6c9f0 535 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
ff9940b0 536
35d965d5
RS		 537/* Return the maximum number of consecutive registers
538 needed to represent mode MODE in a register of class CLASS.
539 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
540#define CLASS_MAX_NREGS(CLASS, MODE) \
541 ((CLASS) == FPU_REGS ? 1 \
542 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
543
ff9940b0 544/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
35d965d5
RS		 545#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
546 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
547 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
ff9940b0 548 ? 20 : 2)
35d965d5
RS		 549\f
550/* Stack layout; function entry, exit and calling. */
551
552/* Define this if pushing a word on the stack
553 makes the stack pointer a smaller address. */
554#define STACK_GROWS_DOWNWARD 1
555
556/* Define this if the nominal address of the stack frame
557 is at the high-address end of the local variables;
558 that is, each additional local variable allocated
559 goes at a more negative offset in the frame. */
560#define FRAME_GROWS_DOWNWARD 1
561
562/* Offset within stack frame to start allocating local variables at.
563 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
564 first local allocated. Otherwise, it is the offset to the BEGINNING
565 of the first local allocated. */
566#define STARTING_FRAME_OFFSET 0
567
568/* If we generate an insn to push BYTES bytes,
569 this says how many the stack pointer really advances by. */
570#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
571
572/* Offset of first parameter from the argument pointer register value. */
573#define FIRST_PARM_OFFSET(FNDECL) 4
574
575/* Value is the number of byte of arguments automatically
576 popped when returning from a subroutine call.
577 FUNTYPE is the data type of the function (as a tree),
578 or for a library call it is an identifier node for the subroutine name.
579 SIZE is the number of bytes of arguments passed on the stack.
580
581 On the ARM, the caller does not pop any of its arguments that were passed
582 on the stack. */
583#define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
584
585/* Define how to find the value returned by a function.
586 VALTYPE is the data type of the value (as a tree).
587 If the precise function being called is known, FUNC is its FUNCTION_DECL;
588 otherwise, FUNC is 0. */
589#define FUNCTION_VALUE(VALTYPE, FUNC) \
590 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
591 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
592 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
593
594/* Define how to find the value returned by a library function
595 assuming the value has mode MODE. */
596#define LIBCALL_VALUE(MODE) \
597 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
598 ? gen_rtx (REG, MODE, 16) \
599 : gen_rtx (REG, MODE, 0))
600
601/* 1 if N is a possible register number for a function value.
602 On the ARM, only r0 and f0 can return results. */
603#define FUNCTION_VALUE_REGNO_P(REGNO) \
604 ((REGNO) == 0 || (REGNO) == 16)
605
606/* Define where to put the arguments to a function.
607 Value is zero to push the argument on the stack,
608 or a hard register in which to store the argument.
609
610 MODE is the argument's machine mode.
611 TYPE is the data type of the argument (as a tree).
612 This is null for libcalls where that information may
613 not be available.
614 CUM is a variable of type CUMULATIVE_ARGS which gives info about
615 the preceding args and about the function being called.
616 NAMED is nonzero if this argument is a named parameter
617 (otherwise it is an extra parameter matching an ellipsis).
618
619 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
620 other arguments are passed on the stack. If (NAMED == 0) (which happens
621 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
622 passed in the stack (function_prologue will indeed make it pass in the
623 stack if necessary). */
624#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
625 ((NAMED) \
626 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
627 : 0)
628
629/* For an arg passed partly in registers and partly in memory,
630 this is the number of registers used.
631 For args passed entirely in registers or entirely in memory, zero. */
632#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
633 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
634 ? GET_MODE_SIZE (MODE) \
635 : int_size_in_bytes (TYPE)) \
636 ? 4 - (CUM) / 4 : 0)
637
638/* A C type for declaring a variable that is used as the first argument of
639 `FUNCTION_ARG' and other related values. For some target machines, the
640 type `int' suffices and can hold the number of bytes of argument so far.
641
642 On the ARM, this is the number of bytes of arguments scanned so far. */
643#define CUMULATIVE_ARGS int
644
645/* Initialize a variable CUM of type CUMULATIVE_ARGS
646 for a call to a function whose data type is FNTYPE.
647 For a library call, FNTYPE is 0.
648 On the ARM, the offset starts at 0. */
649#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
ff9940b0 650 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
35d965d5
RS		 651
652/* Update the data in CUM to advance over an argument
653 of mode MODE and data type TYPE.
654 (TYPE is null for libcalls where that information may not be available.) */
655#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
656 (CUM) += ((MODE) != BLKmode \
657 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
658 : (int_size_in_bytes (TYPE) + 3) & ~3) \
659
660/* 1 if N is a possible register number for function argument passing.
661 On the ARM, r0-r3 are used to pass args. */
662#define FUNCTION_ARG_REGNO_P(REGNO) \
663 ((REGNO) >= 0 && (REGNO) <= 3)
664
665/* Perform any actions needed for a function that is receiving a variable
666 number of arguments. CUM is as above. MODE and TYPE are the mode and type
667 of the current parameter. PRETEND_SIZE is a variable that should be set to
668 the amount of stack that must be pushed by the prolog to pretend that our
669 caller pushed it.
670
671 Normally, this macro will push all remaining incoming registers on the
672 stack and set PRETEND_SIZE to the length of the registers pushed.
673
674 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
675 named arg and all anonymous args onto the stack.
676 XXX I know the prologue shouldn't be pushing registers, but it is faster
677 that way. */
678#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
679{ \
680 extern int current_function_anonymous_args; \
681 current_function_anonymous_args = 1; \
682 if ((CUM) < 16) \
683 (PRETEND_SIZE) = 16 - (CUM); \
684}
685
686/* Generate assembly output for the start of a function. */
687#define FUNCTION_PROLOGUE(STREAM, SIZE) \
008cf58a 688 output_func_prologue ((STREAM), (SIZE))
35d965d5
RS		 689
690/* Call the function profiler with a given profile label. The Acorn compiler
691 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
692 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
693 to mind about this! */
4eda77ec
RE		 694#define FUNCTION_PROFILER(STREAM,LABELNO) \
695{ \
696 fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
697 fprintf(STREAM, "\tbl\tmcount\n"); \
698 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
699 arm_increase_location (12); \
35d965d5
RS		 700}
701
702/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
703 the stack pointer does not matter. The value is tested only in
704 functions that have frame pointers.
705 No definition is equivalent to always zero.
706
707 On the ARM, the function epilogue recovers the stack pointer from the
708 frame. */
709#define EXIT_IGNORE_STACK 1
710
711/* Generate the assembly code for function exit. */
712#define FUNCTION_EPILOGUE(STREAM, SIZE) \
008cf58a 713 output_func_epilogue ((STREAM), (SIZE))
35d965d5
RS		 714
715/* Determine if the epilogue should be output as RTL.
716 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
ff9940b0
RE		 717#define USE_RETURN_INSN use_return_insn ()
718
719/* Definitions for register eliminations.
720
721 This is an array of structures. Each structure initializes one pair
722 of eliminable registers. The "from" register number is given first,
723 followed by "to". Eliminations of the same "from" register are listed
724 in order of preference.
725
726 We have two registers that can be eliminated on the ARM. First, the
727 arg pointer register can often be eliminated in favor of the stack
728 pointer register. Secondly, the pseudo frame pointer register can always
729 be eliminated; it is replaced with either the stack or the real frame
730 pointer. */
731
732#define ELIMINABLE_REGS \
733{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
734 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
735 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
736 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
737
738/* Given FROM and TO register numbers, say whether this elimination is allowed.
739 Frame pointer elimination is automatically handled.
740
741 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
742 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
743 pointer, we must eliminate FRAME_POINTER_REGNUM into
744 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
745#define CAN_ELIMINATE(FROM, TO) \
746 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
747
748/* Define the offset between two registers, one to be eliminated, and the other
749 its replacement, at the start of a routine. */
750#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
751{ \
752 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
753 (OFFSET) = 0; \
754 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
755 (OFFSET) = (get_frame_size () + 3 & ~3); \
756 else \
757 { \
758 int regno; \
759 int offset = 12; \
008cf58a 760 int saved_hard_reg = 0; \
ff9940b0 761 \
008cf58a
RE		 762 for (regno = 0; regno <= 10; regno++) \
763 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
764 saved_hard_reg = 1, offset += 4; \
765 for (regno = 16; regno <=23; regno++) \
766 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
ff9940b0
RE		 767 offset += 12; \
768 if ((FROM) == FRAME_POINTER_REGNUM) \
769 (OFFSET) = -offset; \
770 else \
771 { \
772 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
773 offset -= 16; \
008cf58a 774 if (regs_ever_live[14] || saved_hard_reg) \
ff9940b0
RE		 775 offset += 4; \
776 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
777 } \
778 } \
779}
35d965d5 780
35d965d5
RS		 781/* Output assembler code for a block containing the constant parts
782 of a trampoline, leaving space for the variable parts.
783
784 On the ARM, (if r8 is the static chain regnum, and remembering that
785 referencing pc adds an offset of 8) the trampoline looks like:
786 ldr r8, [pc, #0]
787 ldr pc, [pc]
788 .word static chain value
789 .word function's address */
4eda77ec
RE		 790#define TRAMPOLINE_TEMPLATE(FILE) \
791{ \
792 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \
793 ARM_REG_PREFIX); \
794 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \
795 ARM_REG_PREFIX); \
796 fprintf ((FILE), "\t.word\t0\n"); \
797 fprintf ((FILE), "\t.word\t0\n"); \
35d965d5
RS		 798}
799
800/* Length in units of the trampoline for entering a nested function. */
801#define TRAMPOLINE_SIZE 16
802
803/* Alignment required for a trampoline in units. */
804#define TRAMPOLINE_ALIGN 4
805
806/* Emit RTL insns to initialize the variable parts of a trampoline.
807 FNADDR is an RTX for the address of the function's pure code.
808 CXT is an RTX for the static chain value for the function. */
809#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
810{ \
811 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
812 (CXT)); \
813 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
814 (FNADDR)); \
815}
816
35d965d5
RS		 817\f
818/* Addressing modes, and classification of registers for them. */
819
820#define HAVE_POST_INCREMENT 1
821#define HAVE_PRE_INCREMENT 1
822#define HAVE_POST_DECREMENT 1
823#define HAVE_PRE_DECREMENT 1
824
825/* Macros to check register numbers against specific register classes. */
826
827/* These assume that REGNO is a hard or pseudo reg number.
828 They give nonzero only if REGNO is a hard reg of the suitable class
829 or a pseudo reg currently allocated to a suitable hard reg.
830 Since they use reg_renumber, they are safe only once reg_renumber
831 has been allocated, which happens in local-alloc.c.
832
833 On the ARM, don't allow the pc to be used. */
ff9940b0
RE		 834#define REGNO_OK_FOR_BASE_P(REGNO) \
835 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
836 || (REGNO) == ARG_POINTER_REGNUM \
837 || (unsigned) reg_renumber[(REGNO)] < 15 \
838 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
839 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
840#define REGNO_OK_FOR_INDEX_P(REGNO) \
35d965d5
RS		 841 REGNO_OK_FOR_BASE_P(REGNO)
842
843/* Maximum number of registers that can appear in a valid memory address.
ff9940b0
RE		 844 Shifts in addresses can't be by a register. */
845
846#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 847
848/* Recognize any constant value that is a valid address. */
849/* XXX We can address any constant, eventually... */
850#if 0
851#define CONSTANT_ADDRESS_P(X) \
852 ( GET_CODE(X) == LABEL_REF \
853 || GET_CODE(X) == SYMBOL_REF \
854 || GET_CODE(X) == CONST_INT \
855 || GET_CODE(X) == CONST )
856#endif
857
008cf58a
RE		 858#define CONSTANT_ADDRESS_P(X) \
859 (GET_CODE (X) == SYMBOL_REF \
860 && (CONSTANT_POOL_ADDRESS_P (X) \
861 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5
RS		 862
863/* Nonzero if the constant value X is a legitimate general operand.
864 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
865
866 On the ARM, allow any integer (invalid ones are removed later by insn
867 patterns), nice doubles and symbol_refs which refer to the function's
868 constant pool XXX. */
869#define LEGITIMATE_CONSTANT_P(X) \
870 (GET_CODE (X) == CONST_INT \
871 || (GET_CODE (X) == CONST_DOUBLE \
ff9940b0
RE		 872 && (const_double_rtx_ok_for_fpu (X) \
873 || neg_const_double_rtx_ok_for_fpu (X))) \
874 || CONSTANT_ADDRESS_P (X))
875
876/* Symbols in the text segment can be accessed without indirecting via the
877 constant pool; it may take an extra binary operation, but this is still
008cf58a
RE		 878 faster than indirecting via memory. Don't do this when not optimizing,
879 since we won't be calculating al of the offsets necessary to do this
880 simplification. */
ff9940b0
RE		 881
882#define ENCODE_SECTION_INFO(decl) \
883{ \
008cf58a 884 if (optimize > 0 && TREE_CONSTANT (decl) \
ff9940b0 885 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
228b6a3f
RS		 886 { \
887 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
888 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
889 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
890 } \
ff9940b0 891}
35d965d5
RS		 892
893/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
894 and check its validity for a certain class.
895 We have two alternate definitions for each of them.
896 The usual definition accepts all pseudo regs; the other rejects
897 them unless they have been allocated suitable hard regs.
898 The symbol REG_OK_STRICT causes the latter definition to be used. */
899#ifndef REG_OK_STRICT
ff9940b0 900
35d965d5
RS		 901/* Nonzero if X is a hard reg that can be used as a base reg
902 or if it is a pseudo reg. */
ff9940b0
RE		 903#define REG_OK_FOR_BASE_P(X) \
904 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
905 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
906
35d965d5
RS		 907/* Nonzero if X is a hard reg that can be used as an index
908 or if it is a pseudo reg. */
909#define REG_OK_FOR_INDEX_P(X) \
910 REG_OK_FOR_BASE_P(X)
ff9940b0
RE		 911
912#define REG_OK_FOR_PRE_POST_P(X) \
913 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
914 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
915
35d965d5 916#else
ff9940b0 917
35d965d5
RS		 918/* Nonzero if X is a hard reg that can be used as a base reg. */
919#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 920
35d965d5
RS		 921/* Nonzero if X is a hard reg that can be used as an index. */
922#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
ff9940b0
RE		 923
924#define REG_OK_FOR_PRE_POST_P(X) \
925 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
926 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
927 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
928 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
929
35d965d5
RS		 930#endif
931\f
932/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
933 that is a valid memory address for an instruction.
934 The MODE argument is the machine mode for the MEM expression
935 that wants to use this address.
936
937 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
938#define BASE_REGISTER_RTX_P(X) \
939 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
940
941#define INDEX_REGISTER_RTX_P(X) \
942 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
943
944/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
945 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
946 only be small constants. */
ff9940b0 947#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
4d01c30f
RS		 948do \
949{ \
008cf58a
RE		 950 HOST_WIDE_INT range; \
951 enum rtx_code code = GET_CODE (INDEX); \
4d01c30f
RS		 952 \
953 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
ff9940b0
RE		 954 { \
955 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
956 && INTVAL (INDEX) > -1024 \
957 && (INTVAL (INDEX) & 3) == 0) \
958 goto LABEL; \
959 } \
4d01c30f
RS		 960 else \
961 { \
ff9940b0 962 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
4d01c30f 963 goto LABEL; \
ff9940b0 964 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
4d01c30f
RS		 965 { \
966 rtx xiop0 = XEXP (INDEX, 0); \
967 rtx xiop1 = XEXP (INDEX, 1); \
968 if (INDEX_REGISTER_RTX_P (xiop0) \
969 && power_of_two_operand (xiop1, SImode)) \
970 goto LABEL; \
971 if (INDEX_REGISTER_RTX_P (xiop1) \
972 && power_of_two_operand (xiop0, SImode)) \
973 goto LABEL; \
974 } \
ff9940b0 975 if (GET_MODE_SIZE (MODE) <= 4 \
996a5f59 976 && (code == LSHIFTRT || code == ASHIFTRT \
ff9940b0
RE		 977 || code == ASHIFT || code == ROTATERT)) \
978 { \
979 rtx op = XEXP (INDEX, 1); \
980 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
981 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
982 && INTVAL (op) <= 31) \
983 goto LABEL; \
984 } \
985 range = (MODE) == HImode ? 4095 : 4096; \
986 if (code == CONST_INT && INTVAL (INDEX) < range \
987 && INTVAL (INDEX) > -range) \
988 goto LABEL; \
4d01c30f 989 } \
35d965d5
RS		 990} while (0)
991
992/* Jump to LABEL if X is a valid address RTX. This must also take
993 REG_OK_STRICT into account when deciding about valid registers, but it uses
994 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
995 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
ff9940b0
RE		 996 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
997 refs must be forced though a static cell to ensure addressability. */
35d965d5
RS		 998#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
999{ \
1000 if (BASE_REGISTER_RTX_P (X)) \
1001 goto LABEL; \
1002 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1003 && GET_CODE (XEXP (X, 0)) == REG \
1004 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1005 goto LABEL; \
1006 else if ((MODE) == TImode) \
1007 ; \
1008 else if (GET_CODE (X) == PLUS) \
1009 { \
1010 rtx xop0 = XEXP(X,0); \
1011 rtx xop1 = XEXP(X,1); \
1012 \
1013 if (BASE_REGISTER_RTX_P (xop0)) \
1014 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1015 else if (BASE_REGISTER_RTX_P (xop1)) \
1016 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1017 } \
1018 else if (GET_CODE (X) == MINUS) \
1019 { \
1020 rtx xop0 = XEXP (X,0); \
1021 rtx xop1 = XEXP (X,1); \
1022 \
1023 if (BASE_REGISTER_RTX_P (xop0)) \
1024 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1025 } \
1026 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1027 && GET_CODE (X) == SYMBOL_REF \
1028 && CONSTANT_POOL_ADDRESS_P (X)) \
1029 goto LABEL; \
1030 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1031 && GET_CODE (XEXP (X, 0)) == REG \
1032 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1033 goto LABEL; \
1034}
1035\f
1036/* Try machine-dependent ways of modifying an illegitimate address
1037 to be legitimate. If we find one, return the new, valid address.
1038 This macro is used in only one place: `memory_address' in explow.c.
1039
1040 OLDX is the address as it was before break_out_memory_refs was called.
1041 In some cases it is useful to look at this to decide what needs to be done.
1042
1043 MODE and WIN are passed so that this macro can use
1044 GO_IF_LEGITIMATE_ADDRESS.
1045
1046 It is always safe for this macro to do nothing. It exists to recognize
1047 opportunities to optimize the output.
1048
1049 On the ARM, try to convert [REG, #BIGCONST]
1050 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1051 where VALIDCONST == 0 in case of TImode. */
1052#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1053{ \
1054 if (GET_CODE (X) == PLUS) \
1055 { \
1056 rtx xop0 = XEXP (X, 0); \
1057 rtx xop1 = XEXP (X, 1); \
1058 \
1059 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1060 { \
1061 int n = INTVAL (xop1); \
1062 int low_n = ((MODE) == TImode ? 0 \
1063 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1064 rtx base_reg = gen_reg_rtx (SImode); \
1065 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1066 gen_rtx (CONST_INT, \
1067 VOIDmode, n - low_n)), \
1068 0); \
1069 emit_move_insn (base_reg, val); \
1070 (X) = (low_n == 0 ? base_reg \
1071 : gen_rtx (PLUS, SImode, base_reg, \
1072 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1073 } \
1074 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1075 { \
1076 int n = INTVAL (xop0); \
1077 int low_n = ((MODE) == TImode ? 0 \
1078 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1079 rtx base_reg = gen_reg_rtx (SImode); \
1080 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1081 gen_rtx (CONST_INT, \
1082 VOIDmode, n - low_n)), \
1083 0); \
1084 emit_move_insn (base_reg, val); \
1085 (X) = (low_n == 0 ? base_reg \
1086 : gen_rtx (PLUS, SImode, base_reg, \
1087 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1088 } \
1089 } \
1090 if (memory_address_p (MODE, X)) \
1091 goto win; \
1092}
1093
1094/* Go to LABEL if ADDR (a legitimate address expression)
1095 has an effect that depends on the machine mode it is used for. */
1096#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1097{ \
1098 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1099 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1100 goto LABEL; \
1101}
1102\f
1103/* Specify the machine mode that this machine uses
1104 for the index in the tablejump instruction. */
1105#define CASE_VECTOR_MODE SImode
1106
1107/* Define this if the tablejump instruction expects the table
1108 to contain offsets from the address of the table.
1109 Do not define this if the table should contain absolute addresses. */
1110/* #define CASE_VECTOR_PC_RELATIVE */
1111
1112/* Specify the tree operation to be used to convert reals to integers. */
1113#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1114
1115/* This is the kind of divide that is easiest to do in the general case. */
1116#define EASY_DIV_EXPR TRUNC_DIV_EXPR
1117
ff9940b0
RE		 1118/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1119 unsigned is probably best, but may break some code. */
1120#ifndef DEFAULT_SIGNED_CHAR
35d965d5
RS		 1121#define DEFAULT_SIGNED_CHAR 1
1122#endif
1123
1124/* Don't cse the address of the function being compiled. */
1125#define NO_RECURSIVE_FUNCTION_CSE 1
1126
1127/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 1128 in one reasonably fast instruction. */
1129#define MOVE_MAX 4
35d965d5 1130
ff9940b0
RE		 1131/* Define if operations between registers always perform the operation
1132 on the full register even if a narrower mode is specified. */
1133#define WORD_REGISTER_OPERATIONS
1134
1135/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1136 will either zero-extend or sign-extend. The value of this macro should
1137 be the code that says which one of the two operations is implicitly
1138 done, NIL if none. */
9c872872
RE		 1139#define LOAD_EXTEND_OP(MODE) \
1140 ((MODE) == QImode ? ZERO_EXTEND \
1141 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
ff9940b0 1142
35d965d5
RS		 1143/* Define this if zero-extension is slow (more than one real instruction).
1144 On the ARM, it is more than one instruction only if not fetching from
1145 memory. */
1146/* #define SLOW_ZERO_EXTEND */
1147
1148/* Nonzero if access to memory by bytes is slow and undesirable. */
1149#define SLOW_BYTE_ACCESS 0
1150
1151/* Immediate shift counts are truncated by the output routines (or was it
1152 the assembler?). Shift counts in a register are truncated by ARM. Note
1153 that the native compiler puts too large (> 32) immediate shift counts
1154 into a register and shifts by the register, letting the ARM decide what
1155 to do instead of doing that itself. */
ff9940b0
RE		 1156/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1157 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1158 On the arm, Y in a register is used modulo 256 for the shift. Only for
1159 rotates is modulo 32 used. */
1160/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5
RS		 1161
1162/* XX This is not true, is it? */
1163/* All integers have the same format so truncation is easy. */
1164#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1165
1166/* Calling from registers is a massive pain. */
1167#define NO_FUNCTION_CSE 1
1168
1169/* Chars and shorts should be passed as ints. */
1170#define PROMOTE_PROTOTYPES 1
1171
35d965d5
RS		 1172/* The machine modes of pointers and functions */
1173#define Pmode SImode
1174#define FUNCTION_MODE Pmode
1175
1176/* The structure type of the machine dependent info field of insns
1177 No uses for this yet. */
1178/* #define INSN_MACHINE_INFO struct machine_info */
1179
1180/* The relative costs of various types of constants. Note that cse.c defines
1181 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
ff9940b0
RE		 1182#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1183 case CONST_INT: \
1184 if (const_ok_for_arm (INTVAL (RTX))) \
1185 return (OUTER_CODE) == SET ? 2 : -1; \
1186 else if (OUTER_CODE == AND \
1187 && const_ok_for_arm (~INTVAL (RTX))) \
1188 return -1; \
1189 else if ((OUTER_CODE == COMPARE \
1190 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1191 && const_ok_for_arm (-INTVAL (RTX))) \
1192 return -1; \
1193 else \
1194 return 5; \
1195 case CONST: \
1196 case LABEL_REF: \
1197 case SYMBOL_REF: \
1198 return 6; \
1199 case CONST_DOUBLE: \
1200 if (const_double_rtx_ok_for_fpu (RTX)) \
1201 return (OUTER_CODE) == SET ? 2 : -1; \
1202 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1203 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1204 return -1; \
1205 return(7);
1206
1207#define RTX_COSTS(X,CODE,OUTER_CODE) \
1208 case MEM: \
1209 { \
1210 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1211 return (COSTS_N_INSNS (10*num_words)); \
1212 } \
1213 case MULT: \
1214 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1215 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1216 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1217 return COSTS_N_INSNS (9); \
ff9940b0
RE		 1218 case ASHIFT: \
1219 case LSHIFTRT: \
1220 case ASHIFTRT: \
1221 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1222 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1223 break; \
1224 case MINUS: \
1225 { \
1226 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1227 if (code == MULT) \
1228 { \
1229 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1230 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1231 return COSTS_N_INSNS (1); \
1232 break; \
1233 } \
996a5f59 1234 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
ff9940b0
RE		 1235 return COSTS_N_INSNS (1); \
1236 } /* fall through */ \
1237 case PLUS: \
1238 case IOR: \
1239 case XOR: \
1240 case AND: \
1241 { \
1242 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1243 if (code == MULT) \
1244 { \
1245 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1246 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1247 return COSTS_N_INSNS (1); \
1248 if (GET_CODE (X) == PLUS) \
1249 return COSTS_N_INSNS (12); \
1250 break; \
1251 } \
996a5f59 1252 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
ff9940b0
RE		 1253 return COSTS_N_INSNS (1); \
1254 break; \
1255 } \
1256 case NOT: \
1257 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1258 case IF_THEN_ELSE: \
1259 { \
1260 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1261 return COSTS_N_INSNS (4); \
1262 return COSTS_N_INSNS (1); \
1263 } \
1264 case SIGN_EXTEND: \
1265 return COSTS_N_INSNS (2); \
1266 case ZERO_EXTEND: \
1267 if (GET_MODE (XEXP (X, 0)) == QImode) \
1268 { \
1269 if (GET_CODE (XEXP (X, 0)) == MEM) \
1270 return COSTS_N_INSNS (10); \
1271 return COSTS_N_INSNS (1); \
1272 } \
1273 break; \
1274 case COMPARE: \
1275 if (GET_CODE (XEXP (X, 1)) == REG) \
1276 return 4; \
1277 case SMIN: \
1278 case SMAX: \
1279 case UMIN: \
1280 case UMAX: \
1281 return COSTS_N_INSNS (3); \
1282 case ABS: \
1283 if (GET_MODE (X) == SImode) \
1284 return COSTS_N_INSNS (2); \
1285 return COSTS_N_INSNS (1);
1286
1287/* Moves to and from memory are quite expensive */
1288#define MEMORY_MOVE_COST(MODE) 10
1289
1290/* All address computations that can be done are free */
1291#define ADDRESS_COST(x) 2
1292
1293/* Try to generate sequences that don't involve branches, we can then use
1294 conditional instructions */
1295#define BRANCH_COST 4
35d965d5 1296\f
ff9940b0
RE		 1297/* Condition code information. */
1298/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1299 return the mode to be used for the comparison.
1300 CCFPEmode should be used with floating inequalites,
1301 CCFPmode should be used with floating equalities.
1302 CC_NOOVmode should be used with SImode integer equalites
1303 CCmode should be used otherwise. */
1304
1305#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1306
1307#define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1308
1309#define SELECT_CC_MODE(OP,X,Y) \
1310 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1311 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1312 : ((GET_MODE (X) == SImode) \
1313 && ((OP) == EQ || (OP) == NE) \
1314 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1315 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1316 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1317 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
996a5f59 1318 || GET_CODE (X) == LSHIFTRT \
ff9940b0
RE		 1319 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1320 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1321 ? CC_NOOVmode \
1322 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1323
008cf58a
RE		 1324#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1325
ff9940b0
RE		 1326#define STORE_FLAG_VALUE 1
1327
1328/* Define the information needed to generate branch insns. This is
1329 stored from the compare operation. Note that we can't use "rtx" here
1330 since it hasn't been defined! */
1331
1332extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1333extern int arm_compare_fp;
1334
1335/* Define the codes that are matched by predicates in arm.c */
1336#define PREDICATE_CODES \
1337 {"s_register_operand", {SUBREG, REG}}, \
1338 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1339 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1340 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1341 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1342 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1343 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1344 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
996a5f59 1345 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
ff9940b0
RE		 1346 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1347 {"load_multiple_operation", {PARALLEL}}, \
1348 {"store_multiple_operation", {PARALLEL}}, \
1349 {"equality_operator", {EQ, NE}}, \
1350 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1351 {"const_shift_operand", {CONST_INT}}, \
1352 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1353 {"cc_register", {REG}},
1354
35d965d5
RS		 1355\f
1356/* Assembler output control */
1357
ff9940b0
RE		 1358#ifndef ARM_OS_NAME
1359#define ARM_OS_NAME "(generic)"
1360#endif
1361
35d965d5 1362/* The text to go at the start of the assembler file */
4eda77ec
RE		 1363#define ASM_FILE_START(STREAM) \
1364{ \
1365 extern char *version_string; \
1366 fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \
1367 ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \
1368 fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1369 fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1370 fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1371 fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1372 fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1373 fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1374 fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
35d965d5
RS		 1375}
1376
1377#define ASM_APP_ON ""
1378#define ASM_APP_OFF ""
1379
1380/* Switch to the text or data segment. */
8cf6b9ca
RS		 1381#define TEXT_SECTION_ASM_OP ".text"
1382#define DATA_SECTION_ASM_OP ".data"
35d965d5 1383
4eda77ec
RE		 1384/* The assembler's names for the registers. */
1385#ifndef REGISTER_NAMES
35d965d5
RS		 1386#define REGISTER_NAMES \
1387{ \
1388 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
4eda77ec 1389 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
ff9940b0
RE		 1390 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1391 "cc", "sfp", "afp" \
35d965d5 1392}
4eda77ec
RE		 1393#endif
1394
1395#ifndef ADDITIONAL_REGISTER_NAMES
1396#define ADDITIONAL_REGISTER_NAMES \
1397{ \
1398 {"a1", 0}, \
1399 {"a2", 1}, \
1400 {"a3", 2}, \
1401 {"a4", 3}, \
1402 {"v1", 4}, \
1403 {"v2", 5}, \
1404 {"v3", 6}, \
1405 {"v4", 7}, \
1406 {"v5", 8}, \
1407 {"v6", 9}, \
1408 {"rfp", 9}, /* Gcc used to call it this */ \
1409 {"sb", 9}, \
1410 {"v7", 10}, \
1411 {"r10", 10}, \
1412 {"r11", 11}, /* fp */ \
1413 {"r12", 12}, /* ip */ \
1414 {"r13", 13}, /* sp */ \
1415 {"r14", 14}, /* lr */ \
1416 {"r15", 15} /* pc */ \
1417}
1418#endif
35d965d5 1419
ff9940b0
RE		 1420/* Arm Assembler barfs on dollars */
1421#define DOLLARS_IN_IDENTIFIERS 0
1422
1423#define NO_DOLLAR_IN_LABEL
1424
35d965d5
RS		 1425/* DBX register number for a given compiler register number */
1426#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1427
ff9940b0
RE		 1428/* Generate DBX debugging information. riscix.h will undefine this because
1429 the native assembler does not support stabs. */
35d965d5
RS		 1430#define DBX_DEBUGGING_INFO 1
1431
1432/* Acorn dbx moans about continuation chars, so don't use any. */
1433#define DBX_CONTIN_LENGTH 0
1434
ff9940b0
RE		 1435/* Output a source filename for the debugger. RISCiX dbx insists that the
1436 ``desc'' field is set to compiler version number >= 315 (sic). */
1437#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1438do { \
1439 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1440 &ltext_label_name[1]); \
1441 text_section (); \
1442 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1443} while (0)
1444
35d965d5
RS		 1445/* Output a label definition. */
1446#define ASM_OUTPUT_LABEL(STREAM,NAME) \
1447 arm_asm_output_label ((STREAM), (NAME))
1448
1449/* Output a function label definition. */
1450#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1451 ASM_OUTPUT_LABEL(STREAM, NAME)
1452
1453/* Output a globalising directive for a label. */
1454#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1455 (fprintf (STREAM, "\t.global\t"), \
1456 assemble_name (STREAM, NAME), \
1457 fputc ('\n',STREAM)) \
1458
1459/* Output a reference to a label. */
1460#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1461 fprintf (STREAM, "_%s", NAME)
1462
1463/* Make an internal label into a string. */
1464#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1465 sprintf (STRING, "*%s%d", PREFIX, NUM)
1466
1467/* Output an internal label definition. */
1468#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1469 do \
1470 { \
1471 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1472 extern int arm_target_label, arm_ccfsm_state; \
26563586 1473 extern rtx arm_target_insn; \
35d965d5 1474 \
ff9940b0
RE		 1475 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1476 && !strcmp (PREFIX, "L")) \
1477 { \
1478 arm_ccfsm_state = 0; \
26563586 1479 arm_target_insn = NULL; \
ff9940b0
RE		 1480 } \
1481 strcpy (s, "*"); \
1482 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1483 arm_asm_output_label (STREAM, s); \
35d965d5
RS		 1484 } while (0)
1485
1486/* Nothing special is done about jump tables */
1487/* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1488/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1489
1490/* Construct a private name. */
1491#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1492 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1493 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1494
1495/* Output a push or a pop instruction (only used when profiling). */
4eda77ec
RE		 1496#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1497 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1498 reg_names[REGNO])
35d965d5 1499
4eda77ec
RE		 1500#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1501 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1502 reg_names[REGNO])
35d965d5
RS		 1503
1504/* Output a relative address. Not needed since jump tables are absolute
1505 but we must define it anyway. */
1506#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1507 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1508
1509/* Output an element of a dispatch table. */
1510#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
008cf58a 1511 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
35d965d5 1512
7fc6c9f0
RK		 1513/* Output various types of constants. For real numbers we output hex, with
1514 a comment containing the "human" value, this allows us to pass NaN's which
1515 the riscix assembler doesn't understand (it also makes cross-assembling
1516 less likely to fail). */
1517
ff9940b0 1518#define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
7fc6c9f0
RK		 1519do { char dstr[30]; \
1520 long l[3]; \
ff9940b0
RE		 1521 arm_increase_location (12); \
1522 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
7fc6c9f0 1523 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
ff9940b0 1524 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1525 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \
1526 l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \
ff9940b0 1527 else \
4eda77ec
RE		 1528 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\
1529 l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1530 } while (0)
1531
1532
7fc6c9f0
RK		 1533#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1534do { char dstr[30]; \
1535 long l[2]; \
1536 arm_increase_location (8); \
1537 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1538 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1539 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1540 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \
1541 l[1], ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1542 else \
4eda77ec
RE		 1543 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \
1544 l[1], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1545 } while (0)
1546
7fc6c9f0
RK		 1547#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1548do { char dstr[30]; \
1549 long l; \
1550 arm_increase_location (4); \
1551 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1552 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1553 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1554 fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \
1555 ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1556 else \
4eda77ec
RE		 1557 fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \
1558 ARM_COMMENT_CHAR, dstr); \
ff9940b0 1559 } while (0);
35d965d5 1560
7fc6c9f0
RK		 1561#define ASM_OUTPUT_INT(STREAM, EXP) \
1562 (fprintf (STREAM, "\t.word\t"), \
1563 output_addr_const (STREAM, (EXP)), \
1564 arm_increase_location (4), \
35d965d5
RS		 1565 fputc ('\n', STREAM))
1566
1567#define ASM_OUTPUT_SHORT(STREAM, EXP) \
1568 (fprintf (STREAM, "\t.short\t"), \
1569 output_addr_const (STREAM, (EXP)), \
1570 arm_increase_location (2), \
1571 fputc ('\n', STREAM))
1572
1573#define ASM_OUTPUT_CHAR(STREAM, EXP) \
1574 (fprintf (STREAM, "\t.byte\t"), \
1575 output_addr_const (STREAM, (EXP)), \
1576 arm_increase_location (1), \
1577 fputc ('\n', STREAM))
1578
1579#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1580 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1581 arm_increase_location (1))
1582
1583#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
f70bf59e 1584 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
35d965d5
RS		 1585
1586/* Output a gap. In fact we fill it with nulls. */
1587#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1588 (arm_increase_location (NBYTES), \
1589 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1590
1591/* Align output to a power of two. Horrible /bin/as. */
1592#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1593 do \
1594 { \
1595 register int amount = 1 << (POWER); \
1596 extern int arm_text_location; \
1597 \
1598 if (amount == 2) \
1599 fprintf (STREAM, "\t.even\n"); \
1600 else \
1601 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1602 \
1603 if (in_text_section ()) \
1604 arm_text_location = ((arm_text_location + amount - 1) \
1605 & ~(amount - 1)); \
1606 } while (0)
1607
1608/* Output a common block */
4eda77ec
RE		 1609#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1610 (fprintf (STREAM, "\t.comm\t"), \
1611 assemble_name ((STREAM), (NAME)), \
1612 fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE))
35d965d5
RS		 1613
1614/* Output a local common block. /bin/as can't do this, so hack a `.space' into
1615 the bss segment. Note that this is *bad* practice. */
1616#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1617 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1618
35d965d5
RS		 1619/* Output a source line for the debugger. */
1620/* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1621
1622/* Output a #ident directive. */
1623#define ASM_OUTPUT_IDENT(STREAM,STRING) \
1624 fprintf (STREAM,"- - - ident %s\n",STRING)
1625
1626/* The assembler's parentheses characters. */
1627#define ASM_OPEN_PAREN "("
1628#define ASM_CLOSE_PAREN ")"
1629
1630/* Target characters. */
1631#define TARGET_BELL 007
1632#define TARGET_BS 010
1633#define TARGET_TAB 011
1634#define TARGET_NEWLINE 012
1635#define TARGET_VT 013
1636#define TARGET_FF 014
1637#define TARGET_CR 015
1638\f
35d965d5
RS		 1639/* Only perform branch elimination (by making instructions conditional) if
1640 we're optimising. Otherwise it's of no use anyway. */
1641#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1642 if (optimize) \
1643 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1644
7bc7696c
RE		 1645#ifndef ARM_COMMENT_CHAR
1646#define ARM_COMMENT_CHAR '@'
1647#endif
1648
1649/* Default is for register names not to have a prefix. */
1650#ifndef ARM_REG_PREFIX
1651#define ARM_REG_PREFIX ""
1652#endif
1653
1654#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1655 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1656/* Output an operand of an instruction. */
35d965d5 1657#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 1658 arm_print_operand (STREAM, X, CODE)
1659
1660#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1661 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1662 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1663 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1664 ? ((~ (HOST_WIDE_INT) 0) \
1665 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1666 : 0))))
35d965d5
RS		 1667
1668/* Output the address of an operand. */
1669#define PRINT_OPERAND_ADDRESS(STREAM,X) \
1670{ \
1671 int is_minus = GET_CODE (X) == MINUS; \
1672 \
1673 if (GET_CODE (X) == REG) \
4eda77ec
RE		 1674 fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \
1675 reg_names[REGNO (X)]); \
35d965d5
RS		 1676 else if (GET_CODE (X) == PLUS || is_minus) \
1677 { \
1678 rtx base = XEXP (X, 0); \
1679 rtx index = XEXP (X, 1); \
1680 char *base_reg_name; \
7bc7696c 1681 HOST_WIDE_INT offset = 0; \
35d965d5
RS		 1682 if (GET_CODE (base) != REG) \
1683 { \
1684 /* Ensure that BASE is a register (one of them must be). */ \
1685 rtx temp = base; \
1686 base = index; \
1687 index = temp; \
1688 } \
1689 base_reg_name = reg_names[REGNO (base)]; \
1690 switch (GET_CODE (index)) \
1691 { \
1692 case CONST_INT: \
1693 offset = INTVAL (index); \
1694 if (is_minus) \
1695 offset = -offset; \
4eda77ec
RE		 1696 fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \
1697 base_reg_name, offset); \
35d965d5
RS		 1698 break; \
1699 \
1700 case REG: \
4eda77ec
RE		 1701 fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \
1702 base_reg_name, is_minus ? "-" : "", \
1703 ARM_REG_PREFIX, reg_names[REGNO (index)] ); \
35d965d5
RS		 1704 break; \
1705 \
1706 case MULT: \
ff9940b0
RE		 1707 case ASHIFTRT: \
1708 case LSHIFTRT: \
1709 case ASHIFT: \
ff9940b0
RE		 1710 case ROTATERT: \
1711 { \
4eda77ec
RE		 1712 fprintf (STREAM, "[%s%s, %s%s%s, ", ARM_REG_PREFIX, \
1713 base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\
7bc7696c
RE		 1714 reg_names[REGNO (XEXP (index, 0))]); \
1715 arm_print_operand (STREAM, index, 'S'); \
1716 fputs ("]", STREAM); \
ff9940b0
RE		 1717 break; \
1718 } \
35d965d5
RS		 1719 \
1720 default: \
1721 abort(); \
1722 } \
1723 } \
1724 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1725 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1726 { \
1727 extern int output_memory_reference_mode; \
1728 \
1729 if (GET_CODE (XEXP (X, 0)) != REG) \
1730 abort (); \
1731 \
1732 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
4eda77ec
RE		 1733 fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \
1734 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1735 GET_CODE (X) == PRE_DEC ? "-" : "", \
1736 GET_MODE_SIZE (output_memory_reference_mode)); \
1737 else \
4eda77ec
RE		 1738 fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \
1739 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1740 GET_CODE (X) == POST_DEC ? "-" : "", \
1741 GET_MODE_SIZE (output_memory_reference_mode)); \
1742 } \
1743 else output_addr_const(STREAM, X); \
1744}
Mirror of https://gcc.gnu.org/git/gcc.git