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[thirdparty/gcc.git] / gcc / config / arm / arm.h
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f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
23a5b65a 2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
35d965d5 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 4 and Martin Simmons (@harleqn.co.uk).
949d79eb 5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
4f448245 8 This file is part of GCC.
35d965d5 9
4f448245
NC		 10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
2f83c7d6 12 by the Free Software Foundation; either version 3, or (at your
4f448245 13 option) any later version.
35d965d5 14
4f448245
NC		 15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
35d965d5 19
999db125
GJL		 20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
23
4f448245 24 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 25 along with GCC; see the file COPYING3. If not see
26 <http://www.gnu.org/licenses/>. */
35d965d5 27
88657302
RH		 28#ifndef GCC_ARM_H
29#define GCC_ARM_H
b355a481 30
46107b99
RE		 31/* We can't use enum machine_mode inside a generator file because it
32 hasn't been created yet; we shouldn't be using any code that
33 needs the real definition though, so this ought to be safe. */
34#ifdef GENERATOR_FILE
35#define MACHMODE int
36#else
37#include "insn-modes.h"
38#define MACHMODE enum machine_mode
39#endif
40
9403b7f7
RS		 41#include "config/vxworks-dummy.h"
42
35fd3193 43/* The architecture define. */
78011587
PB		 44extern char arm_arch_name[];
45
e6471be6
NB		 46/* Target CPU builtins. */
47#define TARGET_CPU_CPP_BUILTINS() \
48 do \
49 { \
c884924f
JG		 50 if (TARGET_DSP_MULTIPLY) \
51 builtin_define ("__ARM_FEATURE_DSP"); \
9e94a7fc
MGD		 52 if (TARGET_ARM_QBIT) \
53 builtin_define ("__ARM_FEATURE_QBIT"); \
54 if (TARGET_ARM_SAT) \
55 builtin_define ("__ARM_FEATURE_SAT"); \
021b5e6b
KT		 56 if (TARGET_CRYPTO) \
57 builtin_define ("__ARM_FEATURE_CRYPTO"); \
5d248b41
JG		 58 if (unaligned_access) \
59 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
582e2e43
KT		 60 if (TARGET_CRC32) \
61 builtin_define ("__ARM_FEATURE_CRC32"); \
62 if (TARGET_32BIT) \
63 builtin_define ("__ARM_32BIT_STATE"); \
9e94a7fc
MGD		 64 if (TARGET_ARM_FEATURE_LDREX) \
65 builtin_define_with_int_value ( \
66 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
67 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
68 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
69 builtin_define ("__ARM_FEATURE_CLZ"); \
70 if (TARGET_INT_SIMD) \
71 builtin_define ("__ARM_FEATURE_SIMD32"); \
72 \
73 builtin_define_with_int_value ( \
74 "__ARM_SIZEOF_MINIMAL_ENUM", \
75 flag_short_enums ? 1 : 4); \
76 builtin_define_with_int_value ( \
77 "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \
78 if (TARGET_ARM_ARCH_PROFILE) \
79 builtin_define_with_int_value ( \
80 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
81 \
9b66ebb1
PB		 82 /* Define __arm__ even when in thumb mode, for \
83 consistency with armcc. */ \
84 builtin_define ("__arm__"); \
9e94a7fc
MGD		 85 if (TARGET_ARM_ARCH) \
86 builtin_define_with_int_value ( \
87 "__ARM_ARCH", TARGET_ARM_ARCH); \
88 if (arm_arch_notm) \
89 builtin_define ("__ARM_ARCH_ISA_ARM"); \
61f0ccff 90 builtin_define ("__APCS_32__"); \
9b66ebb1 91 if (TARGET_THUMB) \
e6471be6 92 builtin_define ("__thumb__"); \
5b3e6663
PB		 93 if (TARGET_THUMB2) \
94 builtin_define ("__thumb2__"); \
9e94a7fc
MGD		 95 if (TARGET_ARM_ARCH_ISA_THUMB) \
96 builtin_define_with_int_value ( \
97 "__ARM_ARCH_ISA_THUMB", \
98 TARGET_ARM_ARCH_ISA_THUMB); \
e6471be6
NB		 99 \
100 if (TARGET_BIG_END) \
101 { \
102 builtin_define ("__ARMEB__"); \
9e94a7fc 103 builtin_define ("__ARM_BIG_ENDIAN"); \
e6471be6
NB		 104 if (TARGET_THUMB) \
105 builtin_define ("__THUMBEB__"); \
106 if (TARGET_LITTLE_WORDS) \
107 builtin_define ("__ARMWEL__"); \
108 } \
109 else \
110 { \
111 builtin_define ("__ARMEL__"); \
112 if (TARGET_THUMB) \
113 builtin_define ("__THUMBEL__"); \
114 } \
115 \
e6471be6
NB		 116 if (TARGET_SOFT_FLOAT) \
117 builtin_define ("__SOFTFP__"); \
118 \
9b66ebb1 119 if (TARGET_VFP) \
b5b620a4
JT		 120 builtin_define ("__VFP_FP__"); \
121 \
9e94a7fc
MGD		 122 if (TARGET_ARM_FP) \
123 builtin_define_with_int_value ( \
124 "__ARM_FP", TARGET_ARM_FP); \
125 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
126 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
127 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
128 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
129 if (TARGET_FMA) \
130 builtin_define ("__ARM_FEATURE_FMA"); \
131 \
88f77cba 132 if (TARGET_NEON) \
9e94a7fc
MGD		 133 { \
134 builtin_define ("__ARM_NEON__"); \
135 builtin_define ("__ARM_NEON"); \
136 } \
137 if (TARGET_NEON_FP) \
138 builtin_define_with_int_value ( \
139 "__ARM_NEON_FP", TARGET_NEON_FP); \
88f77cba 140 \
e6471be6
NB		 141 /* Add a define for interworking. \
142 Needed when building libgcc.a. */ \
2ad4dcf9 143 if (arm_cpp_interwork) \
e6471be6
NB		 144 builtin_define ("__THUMB_INTERWORK__"); \
145 \
146 builtin_assert ("cpu=arm"); \
147 builtin_assert ("machine=arm"); \
78011587
PB		 148 \
149 builtin_define (arm_arch_name); \
78011587
PB		 150 if (arm_arch_xscale) \
151 builtin_define ("__XSCALE__"); \
152 if (arm_arch_iwmmxt) \
9e94a7fc
MGD		 153 { \
154 builtin_define ("__IWMMXT__"); \
155 builtin_define ("__ARM_WMMX"); \
156 } \
8fd03515
XQ		 157 if (arm_arch_iwmmxt2) \
158 builtin_define ("__IWMMXT2__"); \
4adf3e34 159 if (TARGET_AAPCS_BASED) \
12ffc7d5
CLT		 160 { \
161 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
162 builtin_define ("__ARM_PCS_VFP"); \
163 else if (arm_pcs_default == ARM_PCS_AAPCS) \
164 builtin_define ("__ARM_PCS"); \
165 builtin_define ("__ARM_EABI__"); \
166 } \
572070ef
PB		 167 if (TARGET_IDIV) \
168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
e6471be6
NB		 169 } while (0)
170
ad7be009 171#include "config/arm/arm-opts.h"
9b66ebb1 172
78011587
PB		 173enum target_cpus
174{
c0e25e65
JG		 175#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
176 TARGET_CPU_##INTERNAL_IDENT,
78011587
PB		 177#include "arm-cores.def"
178#undef ARM_CORE
179 TARGET_CPU_generic
180};
181
9b66ebb1
PB		 182/* The processor for which instructions should be scheduled. */
183extern enum processor_type arm_tune;
184
d5b7b3ae 185typedef enum arm_cond_code
89c7ca52
RE		 186{
187 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
188 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 189}
190arm_cc;
6cfc7210 191
d5b7b3ae 192extern arm_cc arm_current_cc;
ff9940b0 193
d5b7b3ae 194#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 195
cd794ed4 196/* The maximum number of instructions that is beneficial to
b24a2ce5
GY		 197 conditionally execute. */
198#undef MAX_CONDITIONAL_EXECUTE
199#define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
200
6cfc7210
NC		 201extern int arm_target_label;
202extern int arm_ccfsm_state;
e2500fed 203extern GTY(()) rtx arm_target_insn;
d5b7b3ae 204/* The label of the current constant pool. */
e2500fed 205extern rtx pool_vector_label;
d5b7b3ae 206/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 207 is not needed. */
d5b7b3ae 208extern int return_used_this_function;
b76c3c4b
PB		 209/* Callback to output language specific object attributes. */
210extern void (*arm_lang_output_object_attributes_hook)(void);
35d965d5 211\f
d6b4baa4 212/* Just in case configure has failed to define anything. */
7a801826
RE		 213#ifndef TARGET_CPU_DEFAULT
214#define TARGET_CPU_DEFAULT TARGET_CPU_generic
215#endif
216
7a801826 217
5742588d 218#undef CPP_SPEC
78011587 219#define CPP_SPEC "%(subtarget_cpp_spec) \
5e1b4d5a
JM		 220%{mfloat-abi=soft:%{mfloat-abi=hard: \
221 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
e6471be6
NB		 222%{mbig-endian:%{mlittle-endian: \
223 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 224
be393ecf 225#ifndef CC1_SPEC
dfa08768 226#define CC1_SPEC ""
be393ecf 227#endif
7a801826
RE		 228
229/* This macro defines names of additional specifications to put in the specs
230 that can be used in various specifications like CC1_SPEC. Its definition
231 is an initializer with a subgrouping for each command option.
232
233 Each subgrouping contains a string constant, that defines the
4f448245 234 specification name, and a string constant that used by the GCC driver
7a801826
RE		 235 program.
236
237 Do not define this macro if it does not need to do anything. */
238#define EXTRA_SPECS \
38fc909b 239 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
54e73f88 240 { "asm_cpu_spec", ASM_CPU_SPEC }, \
7a801826
RE		 241 SUBTARGET_EXTRA_SPECS
242
914a3b8c 243#ifndef SUBTARGET_EXTRA_SPECS
7a801826 244#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 245#endif
246
6cfc7210 247#ifndef SUBTARGET_CPP_SPEC
38fc909b 248#define SUBTARGET_CPP_SPEC ""
6cfc7210 249#endif
35d965d5
RS		 250\f
251/* Run-time Target Specification. */
9b66ebb1 252#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 253/* Use hardware floating point instructions. */
254#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
255/* Use hardware floating point calling convention. */
256#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
d79f3032 257#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
5a9335ef 258#define TARGET_IWMMXT (arm_arch_iwmmxt)
8fd03515 259#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
5b3e6663 260#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
8fd03515 261#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
5b3e6663 262#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 263#define TARGET_ARM (! TARGET_THUMB)
264#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 265#define TARGET_BACKTRACE (leaf_function_p () \
266 ? TARGET_TPCS_LEAF_FRAME \
267 : TARGET_TPCS_FRAME)
b6685939
PB		 268#define TARGET_AAPCS_BASED \
269 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 270
d3585b76
DJ		 271#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
272#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
ccdc2164 273#define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
d3585b76 274
5b3e6663
PB		 275/* Only 16-bit thumb code. */
276#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
277/* Arm or Thumb-2 32-bit code. */
278#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
279/* 32-bit Thumb-2 code. */
280#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
bf98ec6c
PB		 281/* Thumb-1 only. */
282#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
5b3e6663 283
3383b7fa
GY		 284#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
285 && !TARGET_THUMB1)
286
582e2e43
KT		 287#define TARGET_CRC32 (arm_arch_crc)
288
88f77cba 289/* The following two macros concern the ability to execute coprocessor
302c3d8e
PB		 290 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
291 only ever tested when we know we are generating for VFP hardware; we need
292 to be more careful with TARGET_NEON as noted below. */
88f77cba 293
302c3d8e 294/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
d79f3032 295#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
302c3d8e
PB		 296
297/* FPU supports VFPv3 instructions. */
d79f3032 298#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
302c3d8e 299
e0dc3601
PB		 300/* FPU only supports VFP single-precision instructions. */
301#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
302
303/* FPU supports VFP double-precision instructions. */
304#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
305
306/* FPU supports half-precision floating-point with NEON element load/store. */
d79f3032
PB		 307#define TARGET_NEON_FP16 \
308 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
0fd8c3ad 309
e0dc3601
PB		 310/* FPU supports VFP half-precision floating-point. */
311#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
312
9e94a7fc
MGD		 313/* FPU supports fused-multiply-add operations. */
314#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
315
1dd4fe1f
KT		 316/* FPU is ARMv8 compatible. */
317#define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
318
595fefee
MGD		 319/* FPU supports Crypto extensions. */
320#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
321
88f77cba
JB		 322/* FPU supports Neon instructions. The setting of this macro gets
323 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
324 and TARGET_HARD_FLOAT to ensure that NEON instructions are
325 available. */
326#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
d79f3032 327 && TARGET_VFP && arm_fpu_desc->neon)
f1adb0a9 328
9e94a7fc
MGD		 329/* Q-bit is present. */
330#define TARGET_ARM_QBIT \
331 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
332/* Saturation operation, e.g. SSAT. */
333#define TARGET_ARM_SAT \
334 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
5b3e6663
PB		 335/* "DSP" multiply instructions, eg. SMULxy. */
336#define TARGET_DSP_MULTIPLY \
60bd3528 337 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
5b3e6663
PB		 338/* Integer SIMD instructions, and extend-accumulate instructions. */
339#define TARGET_INT_SIMD \
60bd3528 340 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
5b3e6663 341
571191af 342/* Should MOVW/MOVT be used in preference to a constant pool. */
7ec70105 343#define TARGET_USE_MOVT \
02231c13
TG		 344 (arm_arch_thumb2 \
345 && (arm_disable_literal_pool \
346 || (!optimize_size && !current_tune->prefer_constant_pool)))
571191af 347
5b3e6663
PB		 348/* We could use unified syntax for arm mode, but for now we just use it
349 for Thumb-2. */
350#define TARGET_UNIFIED_ASM TARGET_THUMB2
351
029e79eb 352/* Nonzero if this chip provides the DMB instruction. */
9e2a6301 353#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
029e79eb
MS		 354
355/* Nonzero if this chip implements a memory barrier via CP15. */
80651d8e
DAG		 356#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
357 && ! TARGET_THUMB1)
029e79eb
MS		 358
359/* Nonzero if this chip implements a memory barrier instruction. */
360#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
361
362/* Nonzero if this chip supports ldrex and strex */
363#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
364
cfe52743
DAG		 365/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
366#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
367
368/* Nonzero if this chip supports ldrexd and strexd. */
369#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
370 && arm_arch_notm)
5b3e6663 371
5ad29f12
KT		 372/* Nonzero if this chip supports load-acquire and store-release. */
373#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
374
572070ef
PB		 375/* Nonzero if integer division instructions supported. */
376#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
377 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
378
65074f54
CL		 379/* Should NEON be used for 64-bits bitops. */
380#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits)
381
b3f8d95d
MM		 382/* True iff the full BPABI is being used. If TARGET_BPABI is true,
383 then TARGET_AAPCS_BASED must be true -- but the converse does not
384 hold. TARGET_BPABI implies the use of the BPABI runtime library,
385 etc., in addition to just the AAPCS calling conventions. */
386#ifndef TARGET_BPABI
387#define TARGET_BPABI false
f676971a 388#endif
b3f8d95d 389
7816bea0
DJ		 390/* Support for a compile-time default CPU, et cetera. The rules are:
391 --with-arch is ignored if -march or -mcpu are specified.
392 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
393 by --with-arch.
394 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
395 by -march).
5e1b4d5a 396 --with-float is ignored if -mfloat-abi is specified.
5848830f 397 --with-fpu is ignored if -mfpu is specified.
ccdc2164
NS		 398 --with-abi is ignored if -mabi is specified.
399 --with-tls is ignored if -mtls-dialect is specified. */
7816bea0
DJ		 400#define OPTION_DEFAULT_SPECS \
401 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
402 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
403 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
5e1b4d5a 404 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
5848830f 405 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
3cf94279 406 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
ccdc2164 407 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
7cf13d1f 408 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
7816bea0 409
9b66ebb1
PB		 410/* Which floating point model to use. */
411enum arm_fp_model
412{
413 ARM_FP_MODEL_UNKNOWN,
9b66ebb1
PB		 414 /* VFP floating point model. */
415 ARM_FP_MODEL_VFP
416};
417
d79f3032 418enum vfp_reg_type
24f0c1b4 419{
70dd156a 420 VFP_NONE = 0,
d79f3032
PB		 421 VFP_REG_D16,
422 VFP_REG_D32,
423 VFP_REG_SINGLE
24f0c1b4
RE		 424};
425
d79f3032
PB		 426extern const struct arm_fpu_desc
427{
428 const char *name;
429 enum arm_fp_model model;
430 int rev;
431 enum vfp_reg_type regs;
432 int neon;
433 int fp16;
595fefee 434 int crypto;
d79f3032
PB		 435} *arm_fpu_desc;
436
437/* Which floating point hardware to schedule for. */
438extern int arm_fpu_attr;
71791e16 439
3d8532aa
PB		 440#ifndef TARGET_DEFAULT_FLOAT_ABI
441#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
442#endif
443
0fd8c3ad
SL		 444#define LARGEST_EXPONENT_IS_NORMAL(bits) \
445 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
446
5848830f
PB		 447#ifndef ARM_DEFAULT_ABI
448#define ARM_DEFAULT_ABI ARM_ABI_APCS
449#endif
450
9e94a7fc
MGD		 451/* Map each of the micro-architecture variants to their corresponding
452 major architecture revision. */
453
454enum base_architecture
455{
456 BASE_ARCH_0 = 0,
457 BASE_ARCH_2 = 2,
458 BASE_ARCH_3 = 3,
459 BASE_ARCH_3M = 3,
460 BASE_ARCH_4 = 4,
461 BASE_ARCH_4T = 4,
462 BASE_ARCH_5 = 5,
463 BASE_ARCH_5E = 5,
464 BASE_ARCH_5T = 5,
465 BASE_ARCH_5TE = 5,
466 BASE_ARCH_5TEJ = 5,
467 BASE_ARCH_6 = 6,
468 BASE_ARCH_6J = 6,
469 BASE_ARCH_6ZK = 6,
470 BASE_ARCH_6K = 6,
471 BASE_ARCH_6T2 = 6,
472 BASE_ARCH_6M = 6,
473 BASE_ARCH_6Z = 6,
474 BASE_ARCH_7 = 7,
475 BASE_ARCH_7A = 7,
476 BASE_ARCH_7R = 7,
477 BASE_ARCH_7M = 7,
595fefee
MGD		 478 BASE_ARCH_7EM = 7,
479 BASE_ARCH_8A = 8
9e94a7fc
MGD		 480};
481
482/* The major revision number of the ARM Architecture implemented by the target. */
483extern enum base_architecture arm_base_arch;
484
9b66ebb1
PB		 485/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
486extern int arm_arch3m;
11c1a207 487
9b66ebb1 488/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 489extern int arm_arch4;
490
68d560d4
RE		 491/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
492extern int arm_arch4t;
493
9b66ebb1 494/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 495extern int arm_arch5;
496
9b66ebb1 497/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 498extern int arm_arch5e;
499
9b66ebb1
PB		 500/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
501extern int arm_arch6;
502
029e79eb
MS		 503/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
504extern int arm_arch6k;
505
9e2a6301
TG		 506/* Nonzero if instructions present in ARMv6-M can be used. */
507extern int arm_arch6m;
508
029e79eb
MS		 509/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
510extern int arm_arch7;
511
5b3e6663
PB		 512/* Nonzero if instructions not present in the 'M' profile can be used. */
513extern int arm_arch_notm;
514
60bd3528
PB		 515/* Nonzero if instructions present in ARMv7E-M can be used. */
516extern int arm_arch7em;
517
595fefee
MGD		 518/* Nonzero if this chip supports the ARM Architecture 8 extensions. */
519extern int arm_arch8;
520
f5a1b0d2
NC		 521/* Nonzero if this chip can benefit from load scheduling. */
522extern int arm_ld_sched;
523
906668bb 524/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
0616531f
RE		 525extern int thumb_code;
526
906668bb
BS		 527/* Nonzero if generating Thumb-1 code. */
528extern int thumb1_code;
529
f5a1b0d2 530/* Nonzero if this chip is a StrongARM. */
abac3b49 531extern int arm_tune_strongarm;
f5a1b0d2 532
5a9335ef
NC		 533/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534extern int arm_arch_iwmmxt;
535
8fd03515
XQ		 536/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
537extern int arm_arch_iwmmxt2;
538
d19fb8e3 539/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 540extern int arm_arch_xscale;
541
abac3b49 542/* Nonzero if tuning for XScale. */
4b3c2e48 543extern int arm_tune_xscale;
d19fb8e3 544
abac3b49
RE		 545/* Nonzero if tuning for stores via the write buffer. */
546extern int arm_tune_wbuf;
f5a1b0d2 547
7612f14d
PB		 548/* Nonzero if tuning for Cortex-A9. */
549extern int arm_tune_cortex_a9;
550
2ad4dcf9 551/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 552 preprocessor.
2ad4dcf9
RE		 553 XXX This is a bit of a hack, it's intended to help work around
554 problems in GLD which doesn't understand that armv5t code is
555 interworking clean. */
556extern int arm_cpp_interwork;
557
5b3e6663
PB		 558/* Nonzero if chip supports Thumb 2. */
559extern int arm_arch_thumb2;
560
572070ef
PB		 561/* Nonzero if chip supports integer division instruction in ARM mode. */
562extern int arm_arch_arm_hwdiv;
563
564/* Nonzero if chip supports integer division instruction in Thumb mode. */
565extern int arm_arch_thumb_hwdiv;
5b3e6663 566
65074f54
CL		 567/* Nonzero if we should use Neon to handle 64-bits operations rather
568 than core registers. */
569extern int prefer_neon_for_64bits;
570
02231c13
TG		 571/* Nonzero if we shouldn't use literal pools. */
572#ifndef USED_FOR_TARGET
573extern bool arm_disable_literal_pool;
574#endif
575
582e2e43
KT		 576/* Nonzero if chip supports the ARMv8 CRC instructions. */
577extern int arm_arch_crc;
578
2ce9c1b9 579#ifndef TARGET_DEFAULT
c54c7322 580#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 581#endif
35d965d5 582
86efdc8e
PB		 583/* Nonzero if PIC code requires explicit qualifiers to generate
584 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 585 Subtargets can override these if required. */
586#ifndef NEED_GOT_RELOC
587#define NEED_GOT_RELOC 0
588#endif
589#ifndef NEED_PLT_RELOC
590#define NEED_PLT_RELOC 0
e2723c62 591#endif
84306176 592
32d6e6c0
JY		 593#ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
594#define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
595#endif
596
84306176
PB		 597/* Nonzero if we need to refer to the GOT with a PC-relative
598 offset. In other words, generate
599
f676971a 600 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 601
602 rather than
603
604 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
605
f676971a 606 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 607 override this if required. */
608#ifndef GOT_PCREL
609#define GOT_PCREL 1
610#endif
35d965d5
RS		 611\f
612/* Target machine storage Layout. */
613
ff9940b0
RE		 614
615/* Define this macro if it is advisable to hold scalars in registers
616 in a wider mode than that declared by the program. In such cases,
617 the value is constrained to be within the bounds of the declared
618 type, but kept valid in the wider mode. The signedness of the
619 extension may differ from that of the type. */
620
621/* It is far faster to zero extend chars than to sign extend them */
622
6cfc7210 623#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 624 if (GET_MODE_CLASS (MODE) == MODE_INT \
625 && GET_MODE_SIZE (MODE) < 4) \
626 { \
627 if (MODE == QImode) \
628 UNSIGNEDP = 1; \
629 else if (MODE == HImode) \
61f0ccff 630 UNSIGNEDP = 1; \
2ce9c1b9 631 (MODE) = SImode; \
ff9940b0
RE		 632 }
633
35d965d5
RS		 634/* Define this if most significant bit is lowest numbered
635 in instructions that operate on numbered bit-fields. */
636#define BITS_BIG_ENDIAN 0
637
f676971a 638/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 639 Most ARM processors are run in little endian mode, so that is the default.
640 If you want to have it run-time selectable, change the definition in a
641 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 642#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 643
644/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 645 numbered.
646 This is always false, even when in big-endian mode. */
ddee6aba
RE		 647#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
648
35d965d5
RS		 649#define UNITS_PER_WORD 4
650
5848830f 651/* True if natural alignment is used for doubleword types. */
b6685939
PB		 652#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
653
5848830f 654#define DOUBLEWORD_ALIGNMENT 64
35d965d5 655
5848830f 656#define PARM_BOUNDARY 32
5a9335ef 657
5848830f 658#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 659
5848830f
PB		 660#define PREFERRED_STACK_BOUNDARY \
661 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 662
f711a87a 663#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
35d965d5 664
92928d71
AO		 665/* The lowest bit is used to indicate Thumb-mode functions, so the
666 vbit must go into the delta field of pointers to member
667 functions. */
668#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
669
35d965d5
RS		 670#define EMPTY_FIELD_BOUNDARY 32
671
5848830f 672#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 673
f276d31d
BE		 674#define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
675
27847754
NC		 676/* XXX Blah -- this macro is used directly by libobjc. Since it
677 supports no vector modes, cut out the complexity and fall back
678 on BIGGEST_FIELD_ALIGNMENT. */
679#ifdef IN_TARGET_LIBS
8fca31a2 680#define BIGGEST_FIELD_ALIGNMENT 64
27847754 681#endif
5a9335ef 682
ff9940b0 683/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 684#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 685
d19fb8e3 686#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f 687 ((TREE_CODE (EXP) == STRING_CST \
36b15ad0 688 && !optimize_size \
5848830f
PB		 689 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
690 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 691
96339268
RE		 692/* Align definitions of arrays, unions and structures so that
693 initializations and copies can be made more efficient. This is not
694 ABI-changing, so it only affects places where we can see the
0c86e0dd
CLT		 695 definition. Increasing the alignment tends to introduce padding,
696 so don't do this when optimizing for size/conserving stack space. */
697#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
698 (((COND) && ((ALIGN) < BITS_PER_WORD) \
96339268
RE		 699 && (TREE_CODE (EXP) == ARRAY_TYPE \
700 || TREE_CODE (EXP) == UNION_TYPE \
701 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
702
0c86e0dd
CLT		 703/* Align global data. */
704#define DATA_ALIGNMENT(EXP, ALIGN) \
705 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
706
96339268 707/* Similarly, make sure that objects on the stack are sensibly aligned. */
0c86e0dd
CLT		 708#define LOCAL_ALIGNMENT(EXP, ALIGN) \
709 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
96339268 710
723ae7c1
NC		 711/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
712 value set in previous versions of this toolchain was 8, which produces more
713 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 714 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 715 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 716 0020D) page 2-20 says "Structures are aligned on word boundaries".
717 The AAPCS specifies a value of 8. */
6ead9ba5 718#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
723ae7c1 719
4912a07c 720/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 721 particular arm target wants to change the default value it should change
6bc82793 722 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 723 for an example of this. */
724#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
725#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 726#endif
2a5307b1 727
825dda42 728/* Nonzero if move instructions will actually fail to work
ff9940b0 729 when given unaligned data. */
35d965d5 730#define STRICT_ALIGNMENT 1
b6685939
PB		 731
732/* wchar_t is unsigned under the AAPCS. */
733#ifndef WCHAR_TYPE
734#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
735
736#define WCHAR_TYPE_SIZE BITS_PER_WORD
737#endif
738
655b30bf
JB		 739/* Sized for fixed-point types. */
740
741#define SHORT_FRACT_TYPE_SIZE 8
742#define FRACT_TYPE_SIZE 16
743#define LONG_FRACT_TYPE_SIZE 32
744#define LONG_LONG_FRACT_TYPE_SIZE 64
745
746#define SHORT_ACCUM_TYPE_SIZE 16
747#define ACCUM_TYPE_SIZE 32
748#define LONG_ACCUM_TYPE_SIZE 64
749#define LONG_LONG_ACCUM_TYPE_SIZE 64
750
751#define MAX_FIXED_MODE_SIZE 64
752
b6685939
PB		 753#ifndef SIZE_TYPE
754#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
755#endif
d81d0bdd 756
077fc835
KH		 757#ifndef PTRDIFF_TYPE
758#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
759#endif
760
d81d0bdd
PB		 761/* AAPCS requires that structure alignment is affected by bitfields. */
762#ifndef PCC_BITFIELD_TYPE_MATTERS
763#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
764#endif
765
35d965d5
RS		 766\f
767/* Standard register usage. */
768
0be8bd1a 769/* Register allocation in ARM Procedure Call Standard
35d965d5
RS		 770 (S - saved over call).
771
772 r0 * argument word/integer result
773 r1-r3 argument word
774
775 r4-r8 S register variable
776 r9 S (rfp) register variable (real frame pointer)
f676971a 777
f5a1b0d2 778 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 779 r11 F S (fp) argument pointer
780 r12 (ip) temp workspace
781 r13 F S (sp) lower end of current stack frame
782 r14 (lr) link address/workspace
783 r15 F (pc) program counter
784
ff9940b0
RE		 785 cc This is NOT a real register, but is used internally
786 to represent things that use or set the condition
787 codes.
788 sfp This isn't either. It is used during rtl generation
789 since the offset between the frame pointer and the
790 auto's isn't known until after register allocation.
791 afp Nor this, we only need this because of non-local
792 goto. Without it fp appears to be used and the
793 elimination code won't get rid of sfp. It tracks
794 fp exactly at all times.
795
5efd84c5 796 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
35d965d5 797
9b66ebb1
PB		 798/* s0-s15 VFP scratch (aka d0-d7).
799 s16-s31 S VFP variable (aka d8-d15).
800 vfpcc Not a real register. Represents the VFP condition
801 code flags. */
802
ff9940b0
RE		 803/* The stack backtrace structure is as follows:
804 fp points to here: | save code pointer | [fp]
805 | return link value | [fp, #-4]
806 | return sp value | [fp, #-8]
807 | return fp value | [fp, #-12]
808 [| saved r10 value |]
809 [| saved r9 value |]
810 [| saved r8 value |]
811 [| saved r7 value |]
812 [| saved r6 value |]
813 [| saved r5 value |]
814 [| saved r4 value |]
815 [| saved r3 value |]
816 [| saved r2 value |]
817 [| saved r1 value |]
818 [| saved r0 value |]
ff9940b0
RE		 819 r0-r3 are not normally saved in a C function. */
820
35d965d5
RS		 821/* 1 for registers that have pervasive standard uses
822 and are not available for the register allocator. */
0be8bd1a
RE		 823#define FIXED_REGISTERS \
824{ \
825 /* Core regs. */ \
826 0,0,0,0,0,0,0,0, \
827 0,0,0,0,0,1,0,1, \
828 /* VFP regs. */ \
829 1,1,1,1,1,1,1,1, \
830 1,1,1,1,1,1,1,1, \
831 1,1,1,1,1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1,1,1,1,1,1,1,1, \
836 1,1,1,1,1,1,1,1, \
837 /* IWMMXT regs. */ \
838 1,1,1,1,1,1,1,1, \
839 1,1,1,1,1,1,1,1, \
840 1,1,1,1, \
841 /* Specials. */ \
842 1,1,1,1 \
35d965d5
RS		 843}
844
845/* 1 for registers not available across function calls.
846 These must include the FIXED_REGISTERS and also any
847 registers that can be used without being saved.
848 The latter must include the registers where values are returned
849 and the register where structure-value addresses are passed.
ff9940b0 850 Aside from that, you can include as many other registers as you like.
f676971a 851 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 852 easier to assume this for all. SFP is preserved, since FP is. */
0be8bd1a
RE		 853#define CALL_USED_REGISTERS \
854{ \
855 /* Core regs. */ \
856 1,1,1,1,0,0,0,0, \
857 0,0,0,0,1,1,1,1, \
858 /* VFP Regs. */ \
859 1,1,1,1,1,1,1,1, \
860 1,1,1,1,1,1,1,1, \
861 1,1,1,1,1,1,1,1, \
862 1,1,1,1,1,1,1,1, \
863 1,1,1,1,1,1,1,1, \
864 1,1,1,1,1,1,1,1, \
865 1,1,1,1,1,1,1,1, \
866 1,1,1,1,1,1,1,1, \
867 /* IWMMXT regs. */ \
868 1,1,1,1,1,1,1,1, \
869 1,1,1,1,1,1,1,1, \
870 1,1,1,1, \
871 /* Specials. */ \
872 1,1,1,1 \
35d965d5
RS		 873}
874
6cc8c0b3
NC		 875#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
876#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
877#endif
878
6bc82793 879/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 880 by asm_fprintf:
881 %@ prints out ASM_COMMENT_START
882 %r prints out REGISTER_PREFIX reg_names[arg] */
883#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
884 case '@': \
885 fputs (ASM_COMMENT_START, FILE); \
886 break; \
887 \
888 case 'r': \
889 fputs (REGISTER_PREFIX, FILE); \
890 fputs (reg_names [va_arg (ARGS, int)], FILE); \
891 break;
892
d5b7b3ae 893/* Round X up to the nearest word. */
0c2ca901 894#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 895
6cfc7210 896/* Convert fron bytes to ints. */
e9d7b180 897#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 898
9b66ebb1
PB		 899/* The number of (integer) registers required to hold a quantity of type MODE.
900 Also used for VFP registers. */
e9d7b180
JD		 901#define ARM_NUM_REGS(MODE) \
902 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 903
904/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 905#define ARM_NUM_REGS2(MODE, TYPE) \
906 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 907 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 908
909/* The number of (integer) argument register available. */
d5b7b3ae 910#define NUM_ARG_REGS 4
6cfc7210 911
390b17c2
RE		 912/* And similarly for the VFP. */
913#define NUM_VFP_ARG_REGS 16
914
093354e0 915/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 916#define ARG_REGISTER(N) (N - 1)
6cfc7210 917
d5b7b3ae
RE		 918/* Specify the registers used for certain standard purposes.
919 The values of these macros are register numbers. */
35d965d5 920
d5b7b3ae
RE		 921/* The number of the last argument register. */
922#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 923
c769a35d
RE		 924/* The numbers of the Thumb register ranges. */
925#define FIRST_LO_REGNUM 0
6d3d9133 926#define LAST_LO_REGNUM 7
c769a35d
RE		 927#define FIRST_HI_REGNUM 8
928#define LAST_HI_REGNUM 11
6d3d9133 929
f0a0390e
RH		 930/* Overridden by config/arm/bpabi.h. */
931#ifndef ARM_UNWIND_INFO
932#define ARM_UNWIND_INFO 0
617a1b71
PB		 933#endif
934
c9ca9b88
PB		 935/* Use r0 and r1 to pass exception handling information. */
936#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
937
6d3d9133 938/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 939#define ARM_EH_STACKADJ_REGNUM 2
940#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 941
1e874273
PB		 942#ifndef ARM_TARGET2_DWARF_FORMAT
943#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
3f2f838e 944#endif
1e874273
PB		 945
946/* ttype entries (the only interesting data references used)
947 use TARGET2 relocations. */
948#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
949 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
950 : DW_EH_PE_absptr)
1e874273 951
d5b7b3ae
RE		 952/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
953 as an invisible last argument (possible since varargs don't exist in
954 Pascal), so the following is not true. */
5b3e6663 955#define STATIC_CHAIN_REGNUM 12
35d965d5 956
d5b7b3ae
RE		 957/* Define this to be where the real frame pointer is if it is not possible to
958 work out the offset between the frame pointer and the automatic variables
959 until after register allocation has taken place. FRAME_POINTER_REGNUM
960 should point to a special register that we will make sure is eliminated.
961
962 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 963 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 964 as base register for addressing purposes. (See comments in
965 find_reloads_address()). But - the Thumb does not allow high registers,
966 including r11, to be used as base address registers. Hence our problem.
967
968 The solution used here, and in the old thumb port is to use r7 instead of
969 r11 as the hard frame pointer and to have special code to generate
970 backtrace structures on the stack (if required to do so via a command line
6bc82793 971 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 972 pointer. */
973#define ARM_HARD_FRAME_POINTER_REGNUM 11
974#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 975
b15bca31
RE		 976#define HARD_FRAME_POINTER_REGNUM \
977 (TARGET_ARM \
978 ? ARM_HARD_FRAME_POINTER_REGNUM \
979 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 980
e3339d0f
JM		 981#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
982#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
983
b15bca31 984#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 985
b15bca31
RE		 986/* Register to use for pushing function arguments. */
987#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae 988
0be8bd1a
RE		 989#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
990#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
a76213b9
XQ		 991
992/* Need to sync with WCGR in iwmmxt.md. */
0be8bd1a
RE		 993#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
994#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
d5b7b3ae 995
5a9335ef
NC		 996#define IS_IWMMXT_REGNUM(REGNUM) \
997 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
998#define IS_IWMMXT_GR_REGNUM(REGNUM) \
999 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1000
35d965d5 1001/* Base register for access to local variables of the function. */
0be8bd1a 1002#define FRAME_POINTER_REGNUM 102
ff9940b0 1003
d5b7b3ae 1004/* Base register for access to arguments of the function. */
0be8bd1a 1005#define ARG_POINTER_REGNUM 103
62b10bbc 1006
0be8bd1a
RE		 1007#define FIRST_VFP_REGNUM 16
1008#define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
f1adb0a9 1009#define LAST_VFP_REGNUM \
302c3d8e 1010 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
f1adb0a9 1011
9b66ebb1
PB		 1012#define IS_VFP_REGNUM(REGNUM) \
1013 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1014
f1adb0a9
JB		 1015/* VFP registers are split into two types: those defined by VFP versions < 3
1016 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1017 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1018 in various parts of the backend, we implement as "fake" single-precision
1019 registers (which would be S32-S63, but cannot be used in that way). The
1020 following macros define these ranges of registers. */
0be8bd1a
RE		 1021#define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
1022#define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
1023#define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
f1adb0a9
JB		 1024
1025#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1026 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1027
1028/* DFmode values are only valid in even register pairs. */
1029#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1030 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1031
88f77cba
JB		 1032/* Neon Quad values must start at a multiple of four registers. */
1033#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1034 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1035
1036/* Neon structures of vectors must be in even register pairs and there
1037 must be enough registers available. Because of various patterns
1038 requiring quad registers, we require them to start at a multiple of
1039 four. */
1040#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1041 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1042 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1043
0be8bd1a 1044/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
5a9335ef 1045/* Intel Wireless MMX Technology registers add 16 + 4 more. */
0be8bd1a
RE		 1046/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1047#define FIRST_PSEUDO_REGISTER 104
62b10bbc 1048
2fa330b2
PB		 1049#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1050
35d965d5
RS		 1051/* Value should be nonzero if functions must have frame pointers.
1052 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 1053 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 1054 If we have to have a frame pointer we might as well make use of it.
1055 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 1056 functions, or simple tail call functions. */
a15900b5
DJ		 1057
1058#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1059#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1060#endif
1061
d5b7b3ae
RE		 1062/* Return number of consecutive hard regs needed starting at reg REGNO
1063 to hold something of mode MODE.
1064 This is ordinarily the length in words of a value of mode MODE
1065 but can be less for certain modes in special long registers.
35d965d5 1066
0be8bd1a 1067 On the ARM core regs are UNITS_PER_WORD bits wide. */
d5b7b3ae 1068#define HARD_REGNO_NREGS(REGNO, MODE) \
5b3e6663 1069 ((TARGET_32BIT \
0be8bd1a 1070 && REGNO > PC_REGNUM \
d5b7b3ae
RE		 1071 && REGNO != FRAME_POINTER_REGNUM \
1072 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1073 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1074 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1075
4b02997f 1076/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1077#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1078 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1079
2af8e257 1080#define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
ff9940b0 1081
5a9335ef 1082#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1083 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1084
88f77cba
JB		 1085/* Modes valid for Neon D registers. */
1086#define VALID_NEON_DREG_MODE(MODE) \
1087 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
5819f96f 1088 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode)
88f77cba
JB		 1089
1090/* Modes valid for Neon Q registers. */
1091#define VALID_NEON_QREG_MODE(MODE) \
1092 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1093 || (MODE) == V4SFmode || (MODE) == V2DImode)
1094
1095/* Structure modes valid for Neon registers. */
1096#define VALID_NEON_STRUCT_MODE(MODE) \
1097 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1098 || (MODE) == CImode || (MODE) == XImode)
1099
37119410
BS		 1100/* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1101extern int arm_regs_in_sequence[];
1102
35d965d5 1103/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1104 since no saving is required (though calls clobber it) and it never contains
1105 function parameters. It is quite good to use lr since other calls may
f676971a 1106 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1107 least likely to contain a function parameter; in addition results are
f1adb0a9
JB		 1108 returned in r0.
1109 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1110 then D8-D15. The reason for doing this is to attempt to reduce register
1111 pressure when both single- and double-precision registers are used in a
1112 function. */
1113
0be8bd1a
RE		 1114#define VREG(X) (FIRST_VFP_REGNUM + (X))
1115#define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1116#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1117
f1adb0a9
JB		 1118#define REG_ALLOC_ORDER \
1119{ \
0be8bd1a
RE		 1120 /* General registers. */ \
1121 3, 2, 1, 0, 12, 14, 4, 5, \
1122 6, 7, 8, 9, 10, 11, \
1123 /* High VFP registers. */ \
1124 VREG(32), VREG(33), VREG(34), VREG(35), \
1125 VREG(36), VREG(37), VREG(38), VREG(39), \
1126 VREG(40), VREG(41), VREG(42), VREG(43), \
1127 VREG(44), VREG(45), VREG(46), VREG(47), \
1128 VREG(48), VREG(49), VREG(50), VREG(51), \
1129 VREG(52), VREG(53), VREG(54), VREG(55), \
1130 VREG(56), VREG(57), VREG(58), VREG(59), \
1131 VREG(60), VREG(61), VREG(62), VREG(63), \
1132 /* VFP argument registers. */ \
1133 VREG(15), VREG(14), VREG(13), VREG(12), \
1134 VREG(11), VREG(10), VREG(9), VREG(8), \
1135 VREG(7), VREG(6), VREG(5), VREG(4), \
1136 VREG(3), VREG(2), VREG(1), VREG(0), \
1137 /* VFP call-saved registers. */ \
1138 VREG(16), VREG(17), VREG(18), VREG(19), \
1139 VREG(20), VREG(21), VREG(22), VREG(23), \
1140 VREG(24), VREG(25), VREG(26), VREG(27), \
1141 VREG(28), VREG(29), VREG(30), VREG(31), \
1142 /* IWMMX registers. */ \
1143 WREG(0), WREG(1), WREG(2), WREG(3), \
1144 WREG(4), WREG(5), WREG(6), WREG(7), \
1145 WREG(8), WREG(9), WREG(10), WREG(11), \
1146 WREG(12), WREG(13), WREG(14), WREG(15), \
1147 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1148 /* Registers not for general use. */ \
1149 CC_REGNUM, VFPCC_REGNUM, \
1150 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1151 SP_REGNUM, PC_REGNUM \
35d965d5 1152}
9338ffe6 1153
795dc4fc 1154/* Use different register alloc ordering for Thumb. */
5a733826
BS		 1155#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1156
1157/* Tell IRA to use the order we define rather than messing it up with its
1158 own cost calculations. */
ed15c598 1159#define HONOR_REG_ALLOC_ORDER 1
795dc4fc 1160
9338ffe6
PB		 1161/* Interrupt functions can only use registers that have already been
1162 saved by the prologue, even if they would normally be
1163 call-clobbered. */
1164#define HARD_REGNO_RENAME_OK(SRC, DST) \
1165 (! IS_INTERRUPT (cfun->machine->func_type) || \
6fb5fa3c 1166 df_regs_ever_live_p (DST))
35d965d5
RS		 1167\f
1168/* Register and constant classes. */
1169
0be8bd1a 1170/* Register classes. */
35d965d5
RS		 1171enum reg_class
1172{
1173 NO_REGS,
0be8bd1a
RE		 1174 LO_REGS,
1175 STACK_REG,
1176 BASE_REGS,
1177 HI_REGS,
9adcfa3c 1178 CALLER_SAVE_REGS,
0be8bd1a
RE		 1179 GENERAL_REGS,
1180 CORE_REGS,
f1adb0a9
JB		 1181 VFP_D0_D7_REGS,
1182 VFP_LO_REGS,
1183 VFP_HI_REGS,
9b66ebb1 1184 VFP_REGS,
5a9335ef 1185 IWMMXT_REGS,
0be8bd1a 1186 IWMMXT_GR_REGS,
d5b7b3ae 1187 CC_REG,
9b66ebb1 1188 VFPCC_REG,
0be8bd1a
RE		 1189 SFP_REG,
1190 AFP_REG,
35d965d5
RS		 1191 ALL_REGS,
1192 LIM_REG_CLASSES
1193};
1194
1195#define N_REG_CLASSES (int) LIM_REG_CLASSES
1196
d6b4baa4 1197/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1198#define REG_CLASS_NAMES \
1199{ \
1200 "NO_REGS", \
0be8bd1a
RE		 1201 "LO_REGS", \
1202 "STACK_REG", \
1203 "BASE_REGS", \
1204 "HI_REGS", \
9adcfa3c 1205 "CALLER_SAVE_REGS", \
0be8bd1a
RE		 1206 "GENERAL_REGS", \
1207 "CORE_REGS", \
f1adb0a9
JB		 1208 "VFP_D0_D7_REGS", \
1209 "VFP_LO_REGS", \
1210 "VFP_HI_REGS", \
9b66ebb1 1211 "VFP_REGS", \
5a9335ef 1212 "IWMMXT_REGS", \
0be8bd1a 1213 "IWMMXT_GR_REGS", \
d5b7b3ae 1214 "CC_REG", \
5384443a 1215 "VFPCC_REG", \
9f4f1735
JJ		 1216 "SFP_REG", \
1217 "AFP_REG", \
1218 "ALL_REGS" \
35d965d5
RS		 1219}
1220
1221/* Define which registers fit in which classes.
1222 This is an initializer for a vector of HARD_REG_SET
1223 of length N_REG_CLASSES. */
f1adb0a9
JB		 1224#define REG_CLASS_CONTENTS \
1225{ \
1226 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
f1adb0a9
JB		 1227 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1228 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1229 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
0be8bd1a 1230 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
9adcfa3c 1231 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
0be8bd1a
RE		 1232 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1233 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1234 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1235 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1236 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1237 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1238 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1239 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1240 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1241 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1242 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1243 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
d8484d41 1244 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \
35d965d5 1245}
4b02997f 1246
f1adb0a9
JB		 1247/* Any of the VFP register classes. */
1248#define IS_VFP_CLASS(X) \
1249 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1250 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1251
35d965d5
RS		 1252/* The same information, inverted:
1253 Return the class number of the smallest class containing
1254 reg number REGNO. This could be a conditional expression
1255 or could index an array. */
d5b7b3ae 1256#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1257
0be8bd1a
RE		 1258/* In VFPv1, VFP registers could only be accessed in the mode they
1259 were set, so subregs would be invalid there. However, we don't
1260 support VFPv1 at the moment, and the restriction was lifted in
e81bf2ce
JB		 1261 VFPv2.
1262 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1263 VFP registers in little-endian order. We can't describe that accurately to
db57bbc9
KT		 1264 GCC, so avoid taking subregs of such values.
1265 The only exception is going from a 128-bit to a 64-bit type. In that case
1266 the data layout happens to be consistent for big-endian, so we explicitly allow
1267 that case. */
1268#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1269 (TARGET_VFP && TARGET_BIG_END \
1270 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
1271 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1272 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
e81bf2ce 1273 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
75d2580c 1274
35d965d5 1275/* The class value for index registers, and the one for base regs. */
5b3e6663 1276#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
f5c630c3 1277#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
d5b7b3ae 1278
b93a0fe6 1279/* For the Thumb the high registers cannot be used as base registers
6bc82793 1280 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1281 mode, then we must be conservative. */
3dcc68a4 1282#define MODE_BASE_REG_CLASS(MODE) \
2ae577fd
VM		 1283 (arm_lra_flag \
1284 ? (TARGET_32BIT ? CORE_REGS \
1285 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \
1286 : LO_REGS) \
1287 : ((TARGET_ARM || (TARGET_THUMB2 && !optimize_size)) ? CORE_REGS \
1288 : ((MODE) == SImode) ? BASE_REGS \
1289 : LO_REGS))
888d2cd6
DJ		 1290
1291/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1292 instead of BASE_REGS. */
1293#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1294
42db504c 1295/* When this hook returns true for MODE, the compiler allows
d5b7b3ae
RE		 1296 registers explicitly used in the rtl to be used as spill registers
1297 but prevents the compiler from extending the lifetime of these
d6b4baa4 1298 registers. */
42db504c
SB		 1299#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1300 arm_small_register_classes_for_mode_p
35d965d5 1301
d5b7b3ae
RE		 1302/* Must leave BASE_REGS reloads alone */
1303#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
78a14aa8
YR		 1304 (lra_in_progress ? NO_REGS \
1305 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1306 ? ((true_regnum (X) == -1 ? LO_REGS \
1307 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1308 : NO_REGS)) \
1309 : NO_REGS))
d5b7b3ae
RE		 1310
1311#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1fc017b6
VM		 1312 (lra_in_progress ? NO_REGS \
1313 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1314 ? ((true_regnum (X) == -1 ? LO_REGS \
1315 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1316 : NO_REGS)) \
1317 : NO_REGS)
35d965d5 1318
ff9940b0
RE		 1319/* Return the register class of a scratch register needed to copy IN into
1320 or out of a register in CLASS in MODE. If it can be done directly,
1321 NO_REGS is returned. */
d5b7b3ae 1322#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1323 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1324 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1325 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1326 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1327 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1328 ? coproc_secondary_reload_class (MODE, X, TRUE) \
5b3e6663 1329 : TARGET_32BIT \
9b66ebb1 1330 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1331 ? GENERAL_REGS : NO_REGS) \
1332 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1333
d6b4baa4 1334/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1335#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1336 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1337 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1338 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1339 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1340 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1341 coproc_secondary_reload_class (MODE, X, TRUE) : \
0be8bd1a
RE		 1342 (TARGET_32BIT ? \
1343 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1344 && CONSTANT_P (X)) \
9b6b54e2 1345 ? GENERAL_REGS : \
0be8bd1a 1346 (((MODE) == HImode && ! arm_arch4 \
d435a4be
KT		 1347 && (MEM_P (X) \
1348 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
0be8bd1a
RE		 1349 && true_regnum (X) == -1))) \
1350 ? GENERAL_REGS : NO_REGS) \
1351 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1352
6f734908
RE		 1353/* Try a machine-dependent way of reloading an illegitimate address
1354 operand. If we find one, push the reload and jump to WIN. This
1355 macro is used in only one place: `find_reloads_address' in reload.c.
1356
1357 For the ARM, we wish to handle large displacements off a base
1358 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1359 This can cut the number of reloads needed. */
1360#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1361 do \
1362 { \
0cd98787
JZ		 1363 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1364 goto WIN; \
d5b7b3ae 1365 } \
62b10bbc 1366 while (0)
6f734908 1367
27847754 1368/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1369 SP+large_offset address, then reload won't know how to fix it. It sees
1370 only that SP isn't valid for HImode, and so reloads the SP into an index
1371 register, but the resulting address is still invalid because the offset
1372 is too big. We fix it here instead by reloading the entire address. */
1373/* We could probably achieve better results by defining PROMOTE_MODE to help
1374 cope with the variances between the Thumb's signed and unsigned byte and
1375 halfword load instructions. */
5b3e6663 1376/* ??? This should be safe for thumb2, but we may be able to do better. */
a132dad6
RE		 1377#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1378do { \
1379 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1380 if (new_x) \
1381 { \
1382 X = new_x; \
1383 goto WIN; \
1384 } \
1385} while (0)
d5b7b3ae
RE		 1386
1387#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1388 if (TARGET_ARM) \
1389 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1390 else \
1391 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1392
35d965d5
RS		 1393/* Return the maximum number of consecutive registers
1394 needed to represent mode MODE in a register of class CLASS.
0be8bd1a
RE		 1395 ARM regs are UNITS_PER_WORD bits.
1396 FIXME: Is this true for iWMMX? */
35d965d5 1397#define CLASS_MAX_NREGS(CLASS, MODE) \
0be8bd1a 1398 (ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1399
1400/* If defined, gives a class of registers that cannot be used as the
1401 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5
RS		 1402\f
1403/* Stack layout; function entry, exit and calling. */
1404
1405/* Define this if pushing a word on the stack
1406 makes the stack pointer a smaller address. */
1407#define STACK_GROWS_DOWNWARD 1
1408
a4d05547 1409/* Define this to nonzero if the nominal address of the stack frame
35d965d5
RS		 1410 is at the high-address end of the local variables;
1411 that is, each additional local variable allocated
1412 goes at a more negative offset in the frame. */
1413#define FRAME_GROWS_DOWNWARD 1
1414
a2503645
RS		 1415/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1416 When present, it is one word in size, and sits at the top of the frame,
1417 between the soft frame pointer and either r7 or r11.
1418
1419 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1420 and only then if some outgoing arguments are passed on the stack. It would
1421 be tempting to also check whether the stack arguments are passed by indirect
1422 calls, but there seems to be no reason in principle why a post-reload pass
1423 couldn't convert a direct call into an indirect one. */
1424#define CALLER_INTERWORKING_SLOT_SIZE \
1425 (TARGET_CALLER_INTERWORKING \
38173d38 1426 && crtl->outgoing_args_size != 0 \
a2503645
RS		 1427 ? UNITS_PER_WORD : 0)
1428
35d965d5
RS		 1429/* Offset within stack frame to start allocating local variables at.
1430 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1431 first local allocated. Otherwise, it is the offset to the BEGINNING
1432 of the first local allocated. */
1433#define STARTING_FRAME_OFFSET 0
1434
1435/* If we generate an insn to push BYTES bytes,
1436 this says how many the stack pointer really advances by. */
d5b7b3ae 1437/* The push insns do not do this rounding implicitly.
d6b4baa4 1438 So don't define this. */
0c2ca901 1439/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1440
1441/* Define this if the maximum size of all the outgoing args is to be
1442 accumulated and pushed during the prologue. The amount can be
38173d38 1443 found in the variable crtl->outgoing_args_size. */
6cfc7210 1444#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1445
1446/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1447#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5 1448
9f7bf991
RE		 1449/* Amount of memory needed for an untyped call to save all possible return
1450 registers. */
1451#define APPLY_RESULT_SIZE arm_apply_result_size()
1452
11c1a207
RE		 1453/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1454 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1455 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1456#define DEFAULT_PCC_STRUCT_RETURN 0
1457
6d3d9133 1458/* These bits describe the different types of function supported
112cdef5 1459 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1460 normal function and an interworked function, for example. Knowing the
1461 type of a function is important for determining its prologue and
1462 epilogue sequences.
1463 Note value 7 is currently unassigned. Also note that the interrupt
1464 function types all have bit 2 set, so that they can be tested for easily.
1465 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1466 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1467 default to unknown. This will force the first use of arm_current_func_type
1468 to call arm_compute_func_type. */
1469#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1470#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1471#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1472#define ARM_FT_ISR 4 /* An interrupt service routine. */
1473#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1474#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1475
1476#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1477
1478/* In addition functions can have several type modifiers,
1479 outlined by these bit masks: */
1480#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1481#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1482#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1483#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
5b3e6663 1484#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
6d3d9133
NC		 1485
1486/* Some macros to test these flags. */
1487#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1488#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1489#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1490#define IS_NAKED(t) (t & ARM_FT_NAKED)
1491#define IS_NESTED(t) (t & ARM_FT_NESTED)
5b3e6663 1492#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
6d3d9133 1493
5848830f
PB		 1494
1495/* Structure used to hold the function stack frame layout. Offsets are
1496 relative to the stack pointer on function entry. Positive offsets are
1497 in the direction of stack growth.
1498 Only soft_frame is used in thumb mode. */
1499
d1b38208 1500typedef struct GTY(()) arm_stack_offsets
5848830f
PB		 1501{
1502 int saved_args; /* ARG_POINTER_REGNUM. */
1503 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1504 int saved_regs;
1505 int soft_frame; /* FRAME_POINTER_REGNUM. */
2591db65 1506 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
5848830f 1507 int outgoing_args; /* STACK_POINTER_REGNUM. */
954954d1 1508 unsigned int saved_regs_mask;
5848830f
PB		 1509}
1510arm_stack_offsets;
1511
906668bb 1512#ifndef GENERATOR_FILE
6d3d9133
NC		 1513/* A C structure for machine-specific, per-function data.
1514 This is added to the cfun structure. */
d1b38208 1515typedef struct GTY(()) machine_function
d5b7b3ae 1516{
6bc82793 1517 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1518 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1519 /* Records if LR has to be saved for far jumps. */
1520 int far_jump_used;
1521 /* Records if ARG_POINTER was ever live. */
1522 int arg_pointer_live;
6f7ebcbb
NC		 1523 /* Records if the save of LR has been eliminated. */
1524 int lr_save_eliminated;
0977774b 1525 /* The size of the stack frame. Only valid after reload. */
5848830f 1526 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1527 /* Records the type of the current function. */
1528 unsigned long func_type;
3cb66fd7
NC		 1529 /* Record if the function has a variable argument list. */
1530 int uses_anonymous_args;
5a9335ef
NC		 1531 /* Records if sibcalls are blocked because an argument
1532 register is needed to preserve stack alignment. */
1533 int sibcall_blocked;
020a4035
RE		 1534 /* The PIC register for this function. This might be a pseudo. */
1535 rtx pic_reg;
b12a00f1 1536 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1537 register. We can never call via LR or PC. We can call via SP if a
1538 trampoline happens to be on the top of the stack. */
1539 rtx call_via[14];
934c2060
RR		 1540 /* Set to 1 when a return insn is output, this means that the epilogue
1541 is not needed. */
1542 int return_used_this_function;
906668bb
BS		 1543 /* When outputting Thumb-1 code, record the last insn that provides
1544 information about condition codes, and the comparison operands. */
1545 rtx thumb1_cc_insn;
1546 rtx thumb1_cc_op0;
1547 rtx thumb1_cc_op1;
1548 /* Also record the CC mode that is supported. */
1549 enum machine_mode thumb1_cc_mode;
b0419491
TG		 1550 /* Set to 1 after arm_reorg has started. */
1551 int after_arm_reorg;
6d3d9133
NC		 1552}
1553machine_function;
906668bb 1554#endif
d5b7b3ae 1555
b12a00f1 1556/* As in the machine_function, a global set of call-via labels, for code
d6b5193b 1557 that is in text_section. */
57ecec57 1558extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1559
390b17c2
RE		 1560/* The number of potential ways of assigning to a co-processor. */
1561#define ARM_NUM_COPROC_SLOTS 1
1562
1563/* Enumeration of procedure calling standard variants. We don't really
1564 support all of these yet. */
1565enum arm_pcs
1566{
1567 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1568 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1569 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1570 /* This must be the last AAPCS variant. */
1571 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1572 ARM_PCS_ATPCS, /* ATPCS. */
1573 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1574 ARM_PCS_UNKNOWN
1575};
1576
12ffc7d5
CLT		 1577/* Default procedure calling standard of current compilation unit. */
1578extern enum arm_pcs arm_pcs_default;
1579
82e9d970 1580/* A C type for declaring a variable that is used as the first argument of
390b17c2 1581 `FUNCTION_ARG' and other related values. */
82e9d970
PB		 1582typedef struct
1583{
d5b7b3ae 1584 /* This is the number of registers of arguments scanned so far. */
82e9d970 1585 int nregs;
5a9335ef
NC		 1586 /* This is the number of iWMMXt register arguments scanned so far. */
1587 int iwmmxt_nregs;
1588 int named_count;
1589 int nargs;
390b17c2
RE		 1590 /* Which procedure call variant to use for this call. */
1591 enum arm_pcs pcs_variant;
1592
1593 /* AAPCS related state tracking. */
1594 int aapcs_arg_processed; /* No need to lay out this argument again. */
1595 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1596 this argument, or -1 if using core
1597 registers. */
1598 int aapcs_ncrn;
1599 int aapcs_next_ncrn;
1600 rtx aapcs_reg; /* Register assigned to this argument. */
1601 int aapcs_partial; /* How many bytes are passed in regs (if
1602 split between core regs and stack.
1603 Zero otherwise. */
1604 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1605 int can_split; /* Argument can be split between core regs
1606 and the stack. */
1607 /* Private data for tracking VFP register allocation */
1608 unsigned aapcs_vfp_regs_free;
1609 unsigned aapcs_vfp_reg_alloc;
1610 int aapcs_vfp_rcount;
46107b99 1611 MACHMODE aapcs_vfp_rmode;
d5b7b3ae 1612} CUMULATIVE_ARGS;
82e9d970 1613
866af8a9
JB		 1614#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1615 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1616
1617#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1618 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1619
1620/* For AAPCS, padding should never be below the argument. For other ABIs,
1621 * mimic the default. */
1622#define PAD_VARARGS_DOWN \
1623 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1624
35d965d5
RS		 1625/* Initialize a variable CUM of type CUMULATIVE_ARGS
1626 for a call to a function whose data type is FNTYPE.
1627 For a library call, FNTYPE is 0.
1628 On the ARM, the offset starts at 0. */
0f6937fe 1629#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1630 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5 1631
35d965d5
RS		 1632/* 1 if N is a possible register number for function argument passing.
1633 On the ARM, r0-r3 are used to pass args. */
390b17c2
RE		 1634#define FUNCTION_ARG_REGNO_P(REGNO) \
1635 (IN_RANGE ((REGNO), 0, 3) \
1636 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1637 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1638 || (TARGET_IWMMXT_ABI \
5848830f 1639 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1640
f99fce0c 1641\f
afef3d7a 1642/* If your target environment doesn't prefix user functions with an
96a3900d 1643 underscore, you may wish to re-define this to prevent any conflicts. */
afef3d7a
NC		 1644#ifndef ARM_MCOUNT_NAME
1645#define ARM_MCOUNT_NAME "*mcount"
1646#endif
1647
1648/* Call the function profiler with a given profile label. The Acorn
1649 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1650 On the ARM the full profile code will look like:
1651 .data
1652 LP1
1653 .word 0
1654 .text
1655 mov ip, lr
1656 bl mcount
1657 .word LP1
1658
1659 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1660 will output the .text section.
1661
1662 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1663 ``prof'' doesn't seem to mind about this!
1664
1665 Note - this version of the code is designed to work in both ARM and
1666 Thumb modes. */
be393ecf 1667#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1668#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1669{ \
1670 char temp[20]; \
1671 rtx sym; \
1672 \
dd18ae56 1673 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1674 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1675 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1676 fputc ('\n', STREAM); \
1677 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1678 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1679 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1680}
be393ecf 1681#endif
35d965d5 1682
59be6073 1683#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1684#define FUNCTION_PROFILER(STREAM, LABELNO) \
1685 if (TARGET_ARM) \
1686 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1687 else \
1688 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1689#else
1690#define FUNCTION_PROFILER(STREAM, LABELNO) \
1691 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1692#endif
d5b7b3ae 1693
35d965d5
RS		 1694/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1695 the stack pointer does not matter. The value is tested only in
1696 functions that have frame pointers.
1697 No definition is equivalent to always zero.
1698
1699 On the ARM, the function epilogue recovers the stack pointer from the
1700 frame. */
1701#define EXIT_IGNORE_STACK 1
1702
2b261262 1703#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
c7861455 1704
35d965d5
RS		 1705/* Determine if the epilogue should be output as RTL.
1706 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1707#define USE_RETURN_INSN(ISCOND) \
7c19c715 1708 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1709
1710/* Definitions for register eliminations.
1711
1712 This is an array of structures. Each structure initializes one pair
1713 of eliminable registers. The "from" register number is given first,
1714 followed by "to". Eliminations of the same "from" register are listed
1715 in order of preference.
1716
1717 We have two registers that can be eliminated on the ARM. First, the
1718 arg pointer register can often be eliminated in favor of the stack
1719 pointer register. Secondly, the pseudo frame pointer register can always
1720 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1721 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1722 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1723
d5b7b3ae
RE		 1724#define ELIMINABLE_REGS \
1725{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1726 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1727 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1728 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1729 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1730 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1731 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1732
d5b7b3ae
RE		 1733/* Define the offset between two registers, one to be eliminated, and the
1734 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1735#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1736 if (TARGET_ARM) \
5848830f 1737 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1738 else \
5848830f
PB		 1739 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1740
d5b7b3ae
RE		 1741/* Special case handling of the location of arguments passed on the stack. */
1742#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1743
d5b7b3ae
RE		 1744/* Initialize data used by insn expanders. This is called from insn_emit,
1745 once for every function before code is generated. */
1746#define INIT_EXPANDERS arm_init_expanders ()
1747
35d965d5 1748/* Length in units of the trampoline for entering a nested function. */
5b3e6663 1749#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
35d965d5 1750
006946e4
JM		 1751/* Alignment required for a trampoline in bits. */
1752#define TRAMPOLINE_ALIGNMENT 32
35d965d5
RS		 1753\f
1754/* Addressing modes, and classification of registers for them. */
3cd45774 1755#define HAVE_POST_INCREMENT 1
5b3e6663
PB		 1756#define HAVE_PRE_INCREMENT TARGET_32BIT
1757#define HAVE_POST_DECREMENT TARGET_32BIT
1758#define HAVE_PRE_DECREMENT TARGET_32BIT
1759#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1760#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1761#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1762#define HAVE_POST_MODIFY_REG TARGET_32BIT
35d965d5 1763
8875e939
RR		 1764enum arm_auto_incmodes
1765 {
1766 ARM_POST_INC,
1767 ARM_PRE_INC,
1768 ARM_POST_DEC,
1769 ARM_PRE_DEC
1770 };
1771
1772#define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1773 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1774#define USE_LOAD_POST_INCREMENT(mode) \
1775 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1776#define USE_LOAD_PRE_INCREMENT(mode) \
1777 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1778#define USE_LOAD_POST_DECREMENT(mode) \
1779 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1780#define USE_LOAD_PRE_DECREMENT(mode) \
1781 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1782
1783#define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1784#define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1785#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1786#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1787
35d965d5
RS		 1788/* Macros to check register numbers against specific register classes. */
1789
1790/* These assume that REGNO is a hard or pseudo reg number.
1791 They give nonzero only if REGNO is a hard reg of the suitable class
1792 or a pseudo reg currently allocated to a suitable hard reg.
1793 Since they use reg_renumber, they are safe only once reg_renumber
aeb9f7cf
SB		 1794 has been allocated, which happens in reginfo.c during register
1795 allocation. */
d5b7b3ae
RE		 1796#define TEST_REGNO(R, TEST, VALUE) \
1797 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1798
5b3e6663 1799/* Don't allow the pc to be used. */
f1008e52
RE		 1800#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1801 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1802 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1803 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1804
5b3e6663 1805#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
f1008e52
RE		 1806 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1807 || (GET_MODE_SIZE (MODE) >= 4 \
1808 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1809
1810#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
5b3e6663
PB		 1811 (TARGET_THUMB1 \
1812 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
f1008e52
RE		 1813 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1814
888d2cd6
DJ		 1815/* Nonzero if X can be the base register in a reg+reg addressing mode.
1816 For Thumb, we can not use SP + reg, so reject SP. */
1817#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
f5c630c3 1818 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
888d2cd6 1819
f1008e52
RE		 1820/* For ARM code, we don't care about the mode, but for Thumb, the index
1821 must be suitable for use in a QImode load. */
d5b7b3ae 1822#define REGNO_OK_FOR_INDEX_P(REGNO) \
f5c630c3
PB		 1823 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1824 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
35d965d5
RS		 1825
1826/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1827 Shifts in addresses can't be by a register. */
ff9940b0 1828#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1829
1830/* Recognize any constant value that is a valid address. */
1831/* XXX We can address any constant, eventually... */
5b3e6663 1832/* ??? Should the TARGET_ARM here also apply to thumb2? */
008cf58a
RE		 1833#define CONSTANT_ADDRESS_P(X) \
1834 (GET_CODE (X) == SYMBOL_REF \
1835 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1836 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1837
8426b956
RS		 1838/* True if SYMBOL + OFFSET constants must refer to something within
1839 SYMBOL's section. */
1840#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1841
571191af
PB		 1842/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1843#ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1844#define TARGET_DEFAULT_WORD_RELOCATIONS 0
1845#endif
1846
c27ba912
DM		 1847#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1848#define SUBTARGET_NAME_ENCODING_LENGTHS
1849#endif
1850
6bc82793 1851/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1852 Each case label should return the number of characters to
1853 be stripped from the start of a function's name, if that
1854 name starts with the indicated character. */
1855#define ARM_NAME_ENCODING_LENGTHS \
00fdafef 1856 case '*': return 1; \
f676971a 1857 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1858
c27ba912
DM		 1859/* This is how to output a reference to a user-level label named NAME.
1860 `assemble_name' uses this. */
e5951263 1861#undef ASM_OUTPUT_LABELREF
c27ba912 1862#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1863 arm_asm_output_labelref (FILE, NAME)
c27ba912 1864
7a085dce 1865/* Output IT instructions for conditionally executed Thumb-2 instructions. */
5b3e6663
PB		 1866#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1867 if (TARGET_THUMB2) \
1868 thumb2_asm_output_opcode (STREAM);
1869
7abc66b1
JB		 1870/* The EABI specifies that constructors should go in .init_array.
1871 Other targets use .ctors for compatibility. */
88c6057f 1872#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1873#define ARM_EABI_CTORS_SECTION_OP \
1874 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1875#endif
1876#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1877#define ARM_EABI_DTORS_SECTION_OP \
1878 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1879#endif
7abc66b1
JB		 1880#define ARM_CTORS_SECTION_OP \
1881 "\t.section\t.ctors,\"aw\",%progbits"
1882#define ARM_DTORS_SECTION_OP \
1883 "\t.section\t.dtors,\"aw\",%progbits"
1884
1885/* Define CTORS_SECTION_ASM_OP. */
1886#undef CTORS_SECTION_ASM_OP
1887#undef DTORS_SECTION_ASM_OP
1888#ifndef IN_LIBGCC2
1889# define CTORS_SECTION_ASM_OP \
1890 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1891# define DTORS_SECTION_ASM_OP \
1892 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1893#else /* !defined (IN_LIBGCC2) */
1894/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1895 so we cannot use the definition above. */
1896# ifdef __ARM_EABI__
1897/* The .ctors section is not part of the EABI, so we do not define
1898 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1899 from trying to use it. We do define it when doing normal
1900 compilation, as .init_array can be used instead of .ctors. */
1901/* There is no need to emit begin or end markers when using
1902 init_array; the dynamic linker will compute the size of the
1903 array itself based on special symbols created by the static
1904 linker. However, we do need to arrange to set up
1905 exception-handling here. */
1906# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1907# define CTOR_LIST_END /* empty */
1908# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1909# define DTOR_LIST_END /* empty */
1910# else /* !defined (__ARM_EABI__) */
1911# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1912# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1913# endif /* !defined (__ARM_EABI__) */
1914#endif /* !defined (IN_LIBCC2) */
1915
1e731102
MM		 1916/* True if the operating system can merge entities with vague linkage
1917 (e.g., symbols in COMDAT group) during dynamic linking. */
1918#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1919#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1920#endif
1921
617a1b71
PB		 1922#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1923
35d965d5
RS		 1924/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1925 and check its validity for a certain class.
1926 We have two alternate definitions for each of them.
1927 The usual definition accepts all pseudo regs; the other rejects
1928 them unless they have been allocated suitable hard regs.
5b3e6663 1929 The symbol REG_OK_STRICT causes the latter definition to be used.
7a085dce 1930 Thumb-2 has the same restrictions as arm. */
35d965d5 1931#ifndef REG_OK_STRICT
ff9940b0 1932
f1008e52
RE		 1933#define ARM_REG_OK_FOR_BASE_P(X) \
1934 (REGNO (X) <= LAST_ARM_REGNUM \
1935 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1936 || REGNO (X) == FRAME_POINTER_REGNUM \
1937 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 1938
f5c630c3
PB		 1939#define ARM_REG_OK_FOR_INDEX_P(X) \
1940 ((REGNO (X) <= LAST_ARM_REGNUM \
1941 && REGNO (X) != STACK_POINTER_REGNUM) \
1942 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1943 || REGNO (X) == FRAME_POINTER_REGNUM \
1944 || REGNO (X) == ARG_POINTER_REGNUM)
1945
5b3e6663 1946#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
f1008e52
RE		 1947 (REGNO (X) <= LAST_LO_REGNUM \
1948 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1949 || (GET_MODE_SIZE (MODE) >= 4 \
1950 && (REGNO (X) == STACK_POINTER_REGNUM \
1951 || (X) == hard_frame_pointer_rtx \
1952 || (X) == arg_pointer_rtx)))
ff9940b0 1953
76a318e9
RE		 1954#define REG_STRICT_P 0
1955
d5b7b3ae 1956#else /* REG_OK_STRICT */
ff9940b0 1957
f1008e52
RE		 1958#define ARM_REG_OK_FOR_BASE_P(X) \
1959 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 1960
f5c630c3
PB		 1961#define ARM_REG_OK_FOR_INDEX_P(X) \
1962 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1963
5b3e6663
PB		 1964#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1965 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 1966
76a318e9
RE		 1967#define REG_STRICT_P 1
1968
d5b7b3ae 1969#endif /* REG_OK_STRICT */
f1008e52
RE		 1970
1971/* Now define some helpers in terms of the above. */
1972
1973#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
5b3e6663
PB		 1974 (TARGET_THUMB1 \
1975 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
f1008e52
RE		 1976 : ARM_REG_OK_FOR_BASE_P (X))
1977
5b3e6663 1978/* For 16-bit Thumb, a valid index register is anything that can be used in
f1008e52 1979 a byte load instruction. */
5b3e6663
PB		 1980#define THUMB1_REG_OK_FOR_INDEX_P(X) \
1981 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
f1008e52
RE		 1982
1983/* Nonzero if X is a hard reg that can be used as an index
1984 or if it is a pseudo reg. On the Thumb, the stack pointer
1985 is not suitable. */
1986#define REG_OK_FOR_INDEX_P(X) \
5b3e6663
PB		 1987 (TARGET_THUMB1 \
1988 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
f1008e52
RE		 1989 : ARM_REG_OK_FOR_INDEX_P (X))
1990
888d2cd6
DJ		 1991/* Nonzero if X can be the base register in a reg+reg addressing mode.
1992 For Thumb, we can not use SP + reg, so reject SP. */
1993#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1994 REG_OK_FOR_INDEX_P (X)
35d965d5 1995\f
f1008e52 1996#define ARM_BASE_REGISTER_RTX_P(X) \
d435a4be 1997 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 1998
f1008e52 1999#define ARM_INDEX_REGISTER_RTX_P(X) \
d435a4be 2000 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2001\f
35d965d5
RS		 2002/* Specify the machine mode that this machine uses
2003 for the index in the tablejump instruction. */
d5b7b3ae 2004#define CASE_VECTOR_MODE Pmode
35d965d5 2005
907dd0c7 2006#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
83c3a2d8 2007 || (TARGET_THUMB1 \
907dd0c7
RE		 2008 && (optimize_size || flag_pic)))
2009
2010#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
83c3a2d8 2011 (TARGET_THUMB1 \
907dd0c7
RE		 2012 ? (min >= 0 && max < 512 \
2013 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2014 : min >= -256 && max < 256 \
2015 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2016 : min >= 0 && max < 8192 \
2017 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2018 : min >= -4096 && max < 4096 \
2019 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2020 : SImode) \
10c241af 2021 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
907dd0c7
RE		 2022 : (max >= 0x200) ? HImode \
2023 : QImode))
5b3e6663 2024
ff9940b0
RE		 2025/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2026 unsigned is probably best, but may break some code. */
2027#ifndef DEFAULT_SIGNED_CHAR
3967692c 2028#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2029#endif
2030
35d965d5 2031/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2032 in one reasonably fast instruction. */
2033#define MOVE_MAX 4
35d965d5 2034
d19fb8e3 2035#undef MOVE_RATIO
e04ad03d 2036#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
d19fb8e3 2037
ff9940b0
RE		 2038/* Define if operations between registers always perform the operation
2039 on the full register even if a narrower mode is specified. */
2040#define WORD_REGISTER_OPERATIONS
2041
2042/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2043 will either zero-extend or sign-extend. The value of this macro should
2044 be the code that says which one of the two operations is implicitly
f822d252 2045 done, UNKNOWN if none. */
9c872872 2046#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2047 (TARGET_THUMB ? ZERO_EXTEND : \
2048 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2049 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2050
35d965d5
RS		 2051/* Nonzero if access to memory by bytes is slow and undesirable. */
2052#define SLOW_BYTE_ACCESS 0
2053
d5b7b3ae 2054#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2055
35d965d5
RS		 2056/* Immediate shift counts are truncated by the output routines (or was it
2057 the assembler?). Shift counts in a register are truncated by ARM. Note
2058 that the native compiler puts too large (> 32) immediate shift counts
2059 into a register and shifts by the register, letting the ARM decide what
2060 to do instead of doing that itself. */
ff9940b0
RE		 2061/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2062 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2063 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2064 rotates is modulo 32 used. */
ff9940b0 2065/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2066
35d965d5 2067/* All integers have the same format so truncation is easy. */
d5b7b3ae 2068#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2069
2070/* Calling from registers is a massive pain. */
2071#define NO_FUNCTION_CSE 1
2072
35d965d5
RS		 2073/* The machine modes of pointers and functions */
2074#define Pmode SImode
2075#define FUNCTION_MODE Pmode
2076
d5b7b3ae
RE		 2077#define ARM_FRAME_RTX(X) \
2078 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2079 || (X) == arg_pointer_rtx)
2080
ff9940b0 2081/* Try to generate sequences that don't involve branches, we can then use
a51fb17f 2082 conditional instructions. */
3a4fd356 2083#define BRANCH_COST(speed_p, predictable_p) \
153668ec
JB		 2084 (current_tune->branch_cost (speed_p, predictable_p))
2085
a51fb17f
BC		 2086/* False if short circuit operation is preferred. */
2087#define LOGICAL_OP_NON_SHORT_CIRCUIT \
2088 ((optimize_size) \
2089 ? (TARGET_THUMB ? false : true) \
2090 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2091
7a801826
RE		 2092\f
2093/* Position Independent Code. */
2094/* We decide which register to use based on the compilation options and
2095 the assembler in use; this is more general than the APCS restriction of
2096 using sb (r9) all the time. */
020a4035 2097extern unsigned arm_pic_register;
7a801826
RE		 2098
2099/* The register number of the register used to address a table of static
2100 data addresses in memory. */
2101#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2102
f5a1b0d2 2103/* We can't directly access anything that contains a symbol,
d3585b76
DJ		 2104 nor can we indirect via the constant pool. One exception is
2105 UNSPEC_TLS, which is always PIC. */
82e9d970 2106#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2107 (!(symbol_mentioned_p (X) \
2108 || label_mentioned_p (X) \
2109 || (GET_CODE (X) == SYMBOL_REF \
2110 && CONSTANT_POOL_ADDRESS_P (X) \
2111 && (symbol_mentioned_p (get_pool_constant (X)) \
d3585b76
DJ		 2112 || label_mentioned_p (get_pool_constant (X))))) \
2113 || tls_mentioned_p (X))
1575c31e 2114
13bd191d
PB		 2115/* We need to know when we are making a constant pool; this determines
2116 whether data needs to be in the GOT or can be referenced via a GOT
2117 offset. */
2118extern int making_const_table;
82e9d970 2119\f
c27ba912 2120/* Handle pragmas for compatibility with Intel's compilers. */
b76c3c4b 2121/* Also abuse this to register additional C specific EABI attributes. */
c58b209a
NB		 2122#define REGISTER_TARGET_PRAGMAS() do { \
2123 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2124 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2125 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
b76c3c4b 2126 arm_lang_object_attributes_init(); \
8b97c5f8
ZW		 2127} while (0)
2128
d6b4baa4 2129/* Condition code information. */
ff9940b0 2130/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2131 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2132
2133#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2134
880873be
RE		 2135#define REVERSIBLE_CC_MODE(MODE) 1
2136
2137#define REVERSE_CONDITION(CODE,MODE) \
2138 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2139 ? reverse_condition_maybe_unordered (code) \
2140 : reverse_condition (code))
008cf58a 2141
7dba8395
RH		 2142/* The arm5 clz instruction returns 32. */
2143#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
ca96ed43 2144#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2145\f
906668bb
BS		 2146#define CC_STATUS_INIT \
2147 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2148
d5b7b3ae 2149#undef ASM_APP_OFF
6a9accca 2150#define ASM_APP_OFF (TARGET_ARM ? "" : "\t.thumb\n")
35d965d5 2151
2ee67fbb
JB		 2152/* Output a push or a pop instruction (only used when profiling).
2153 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2154 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2155 that r7 isn't used by the function profiler, so we can use it as a
2156 scratch reg. WARNING: This isn't safe in the general case! It may be
2157 sensitive to future changes in final.c:profile_function. */
d5b7b3ae 2158#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2159 do \
2160 { \
2161 if (TARGET_ARM) \
2162 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2163 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2164 else if (TARGET_THUMB1 \
2165 && (REGNO) == STATIC_CHAIN_REGNUM) \
2166 { \
2167 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2168 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2169 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2170 } \
8a81cc45
RE		 2171 else \
2172 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2173 } while (0)
d5b7b3ae
RE		 2174
2175
2ee67fbb 2176/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
d5b7b3ae 2177#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2178 do \
2179 { \
2180 if (TARGET_ARM) \
2181 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2182 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2183 else if (TARGET_THUMB1 \
2184 && (REGNO) == STATIC_CHAIN_REGNUM) \
2185 { \
2186 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2187 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2188 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2189 } \
8a81cc45
RE		 2190 else \
2191 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2192 } while (0)
d5b7b3ae 2193
b0fe107e
JM		 2194#define ADDR_VEC_ALIGN(JUMPTABLE) \
2195 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2196
2197/* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2198 default alignment from elfos.h. */
2199#undef ASM_OUTPUT_BEFORE_CASE_LABEL
2200#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
5b3e6663 2201
e75c1617
CB		 2202#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
2203 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
2204 ? 1 : 0)
35d965d5 2205
6cfc7210
NC		 2206#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2207 do \
2208 { \
d5b7b3ae
RE		 2209 if (TARGET_THUMB) \
2210 { \
5b3e6663 2211 if (is_called_in_ARM_mode (DECL) \
bf98ec6c 2212 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
3c072c6b 2213 && cfun->is_thunk)) \
d5b7b3ae 2214 fprintf (STREAM, "\t.code 32\n") ; \
5b3e6663
PB		 2215 else if (TARGET_THUMB1) \
2216 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
d5b7b3ae 2217 else \
5b3e6663 2218 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
d5b7b3ae 2219 } \
6cfc7210 2220 if (TARGET_POKE_FUNCTION_NAME) \
586de218 2221 arm_poke_function_name (STREAM, (const char *) NAME); \
6cfc7210
NC		 2222 } \
2223 while (0)
35d965d5 2224
d5b7b3ae
RE		 2225/* For aliases of functions we use .thumb_set instead. */
2226#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2227 do \
2228 { \
91ea4f8d
KG		 2229 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2230 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2231 \
2232 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2233 { \
2234 fprintf (FILE, "\t.thumb_set "); \
2235 assemble_name (FILE, LABEL1); \
2236 fprintf (FILE, ","); \
2237 assemble_name (FILE, LABEL2); \
2238 fprintf (FILE, "\n"); \
2239 } \
2240 else \
2241 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2242 } \
2243 while (0)
2244
fdc2d3b0
NC		 2245#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2246/* To support -falign-* switches we need to use .p2align so
2247 that alignment directives in code sections will be padded
2248 with no-op instructions, rather than zeroes. */
5a9335ef 2249#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2250 if ((LOG) != 0) \
2251 { \
2252 if ((MAX_SKIP) == 0) \
5a9335ef 2253 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2254 else \
2255 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2256 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2257 }
2258#endif
35d965d5 2259\f
5b3e6663
PB		 2260/* Add two bytes to the length of conditionally executed Thumb-2
2261 instructions for the IT instruction. */
2262#define ADJUST_INSN_LENGTH(insn, length) \
2263 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2264 length += 2;
2265
35d965d5 2266/* Only perform branch elimination (by making instructions conditional) if
5b3e6663
PB		 2267 we're optimizing. For Thumb-2 check if any IT instructions need
2268 outputting. */
d5b7b3ae
RE		 2269#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2270 if (TARGET_ARM && optimize) \
2271 arm_final_prescan_insn (INSN); \
5b3e6663
PB		 2272 else if (TARGET_THUMB2) \
2273 thumb2_final_prescan_insn (INSN); \
2274 else if (TARGET_THUMB1) \
2275 thumb1_final_prescan_insn (INSN)
35d965d5 2276
7b8b8ade
NC		 2277#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2278 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2279 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2280 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2281 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2282 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2283 : 0))))
35d965d5 2284
6a5d7526
MS		 2285/* A C expression whose value is RTL representing the value of the return
2286 address for the frame COUNT steps up from the current frame. */
2287
d5b7b3ae
RE		 2288#define RETURN_ADDR_RTX(COUNT, FRAME) \
2289 arm_return_addr (COUNT, FRAME)
2290
f676971a 2291/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2292 when running in 26-bit mode. */
2293#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2294
2c849145
JM		 2295/* Pick up the return address upon entry to a procedure. Used for
2296 dwarf2 unwind information. This also enables the table driven
2297 mechanism. */
2c849145
JM		 2298#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2299#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2300
39950dff
MS		 2301/* Used to mask out junk bits from the return address, such as
2302 processor state, interrupt status, condition codes and the like. */
2303#define MASK_RETURN_ADDR \
2304 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2305 in 26 bit mode, the condition codes must be masked out of the \
2306 return address. This does not apply to ARM6 and later processors \
2307 when running in 32 bit mode. */ \
61f0ccff
RE		 2308 ((arm_arch4 || TARGET_THUMB) \
2309 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2310 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2311
2312\f
978e411f
CD		 2313/* Do not emit .note.GNU-stack by default. */
2314#ifndef NEED_INDICATE_EXEC_STACK
2315#define NEED_INDICATE_EXEC_STACK 0
2316#endif
2317
9e94a7fc
MGD		 2318#define TARGET_ARM_ARCH \
2319 (arm_base_arch) \
2320
2321#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2322#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2323
2324/* The highest Thumb instruction set version supported by the chip. */
2325#define TARGET_ARM_ARCH_ISA_THUMB \
2326 (arm_arch_thumb2 ? 2 \
2327 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2328
2329/* Expands to an upper-case char of the target's architectural
2330 profile. */
2331#define TARGET_ARM_ARCH_PROFILE \
2332 (!arm_arch_notm \
2333 ? 'M' \
2334 : (arm_arch7 \
2335 ? (strlen (arm_arch_name) >=3 \
2336 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2337 : 0) \
2338 : 0))
2339
2340/* Bit-field indicating what size LDREX/STREX loads/stores are available.
2341 Bit 0 for bytes, up to bit 3 for double-words. */
2342#define TARGET_ARM_FEATURE_LDREX \
2343 ((TARGET_HAVE_LDREX ? 4 : 0) \
2344 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2345 | (TARGET_HAVE_LDREXD ? 8 : 0))
2346
2347/* Set as a bit mask indicating the available widths of hardware floating
2348 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2349 32-bit support, bit 3 indicates 64-bit support. */
2350#define TARGET_ARM_FP \
2351 (TARGET_VFP_SINGLE ? 4 \
2352 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2353
2354
2355/* Set as a bit mask indicating the available widths of floating point
2356 types for hardware NEON floating point. This is the same as
2357 TARGET_ARM_FP without the 64-bit bit set. */
2358#ifdef TARGET_NEON
2359#define TARGET_NEON_FP \
2360 (TARGET_ARM_FP & (0xff ^ 0x08))
2361#endif
2362
93b338c3
BS		 2363/* The maximum number of parallel loads or stores we support in an ldm/stm
2364 instruction. */
2365#define MAX_LDM_STM_OPS 4
2366
b848e289 2367#define BIG_LITTLE_SPEC \
84e90123 2368 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
b848e289
JG		 2369
2370extern const char *arm_rewrite_mcpu (int argc, const char **argv);
2371#define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
2372 { "rewrite_mcpu", arm_rewrite_mcpu },
2373
54e73f88
AS		 2374#define ASM_CPU_SPEC \
2375 " %{mcpu=generic-*:-march=%*;" \
b848e289
JG		 2376 " :%{march=*:-march=%*}}" \
2377 BIG_LITTLE_SPEC
54e73f88 2378
33aa08b3
AS		 2379/* -mcpu=native handling only makes sense with compiler running on
2380 an ARM chip. */
2381#if defined(__arm__)
2382extern const char *host_detect_local_cpu (int argc, const char **argv);
2383# define EXTRA_SPEC_FUNCTIONS \
b848e289
JG		 2384 { "local_cpu_detect", host_detect_local_cpu }, \
2385 BIG_LITTLE_CPU_SPEC_FUNCTIONS
33aa08b3
AS		 2386
2387# define MCPU_MTUNE_NATIVE_SPECS \
2388 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2389 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2390 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2391#else
2392# define MCPU_MTUNE_NATIVE_SPECS ""
b848e289 2393# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
33aa08b3
AS		 2394#endif
2395
2396#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2397
88657302 2398#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git