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35d965d5 | 1 | /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. |
7a801826 | 2 | Copyright (C) 1991, 93, 94, 95, 96, 1997 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
ff9940b0 RE |
5 | More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) |
6 | ||
35d965d5 RS |
7 | This file is part of GNU CC. |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 23 | |
52a02435 | 24 | /* Configuration triples for ARM ports work as follows: |
9e7d0bcc | 25 | (This is a bit of a mess and needs some thought) |
52a02435 DE |
26 | arm-*-*: little endian |
27 | armel-*-*: little endian | |
28 | armeb-*-*: big endian | |
5da4dc2c DE |
29 | If a non-embedded environment (ie: "real" OS) is specified, `arm' |
30 | should default to that used by the OS. | |
52a02435 DE |
31 | */ |
32 | ||
7a801826 RE |
33 | #define TARGET_CPU_arm2 0x0000 |
34 | #define TARGET_CPU_arm250 0x0000 | |
35 | #define TARGET_CPU_arm3 0x0000 | |
36 | #define TARGET_CPU_arm6 0x0001 | |
37 | #define TARGET_CPU_arm600 0x0001 | |
38 | #define TARGET_CPU_arm610 0x0002 | |
39 | #define TARGET_CPU_arm7 0x0001 | |
40 | #define TARGET_CPU_arm7m 0x0004 | |
41 | #define TARGET_CPU_arm7dm 0x0004 | |
42 | #define TARGET_CPU_arm7dmi 0x0004 | |
43 | #define TARGET_CPU_arm700 0x0001 | |
44 | #define TARGET_CPU_arm710 0x0002 | |
45 | #define TARGET_CPU_arm7100 0x0002 | |
46 | #define TARGET_CPU_arm7500 0x0002 | |
47 | #define TARGET_CPU_arm7500fe 0x1001 | |
48 | #define TARGET_CPU_arm7tdmi 0x0008 | |
49 | #define TARGET_CPU_arm8 0x0010 | |
50 | #define TARGET_CPU_arm810 0x0020 | |
51 | #define TARGET_CPU_strongarm 0x0040 | |
52 | #define TARGET_CPU_strongarm110 0x0040 | |
53 | /* Configure didn't specify */ | |
54 | #define TARGET_CPU_generic 0x8000 | |
ff9940b0 | 55 | |
89c7ca52 RE |
56 | enum arm_cond_code |
57 | { | |
58 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
59 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
60 | }; | |
61 | extern enum arm_cond_code arm_current_cc; | |
ff9940b0 RE |
62 | extern char *arm_condition_codes[]; |
63 | ||
89c7ca52 RE |
64 | #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1)) |
65 | ||
ff9940b0 RE |
66 | /* This is needed by the tail-calling peepholes */ |
67 | extern int frame_pointer_needed; | |
68 | ||
35d965d5 | 69 | \f |
7a801826 RE |
70 | /* Just in case configure has failed to define anything. */ |
71 | #ifndef TARGET_CPU_DEFAULT | |
72 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
73 | #endif | |
74 | ||
75 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
76 | override it. If it doesn't, then default to an ARM6. */ | |
77 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic | |
78 | #undef TARGET_CPU_DEFAULT | |
79 | #ifdef SUBTARGET_CPU_DEFAULT | |
80 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
81 | #else | |
82 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
83 | #endif | |
84 | #endif | |
85 | ||
86 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
87 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
88 | #else | |
89 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFUALT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe | |
90 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" | |
91 | #else | |
92 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
93 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
94 | #else | |
95 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi | |
96 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" | |
97 | #else | |
98 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm | |
99 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" | |
100 | #else | |
101 | Unrecognized value in TARGET_CPU_DEFAULT. | |
102 | #endif | |
103 | #endif | |
104 | #endif | |
105 | #endif | |
106 | #endif | |
107 | ||
ff9940b0 RE |
108 | #ifndef CPP_PREDEFINES |
109 | #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" | |
110 | #endif | |
35d965d5 | 111 | |
38fc909b RE |
112 | #define CPP_SPEC "\ |
113 | %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \ | |
114 | %(cpp_endian) %(subtarget_cpp_spec)" | |
7a801826 | 115 | |
71791e16 RE |
116 | /* Set the architecture define -- if -march= is set, then it overrides |
117 | the -mcpu= setting. */ | |
7a801826 RE |
118 | #define CPP_CPU_ARCH_SPEC "\ |
119 | %{m2:-D__arm2__ -D__ARM_ARCH_2__} \ | |
120 | %{m3:-D__arm2__ -D__ARM_ARCH_2__} \ | |
121 | %{m6:-D__arm6__ -D__ARM_ARCH_3__} \ | |
71791e16 RE |
122 | %{march=arm2:-D__ARM_ARCH_2__} \ |
123 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
124 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
125 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
126 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
127 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
128 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
129 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
130 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
131 | %{march=arm7100:-D__ARM_ARCH_3__} \ | |
132 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
133 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
134 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
135 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
136 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
137 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
138 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
139 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
140 | %{march=strongarm:-D__ARM_ARCH_4__} \ | |
141 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
142 | %{march=armv2:-D__ARM_ARCH_2__} \ | |
143 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
144 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
145 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
146 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
147 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
148 | %{!march=*: \ | |
149 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
150 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
151 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
152 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
153 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
154 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
155 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
156 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
157 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
158 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ | |
159 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
160 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
161 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
162 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
163 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
164 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
165 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
166 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
167 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ | |
168 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
169 | %{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \ | |
11c1a207 | 170 | " |
7a801826 RE |
171 | |
172 | /* Define __APCS_26__ if the PC also contains the PSR */ | |
173 | /* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set, | |
174 | ??? Delete this for 2.9. */ | |
175 | #define CPP_APCS_PC_SPEC "\ | |
176 | %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ | |
177 | -D__APCS_32__} \ | |
178 | %{mapcs-26:-D__APCS_26__} \ | |
179 | %{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \ | |
180 | %{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \ | |
181 | " | |
182 | ||
183 | #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__" | |
184 | ||
185 | #define CPP_FLOAT_SPEC "\ | |
186 | %{msoft-float:\ | |
187 | %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \ | |
188 | -D__SOFTFP__} \ | |
189 | %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \ | |
190 | " | |
191 | ||
192 | /* Default is hard float, which doesn't define anything */ | |
193 | #define CPP_FLOAT_DEFAULT_SPEC "" | |
194 | ||
195 | #define CPP_ENDIAN_SPEC "\ | |
196 | %{mbig-endian: \ | |
197 | %{mlittle-endian: \ | |
198 | %e-mbig-endian and -mlittle-endian may not be used together} \ | |
7a801826 | 199 | -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \ |
9e7d0bcc | 200 | %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \ |
7a801826 RE |
201 | " |
202 | ||
203 | /* Default is little endian, which doesn't define anything. */ | |
204 | #define CPP_ENDIAN_DEFAULT_SPEC "" | |
205 | ||
206 | /* Translate (for now) the old -m[236] option into the appropriate -mcpu=... | |
207 | and -mapcs-xx equivalents. | |
9e7d0bcc | 208 | ??? Remove support for this style in 2.9.*/ |
7a801826 RE |
209 | #define CC1_SPEC "\ |
210 | %{m2:-mcpu=arm2 -mapcs-26} \ | |
211 | %{m3:-mcpu=arm3 -mapcs-26} \ | |
212 | %{m6:-mcpu=arm6 -mapcs-32} \ | |
7a801826 RE |
213 | " |
214 | ||
215 | /* This macro defines names of additional specifications to put in the specs | |
216 | that can be used in various specifications like CC1_SPEC. Its definition | |
217 | is an initializer with a subgrouping for each command option. | |
218 | ||
219 | Each subgrouping contains a string constant, that defines the | |
220 | specification name, and a string constant that used by the GNU CC driver | |
221 | program. | |
222 | ||
223 | Do not define this macro if it does not need to do anything. */ | |
224 | #define EXTRA_SPECS \ | |
225 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
226 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
227 | { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \ | |
228 | { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \ | |
229 | { "cpp_float", CPP_FLOAT_SPEC }, \ | |
230 | { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ | |
231 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
232 | { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ | |
38fc909b | 233 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
234 | SUBTARGET_EXTRA_SPECS |
235 | ||
236 | #define SUBTARGET_EXTRA_SPECS | |
38fc909b | 237 | #define SUBTARGET_CPP_SPEC "" |
7a801826 | 238 | |
35d965d5 RS |
239 | \f |
240 | /* Run-time Target Specification. */ | |
ff9940b0 | 241 | #ifndef TARGET_VERSION |
35d965d5 | 242 | #define TARGET_VERSION \ |
ff9940b0 RE |
243 | fputs (" (ARM/generic)", stderr); |
244 | #endif | |
35d965d5 | 245 | |
11c1a207 | 246 | /* Run-time compilation parameters selecting different hardware subsets. */ |
35d965d5 RS |
247 | extern int target_flags; |
248 | ||
71791e16 RE |
249 | /* The floating point instruction architecture, can be 2 or 3 */ |
250 | extern char *target_fp_name; | |
11c1a207 | 251 | |
35d965d5 RS |
252 | /* Nonzero if the function prologue (and epilogue) should obey |
253 | the ARM Procedure Call Standard. */ | |
11c1a207 | 254 | #define ARM_FLAG_APCS_FRAME (0x0001) |
35d965d5 RS |
255 | |
256 | /* Nonzero if the function prologue should output the function name to enable | |
257 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
258 | unused on RISCiX). Specifying this flag also enables |
259 | -fno-omit-frame-pointer. | |
35d965d5 | 260 | XXX Must still be implemented in the prologue. */ |
11c1a207 | 261 | #define ARM_FLAG_POKE (0x0002) |
35d965d5 RS |
262 | |
263 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
264 | case instruction scheduling becomes very uninteresting. */ | |
11c1a207 | 265 | #define ARM_FLAG_FPE (0x0004) |
35d965d5 | 266 | |
ff9940b0 RE |
267 | /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration |
268 | of condition flags when returning from a branch & link (ie. a function) */ | |
11c1a207 RE |
269 | /* ********* DEPRECATED ******** */ |
270 | #define ARM_FLAG_ARM6 (0x0008) | |
271 | ||
272 | /* ********* DEPRECATED ******** */ | |
273 | #define ARM_FLAG_ARM3 (0x0010) | |
274 | ||
275 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit | |
276 | that assume restoration of the condition flags when returning from a | |
277 | branch and link (ie a function). */ | |
278 | #define ARM_FLAG_APCS_32 (0x0020) | |
279 | ||
280 | /* Nonzero if stack checking should be performed on entry to each function | |
281 | which allocates temporary variables on the stack. */ | |
282 | #define ARM_FLAG_APCS_STACK (0x0040) | |
283 | ||
284 | /* Nonzero if floating point parameters should be passed to functions in | |
285 | floating point registers. */ | |
286 | #define ARM_FLAG_APCS_FLOAT (0x0080) | |
287 | ||
288 | /* Nonzero if re-entrant, position independent code should be generated. | |
289 | This is equivalent to -fpic. */ | |
290 | #define ARM_FLAG_APCS_REENT (0x0100) | |
291 | ||
292 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be | |
293 | loaded byte-at-a-time. */ | |
294 | #define ARM_FLAG_SHORT_BYTE (0x0200) | |
295 | ||
296 | /* Nonzero if all floating point instructions are missing (and there is no | |
297 | emulator either). Generate function calls for all ops in this case. */ | |
298 | #define ARM_FLAG_SOFT_FLOAT (0x0400) | |
299 | ||
300 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
301 | #define ARM_FLAG_BIG_END (0x0800) | |
302 | ||
303 | /* Nonzero if we should compile for Thumb interworking. */ | |
304 | #define ARM_FLAG_THUMB (0x1000) | |
305 | ||
ddee6aba RE |
306 | /* Nonzero if we should have little-endian words even when compiling for |
307 | big-endian (for backwards compatibility with older versions of GCC). */ | |
308 | #define ARM_FLAG_LITTLE_WORDS (0x2000) | |
309 | ||
11c1a207 RE |
310 | #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME) |
311 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) | |
312 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
313 | #define TARGET_6 (target_flags & ARM_FLAG_ARM6) | |
314 | #define TARGET_3 (target_flags & ARM_FLAG_ARM3) | |
315 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) | |
316 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
317 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
318 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
319 | #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE) | |
320 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) | |
321 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
322 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
323 | #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB) | |
ddee6aba | 324 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
3ada8e17 DE |
325 | |
326 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. | |
327 | Bit 31 is reserved. See riscix.h. */ | |
328 | #ifndef SUBTARGET_SWITCHES | |
329 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
330 | #endif |
331 | ||
2ce9c1b9 RE |
332 | #define TARGET_SWITCHES \ |
333 | { \ | |
11c1a207 RE |
334 | {"apcs", ARM_FLAG_APCS_FRAME}, \ |
335 | {"apcs-frame", ARM_FLAG_APCS_FRAME}, \ | |
336 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME}, \ | |
337 | {"poke-function-name", ARM_FLAG_POKE}, \ | |
338 | {"fpe", ARM_FLAG_FPE}, \ | |
339 | {"6", ARM_FLAG_ARM6}, \ | |
340 | {"2", ARM_FLAG_ARM3}, \ | |
341 | {"3", ARM_FLAG_ARM3}, \ | |
342 | {"apcs-32", ARM_FLAG_APCS_32}, \ | |
343 | {"apcs-26", -ARM_FLAG_APCS_32}, \ | |
344 | {"apcs-stack-check", ARM_FLAG_APCS_STACK}, \ | |
345 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK}, \ | |
346 | {"apcs-float", ARM_FLAG_APCS_FLOAT}, \ | |
347 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT}, \ | |
348 | {"apcs-reentrant", ARM_FLAG_APCS_REENT}, \ | |
349 | {"no-apcs-rentrant", -ARM_FLAG_APCS_REENT}, \ | |
350 | {"short-load-bytes", ARM_FLAG_SHORT_BYTE}, \ | |
351 | {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE}, \ | |
352 | {"short-load-words", -ARM_FLAG_SHORT_BYTE}, \ | |
353 | {"no-short-load-words", ARM_FLAG_SHORT_BYTE}, \ | |
354 | {"soft-float", ARM_FLAG_SOFT_FLOAT}, \ | |
355 | {"hard-float", -ARM_FLAG_SOFT_FLOAT}, \ | |
356 | {"big-endian", ARM_FLAG_BIG_END}, \ | |
11c1a207 | 357 | {"little-endian", -ARM_FLAG_BIG_END}, \ |
11c1a207 RE |
358 | {"thumb-interwork", ARM_FLAG_THUMB}, \ |
359 | {"no-thumb-interwork", -ARM_FLAG_THUMB}, \ | |
ddee6aba | 360 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS}, \ |
3ada8e17 | 361 | SUBTARGET_SWITCHES \ |
11c1a207 | 362 | {"", TARGET_DEFAULT } \ |
35d965d5 RS |
363 | } |
364 | ||
62dd06ea RE |
365 | #define TARGET_OPTIONS \ |
366 | { \ | |
367 | {"cpu=", &arm_select[1].string}, \ | |
71791e16 RE |
368 | {"arch=", &arm_select[2].string}, \ |
369 | {"tune=", &arm_select[3].string}, \ | |
370 | {"fp=", &target_fp_name} \ | |
11c1a207 | 371 | } |
ff9940b0 | 372 | |
62dd06ea RE |
373 | /* arm_select[0] is reserved for the default cpu. */ |
374 | struct arm_cpu_select | |
375 | { | |
376 | char *string; | |
377 | char *name; | |
378 | int set_tune_p; | |
379 | int set_arch_p; | |
380 | }; | |
381 | ||
382 | extern struct arm_cpu_select arm_select[]; | |
383 | ||
384 | #ifndef PROCESSOR_DEFAULT | |
385 | #define PROCESSOR_DEFAULT PROCESSOR_ARM2 | |
386 | #endif | |
387 | ||
388 | #ifndef TARGET_CPU_DEFAULT | |
389 | #define TARGET_CPU_DEFAULT ((char *) 0) | |
390 | #endif | |
391 | ||
71791e16 RE |
392 | /* Which processor we are running on, for instruction scheduling |
393 | purposes. */ | |
ff9940b0 RE |
394 | enum processor_type |
395 | { | |
396 | PROCESSOR_ARM2, | |
397 | PROCESSOR_ARM3, | |
11c1a207 | 398 | PROCESSOR_ARM6, |
7a801826 RE |
399 | PROCESSOR_ARM7, |
400 | PROCESSOR_ARM8, | |
71791e16 RE |
401 | PROCESSOR_STARM, |
402 | PROCESSOR_NONE /* NOTE: This must be last, since it doesn't | |
403 | appear in the attr_cpu list */ | |
ff9940b0 RE |
404 | }; |
405 | ||
ff9940b0 RE |
406 | /* Recast the cpu class to be the cpu attribute. */ |
407 | #define arm_cpu_attr ((enum attr_cpu)arm_cpu) | |
408 | ||
409 | extern enum processor_type arm_cpu; | |
410 | ||
11c1a207 RE |
411 | enum prog_mode_type |
412 | { | |
413 | prog_mode26, | |
414 | prog_mode32 | |
415 | }; | |
416 | ||
417 | /* Recast the program mode class to be the prog_mode attribute */ | |
418 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
419 | ||
420 | extern enum prog_mode_type arm_prgmode; | |
421 | ||
422 | /* What sort of floating point unit do we have? Hardware or software. | |
423 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
424 | enum floating_point_type |
425 | { | |
426 | FP_HARD, | |
11c1a207 RE |
427 | FP_SOFT2, |
428 | FP_SOFT3 | |
24f0c1b4 RE |
429 | }; |
430 | ||
431 | /* Recast the floating point class to be the floating point attribute. */ | |
432 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
433 | ||
71791e16 | 434 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
435 | extern enum floating_point_type arm_fpu; |
436 | ||
71791e16 RE |
437 | /* What type of floating point instructions are available */ |
438 | extern enum floating_point_type arm_fpu_arch; | |
439 | ||
440 | /* Default floating point archtitecture. Override in sub-target if | |
441 | necessary. */ | |
442 | #define FP_DEFAULT FP_SOFT2 | |
443 | ||
11c1a207 RE |
444 | /* Nonzero if the processor has a fast multiply insn, and one that does |
445 | a 64-bit multiply of two 32-bit values. */ | |
446 | extern int arm_fast_multiply; | |
447 | ||
71791e16 | 448 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
449 | extern int arm_arch4; |
450 | ||
2ce9c1b9 | 451 | #ifndef TARGET_DEFAULT |
35d965d5 | 452 | #define TARGET_DEFAULT 0 |
2ce9c1b9 | 453 | #endif |
35d965d5 | 454 | |
11c1a207 RE |
455 | /* The frame pointer register used in gcc has nothing to do with debugging; |
456 | that is controlled by the APCS-FRAME option. */ | |
457 | /* Not fully implemented yet */ | |
458 | /* #define CAN_DEBUG_WITHOUT_FP 1 */ | |
35d965d5 | 459 | |
11c1a207 RE |
460 | #define TARGET_MEM_FUNCTIONS 1 |
461 | ||
462 | #define OVERRIDE_OPTIONS arm_override_options () | |
35d965d5 RS |
463 | \f |
464 | /* Target machine storage Layout. */ | |
465 | ||
ff9940b0 RE |
466 | |
467 | /* Define this macro if it is advisable to hold scalars in registers | |
468 | in a wider mode than that declared by the program. In such cases, | |
469 | the value is constrained to be within the bounds of the declared | |
470 | type, but kept valid in the wider mode. The signedness of the | |
471 | extension may differ from that of the type. */ | |
472 | ||
473 | /* It is far faster to zero extend chars than to sign extend them */ | |
474 | ||
475 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
2ce9c1b9 RE |
476 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
477 | && GET_MODE_SIZE (MODE) < 4) \ | |
478 | { \ | |
479 | if (MODE == QImode) \ | |
480 | UNSIGNEDP = 1; \ | |
481 | else if (MODE == HImode) \ | |
482 | UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \ | |
483 | (MODE) = SImode; \ | |
ff9940b0 RE |
484 | } |
485 | ||
486 | /* Define for XFmode extended real floating point support. | |
487 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
488 | /* For the ARM: | |
489 | I think I have added all the code to make this work. Unfortunately, | |
490 | early releases of the floating point emulation code on RISCiX used a | |
491 | different format for extended precision numbers. On my RISCiX box there | |
492 | is a bug somewhere which causes the machine to lock up when running enquire | |
493 | with long doubles. There is the additional aspect that Norcroft C | |
494 | treats long doubles as doubles and we ought to remain compatible. | |
495 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
496 | to try this someday. */ | |
497 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
498 | ||
499 | /* Disable XFmode patterns in md file */ | |
500 | #define ENABLE_XF_PATTERNS 0 | |
501 | ||
502 | /* Define if you don't want extended real, but do want to use the | |
503 | software floating point emulator for REAL_ARITHMETIC and | |
504 | decimal <-> binary conversion. */ | |
505 | /* See comment above */ | |
506 | #define REAL_ARITHMETIC | |
507 | ||
35d965d5 RS |
508 | /* Define this if most significant bit is lowest numbered |
509 | in instructions that operate on numbered bit-fields. */ | |
510 | #define BITS_BIG_ENDIAN 0 | |
511 | ||
9c872872 | 512 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
513 | Most ARM processors are run in little endian mode, so that is the default. |
514 | If you want to have it run-time selectable, change the definition in a | |
515 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 516 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
517 | |
518 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
519 | numbered. |
520 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
521 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
522 | ||
523 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
524 | on processor pre-defineds when compiling libgcc2.c. */ | |
525 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
526 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
527 | #else | |
528 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
529 | #endif | |
35d965d5 | 530 | |
11c1a207 RE |
531 | /* Define this if most significant word of doubles is the lowest numbered. |
532 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
533 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
534 | ||
b4ac57ab | 535 | /* Number of bits in an addressable storage unit */ |
35d965d5 RS |
536 | #define BITS_PER_UNIT 8 |
537 | ||
538 | #define BITS_PER_WORD 32 | |
539 | ||
540 | #define UNITS_PER_WORD 4 | |
541 | ||
542 | #define POINTER_SIZE 32 | |
543 | ||
544 | #define PARM_BOUNDARY 32 | |
545 | ||
546 | #define STACK_BOUNDARY 32 | |
547 | ||
548 | #define FUNCTION_BOUNDARY 32 | |
549 | ||
550 | #define EMPTY_FIELD_BOUNDARY 32 | |
551 | ||
552 | #define BIGGEST_ALIGNMENT 32 | |
553 | ||
ff9940b0 RE |
554 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
555 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
556 | (TREE_CODE (EXP) == STRING_CST \ | |
557 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
558 | ||
b4ac57ab | 559 | /* Every structures size must be a multiple of 32 bits. */ |
7d94bb81 DE |
560 | /* This is for compatibility with ARMCC. ARM SDT Reference Manual |
561 | (ARM DUI 0020D) page 2-20 says "Structures are aligned on word | |
562 | boundaries". */ | |
b4ac57ab RS |
563 | #define STRUCTURE_SIZE_BOUNDARY 32 |
564 | ||
ff9940b0 RE |
565 | /* Non-zero if move instructions will actually fail to work |
566 | when given unaligned data. */ | |
35d965d5 RS |
567 | #define STRICT_ALIGNMENT 1 |
568 | ||
ff9940b0 RE |
569 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
570 | ||
35d965d5 RS |
571 | \f |
572 | /* Standard register usage. */ | |
573 | ||
574 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
575 | (S - saved over call). | |
576 | ||
577 | r0 * argument word/integer result | |
578 | r1-r3 argument word | |
579 | ||
580 | r4-r8 S register variable | |
581 | r9 S (rfp) register variable (real frame pointer) | |
582 | ||
583 | r10 F S (sl) stack limit (not currently used) | |
584 | r11 F S (fp) argument pointer | |
585 | r12 (ip) temp workspace | |
586 | r13 F S (sp) lower end of current stack frame | |
587 | r14 (lr) link address/workspace | |
588 | r15 F (pc) program counter | |
589 | ||
590 | f0 floating point result | |
591 | f1-f3 floating point scratch | |
592 | ||
593 | f4-f7 S floating point variable | |
594 | ||
ff9940b0 RE |
595 | cc This is NOT a real register, but is used internally |
596 | to represent things that use or set the condition | |
597 | codes. | |
598 | sfp This isn't either. It is used during rtl generation | |
599 | since the offset between the frame pointer and the | |
600 | auto's isn't known until after register allocation. | |
601 | afp Nor this, we only need this because of non-local | |
602 | goto. Without it fp appears to be used and the | |
603 | elimination code won't get rid of sfp. It tracks | |
604 | fp exactly at all times. | |
605 | ||
35d965d5 RS |
606 | *: See CONDITIONAL_REGISTER_USAGE */ |
607 | ||
ff9940b0 RE |
608 | /* The stack backtrace structure is as follows: |
609 | fp points to here: | save code pointer | [fp] | |
610 | | return link value | [fp, #-4] | |
611 | | return sp value | [fp, #-8] | |
612 | | return fp value | [fp, #-12] | |
613 | [| saved r10 value |] | |
614 | [| saved r9 value |] | |
615 | [| saved r8 value |] | |
616 | [| saved r7 value |] | |
617 | [| saved r6 value |] | |
618 | [| saved r5 value |] | |
619 | [| saved r4 value |] | |
620 | [| saved r3 value |] | |
621 | [| saved r2 value |] | |
622 | [| saved r1 value |] | |
623 | [| saved r0 value |] | |
624 | [| saved f7 value |] three words | |
625 | [| saved f6 value |] three words | |
626 | [| saved f5 value |] three words | |
627 | [| saved f4 value |] three words | |
628 | r0-r3 are not normally saved in a C function. */ | |
629 | ||
630 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ | |
631 | #define FIRST_PSEUDO_REGISTER 27 | |
35d965d5 RS |
632 | |
633 | /* 1 for registers that have pervasive standard uses | |
634 | and are not available for the register allocator. */ | |
635 | #define FIXED_REGISTERS \ | |
636 | { \ | |
637 | 0,0,0,0,0,0,0,0, \ | |
638 | 0,0,1,1,0,1,0,1, \ | |
ff9940b0 RE |
639 | 0,0,0,0,0,0,0,0, \ |
640 | 1,1,1 \ | |
35d965d5 RS |
641 | } |
642 | ||
643 | /* 1 for registers not available across function calls. | |
644 | These must include the FIXED_REGISTERS and also any | |
645 | registers that can be used without being saved. | |
646 | The latter must include the registers where values are returned | |
647 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
648 | Aside from that, you can include as many other registers as you like. |
649 | The CC is not preserved over function calls on the ARM 6, so it is | |
650 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
651 | #define CALL_USED_REGISTERS \ |
652 | { \ | |
653 | 1,1,1,1,0,0,0,0, \ | |
654 | 0,0,1,1,1,1,1,1, \ | |
ff9940b0 RE |
655 | 1,1,1,1,0,0,0,0, \ |
656 | 1,1,1 \ | |
35d965d5 RS |
657 | } |
658 | ||
659 | /* If doing stupid life analysis, avoid a bug causing a return value r0 to be | |
660 | trampled. This effectively reduces the number of available registers by 1. | |
661 | XXX It is a hack, I know. | |
662 | XXX Is this still needed? */ | |
663 | #define CONDITIONAL_REGISTER_USAGE \ | |
3ada8e17 DE |
664 | { \ |
665 | if (obey_regdecls) \ | |
666 | fixed_regs[0] = 1; \ | |
667 | if (TARGET_SOFT_FLOAT) \ | |
668 | { \ | |
669 | int regno; \ | |
670 | for (regno = 16; regno < 24; ++regno) \ | |
671 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
672 | } \ | |
7a801826 RE |
673 | if (flag_pic) \ |
674 | { \ | |
675 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
676 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \ | |
677 | } \ | |
35d965d5 RS |
678 | } |
679 | ||
680 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
681 | to hold something of mode MODE. | |
682 | This is ordinarily the length in words of a value of mode MODE | |
683 | but can be less for certain modes in special long registers. | |
684 | ||
685 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP | |
686 | mode. */ | |
ff9940b0 RE |
687 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
688 | (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ | |
689 | && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ | |
35d965d5 RS |
690 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
691 | ||
692 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
693 | This is TRUE for ARM regs since they can hold anything, and TRUE for FPU | |
694 | regs holding FP. */ | |
ff9940b0 RE |
695 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
696 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
697 | ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
698 | || REGNO == ARG_POINTER_REGNUM \ | |
699 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) | |
35d965d5 RS |
700 | |
701 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
702 | when one has mode MODE1 and one has mode MODE2. | |
703 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
704 | for any hard reg, then this must be 0 for correct output. */ | |
705 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
3967692c | 706 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) |
35d965d5 RS |
707 | |
708 | /* Specify the registers used for certain standard purposes. | |
709 | The values of these macros are register numbers. */ | |
710 | ||
711 | /* Define this if the program counter is overloaded on a register. */ | |
712 | #define PC_REGNUM 15 | |
713 | ||
714 | /* Register to use for pushing function arguments. */ | |
715 | #define STACK_POINTER_REGNUM 13 | |
716 | ||
717 | /* Base register for access to local variables of the function. */ | |
ff9940b0 RE |
718 | #define FRAME_POINTER_REGNUM 25 |
719 | ||
720 | /* Define this to be where the real frame pointer is if it is not possible to | |
721 | work out the offset between the frame pointer and the automatic variables | |
722 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
723 | should point to a special register that we will make sure is eliminated. */ | |
724 | #define HARD_FRAME_POINTER_REGNUM 11 | |
35d965d5 RS |
725 | |
726 | /* Value should be nonzero if functions must have frame pointers. | |
727 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
728 | via the stack pointer) in functions that seem suitable. |
729 | If we have to have a frame pointer we might as well make use of it. | |
730 | APCS says that the frame pointer does not need to be pushed in leaf | |
731 | functions. */ | |
688743e7 RE |
732 | #define FRAME_POINTER_REQUIRED \ |
733 | (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) | |
35d965d5 RS |
734 | |
735 | /* Base register for access to arguments of the function. */ | |
ff9940b0 | 736 | #define ARG_POINTER_REGNUM 26 |
35d965d5 RS |
737 | |
738 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain | |
739 | as an invisible last argument (possible since varargs don't exist in | |
740 | Pascal), so the following is not true. */ | |
741 | #define STATIC_CHAIN_REGNUM 8 | |
742 | ||
743 | /* Register in which address to store a structure value | |
744 | is passed to a function. */ | |
745 | #define STRUCT_VALUE_REGNUM 0 | |
746 | ||
ff9940b0 RE |
747 | /* Internal, so that we don't need to refer to a raw number */ |
748 | #define CC_REGNUM 24 | |
749 | ||
35d965d5 | 750 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
751 | since no saving is required (though calls clobber it) and it never contains |
752 | function parameters. It is quite good to use lr since other calls may | |
753 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
754 | least likely to contain a function parameter; in addition results are | |
755 | returned in r0. | |
756 | */ | |
35d965d5 RS |
757 | #define REG_ALLOC_ORDER \ |
758 | { \ | |
ff9940b0 | 759 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
35d965d5 | 760 | 6, 7, 8, 10, 9, 11, 13, 15, \ |
ff9940b0 RE |
761 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
762 | 24, 25 \ | |
35d965d5 RS |
763 | } |
764 | \f | |
765 | /* Register and constant classes. */ | |
766 | ||
767 | /* Register classes: all ARM regs or all FPU regs---simple! */ | |
768 | enum reg_class | |
769 | { | |
770 | NO_REGS, | |
771 | FPU_REGS, | |
772 | GENERAL_REGS, | |
773 | ALL_REGS, | |
774 | LIM_REG_CLASSES | |
775 | }; | |
776 | ||
777 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
778 | ||
779 | /* Give names of register classes as strings for dump file. */ | |
780 | #define REG_CLASS_NAMES \ | |
781 | { \ | |
782 | "NO_REGS", \ | |
783 | "FPU_REGS", \ | |
784 | "GENERAL_REGS", \ | |
785 | "ALL_REGS", \ | |
786 | } | |
787 | ||
788 | /* Define which registers fit in which classes. | |
789 | This is an initializer for a vector of HARD_REG_SET | |
790 | of length N_REG_CLASSES. */ | |
791 | #define REG_CLASS_CONTENTS \ | |
792 | { \ | |
ff9940b0 RE |
793 | 0x0000000, /* NO_REGS */ \ |
794 | 0x0FF0000, /* FPU_REGS */ \ | |
795 | 0x200FFFF, /* GENERAL_REGS */ \ | |
796 | 0x2FFFFFF /* ALL_REGS */ \ | |
35d965d5 RS |
797 | } |
798 | ||
799 | /* The same information, inverted: | |
800 | Return the class number of the smallest class containing | |
801 | reg number REGNO. This could be a conditional expression | |
802 | or could index an array. */ | |
ff9940b0 RE |
803 | #define REGNO_REG_CLASS(REGNO) \ |
804 | (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
805 | || REGNO == ARG_POINTER_REGNUM) \ | |
806 | ? GENERAL_REGS : (REGNO) == CC_REGNUM \ | |
807 | ? NO_REGS : FPU_REGS) | |
35d965d5 RS |
808 | |
809 | /* The class value for index registers, and the one for base regs. */ | |
810 | #define INDEX_REG_CLASS GENERAL_REGS | |
811 | #define BASE_REG_CLASS GENERAL_REGS | |
812 | ||
813 | /* Get reg_class from a letter such as appears in the machine description. | |
814 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ | |
815 | #define REG_CLASS_FROM_LETTER(C) \ | |
816 | ((C)=='f' ? FPU_REGS : NO_REGS) | |
817 | ||
818 | /* The letters I, J, K, L and M in a register constraint string | |
819 | can be used to stand for particular ranges of immediate operands. | |
820 | This macro defines what the ranges are. | |
821 | C is the letter, and VALUE is a constant value. | |
822 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 823 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 824 | J: valid indexing constants. |
aef1764c | 825 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
826 | L: -value ok in rhs argument of data operand. |
827 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
aef1764c RE |
828 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
829 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ | |
830 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
831 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
832 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
833 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
834 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
835 | : 0) | |
ff9940b0 RE |
836 | |
837 | /* For the ARM, `Q' means that this is a memory operand that is just | |
838 | an offset from a register. | |
839 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
840 | address. This means that the symbol is in the text segment and can be | |
841 | accessed without using a load. */ | |
842 | ||
7a801826 RE |
843 | #define EXTRA_CONSTRAINT(OP, C) \ |
844 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
845 | : (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
846 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
847 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ | |
848 | : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
849 | : 0) | |
ff9940b0 RE |
850 | |
851 | /* Constant letter 'G' for the FPU immediate constants. | |
852 | 'H' means the same constant negated. */ | |
853 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ | |
854 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ | |
855 | : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
35d965d5 RS |
856 | |
857 | /* Given an rtx X being reloaded into a reg required to be | |
858 | in class CLASS, return the class of reg to actually use. | |
859 | In general this is just CLASS; but on some machines | |
860 | in some cases it is preferable to use a more restrictive class. */ | |
861 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) | |
862 | ||
ff9940b0 RE |
863 | /* Return the register class of a scratch register needed to copy IN into |
864 | or out of a register in CLASS in MODE. If it can be done directly, | |
865 | NO_REGS is returned. */ | |
11c1a207 RE |
866 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
867 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
868 | ? GENERAL_REGS : NO_REGS) | |
ff9940b0 | 869 | |
2ce9c1b9 RE |
870 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
871 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
872 | (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \ | |
873 | ? GENERAL_REGS : NO_REGS) | |
874 | ||
35d965d5 RS |
875 | /* Return the maximum number of consecutive registers |
876 | needed to represent mode MODE in a register of class CLASS. | |
877 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
878 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
879 | ((CLASS) == FPU_REGS ? 1 \ | |
880 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
881 | ||
ff9940b0 | 882 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
35d965d5 RS |
883 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
884 | ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ | |
885 | || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ | |
ff9940b0 | 886 | ? 20 : 2) |
35d965d5 RS |
887 | \f |
888 | /* Stack layout; function entry, exit and calling. */ | |
889 | ||
890 | /* Define this if pushing a word on the stack | |
891 | makes the stack pointer a smaller address. */ | |
892 | #define STACK_GROWS_DOWNWARD 1 | |
893 | ||
894 | /* Define this if the nominal address of the stack frame | |
895 | is at the high-address end of the local variables; | |
896 | that is, each additional local variable allocated | |
897 | goes at a more negative offset in the frame. */ | |
898 | #define FRAME_GROWS_DOWNWARD 1 | |
899 | ||
900 | /* Offset within stack frame to start allocating local variables at. | |
901 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
902 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
903 | of the first local allocated. */ | |
904 | #define STARTING_FRAME_OFFSET 0 | |
905 | ||
906 | /* If we generate an insn to push BYTES bytes, | |
907 | this says how many the stack pointer really advances by. */ | |
908 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) | |
909 | ||
910 | /* Offset of first parameter from the argument pointer register value. */ | |
911 | #define FIRST_PARM_OFFSET(FNDECL) 4 | |
912 | ||
913 | /* Value is the number of byte of arguments automatically | |
914 | popped when returning from a subroutine call. | |
8b109b37 | 915 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
916 | FUNTYPE is the data type of the function (as a tree), |
917 | or for a library call it is an identifier node for the subroutine name. | |
918 | SIZE is the number of bytes of arguments passed on the stack. | |
919 | ||
920 | On the ARM, the caller does not pop any of its arguments that were passed | |
921 | on the stack. */ | |
8b109b37 | 922 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
35d965d5 RS |
923 | |
924 | /* Define how to find the value returned by a function. | |
925 | VALTYPE is the data type of the value (as a tree). | |
926 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
927 | otherwise, FUNC is 0. */ | |
928 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
3ada8e17 DE |
929 | (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \ |
930 | ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ | |
35d965d5 RS |
931 | : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) |
932 | ||
933 | /* Define how to find the value returned by a library function | |
934 | assuming the value has mode MODE. */ | |
935 | #define LIBCALL_VALUE(MODE) \ | |
3ada8e17 DE |
936 | (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \ |
937 | ? gen_rtx (REG, MODE, 16) \ | |
35d965d5 RS |
938 | : gen_rtx (REG, MODE, 0)) |
939 | ||
940 | /* 1 if N is a possible register number for a function value. | |
941 | On the ARM, only r0 and f0 can return results. */ | |
942 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
3ada8e17 | 943 | ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT) |
35d965d5 | 944 | |
11c1a207 RE |
945 | /* How large values are returned */ |
946 | /* A C expression which can inhibit the returning of certain function values | |
947 | in registers, based on the type of value. */ | |
948 | #define RETURN_IN_MEMORY(TYPE) \ | |
949 | (TYPE_MODE ((TYPE)) == BLKmode || \ | |
950 | (AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE)))) | |
951 | ||
952 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
953 | values must be in memory. On the ARM, they need only do so if larger | |
954 | than a word, or if they contain elements offset from zero in the struct. */ | |
955 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
956 | ||
35d965d5 RS |
957 | /* Define where to put the arguments to a function. |
958 | Value is zero to push the argument on the stack, | |
959 | or a hard register in which to store the argument. | |
960 | ||
961 | MODE is the argument's machine mode. | |
962 | TYPE is the data type of the argument (as a tree). | |
963 | This is null for libcalls where that information may | |
964 | not be available. | |
965 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
966 | the preceding args and about the function being called. | |
967 | NAMED is nonzero if this argument is a named parameter | |
968 | (otherwise it is an extra parameter matching an ellipsis). | |
969 | ||
970 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
971 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
972 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
973 | passed in the stack (function_prologue will indeed make it pass in the | |
974 | stack if necessary). */ | |
975 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
976 | ((NAMED) \ | |
977 | ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ | |
978 | : 0) | |
979 | ||
980 | /* For an arg passed partly in registers and partly in memory, | |
981 | this is the number of registers used. | |
982 | For args passed entirely in registers or entirely in memory, zero. */ | |
983 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
984 | ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ | |
985 | ? GET_MODE_SIZE (MODE) \ | |
986 | : int_size_in_bytes (TYPE)) \ | |
987 | ? 4 - (CUM) / 4 : 0) | |
988 | ||
989 | /* A C type for declaring a variable that is used as the first argument of | |
990 | `FUNCTION_ARG' and other related values. For some target machines, the | |
991 | type `int' suffices and can hold the number of bytes of argument so far. | |
992 | ||
993 | On the ARM, this is the number of bytes of arguments scanned so far. */ | |
994 | #define CUMULATIVE_ARGS int | |
995 | ||
996 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
997 | for a call to a function whose data type is FNTYPE. | |
998 | For a library call, FNTYPE is 0. | |
999 | On the ARM, the offset starts at 0. */ | |
2c7ee1a6 | 1000 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
ff9940b0 | 1001 | ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) |
35d965d5 RS |
1002 | |
1003 | /* Update the data in CUM to advance over an argument | |
1004 | of mode MODE and data type TYPE. | |
1005 | (TYPE is null for libcalls where that information may not be available.) */ | |
1006 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1007 | (CUM) += ((MODE) != BLKmode \ | |
1008 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
1009 | : (int_size_in_bytes (TYPE) + 3) & ~3) \ | |
1010 | ||
1011 | /* 1 if N is a possible register number for function argument passing. | |
1012 | On the ARM, r0-r3 are used to pass args. */ | |
1013 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1014 | ((REGNO) >= 0 && (REGNO) <= 3) | |
1015 | ||
1016 | /* Perform any actions needed for a function that is receiving a variable | |
1017 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1018 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1019 | the amount of stack that must be pushed by the prolog to pretend that our | |
1020 | caller pushed it. | |
1021 | ||
1022 | Normally, this macro will push all remaining incoming registers on the | |
1023 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1024 | ||
1025 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1026 | named arg and all anonymous args onto the stack. | |
1027 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1028 | that way. */ | |
1029 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ | |
1030 | { \ | |
1031 | extern int current_function_anonymous_args; \ | |
1032 | current_function_anonymous_args = 1; \ | |
1033 | if ((CUM) < 16) \ | |
1034 | (PRETEND_SIZE) = 16 - (CUM); \ | |
1035 | } | |
1036 | ||
1037 | /* Generate assembly output for the start of a function. */ | |
1038 | #define FUNCTION_PROLOGUE(STREAM, SIZE) \ | |
008cf58a | 1039 | output_func_prologue ((STREAM), (SIZE)) |
35d965d5 RS |
1040 | |
1041 | /* Call the function profiler with a given profile label. The Acorn compiler | |
7a801826 | 1042 | puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr'' |
35d965d5 RS |
1043 | seems like a good idea to stick with cc convention. ``prof'' doesn't seem |
1044 | to mind about this! */ | |
4eda77ec RE |
1045 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
1046 | { \ | |
c383667d | 1047 | fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \ |
4eda77ec RE |
1048 | fprintf(STREAM, "\tbl\tmcount\n"); \ |
1049 | fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ | |
35d965d5 RS |
1050 | } |
1051 | ||
1052 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1053 | the stack pointer does not matter. The value is tested only in | |
1054 | functions that have frame pointers. | |
1055 | No definition is equivalent to always zero. | |
1056 | ||
1057 | On the ARM, the function epilogue recovers the stack pointer from the | |
1058 | frame. */ | |
1059 | #define EXIT_IGNORE_STACK 1 | |
1060 | ||
1061 | /* Generate the assembly code for function exit. */ | |
1062 | #define FUNCTION_EPILOGUE(STREAM, SIZE) \ | |
008cf58a | 1063 | output_func_epilogue ((STREAM), (SIZE)) |
35d965d5 RS |
1064 | |
1065 | /* Determine if the epilogue should be output as RTL. | |
1066 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
ff9940b0 RE |
1067 | #define USE_RETURN_INSN use_return_insn () |
1068 | ||
1069 | /* Definitions for register eliminations. | |
1070 | ||
1071 | This is an array of structures. Each structure initializes one pair | |
1072 | of eliminable registers. The "from" register number is given first, | |
1073 | followed by "to". Eliminations of the same "from" register are listed | |
1074 | in order of preference. | |
1075 | ||
1076 | We have two registers that can be eliminated on the ARM. First, the | |
1077 | arg pointer register can often be eliminated in favor of the stack | |
1078 | pointer register. Secondly, the pseudo frame pointer register can always | |
1079 | be eliminated; it is replaced with either the stack or the real frame | |
1080 | pointer. */ | |
1081 | ||
1082 | #define ELIMINABLE_REGS \ | |
1083 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1084 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1085 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1086 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1087 | ||
1088 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1089 | Frame pointer elimination is automatically handled. | |
1090 | ||
1091 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1092 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 RE |
1093 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
1094 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ | |
1095 | #define CAN_ELIMINATE(FROM, TO) \ | |
1096 | (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) | |
1097 | ||
1098 | /* Define the offset between two registers, one to be eliminated, and the other | |
1099 | its replacement, at the start of a routine. */ | |
1100 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1101 | { \ | |
3967692c | 1102 | int volatile_func = arm_volatile_func (); \ |
ff9940b0 RE |
1103 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ |
1104 | (OFFSET) = 0; \ | |
1105 | else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\ | |
1106 | (OFFSET) = (get_frame_size () + 3 & ~3); \ | |
1107 | else \ | |
1108 | { \ | |
1109 | int regno; \ | |
1110 | int offset = 12; \ | |
008cf58a | 1111 | int saved_hard_reg = 0; \ |
ff9940b0 | 1112 | \ |
3967692c RE |
1113 | if (! volatile_func) \ |
1114 | { \ | |
1115 | for (regno = 0; regno <= 10; regno++) \ | |
1116 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1117 | saved_hard_reg = 1, offset += 4; \ | |
1118 | for (regno = 16; regno <=23; regno++) \ | |
1119 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1120 | offset += 12; \ | |
1121 | } \ | |
ff9940b0 RE |
1122 | if ((FROM) == FRAME_POINTER_REGNUM) \ |
1123 | (OFFSET) = -offset; \ | |
1124 | else \ | |
1125 | { \ | |
bd4d60ce | 1126 | if (! frame_pointer_needed) \ |
ff9940b0 | 1127 | offset -= 16; \ |
3967692c | 1128 | if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \ |
ff9940b0 RE |
1129 | offset += 4; \ |
1130 | (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \ | |
1131 | } \ | |
1132 | } \ | |
1133 | } | |
35d965d5 | 1134 | |
35d965d5 RS |
1135 | /* Output assembler code for a block containing the constant parts |
1136 | of a trampoline, leaving space for the variable parts. | |
1137 | ||
1138 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1139 | referencing pc adds an offset of 8) the trampoline looks like: | |
1140 | ldr r8, [pc, #0] | |
1141 | ldr pc, [pc] | |
1142 | .word static chain value | |
11c1a207 RE |
1143 | .word function's address |
1144 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
4eda77ec RE |
1145 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1146 | { \ | |
c383667d DE |
1147 | fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \ |
1148 | REGISTER_PREFIX, REGISTER_PREFIX); \ | |
1149 | fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \ | |
1150 | REGISTER_PREFIX, REGISTER_PREFIX); \ | |
4eda77ec RE |
1151 | fprintf ((FILE), "\t.word\t0\n"); \ |
1152 | fprintf ((FILE), "\t.word\t0\n"); \ | |
35d965d5 RS |
1153 | } |
1154 | ||
1155 | /* Length in units of the trampoline for entering a nested function. */ | |
1156 | #define TRAMPOLINE_SIZE 16 | |
1157 | ||
1158 | /* Alignment required for a trampoline in units. */ | |
1159 | #define TRAMPOLINE_ALIGN 4 | |
1160 | ||
1161 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1162 | FNADDR is an RTX for the address of the function's pure code. | |
1163 | CXT is an RTX for the static chain value for the function. */ | |
1164 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1165 | { \ | |
1166 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ | |
1167 | (CXT)); \ | |
1168 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
1169 | (FNADDR)); \ | |
1170 | } | |
1171 | ||
35d965d5 RS |
1172 | \f |
1173 | /* Addressing modes, and classification of registers for them. */ | |
1174 | ||
1175 | #define HAVE_POST_INCREMENT 1 | |
1176 | #define HAVE_PRE_INCREMENT 1 | |
1177 | #define HAVE_POST_DECREMENT 1 | |
1178 | #define HAVE_PRE_DECREMENT 1 | |
1179 | ||
1180 | /* Macros to check register numbers against specific register classes. */ | |
1181 | ||
1182 | /* These assume that REGNO is a hard or pseudo reg number. | |
1183 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1184 | or a pseudo reg currently allocated to a suitable hard reg. | |
1185 | Since they use reg_renumber, they are safe only once reg_renumber | |
1186 | has been allocated, which happens in local-alloc.c. | |
1187 | ||
1188 | On the ARM, don't allow the pc to be used. */ | |
ff9940b0 RE |
1189 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1190 | ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1191 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1192 | || (unsigned) reg_renumber[(REGNO)] < 15 \ | |
1193 | || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ | |
1194 | || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) | |
1195 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
35d965d5 RS |
1196 | REGNO_OK_FOR_BASE_P(REGNO) |
1197 | ||
1198 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 RE |
1199 | Shifts in addresses can't be by a register. */ |
1200 | ||
1201 | #define MAX_REGS_PER_ADDRESS 2 | |
35d965d5 RS |
1202 | |
1203 | /* Recognize any constant value that is a valid address. */ | |
1204 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1205 | |
1206 | #ifdef AOF_ASSEMBLER | |
1207 | ||
1208 | #define CONSTANT_ADDRESS_P(X) \ | |
1209 | (GET_CODE (X) == SYMBOL_REF \ | |
1210 | && CONSTANT_POOL_ADDRESS_P (X)) | |
1211 | ||
1212 | #else | |
35d965d5 | 1213 | |
008cf58a RE |
1214 | #define CONSTANT_ADDRESS_P(X) \ |
1215 | (GET_CODE (X) == SYMBOL_REF \ | |
1216 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
1217 | || (optimize > 0 && SYMBOL_REF_FLAG (X)))) | |
35d965d5 | 1218 | |
11c1a207 RE |
1219 | #endif /* AOF_ASSEMBLER */ |
1220 | ||
35d965d5 RS |
1221 | /* Nonzero if the constant value X is a legitimate general operand. |
1222 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1223 | ||
1224 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1225 | patterns), nice doubles and symbol_refs which refer to the function's | |
1226 | constant pool XXX. */ | |
11c1a207 | 1227 | #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X)) |
ff9940b0 RE |
1228 | |
1229 | /* Symbols in the text segment can be accessed without indirecting via the | |
1230 | constant pool; it may take an extra binary operation, but this is still | |
008cf58a RE |
1231 | faster than indirecting via memory. Don't do this when not optimizing, |
1232 | since we won't be calculating al of the offsets necessary to do this | |
1233 | simplification. */ | |
11c1a207 RE |
1234 | /* This doesn't work with AOF syntax, since the string table may be in |
1235 | a different AREA. */ | |
1236 | #ifndef AOF_ASSEMBLER | |
ff9940b0 RE |
1237 | #define ENCODE_SECTION_INFO(decl) \ |
1238 | { \ | |
008cf58a | 1239 | if (optimize > 0 && TREE_CONSTANT (decl) \ |
ff9940b0 | 1240 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ |
228b6a3f RS |
1241 | { \ |
1242 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ | |
1243 | ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ | |
1244 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ | |
1245 | } \ | |
ff9940b0 | 1246 | } |
11c1a207 | 1247 | #endif |
7a801826 | 1248 | |
35d965d5 RS |
1249 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1250 | and check its validity for a certain class. | |
1251 | We have two alternate definitions for each of them. | |
1252 | The usual definition accepts all pseudo regs; the other rejects | |
1253 | them unless they have been allocated suitable hard regs. | |
1254 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1255 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1256 | |
35d965d5 RS |
1257 | /* Nonzero if X is a hard reg that can be used as a base reg |
1258 | or if it is a pseudo reg. */ | |
ff9940b0 RE |
1259 | #define REG_OK_FOR_BASE_P(X) \ |
1260 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1261 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1262 | ||
35d965d5 RS |
1263 | /* Nonzero if X is a hard reg that can be used as an index |
1264 | or if it is a pseudo reg. */ | |
1265 | #define REG_OK_FOR_INDEX_P(X) \ | |
1266 | REG_OK_FOR_BASE_P(X) | |
ff9940b0 RE |
1267 | |
1268 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1269 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1270 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1271 | ||
35d965d5 | 1272 | #else |
ff9940b0 | 1273 | |
35d965d5 RS |
1274 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
1275 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1276 | |
35d965d5 RS |
1277 | /* Nonzero if X is a hard reg that can be used as an index. */ |
1278 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
ff9940b0 RE |
1279 | |
1280 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1281 | (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ | |
1282 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ | |
1283 | || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ | |
1284 | || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) | |
1285 | ||
35d965d5 RS |
1286 | #endif |
1287 | \f | |
1288 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1289 | that is a valid memory address for an instruction. | |
1290 | The MODE argument is the machine mode for the MEM expression | |
1291 | that wants to use this address. | |
1292 | ||
1293 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1294 | #define BASE_REGISTER_RTX_P(X) \ | |
1295 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
1296 | ||
1297 | #define INDEX_REGISTER_RTX_P(X) \ | |
1298 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
1299 | ||
1300 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
1301 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
1302 | only be small constants. */ | |
ff9940b0 | 1303 | #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
4d01c30f RS |
1304 | do \ |
1305 | { \ | |
008cf58a RE |
1306 | HOST_WIDE_INT range; \ |
1307 | enum rtx_code code = GET_CODE (INDEX); \ | |
4d01c30f | 1308 | \ |
11c1a207 | 1309 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
ff9940b0 RE |
1310 | { \ |
1311 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
1312 | && INTVAL (INDEX) > -1024 \ | |
1313 | && (INTVAL (INDEX) & 3) == 0) \ | |
1314 | goto LABEL; \ | |
1315 | } \ | |
4d01c30f RS |
1316 | else \ |
1317 | { \ | |
ff9940b0 | 1318 | if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ |
4d01c30f | 1319 | goto LABEL; \ |
11c1a207 RE |
1320 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ |
1321 | && (! arm_arch4 || (MODE) != HImode)) \ | |
4d01c30f RS |
1322 | { \ |
1323 | rtx xiop0 = XEXP (INDEX, 0); \ | |
1324 | rtx xiop1 = XEXP (INDEX, 1); \ | |
1325 | if (INDEX_REGISTER_RTX_P (xiop0) \ | |
1326 | && power_of_two_operand (xiop1, SImode)) \ | |
1327 | goto LABEL; \ | |
1328 | if (INDEX_REGISTER_RTX_P (xiop1) \ | |
1329 | && power_of_two_operand (xiop0, SImode)) \ | |
1330 | goto LABEL; \ | |
1331 | } \ | |
ff9940b0 | 1332 | if (GET_MODE_SIZE (MODE) <= 4 \ |
996a5f59 | 1333 | && (code == LSHIFTRT || code == ASHIFTRT \ |
11c1a207 RE |
1334 | || code == ASHIFT || code == ROTATERT) \ |
1335 | && (! arm_arch4 || (MODE) != HImode)) \ | |
ff9940b0 RE |
1336 | { \ |
1337 | rtx op = XEXP (INDEX, 1); \ | |
1338 | if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
1339 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
1340 | && INTVAL (op) <= 31) \ | |
1341 | goto LABEL; \ | |
1342 | } \ | |
11c1a207 | 1343 | range = (MODE) == HImode ? (arm_arch4 ? 256 : 4095) : 4096; \ |
ff9940b0 RE |
1344 | if (code == CONST_INT && INTVAL (INDEX) < range \ |
1345 | && INTVAL (INDEX) > -range) \ | |
1346 | goto LABEL; \ | |
4d01c30f | 1347 | } \ |
35d965d5 RS |
1348 | } while (0) |
1349 | ||
1350 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
1351 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
1352 | the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, | |
1353 | INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. | |
ff9940b0 RE |
1354 | Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol |
1355 | refs must be forced though a static cell to ensure addressability. */ | |
11c1a207 | 1356 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
35d965d5 RS |
1357 | { \ |
1358 | if (BASE_REGISTER_RTX_P (X)) \ | |
1359 | goto LABEL; \ | |
1360 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
1361 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1362 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1363 | goto LABEL; \ | |
11c1a207 RE |
1364 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ |
1365 | && (GET_CODE (X) == LABEL_REF \ | |
1366 | || (GET_CODE (X) == CONST \ | |
1367 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
1368 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
1369 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
1370 | goto LABEL; \ | |
35d965d5 RS |
1371 | else if ((MODE) == TImode) \ |
1372 | ; \ | |
11c1a207 RE |
1373 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ |
1374 | { \ | |
1375 | if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
1376 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1377 | { \ | |
1378 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1379 | if (val == 4 || val == -4 || val == -8) \ | |
1380 | goto LABEL; \ | |
1381 | } \ | |
1382 | } \ | |
35d965d5 RS |
1383 | else if (GET_CODE (X) == PLUS) \ |
1384 | { \ | |
1385 | rtx xop0 = XEXP(X,0); \ | |
1386 | rtx xop1 = XEXP(X,1); \ | |
1387 | \ | |
1388 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1389 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
1390 | else if (BASE_REGISTER_RTX_P (xop1)) \ | |
1391 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
1392 | } \ | |
1393 | else if (GET_CODE (X) == MINUS) \ | |
1394 | { \ | |
1395 | rtx xop0 = XEXP (X,0); \ | |
1396 | rtx xop1 = XEXP (X,1); \ | |
1397 | \ | |
1398 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1399 | GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
1400 | } \ | |
1401 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
1402 | && GET_CODE (X) == SYMBOL_REF \ | |
1403 | && CONSTANT_POOL_ADDRESS_P (X)) \ | |
1404 | goto LABEL; \ | |
1405 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
11c1a207 | 1406 | && (GET_MODE_SIZE (MODE) <= 4) \ |
35d965d5 RS |
1407 | && GET_CODE (XEXP (X, 0)) == REG \ |
1408 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1409 | goto LABEL; \ | |
1410 | } | |
1411 | \f | |
1412 | /* Try machine-dependent ways of modifying an illegitimate address | |
1413 | to be legitimate. If we find one, return the new, valid address. | |
1414 | This macro is used in only one place: `memory_address' in explow.c. | |
1415 | ||
1416 | OLDX is the address as it was before break_out_memory_refs was called. | |
1417 | In some cases it is useful to look at this to decide what needs to be done. | |
1418 | ||
1419 | MODE and WIN are passed so that this macro can use | |
1420 | GO_IF_LEGITIMATE_ADDRESS. | |
1421 | ||
1422 | It is always safe for this macro to do nothing. It exists to recognize | |
1423 | opportunities to optimize the output. | |
1424 | ||
1425 | On the ARM, try to convert [REG, #BIGCONST] | |
1426 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
1427 | where VALIDCONST == 0 in case of TImode. */ | |
7a801826 | 1428 | extern struct rtx_def *legitimize_pic_address (); |
3967692c RE |
1429 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1430 | { \ | |
1431 | if (GET_CODE (X) == PLUS) \ | |
1432 | { \ | |
1433 | rtx xop0 = XEXP (X, 0); \ | |
1434 | rtx xop1 = XEXP (X, 1); \ | |
1435 | \ | |
11c1a207 | 1436 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 1437 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 1438 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1439 | xop1 = force_reg (SImode, xop1); \ |
1440 | if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ | |
1441 | { \ | |
1442 | HOST_WIDE_INT n, low_n; \ | |
1443 | rtx base_reg, val; \ | |
1444 | n = INTVAL (xop1); \ | |
1445 | \ | |
11c1a207 | 1446 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
1447 | { \ |
1448 | low_n = n & 0x0f; \ | |
1449 | n &= ~0x0f; \ | |
1450 | if (low_n > 4) \ | |
1451 | { \ | |
1452 | n += 16; \ | |
1453 | low_n -= 16; \ | |
1454 | } \ | |
1455 | } \ | |
1456 | else \ | |
1457 | { \ | |
1458 | low_n = ((MODE) == TImode ? 0 \ | |
1459 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
1460 | n -= low_n; \ | |
1461 | } \ | |
1462 | base_reg = gen_reg_rtx (SImode); \ | |
1463 | val = force_operand (gen_rtx (PLUS, SImode, xop0, \ | |
1464 | GEN_INT (n)), NULL_RTX); \ | |
1465 | emit_move_insn (base_reg, val); \ | |
1466 | (X) = (low_n == 0 ? base_reg \ | |
1467 | : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \ | |
1468 | } \ | |
1469 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
1470 | (X) = gen_rtx (PLUS, SImode, xop0, xop1); \ | |
1471 | } \ | |
1472 | else if (GET_CODE (X) == MINUS) \ | |
1473 | { \ | |
1474 | rtx xop0 = XEXP (X, 0); \ | |
1475 | rtx xop1 = XEXP (X, 1); \ | |
1476 | \ | |
1477 | if (CONSTANT_P (xop0)) \ | |
1478 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 1479 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1480 | xop1 = force_reg (SImode, xop1); \ |
1481 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
1482 | (X) = gen_rtx (MINUS, SImode, xop0, xop1); \ | |
1483 | } \ | |
7a801826 RE |
1484 | if (flag_pic) \ |
1485 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
1486 | if (memory_address_p (MODE, X)) \ |
1487 | goto WIN; \ | |
35d965d5 RS |
1488 | } |
1489 | ||
1490 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1491 | has an effect that depends on the machine mode it is used for. */ | |
1492 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1493 | { \ | |
1494 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ | |
1495 | || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ | |
1496 | goto LABEL; \ | |
1497 | } | |
1498 | \f | |
1499 | /* Specify the machine mode that this machine uses | |
1500 | for the index in the tablejump instruction. */ | |
1501 | #define CASE_VECTOR_MODE SImode | |
1502 | ||
1503 | /* Define this if the tablejump instruction expects the table | |
1504 | to contain offsets from the address of the table. | |
1505 | Do not define this if the table should contain absolute addresses. */ | |
1506 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1507 | ||
1508 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1509 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1510 | ||
1511 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1512 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1513 | ||
ff9940b0 RE |
1514 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
1515 | unsigned is probably best, but may break some code. */ | |
1516 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 1517 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
1518 | #endif |
1519 | ||
1520 | /* Don't cse the address of the function being compiled. */ | |
1521 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
1522 | ||
1523 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
1524 | in one reasonably fast instruction. */ |
1525 | #define MOVE_MAX 4 | |
35d965d5 | 1526 | |
ff9940b0 RE |
1527 | /* Define if operations between registers always perform the operation |
1528 | on the full register even if a narrower mode is specified. */ | |
1529 | #define WORD_REGISTER_OPERATIONS | |
1530 | ||
1531 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1532 | will either zero-extend or sign-extend. The value of this macro should | |
1533 | be the code that says which one of the two operations is implicitly | |
1534 | done, NIL if none. */ | |
9c872872 | 1535 | #define LOAD_EXTEND_OP(MODE) \ |
11c1a207 | 1536 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ |
9c872872 | 1537 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) |
ff9940b0 | 1538 | |
35d965d5 RS |
1539 | /* Define this if zero-extension is slow (more than one real instruction). |
1540 | On the ARM, it is more than one instruction only if not fetching from | |
1541 | memory. */ | |
1542 | /* #define SLOW_ZERO_EXTEND */ | |
1543 | ||
1544 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1545 | #define SLOW_BYTE_ACCESS 0 | |
1546 | ||
1547 | /* Immediate shift counts are truncated by the output routines (or was it | |
1548 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
1549 | that the native compiler puts too large (> 32) immediate shift counts | |
1550 | into a register and shifts by the register, letting the ARM decide what | |
1551 | to do instead of doing that itself. */ | |
ff9940b0 RE |
1552 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
1553 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1554 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
1555 | rotates is modulo 32 used. */ | |
1556 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 1557 | |
35d965d5 RS |
1558 | /* All integers have the same format so truncation is easy. */ |
1559 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
1560 | ||
1561 | /* Calling from registers is a massive pain. */ | |
1562 | #define NO_FUNCTION_CSE 1 | |
1563 | ||
1564 | /* Chars and shorts should be passed as ints. */ | |
1565 | #define PROMOTE_PROTOTYPES 1 | |
1566 | ||
35d965d5 RS |
1567 | /* The machine modes of pointers and functions */ |
1568 | #define Pmode SImode | |
1569 | #define FUNCTION_MODE Pmode | |
1570 | ||
1571 | /* The structure type of the machine dependent info field of insns | |
1572 | No uses for this yet. */ | |
1573 | /* #define INSN_MACHINE_INFO struct machine_info */ | |
1574 | ||
1575 | /* The relative costs of various types of constants. Note that cse.c defines | |
1576 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
ff9940b0 RE |
1577 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
1578 | case CONST_INT: \ | |
1579 | if (const_ok_for_arm (INTVAL (RTX))) \ | |
1580 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1581 | else if (OUTER_CODE == AND \ | |
1582 | && const_ok_for_arm (~INTVAL (RTX))) \ | |
1583 | return -1; \ | |
1584 | else if ((OUTER_CODE == COMPARE \ | |
1585 | || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ | |
1586 | && const_ok_for_arm (-INTVAL (RTX))) \ | |
1587 | return -1; \ | |
1588 | else \ | |
1589 | return 5; \ | |
1590 | case CONST: \ | |
1591 | case LABEL_REF: \ | |
1592 | case SYMBOL_REF: \ | |
1593 | return 6; \ | |
1594 | case CONST_DOUBLE: \ | |
1595 | if (const_double_rtx_ok_for_fpu (RTX)) \ | |
1596 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1597 | else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ | |
1598 | && neg_const_double_rtx_ok_for_fpu (RTX)) \ | |
1599 | return -1; \ | |
1600 | return(7); | |
1601 | ||
3967692c RE |
1602 | #define ARM_FRAME_RTX(X) \ |
1603 | ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
1604 | || (X) == arg_pointer_rtx) | |
1605 | ||
11c1a207 RE |
1606 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1607 | default: \ | |
3967692c | 1608 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
1609 | |
1610 | /* Moves to and from memory are quite expensive */ | |
1611 | #define MEMORY_MOVE_COST(MODE) 10 | |
1612 | ||
3967692c | 1613 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 1614 | the same for practically all of them. So we weight the different types |
3967692c RE |
1615 | of address here in the order (most pref first): |
1616 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
1617 | #define ADDRESS_COST(X) \ | |
1618 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ | |
1619 | || GET_CODE (X) == SYMBOL_REF) \ | |
1620 | ? 0 \ | |
1621 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
1622 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
1623 | ? 10 \ | |
1624 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
1625 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
1626 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
1627 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
1628 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
1629 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
1630 | ? 1 : 0)) \ | |
1631 | : 4))))) | |
1632 | ||
1633 | ||
ff9940b0 RE |
1634 | |
1635 | /* Try to generate sequences that don't involve branches, we can then use | |
1636 | conditional instructions */ | |
1637 | #define BRANCH_COST 4 | |
7a801826 RE |
1638 | |
1639 | /* A C statement to update the variable COST based on the relationship | |
1640 | between INSN that is dependent on DEP through dependence LINK. */ | |
1641 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ | |
1642 | (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST)) | |
1643 | \f | |
1644 | /* Position Independent Code. */ | |
1645 | /* We decide which register to use based on the compilation options and | |
1646 | the assembler in use; this is more general than the APCS restriction of | |
1647 | using sb (r9) all the time. */ | |
1648 | extern int arm_pic_register; | |
1649 | ||
1650 | /* The register number of the register used to address a table of static | |
1651 | data addresses in memory. */ | |
1652 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
1653 | ||
1654 | #define FINALIZE_PIC arm_finalize_pic () | |
1655 | ||
1656 | #define LEGITIMATE_PIC_OPERAND_P(X) (! symbol_mentioned_p (X)) | |
1657 | ||
1658 | ||
35d965d5 | 1659 | \f |
ff9940b0 RE |
1660 | /* Condition code information. */ |
1661 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
1662 | return the mode to be used for the comparison. | |
ddd5a7c1 | 1663 | CCFPEmode should be used with floating inequalities, |
ff9940b0 | 1664 | CCFPmode should be used with floating equalities. |
ddd5a7c1 | 1665 | CC_NOOVmode should be used with SImode integer equalities. |
69fcc21d | 1666 | CC_Zmode should be used if only the Z flag is set correctly |
ff9940b0 RE |
1667 | CCmode should be used otherwise. */ |
1668 | ||
89c7ca52 RE |
1669 | #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \ |
1670 | CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \ | |
1671 | CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \ | |
62dd06ea | 1672 | CC_DGEUmode, CC_DGTUmode, CC_Cmode |
89c7ca52 RE |
1673 | |
1674 | #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \ | |
1675 | "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \ | |
62dd06ea | 1676 | "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C" |
89c7ca52 RE |
1677 | |
1678 | enum machine_mode arm_select_cc_mode (); | |
1679 | #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y)) | |
ff9940b0 | 1680 | |
008cf58a RE |
1681 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
1682 | ||
62dd06ea RE |
1683 | enum rtx_code arm_canonicalize_comparison (); |
1684 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1685 | do \ | |
1686 | { \ | |
1687 | if (GET_CODE (OP1) == CONST_INT \ | |
1688 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
1689 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
1690 | { \ | |
1691 | rtx const_op = OP1; \ | |
1692 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
1693 | } \ | |
1694 | } while (0) | |
1695 | ||
ff9940b0 RE |
1696 | #define STORE_FLAG_VALUE 1 |
1697 | ||
1698 | /* Define the information needed to generate branch insns. This is | |
1699 | stored from the compare operation. Note that we can't use "rtx" here | |
1700 | since it hasn't been defined! */ | |
1701 | ||
1702 | extern struct rtx_def *arm_compare_op0, *arm_compare_op1; | |
1703 | extern int arm_compare_fp; | |
1704 | ||
1705 | /* Define the codes that are matched by predicates in arm.c */ | |
1706 | #define PREDICATE_CODES \ | |
1707 | {"s_register_operand", {SUBREG, REG}}, \ | |
71791e16 | 1708 | {"f_register_operand", {SUBREG, REG}}, \ |
ff9940b0 RE |
1709 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ |
1710 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1711 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
1712 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1713 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
69fcc21d RE |
1714 | {"offsettable_memory_operand", {MEM}}, \ |
1715 | {"alignable_memory_operand", {MEM}}, \ | |
ff9940b0 RE |
1716 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ |
1717 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
3967692c | 1718 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ |
ff9940b0 | 1719 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ |
c383667d | 1720 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ |
ff9940b0 RE |
1721 | {"load_multiple_operation", {PARALLEL}}, \ |
1722 | {"store_multiple_operation", {PARALLEL}}, \ | |
1723 | {"equality_operator", {EQ, NE}}, \ | |
1724 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ | |
1725 | {"const_shift_operand", {CONST_INT}}, \ | |
1726 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
3967692c RE |
1727 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ |
1728 | {"multi_register_push", {PARALLEL}}, \ | |
31e6408a | 1729 | {"cc_register", {REG}}, \ |
89c7ca52 | 1730 | {"dominant_cc_register", {REG}}, |
ff9940b0 | 1731 | |
35d965d5 | 1732 | \f |
35d965d5 | 1733 | |
11c1a207 RE |
1734 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
1735 | load addresses a limited distance around the pc. We do some | |
1736 | special munging to move the constant pool values to the correct | |
1737 | point in the code. */ | |
1738 | #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN)) | |
35d965d5 | 1739 | |
11c1a207 RE |
1740 | /* The pool is empty, since we have moved everything into the code. */ |
1741 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \ | |
1742 | goto JUMPTO | |
35d965d5 RS |
1743 | |
1744 | /* Output an internal label definition. */ | |
1745 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ | |
1746 | do \ | |
1747 | { \ | |
11c1a207 | 1748 | char *s = (char *) alloca (40 + strlen (PREFIX)); \ |
35d965d5 | 1749 | extern int arm_target_label, arm_ccfsm_state; \ |
26563586 | 1750 | extern rtx arm_target_insn; \ |
35d965d5 | 1751 | \ |
ff9940b0 RE |
1752 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ |
1753 | && !strcmp (PREFIX, "L")) \ | |
1754 | { \ | |
1755 | arm_ccfsm_state = 0; \ | |
26563586 | 1756 | arm_target_insn = NULL; \ |
ff9940b0 | 1757 | } \ |
11c1a207 | 1758 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
ff9940b0 | 1759 | arm_asm_output_label (STREAM, s); \ |
35d965d5 RS |
1760 | } while (0) |
1761 | ||
11c1a207 RE |
1762 | /* Output a label definition. */ |
1763 | #define ASM_OUTPUT_LABEL(STREAM,NAME) \ | |
1764 | arm_asm_output_label ((STREAM), (NAME)) | |
35d965d5 RS |
1765 | |
1766 | /* Output a push or a pop instruction (only used when profiling). */ | |
c383667d DE |
1767 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ |
1768 | fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \ | |
1769 | REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) | |
35d965d5 | 1770 | |
c383667d DE |
1771 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ |
1772 | fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \ | |
1773 | REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) | |
35d965d5 | 1774 | |
35d965d5 RS |
1775 | /* Target characters. */ |
1776 | #define TARGET_BELL 007 | |
1777 | #define TARGET_BS 010 | |
1778 | #define TARGET_TAB 011 | |
1779 | #define TARGET_NEWLINE 012 | |
1780 | #define TARGET_VT 013 | |
1781 | #define TARGET_FF 014 | |
1782 | #define TARGET_CR 015 | |
1783 | \f | |
35d965d5 RS |
1784 | /* Only perform branch elimination (by making instructions conditional) if |
1785 | we're optimising. Otherwise it's of no use anyway. */ | |
1786 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
1787 | if (optimize) \ | |
1788 | final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
1789 | ||
7bc7696c RE |
1790 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
1791 | ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') | |
1792 | /* Output an operand of an instruction. */ | |
35d965d5 | 1793 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
1794 | arm_print_operand (STREAM, X, CODE) |
1795 | ||
1796 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
1797 | (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ | |
1798 | : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \ | |
1799 | (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1800 | ? ((~ (HOST_WIDE_INT) 0) \ | |
1801 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
1802 | : 0)))) | |
35d965d5 RS |
1803 | |
1804 | /* Output the address of an operand. */ | |
1805 | #define PRINT_OPERAND_ADDRESS(STREAM,X) \ | |
1806 | { \ | |
1807 | int is_minus = GET_CODE (X) == MINUS; \ | |
1808 | \ | |
1809 | if (GET_CODE (X) == REG) \ | |
c383667d | 1810 | fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \ |
4eda77ec | 1811 | reg_names[REGNO (X)]); \ |
35d965d5 RS |
1812 | else if (GET_CODE (X) == PLUS || is_minus) \ |
1813 | { \ | |
1814 | rtx base = XEXP (X, 0); \ | |
1815 | rtx index = XEXP (X, 1); \ | |
1816 | char *base_reg_name; \ | |
7bc7696c | 1817 | HOST_WIDE_INT offset = 0; \ |
35d965d5 RS |
1818 | if (GET_CODE (base) != REG) \ |
1819 | { \ | |
1820 | /* Ensure that BASE is a register (one of them must be). */ \ | |
1821 | rtx temp = base; \ | |
1822 | base = index; \ | |
1823 | index = temp; \ | |
1824 | } \ | |
1825 | base_reg_name = reg_names[REGNO (base)]; \ | |
1826 | switch (GET_CODE (index)) \ | |
1827 | { \ | |
1828 | case CONST_INT: \ | |
1829 | offset = INTVAL (index); \ | |
1830 | if (is_minus) \ | |
1831 | offset = -offset; \ | |
c383667d | 1832 | fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \ |
4eda77ec | 1833 | base_reg_name, offset); \ |
35d965d5 RS |
1834 | break; \ |
1835 | \ | |
1836 | case REG: \ | |
c383667d | 1837 | fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \ |
4eda77ec | 1838 | base_reg_name, is_minus ? "-" : "", \ |
c383667d | 1839 | REGISTER_PREFIX, reg_names[REGNO (index)] ); \ |
35d965d5 RS |
1840 | break; \ |
1841 | \ | |
1842 | case MULT: \ | |
ff9940b0 RE |
1843 | case ASHIFTRT: \ |
1844 | case LSHIFTRT: \ | |
1845 | case ASHIFT: \ | |
ff9940b0 RE |
1846 | case ROTATERT: \ |
1847 | { \ | |
c383667d DE |
1848 | fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \ |
1849 | base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\ | |
7bc7696c RE |
1850 | reg_names[REGNO (XEXP (index, 0))]); \ |
1851 | arm_print_operand (STREAM, index, 'S'); \ | |
1852 | fputs ("]", STREAM); \ | |
ff9940b0 RE |
1853 | break; \ |
1854 | } \ | |
35d965d5 RS |
1855 | \ |
1856 | default: \ | |
1857 | abort(); \ | |
1858 | } \ | |
1859 | } \ | |
1860 | else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ | |
1861 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ | |
1862 | { \ | |
1863 | extern int output_memory_reference_mode; \ | |
1864 | \ | |
1865 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
1866 | abort (); \ | |
1867 | \ | |
1868 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
c383667d | 1869 | fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \ |
4eda77ec | 1870 | reg_names[REGNO (XEXP (X, 0))], \ |
35d965d5 RS |
1871 | GET_CODE (X) == PRE_DEC ? "-" : "", \ |
1872 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
1873 | else \ | |
c383667d | 1874 | fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \ |
4eda77ec | 1875 | reg_names[REGNO (XEXP (X, 0))], \ |
35d965d5 RS |
1876 | GET_CODE (X) == POST_DEC ? "-" : "", \ |
1877 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
1878 | } \ | |
1879 | else output_addr_const(STREAM, X); \ | |
1880 | } | |
62dd06ea | 1881 | |
7a801826 RE |
1882 | /* Handles PIC addr specially */ |
1883 | #define OUTPUT_INT_ADDR_CONST(STREAM,X) \ | |
1884 | { \ | |
1885 | if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \ | |
1886 | { \ | |
1887 | output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \ | |
1888 | fputs(" - (", STREAM); \ | |
1889 | output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \ | |
1890 | fputs(")", STREAM); \ | |
1891 | } \ | |
1892 | else output_addr_const(STREAM, X); \ | |
1893 | } | |
1894 | ||
62dd06ea RE |
1895 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
1896 | Used for C++ multiple inheritance. */ | |
1897 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ | |
1898 | do { \ | |
1899 | int mi_delta = (DELTA); \ | |
1900 | char *mi_op = mi_delta < 0 ? "sub" : "add"; \ | |
1901 | int shift = 0; \ | |
821581e4 DE |
1902 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ |
1903 | ? 1 : 0); \ | |
62dd06ea RE |
1904 | if (mi_delta < 0) mi_delta = -mi_delta; \ |
1905 | while (mi_delta != 0) \ | |
1906 | { \ | |
1907 | if (mi_delta & (3 << shift) == 0) \ | |
1908 | shift += 2; \ | |
1909 | else \ | |
1910 | { \ | |
1911 | fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \ | |
821581e4 DE |
1912 | mi_op, REGISTER_PREFIX, reg_names[this_regno], \ |
1913 | REGISTER_PREFIX, reg_names[this_regno], \ | |
62dd06ea | 1914 | mi_delta & (0xff << shift)); \ |
62dd06ea RE |
1915 | mi_delta &= ~(0xff << shift); \ |
1916 | shift += 8; \ | |
1917 | } \ | |
1918 | } \ | |
1919 | fprintf (FILE, "\tldr\t%spc, [%spc, #-4]\n", REGISTER_PREFIX, \ | |
1920 | REGISTER_PREFIX); \ | |
62dd06ea RE |
1921 | ASM_OUTPUT_INT (FILE, XEXP (DECL_RTL (FUNCTION), 0)); \ |
1922 | } while (0) | |
39950dff | 1923 | |
6a5d7526 MS |
1924 | /* A C expression whose value is RTL representing the value of the return |
1925 | address for the frame COUNT steps up from the current frame. */ | |
1926 | ||
1927 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
1928 | ((COUNT == 0) \ | |
1929 | ? gen_rtx (MEM, Pmode, plus_constant (FRAME, -4)) \ | |
1930 | : (rtx) 0) | |
1931 | ||
39950dff MS |
1932 | /* Used to mask out junk bits from the return address, such as |
1933 | processor state, interrupt status, condition codes and the like. */ | |
1934 | #define MASK_RETURN_ADDR \ | |
1935 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
1936 | in 26 bit mode, the condition codes must be masked out of the \ | |
1937 | return address. This does not apply to ARM6 and later processors \ | |
1938 | when running in 32 bit mode. */ \ | |
7a801826 | 1939 | ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff))) |
71791e16 RE |
1940 | |
1941 | /* Prototypes for arm.c -- actually, they aren't since the types aren't | |
1942 | fully defined yet. */ | |
1943 | ||
1944 | void arm_override_options (/* void */); | |
1945 | int use_return_insn (/* void */); | |
1946 | int const_ok_for_arm (/* HOST_WIDE_INT */); | |
1947 | int const_ok_for_op (/* HOST_WIDE_INT, enum rtx_code, | |
1948 | enum machine_mode */); | |
1949 | int arm_split_constant (/* enum rtx_code, enum machine_mode, | |
1950 | HOST_WIDE_INT, struct rtx_def *, | |
1951 | struct rtx_def *, int */); | |
1952 | enum rtx_code arm_canonicalize_comparison (/* enum rtx_code, | |
1953 | struct rtx_def ** */); | |
1954 | int arm_return_in_memory (/* union tree_node * */); | |
1955 | int legitimate_pic_operand_p (/* struct rtx_def * */); | |
1956 | struct rtx_def *legitimize_pic_address (/* struct rtx_def *, | |
1957 | enum machine_mode, | |
1958 | struct rtx_def * */); | |
1959 | int is_pic (/* struct rtx_def * */); | |
1960 | void arm_finalize_pic (/* void */); | |
1961 | int arm_rtx_costs (/* struct rtx_def *, enum rtx_code, enum rtx_code */); | |
1962 | int arm_adjust_code (/* struct rtx_def *, struct rtx_def *, | |
1963 | struct rtx_def *, int */); | |
1964 | int const_double_rtx_ok_for_fpu (/* struct rtx_def * */); | |
1965 | int neg_const_double_rtx_ok_for_fpu (/* struct rtx_def * */); | |
1966 | int s_register_operand (/* struct rtx_def *, enum machine_mode */); | |
1967 | int f_register_operand (/* struct rtx_def *, enum machine_mode */); | |
1968 | int reg_or_int_operand (/* struct rtx_def *, enum machine_mode */); | |
1969 | int reload_memory_operand (/* struct rtx_def *, enum machine_mode */); | |
1970 | int arm_rhs_operand (/* struct rtx_def *, enum machine_mode */); | |
1971 | int arm_rhsm_operand (/* struct rtx_def *, enum machine_mode */); | |
1972 | int arm_add_operand (/* struct rtx_def *, enum machine_mode */); | |
1973 | int arm_not_operand (/* struct rtx_def *, enum machine_mode */); | |
1974 | int offsettable_memory_operand (/* struct rtx_def *, enum machine_mode */); | |
1975 | int alignable_memory_operand (/* struct rtx_def *, enum machine_mode */); | |
1976 | int fpu_rhs_operand (/* struct rtx_def *, enum machine_mode */); | |
1977 | int fpu_add_operand (/* struct rtx_def *, enum machine_mode */); | |
1978 | int power_of_two_operand (/* struct rtx_def *, enum machine_mode */); | |
1979 | int di_operand (/* struct rtx_def *, enum machine_mode */); | |
1980 | int soft_df_operand (/* struct rtx_def *, enum machine_mode */); | |
1981 | int index_operand (/* struct rtx_def *, enum machine_mode */); | |
1982 | int const_shift_operand (/* struct rtx_def *, enum machine_mode */); | |
1983 | int shiftable_operator (/* struct rtx_def *, enum machine_mode */); | |
1984 | int shift_operator (/* struct rtx_def *, enum machine_mode */); | |
1985 | int equality_operator (/* struct rtx_def *, enum machine_mode */); | |
1986 | int minmax_operator (/* struct rtx_def *, enum machine_mode */); | |
1987 | int cc_register (/* struct rtx_def *, enum machine_mode */); | |
1988 | int dominant_cc_register (/* struct rtx_def *, enum machine_mode */); | |
1989 | int symbol_mentioned_p (/* struct rtx_def * */); | |
1990 | int label_mentioned_p (/* struct rtx_def * */); | |
1991 | enum rtx_code minmax_code (/* struct rtx_def * */); | |
1992 | int adjacent_mem_locations (/* struct rtx_def *, struct rtx_def * */); | |
1993 | int load_multiple_operation (/* struct rtx_def *, enum machine_mode */); | |
1994 | int store_multiple_operation (/* struct rtx_def *, enum machine_mode */); | |
1995 | int load_multiple_sequence (/* struct rtx_def **, int, int *, int *, | |
1996 | HOST_WIDE_INT * */); | |
1997 | char *emit_ldm_seq (/* struct rtx_def **, int */); | |
1998 | int store_multiple_sequence (/* struct rtx_def **, int, int *, int *, | |
1999 | HOST_WIDE_INT * */); | |
2000 | char *emit_stm_seq (/* struct rtx_def **, int */); | |
2001 | int multi_register_push (/* struct rtx_def *, enum machine_mode */); | |
2002 | int arm_valid_machine_decl_attribute (/* union tree_node *, union tree_node *, | |
2003 | union tree_node *, | |
2004 | union tree_node * */); | |
2005 | struct rtx_def *arm_gen_load_multiple (/* int, int, struct rtx_def *, | |
2006 | int, int */); | |
2007 | struct rtx_def *arm_gen_store_multiple (/* int, int, struct rtx_def *, | |
2008 | int, int */); | |
2009 | int arm_gen_movstrqi (/* struct rtx_def ** */); | |
2010 | struct rtx_def *gen_rotated_half_load (/* struct rtx_def * */); | |
2011 | enum machine_mode arm_select_cc_mode (/* enum rtx_code, struct rtx_def *, | |
2012 | struct rtx_def * */); | |
2013 | struct rtx_def *gen_compare_reg (/* enum rtx_code, struct rtx_def *, | |
2014 | struct rtx_def * */); | |
2015 | void arm_reload_in_hi (/* struct rtx_def ** */); | |
2016 | void arm_reload_out_hi (/* struct rtx_def ** */); | |
2017 | void arm_reorg (/* struct rtx_def * */); | |
2018 | char *fp_immediate_constant (/* struct rtx_def * */); | |
2019 | void print_multi_reg (/* FILE *, char *, int, int */); | |
2020 | char *output_call (/* struct rtx_def ** */); | |
2021 | char *output_call_mem (/* struct rtx_def ** */); | |
2022 | char *output_mov_long_double_fpu_from_arm (/* struct rtx_def ** */); | |
2023 | char *output_mov_long_double_arm_from_fpu (/* struct rtx_def ** */); | |
2024 | char *output_mov_long_double_arm_from_arm (/* struct rtx_def ** */); | |
2025 | char *output_mov_double_fpu_from_arm (/* struct rtx_def ** */); | |
2026 | char *output_mov_double_arm_from_fpu (/* struct rtx_def ** */); | |
2027 | char *output_mov_double (/* struct rtx_def ** */); | |
2028 | char *output_mov_immediate (/* struct rtx_def ** */); | |
2029 | char *output_add_immediate (/* struct rtx_def ** */); | |
2030 | char *arithmetic_instr (/* struct rtx_def *, int */); | |
2031 | void output_ascii_pseudo_op (/* FILE *, unsigned char *, int */); | |
2032 | char *output_return_instruction (/* struct rtx_def *, int, int */); | |
2033 | int arm_volatile_func (/* void */); | |
2034 | void output_func_prologue (/* FILE *, int */); | |
2035 | void output_func_epilogue (/* FILE *, int */); | |
2036 | void arm_expand_prologue (/* void */); | |
2037 | void arm_print_operand (/* FILE *, struct rtx_def *, int */); | |
2038 | void arm_asm_output_label (/* FILE *, char * */); | |
2039 | void output_lcomm_directive (/* FILE *, char *, int, int */); | |
2040 | void final_prescan_insn (/* struct rtx_def *, struct rtx_def **, int */); | |
2041 | #ifdef AOF_ASSEMBLER | |
2042 | struct rtx_def *aof_pic_entry (/* struct rtx_def * */); | |
2043 | void aof_dump_pic_table (/* FILE * */); | |
2044 | char *aof_text_section (/* void */); | |
2045 | char *aof_data_section (/* void */); | |
2046 | void aof_add_import (/* char * */); | |
2047 | void aof_delete_import (/* char * */); | |
2048 | void aof_dump_imports (/* FILE * */); | |
2049 | #endif |