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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 AO |
2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
3 | 2001 Free Software Foundation, Inc. | |
35d965d5 | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 5 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
7 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
8 | ||
35d965d5 RS |
9 | This file is part of GNU CC. |
10 | ||
11 | GNU CC is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GNU CC is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, |
24 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 25 | |
b355a481 NC |
26 | #ifndef __ARM_H__ |
27 | #define __ARM_H__ | |
28 | ||
7a801826 RE |
29 | #define TARGET_CPU_arm2 0x0000 |
30 | #define TARGET_CPU_arm250 0x0000 | |
31 | #define TARGET_CPU_arm3 0x0000 | |
32 | #define TARGET_CPU_arm6 0x0001 | |
33 | #define TARGET_CPU_arm600 0x0001 | |
34 | #define TARGET_CPU_arm610 0x0002 | |
35 | #define TARGET_CPU_arm7 0x0001 | |
36 | #define TARGET_CPU_arm7m 0x0004 | |
37 | #define TARGET_CPU_arm7dm 0x0004 | |
38 | #define TARGET_CPU_arm7dmi 0x0004 | |
39 | #define TARGET_CPU_arm700 0x0001 | |
40 | #define TARGET_CPU_arm710 0x0002 | |
41 | #define TARGET_CPU_arm7100 0x0002 | |
42 | #define TARGET_CPU_arm7500 0x0002 | |
43 | #define TARGET_CPU_arm7500fe 0x1001 | |
44 | #define TARGET_CPU_arm7tdmi 0x0008 | |
45 | #define TARGET_CPU_arm8 0x0010 | |
46 | #define TARGET_CPU_arm810 0x0020 | |
47 | #define TARGET_CPU_strongarm 0x0040 | |
48 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 49 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
50 | #define TARGET_CPU_arm9 0x0080 |
51 | #define TARGET_CPU_arm9tdmi 0x0080 | |
d19fb8e3 | 52 | #define TARGET_CPU_xscale 0x0100 |
82e9d970 | 53 | /* Configure didn't specify. */ |
7a801826 | 54 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 55 | |
d5b7b3ae | 56 | typedef enum arm_cond_code |
89c7ca52 RE |
57 | { |
58 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
59 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
60 | } |
61 | arm_cc; | |
6cfc7210 | 62 | |
d5b7b3ae | 63 | extern arm_cc arm_current_cc; |
cd2b33d0 | 64 | extern const char * arm_condition_codes[]; |
ff9940b0 | 65 | |
d5b7b3ae | 66 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 67 | |
6cfc7210 NC |
68 | extern int arm_target_label; |
69 | extern int arm_ccfsm_state; | |
70 | extern struct rtx_def * arm_target_insn; | |
6cfc7210 NC |
71 | /* Run-time compilation parameters selecting different hardware subsets. */ |
72 | extern int target_flags; | |
73 | /* The floating point instruction architecture, can be 2 or 3 */ | |
74 | extern const char * target_fp_name; | |
d5b7b3ae RE |
75 | /* Define the information needed to generate branch insns. This is |
76 | stored from the compare operation. Note that we can't use "rtx" here | |
77 | since it hasn't been defined! */ | |
78 | extern struct rtx_def * arm_compare_op0; | |
79 | extern struct rtx_def * arm_compare_op1; | |
80 | /* The label of the current constant pool. */ | |
81 | extern struct rtx_def * pool_vector_label; | |
82 | /* Set to 1 when a return insn is output, this means that the epilogue | |
83 | is not needed. */ | |
84 | extern int return_used_this_function; | |
85 | /* Nonzero if the prologue must setup `fp'. */ | |
86 | extern int current_function_anonymous_args; | |
35d965d5 | 87 | \f |
7a801826 RE |
88 | /* Just in case configure has failed to define anything. */ |
89 | #ifndef TARGET_CPU_DEFAULT | |
90 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
91 | #endif | |
92 | ||
93 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
70f24e49 | 94 | override it. If it doesn't, then default to an ARM6. */ |
7a801826 RE |
95 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic |
96 | #undef TARGET_CPU_DEFAULT | |
70f24e49 | 97 | |
7a801826 RE |
98 | #ifdef SUBTARGET_CPU_DEFAULT |
99 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
100 | #else | |
101 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
102 | #endif | |
103 | #endif | |
104 | ||
105 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
106 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
107 | #else | |
18543a22 | 108 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
109 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
110 | #else | |
111 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
112 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
113 | #else | |
70f24e49 | 114 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi |
7a801826 RE |
115 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
116 | #else | |
dc60a41b | 117 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 |
7a801826 RE |
118 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" |
119 | #else | |
d19fb8e3 NC |
120 | #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale |
121 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" | |
122 | #else | |
7a801826 RE |
123 | Unrecognized value in TARGET_CPU_DEFAULT. |
124 | #endif | |
125 | #endif | |
126 | #endif | |
127 | #endif | |
128 | #endif | |
d19fb8e3 | 129 | #endif |
7a801826 | 130 | |
ff9940b0 | 131 | #ifndef CPP_PREDEFINES |
2b57e919 | 132 | #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm" |
ff9940b0 | 133 | #endif |
35d965d5 | 134 | |
38fc909b RE |
135 | #define CPP_SPEC "\ |
136 | %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \ | |
6dcd26ea | 137 | %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)" |
d5b7b3ae | 138 | |
75d8aea7 | 139 | #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}" |
7a801826 | 140 | |
71791e16 RE |
141 | /* Set the architecture define -- if -march= is set, then it overrides |
142 | the -mcpu= setting. */ | |
7a801826 | 143 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
144 | %{march=arm2:-D__ARM_ARCH_2__} \ |
145 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
146 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
147 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
148 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
149 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
150 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
151 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
152 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 153 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
154 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
155 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
156 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
157 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
158 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
159 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
160 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
161 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
162 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 163 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
164 | %{march=arm920:-D__ARM_ARCH_4__} \ |
165 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 166 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
167 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
168 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 169 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
170 | %{march=xscale:-D__ARM_ARCH_5TE__} \ |
171 | %{march=xscale:-D__XSCALE__} \ | |
71791e16 RE |
172 | %{march=armv2:-D__ARM_ARCH_2__} \ |
173 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
174 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
175 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
176 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
177 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 178 | %{march=armv5:-D__ARM_ARCH_5__} \ |
d5b7b3ae RE |
179 | %{march=armv5t:-D__ARM_ARCH_5T__} \ |
180 | %{march=armv5e:-D__ARM_ARCH_5E__} \ | |
181 | %{march=armv5te:-D__ARM_ARCH_5TE__} \ | |
71791e16 RE |
182 | %{!march=*: \ |
183 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
184 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
185 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
186 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
187 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
188 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
189 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
190 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
191 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 192 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
193 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
194 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
195 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
196 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
197 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
198 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
199 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
200 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
201 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 202 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
203 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
204 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 205 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
206 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
207 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 208 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
209 | %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ |
210 | %{mcpu=xscale:-D__XSCALE__} \ | |
dfa08768 | 211 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 212 | " |
7a801826 RE |
213 | |
214 | /* Define __APCS_26__ if the PC also contains the PSR */ | |
7a801826 RE |
215 | #define CPP_APCS_PC_SPEC "\ |
216 | %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ | |
217 | -D__APCS_32__} \ | |
218 | %{mapcs-26:-D__APCS_26__} \ | |
dfa08768 | 219 | %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \ |
7a801826 RE |
220 | " |
221 | ||
b355a481 | 222 | #ifndef CPP_APCS_PC_DEFAULT_SPEC |
7a801826 | 223 | #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__" |
b355a481 | 224 | #endif |
7a801826 RE |
225 | |
226 | #define CPP_FLOAT_SPEC "\ | |
227 | %{msoft-float:\ | |
228 | %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \ | |
229 | -D__SOFTFP__} \ | |
230 | %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \ | |
231 | " | |
232 | ||
233 | /* Default is hard float, which doesn't define anything */ | |
234 | #define CPP_FLOAT_DEFAULT_SPEC "" | |
235 | ||
236 | #define CPP_ENDIAN_SPEC "\ | |
6cfc7210 NC |
237 | %{mbig-endian: \ |
238 | %{mlittle-endian: \ | |
239 | %e-mbig-endian and -mlittle-endian may not be used together} \ | |
d5b7b3ae RE |
240 | -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\ |
241 | %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \ | |
6cfc7210 | 242 | %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \ |
7a801826 RE |
243 | " |
244 | ||
d5b7b3ae RE |
245 | /* Default is little endian. */ |
246 | #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}" | |
7a801826 | 247 | |
6dcd26ea RE |
248 | /* Add a define for interworking. Needed when building libgcc.a. |
249 | This must define __THUMB_INTERWORK__ to the pre-processor if | |
250 | interworking is enabled by default. */ | |
251 | #ifndef CPP_INTERWORK_DEFAULT_SPEC | |
252 | #define CPP_INTERWORK_DEFAULT_SPEC "" | |
253 | #endif | |
254 | ||
255 | #define CPP_INTERWORK_SPEC " \ | |
256 | %{mthumb-interwork: \ | |
257 | %{mno-thumb-interwork: %eIncompatible interworking options} \ | |
258 | -D__THUMB_INTERWORK__} \ | |
259 | %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \ | |
260 | " | |
261 | ||
dfa08768 | 262 | #define CC1_SPEC "" |
7a801826 RE |
263 | |
264 | /* This macro defines names of additional specifications to put in the specs | |
265 | that can be used in various specifications like CC1_SPEC. Its definition | |
266 | is an initializer with a subgrouping for each command option. | |
267 | ||
268 | Each subgrouping contains a string constant, that defines the | |
269 | specification name, and a string constant that used by the GNU CC driver | |
270 | program. | |
271 | ||
272 | Do not define this macro if it does not need to do anything. */ | |
273 | #define EXTRA_SPECS \ | |
274 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
275 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
276 | { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \ | |
277 | { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \ | |
278 | { "cpp_float", CPP_FLOAT_SPEC }, \ | |
279 | { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ | |
280 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
281 | { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ | |
d5b7b3ae | 282 | { "cpp_isa", CPP_ISA_SPEC }, \ |
6dcd26ea RE |
283 | { "cpp_interwork", CPP_INTERWORK_SPEC }, \ |
284 | { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \ | |
38fc909b | 285 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
286 | SUBTARGET_EXTRA_SPECS |
287 | ||
914a3b8c | 288 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 289 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
290 | #endif |
291 | ||
6cfc7210 | 292 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 293 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 294 | #endif |
35d965d5 RS |
295 | \f |
296 | /* Run-time Target Specification. */ | |
ff9940b0 | 297 | #ifndef TARGET_VERSION |
6cfc7210 | 298 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 299 | #endif |
35d965d5 | 300 | |
35d965d5 RS |
301 | /* Nonzero if the function prologue (and epilogue) should obey |
302 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 303 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
304 | |
305 | /* Nonzero if the function prologue should output the function name to enable | |
306 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
307 | unused on RISCiX). Specifying this flag also enables |
308 | -fno-omit-frame-pointer. | |
35d965d5 | 309 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 310 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
311 | |
312 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
313 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 314 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 315 | |
11c1a207 RE |
316 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
317 | that assume restoration of the condition flags when returning from a | |
318 | branch and link (ie a function). */ | |
6cfc7210 | 319 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 320 | |
dfa08768 RE |
321 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
322 | ||
11c1a207 RE |
323 | /* Nonzero if stack checking should be performed on entry to each function |
324 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 325 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
326 | |
327 | /* Nonzero if floating point parameters should be passed to functions in | |
328 | floating point registers. */ | |
6cfc7210 | 329 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
330 | |
331 | /* Nonzero if re-entrant, position independent code should be generated. | |
332 | This is equivalent to -fpic. */ | |
6cfc7210 | 333 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 334 | |
5f1e6755 NC |
335 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
336 | be loaded using either LDRH or LDRB instructions. */ | |
337 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
338 | |
339 | /* Nonzero if all floating point instructions are missing (and there is no | |
340 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 341 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
342 | |
343 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 344 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
345 | |
346 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 347 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 348 | |
ddee6aba RE |
349 | /* Nonzero if we should have little-endian words even when compiling for |
350 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 351 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 352 | |
f5a1b0d2 | 353 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 354 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 355 | |
c11145f6 | 356 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 357 | function tries to return. */ |
6cfc7210 | 358 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 359 | |
ed0e6530 | 360 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 361 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 362 | |
b020fd92 NC |
363 | /* Nonzero if all call instructions should be indirect. */ |
364 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
d5b7b3ae RE |
365 | |
366 | /* Nonzero means that the target ISA is the THUMB, not the ARM. */ | |
367 | #define ARM_FLAG_THUMB (1 << 16) | |
368 | ||
369 | /* Set if a TPCS style stack frame should be generated, for non-leaf | |
370 | functions, even if they do not need one. */ | |
371 | #define THUMB_FLAG_BACKTRACE (1 << 17) | |
b020fd92 | 372 | |
d5b7b3ae RE |
373 | /* Set if a TPCS style stack frame should be generated, for leaf |
374 | functions, even if they do not need one. */ | |
375 | #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) | |
376 | ||
377 | /* Set if externally visible functions should assume that they | |
378 | might be called in ARM mode, from a non-thumb aware code. */ | |
379 | #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) | |
380 | ||
381 | /* Set if calls via function pointers should assume that their | |
382 | destination is non-Thumb aware. */ | |
383 | #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) | |
384 | ||
385 | #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) | |
11c1a207 RE |
386 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) |
387 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
388 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
389 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
390 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
391 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
5f1e6755 | 392 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
393 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
394 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
395 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
6cfc7210 | 396 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 397 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 398 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 399 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 400 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 401 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
d5b7b3ae RE |
402 | #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) |
403 | #define TARGET_ARM (! TARGET_THUMB) | |
404 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
405 | #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) | |
406 | #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) | |
407 | #define TARGET_BACKTRACE (leaf_function_p () \ | |
408 | ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ | |
409 | : (target_flags & THUMB_FLAG_BACKTRACE)) | |
3ada8e17 DE |
410 | |
411 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. | |
412 | Bit 31 is reserved. See riscix.h. */ | |
413 | #ifndef SUBTARGET_SWITCHES | |
414 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
415 | #endif |
416 | ||
047142d3 PT |
417 | #define TARGET_SWITCHES \ |
418 | { \ | |
419 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
420 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
421 | N_("Generate APCS conformant stack frames") }, \ | |
422 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
423 | {"poke-function-name", ARM_FLAG_POKE, \ | |
424 | N_("Store function names in object code") }, \ | |
425 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
426 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
427 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
b605cfa8 | 428 | N_("Use the 32-bit version of the APCS") }, \ |
047142d3 | 429 | {"apcs-26", -ARM_FLAG_APCS_32, \ |
b605cfa8 | 430 | N_("Use the 26-bit version of the APCS") }, \ |
047142d3 PT |
431 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ |
432 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
433 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
434 | N_("Pass FP arguments in FP registers") }, \ | |
435 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
436 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
437 | N_("Generate re-entrant, PIC code") }, \ | |
438 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
439 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ | |
440 | N_("The MMU will trap on unaligned accesses") }, \ | |
441 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
442 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
443 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
444 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
445 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
446 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ | |
447 | N_("Use library calls to perform FP operations") }, \ | |
448 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
449 | N_("Use hardware floating point instructions") }, \ | |
450 | {"big-endian", ARM_FLAG_BIG_END, \ | |
451 | N_("Assume target CPU is configured as big endian") }, \ | |
452 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
453 | N_("Assume target CPU is configured as little endian") }, \ | |
454 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
455 | N_("Assume big endian bytes, little endian words") }, \ | |
456 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
b605cfa8 | 457 | N_("Support calls between Thumb and ARM instruction sets") }, \ |
047142d3 PT |
458 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ |
459 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
460 | N_("Generate a call to abort if a noreturn function returns")}, \ | |
461 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ | |
b605cfa8 | 462 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ |
047142d3 | 463 | N_("Do not move instructions into a function's prologue") }, \ |
b605cfa8 | 464 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ |
047142d3 PT |
465 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ |
466 | N_("Do not load the PIC register in function prologues") }, \ | |
467 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ | |
468 | {"long-calls", ARM_FLAG_LONG_CALLS, \ | |
469 | N_("Generate call insns as indirect calls, if necessary") }, \ | |
470 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ | |
471 | {"thumb", ARM_FLAG_THUMB, \ | |
472 | N_("Compile for the Thumb not the ARM") }, \ | |
473 | {"no-thumb", -ARM_FLAG_THUMB, "" }, \ | |
474 | {"arm", -ARM_FLAG_THUMB, "" }, \ | |
475 | {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ | |
476 | N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ | |
477 | {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ | |
478 | {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ | |
479 | N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ | |
480 | {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ | |
481 | {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
482 | N_("Thumb: Assume non-static functions may be called from ARM code") }, \ | |
483 | {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
484 | "" }, \ | |
485 | {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
486 | N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ | |
487 | {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
488 | "" }, \ | |
489 | SUBTARGET_SWITCHES \ | |
490 | {"", TARGET_DEFAULT, "" } \ | |
35d965d5 RS |
491 | } |
492 | ||
43cffd11 RE |
493 | #define TARGET_OPTIONS \ |
494 | { \ | |
f5a1b0d2 | 495 | {"cpu=", & arm_select[0].string, \ |
047142d3 | 496 | N_("Specify the name of the target CPU") }, \ |
f5a1b0d2 | 497 | {"arch=", & arm_select[1].string, \ |
047142d3 | 498 | N_("Specify the name of the target architecture") }, \ |
f5a1b0d2 NC |
499 | {"tune=", & arm_select[2].string, "" }, \ |
500 | {"fpe=", & target_fp_name, "" }, \ | |
501 | {"fp=", & target_fp_name, \ | |
047142d3 PT |
502 | N_("Specify the version of the floating point emulator") }, \ |
503 | {"structure-size-boundary=", & structure_size_string, \ | |
504 | N_("Specify the minimum bit alignment of structures") }, \ | |
505 | {"pic-register=", & arm_pic_register_string, \ | |
506 | N_("Specify the register to be used for PIC addressing") } \ | |
11c1a207 | 507 | } |
ff9940b0 | 508 | |
62dd06ea RE |
509 | struct arm_cpu_select |
510 | { | |
f9cc092a RE |
511 | const char * string; |
512 | const char * name; | |
513 | const struct processors * processors; | |
62dd06ea RE |
514 | }; |
515 | ||
f5a1b0d2 NC |
516 | /* This is a magic array. If the user specifies a command line switch |
517 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
518 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
519 | extern struct arm_cpu_select arm_select[]; |
520 | ||
11c1a207 RE |
521 | enum prog_mode_type |
522 | { | |
523 | prog_mode26, | |
524 | prog_mode32 | |
525 | }; | |
526 | ||
527 | /* Recast the program mode class to be the prog_mode attribute */ | |
528 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
529 | ||
530 | extern enum prog_mode_type arm_prgmode; | |
531 | ||
532 | /* What sort of floating point unit do we have? Hardware or software. | |
533 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
534 | enum floating_point_type |
535 | { | |
536 | FP_HARD, | |
11c1a207 RE |
537 | FP_SOFT2, |
538 | FP_SOFT3 | |
24f0c1b4 RE |
539 | }; |
540 | ||
541 | /* Recast the floating point class to be the floating point attribute. */ | |
542 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
543 | ||
71791e16 | 544 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
545 | extern enum floating_point_type arm_fpu; |
546 | ||
71791e16 RE |
547 | /* What type of floating point instructions are available */ |
548 | extern enum floating_point_type arm_fpu_arch; | |
549 | ||
18543a22 | 550 | /* Default floating point architecture. Override in sub-target if |
71791e16 RE |
551 | necessary. */ |
552 | #define FP_DEFAULT FP_SOFT2 | |
553 | ||
11c1a207 RE |
554 | /* Nonzero if the processor has a fast multiply insn, and one that does |
555 | a 64-bit multiply of two 32-bit values. */ | |
556 | extern int arm_fast_multiply; | |
557 | ||
71791e16 | 558 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
559 | extern int arm_arch4; |
560 | ||
62b10bbc NC |
561 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
562 | extern int arm_arch5; | |
563 | ||
b15bca31 RE |
564 | /* Nonzero if this chip supports the ARM Architecture 5E extensions */ |
565 | extern int arm_arch5e; | |
566 | ||
f5a1b0d2 NC |
567 | /* Nonzero if this chip can benefit from load scheduling. */ |
568 | extern int arm_ld_sched; | |
569 | ||
0616531f RE |
570 | /* Nonzero if generating thumb code. */ |
571 | extern int thumb_code; | |
572 | ||
f5a1b0d2 NC |
573 | /* Nonzero if this chip is a StrongARM. */ |
574 | extern int arm_is_strong; | |
575 | ||
d19fb8e3 NC |
576 | /* Nonzero if this chip is an XScale. */ |
577 | extern int arm_is_xscale; | |
578 | ||
f5a1b0d2 NC |
579 | /* Nonzero if this chip is a an ARM6 or an ARM7. */ |
580 | extern int arm_is_6_or_7; | |
581 | ||
2ce9c1b9 | 582 | #ifndef TARGET_DEFAULT |
d5b7b3ae | 583 | #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) |
2ce9c1b9 | 584 | #endif |
35d965d5 | 585 | |
11c1a207 RE |
586 | /* The frame pointer register used in gcc has nothing to do with debugging; |
587 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 588 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 589 | |
11c1a207 RE |
590 | #define TARGET_MEM_FUNCTIONS 1 |
591 | ||
592 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
593 | |
594 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
595 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
596 | Subtargets can override these if required. */ |
597 | #ifndef NEED_GOT_RELOC | |
598 | #define NEED_GOT_RELOC 0 | |
599 | #endif | |
600 | #ifndef NEED_PLT_RELOC | |
601 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 602 | #endif |
84306176 PB |
603 | |
604 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
605 | offset. In other words, generate | |
606 | ||
607 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
608 | ||
609 | rather than | |
610 | ||
611 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
612 | ||
613 | The default is true, which matches NetBSD. Subtargets can | |
614 | override this if required. */ | |
615 | #ifndef GOT_PCREL | |
616 | #define GOT_PCREL 1 | |
617 | #endif | |
35d965d5 RS |
618 | \f |
619 | /* Target machine storage Layout. */ | |
620 | ||
ff9940b0 RE |
621 | |
622 | /* Define this macro if it is advisable to hold scalars in registers | |
623 | in a wider mode than that declared by the program. In such cases, | |
624 | the value is constrained to be within the bounds of the declared | |
625 | type, but kept valid in the wider mode. The signedness of the | |
626 | extension may differ from that of the type. */ | |
627 | ||
628 | /* It is far faster to zero extend chars than to sign extend them */ | |
629 | ||
6cfc7210 | 630 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
631 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
632 | && GET_MODE_SIZE (MODE) < 4) \ | |
633 | { \ | |
634 | if (MODE == QImode) \ | |
635 | UNSIGNEDP = 1; \ | |
636 | else if (MODE == HImode) \ | |
5f1e6755 | 637 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 638 | (MODE) = SImode; \ |
ff9940b0 RE |
639 | } |
640 | ||
18543a22 ILT |
641 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
642 | should also be done for outgoing function arguments. */ | |
643 | /* This is required to ensure that push insns always push a word. */ | |
644 | #define PROMOTE_FUNCTION_ARGS | |
645 | ||
ff9940b0 RE |
646 | /* Define for XFmode extended real floating point support. |
647 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
648 | /* For the ARM: | |
649 | I think I have added all the code to make this work. Unfortunately, | |
650 | early releases of the floating point emulation code on RISCiX used a | |
651 | different format for extended precision numbers. On my RISCiX box there | |
652 | is a bug somewhere which causes the machine to lock up when running enquire | |
653 | with long doubles. There is the additional aspect that Norcroft C | |
654 | treats long doubles as doubles and we ought to remain compatible. | |
655 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
656 | to try this someday. */ | |
657 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
658 | ||
659 | /* Disable XFmode patterns in md file */ | |
660 | #define ENABLE_XF_PATTERNS 0 | |
661 | ||
662 | /* Define if you don't want extended real, but do want to use the | |
663 | software floating point emulator for REAL_ARITHMETIC and | |
664 | decimal <-> binary conversion. */ | |
665 | /* See comment above */ | |
666 | #define REAL_ARITHMETIC | |
667 | ||
35d965d5 RS |
668 | /* Define this if most significant bit is lowest numbered |
669 | in instructions that operate on numbered bit-fields. */ | |
670 | #define BITS_BIG_ENDIAN 0 | |
671 | ||
9c872872 | 672 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
673 | Most ARM processors are run in little endian mode, so that is the default. |
674 | If you want to have it run-time selectable, change the definition in a | |
675 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 676 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
677 | |
678 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
679 | numbered. |
680 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
681 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
682 | ||
683 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
684 | on processor pre-defineds when compiling libgcc2.c. */ | |
685 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
686 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
687 | #else | |
688 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
689 | #endif | |
35d965d5 | 690 | |
11c1a207 RE |
691 | /* Define this if most significant word of doubles is the lowest numbered. |
692 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
693 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
694 | ||
b4ac57ab | 695 | /* Number of bits in an addressable storage unit */ |
35d965d5 RS |
696 | #define BITS_PER_UNIT 8 |
697 | ||
698 | #define BITS_PER_WORD 32 | |
699 | ||
700 | #define UNITS_PER_WORD 4 | |
701 | ||
702 | #define POINTER_SIZE 32 | |
703 | ||
704 | #define PARM_BOUNDARY 32 | |
705 | ||
706 | #define STACK_BOUNDARY 32 | |
707 | ||
708 | #define FUNCTION_BOUNDARY 32 | |
709 | ||
92928d71 AO |
710 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
711 | vbit must go into the delta field of pointers to member | |
712 | functions. */ | |
713 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
714 | ||
35d965d5 RS |
715 | #define EMPTY_FIELD_BOUNDARY 32 |
716 | ||
717 | #define BIGGEST_ALIGNMENT 32 | |
718 | ||
ff9940b0 | 719 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
d19fb8e3 NC |
720 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) |
721 | ||
722 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
723 | ((TREE_CODE (EXP) == STRING_CST \ | |
724 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
725 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 726 | |
723ae7c1 NC |
727 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
728 | value set in previous versions of this toolchain was 8, which produces more | |
729 | compact structures. The command line option -mstructure_size_boundary=<n> | |
730 | can be used to change this value. For compatability with the ARM SDK | |
731 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI | |
732 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
733 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
734 | extern int arm_structure_size_boundary; | |
723ae7c1 NC |
735 | |
736 | /* This is the value used to initialise arm_structure_size_boundary. If a | |
737 | particular arm target wants to change the default value it should change | |
738 | the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h | |
739 | for an example of this. */ | |
740 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
741 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 742 | #endif |
2a5307b1 | 743 | |
b355a481 | 744 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 745 | extern const char * structure_size_string; |
b4ac57ab | 746 | |
ff9940b0 RE |
747 | /* Non-zero if move instructions will actually fail to work |
748 | when given unaligned data. */ | |
35d965d5 RS |
749 | #define STRICT_ALIGNMENT 1 |
750 | ||
ff9940b0 RE |
751 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
752 | ||
35d965d5 RS |
753 | \f |
754 | /* Standard register usage. */ | |
755 | ||
756 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
757 | (S - saved over call). | |
758 | ||
759 | r0 * argument word/integer result | |
760 | r1-r3 argument word | |
761 | ||
762 | r4-r8 S register variable | |
763 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
764 | |
765 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
766 | r11 F S (fp) argument pointer |
767 | r12 (ip) temp workspace | |
768 | r13 F S (sp) lower end of current stack frame | |
769 | r14 (lr) link address/workspace | |
770 | r15 F (pc) program counter | |
771 | ||
772 | f0 floating point result | |
773 | f1-f3 floating point scratch | |
774 | ||
775 | f4-f7 S floating point variable | |
776 | ||
ff9940b0 RE |
777 | cc This is NOT a real register, but is used internally |
778 | to represent things that use or set the condition | |
779 | codes. | |
780 | sfp This isn't either. It is used during rtl generation | |
781 | since the offset between the frame pointer and the | |
782 | auto's isn't known until after register allocation. | |
783 | afp Nor this, we only need this because of non-local | |
784 | goto. Without it fp appears to be used and the | |
785 | elimination code won't get rid of sfp. It tracks | |
786 | fp exactly at all times. | |
787 | ||
35d965d5 RS |
788 | *: See CONDITIONAL_REGISTER_USAGE */ |
789 | ||
ff9940b0 RE |
790 | /* The stack backtrace structure is as follows: |
791 | fp points to here: | save code pointer | [fp] | |
792 | | return link value | [fp, #-4] | |
793 | | return sp value | [fp, #-8] | |
794 | | return fp value | [fp, #-12] | |
795 | [| saved r10 value |] | |
796 | [| saved r9 value |] | |
797 | [| saved r8 value |] | |
798 | [| saved r7 value |] | |
799 | [| saved r6 value |] | |
800 | [| saved r5 value |] | |
801 | [| saved r4 value |] | |
802 | [| saved r3 value |] | |
803 | [| saved r2 value |] | |
804 | [| saved r1 value |] | |
805 | [| saved r0 value |] | |
806 | [| saved f7 value |] three words | |
807 | [| saved f6 value |] three words | |
808 | [| saved f5 value |] three words | |
809 | [| saved f4 value |] three words | |
810 | r0-r3 are not normally saved in a C function. */ | |
811 | ||
35d965d5 RS |
812 | /* 1 for registers that have pervasive standard uses |
813 | and are not available for the register allocator. */ | |
814 | #define FIXED_REGISTERS \ | |
815 | { \ | |
816 | 0,0,0,0,0,0,0,0, \ | |
d5b7b3ae | 817 | 0,0,0,0,0,1,0,1, \ |
ff9940b0 RE |
818 | 0,0,0,0,0,0,0,0, \ |
819 | 1,1,1 \ | |
35d965d5 RS |
820 | } |
821 | ||
822 | /* 1 for registers not available across function calls. | |
823 | These must include the FIXED_REGISTERS and also any | |
824 | registers that can be used without being saved. | |
825 | The latter must include the registers where values are returned | |
826 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
827 | Aside from that, you can include as many other registers as you like. |
828 | The CC is not preserved over function calls on the ARM 6, so it is | |
829 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
830 | #define CALL_USED_REGISTERS \ |
831 | { \ | |
832 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 833 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 RE |
834 | 1,1,1,1,0,0,0,0, \ |
835 | 1,1,1 \ | |
35d965d5 RS |
836 | } |
837 | ||
6cc8c0b3 NC |
838 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
839 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
840 | #endif | |
841 | ||
d5b7b3ae RE |
842 | #define CONDITIONAL_REGISTER_USAGE \ |
843 | { \ | |
844 | if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ | |
845 | { \ | |
846 | int regno; \ | |
847 | for (regno = FIRST_ARM_FP_REGNUM; \ | |
848 | regno <= LAST_ARM_FP_REGNUM; ++regno) \ | |
849 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
850 | } \ | |
851 | if (flag_pic) \ | |
852 | { \ | |
853 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
854 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
855 | } \ | |
856 | else if (TARGET_APCS_STACK) \ | |
857 | { \ | |
858 | fixed_regs[10] = 1; \ | |
859 | call_used_regs[10] = 1; \ | |
860 | } \ | |
861 | if (TARGET_APCS_FRAME) \ | |
862 | { \ | |
863 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
864 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
865 | } \ | |
866 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 867 | } |
d5b7b3ae | 868 | |
dd18ae56 NC |
869 | /* These are a couple of extensions to the formats accecpted |
870 | by asm_fprintf: | |
871 | %@ prints out ASM_COMMENT_START | |
872 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
873 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
874 | case '@': \ | |
875 | fputs (ASM_COMMENT_START, FILE); \ | |
876 | break; \ | |
877 | \ | |
878 | case 'r': \ | |
879 | fputs (REGISTER_PREFIX, FILE); \ | |
880 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
881 | break; | |
882 | ||
d5b7b3ae RE |
883 | /* Round X up to the nearest word. */ |
884 | #define ROUND_UP(X) (((X) + 3) & ~3) | |
885 | ||
6cfc7210 NC |
886 | /* Convert fron bytes to ints. */ |
887 | #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
888 | ||
889 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
890 | #define NUM_REGS(MODE) \ | |
891 | NUM_INTS (GET_MODE_SIZE (MODE)) | |
892 | ||
893 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
894 | #define NUM_REGS2(MODE, TYPE) \ | |
d5b7b3ae RE |
895 | NUM_INTS ((MODE) == BLKmode ? \ |
896 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
897 | |
898 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 899 | #define NUM_ARG_REGS 4 |
6cfc7210 NC |
900 | |
901 | /* Return the regiser number of the N'th (integer) argument. */ | |
d5b7b3ae | 902 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 903 | |
64a7723d | 904 | /* RTX for structure returns. NULL means use a hidden first argument. */ |
31448271 | 905 | #define STRUCT_VALUE 0 |
6cfc7210 | 906 | |
d5b7b3ae RE |
907 | /* Specify the registers used for certain standard purposes. |
908 | The values of these macros are register numbers. */ | |
35d965d5 | 909 | |
d5b7b3ae RE |
910 | /* The number of the last argument register. */ |
911 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 912 | |
d5b7b3ae | 913 | /* The number of the last "lo" register (thumb). */ |
6d3d9133 NC |
914 | #define LAST_LO_REGNUM 7 |
915 | ||
916 | /* The register that holds the return address in exception handlers. */ | |
917 | #define EXCEPTION_LR_REGNUM 2 | |
35d965d5 | 918 | |
d5b7b3ae RE |
919 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
920 | as an invisible last argument (possible since varargs don't exist in | |
921 | Pascal), so the following is not true. */ | |
68dfd979 | 922 | #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) |
35d965d5 | 923 | |
d5b7b3ae RE |
924 | /* Define this to be where the real frame pointer is if it is not possible to |
925 | work out the offset between the frame pointer and the automatic variables | |
926 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
927 | should point to a special register that we will make sure is eliminated. | |
928 | ||
929 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
930 | as r11, and GCC belives that it is always possible to use the frame pointer | |
931 | as base register for addressing purposes. (See comments in | |
932 | find_reloads_address()). But - the Thumb does not allow high registers, | |
933 | including r11, to be used as base address registers. Hence our problem. | |
934 | ||
935 | The solution used here, and in the old thumb port is to use r7 instead of | |
936 | r11 as the hard frame pointer and to have special code to generate | |
937 | backtrace structures on the stack (if required to do so via a command line | |
938 | option) using r11. This is the only 'user visable' use of r11 as a frame | |
939 | pointer. */ | |
940 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
941 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 942 | |
b15bca31 RE |
943 | #define HARD_FRAME_POINTER_REGNUM \ |
944 | (TARGET_ARM \ | |
945 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
946 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 947 | |
b15bca31 | 948 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 949 | |
b15bca31 RE |
950 | /* Register to use for pushing function arguments. */ |
951 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
952 | |
953 | /* ARM floating pointer registers. */ | |
954 | #define FIRST_ARM_FP_REGNUM 16 | |
955 | #define LAST_ARM_FP_REGNUM 23 | |
956 | ||
35d965d5 | 957 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
958 | #define FRAME_POINTER_REGNUM 25 |
959 | ||
d5b7b3ae RE |
960 | /* Base register for access to arguments of the function. */ |
961 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 962 | |
d5b7b3ae RE |
963 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ |
964 | #define FIRST_PSEUDO_REGISTER 27 | |
62b10bbc | 965 | |
35d965d5 RS |
966 | /* Value should be nonzero if functions must have frame pointers. |
967 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
968 | via the stack pointer) in functions that seem suitable. |
969 | If we have to have a frame pointer we might as well make use of it. | |
970 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 971 | functions, or simple tail call functions. */ |
d5b7b3ae RE |
972 | #define FRAME_POINTER_REQUIRED \ |
973 | (current_function_has_nonlocal_label \ | |
974 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) | |
35d965d5 | 975 | |
d5b7b3ae RE |
976 | /* Return number of consecutive hard regs needed starting at reg REGNO |
977 | to hold something of mode MODE. | |
978 | This is ordinarily the length in words of a value of mode MODE | |
979 | but can be less for certain modes in special long registers. | |
35d965d5 | 980 | |
d5b7b3ae RE |
981 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP |
982 | mode. */ | |
983 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
984 | ((TARGET_ARM \ | |
985 | && REGNO >= FIRST_ARM_FP_REGNUM \ | |
986 | && REGNO != FRAME_POINTER_REGNUM \ | |
987 | && REGNO != ARG_POINTER_REGNUM) \ | |
988 | ? 1 : NUM_REGS (MODE)) | |
35d965d5 | 989 | |
d5b7b3ae RE |
990 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
991 | This is TRUE for ARM regs since they can hold anything, and TRUE for FPU | |
992 | regs holding FP. | |
993 | For the Thumb we only allow values bigger than SImode in registers 0 - 6, | |
994 | so that there is always a second lo register available to hold the upper | |
995 | part of the value. Probably we ought to ensure that the register is the | |
996 | start of an even numbered register pair. */ | |
997 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
998 | (TARGET_ARM ? \ | |
999 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
1000 | ( REGNO <= LAST_ARM_REGNUM \ | |
1001 | || REGNO == FRAME_POINTER_REGNUM \ | |
1002 | || REGNO == ARG_POINTER_REGNUM \ | |
1003 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ | |
1004 | : \ | |
1005 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
1006 | (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM))) | |
35d965d5 | 1007 | |
d5b7b3ae RE |
1008 | /* Value is 1 if it is a good idea to tie two pseudo registers |
1009 | when one has mode MODE1 and one has mode MODE2. | |
1010 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1011 | for any hard reg, then this must be 0 for correct output. */ | |
1012 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1013 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 1014 | |
35d965d5 | 1015 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1016 | since no saving is required (though calls clobber it) and it never contains |
1017 | function parameters. It is quite good to use lr since other calls may | |
1018 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
1019 | least likely to contain a function parameter; in addition results are | |
d5b7b3ae | 1020 | returned in r0. */ |
ff73fb53 | 1021 | #define REG_ALLOC_ORDER \ |
35d965d5 | 1022 | { \ |
ff73fb53 NC |
1023 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
1024 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 1025 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
ff73fb53 | 1026 | 24, 25, 26 \ |
35d965d5 RS |
1027 | } |
1028 | \f | |
1029 | /* Register and constant classes. */ | |
1030 | ||
d5b7b3ae RE |
1031 | /* Register classes: used to be simple, just all ARM regs or all FPU regs |
1032 | Now that the Thumb is involved it has become more compilcated. */ | |
35d965d5 RS |
1033 | enum reg_class |
1034 | { | |
1035 | NO_REGS, | |
1036 | FPU_REGS, | |
d5b7b3ae RE |
1037 | LO_REGS, |
1038 | STACK_REG, | |
1039 | BASE_REGS, | |
1040 | HI_REGS, | |
1041 | CC_REG, | |
35d965d5 RS |
1042 | GENERAL_REGS, |
1043 | ALL_REGS, | |
1044 | LIM_REG_CLASSES | |
1045 | }; | |
1046 | ||
1047 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1048 | ||
1049 | /* Give names of register classes as strings for dump file. */ | |
1050 | #define REG_CLASS_NAMES \ | |
1051 | { \ | |
1052 | "NO_REGS", \ | |
1053 | "FPU_REGS", \ | |
d5b7b3ae RE |
1054 | "LO_REGS", \ |
1055 | "STACK_REG", \ | |
1056 | "BASE_REGS", \ | |
1057 | "HI_REGS", \ | |
1058 | "CC_REG", \ | |
35d965d5 RS |
1059 | "GENERAL_REGS", \ |
1060 | "ALL_REGS", \ | |
1061 | } | |
1062 | ||
1063 | /* Define which registers fit in which classes. | |
1064 | This is an initializer for a vector of HARD_REG_SET | |
1065 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
1066 | #define REG_CLASS_CONTENTS \ |
1067 | { \ | |
1068 | { 0x0000000 }, /* NO_REGS */ \ | |
1069 | { 0x0FF0000 }, /* FPU_REGS */ \ | |
d5b7b3ae RE |
1070 | { 0x00000FF }, /* LO_REGS */ \ |
1071 | { 0x0002000 }, /* STACK_REG */ \ | |
1072 | { 0x00020FF }, /* BASE_REGS */ \ | |
1073 | { 0x000FF00 }, /* HI_REGS */ \ | |
1074 | { 0x1000000 }, /* CC_REG */ \ | |
aec3cfba NC |
1075 | { 0x200FFFF }, /* GENERAL_REGS */ \ |
1076 | { 0x2FFFFFF } /* ALL_REGS */ \ | |
35d965d5 | 1077 | } |
d5b7b3ae | 1078 | |
35d965d5 RS |
1079 | /* The same information, inverted: |
1080 | Return the class number of the smallest class containing | |
1081 | reg number REGNO. This could be a conditional expression | |
1082 | or could index an array. */ | |
d5b7b3ae | 1083 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1084 | |
1085 | /* The class value for index registers, and the one for base regs. */ | |
d5b7b3ae RE |
1086 | #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
1087 | #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS) | |
1088 | ||
1089 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows | |
1090 | registers explicitly used in the rtl to be used as spill registers | |
1091 | but prevents the compiler from extending the lifetime of these | |
1092 | registers. */ | |
1093 | #define SMALL_REGISTER_CLASSES TARGET_THUMB | |
35d965d5 RS |
1094 | |
1095 | /* Get reg_class from a letter such as appears in the machine description. | |
d5b7b3ae RE |
1096 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the |
1097 | ARM, but several more letters for the Thumb. */ | |
1098 | #define REG_CLASS_FROM_LETTER(C) \ | |
1099 | ( (C) == 'f' ? FPU_REGS \ | |
1100 | : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ | |
1101 | : TARGET_ARM ? NO_REGS \ | |
1102 | : (C) == 'h' ? HI_REGS \ | |
1103 | : (C) == 'b' ? BASE_REGS \ | |
1104 | : (C) == 'k' ? STACK_REG \ | |
1105 | : (C) == 'c' ? CC_REG \ | |
1106 | : NO_REGS) | |
35d965d5 RS |
1107 | |
1108 | /* The letters I, J, K, L and M in a register constraint string | |
1109 | can be used to stand for particular ranges of immediate operands. | |
1110 | This macro defines what the ranges are. | |
1111 | C is the letter, and VALUE is a constant value. | |
1112 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 1113 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 1114 | J: valid indexing constants. |
aef1764c | 1115 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
1116 | L: -value ok in rhs argument of data operand. |
1117 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
d5b7b3ae | 1118 | #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ |
aef1764c RE |
1119 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ |
1120 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
1121 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
1122 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
1123 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
1124 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
1125 | : 0) | |
ff9940b0 | 1126 | |
d5b7b3ae RE |
1127 | #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ |
1128 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ | |
1129 | (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ | |
1130 | (C) == 'K' ? thumb_shiftable_const (VAL) : \ | |
1131 | (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ | |
1132 | (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ | |
1133 | && ((VAL) & 3) == 0) : \ | |
1134 | (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ | |
1135 | (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ | |
1136 | : 0) | |
1137 | ||
1138 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1139 | (TARGET_ARM ? \ | |
1140 | CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) | |
1141 | ||
1142 | /* Constant letter 'G' for the FPU immediate constants. | |
1143 | 'H' means the same constant negated. */ | |
1144 | #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ | |
1145 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ | |
1146 | (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
1147 | ||
1148 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ | |
1149 | (TARGET_ARM ? \ | |
1150 | CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) | |
1151 | ||
ff9940b0 RE |
1152 | /* For the ARM, `Q' means that this is a memory operand that is just |
1153 | an offset from a register. | |
1154 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
1155 | address. This means that the symbol is in the text segment and can be | |
1156 | accessed without using a load. */ | |
1157 | ||
d5b7b3ae RE |
1158 | #define EXTRA_CONSTRAINT_ARM(OP, C) \ |
1159 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ | |
1160 | (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
1161 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
1162 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ | |
1163 | (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
7a801826 | 1164 | : 0) |
ff9940b0 | 1165 | |
d5b7b3ae RE |
1166 | #define EXTRA_CONSTRAINT_THUMB(X, C) \ |
1167 | ((C) == 'Q' ? (GET_CODE (X) == MEM \ | |
1168 | && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) | |
1169 | ||
1170 | #define EXTRA_CONSTRAINT(X, C) \ | |
1171 | (TARGET_ARM ? \ | |
1172 | EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) | |
35d965d5 RS |
1173 | |
1174 | /* Given an rtx X being reloaded into a reg required to be | |
1175 | in class CLASS, return the class of reg to actually use. | |
d5b7b3ae RE |
1176 | In general this is just CLASS, but for the Thumb we prefer |
1177 | a LO_REGS class or a subset. */ | |
1178 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1179 | (TARGET_ARM ? (CLASS) : \ | |
1180 | ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) | |
1181 | ||
1182 | /* Must leave BASE_REGS reloads alone */ | |
1183 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1184 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1185 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1186 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1187 | : NO_REGS)) \ | |
1188 | : NO_REGS) | |
1189 | ||
1190 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1191 | ((CLASS) != LO_REGS \ | |
1192 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1193 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1194 | : NO_REGS)) \ | |
1195 | : NO_REGS) | |
35d965d5 | 1196 | |
ff9940b0 RE |
1197 | /* Return the register class of a scratch register needed to copy IN into |
1198 | or out of a register in CLASS in MODE. If it can be done directly, | |
1199 | NO_REGS is returned. */ | |
d5b7b3ae RE |
1200 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1201 | (TARGET_ARM ? \ | |
1202 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
1203 | ? GENERAL_REGS : NO_REGS) \ | |
1204 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
1205 | ||
2ce9c1b9 | 1206 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae RE |
1207 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1208 | (TARGET_ARM ? \ | |
1209 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ | |
1210 | && (GET_CODE (X) == MEM \ | |
1211 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1212 | && true_regnum (X) == -1))) \ | |
1213 | ? GENERAL_REGS : NO_REGS) \ | |
1214 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
2ce9c1b9 | 1215 | |
6f734908 RE |
1216 | /* Try a machine-dependent way of reloading an illegitimate address |
1217 | operand. If we find one, push the reload and jump to WIN. This | |
1218 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1219 | ||
1220 | For the ARM, we wish to handle large displacements off a base | |
1221 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1222 | This can cut the number of reloads needed. */ |
1223 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1224 | do \ | |
1225 | { \ | |
1226 | if (GET_CODE (X) == PLUS \ | |
1227 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1228 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1229 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1230 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1231 | { \ | |
1232 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1233 | HOST_WIDE_INT low, high; \ | |
1234 | \ | |
1235 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1236 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
1237 | else if (MODE == SImode \ | |
1238 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1239 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1240 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1241 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1242 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1243 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1244 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1245 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1246 | && TARGET_HARD_FLOAT) \ | |
1247 | /* Need to be careful, -1024 is not a valid offset. */ \ | |
1248 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1249 | else \ | |
1250 | break; \ | |
1251 | \ | |
e5951263 NC |
1252 | high = ((((val - low) & HOST_UINT (0xffffffff)) \ |
1253 | ^ HOST_UINT (0x80000000)) \ | |
1254 | - HOST_UINT (0x80000000)); \ | |
d5b7b3ae RE |
1255 | /* Check for overflow or zero */ \ |
1256 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1257 | break; \ | |
1258 | \ | |
1259 | /* Reload the high part into a base reg; leave the low part \ | |
1260 | in the mem. */ \ | |
1261 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1262 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1263 | GEN_INT (high)), \ | |
1264 | GEN_INT (low)); \ | |
df4ae160 | 1265 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
d5b7b3ae RE |
1266 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1267 | OPNUM, TYPE); \ | |
1268 | goto WIN; \ | |
1269 | } \ | |
1270 | } \ | |
62b10bbc | 1271 | while (0) |
6f734908 | 1272 | |
d5b7b3ae RE |
1273 | /* ??? If an HImode FP+large_offset address is converted to an HImode |
1274 | SP+large_offset address, then reload won't know how to fix it. It sees | |
1275 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1276 | register, but the resulting address is still invalid because the offset | |
1277 | is too big. We fix it here instead by reloading the entire address. */ | |
1278 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1279 | cope with the variances between the Thumb's signed and unsigned byte and | |
1280 | halfword load instructions. */ | |
1281 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1282 | { \ | |
1283 | if (GET_CODE (X) == PLUS \ | |
1284 | && GET_MODE_SIZE (MODE) < 4 \ | |
1285 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1286 | && XEXP (X, 0) == stack_pointer_rtx \ | |
1287 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 1288 | && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
1289 | { \ |
1290 | rtx orig_X = X; \ | |
1291 | X = copy_rtx (X); \ | |
df4ae160 | 1292 | push_reload (orig_X, NULL_RTX, &X, NULL, \ |
d5b7b3ae RE |
1293 | BASE_REG_CLASS, \ |
1294 | Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ | |
1295 | goto WIN; \ | |
1296 | } \ | |
1297 | } | |
1298 | ||
1299 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1300 | if (TARGET_ARM) \ | |
1301 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1302 | else \ | |
1303 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
1304 | ||
35d965d5 RS |
1305 | /* Return the maximum number of consecutive registers |
1306 | needed to represent mode MODE in a register of class CLASS. | |
1307 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
1308 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
6cfc7210 | 1309 | ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE)) |
35d965d5 | 1310 | |
ff9940b0 | 1311 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
cf011243 | 1312 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
d5b7b3ae RE |
1313 | (TARGET_ARM ? \ |
1314 | ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ | |
1315 | (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ | |
1316 | : \ | |
1317 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 RS |
1318 | \f |
1319 | /* Stack layout; function entry, exit and calling. */ | |
1320 | ||
1321 | /* Define this if pushing a word on the stack | |
1322 | makes the stack pointer a smaller address. */ | |
1323 | #define STACK_GROWS_DOWNWARD 1 | |
1324 | ||
1325 | /* Define this if the nominal address of the stack frame | |
1326 | is at the high-address end of the local variables; | |
1327 | that is, each additional local variable allocated | |
1328 | goes at a more negative offset in the frame. */ | |
1329 | #define FRAME_GROWS_DOWNWARD 1 | |
1330 | ||
1331 | /* Offset within stack frame to start allocating local variables at. | |
1332 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1333 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1334 | of the first local allocated. */ | |
1335 | #define STARTING_FRAME_OFFSET 0 | |
1336 | ||
1337 | /* If we generate an insn to push BYTES bytes, | |
1338 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae RE |
1339 | /* The push insns do not do this rounding implicitly. |
1340 | So don't define this. */ | |
1341 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ | |
18543a22 ILT |
1342 | |
1343 | /* Define this if the maximum size of all the outgoing args is to be | |
1344 | accumulated and pushed during the prologue. The amount can be | |
1345 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1346 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1347 | |
1348 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1349 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1350 | |
1351 | /* Value is the number of byte of arguments automatically | |
1352 | popped when returning from a subroutine call. | |
8b109b37 | 1353 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1354 | FUNTYPE is the data type of the function (as a tree), |
1355 | or for a library call it is an identifier node for the subroutine name. | |
1356 | SIZE is the number of bytes of arguments passed on the stack. | |
1357 | ||
1358 | On the ARM, the caller does not pop any of its arguments that were passed | |
1359 | on the stack. */ | |
6cfc7210 | 1360 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1361 | |
1362 | /* Define how to find the value returned by a library function | |
1363 | assuming the value has mode MODE. */ | |
1364 | #define LIBCALL_VALUE(MODE) \ | |
d5b7b3ae RE |
1365 | (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1366 | ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ | |
1367 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) | |
35d965d5 | 1368 | |
6cfc7210 NC |
1369 | /* Define how to find the value returned by a function. |
1370 | VALTYPE is the data type of the value (as a tree). | |
1371 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1372 | otherwise, FUNC is 0. */ | |
d5b7b3ae | 1373 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
6cfc7210 NC |
1374 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
1375 | ||
35d965d5 RS |
1376 | /* 1 if N is a possible register number for a function value. |
1377 | On the ARM, only r0 and f0 can return results. */ | |
1378 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
d5b7b3ae RE |
1379 | ((REGNO) == ARG_REGISTER (1) \ |
1380 | || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) | |
35d965d5 | 1381 | |
11c1a207 RE |
1382 | /* How large values are returned */ |
1383 | /* A C expression which can inhibit the returning of certain function values | |
1384 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1385 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1386 | |
1387 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1388 | values must be in memory. On the ARM, they need only do so if larger | |
1389 | than a word, or if they contain elements offset from zero in the struct. */ | |
1390 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1391 | ||
d5b7b3ae RE |
1392 | /* Flags for the call/call_value rtl operations set up by function_arg. */ |
1393 | #define CALL_NORMAL 0x00000000 /* No special processing. */ | |
1394 | #define CALL_LONG 0x00000001 /* Always call indirect. */ | |
1395 | #define CALL_SHORT 0x00000002 /* Never call indirect. */ | |
1396 | ||
6d3d9133 NC |
1397 | /* These bits describe the different types of function supported |
1398 | by the ARM backend. They are exclusive. ie a function cannot be both a | |
1399 | normal function and an interworked function, for example. Knowing the | |
1400 | type of a function is important for determining its prologue and | |
1401 | epilogue sequences. | |
1402 | Note value 7 is currently unassigned. Also note that the interrupt | |
1403 | function types all have bit 2 set, so that they can be tested for easily. | |
1404 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
1405 | machine_function structure is initialised (to zero) func_type will | |
1406 | default to unknown. This will force the first use of arm_current_func_type | |
1407 | to call arm_compute_func_type. */ | |
1408 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1409 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1410 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
1411 | #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ | |
1412 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
1413 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1414 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1415 | ||
1416 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1417 | ||
1418 | /* In addition functions can have several type modifiers, | |
1419 | outlined by these bit masks: */ | |
1420 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1421 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1422 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
1423 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
1424 | ||
1425 | /* Some macros to test these flags. */ | |
1426 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1427 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1428 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1429 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1430 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
1431 | ||
1432 | /* A C structure for machine-specific, per-function data. | |
1433 | This is added to the cfun structure. */ | |
1434 | typedef struct machine_function | |
d5b7b3ae RE |
1435 | { |
1436 | /* Records __builtin_return address. */ | |
1437 | struct rtx_def *ra_rtx; | |
1438 | /* Additionsl stack adjustment in __builtin_eh_throw. */ | |
1439 | struct rtx_def *eh_epilogue_sp_ofs; | |
1440 | /* Records if LR has to be saved for far jumps. */ | |
1441 | int far_jump_used; | |
1442 | /* Records if ARG_POINTER was ever live. */ | |
1443 | int arg_pointer_live; | |
6f7ebcbb NC |
1444 | /* Records if the save of LR has been eliminated. */ |
1445 | int lr_save_eliminated; | |
6d3d9133 NC |
1446 | /* Records the type of the current function. */ |
1447 | unsigned long func_type; | |
1448 | } | |
1449 | machine_function; | |
d5b7b3ae | 1450 | |
82e9d970 PB |
1451 | /* A C type for declaring a variable that is used as the first argument of |
1452 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1453 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1454 | typedef struct | |
1455 | { | |
d5b7b3ae | 1456 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1457 | int nregs; |
d5b7b3ae | 1458 | /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ |
82e9d970 | 1459 | int call_cookie; |
d5b7b3ae | 1460 | } CUMULATIVE_ARGS; |
82e9d970 | 1461 | |
35d965d5 RS |
1462 | /* Define where to put the arguments to a function. |
1463 | Value is zero to push the argument on the stack, | |
1464 | or a hard register in which to store the argument. | |
1465 | ||
1466 | MODE is the argument's machine mode. | |
1467 | TYPE is the data type of the argument (as a tree). | |
1468 | This is null for libcalls where that information may | |
1469 | not be available. | |
1470 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1471 | the preceding args and about the function being called. | |
1472 | NAMED is nonzero if this argument is a named parameter | |
1473 | (otherwise it is an extra parameter matching an ellipsis). | |
1474 | ||
1475 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1476 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1477 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1478 | passed in the stack (function_prologue will indeed make it pass in the | |
1479 | stack if necessary). */ | |
82e9d970 PB |
1480 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1481 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1482 | |
1483 | /* For an arg passed partly in registers and partly in memory, | |
1484 | this is the number of registers used. | |
1485 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1486 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 PB |
1487 | ( NUM_ARG_REGS > (CUM).nregs \ |
1488 | && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \ | |
1489 | ? NUM_ARG_REGS - (CUM).nregs : 0) | |
35d965d5 RS |
1490 | |
1491 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1492 | for a call to a function whose data type is FNTYPE. | |
1493 | For a library call, FNTYPE is 0. | |
1494 | On the ARM, the offset starts at 0. */ | |
82e9d970 PB |
1495 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1496 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) | |
35d965d5 RS |
1497 | |
1498 | /* Update the data in CUM to advance over an argument | |
1499 | of mode MODE and data type TYPE. | |
1500 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1501 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1502 | (CUM).nregs += NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1503 | |
1504 | /* 1 if N is a possible register number for function argument passing. | |
1505 | On the ARM, r0-r3 are used to pass args. */ | |
1506 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1507 | ((REGNO) >= 0 && (REGNO) <= 3) | |
1508 | ||
f99fce0c RE |
1509 | \f |
1510 | /* Tail calling. */ | |
1511 | ||
1512 | /* A C expression that evaluates to true if it is ok to perform a sibling | |
1513 | call to DECL. */ | |
1514 | #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) | |
1515 | ||
35d965d5 RS |
1516 | /* Perform any actions needed for a function that is receiving a variable |
1517 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1518 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1519 | the amount of stack that must be pushed by the prolog to pretend that our | |
1520 | caller pushed it. | |
1521 | ||
1522 | Normally, this macro will push all remaining incoming registers on the | |
1523 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1524 | ||
1525 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1526 | named arg and all anonymous args onto the stack. | |
1527 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1528 | that way. */ | |
6cfc7210 | 1529 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 RS |
1530 | { \ |
1531 | extern int current_function_anonymous_args; \ | |
1532 | current_function_anonymous_args = 1; \ | |
82e9d970 PB |
1533 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1534 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1535 | } |
1536 | ||
1537 | /* Generate assembly output for the start of a function. */ | |
d5b7b3ae RE |
1538 | #define FUNCTION_PROLOGUE(STREAM, SIZE) \ |
1539 | do \ | |
1540 | { \ | |
1541 | if (TARGET_ARM) \ | |
1542 | output_arm_prologue (STREAM, SIZE); \ | |
1543 | else \ | |
1544 | output_thumb_prologue (STREAM); \ | |
1545 | } \ | |
1546 | while (0) | |
35d965d5 | 1547 | |
afef3d7a NC |
1548 | /* If your target environment doesn't prefix user functions with an |
1549 | underscore, you may wish to re-define this to prevent any conflicts. | |
1550 | e.g. AOF may prefix mcount with an underscore. */ | |
1551 | #ifndef ARM_MCOUNT_NAME | |
1552 | #define ARM_MCOUNT_NAME "*mcount" | |
1553 | #endif | |
1554 | ||
1555 | /* Call the function profiler with a given profile label. The Acorn | |
1556 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1557 | On the ARM the full profile code will look like: | |
1558 | .data | |
1559 | LP1 | |
1560 | .word 0 | |
1561 | .text | |
1562 | mov ip, lr | |
1563 | bl mcount | |
1564 | .word LP1 | |
1565 | ||
1566 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1567 | will output the .text section. | |
1568 | ||
1569 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
1570 | ``prof'' doesn't seem to mind about this! */ | |
d5b7b3ae | 1571 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1572 | { \ |
1573 | char temp[20]; \ | |
1574 | rtx sym; \ | |
1575 | \ | |
dd18ae56 | 1576 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1577 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1578 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1579 | fputc ('\n', STREAM); \ | |
1580 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1581 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
1582 | ASM_OUTPUT_INT (STREAM, sym); \ | |
35d965d5 RS |
1583 | } |
1584 | ||
d5b7b3ae RE |
1585 | #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \ |
1586 | { \ | |
1587 | fprintf (STREAM, "\tmov\\tip, lr\n"); \ | |
1588 | fprintf (STREAM, "\tbl\tmcount\n"); \ | |
1589 | fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \ | |
1590 | } | |
1591 | ||
1592 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1593 | if (TARGET_ARM) \ | |
1594 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1595 | else \ | |
1596 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
1597 | ||
35d965d5 RS |
1598 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1599 | the stack pointer does not matter. The value is tested only in | |
1600 | functions that have frame pointers. | |
1601 | No definition is equivalent to always zero. | |
1602 | ||
1603 | On the ARM, the function epilogue recovers the stack pointer from the | |
1604 | frame. */ | |
1605 | #define EXIT_IGNORE_STACK 1 | |
1606 | ||
1607 | /* Generate the assembly code for function exit. */ | |
d5b7b3ae | 1608 | #define FUNCTION_EPILOGUE(STREAM, SIZE) \ |
eb3921e8 | 1609 | output_func_epilogue (SIZE) |
35d965d5 | 1610 | |
c7861455 RE |
1611 | #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) |
1612 | ||
35d965d5 RS |
1613 | /* Determine if the epilogue should be output as RTL. |
1614 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae RE |
1615 | #define USE_RETURN_INSN(ISCOND) \ |
1616 | (TARGET_ARM ? use_return_insn (ISCOND) : 0) | |
ff9940b0 RE |
1617 | |
1618 | /* Definitions for register eliminations. | |
1619 | ||
1620 | This is an array of structures. Each structure initializes one pair | |
1621 | of eliminable registers. The "from" register number is given first, | |
1622 | followed by "to". Eliminations of the same "from" register are listed | |
1623 | in order of preference. | |
1624 | ||
1625 | We have two registers that can be eliminated on the ARM. First, the | |
1626 | arg pointer register can often be eliminated in favor of the stack | |
1627 | pointer register. Secondly, the pseudo frame pointer register can always | |
1628 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae RE |
1629 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
1630 | because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */ | |
ff9940b0 | 1631 | |
d5b7b3ae RE |
1632 | #define ELIMINABLE_REGS \ |
1633 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1634 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1635 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1636 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1637 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1638 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1639 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1640 | |
d5b7b3ae RE |
1641 | /* Given FROM and TO register numbers, say whether this elimination is |
1642 | allowed. Frame pointer elimination is automatically handled. | |
ff9940b0 RE |
1643 | |
1644 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1645 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 | 1646 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
d5b7b3ae RE |
1647 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or |
1648 | ARG_POINTER_REGNUM. */ | |
1649 | #define CAN_ELIMINATE(FROM, TO) \ | |
1650 | (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ | |
1651 | ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ | |
1652 | ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ | |
1653 | ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ | |
1654 | 1) | |
1655 | ||
1656 | /* Define the offset between two registers, one to be eliminated, and the | |
1657 | other its replacement, at the start of a routine. */ | |
1658 | #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
ff9940b0 | 1659 | { \ |
6d3d9133 | 1660 | int volatile_func = IS_VOLATILE (arm_current_func_type ()); \ |
ff9940b0 | 1661 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ |
68dfd979 NC |
1662 | { \ |
1663 | if (! current_function_needs_context || ! frame_pointer_needed) \ | |
1664 | (OFFSET) = 0; \ | |
1665 | else \ | |
1666 | (OFFSET) = 4; \ | |
1667 | } \ | |
18543a22 ILT |
1668 | else if ((FROM) == FRAME_POINTER_REGNUM \ |
1669 | && (TO) == STACK_POINTER_REGNUM) \ | |
9daca635 | 1670 | (OFFSET) = current_function_outgoing_args_size \ |
d5b7b3ae | 1671 | + ROUND_UP (get_frame_size ()); \ |
ff9940b0 RE |
1672 | else \ |
1673 | { \ | |
1674 | int regno; \ | |
1675 | int offset = 12; \ | |
008cf58a | 1676 | int saved_hard_reg = 0; \ |
ff9940b0 | 1677 | \ |
3967692c RE |
1678 | if (! volatile_func) \ |
1679 | { \ | |
1680 | for (regno = 0; regno <= 10; regno++) \ | |
1681 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1682 | saved_hard_reg = 1, offset += 4; \ | |
d5b7b3ae RE |
1683 | if (! TARGET_APCS_FRAME \ |
1684 | && ! frame_pointer_needed \ | |
1685 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \ | |
1686 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \ | |
1687 | saved_hard_reg = 1, offset += 4; \ | |
6ed30148 RE |
1688 | /* PIC register is a fixed reg, so call_used_regs set. */ \ |
1689 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \ | |
1690 | saved_hard_reg = 1, offset += 4; \ | |
d5b7b3ae RE |
1691 | for (regno = FIRST_ARM_FP_REGNUM; \ |
1692 | regno <= LAST_ARM_FP_REGNUM; regno++) \ | |
3967692c RE |
1693 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ |
1694 | offset += 12; \ | |
1695 | } \ | |
ff9940b0 | 1696 | if ((FROM) == FRAME_POINTER_REGNUM) \ |
d5b7b3ae | 1697 | (OFFSET) = - offset; \ |
ff9940b0 RE |
1698 | else \ |
1699 | { \ | |
bd4d60ce | 1700 | if (! frame_pointer_needed) \ |
ff9940b0 | 1701 | offset -= 16; \ |
18543a22 | 1702 | if (! volatile_func \ |
c7861455 | 1703 | && (regs_ever_live[LR_REGNUM] /*|| saved_hard_reg */)) \ |
ff9940b0 | 1704 | offset += 4; \ |
18543a22 | 1705 | offset += current_function_outgoing_args_size; \ |
d5b7b3ae | 1706 | (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \ |
ff9940b0 RE |
1707 | } \ |
1708 | } \ | |
1709 | } | |
35d965d5 | 1710 | |
d5b7b3ae RE |
1711 | /* Note: This macro must match the code in thumb_function_prologue(). */ |
1712 | #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1713 | { \ | |
1714 | (OFFSET) = 0; \ | |
1715 | if ((FROM) == ARG_POINTER_REGNUM) \ | |
1716 | { \ | |
1717 | int count_regs = 0; \ | |
1718 | int regno; \ | |
1719 | for (regno = 8; regno < 13; regno ++) \ | |
1720 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1721 | count_regs ++; \ | |
1722 | if (count_regs) \ | |
1723 | (OFFSET) += 4 * count_regs; \ | |
1724 | count_regs = 0; \ | |
1725 | for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ | |
1726 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1727 | count_regs ++; \ | |
1728 | if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ | |
1729 | (OFFSET) += 4 * (count_regs + 1); \ | |
1730 | if (TARGET_BACKTRACE) \ | |
1731 | { \ | |
1732 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ | |
1733 | (OFFSET) += 20; \ | |
1734 | else \ | |
1735 | (OFFSET) += 16; \ | |
1736 | } \ | |
1737 | } \ | |
1738 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1739 | { \ | |
1740 | (OFFSET) += current_function_outgoing_args_size; \ | |
1741 | (OFFSET) += ROUND_UP (get_frame_size ()); \ | |
1742 | } \ | |
1743 | } | |
1744 | ||
1745 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1746 | if (TARGET_ARM) \ | |
1747 | ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \ | |
1748 | else \ | |
1749 | THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) | |
1750 | ||
1751 | /* Special case handling of the location of arguments passed on the stack. */ | |
1752 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
1753 | ||
1754 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1755 | once for every function before code is generated. */ | |
1756 | #define INIT_EXPANDERS arm_init_expanders () | |
1757 | ||
35d965d5 RS |
1758 | /* Output assembler code for a block containing the constant parts |
1759 | of a trampoline, leaving space for the variable parts. | |
1760 | ||
1761 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1762 | referencing pc adds an offset of 8) the trampoline looks like: | |
1763 | ldr r8, [pc, #0] | |
1764 | ldr pc, [pc] | |
1765 | .word static chain value | |
11c1a207 RE |
1766 | .word function's address |
1767 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
d5b7b3ae RE |
1768 | #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ |
1769 | { \ | |
1770 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1771 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1772 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1773 | PC_REGNUM, PC_REGNUM); \ | |
1774 | ASM_OUTPUT_INT (FILE, const0_rtx); \ | |
1775 | ASM_OUTPUT_INT (FILE, const0_rtx); \ | |
1776 | } | |
1777 | ||
1778 | /* On the Thumb we always switch into ARM mode to execute the trampoline. | |
1779 | Why - because it is easier. This code will always be branched to via | |
1780 | a BX instruction and since the compiler magically generates the address | |
1781 | of the function the linker has no opportunity to ensure that the | |
1782 | bottom bit is set. Thus the processor will be in ARM mode when it | |
1783 | reaches this code. So we duplicate the ARM trampoline code and add | |
1784 | a switch into Thumb mode as well. */ | |
1785 | #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ | |
1786 | { \ | |
1787 | fprintf (FILE, "\t.code 32\n"); \ | |
1788 | fprintf (FILE, ".Ltrampoline_start:\n"); \ | |
1789 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1790 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1791 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1792 | IP_REGNUM, PC_REGNUM); \ | |
1793 | asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ | |
1794 | IP_REGNUM, IP_REGNUM); \ | |
1795 | asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ | |
1796 | fprintf (FILE, "\t.word\t0\n"); \ | |
1797 | fprintf (FILE, "\t.word\t0\n"); \ | |
1798 | fprintf (FILE, "\t.code 16\n"); \ | |
35d965d5 RS |
1799 | } |
1800 | ||
d5b7b3ae RE |
1801 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1802 | if (TARGET_ARM) \ | |
1803 | ARM_TRAMPOLINE_TEMPLATE (FILE) \ | |
1804 | else \ | |
1805 | THUMB_TRAMPOLINE_TEMPLATE (FILE) | |
1806 | ||
35d965d5 | 1807 | /* Length in units of the trampoline for entering a nested function. */ |
d5b7b3ae | 1808 | #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) |
35d965d5 RS |
1809 | |
1810 | /* Alignment required for a trampoline in units. */ | |
1811 | #define TRAMPOLINE_ALIGN 4 | |
1812 | ||
1813 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1814 | FNADDR is an RTX for the address of the function's pure code. | |
1815 | CXT is an RTX for the static chain value for the function. */ | |
d5b7b3ae RE |
1816 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1817 | { \ | |
1818 | emit_move_insn \ | |
1819 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ | |
1820 | emit_move_insn \ | |
1821 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ | |
35d965d5 RS |
1822 | } |
1823 | ||
35d965d5 RS |
1824 | \f |
1825 | /* Addressing modes, and classification of registers for them. */ | |
35d965d5 | 1826 | #define HAVE_POST_INCREMENT 1 |
d5b7b3ae RE |
1827 | #define HAVE_PRE_INCREMENT TARGET_ARM |
1828 | #define HAVE_POST_DECREMENT TARGET_ARM | |
1829 | #define HAVE_PRE_DECREMENT TARGET_ARM | |
35d965d5 RS |
1830 | |
1831 | /* Macros to check register numbers against specific register classes. */ | |
1832 | ||
1833 | /* These assume that REGNO is a hard or pseudo reg number. | |
1834 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1835 | or a pseudo reg currently allocated to a suitable hard reg. | |
1836 | Since they use reg_renumber, they are safe only once reg_renumber | |
d5b7b3ae RE |
1837 | has been allocated, which happens in local-alloc.c. */ |
1838 | #define TEST_REGNO(R, TEST, VALUE) \ | |
1839 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1840 | ||
1841 | /* On the ARM, don't allow the pc to be used. */ | |
f1008e52 RE |
1842 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1843 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1844 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1845 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1846 | ||
1847 | #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1848 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
1849 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1850 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1851 | ||
1852 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1853 | (TARGET_THUMB \ | |
1854 | ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
1855 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
1856 | ||
1857 | /* For ARM code, we don't care about the mode, but for Thumb, the index | |
1858 | must be suitable for use in a QImode load. */ | |
d5b7b3ae RE |
1859 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1860 | REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) | |
35d965d5 RS |
1861 | |
1862 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 | 1863 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1864 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1865 | |
1866 | /* Recognize any constant value that is a valid address. */ | |
1867 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1868 | |
1869 | #ifdef AOF_ASSEMBLER | |
1870 | ||
1871 | #define CONSTANT_ADDRESS_P(X) \ | |
d5b7b3ae | 1872 | (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) |
11c1a207 RE |
1873 | |
1874 | #else | |
35d965d5 | 1875 | |
008cf58a RE |
1876 | #define CONSTANT_ADDRESS_P(X) \ |
1877 | (GET_CODE (X) == SYMBOL_REF \ | |
1878 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1879 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1880 | |
11c1a207 RE |
1881 | #endif /* AOF_ASSEMBLER */ |
1882 | ||
35d965d5 RS |
1883 | /* Nonzero if the constant value X is a legitimate general operand. |
1884 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1885 | ||
1886 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1887 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1888 | constant pool XXX. |
82e9d970 PB |
1889 | |
1890 | When generating pic allow anything. */ | |
d5b7b3ae RE |
1891 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1892 | ||
1893 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1894 | ( GET_CODE (X) == CONST_INT \ | |
1895 | || GET_CODE (X) == CONST_DOUBLE \ | |
1896 | || CONSTANT_ADDRESS_P (X)) | |
1897 | ||
1898 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1899 | (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) | |
1900 | ||
c27ba912 DM |
1901 | /* Special characters prefixed to function names |
1902 | in order to encode attribute like information. | |
1903 | Note, '@' and '*' have already been taken. */ | |
1904 | #define SHORT_CALL_FLAG_CHAR '^' | |
1905 | #define LONG_CALL_FLAG_CHAR '#' | |
1906 | ||
1907 | #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ | |
1908 | (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) | |
1909 | ||
1910 | #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ | |
1911 | (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) | |
1912 | ||
1913 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
1914 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1915 | #endif | |
1916 | ||
1917 | /* This is a C fragement for the inside of a switch statement. | |
1918 | Each case label should return the number of characters to | |
1919 | be stripped from the start of a function's name, if that | |
1920 | name starts with the indicated character. */ | |
1921 | #define ARM_NAME_ENCODING_LENGTHS \ | |
1922 | case SHORT_CALL_FLAG_CHAR: return 1; \ | |
1923 | case LONG_CALL_FLAG_CHAR: return 1; \ | |
00fdafef | 1924 | case '*': return 1; \ |
c27ba912 DM |
1925 | SUBTARGET_NAME_ENCODING_LENGTHS |
1926 | ||
1927 | /* This has to be handled by a function because more than part of the | |
6d77b53e | 1928 | ARM backend uses function name prefixes to encode attributes. */ |
e5951263 | 1929 | #undef STRIP_NAME_ENCODING |
c27ba912 DM |
1930 | #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \ |
1931 | (VAR) = arm_strip_name_encoding (SYMBOL_NAME) | |
1932 | ||
1933 | /* This is how to output a reference to a user-level label named NAME. | |
1934 | `assemble_name' uses this. */ | |
e5951263 | 1935 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1936 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
d4206a10 | 1937 | asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME)) |
c27ba912 DM |
1938 | |
1939 | /* If we are referencing a function that is weak then encode a long call | |
1940 | flag in the function name, otherwise if the function is static or | |
1941 | or known to be defined in this file then encode a short call flag. | |
1942 | This macro is used inside the ENCODE_SECTION macro. */ | |
1943 | #define ARM_ENCODE_CALL_TYPE(decl) \ | |
1944 | if (TREE_CODE (decl) == FUNCTION_DECL) \ | |
1945 | { \ | |
1946 | if (DECL_WEAK (decl)) \ | |
1947 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \ | |
1948 | else if (! TREE_PUBLIC (decl)) \ | |
1949 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \ | |
1950 | } \ | |
82e9d970 | 1951 | |
ff9940b0 RE |
1952 | /* Symbols in the text segment can be accessed without indirecting via the |
1953 | constant pool; it may take an extra binary operation, but this is still | |
008cf58a RE |
1954 | faster than indirecting via memory. Don't do this when not optimizing, |
1955 | since we won't be calculating al of the offsets necessary to do this | |
1956 | simplification. */ | |
11c1a207 RE |
1957 | /* This doesn't work with AOF syntax, since the string table may be in |
1958 | a different AREA. */ | |
1959 | #ifndef AOF_ASSEMBLER | |
ff9940b0 RE |
1960 | #define ENCODE_SECTION_INFO(decl) \ |
1961 | { \ | |
008cf58a | 1962 | if (optimize > 0 && TREE_CONSTANT (decl) \ |
ff9940b0 | 1963 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ |
228b6a3f RS |
1964 | { \ |
1965 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ | |
1966 | ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ | |
1967 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ | |
1968 | } \ | |
c27ba912 DM |
1969 | ARM_ENCODE_CALL_TYPE (decl) \ |
1970 | } | |
1971 | #else | |
1972 | #define ENCODE_SECTION_INFO(decl) \ | |
1973 | { \ | |
1974 | ARM_ENCODE_CALL_TYPE (decl) \ | |
ff9940b0 | 1975 | } |
11c1a207 | 1976 | #endif |
7a801826 | 1977 | |
c27ba912 DM |
1978 | #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ |
1979 | arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) | |
1980 | ||
35d965d5 RS |
1981 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1982 | and check its validity for a certain class. | |
1983 | We have two alternate definitions for each of them. | |
1984 | The usual definition accepts all pseudo regs; the other rejects | |
1985 | them unless they have been allocated suitable hard regs. | |
1986 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1987 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1988 | |
f1008e52 RE |
1989 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1990 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1991 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1992 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1993 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1994 | |
f1008e52 RE |
1995 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1996 | (REGNO (X) <= LAST_LO_REGNUM \ | |
1997 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1998 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1999 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
2000 | || (X) == hard_frame_pointer_rtx \ | |
2001 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 2002 | |
d5b7b3ae | 2003 | #else /* REG_OK_STRICT */ |
ff9940b0 | 2004 | |
f1008e52 RE |
2005 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2006 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 2007 | |
f1008e52 RE |
2008 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2009 | THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 2010 | |
d5b7b3ae | 2011 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
2012 | |
2013 | /* Now define some helpers in terms of the above. */ | |
2014 | ||
2015 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
2016 | (TARGET_THUMB \ | |
2017 | ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
2018 | : ARM_REG_OK_FOR_BASE_P (X)) | |
2019 | ||
2020 | #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) | |
2021 | ||
2022 | /* For Thumb, a valid index register is anything that can be used in | |
2023 | a byte load instruction. */ | |
2024 | #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
2025 | ||
2026 | /* Nonzero if X is a hard reg that can be used as an index | |
2027 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
2028 | is not suitable. */ | |
2029 | #define REG_OK_FOR_INDEX_P(X) \ | |
2030 | (TARGET_THUMB \ | |
2031 | ? THUMB_REG_OK_FOR_INDEX_P (X) \ | |
2032 | : ARM_REG_OK_FOR_INDEX_P (X)) | |
2033 | ||
35d965d5 RS |
2034 | \f |
2035 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
2036 | that is a valid memory address for an instruction. | |
2037 | The MODE argument is the machine mode for the MEM expression | |
2038 | that wants to use this address. | |
2039 | ||
d5b7b3ae RE |
2040 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ |
2041 | ||
2042 | /* --------------------------------arm version----------------------------- */ | |
f1008e52 RE |
2043 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
2044 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 2045 | |
f1008e52 RE |
2046 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
2047 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 RS |
2048 | |
2049 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
2050 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
2051 | only be small constants. */ | |
f1008e52 RE |
2052 | #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
2053 | do \ | |
35d965d5 | 2054 | { \ |
f1008e52 RE |
2055 | HOST_WIDE_INT range; \ |
2056 | enum rtx_code code = GET_CODE (INDEX); \ | |
35d965d5 | 2057 | \ |
f1008e52 RE |
2058 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
2059 | { \ | |
2060 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
2061 | && INTVAL (INDEX) > -1024 \ | |
2062 | && (INTVAL (INDEX) & 3) == 0) \ | |
2063 | goto LABEL; \ | |
2064 | } \ | |
2065 | else \ | |
2066 | { \ | |
2067 | if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ | |
2068 | && GET_MODE_SIZE (MODE) <= 4) \ | |
2069 | goto LABEL; \ | |
2070 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ | |
2071 | && (! arm_arch4 || (MODE) != HImode)) \ | |
2072 | { \ | |
2073 | rtx xiop0 = XEXP (INDEX, 0); \ | |
2074 | rtx xiop1 = XEXP (INDEX, 1); \ | |
2075 | if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ | |
2076 | && power_of_two_operand (xiop1, SImode)) \ | |
2077 | goto LABEL; \ | |
2078 | if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ | |
2079 | && power_of_two_operand (xiop0, SImode)) \ | |
2080 | goto LABEL; \ | |
2081 | } \ | |
2082 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2083 | && (code == LSHIFTRT || code == ASHIFTRT \ | |
2084 | || code == ASHIFT || code == ROTATERT) \ | |
2085 | && (! arm_arch4 || (MODE) != HImode)) \ | |
2086 | { \ | |
2087 | rtx op = XEXP (INDEX, 1); \ | |
2088 | if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
2089 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
2090 | && INTVAL (op) <= 31) \ | |
2091 | goto LABEL; \ | |
2092 | } \ | |
2093 | /* NASTY: Since this limits the addressing of unsigned \ | |
2094 | byte loads. */ \ | |
2095 | range = ((MODE) == HImode || (MODE) == QImode) \ | |
2096 | ? (arm_arch4 ? 256 : 4095) : 4096; \ | |
2097 | if (code == CONST_INT && INTVAL (INDEX) < range \ | |
2098 | && INTVAL (INDEX) > -range) \ | |
2099 | goto LABEL; \ | |
2100 | } \ | |
35d965d5 | 2101 | } \ |
f1008e52 RE |
2102 | while (0) |
2103 | ||
2104 | /* Jump to LABEL if X is a valid address RTX. This must take | |
2105 | REG_OK_STRICT into account when deciding about valid registers. | |
2106 | ||
2107 | Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non | |
2108 | floating SYMBOL_REF to the constant pool. Allow REG-only and | |
2109 | AUTINC-REG if handling TImode or HImode. Other symbol refs must be | |
2110 | forced though a static cell to ensure addressability. */ | |
d19fb8e3 NC |
2111 | #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
2112 | { \ | |
2113 | if (ARM_BASE_REGISTER_RTX_P (X)) \ | |
2114 | goto LABEL; \ | |
2115 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
2116 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2117 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2118 | goto LABEL; \ | |
2119 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2120 | && (GET_CODE (X) == LABEL_REF \ | |
2121 | || (GET_CODE (X) == CONST \ | |
2122 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
2123 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
2124 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
2125 | goto LABEL; \ | |
2126 | else if ((MODE) == TImode) \ | |
2127 | ; \ | |
2128 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ | |
2129 | { \ | |
2130 | if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
2131 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2132 | { \ | |
2133 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
2134 | if (val == 4 || val == -4 || val == -8) \ | |
2135 | goto LABEL; \ | |
2136 | } \ | |
2137 | } \ | |
2138 | else if (GET_CODE (X) == PLUS) \ | |
2139 | { \ | |
2140 | rtx xop0 = XEXP (X, 0); \ | |
2141 | rtx xop1 = XEXP (X, 1); \ | |
2142 | \ | |
2143 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2144 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
2145 | else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ | |
2146 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
2147 | } \ | |
2148 | /* Reload currently can't handle MINUS, so disable this for now */ \ | |
2149 | /* else if (GET_CODE (X) == MINUS) \ | |
2150 | { \ | |
2151 | rtx xop0 = XEXP (X,0); \ | |
2152 | rtx xop1 = XEXP (X,1); \ | |
2153 | \ | |
2154 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2155 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
2156 | } */ \ | |
2157 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2158 | && GET_CODE (X) == SYMBOL_REF \ | |
2159 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2160 | && ! (flag_pic \ | |
2161 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2162 | goto LABEL; \ | |
2163 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
2164 | && (GET_MODE_SIZE (MODE) <= 4) \ | |
2165 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2166 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2167 | goto LABEL; \ | |
35d965d5 | 2168 | } |
d5b7b3ae RE |
2169 | |
2170 | /* ---------------------thumb version----------------------------------*/ | |
f1008e52 | 2171 | #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ |
d5b7b3ae RE |
2172 | (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ |
2173 | : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ | |
2174 | && ((VAL) & 1) == 0) \ | |
2175 | : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ | |
2176 | && ((VAL) & 3) == 0)) | |
2177 | ||
2178 | /* The AP may be eliminated to either the SP or the FP, so we use the | |
2179 | least common denominator, e.g. SImode, and offsets from 0 to 64. */ | |
2180 | ||
2181 | /* ??? Verify whether the above is the right approach. */ | |
2182 | ||
2183 | /* ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2184 | needs special handling also. */ | |
2185 | ||
2186 | /* ??? Look at how the mips16 port solves this problem. It probably uses | |
2187 | better ways to solve some of these problems. */ | |
2188 | ||
2189 | /* Although it is not incorrect, we don't accept QImode and HImode | |
f1008e52 RE |
2190 | addresses based on the frame pointer or arg pointer until the |
2191 | reload pass starts. This is so that eliminating such addresses | |
2192 | into stack based ones won't produce impossible code. */ | |
d5b7b3ae RE |
2193 | #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ |
2194 | { \ | |
2195 | /* ??? Not clear if this is right. Experiment. */ \ | |
2196 | if (GET_MODE_SIZE (MODE) < 4 \ | |
2197 | && ! (reload_in_progress || reload_completed) \ | |
2198 | && ( reg_mentioned_p (frame_pointer_rtx, X) \ | |
2199 | || reg_mentioned_p (arg_pointer_rtx, X) \ | |
2200 | || reg_mentioned_p (virtual_incoming_args_rtx, X) \ | |
2201 | || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ | |
2202 | || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ | |
2203 | || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ | |
2204 | ; \ | |
2205 | /* Accept any base register. SP only in SImode or larger. */ \ | |
f1008e52 RE |
2206 | else if (GET_CODE (X) == REG \ |
2207 | && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ | |
d5b7b3ae RE |
2208 | goto WIN; \ |
2209 | /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ | |
2210 | else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ | |
2211 | && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ | |
2212 | goto WIN; \ | |
2213 | /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ | |
2214 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2215 | && (GET_CODE (X) == LABEL_REF \ | |
2216 | || (GET_CODE (X) == CONST \ | |
2217 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
2218 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ | |
2219 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ | |
2220 | goto WIN; \ | |
2221 | /* Post-inc indexing only supported for SImode and larger. */ \ | |
2222 | else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ | |
2223 | && GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2224 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
d5b7b3ae RE |
2225 | goto WIN; \ |
2226 | else if (GET_CODE (X) == PLUS) \ | |
2227 | { \ | |
2228 | /* REG+REG address can be any two index registers. */ \ | |
2229 | /* We disallow FRAME+REG addressing since we know that FRAME \ | |
2230 | will be replaced with STACK, and SP relative addressing only \ | |
2231 | permits SP+OFFSET. */ \ | |
2232 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2233 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2234 | && GET_CODE (XEXP (X, 1)) == REG \ | |
2235 | && XEXP (X, 0) != frame_pointer_rtx \ | |
2236 | && XEXP (X, 1) != frame_pointer_rtx \ | |
2237 | && XEXP (X, 0) != virtual_stack_vars_rtx \ | |
2238 | && XEXP (X, 1) != virtual_stack_vars_rtx \ | |
f1008e52 RE |
2239 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
2240 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ | |
d5b7b3ae RE |
2241 | goto WIN; \ |
2242 | /* REG+const has 5-7 bit offset for non-SP registers. */ \ | |
2243 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2244 | && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
d5b7b3ae RE |
2245 | || XEXP (X, 0) == arg_pointer_rtx) \ |
2246 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 2247 | && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
2248 | goto WIN; \ |
2249 | /* REG+const has 10 bit offset for SP, but only SImode and \ | |
2250 | larger is supported. */ \ | |
2251 | /* ??? Should probably check for DI/DFmode overflow here \ | |
2252 | just like GO_IF_LEGITIMATE_OFFSET does. */ \ | |
2253 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2254 | && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ | |
2255 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2256 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2257 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ | |
2258 | + GET_MODE_SIZE (MODE)) <= 1024 \ | |
2259 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2260 | goto WIN; \ | |
2261 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2262 | && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ | |
2263 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2264 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2265 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2266 | goto WIN; \ | |
2267 | } \ | |
2268 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2269 | && GET_CODE (X) == SYMBOL_REF \ | |
2270 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2271 | && ! (flag_pic \ | |
2272 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2273 | goto WIN; \ | |
2274 | } | |
2275 | ||
2276 | /* ------------------------------------------------------------------- */ | |
2277 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
2278 | if (TARGET_ARM) \ | |
2279 | ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ | |
2280 | else /* if (TARGET_THUMB) */ \ | |
2281 | THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) | |
2282 | /* ------------------------------------------------------------------- */ | |
35d965d5 RS |
2283 | \f |
2284 | /* Try machine-dependent ways of modifying an illegitimate address | |
2285 | to be legitimate. If we find one, return the new, valid address. | |
2286 | This macro is used in only one place: `memory_address' in explow.c. | |
2287 | ||
2288 | OLDX is the address as it was before break_out_memory_refs was called. | |
2289 | In some cases it is useful to look at this to decide what needs to be done. | |
2290 | ||
2291 | MODE and WIN are passed so that this macro can use | |
2292 | GO_IF_LEGITIMATE_ADDRESS. | |
2293 | ||
2294 | It is always safe for this macro to do nothing. It exists to recognize | |
2295 | opportunities to optimize the output. | |
2296 | ||
2297 | On the ARM, try to convert [REG, #BIGCONST] | |
2298 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
2299 | where VALIDCONST == 0 in case of TImode. */ | |
d5b7b3ae | 2300 | #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
3967692c RE |
2301 | { \ |
2302 | if (GET_CODE (X) == PLUS) \ | |
2303 | { \ | |
2304 | rtx xop0 = XEXP (X, 0); \ | |
2305 | rtx xop1 = XEXP (X, 1); \ | |
2306 | \ | |
11c1a207 | 2307 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 2308 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 2309 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c | 2310 | xop1 = force_reg (SImode, xop1); \ |
f1008e52 RE |
2311 | if (ARM_BASE_REGISTER_RTX_P (xop0) \ |
2312 | && GET_CODE (xop1) == CONST_INT) \ | |
3967692c RE |
2313 | { \ |
2314 | HOST_WIDE_INT n, low_n; \ | |
2315 | rtx base_reg, val; \ | |
2316 | n = INTVAL (xop1); \ | |
2317 | \ | |
11c1a207 | 2318 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
2319 | { \ |
2320 | low_n = n & 0x0f; \ | |
2321 | n &= ~0x0f; \ | |
2322 | if (low_n > 4) \ | |
2323 | { \ | |
2324 | n += 16; \ | |
2325 | low_n -= 16; \ | |
2326 | } \ | |
2327 | } \ | |
2328 | else \ | |
2329 | { \ | |
2330 | low_n = ((MODE) == TImode ? 0 \ | |
2331 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
2332 | n -= low_n; \ | |
2333 | } \ | |
2334 | base_reg = gen_reg_rtx (SImode); \ | |
43cffd11 RE |
2335 | val = force_operand (gen_rtx_PLUS (SImode, xop0, \ |
2336 | GEN_INT (n)), NULL_RTX); \ | |
3967692c RE |
2337 | emit_move_insn (base_reg, val); \ |
2338 | (X) = (low_n == 0 ? base_reg \ | |
43cffd11 | 2339 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ |
3967692c RE |
2340 | } \ |
2341 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
43cffd11 | 2342 | (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ |
3967692c RE |
2343 | } \ |
2344 | else if (GET_CODE (X) == MINUS) \ | |
2345 | { \ | |
2346 | rtx xop0 = XEXP (X, 0); \ | |
2347 | rtx xop1 = XEXP (X, 1); \ | |
2348 | \ | |
2349 | if (CONSTANT_P (xop0)) \ | |
2350 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 2351 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
2352 | xop1 = force_reg (SImode, xop1); \ |
2353 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
43cffd11 | 2354 | (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ |
3967692c | 2355 | } \ |
7a801826 RE |
2356 | if (flag_pic) \ |
2357 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
2358 | if (memory_address_p (MODE, X)) \ |
2359 | goto WIN; \ | |
35d965d5 RS |
2360 | } |
2361 | ||
d5b7b3ae RE |
2362 | #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
2363 | if (flag_pic) \ | |
2364 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); | |
2365 | ||
2366 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2367 | if (TARGET_ARM) \ | |
2368 | ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ | |
2369 | else \ | |
2370 | THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) | |
2371 | ||
35d965d5 RS |
2372 | /* Go to LABEL if ADDR (a legitimate address expression) |
2373 | has an effect that depends on the machine mode it is used for. */ | |
d5b7b3ae | 2374 | #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
35d965d5 | 2375 | { \ |
d5b7b3ae RE |
2376 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ |
2377 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
35d965d5 RS |
2378 | goto LABEL; \ |
2379 | } | |
d5b7b3ae RE |
2380 | |
2381 | /* Nothing helpful to do for the Thumb */ | |
2382 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2383 | if (TARGET_ARM) \ | |
2384 | ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) | |
35d965d5 | 2385 | \f |
d5b7b3ae | 2386 | |
35d965d5 RS |
2387 | /* Specify the machine mode that this machine uses |
2388 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2389 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2390 | |
18543a22 ILT |
2391 | /* Define as C expression which evaluates to nonzero if the tablejump |
2392 | instruction expects the table to contain offsets from the address of the | |
2393 | table. | |
2394 | Do not define this if the table should contain absolute addresses. */ | |
2395 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 RS |
2396 | |
2397 | /* Specify the tree operation to be used to convert reals to integers. */ | |
2398 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
2399 | ||
2400 | /* This is the kind of divide that is easiest to do in the general case. */ | |
2401 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
2402 | ||
ff9940b0 RE |
2403 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2404 | unsigned is probably best, but may break some code. */ | |
2405 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2406 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2407 | #endif |
2408 | ||
2409 | /* Don't cse the address of the function being compiled. */ | |
2410 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
2411 | ||
2412 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
2413 | in one reasonably fast instruction. */ |
2414 | #define MOVE_MAX 4 | |
35d965d5 | 2415 | |
d19fb8e3 NC |
2416 | #undef MOVE_RATIO |
2417 | #define MOVE_RATIO (arm_is_xscale ? 4 : 2) | |
2418 | ||
ff9940b0 RE |
2419 | /* Define if operations between registers always perform the operation |
2420 | on the full register even if a narrower mode is specified. */ | |
2421 | #define WORD_REGISTER_OPERATIONS | |
2422 | ||
2423 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2424 | will either zero-extend or sign-extend. The value of this macro should | |
2425 | be the code that says which one of the two operations is implicitly | |
2426 | done, NIL if none. */ | |
9c872872 | 2427 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2428 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2429 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
2430 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) | |
ff9940b0 | 2431 | |
35d965d5 RS |
2432 | /* Define this if zero-extension is slow (more than one real instruction). |
2433 | On the ARM, it is more than one instruction only if not fetching from | |
2434 | memory. */ | |
2435 | /* #define SLOW_ZERO_EXTEND */ | |
2436 | ||
2437 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
2438 | #define SLOW_BYTE_ACCESS 0 | |
2439 | ||
d5b7b3ae RE |
2440 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
2441 | ||
35d965d5 RS |
2442 | /* Immediate shift counts are truncated by the output routines (or was it |
2443 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2444 | that the native compiler puts too large (> 32) immediate shift counts | |
2445 | into a register and shifts by the register, letting the ARM decide what | |
2446 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2447 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2448 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2449 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
2450 | rotates is modulo 32 used. */ | |
2451 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 2452 | |
35d965d5 | 2453 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2454 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2455 | |
2456 | /* Calling from registers is a massive pain. */ | |
2457 | #define NO_FUNCTION_CSE 1 | |
2458 | ||
2459 | /* Chars and shorts should be passed as ints. */ | |
2460 | #define PROMOTE_PROTOTYPES 1 | |
2461 | ||
35d965d5 RS |
2462 | /* The machine modes of pointers and functions */ |
2463 | #define Pmode SImode | |
2464 | #define FUNCTION_MODE Pmode | |
2465 | ||
d5b7b3ae RE |
2466 | #define ARM_FRAME_RTX(X) \ |
2467 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2468 | || (X) == arg_pointer_rtx) |
2469 | ||
62b10bbc | 2470 | #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ |
d5b7b3ae | 2471 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
2472 | |
2473 | /* Moves to and from memory are quite expensive */ | |
d5b7b3ae RE |
2474 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
2475 | (TARGET_ARM ? 10 : \ | |
2476 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
2477 | * (CLASS == LO_REGS ? 1 : 2))) | |
2478 | ||
3967692c | 2479 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 2480 | the same for practically all of them. So we weight the different types |
3967692c RE |
2481 | of address here in the order (most pref first): |
2482 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
d5b7b3ae | 2483 | #define ARM_ADDRESS_COST(X) \ |
3967692c RE |
2484 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ |
2485 | || GET_CODE (X) == SYMBOL_REF) \ | |
2486 | ? 0 \ | |
2487 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
2488 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
2489 | ? 10 \ | |
2490 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
2491 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
2492 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
2493 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
2494 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
2495 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
2496 | ? 1 : 0)) \ | |
2497 | : 4))))) | |
d5b7b3ae RE |
2498 | |
2499 | #define THUMB_ADDRESS_COST(X) \ | |
2500 | ((GET_CODE (X) == REG \ | |
2501 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
2502 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
2503 | ? 1 : 2) | |
2504 | ||
2505 | #define ADDRESS_COST(X) \ | |
2506 | (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) | |
2507 | ||
ff9940b0 RE |
2508 | /* Try to generate sequences that don't involve branches, we can then use |
2509 | conditional instructions */ | |
d5b7b3ae RE |
2510 | #define BRANCH_COST \ |
2511 | (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) | |
7a801826 RE |
2512 | |
2513 | /* A C statement to update the variable COST based on the relationship | |
2514 | between INSN that is dependent on DEP through dependence LINK. */ | |
6cfc7210 NC |
2515 | #define ADJUST_COST(INSN, LINK, DEP, COST) \ |
2516 | (COST) = arm_adjust_cost (INSN, LINK, DEP, COST) | |
7a801826 RE |
2517 | \f |
2518 | /* Position Independent Code. */ | |
2519 | /* We decide which register to use based on the compilation options and | |
2520 | the assembler in use; this is more general than the APCS restriction of | |
2521 | using sb (r9) all the time. */ | |
2522 | extern int arm_pic_register; | |
2523 | ||
ed0e6530 PB |
2524 | /* Used when parsing command line option -mpic-register=. */ |
2525 | extern const char * arm_pic_register_string; | |
2526 | ||
7a801826 RE |
2527 | /* The register number of the register used to address a table of static |
2528 | data addresses in memory. */ | |
2529 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2530 | ||
c1163e75 | 2531 | #define FINALIZE_PIC arm_finalize_pic (1) |
7a801826 | 2532 | |
f5a1b0d2 NC |
2533 | /* We can't directly access anything that contains a symbol, |
2534 | nor can we indirect via the constant pool. */ | |
82e9d970 PB |
2535 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
2536 | ( ! symbol_mentioned_p (X) \ | |
2537 | && ! label_mentioned_p (X) \ | |
2538 | && (! CONSTANT_POOL_ADDRESS_P (X) \ | |
c27ba912 DM |
2539 | || ( ! symbol_mentioned_p (get_pool_constant (X)) \ |
2540 | && ! label_mentioned_p (get_pool_constant (X))))) | |
13bd191d PB |
2541 | |
2542 | /* We need to know when we are making a constant pool; this determines | |
2543 | whether data needs to be in the GOT or can be referenced via a GOT | |
2544 | offset. */ | |
2545 | extern int making_const_table; | |
82e9d970 PB |
2546 | \f |
2547 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
2548 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
2549 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
2550 | #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ | |
2551 | (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) | |
2552 | ||
2553 | /* If defined, a C expression whose value is zero if the attributes on | |
2554 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
2555 | two if they are nearly compatible (which causes a warning to be | |
2556 | generated). */ | |
2557 | #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ | |
2558 | (arm_comp_type_attributes (TYPE1, TYPE2)) | |
c27ba912 DM |
2559 | |
2560 | /* If defined, a C statement that assigns default attributes to newly | |
2561 | defined TYPE. */ | |
2562 | #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \ | |
2563 | arm_set_default_type_attributes (TYPE) | |
2564 | ||
2565 | /* Handle pragmas for compatibility with Intel's compilers. */ | |
8b97c5f8 ZW |
2566 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ |
2567 | cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ | |
2568 | cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ | |
2569 | cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ | |
2570 | } while (0) | |
2571 | ||
ff9940b0 RE |
2572 | /* Condition code information. */ |
2573 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2574 | return the mode to be used for the comparison. | |
ddd5a7c1 | 2575 | CCFPEmode should be used with floating inequalities, |
ff9940b0 | 2576 | CCFPmode should be used with floating equalities. |
ddd5a7c1 | 2577 | CC_NOOVmode should be used with SImode integer equalities. |
69fcc21d | 2578 | CC_Zmode should be used if only the Z flag is set correctly |
ff9940b0 RE |
2579 | CCmode should be used otherwise. */ |
2580 | ||
d5b7b3ae RE |
2581 | #define EXTRA_CC_MODES \ |
2582 | CC(CC_NOOVmode, "CC_NOOV") \ | |
2583 | CC(CC_Zmode, "CC_Z") \ | |
2584 | CC(CC_SWPmode, "CC_SWP") \ | |
2585 | CC(CCFPmode, "CCFP") \ | |
2586 | CC(CCFPEmode, "CCFPE") \ | |
2587 | CC(CC_DNEmode, "CC_DNE") \ | |
2588 | CC(CC_DEQmode, "CC_DEQ") \ | |
2589 | CC(CC_DLEmode, "CC_DLE") \ | |
2590 | CC(CC_DLTmode, "CC_DLT") \ | |
2591 | CC(CC_DGEmode, "CC_DGE") \ | |
2592 | CC(CC_DGTmode, "CC_DGT") \ | |
2593 | CC(CC_DLEUmode, "CC_DLEU") \ | |
2594 | CC(CC_DLTUmode, "CC_DLTU") \ | |
2595 | CC(CC_DGEUmode, "CC_DGEU") \ | |
2596 | CC(CC_DGTUmode, "CC_DGTU") \ | |
2597 | CC(CC_Cmode, "CC_C") | |
2598 | ||
2599 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2600 | |
008cf58a RE |
2601 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
2602 | ||
62b10bbc NC |
2603 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2604 | do \ | |
2605 | { \ | |
2606 | if (GET_CODE (OP1) == CONST_INT \ | |
2607 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2608 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2609 | { \ | |
2610 | rtx const_op = OP1; \ | |
2611 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
2612 | OP1 = const_op; \ | |
2613 | } \ | |
2614 | } \ | |
2615 | while (0) | |
62dd06ea | 2616 | |
ff9940b0 RE |
2617 | #define STORE_FLAG_VALUE 1 |
2618 | ||
35d965d5 | 2619 | \f |
35d965d5 | 2620 | |
11c1a207 RE |
2621 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
2622 | load addresses a limited distance around the pc. We do some | |
2623 | special munging to move the constant pool values to the correct | |
2624 | point in the code. */ | |
d5b7b3ae RE |
2625 | #define MACHINE_DEPENDENT_REORG(INSN) \ |
2626 | arm_reorg (INSN); \ | |
2627 | ||
2628 | #undef ASM_APP_OFF | |
2629 | #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") | |
35d965d5 | 2630 | |
35d965d5 | 2631 | /* Output an internal label definition. */ |
b355a481 | 2632 | #ifndef ASM_OUTPUT_INTERNAL_LABEL |
62b10bbc NC |
2633 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ |
2634 | do \ | |
2635 | { \ | |
2a5307b1 | 2636 | char * s = (char *) alloca (40 + strlen (PREFIX)); \ |
62b10bbc NC |
2637 | \ |
2638 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ | |
2639 | && !strcmp (PREFIX, "L")) \ | |
18543a22 | 2640 | { \ |
62b10bbc | 2641 | arm_ccfsm_state = 0; \ |
18543a22 ILT |
2642 | arm_target_insn = NULL; \ |
2643 | } \ | |
62b10bbc NC |
2644 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
2645 | ASM_OUTPUT_LABEL (STREAM, s); \ | |
2646 | } \ | |
2647 | while (0) | |
b355a481 | 2648 | #endif |
2a5307b1 | 2649 | |
35d965d5 | 2650 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae RE |
2651 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
2652 | if (TARGET_ARM) \ | |
2653 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2654 | STACK_POINTER_REGNUM, REGNO); \ | |
2655 | else \ | |
2656 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) | |
2657 | ||
2658 | ||
2659 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
2660 | if (TARGET_ARM) \ | |
2661 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2662 | STACK_POINTER_REGNUM, REGNO); \ | |
2663 | else \ | |
2664 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) | |
2665 | ||
2666 | /* This is how to output a label which precedes a jumptable. Since | |
2667 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
2668 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ | |
2669 | do \ | |
2670 | { \ | |
2671 | if (TARGET_THUMB) \ | |
2672 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2673 | ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ | |
2674 | } \ | |
2675 | while (0) | |
35d965d5 | 2676 | |
6cfc7210 NC |
2677 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2678 | do \ | |
2679 | { \ | |
d5b7b3ae RE |
2680 | if (TARGET_THUMB) \ |
2681 | { \ | |
2682 | if (is_called_in_ARM_mode (DECL)) \ | |
2683 | fprintf (STREAM, "\t.code 32\n") ; \ | |
2684 | else \ | |
2685 | fprintf (STREAM, "\t.thumb_func\n") ; \ | |
2686 | } \ | |
6cfc7210 | 2687 | if (TARGET_POKE_FUNCTION_NAME) \ |
6354dc9b | 2688 | arm_poke_function_name (STREAM, (char *) NAME); \ |
6cfc7210 NC |
2689 | } \ |
2690 | while (0) | |
35d965d5 | 2691 | |
d5b7b3ae RE |
2692 | /* For aliases of functions we use .thumb_set instead. */ |
2693 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2694 | do \ | |
2695 | { \ | |
2696 | char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ | |
2697 | char * LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
2698 | \ | |
2699 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2700 | { \ | |
2701 | fprintf (FILE, "\t.thumb_set "); \ | |
2702 | assemble_name (FILE, LABEL1); \ | |
2703 | fprintf (FILE, ","); \ | |
2704 | assemble_name (FILE, LABEL2); \ | |
2705 | fprintf (FILE, "\n"); \ | |
2706 | } \ | |
2707 | else \ | |
2708 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2709 | } \ | |
2710 | while (0) | |
2711 | ||
fdc2d3b0 NC |
2712 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2713 | /* To support -falign-* switches we need to use .p2align so | |
2714 | that alignment directives in code sections will be padded | |
2715 | with no-op instructions, rather than zeroes. */ | |
2716 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ | |
2717 | if ((LOG) != 0) \ | |
2718 | { \ | |
2719 | if ((MAX_SKIP) == 0) \ | |
2720 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2721 | else \ | |
2722 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
2723 | (LOG), (MAX_SKIP)); \ | |
2724 | } | |
2725 | #endif | |
2726 | ||
35d965d5 RS |
2727 | /* Target characters. */ |
2728 | #define TARGET_BELL 007 | |
2729 | #define TARGET_BS 010 | |
2730 | #define TARGET_TAB 011 | |
2731 | #define TARGET_NEWLINE 012 | |
2732 | #define TARGET_VT 013 | |
2733 | #define TARGET_FF 014 | |
2734 | #define TARGET_CR 015 | |
2735 | \f | |
35d965d5 RS |
2736 | /* Only perform branch elimination (by making instructions conditional) if |
2737 | we're optimising. Otherwise it's of no use anyway. */ | |
d5b7b3ae RE |
2738 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2739 | if (TARGET_ARM && optimize) \ | |
2740 | arm_final_prescan_insn (INSN); \ | |
2741 | else if (TARGET_THUMB) \ | |
2742 | thumb_final_prescan_insn (INSN) | |
35d965d5 | 2743 | |
7bc7696c | 2744 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
d5b7b3ae RE |
2745 | (CODE == '@' || CODE == '|' \ |
2746 | || (TARGET_ARM && (CODE == '?')) \ | |
2747 | || (TARGET_THUMB && (CODE == '_'))) | |
6cfc7210 | 2748 | |
7bc7696c | 2749 | /* Output an operand of an instruction. */ |
35d965d5 | 2750 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2751 | arm_print_operand (STREAM, X, CODE) |
2752 | ||
e5951263 NC |
2753 | /* Create an [unsigned] host sized integer declaration that |
2754 | avoids compiler warnings. */ | |
2755 | #ifdef __STDC__ | |
2756 | #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL) | |
2757 | #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL) | |
2758 | #else | |
2759 | #define HOST_INT(x) ((HOST_WIDE_INT) x) | |
2760 | #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x) | |
2761 | #endif | |
2762 | ||
2763 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
2764 | (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ | |
2765 | : (((x) & HOST_UINT (0xffffffff)) | \ | |
2766 | (((x) & HOST_UINT (0x80000000)) \ | |
2767 | ? ((~ HOST_INT (0)) \ | |
2768 | & ~ HOST_UINT(0xffffffff)) \ | |
7bc7696c | 2769 | : 0)))) |
35d965d5 RS |
2770 | |
2771 | /* Output the address of an operand. */ | |
d5b7b3ae RE |
2772 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2773 | { \ | |
2774 | int is_minus = GET_CODE (X) == MINUS; \ | |
2775 | \ | |
2776 | if (GET_CODE (X) == REG) \ | |
2777 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2778 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2779 | { \ | |
2780 | rtx base = XEXP (X, 0); \ | |
2781 | rtx index = XEXP (X, 1); \ | |
2782 | HOST_WIDE_INT offset = 0; \ | |
2783 | if (GET_CODE (base) != REG) \ | |
2784 | { \ | |
2785 | /* Ensure that BASE is a register */ \ | |
2786 | /* (one of them must be). */ \ | |
2787 | rtx temp = base; \ | |
2788 | base = index; \ | |
2789 | index = temp; \ | |
2790 | } \ | |
2791 | switch (GET_CODE (index)) \ | |
2792 | { \ | |
2793 | case CONST_INT: \ | |
2794 | offset = INTVAL (index); \ | |
2795 | if (is_minus) \ | |
2796 | offset = -offset; \ | |
2797 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2798 | REGNO (base), offset); \ | |
2799 | break; \ | |
2800 | \ | |
2801 | case REG: \ | |
2802 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2803 | REGNO (base), is_minus ? "-" : "", \ | |
2804 | REGNO (index)); \ | |
2805 | break; \ | |
2806 | \ | |
2807 | case MULT: \ | |
2808 | case ASHIFTRT: \ | |
2809 | case LSHIFTRT: \ | |
2810 | case ASHIFT: \ | |
2811 | case ROTATERT: \ | |
2812 | { \ | |
2813 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2814 | REGNO (base), is_minus ? "-" : "", \ | |
2815 | REGNO (XEXP (index, 0))); \ | |
2816 | arm_print_operand (STREAM, index, 'S'); \ | |
2817 | fputs ("]", STREAM); \ | |
2818 | break; \ | |
2819 | } \ | |
2820 | \ | |
2821 | default: \ | |
2822 | abort(); \ | |
2823 | } \ | |
2824 | } \ | |
2825 | else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ | |
2826 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ | |
2827 | { \ | |
2828 | extern int output_memory_reference_mode; \ | |
2829 | \ | |
2830 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2831 | abort (); \ | |
2832 | \ | |
2833 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2834 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2835 | REGNO (XEXP (X, 0)), \ | |
2836 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2837 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2838 | else \ | |
2839 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2840 | REGNO (XEXP (X, 0)), \ | |
2841 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2842 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2843 | } \ | |
2844 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2845 | } |
62dd06ea | 2846 | |
d5b7b3ae RE |
2847 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2848 | { \ | |
2849 | if (GET_CODE (X) == REG) \ | |
2850 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2851 | else if (GET_CODE (X) == POST_INC) \ | |
2852 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2853 | else if (GET_CODE (X) == PLUS) \ | |
2854 | { \ | |
2855 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2856 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2857 | REGNO (XEXP (X, 0)), \ | |
2858 | (int) INTVAL (XEXP (X, 1))); \ | |
2859 | else \ | |
2860 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2861 | REGNO (XEXP (X, 0)), \ | |
2862 | REGNO (XEXP (X, 1))); \ | |
2863 | } \ | |
2864 | else \ | |
2865 | output_addr_const (STREAM, X); \ | |
2866 | } | |
2867 | ||
2868 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2869 | if (TARGET_ARM) \ | |
2870 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ | |
2871 | else \ | |
2872 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
2873 | ||
d5b7b3ae | 2874 | #define OUTPUT_INT_ADDR_CONST(STREAM, X) \ |
7a801826 | 2875 | { \ |
c1163e75 | 2876 | output_addr_const (STREAM, X); \ |
687f77a1 NC |
2877 | \ |
2878 | /* Mark symbols as position independent. We only do this in the \ | |
2879 | .text segment, not in the .data segment. */ \ | |
ed0e6530 | 2880 | if (NEED_GOT_RELOC && flag_pic && making_const_table && \ |
687f77a1 NC |
2881 | (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \ |
2882 | { \ | |
2883 | if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \ | |
2884 | fprintf (STREAM, "(GOTOFF)"); \ | |
2885 | else if (GET_CODE (X) == LABEL_REF) \ | |
2886 | fprintf (STREAM, "(GOTOFF)"); \ | |
2887 | else \ | |
2888 | fprintf (STREAM, "(GOT)"); \ | |
2889 | } \ | |
7a801826 RE |
2890 | } |
2891 | ||
62dd06ea RE |
2892 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2893 | Used for C++ multiple inheritance. */ | |
62b10bbc NC |
2894 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2895 | do \ | |
2896 | { \ | |
2897 | int mi_delta = (DELTA); \ | |
6354dc9b | 2898 | const char * mi_op = mi_delta < 0 ? "sub" : "add"; \ |
62b10bbc NC |
2899 | int shift = 0; \ |
2900 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ | |
2901 | ? 1 : 0); \ | |
b1801c02 NC |
2902 | if (mi_delta < 0) \ |
2903 | mi_delta = - mi_delta; \ | |
62b10bbc NC |
2904 | while (mi_delta != 0) \ |
2905 | { \ | |
b1801c02 | 2906 | if ((mi_delta & (3 << shift)) == 0) \ |
62b10bbc NC |
2907 | shift += 2; \ |
2908 | else \ | |
2909 | { \ | |
dd18ae56 NC |
2910 | asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \ |
2911 | mi_op, this_regno, this_regno, \ | |
6cfc7210 | 2912 | mi_delta & (0xff << shift)); \ |
62b10bbc NC |
2913 | mi_delta &= ~(0xff << shift); \ |
2914 | shift += 8; \ | |
2915 | } \ | |
2916 | } \ | |
2917 | fputs ("\tb\t", FILE); \ | |
2918 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
dd18ae56 | 2919 | if (NEED_PLT_RELOC) \ |
62b10bbc NC |
2920 | fputs ("(PLT)", FILE); \ |
2921 | fputc ('\n', FILE); \ | |
2922 | } \ | |
2923 | while (0) | |
39950dff | 2924 | |
6a5d7526 MS |
2925 | /* A C expression whose value is RTL representing the value of the return |
2926 | address for the frame COUNT steps up from the current frame. */ | |
2927 | ||
d5b7b3ae RE |
2928 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2929 | arm_return_addr (COUNT, FRAME) | |
2930 | ||
2931 | /* Mask of the bits in the PC that contain the real return address | |
2932 | when running in 26-bit mode. */ | |
2933 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2934 | |
2c849145 JM |
2935 | /* Pick up the return address upon entry to a procedure. Used for |
2936 | dwarf2 unwind information. This also enables the table driven | |
2937 | mechanism. */ | |
2c849145 JM |
2938 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2939 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2940 | ||
39950dff MS |
2941 | /* Used to mask out junk bits from the return address, such as |
2942 | processor state, interrupt status, condition codes and the like. */ | |
2943 | #define MASK_RETURN_ADDR \ | |
2944 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2945 | in 26 bit mode, the condition codes must be masked out of the \ | |
2946 | return address. This does not apply to ARM6 and later processors \ | |
2947 | when running in 32 bit mode. */ \ | |
d5b7b3ae RE |
2948 | ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \ |
2949 | : (GEN_INT ((unsigned long)0xffffffff))) | |
2950 | ||
2951 | \f | |
2952 | /* Define the codes that are matched by predicates in arm.c */ | |
2953 | #define PREDICATE_CODES \ | |
2954 | {"s_register_operand", {SUBREG, REG}}, \ | |
b15bca31 | 2955 | {"arm_hard_register_operand", {REG}}, \ |
d5b7b3ae RE |
2956 | {"f_register_operand", {SUBREG, REG}}, \ |
2957 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2958 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2959 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2960 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
2961 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
2962 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ | |
2963 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
2964 | {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ | |
2965 | {"offsettable_memory_operand", {MEM}}, \ | |
2966 | {"bad_signed_byte_operand", {MEM}}, \ | |
2967 | {"alignable_memory_operand", {MEM}}, \ | |
2968 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ | |
2969 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
2970 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ | |
2971 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ | |
2972 | {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ | |
2973 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ | |
2974 | {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ | |
2975 | {"load_multiple_operation", {PARALLEL}}, \ | |
2976 | {"store_multiple_operation", {PARALLEL}}, \ | |
2977 | {"equality_operator", {EQ, NE}}, \ | |
e45b72c4 RE |
2978 | {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ |
2979 | LTU, UNORDERED, ORDERED, UNLT, UNLE, \ | |
2980 | UNGE, UNGT}}, \ | |
d5b7b3ae RE |
2981 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2982 | {"const_shift_operand", {CONST_INT}}, \ | |
2983 | {"multi_register_push", {PARALLEL}}, \ | |
2984 | {"cc_register", {REG}}, \ | |
2985 | {"logical_binary_operator", {AND, IOR, XOR}}, \ | |
2986 | {"dominant_cc_register", {REG}}, | |
71791e16 | 2987 | |
ad027eae RE |
2988 | /* Define this if you have special predicates that know special things |
2989 | about modes. Genrecog will warn about certain forms of | |
2990 | match_operand without a mode; if the operand predicate is listed in | |
2991 | SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ | |
2992 | #define SPECIAL_MODE_PREDICATES \ | |
2993 | "cc_register", "dominant_cc_register", | |
2994 | ||
d19fb8e3 NC |
2995 | enum arm_builtins |
2996 | { | |
2997 | ARM_BUILTIN_CLZ, | |
2998 | ARM_BUILTIN_PREFETCH, | |
2999 | ARM_BUILTIN_MAX | |
3000 | }; | |
3001 | ||
3002 | #define MD_INIT_BUILTINS \ | |
3003 | do \ | |
3004 | { \ | |
3005 | arm_init_builtins (); \ | |
3006 | } \ | |
3007 | while (0) | |
3008 | ||
3009 | #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \ | |
3010 | arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE)) | |
b355a481 | 3011 | #endif /* __ARM_H__ */ |