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c54c7322 RS |
1 | ; Options for the ARM port of the compiler. |
2 | ||
99dee823 | 3 | ; Copyright (C) 2005-2021 Free Software Foundation, Inc. |
c54c7322 RS |
4 | ; |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 9 | ; Software Foundation; either version 3, or (at your option) any later |
c54c7322 RS |
10 | ; version. |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | ; for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ; along with GCC; see the file COPYING3. If not see |
19 | ; <http://www.gnu.org/licenses/>. | |
c54c7322 | 20 | |
ad7be009 JM |
21 | HeaderInclude |
22 | config/arm/arm-opts.h | |
23 | ||
ccdc2164 NS |
24 | Enum |
25 | Name(tls_type) Type(enum arm_tls_type) | |
26 | TLS dialect to use: | |
27 | ||
28 | EnumValue | |
29 | Enum(tls_type) String(gnu) Value(TLS_GNU) | |
30 | ||
31 | EnumValue | |
32 | Enum(tls_type) String(gnu2) Value(TLS_GNU2) | |
33 | ||
c54c7322 | 34 | mabi= |
ba163417 | 35 | Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI) |
a7b2e184 | 36 | Specify an ABI. |
c54c7322 | 37 | |
ba163417 JM |
38 | Enum |
39 | Name(arm_abi_type) Type(enum arm_abi_type) | |
40 | Known ARM ABIs (for use with the -mabi= option): | |
41 | ||
42 | EnumValue | |
43 | Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS) | |
44 | ||
45 | EnumValue | |
46 | Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS) | |
47 | ||
48 | EnumValue | |
49 | Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) | |
50 | ||
51 | EnumValue | |
52 | Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) | |
53 | ||
54 | EnumValue | |
55 | Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) | |
56 | ||
c54c7322 | 57 | mabort-on-noreturn |
eece52b5 | 58 | Target Mask(ABORT_NORETURN) |
a7b2e184 | 59 | Generate a call to abort if a noreturn function returns. |
c54c7322 RS |
60 | |
61 | mapcs | |
719e1e80 | 62 | Target RejectNegative Mask(APCS_FRAME) Undocumented |
c54c7322 | 63 | |
c54c7322 | 64 | mapcs-frame |
eece52b5 | 65 | Target Mask(APCS_FRAME) |
a7b2e184 | 66 | Generate APCS conformant stack frames. |
c54c7322 RS |
67 | |
68 | mapcs-reentrant | |
eece52b5 | 69 | Target Mask(APCS_REENT) |
a7b2e184 | 70 | Generate re-entrant, PIC code. |
c54c7322 RS |
71 | |
72 | mapcs-stack-check | |
eece52b5 | 73 | Target Mask(APCS_STACK) Undocumented |
c54c7322 RS |
74 | |
75 | march= | |
d106029c | 76 | Target Save RejectNegative Negative(march=) ToLower Joined Var(arm_arch_string) |
a7b2e184 | 77 | Specify the name of the target architecture. |
c54c7322 | 78 | |
33aa08b3 AS |
79 | ; Other arm_arch values are loaded from arm-tables.opt |
80 | ; but that is a generated file and this is an odd-one-out. | |
81 | EnumValue | |
82 | Enum(arm_arch) String(native) Value(-1) DriverOnly | |
83 | ||
c54c7322 | 84 | marm |
eece52b5 | 85 | Target RejectNegative Negative(mthumb) InverseMask(THUMB) |
ee6824ae | 86 | Generate code in 32 bit ARM state. |
c54c7322 RS |
87 | |
88 | mbig-endian | |
eece52b5 | 89 | Target RejectNegative Negative(mlittle-endian) Mask(BIG_END) |
a7b2e184 | 90 | Assume target CPU is configured as big endian. |
c54c7322 RS |
91 | |
92 | mcallee-super-interworking | |
eece52b5 | 93 | Target Mask(CALLEE_INTERWORKING) |
a7b2e184 | 94 | Thumb: Assume non-static functions may be called from ARM code. |
c54c7322 RS |
95 | |
96 | mcaller-super-interworking | |
eece52b5 | 97 | Target Mask(CALLER_INTERWORKING) |
a7b2e184 | 98 | Thumb: Assume function pointers may go to non-Thumb aware code. |
c54c7322 | 99 | |
c54c7322 | 100 | mcpu= |
d106029c | 101 | Target Save RejectNegative Negative(mcpu=) ToLower Joined Var(arm_cpu_string) |
a7b2e184 | 102 | Specify the name of the target CPU. |
c54c7322 RS |
103 | |
104 | mfloat-abi= | |
ba163417 | 105 | Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) |
a7b2e184 | 106 | Specify if floating point hardware should be used. |
c54c7322 | 107 | |
de7b5723 AV |
108 | mcmse |
109 | Target RejectNegative Var(use_cmse) | |
110 | Specify that the compiler should target secure code as per ARMv8-M Security Extensions. | |
111 | ||
ba163417 JM |
112 | Enum |
113 | Name(float_abi_type) Type(enum float_abi_type) | |
114 | Known floating-point ABIs (for use with the -mfloat-abi= option): | |
115 | ||
116 | EnumValue | |
117 | Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT) | |
118 | ||
119 | EnumValue | |
120 | Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP) | |
121 | ||
122 | EnumValue | |
123 | Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) | |
124 | ||
e6553050 | 125 | mflip-thumb |
eece52b5 | 126 | Target Var(TARGET_FLIP_THUMB) Undocumented |
a7b2e184 | 127 | Switch ARM/Thumb modes on alternating functions for compiler testing. |
e6553050 | 128 | |
0fd8c3ad | 129 | mfp16-format= |
ba163417 | 130 | Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE) |
a7b2e184 | 131 | Specify the __fp16 floating-point format. |
0fd8c3ad | 132 | |
ba163417 JM |
133 | Enum |
134 | Name(arm_fp16_format_type) Type(enum arm_fp16_format_type) | |
135 | Known __fp16 formats (for use with the -mfp16-format= option): | |
136 | ||
137 | EnumValue | |
138 | Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE) | |
139 | ||
140 | EnumValue | |
141 | Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE) | |
142 | ||
143 | EnumValue | |
144 | Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE) | |
145 | ||
c54c7322 | 146 | mfpu= |
844af767 | 147 | Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Init(TARGET_FPU_auto) Save |
a7b2e184 | 148 | Specify the name of the target floating point hardware/format. |
c54c7322 RS |
149 | |
150 | mhard-float | |
2cdf9574 | 151 | Target RejectNegative Alias(mfloat-abi=, hard) Undocumented |
c54c7322 RS |
152 | |
153 | mlittle-endian | |
eece52b5 | 154 | Target RejectNegative Negative(mbig-endian) InverseMask(BIG_END) |
a7b2e184 | 155 | Assume target CPU is configured as little endian. |
c54c7322 RS |
156 | |
157 | mlong-calls | |
eece52b5 | 158 | Target Mask(LONG_CALLS) |
a7b2e184 | 159 | Generate call insns as indirect calls, if necessary. |
c54c7322 | 160 | |
32d6e6c0 | 161 | mpic-data-is-text-relative |
eece52b5 | 162 | Target Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) |
32d6e6c0 JY |
163 | Assume data segments are relative to text segment. |
164 | ||
c54c7322 | 165 | mpic-register= |
55bea00a | 166 | Target RejectNegative Joined Var(arm_pic_register_string) |
a7b2e184 | 167 | Specify the register to be used for PIC addressing. |
c54c7322 RS |
168 | |
169 | mpoke-function-name | |
eece52b5 | 170 | Target Mask(POKE_FUNCTION_NAME) |
a7b2e184 | 171 | Store function names in object code. |
c54c7322 RS |
172 | |
173 | msched-prolog | |
eece52b5 | 174 | Target Mask(SCHED_PROLOG) |
a7b2e184 | 175 | Permit scheduling of a function's prologue sequence. |
c54c7322 RS |
176 | |
177 | msingle-pic-base | |
eece52b5 | 178 | Target Mask(SINGLE_PIC_BASE) |
a7b2e184 | 179 | Do not load the PIC register in function prologues. |
c54c7322 RS |
180 | |
181 | msoft-float | |
2cdf9574 | 182 | Target RejectNegative Alias(mfloat-abi=, soft) Undocumented |
c54c7322 RS |
183 | |
184 | mstructure-size-boundary= | |
ba163417 | 185 | Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) |
33cd5f8f | 186 | Specify the minimum bit alignment of structures. (Deprecated). |
c54c7322 RS |
187 | |
188 | mthumb | |
eece52b5 | 189 | Target RejectNegative Negative(marm) Mask(THUMB) Save |
a7b2e184 | 190 | Generate code for Thumb state. |
c54c7322 RS |
191 | |
192 | mthumb-interwork | |
eece52b5 | 193 | Target Mask(INTERWORK) |
a7b2e184 | 194 | Support calls between Thumb and ARM instruction sets. |
c54c7322 | 195 | |
ccdc2164 NS |
196 | mtls-dialect= |
197 | Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU) | |
a7b2e184 | 198 | Specify thread local storage scheme. |
ccdc2164 | 199 | |
d3585b76 | 200 | mtp= |
ba163417 | 201 | Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO) |
a7b2e184 | 202 | Specify how to access the thread pointer. |
d3585b76 | 203 | |
ba163417 JM |
204 | Enum |
205 | Name(arm_tp_type) Type(enum arm_tp_type) | |
206 | Valid arguments to -mtp=: | |
207 | ||
208 | EnumValue | |
209 | Enum(arm_tp_type) String(soft) Value(TP_SOFT) | |
210 | ||
211 | EnumValue | |
212 | Enum(arm_tp_type) String(auto) Value(TP_AUTO) | |
213 | ||
214 | EnumValue | |
215 | Enum(arm_tp_type) String(cp15) Value(TP_CP15) | |
216 | ||
c54c7322 | 217 | mtpcs-frame |
eece52b5 | 218 | Target Mask(TPCS_FRAME) |
a7b2e184 | 219 | Thumb: Generate (non-leaf) stack frames even if not needed. |
c54c7322 RS |
220 | |
221 | mtpcs-leaf-frame | |
eece52b5 | 222 | Target Mask(TPCS_LEAF_FRAME) |
a7b2e184 | 223 | Thumb: Generate (leaf) stack frames even if not needed. |
c54c7322 RS |
224 | |
225 | mtune= | |
d106029c | 226 | Target Save RejectNegative Negative(mtune=) ToLower Joined Var(arm_tune_string) |
a7b2e184 | 227 | Tune code for the given processor. |
c54c7322 | 228 | |
2301ca74 | 229 | mprint-tune-info |
eece52b5 | 230 | Target RejectNegative Var(print_tune_info) Init(0) |
2301ca74 BC |
231 | Print CPU tuning information as comment in assembler file. This is |
232 | an option used only for regression testing of the compiler and not | |
233 | intended for ordinary use in compiling code. | |
234 | ||
33aa08b3 AS |
235 | ; Other processor_type values are loaded from arm-tables.opt |
236 | ; but that is a generated file and this is an odd-one-out. | |
237 | EnumValue | |
238 | Enum(processor_type) String(native) Value(-1) DriverOnly | |
239 | ||
88f77cba | 240 | mvectorize-with-neon-quad |
eece52b5 | 241 | Target RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) |
a7b2e184 | 242 | Use Neon quad-word (rather than double-word) registers for vectorization. |
571191af | 243 | |
8f40ccea | 244 | mvectorize-with-neon-double |
eece52b5 | 245 | Target RejectNegative Mask(NEON_VECTORIZE_DOUBLE) |
a7b2e184 | 246 | Use Neon double-word (rather than quad-word) registers for vectorization. |
8f40ccea | 247 | |
636f605c KT |
248 | mverbose-cost-dump |
249 | Common Undocumented Var(arm_verbose_cost) Init(0) | |
250 | Enable more verbose RTX cost dumps during debug. For GCC developers use only. | |
251 | ||
571191af | 252 | mword-relocations |
eece52b5 | 253 | Target Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) |
5fd42423 PB |
254 | Only generate absolute relocations on word sized values. |
255 | ||
9912dbe5 | 256 | mrestrict-it |
eece52b5 | 257 | Target Var(arm_restrict_it) Init(2) Save |
9912dbe5 KT |
258 | Generate IT blocks appropriate for ARMv8. |
259 | ||
5fd42423 | 260 | mfix-cortex-m3-ldrd |
eece52b5 | 261 | Target Var(fix_cm3_ldrd) Init(2) |
5fd42423 PB |
262 | Avoid overlapping destination and address registers on LDRD instructions |
263 | that may trigger Cortex-M3 errata. | |
86b60116 JB |
264 | |
265 | munaligned-access | |
eece52b5 | 266 | Target Var(unaligned_access) Init(2) Save |
86b60116 | 267 | Enable unaligned word and halfword accesses to packed data. |
65074f54 CL |
268 | |
269 | mneon-for-64bits | |
68a57628 | 270 | Target WarnRemoved |
bf1a58e9 | 271 | This option is deprecated and has no effect. |
02231c13 TG |
272 | |
273 | mslow-flash-data | |
eece52b5 | 274 | Target Var(target_slow_flash_data) Init(0) |
02231c13 | 275 | Assume loading data from flash is slower than fetching instructions. |
decfc6e1 TG |
276 | |
277 | masm-syntax-unified | |
eece52b5 | 278 | Target Var(inline_asm_unified) Init(0) Save |
bae4ce0f | 279 | Assume unified syntax for inline assembly code. |
0ee70cc0 AV |
280 | |
281 | mpure-code | |
eece52b5 | 282 | Target Var(target_pure_code) Init(0) |
0ee70cc0 | 283 | Do not allow constant data to be placed in code sections. |
63d03dce RE |
284 | |
285 | mbe8 | |
eece52b5 | 286 | Target RejectNegative Negative(mbe32) Mask(BE8) |
63d03dce RE |
287 | When linking for big-endian targets, generate a BE8 format image. |
288 | ||
289 | mbe32 | |
eece52b5 | 290 | Target RejectNegative Negative(mbe8) InverseMask(BE8) |
63d03dce | 291 | When linking for big-endian targets, generate a legacy BE32 format image. |
227e5798 CL |
292 | |
293 | mbranch-cost= | |
294 | Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1) | |
295 | Cost to assume for a branch insn. | |
48528842 RR |
296 | |
297 | mgeneral-regs-only | |
eece52b5 | 298 | Target RejectNegative Mask(GENERAL_REGS_ONLY) Save |
48528842 | 299 | Generate code which uses the core registers only (r0-r14). |
4563bc4d CL |
300 | |
301 | mfdpic | |
eece52b5 | 302 | Target Mask(FDPIC) |
4563bc4d | 303 | Enable Function Descriptor PIC mode. |