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81f6de2f | 1 | ; Options for the ARM port of the compiler. |
2 | ||
f1717362 | 3 | ; Copyright (C) 2005-2016 Free Software Foundation, Inc. |
81f6de2f | 4 | ; |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
038d1e19 | 9 | ; Software Foundation; either version 3, or (at your option) any later |
81f6de2f | 10 | ; version. |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | ; for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
038d1e19 | 18 | ; along with GCC; see the file COPYING3. If not see |
19 | ; <http://www.gnu.org/licenses/>. | |
81f6de2f | 20 | |
9a4818f1 | 21 | HeaderInclude |
22 | config/arm/arm-opts.h | |
23 | ||
f41e4452 | 24 | Enum |
25 | Name(tls_type) Type(enum arm_tls_type) | |
26 | TLS dialect to use: | |
27 | ||
28 | EnumValue | |
29 | Enum(tls_type) String(gnu) Value(TLS_GNU) | |
30 | ||
31 | EnumValue | |
32 | Enum(tls_type) String(gnu2) Value(TLS_GNU2) | |
33 | ||
81f6de2f | 34 | mabi= |
8bbee4a9 | 35 | Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI) |
8fb42bbc | 36 | Specify an ABI. |
81f6de2f | 37 | |
8bbee4a9 | 38 | Enum |
39 | Name(arm_abi_type) Type(enum arm_abi_type) | |
40 | Known ARM ABIs (for use with the -mabi= option): | |
41 | ||
42 | EnumValue | |
43 | Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS) | |
44 | ||
45 | EnumValue | |
46 | Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS) | |
47 | ||
48 | EnumValue | |
49 | Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) | |
50 | ||
51 | EnumValue | |
52 | Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) | |
53 | ||
54 | EnumValue | |
55 | Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) | |
56 | ||
81f6de2f | 57 | mabort-on-noreturn |
58 | Target Report Mask(ABORT_NORETURN) | |
8fb42bbc | 59 | Generate a call to abort if a noreturn function returns. |
81f6de2f | 60 | |
61 | mapcs | |
367d727c | 62 | Target RejectNegative Mask(APCS_FRAME) Undocumented |
81f6de2f | 63 | |
64 | mapcs-float | |
65 | Target Report Mask(APCS_FLOAT) | |
8fb42bbc | 66 | Pass FP arguments in FP registers. |
81f6de2f | 67 | |
68 | mapcs-frame | |
69 | Target Report Mask(APCS_FRAME) | |
8fb42bbc | 70 | Generate APCS conformant stack frames. |
81f6de2f | 71 | |
72 | mapcs-reentrant | |
73 | Target Report Mask(APCS_REENT) | |
8fb42bbc | 74 | Generate re-entrant, PIC code. |
81f6de2f | 75 | |
76 | mapcs-stack-check | |
77 | Target Report Mask(APCS_STACK) Undocumented | |
78 | ||
79 | march= | |
d5b90111 | 80 | Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option) |
8fb42bbc | 81 | Specify the name of the target architecture. |
81f6de2f | 82 | |
2ae1f0cc | 83 | ; Other arm_arch values are loaded from arm-tables.opt |
84 | ; but that is a generated file and this is an odd-one-out. | |
85 | EnumValue | |
86 | Enum(arm_arch) String(native) Value(-1) DriverOnly | |
87 | ||
81f6de2f | 88 | marm |
d6d485a9 | 89 | Target Report RejectNegative InverseMask(THUMB) |
90 | Generate code in 32 bit ARM state. | |
81f6de2f | 91 | |
92 | mbig-endian | |
93 | Target Report RejectNegative Mask(BIG_END) | |
8fb42bbc | 94 | Assume target CPU is configured as big endian. |
81f6de2f | 95 | |
96 | mcallee-super-interworking | |
97 | Target Report Mask(CALLEE_INTERWORKING) | |
8fb42bbc | 98 | Thumb: Assume non-static functions may be called from ARM code. |
81f6de2f | 99 | |
100 | mcaller-super-interworking | |
101 | Target Report Mask(CALLER_INTERWORKING) | |
8fb42bbc | 102 | Thumb: Assume function pointers may go to non-Thumb aware code. |
81f6de2f | 103 | |
81f6de2f | 104 | mcpu= |
d5b90111 | 105 | Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none) |
8fb42bbc | 106 | Specify the name of the target CPU. |
81f6de2f | 107 | |
108 | mfloat-abi= | |
8bbee4a9 | 109 | Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) |
8fb42bbc | 110 | Specify if floating point hardware should be used. |
81f6de2f | 111 | |
8bbee4a9 | 112 | Enum |
113 | Name(float_abi_type) Type(enum float_abi_type) | |
114 | Known floating-point ABIs (for use with the -mfloat-abi= option): | |
115 | ||
116 | EnumValue | |
117 | Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT) | |
118 | ||
119 | EnumValue | |
120 | Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP) | |
121 | ||
122 | EnumValue | |
123 | Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) | |
124 | ||
967c3489 | 125 | mflip-thumb |
126 | Target Report Var(TARGET_FLIP_THUMB) Undocumented | |
8fb42bbc | 127 | Switch ARM/Thumb modes on alternating functions for compiler testing. |
967c3489 | 128 | |
9b8516be | 129 | mfp16-format= |
8bbee4a9 | 130 | Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE) |
8fb42bbc | 131 | Specify the __fp16 floating-point format. |
9b8516be | 132 | |
8bbee4a9 | 133 | Enum |
134 | Name(arm_fp16_format_type) Type(enum arm_fp16_format_type) | |
135 | Known __fp16 formats (for use with the -mfp16-format= option): | |
136 | ||
137 | EnumValue | |
138 | Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE) | |
139 | ||
140 | EnumValue | |
141 | Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE) | |
142 | ||
143 | EnumValue | |
144 | Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE) | |
145 | ||
81f6de2f | 146 | mfpu= |
783bc931 | 147 | Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Save |
8fb42bbc | 148 | Specify the name of the target floating point hardware/format. |
81f6de2f | 149 | |
150 | mhard-float | |
0670b683 | 151 | Target RejectNegative Alias(mfloat-abi=, hard) Undocumented |
81f6de2f | 152 | |
153 | mlittle-endian | |
154 | Target Report RejectNegative InverseMask(BIG_END) | |
8fb42bbc | 155 | Assume target CPU is configured as little endian. |
81f6de2f | 156 | |
157 | mlong-calls | |
158 | Target Report Mask(LONG_CALLS) | |
8fb42bbc | 159 | Generate call insns as indirect calls, if necessary. |
81f6de2f | 160 | |
720381ff | 161 | mpic-data-is-text-relative |
162 | Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) | |
163 | Assume data segments are relative to text segment. | |
164 | ||
81f6de2f | 165 | mpic-register= |
0fe44c73 | 166 | Target RejectNegative Joined Var(arm_pic_register_string) |
8fb42bbc | 167 | Specify the register to be used for PIC addressing. |
81f6de2f | 168 | |
169 | mpoke-function-name | |
170 | Target Report Mask(POKE_FUNCTION_NAME) | |
8fb42bbc | 171 | Store function names in object code. |
81f6de2f | 172 | |
173 | msched-prolog | |
174 | Target Report Mask(SCHED_PROLOG) | |
8fb42bbc | 175 | Permit scheduling of a function's prologue sequence. |
81f6de2f | 176 | |
177 | msingle-pic-base | |
178 | Target Report Mask(SINGLE_PIC_BASE) | |
8fb42bbc | 179 | Do not load the PIC register in function prologues. |
81f6de2f | 180 | |
181 | msoft-float | |
0670b683 | 182 | Target RejectNegative Alias(mfloat-abi=, soft) Undocumented |
81f6de2f | 183 | |
184 | mstructure-size-boundary= | |
8bbee4a9 | 185 | Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) |
8fb42bbc | 186 | Specify the minimum bit alignment of structures. |
81f6de2f | 187 | |
188 | mthumb | |
95f1e0d1 | 189 | Target Report RejectNegative Mask(THUMB) Save |
8fb42bbc | 190 | Generate code for Thumb state. |
81f6de2f | 191 | |
192 | mthumb-interwork | |
193 | Target Report Mask(INTERWORK) | |
8fb42bbc | 194 | Support calls between Thumb and ARM instruction sets. |
81f6de2f | 195 | |
f41e4452 | 196 | mtls-dialect= |
197 | Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU) | |
8fb42bbc | 198 | Specify thread local storage scheme. |
f41e4452 | 199 | |
f655717d | 200 | mtp= |
8bbee4a9 | 201 | Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO) |
8fb42bbc | 202 | Specify how to access the thread pointer. |
f655717d | 203 | |
8bbee4a9 | 204 | Enum |
205 | Name(arm_tp_type) Type(enum arm_tp_type) | |
206 | Valid arguments to -mtp=: | |
207 | ||
208 | EnumValue | |
209 | Enum(arm_tp_type) String(soft) Value(TP_SOFT) | |
210 | ||
211 | EnumValue | |
212 | Enum(arm_tp_type) String(auto) Value(TP_AUTO) | |
213 | ||
214 | EnumValue | |
215 | Enum(arm_tp_type) String(cp15) Value(TP_CP15) | |
216 | ||
81f6de2f | 217 | mtpcs-frame |
218 | Target Report Mask(TPCS_FRAME) | |
8fb42bbc | 219 | Thumb: Generate (non-leaf) stack frames even if not needed. |
81f6de2f | 220 | |
221 | mtpcs-leaf-frame | |
222 | Target Report Mask(TPCS_LEAF_FRAME) | |
8fb42bbc | 223 | Thumb: Generate (leaf) stack frames even if not needed. |
81f6de2f | 224 | |
225 | mtune= | |
d5b90111 | 226 | Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(arm_none) |
8fb42bbc | 227 | Tune code for the given processor. |
81f6de2f | 228 | |
0c2a1f1d | 229 | mprint-tune-info |
230 | Target Report RejectNegative Var(print_tune_info) Init(0) | |
231 | Print CPU tuning information as comment in assembler file. This is | |
232 | an option used only for regression testing of the compiler and not | |
233 | intended for ordinary use in compiling code. | |
234 | ||
2ae1f0cc | 235 | ; Other processor_type values are loaded from arm-tables.opt |
236 | ; but that is a generated file and this is an odd-one-out. | |
237 | EnumValue | |
238 | Enum(processor_type) String(native) Value(-1) DriverOnly | |
239 | ||
d98a3884 | 240 | mvectorize-with-neon-quad |
859baaaf | 241 | Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) |
8fb42bbc | 242 | Use Neon quad-word (rather than double-word) registers for vectorization. |
d0e6a121 | 243 | |
859baaaf | 244 | mvectorize-with-neon-double |
245 | Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) | |
8fb42bbc | 246 | Use Neon double-word (rather than quad-word) registers for vectorization. |
859baaaf | 247 | |
d0e6a121 | 248 | mword-relocations |
249 | Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) | |
1868dd16 | 250 | Only generate absolute relocations on word sized values. |
251 | ||
889fe57c | 252 | mrestrict-it |
95f1e0d1 | 253 | Target Report Var(arm_restrict_it) Init(2) Save |
889fe57c | 254 | Generate IT blocks appropriate for ARMv8. |
255 | ||
8f67eb82 | 256 | mold-rtx-costs |
257 | Target Report Mask(OLD_RTX_COSTS) | |
258 | Use the old RTX costing tables (transitional). | |
259 | ||
260 | mnew-generic-costs | |
261 | Target Report Mask(NEW_GENERIC_COSTS) | |
262 | Use the new generic RTX cost tables if new core-specific cost table not available (transitional). | |
263 | ||
1868dd16 | 264 | mfix-cortex-m3-ldrd |
265 | Target Report Var(fix_cm3_ldrd) Init(2) | |
266 | Avoid overlapping destination and address registers on LDRD instructions | |
267 | that may trigger Cortex-M3 errata. | |
eb04cafb | 268 | |
269 | munaligned-access | |
19965472 | 270 | Target Report Var(unaligned_access) Init(2) Save |
eb04cafb | 271 | Enable unaligned word and halfword accesses to packed data. |
b6779ddc | 272 | |
273 | mneon-for-64bits | |
274 | Target Report RejectNegative Var(use_neon_for_64bits) Init(0) | |
275 | Use Neon to perform 64-bits operations rather than core registers. | |
861033d5 | 276 | |
277 | mslow-flash-data | |
278 | Target Report Var(target_slow_flash_data) Init(0) | |
279 | Assume loading data from flash is slower than fetching instructions. | |
7e3c779e | 280 | |
281 | masm-syntax-unified | |
95f1e0d1 | 282 | Target Report Var(inline_asm_unified) Init(0) Save |
3ef90e77 | 283 | Assume unified syntax for inline assembly code. |