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ce92b223 | 1 | ;; Constraint definitions for ARM and Thumb |
8d9254fc | 2 | ;; Copyright (C) 2006-2020 Free Software Foundation, Inc. |
ce92b223 RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
ce92b223 RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
ce92b223 RE |
20 | |
21 | ;; The following register constraints have been used: | |
dae840fc | 22 | ;; - in ARM/Thumb-2 state: t, w, x, y, z |
f5c630c3 | 23 | ;; - in Thumb state: h, b |
e36dbdfe | 24 | ;; - in both states: l, c, k, q, Cs, Ts, US |
ce92b223 | 25 | ;; In ARM state, 'l' is an alias for 'r' |
dae840fc | 26 | ;; 'f' and 'v' were previously used for FPA and MAVERICK registers. |
ce92b223 RE |
27 | |
28 | ;; The following normal constraints have been used: | |
dae840fc | 29 | ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M |
5b3e6663 | 30 | ;; in Thumb-1 state: I, J, K, L, M, N, O |
dae840fc | 31 | ;; 'H' was previously used for FPA. |
ce92b223 RE |
32 | |
33 | ;; The following multi-letter normal constraints have been used: | |
e009dfb3 MM |
34 | ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di, |
35 | ;; Dt, Dp, Dz, Tu | |
572a49c8 | 36 | ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe |
33203b4c | 37 | ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra, |
7a5fffa5 | 38 | ;; Rg, Ri |
a968a40c | 39 | ;; in all states: Pf, Pg |
ce92b223 RE |
40 | |
41 | ;; The following memory constraints have been used: | |
c7be0832 | 42 | ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf |
5b3e6663 | 43 | ;; in ARM state: Uq |
86b60116 | 44 | ;; in Thumb state: Uu, Uw |
84c20253 | 45 | ;; in all states: Q |
ce92b223 | 46 | |
63c8f7d6 SP |
47 | (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS" |
48 | "MVE VPR register") | |
ce92b223 | 49 | |
c7be0832 SP |
50 | (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS" |
51 | "MVE FPCCR register") | |
52 | ||
6df4618c SP |
53 | (define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS" |
54 | "MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8}, | |
55 | @code{r10}, @code{r12}, @code{r14}") | |
56 | ||
4be8cf77 SP |
57 | (define_constraint "Rd" |
58 | "@internal In Thumb-2 state a constant in range 1 to 16" | |
59 | (and (match_code "const_int") | |
60 | (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16"))) | |
61 | ||
33203b4c SP |
62 | (define_constraint "Ra" |
63 | "@internal In Thumb-2 state a constant in range 0 to 7" | |
64 | (and (match_code "const_int") | |
65 | (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 7"))) | |
66 | ||
f166a8cd SP |
67 | (define_constraint "Rb" |
68 | "@internal In Thumb-2 state a constant in range 1 to 8" | |
69 | (and (match_code "const_int") | |
70 | (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8"))) | |
71 | ||
8165795c SP |
72 | (define_constraint "Rc" |
73 | "@internal In Thumb-2 state a constant in range 0 to 15" | |
74 | (and (match_code "const_int") | |
75 | (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 15"))) | |
76 | ||
77 | (define_constraint "Re" | |
78 | "@internal In Thumb-2 state a constant in range 0 to 31" | |
79 | (and (match_code "const_int") | |
80 | (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 31"))) | |
81 | ||
f166a8cd SP |
82 | (define_constraint "Rf" |
83 | "@internal In Thumb-2 state a constant in range 1 to 32" | |
84 | (and (match_code "const_int") | |
85 | (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32"))) | |
86 | ||
33203b4c SP |
87 | (define_constraint "Rg" |
88 | "@internal In Thumb-2 state a constant is one among 1, 2, 4 and 8" | |
89 | (and (match_code "const_int") | |
90 | (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) | |
91 | || (ival == 4) || (ival == 8))"))) | |
92 | ||
7a5fffa5 SP |
93 | ;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. |
94 | (define_predicate "mve_vldrd_immediate" | |
95 | (match_test "satisfies_constraint_Ri (op)")) | |
96 | ||
f1adb0a9 JB |
97 | (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" |
98 | "The VFP registers @code{s0}-@code{s31}.") | |
99 | ||
f1adb0a9 | 100 | (define_register_constraint "w" |
302c3d8e | 101 | "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS" |
f1adb0a9 JB |
102 | "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.") |
103 | ||
104 | (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS" | |
105 | "The VFP registers @code{d0}-@code{d7}.") | |
ce92b223 RE |
106 | |
107 | (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" | |
108 | "The Intel iWMMX co-processor registers.") | |
109 | ||
110 | (define_register_constraint "z" | |
111 | "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" | |
112 | "The Intel iWMMX GR registers.") | |
113 | ||
114 | (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" | |
115 | "In Thumb state the core registers @code{r0}-@code{r7}.") | |
116 | ||
117 | (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" | |
118 | "In Thumb state the core registers @code{r8}-@code{r15}.") | |
119 | ||
d58bc084 NS |
120 | (define_constraint "j" |
121 | "A constant suitable for a MOVW instruction. (ARM/Thumb-2)" | |
33427b46 | 122 | (and (match_test "TARGET_HAVE_MOVT") |
6ce43645 RL |
123 | (ior (and (match_code "high") |
124 | (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))")) | |
d58bc084 NS |
125 | (and (match_code "const_int") |
126 | (match_test "(ival & 0xffff0000) == 0"))))) | |
127 | ||
c2b640a7 AS |
128 | (define_constraint "Pj" |
129 | "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)" | |
130 | (and (match_code "const_int") | |
131 | (and (match_test "TARGET_THUMB2") | |
132 | (match_test "(ival & 0xfffff000) == 0")))) | |
133 | ||
134 | (define_constraint "PJ" | |
135 | "@internal A constant that satisfies the Pj constrant if negated." | |
136 | (and (match_code "const_int") | |
137 | (and (match_test "TARGET_THUMB2") | |
138 | (match_test "((-ival) & 0xfffff000) == 0")))) | |
139 | ||
f5c630c3 PB |
140 | (define_register_constraint "k" "STACK_REG" |
141 | "@internal The stack register.") | |
ce92b223 RE |
142 | |
143 | (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" | |
144 | "@internal | |
145 | Thumb only. The union of the low registers and the stack register.") | |
146 | ||
0be72bfa RH |
147 | (define_constraint "c" |
148 | "@internal The condition code register." | |
149 | (match_operand 0 "cc_register")) | |
ce92b223 | 150 | |
9adcfa3c RR |
151 | (define_register_constraint "Cs" "CALLER_SAVE_REGS" |
152 | "@internal The caller save registers. Useful for sibcalls.") | |
153 | ||
ce92b223 | 154 | (define_constraint "I" |
5b3e6663 PB |
155 | "In ARM/Thumb-2 state a constant that can be used as an immediate value in a |
156 | Data Processing instruction. In Thumb-1 state a constant in the range | |
157 | 0-255." | |
ce92b223 | 158 | (and (match_code "const_int") |
5b3e6663 | 159 | (match_test "TARGET_32BIT ? const_ok_for_arm (ival) |
ce92b223 RE |
160 | : ival >= 0 && ival <= 255"))) |
161 | ||
162 | (define_constraint "J" | |
5b3e6663 PB |
163 | "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1 |
164 | state a constant in the range @minus{}255-@minus{}1." | |
ce92b223 | 165 | (and (match_code "const_int") |
5b3e6663 | 166 | (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095) |
ce92b223 RE |
167 | : (ival >= -255 && ival <= -1)"))) |
168 | ||
169 | (define_constraint "K" | |
5b3e6663 PB |
170 | "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if |
171 | inverted. In Thumb-1 state a constant that satisfies the @code{I} | |
172 | constraint multiplied by any power of 2." | |
ce92b223 | 173 | (and (match_code "const_int") |
5b3e6663 | 174 | (match_test "TARGET_32BIT ? const_ok_for_arm (~ival) |
ce92b223 RE |
175 | : thumb_shiftable_const (ival)"))) |
176 | ||
177 | (define_constraint "L" | |
5b3e6663 PB |
178 | "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if |
179 | negated. In Thumb-1 state a constant in the range @minus{}7-7." | |
ce92b223 | 180 | (and (match_code "const_int") |
5b3e6663 | 181 | (match_test "TARGET_32BIT ? const_ok_for_arm (-ival) |
ce92b223 RE |
182 | : (ival >= -7 && ival <= 7)"))) |
183 | ||
184 | ;; The ARM state version is internal... | |
5b3e6663 PB |
185 | ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any |
186 | ;; power of 2. | |
ce92b223 | 187 | (define_constraint "M" |
5b3e6663 | 188 | "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020." |
ce92b223 | 189 | (and (match_code "const_int") |
5b3e6663 | 190 | (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32) |
29b40d79 | 191 | || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0)) |
16737e76 | 192 | : ival >= 0 && ival <= 1020 && (ival & 3) == 0"))) |
ce92b223 RE |
193 | |
194 | (define_constraint "N" | |
d58bc084 | 195 | "Thumb-1 state a constant in the range 0-31." |
ce92b223 | 196 | (and (match_code "const_int") |
d58bc084 | 197 | (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)"))) |
ce92b223 RE |
198 | |
199 | (define_constraint "O" | |
5b3e6663 | 200 | "In Thumb-1 state a constant that is a multiple of 4 in the range |
ce92b223 RE |
201 | @minus{}508-508." |
202 | (and (match_code "const_int") | |
5b3e6663 | 203 | (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508 |
ce92b223 RE |
204 | && ((ival & 3) == 0)"))) |
205 | ||
81beb031 RE |
206 | (define_constraint "Pa" |
207 | "@internal In Thumb-1 state a constant in the range -510 to +510" | |
208 | (and (match_code "const_int") | |
209 | (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510 | |
210 | && (ival > 255 || ival < -255)"))) | |
211 | ||
212 | (define_constraint "Pb" | |
213 | "@internal In Thumb-1 state a constant in the range -262 to +262" | |
214 | (and (match_code "const_int") | |
215 | (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262 | |
216 | && (ival > 255 || ival < -255)"))) | |
217 | ||
16737e76 BS |
218 | (define_constraint "Pc" |
219 | "@internal In Thumb-1 state a constant that is in the range 1021 to 1275" | |
220 | (and (match_code "const_int") | |
221 | (match_test "TARGET_THUMB1 | |
222 | && ival > 1020 && ival <= 1275"))) | |
223 | ||
906668bb | 224 | (define_constraint "Pd" |
5e5f7673 | 225 | "@internal In Thumb state a constant in the range 0 to 7" |
906668bb | 226 | (and (match_code "const_int") |
5e5f7673 | 227 | (match_test "TARGET_THUMB && ival >= 0 && ival <= 7"))) |
906668bb | 228 | |
572a49c8 JY |
229 | (define_constraint "Pe" |
230 | "@internal In Thumb-1 state a constant in the range 256 to +510" | |
231 | (and (match_code "const_int") | |
232 | (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510"))) | |
233 | ||
84c20253 TP |
234 | (define_constraint "Pf" |
235 | "Memory models except relaxed, consume or release ones." | |
236 | (and (match_code "const_int") | |
237 | (match_test "!is_mm_relaxed (memmodel_from_int (ival)) | |
238 | && !is_mm_consume (memmodel_from_int (ival)) | |
239 | && !is_mm_release (memmodel_from_int (ival))"))) | |
240 | ||
a968a40c MI |
241 | (define_constraint "Pg" |
242 | "@internal In Thumb-2 state a constant in range 1 to 32" | |
243 | (and (match_code "const_int") | |
244 | (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) | |
245 | ||
85f28bf1 JB |
246 | (define_constraint "Ps" |
247 | "@internal In Thumb-2 state a constant in the range -255 to +255" | |
248 | (and (match_code "const_int") | |
249 | (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255"))) | |
250 | ||
251 | (define_constraint "Pt" | |
252 | "@internal In Thumb-2 state a constant in the range -7 to +7" | |
253 | (and (match_code "const_int") | |
254 | (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7"))) | |
255 | ||
ee4e1706 WG |
256 | (define_constraint "Pu" |
257 | "@internal In Thumb-2 state a constant in the range +1 to +8" | |
258 | (and (match_code "const_int") | |
259 | (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8"))) | |
260 | ||
dcd8b2ee JB |
261 | (define_constraint "Pv" |
262 | "@internal In Thumb-2 state a constant in the range -255 to 0" | |
263 | (and (match_code "const_int") | |
264 | (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0"))) | |
265 | ||
e6bfe8a2 RE |
266 | (define_constraint "Pw" |
267 | "@internal In Thumb-2 state a constant in the range -255 to -1" | |
268 | (and (match_code "const_int") | |
269 | (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1"))) | |
270 | ||
271 | (define_constraint "Px" | |
272 | "@internal In Thumb-2 state a constant in the range -7 to -1" | |
273 | (and (match_code "const_int") | |
274 | (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1"))) | |
275 | ||
4925d0d5 WG |
276 | (define_constraint "Py" |
277 | "@internal In Thumb-2 state a constant in the range 0 to 255" | |
278 | (and (match_code "const_int") | |
279 | (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255"))) | |
280 | ||
5e5f7673 KT |
281 | (define_constraint "Pz" |
282 | "@internal In Thumb-2 state the constant 0" | |
283 | (and (match_code "const_int") | |
284 | (match_test "TARGET_THUMB2 && (ival == 0)"))) | |
285 | ||
ce92b223 | 286 | (define_constraint "G" |
dae840fc | 287 | "In ARM/Thumb-2 state the floating-point constant 0." |
ce92b223 | 288 | (and (match_code "const_double") |
5b3e6663 | 289 | (match_test "TARGET_32BIT && arm_const_double_rtx (op)"))) |
ce92b223 | 290 | |
8d33eae8 TP |
291 | (define_constraint "Ha" |
292 | "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed." | |
293 | (and (match_code "const_double") | |
294 | (match_test "satisfies_constraint_E (op)") | |
295 | (match_test "!arm_disable_literal_pool"))) | |
296 | ||
5bfc5baa JB |
297 | (define_constraint "Dz" |
298 | "@internal | |
299 | In ARM/Thumb-2 state a vector of constant zeros." | |
300 | (and (match_code "const_vector") | |
301 | (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) | |
302 | ||
ce92b223 RE |
303 | (define_constraint "Da" |
304 | "@internal | |
5b3e6663 | 305 | In ARM/Thumb-2 state a const_int, const_double or const_vector that can |
ce92b223 RE |
306 | be generated with two Data Processing insns." |
307 | (and (match_code "const_double,const_int,const_vector") | |
5b3e6663 | 308 | (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2"))) |
ce92b223 RE |
309 | |
310 | (define_constraint "Db" | |
311 | "@internal | |
5b3e6663 | 312 | In ARM/Thumb-2 state a const_int, const_double or const_vector that can |
ce92b223 RE |
313 | be generated with three Data Processing insns." |
314 | (and (match_code "const_double,const_int,const_vector") | |
5b3e6663 | 315 | (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3"))) |
ce92b223 RE |
316 | |
317 | (define_constraint "Dc" | |
318 | "@internal | |
5b3e6663 | 319 | In ARM/Thumb-2 state a const_int, const_double or const_vector that can |
ce92b223 RE |
320 | be generated with four Data Processing insns. This pattern is disabled |
321 | if optimizing for space or when we have load-delay slots to fill." | |
322 | (and (match_code "const_double,const_int,const_vector") | |
5b3e6663 | 323 | (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 |
ce92b223 RE |
324 | && !(optimize_size || arm_ld_sched)"))) |
325 | ||
44cd6810 WG |
326 | (define_constraint "Dd" |
327 | "@internal | |
328 | In ARM/Thumb-2 state a const_int that can be used by insn adddi." | |
329 | (and (match_code "const_int") | |
330 | (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)"))) | |
331 | ||
73160ba9 DJ |
332 | (define_constraint "Di" |
333 | "@internal | |
334 | In ARM/Thumb-2 state a const_int or const_double where both the high | |
335 | and low SImode words can be generated as immediates in 32-bit instructions." | |
336 | (and (match_code "const_double,const_int") | |
337 | (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)"))) | |
338 | ||
e009dfb3 | 339 | (define_constraint "Dm" |
88f77cba | 340 | "@internal |
e009dfb3 MM |
341 | In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov |
342 | immediate instruction." | |
343 | (and (match_code "const_vector") | |
88f77cba JB |
344 | (match_test "TARGET_32BIT |
345 | && imm_for_neon_mov_operand (op, GET_MODE (op))"))) | |
346 | ||
e009dfb3 MM |
347 | (define_constraint "Dn" |
348 | "@internal | |
349 | In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov | |
350 | immediate instruction." | |
351 | (and (match_code "const_int") | |
352 | (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)"))) | |
353 | ||
354 | (define_constraint "DN" | |
355 | "@internal | |
356 | In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov | |
357 | immediate instruction." | |
358 | (and (match_code "const_int") | |
359 | (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)"))) | |
360 | ||
88f77cba JB |
361 | (define_constraint "Dl" |
362 | "@internal | |
363 | In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or | |
364 | vbic instruction." | |
365 | (and (match_code "const_vector") | |
366 | (match_test "TARGET_32BIT | |
367 | && imm_for_neon_logic_operand (op, GET_MODE (op))"))) | |
368 | ||
369 | (define_constraint "DL" | |
370 | "@internal | |
371 | In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or | |
372 | vand instruction." | |
373 | (and (match_code "const_vector") | |
374 | (match_test "TARGET_32BIT | |
375 | && imm_for_neon_inv_logic_operand (op, GET_MODE (op))"))) | |
376 | ||
56289ed2 SD |
377 | (define_constraint "Do" |
378 | "@internal | |
379 | In ARM/Thumb2 state valid offset for an ldrd/strd instruction." | |
380 | (and (match_code "const_int") | |
381 | (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)"))) | |
382 | ||
f1adb0a9 JB |
383 | (define_constraint "Dv" |
384 | "@internal | |
385 | In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts | |
e0dc3601 | 386 | instruction." |
f1adb0a9 JB |
387 | (and (match_code "const_double") |
388 | (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)"))) | |
389 | ||
e0dc3601 PB |
390 | (define_constraint "Dy" |
391 | "@internal | |
392 | In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd | |
393 | instruction." | |
394 | (and (match_code "const_double") | |
395 | (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)"))) | |
396 | ||
c75d51aa | 397 | (define_constraint "Dt" |
7f3d8f56 RR |
398 | "@internal |
399 | In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation" | |
400 | (and (match_code "const_double") | |
00ea1506 | 401 | (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)"))) |
7f3d8f56 | 402 | |
c75d51aa RL |
403 | (define_constraint "Dp" |
404 | "@internal | |
405 | In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation" | |
406 | (and (match_code "const_double") | |
00ea1506 | 407 | (match_test "TARGET_32BIT |
85f5231d | 408 | && vfp3_const_double_for_bits (op) > 0"))) |
c75d51aa | 409 | |
8d33eae8 TP |
410 | (define_constraint "Tu" |
411 | "@internal In ARM / Thumb-2 an integer constant iff literal pools are | |
412 | allowed." | |
413 | (and (match_test "CONSTANT_P (op)") | |
414 | (match_test "!arm_disable_literal_pool"))) | |
415 | ||
956a95a5 KT |
416 | (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS" |
417 | "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.") | |
418 | ||
18f0fe6b RH |
419 | (define_memory_constraint "Ua" |
420 | "@internal | |
421 | An address valid for loading/storing register exclusive" | |
422 | (match_operand 0 "mem_noofs_operand")) | |
423 | ||
aed773a2 CB |
424 | (define_memory_constraint "Uh" |
425 | "@internal | |
426 | An address suitable for byte and half-word loads which does not point inside a constant pool" | |
427 | (and (match_code "mem") | |
428 | (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)"))) | |
429 | ||
88f77cba JB |
430 | (define_memory_constraint "Ut" |
431 | "@internal | |
432 | In ARM/Thumb-2 state an address valid for loading/storing opaque structure | |
433 | types wider than TImode." | |
434 | (and (match_code "mem") | |
435 | (match_test "TARGET_32BIT && neon_struct_mem_operand (op)"))) | |
436 | ||
ce92b223 RE |
437 | (define_memory_constraint "Uv" |
438 | "@internal | |
5b3e6663 | 439 | In ARM/Thumb-2 state a valid VFP load/store address." |
ce92b223 | 440 | (and (match_code "mem") |
5b3e6663 | 441 | (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)"))) |
ce92b223 RE |
442 | |
443 | (define_memory_constraint "Uy" | |
444 | "@internal | |
5b3e6663 | 445 | In ARM/Thumb-2 state a valid iWMMX load/store address." |
ce92b223 | 446 | (and (match_code "mem") |
5b3e6663 | 447 | (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)"))) |
ce92b223 | 448 | |
88f77cba | 449 | (define_memory_constraint "Un" |
dc34db56 PB |
450 | "@internal |
451 | In ARM/Thumb-2 state a valid address for Neon doubleword vector | |
452 | load/store instructions." | |
453 | (and (match_code "mem") | |
33255ae3 | 454 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)"))) |
dc34db56 PB |
455 | |
456 | (define_memory_constraint "Um" | |
88f77cba JB |
457 | "@internal |
458 | In ARM/Thumb-2 state a valid address for Neon element and structure | |
459 | load/store instructions." | |
460 | (and (match_code "mem") | |
33255ae3 | 461 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) |
88f77cba JB |
462 | |
463 | (define_memory_constraint "Us" | |
464 | "@internal | |
465 | In ARM/Thumb-2 state a valid address for non-offset loads/stores of | |
466 | quad-word values in four ARM registers." | |
467 | (and (match_code "mem") | |
33255ae3 | 468 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)"))) |
88f77cba | 469 | |
ce92b223 RE |
470 | (define_memory_constraint "Uq" |
471 | "@internal | |
472 | In ARM state an address valid in ldrsb instructions." | |
473 | (and (match_code "mem") | |
474 | (match_test "TARGET_ARM | |
c6c3dba9 | 475 | && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0), |
aed773a2 CB |
476 | SIGN_EXTEND, 0) |
477 | && !arm_is_constant_pool_ref (op)"))) | |
ce92b223 RE |
478 | |
479 | (define_memory_constraint "Q" | |
480 | "@internal | |
84c20253 | 481 | An address that is a single base register." |
ce92b223 RE |
482 | (and (match_code "mem") |
483 | (match_test "REG_P (XEXP (op, 0))"))) | |
484 | ||
363ee90e WG |
485 | (define_memory_constraint "Uu" |
486 | "@internal | |
487 | In Thumb state an address that is valid in 16bit encoding." | |
488 | (and (match_code "mem") | |
489 | (match_test "TARGET_THUMB | |
490 | && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0), | |
491 | 0)"))) | |
492 | ||
86b60116 JB |
493 | ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p |
494 | ; are actually LDM/STM instructions, so cannot be used to access unaligned | |
495 | ; data. | |
496 | (define_memory_constraint "Uw" | |
497 | "@internal | |
498 | In Thumb state an address that is valid in 16bit encoding, and that can be | |
499 | used for unaligned accesses." | |
500 | (and (match_code "mem") | |
501 | (match_test "TARGET_THUMB | |
502 | && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0), | |
503 | 0) | |
504 | && GET_CODE (XEXP (op, 0)) != POST_INC"))) | |
505 | ||
0b93d3b6 RR |
506 | (define_constraint "US" |
507 | "@internal | |
508 | US is a symbol reference." | |
509 | (match_code "symbol_ref") | |
510 | ) | |
511 | ||
3811581f AV |
512 | (define_memory_constraint "Uz" |
513 | "@internal | |
514 | A memory access that is accessible as an LDC/STC operand" | |
515 | (and (match_code "mem") | |
516 | (match_test "arm_coproc_ldc_stc_legitimate_address (op)"))) | |
517 | ||
ce92b223 RE |
518 | ;; We used to have constraint letters for S and R in ARM state, but |
519 | ;; all uses of these now appear to have been removed. | |
520 | ||
521 | ;; Additionally, we used to have a Q constraint in Thumb state, but | |
522 | ;; this wasn't really a valid memory constraint. Again, all uses of | |
523 | ;; this now seem to have been removed. | |
9adcfa3c | 524 |