[thirdparty/gcc.git] / gcc / config / arm / constraints.md

;; Constraint definitions for ARM and Thumb
;; Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; The following register constraints have been used:
;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
;; - in Thumb state: h, b
;; - in both states: l, c, k
;; In ARM state, 'l' is an alias for 'r'

;; The following normal constraints have been used:
;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
;; in Thumb-1 state: I, J, K, L, M, N, O

;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
;; in Thumb-1 state: Pa, Pb, Pc, Pd
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py

;; The following memory constraints have been used:
;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
;; in ARM state: Uq
;; in Thumb state: Uu, Uw


(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
 "Legacy FPA registers @code{f0}-@code{f7}.")

(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
 "The VFP registers @code{s0}-@code{s31}.")

(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
 "The Cirrus Maverick co-processor registers.")

(define_register_constraint "w"
  "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")

(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
 "The VFP registers @code{d0}-@code{d7}.")

(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
 "The Intel iWMMX co-processor registers.")

(define_register_constraint "z"
 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
 "The Intel iWMMX GR registers.")

(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
 "In Thumb state the core registers @code{r0}-@code{r7}.")

(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
 "In Thumb state the core registers @code{r8}-@code{r15}.")

(define_constraint "j"
 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
 (and (match_test "TARGET_32BIT && arm_arch_thumb2")
      (ior (match_code "high")
	   (and (match_code "const_int")
                (match_test "(ival & 0xffff0000) == 0")))))

(define_constraint "Pj"
 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "(ival & 0xfffff000) == 0"))))

(define_constraint "PJ"
 "@internal A constant that satisfies the Pj constrant if negated."
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "((-ival) & 0xfffff000) == 0"))))

(define_register_constraint "k" "STACK_REG"
 "@internal The stack register.")

(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 "@internal
  Thumb only.  The union of the low registers and the stack register.")

(define_register_constraint "c" "CC_REG"
 "@internal The condition code register.")

(define_constraint "I"
 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  Data Processing instruction.  In Thumb-1 state a constant in the range
  0-255."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
		   : ival >= 0 && ival <= 255")))

(define_constraint "J"
 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  state a constant in the range @minus{}255-@minus{}1."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
		   : (ival >= -255 && ival <= -1)")))

(define_constraint "K"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  inverted.  In Thumb-1 state a constant that satisfies the @code{I}
  constraint multiplied by any power of 2."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
		   : thumb_shiftable_const (ival)")))

(define_constraint "L"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
		   : (ival >= -7 && ival <= 7)")))

;; The ARM state version is internal...
;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
;; power of 2.
(define_constraint "M"
 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
				 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
		   : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))

(define_constraint "N"
 "Thumb-1 state a constant in the range 0-31."
 (and (match_code "const_int")
      (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))

(define_constraint "O"
 "In Thumb-1 state a constant that is a multiple of 4 in the range
  @minus{}508-508."
 (and (match_code "const_int")
      (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
		   && ((ival & 3) == 0)")))

(define_constraint "Pa"
  "@internal In Thumb-1 state a constant in the range -510 to +510"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pb"
  "@internal In Thumb-1 state a constant in the range -262 to +262"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pc"
  "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1
  		    && ival > 1020 && ival <= 1275")))

(define_constraint "Pd"
  "@internal In Thumb-1 state a constant in the range 0 to 7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))

(define_constraint "Ps"
  "@internal In Thumb-2 state a constant in the range -255 to +255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))

(define_constraint "Pt"
  "@internal In Thumb-2 state a constant in the range -7 to +7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))

(define_constraint "Pu"
  "@internal In Thumb-2 state a constant in the range +1 to +8"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))

(define_constraint "Pv"
  "@internal In Thumb-2 state a constant in the range -255 to 0"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))

(define_constraint "Pw"
  "@internal In Thumb-2 state a constant in the range -255 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))

(define_constraint "Px"
  "@internal In Thumb-2 state a constant in the range -7 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))

(define_constraint "Py"
  "@internal In Thumb-2 state a constant in the range 0 to 255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))

(define_constraint "G"
 "In ARM/Thumb-2 state a valid FPA immediate constant."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))

(define_constraint "H"
 "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))

(define_constraint "Dz"
 "@internal
  In ARM/Thumb-2 state a vector of constant zeros."
 (and (match_code "const_vector")
      (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))

(define_constraint "Da"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with two Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))

(define_constraint "Db"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with three Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))

(define_constraint "Dc"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with four Data Processing insns.  This pattern is disabled
  if optimizing for space or when we have load-delay slots to fill."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
		   && !(optimize_size || arm_ld_sched)")))

(define_constraint "Di"
 "@internal
  In ARM/Thumb-2 state a const_int or const_double where both the high
  and low SImode words can be generated as immediates in 32-bit instructions."
 (and (match_code "const_double,const_int")
      (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))

(define_constraint "Dn"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
  immediate instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_mov_operand (op, GET_MODE (op))")))

(define_constraint "Dl"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
  vbic instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_logic_operand (op, GET_MODE (op))")))

(define_constraint "DL"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
  vand instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))

(define_constraint "Dv"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))

(define_constraint "Dy"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))

(define_constraint "Dt" 
 "@internal
  In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
  (and (match_code "const_double")
       (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))

(define_memory_constraint "Ut"
 "@internal
  In ARM/Thumb-2 state an address valid for loading/storing opaque structure
  types wider than TImode."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))

(define_memory_constraint "Uv"
 "@internal
  In ARM/Thumb-2 state a valid VFP load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))

(define_memory_constraint "Uy"
 "@internal
  In ARM/Thumb-2 state a valid iWMMX load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))

(define_memory_constraint "Un"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon doubleword vector
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))

(define_memory_constraint "Um"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon element and structure
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))

(define_memory_constraint "Us"
 "@internal
  In ARM/Thumb-2 state a valid address for non-offset loads/stores of
  quad-word values in four ARM registers."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))

(define_memory_constraint "Uq"
 "@internal
  In ARM state an address valid in ldrsb instructions."
 (and (match_code "mem")
      (match_test "TARGET_ARM
		   && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
						      SIGN_EXTEND, 0)")))

(define_memory_constraint "Q"
 "@internal
  In ARM/Thumb-2 state an address that is a single base register."
 (and (match_code "mem")
      (match_test "REG_P (XEXP (op, 0))")))

(define_memory_constraint "Uu"
 "@internal
  In Thumb state an address that is valid in 16bit encoding."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)")))

; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
; are actually LDM/STM instructions, so cannot be used to access unaligned
; data.
(define_memory_constraint "Uw"
 "@internal
  In Thumb state an address that is valid in 16bit encoding, and that can be
  used for unaligned accesses."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)
		   && GET_CODE (XEXP (op, 0)) != POST_INC")))

;; We used to have constraint letters for S and R in ARM state, but
;; all uses of these now appear to have been removed.

;; Additionally, we used to have a Q constraint in Thumb state, but
;; this wasn't really a valid memory constraint.  Again, all uses of
;; this now seem to have been removed.
Commit	Line	Data
ce92b223	1	;; Constraint definitions for ARM and Thumb
d652f226	2	;; Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
ce92b223 RE	3	;; Contributed by ARM Ltd.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
2f83c7d6	9	;; by the Free Software Foundation; either version 3, or (at your
ce92b223 RE	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>.
ce92b223 RE	20
ce92b223 RE	21	;; The following register constraints have been used:
f1adb0a9	22	;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
f5c630c3 PB	23	;; - in Thumb state: h, b
f5c630c3 PB	24	;; - in both states: l, c, k
ce92b223 RE	25	;; In ARM state, 'l' is an alias for 'r'
	26
	27	;; The following normal constraints have been used:
d58bc084	28	;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
5b3e6663	29	;; in Thumb-1 state: I, J, K, L, M, N, O
ce92b223 RE	30
ce92b223 RE	31	;; The following multi-letter normal constraints have been used:
7f3d8f56	32	;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
906668bb	33	;; in Thumb-1 state: Pa, Pb, Pc, Pd
c2b640a7	34	;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
ce92b223 RE	35
ce92b223 RE	36	;; The following memory constraints have been used:
dc34db56	37	;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
5b3e6663	38	;; in ARM state: Uq
86b60116	39	;; in Thumb state: Uu, Uw
ce92b223 RE	40
	41
	42	(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
	43	"Legacy FPA registers @code{f0}-@code{f7}.")
	44
f1adb0a9 JB	45	(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
	46	"The VFP registers @code{s0}-@code{s31}.")
	47
ce92b223 RE	48	(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
	49	"The Cirrus Maverick co-processor registers.")
	50
f1adb0a9	51	(define_register_constraint "w"
302c3d8e	52	"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
f1adb0a9 JB	53	"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
	54
	55	(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
	56	"The VFP registers @code{d0}-@code{d7}.")
ce92b223 RE	57
	58	(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
	59	"The Intel iWMMX co-processor registers.")
	60
	61	(define_register_constraint "z"
	62	"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
	63	"The Intel iWMMX GR registers.")
	64
	65	(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
	66	"In Thumb state the core registers @code{r0}-@code{r7}.")
	67
	68	(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
	69	"In Thumb state the core registers @code{r8}-@code{r15}.")
	70
d58bc084 NS	71	(define_constraint "j"
	72	"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
	73	(and (match_test "TARGET_32BIT && arm_arch_thumb2")
	74	(ior (match_code "high")
	75	(and (match_code "const_int")
	76	(match_test "(ival & 0xffff0000) == 0")))))
	77
c2b640a7 AS	78	(define_constraint "Pj"
	79	"@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
	80	(and (match_code "const_int")
	81	(and (match_test "TARGET_THUMB2")
	82	(match_test "(ival & 0xfffff000) == 0"))))
	83
	84	(define_constraint "PJ"
	85	"@internal A constant that satisfies the Pj constrant if negated."
	86	(and (match_code "const_int")
	87	(and (match_test "TARGET_THUMB2")
	88	(match_test "((-ival) & 0xfffff000) == 0"))))
	89
f5c630c3 PB	90	(define_register_constraint "k" "STACK_REG"
f5c630c3 PB	91	"@internal The stack register.")
ce92b223 RE	92
	93	(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
	94	"@internal
	95	Thumb only. The union of the low registers and the stack register.")
	96
	97	(define_register_constraint "c" "CC_REG"
a876121d	98	"@internal The condition code register.")
ce92b223 RE	99
ce92b223 RE	100	(define_constraint "I"
5b3e6663 PB	101	"In ARM/Thumb-2 state a constant that can be used as an immediate value in a
	102	Data Processing instruction. In Thumb-1 state a constant in the range
	103	0-255."
ce92b223	104	(and (match_code "const_int")
5b3e6663	105	(match_test "TARGET_32BIT ? const_ok_for_arm (ival)
ce92b223 RE	106	: ival >= 0 && ival <= 255")))
	107
	108	(define_constraint "J"
5b3e6663 PB	109	"In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
5b3e6663 PB	110	state a constant in the range @minus{}255-@minus{}1."
ce92b223	111	(and (match_code "const_int")
5b3e6663	112	(match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
ce92b223 RE	113	: (ival >= -255 && ival <= -1)")))
	114
	115	(define_constraint "K"
5b3e6663 PB	116	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
	117	inverted. In Thumb-1 state a constant that satisfies the @code{I}
	118	constraint multiplied by any power of 2."
ce92b223	119	(and (match_code "const_int")
5b3e6663	120	(match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
ce92b223 RE	121	: thumb_shiftable_const (ival)")))
	122
	123	(define_constraint "L"
5b3e6663 PB	124	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
5b3e6663 PB	125	negated. In Thumb-1 state a constant in the range @minus{}7-7."
ce92b223	126	(and (match_code "const_int")
5b3e6663	127	(match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
ce92b223 RE	128	: (ival >= -7 && ival <= 7)")))
	129
	130	;; The ARM state version is internal...
5b3e6663 PB	131	;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
5b3e6663 PB	132	;; power of 2.
ce92b223	133	(define_constraint "M"
5b3e6663	134	"In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
ce92b223	135	(and (match_code "const_int")
5b3e6663	136	(match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
29b40d79	137	\|\| (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
16737e76	138	: ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
ce92b223 RE	139
ce92b223 RE	140	(define_constraint "N"
d58bc084	141	"Thumb-1 state a constant in the range 0-31."
ce92b223	142	(and (match_code "const_int")
d58bc084	143	(match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
ce92b223 RE	144
ce92b223 RE	145	(define_constraint "O"
5b3e6663	146	"In Thumb-1 state a constant that is a multiple of 4 in the range
ce92b223 RE	147	@minus{}508-508."
ce92b223 RE	148	(and (match_code "const_int")
5b3e6663	149	(match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
ce92b223 RE	150	&& ((ival & 3) == 0)")))
ce92b223 RE	151
81beb031 RE	152	(define_constraint "Pa"
	153	"@internal In Thumb-1 state a constant in the range -510 to +510"
	154	(and (match_code "const_int")
	155	(match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
	156	&& (ival > 255 \|\| ival < -255)")))
	157
	158	(define_constraint "Pb"
	159	"@internal In Thumb-1 state a constant in the range -262 to +262"
	160	(and (match_code "const_int")
	161	(match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
	162	&& (ival > 255 \|\| ival < -255)")))
	163
16737e76 BS	164	(define_constraint "Pc"
	165	"@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
	166	(and (match_code "const_int")
	167	(match_test "TARGET_THUMB1
	168	&& ival > 1020 && ival <= 1275")))
	169
906668bb BS	170	(define_constraint "Pd"
	171	"@internal In Thumb-1 state a constant in the range 0 to 7"
	172	(and (match_code "const_int")
	173	(match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
	174
85f28bf1 JB	175	(define_constraint "Ps"
	176	"@internal In Thumb-2 state a constant in the range -255 to +255"
	177	(and (match_code "const_int")
	178	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
	179
	180	(define_constraint "Pt"
	181	"@internal In Thumb-2 state a constant in the range -7 to +7"
	182	(and (match_code "const_int")
	183	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
	184
ee4e1706 WG	185	(define_constraint "Pu"
	186	"@internal In Thumb-2 state a constant in the range +1 to +8"
	187	(and (match_code "const_int")
	188	(match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
	189
dcd8b2ee JB	190	(define_constraint "Pv"
	191	"@internal In Thumb-2 state a constant in the range -255 to 0"
	192	(and (match_code "const_int")
	193	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
	194
e6bfe8a2 RE	195	(define_constraint "Pw"
	196	"@internal In Thumb-2 state a constant in the range -255 to -1"
	197	(and (match_code "const_int")
	198	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
	199
	200	(define_constraint "Px"
	201	"@internal In Thumb-2 state a constant in the range -7 to -1"
	202	(and (match_code "const_int")
	203	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
	204
4925d0d5 WG	205	(define_constraint "Py"
	206	"@internal In Thumb-2 state a constant in the range 0 to 255"
	207	(and (match_code "const_int")
	208	(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
	209
ce92b223	210	(define_constraint "G"
5b3e6663	211	"In ARM/Thumb-2 state a valid FPA immediate constant."
ce92b223	212	(and (match_code "const_double")
5b3e6663	213	(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
ce92b223 RE	214
ce92b223 RE	215	(define_constraint "H"
5b3e6663	216	"In ARM/Thumb-2 state a valid FPA immediate constant when negated."
ce92b223	217	(and (match_code "const_double")
5b3e6663	218	(match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
ce92b223	219
5bfc5baa JB	220	(define_constraint "Dz"
	221	"@internal
	222	In ARM/Thumb-2 state a vector of constant zeros."
	223	(and (match_code "const_vector")
	224	(match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
	225
ce92b223 RE	226	(define_constraint "Da"
ce92b223 RE	227	"@internal
5b3e6663	228	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	229	be generated with two Data Processing insns."
ce92b223 RE	230	(and (match_code "const_double,const_int,const_vector")
5b3e6663	231	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
ce92b223 RE	232
	233	(define_constraint "Db"
	234	"@internal
5b3e6663	235	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	236	be generated with three Data Processing insns."
ce92b223 RE	237	(and (match_code "const_double,const_int,const_vector")
5b3e6663	238	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
ce92b223 RE	239
	240	(define_constraint "Dc"
	241	"@internal
5b3e6663	242	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	243	be generated with four Data Processing insns. This pattern is disabled
	244	if optimizing for space or when we have load-delay slots to fill."
	245	(and (match_code "const_double,const_int,const_vector")
5b3e6663	246	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
ce92b223 RE	247	&& !(optimize_size \|\| arm_ld_sched)")))
ce92b223 RE	248
73160ba9 DJ	249	(define_constraint "Di"
	250	"@internal
	251	In ARM/Thumb-2 state a const_int or const_double where both the high
	252	and low SImode words can be generated as immediates in 32-bit instructions."
	253	(and (match_code "const_double,const_int")
	254	(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
	255
88f77cba JB	256	(define_constraint "Dn"
	257	"@internal
	258	In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
	259	immediate instruction."
	260	(and (match_code "const_vector")
	261	(match_test "TARGET_32BIT
	262	&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
	263
	264	(define_constraint "Dl"
	265	"@internal
	266	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
	267	vbic instruction."
	268	(and (match_code "const_vector")
	269	(match_test "TARGET_32BIT
	270	&& imm_for_neon_logic_operand (op, GET_MODE (op))")))
	271
	272	(define_constraint "DL"
	273	"@internal
	274	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
	275	vand instruction."
	276	(and (match_code "const_vector")
	277	(match_test "TARGET_32BIT
	278	&& imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
	279
f1adb0a9 JB	280	(define_constraint "Dv"
	281	"@internal
	282	In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
e0dc3601	283	instruction."
f1adb0a9 JB	284	(and (match_code "const_double")
	285	(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
	286
e0dc3601 PB	287	(define_constraint "Dy"
	288	"@internal
	289	In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
	290	instruction."
	291	(and (match_code "const_double")
	292	(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
	293
7f3d8f56 RR	294	(define_constraint "Dt"
	295	"@internal
	296	In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
	297	(and (match_code "const_double")
	298	(match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
	299
88f77cba JB	300	(define_memory_constraint "Ut"
	301	"@internal
	302	In ARM/Thumb-2 state an address valid for loading/storing opaque structure
	303	types wider than TImode."
	304	(and (match_code "mem")
	305	(match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
	306
ce92b223 RE	307	(define_memory_constraint "Uv"
ce92b223 RE	308	"@internal
5b3e6663	309	In ARM/Thumb-2 state a valid VFP load/store address."
ce92b223	310	(and (match_code "mem")
5b3e6663	311	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
ce92b223 RE	312
	313	(define_memory_constraint "Uy"
	314	"@internal
5b3e6663	315	In ARM/Thumb-2 state a valid iWMMX load/store address."
ce92b223	316	(and (match_code "mem")
5b3e6663	317	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
ce92b223	318
88f77cba	319	(define_memory_constraint "Un"
dc34db56 PB	320	"@internal
	321	In ARM/Thumb-2 state a valid address for Neon doubleword vector
	322	load/store instructions."
	323	(and (match_code "mem")
	324	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
	325
	326	(define_memory_constraint "Um"
88f77cba JB	327	"@internal
	328	In ARM/Thumb-2 state a valid address for Neon element and structure
	329	load/store instructions."
	330	(and (match_code "mem")
dc34db56	331	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
88f77cba JB	332
	333	(define_memory_constraint "Us"
	334	"@internal
	335	In ARM/Thumb-2 state a valid address for non-offset loads/stores of
	336	quad-word values in four ARM registers."
	337	(and (match_code "mem")
dc34db56	338	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
88f77cba	339
ce92b223 RE	340	(define_memory_constraint "Uq"
	341	"@internal
	342	In ARM state an address valid in ldrsb instructions."
	343	(and (match_code "mem")
	344	(match_test "TARGET_ARM
c6c3dba9 PB	345	&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
c6c3dba9 PB	346	SIGN_EXTEND, 0)")))
ce92b223 RE	347
	348	(define_memory_constraint "Q"
	349	"@internal
5b3e6663	350	In ARM/Thumb-2 state an address that is a single base register."
ce92b223 RE	351	(and (match_code "mem")
	352	(match_test "REG_P (XEXP (op, 0))")))
	353
363ee90e WG	354	(define_memory_constraint "Uu"
	355	"@internal
	356	In Thumb state an address that is valid in 16bit encoding."
	357	(and (match_code "mem")
	358	(match_test "TARGET_THUMB
	359	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	360	0)")))
	361
86b60116 JB	362	; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
	363	; are actually LDM/STM instructions, so cannot be used to access unaligned
	364	; data.
	365	(define_memory_constraint "Uw"
	366	"@internal
	367	In Thumb state an address that is valid in 16bit encoding, and that can be
	368	used for unaligned accesses."
	369	(and (match_code "mem")
	370	(match_test "TARGET_THUMB
	371	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	372	0)
	373	&& GET_CODE (XEXP (op, 0)) != POST_INC")))
	374
ce92b223 RE	375	;; We used to have constraint letters for S and R in ARM state, but
	376	;; all uses of these now appear to have been removed.
	377
	378	;; Additionally, we used to have a Q constraint in Thumb state, but
	379	;; this wasn't really a valid memory constraint. Again, all uses of
	380	;; this now seem to have been removed.