[thirdparty/gcc.git] / gcc / config / arm / constraints.md

;; Constraint definitions for ARM and Thumb
;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; The following register constraints have been used:
;; - in ARM/Thumb-2 state: t, w, x, y, z
;; - in Thumb state: h, b
;; - in both states: l, c, k, q, US
;; In ARM state, 'l' is an alias for 'r'
;; 'f' and 'v' were previously used for FPA and MAVERICK registers.

;; The following normal constraints have been used:
;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
;; in Thumb-1 state: I, J, K, L, M, N, O
;; 'H' was previously used for FPA.

;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dz
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py

;; The following memory constraints have been used:
;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
;; in ARM state: Uq
;; in Thumb state: Uu, Uw


(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
 "The VFP registers @code{s0}-@code{s31}.")

(define_register_constraint "w"
  "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")

(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
 "The VFP registers @code{d0}-@code{d7}.")

(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
 "The Intel iWMMX co-processor registers.")

(define_register_constraint "z"
 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
 "The Intel iWMMX GR registers.")

(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
 "In Thumb state the core registers @code{r0}-@code{r7}.")

(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
 "In Thumb state the core registers @code{r8}-@code{r15}.")

(define_constraint "j"
 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
 (and (match_test "TARGET_32BIT && arm_arch_thumb2")
      (ior (match_code "high")
	   (and (match_code "const_int")
                (match_test "(ival & 0xffff0000) == 0")))))

(define_constraint "Pj"
 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "(ival & 0xfffff000) == 0"))))

(define_constraint "PJ"
 "@internal A constant that satisfies the Pj constrant if negated."
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "((-ival) & 0xfffff000) == 0"))))

(define_register_constraint "k" "STACK_REG"
 "@internal The stack register.")

(define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
  "@internal In ARM state with LDRD support, core registers, otherwise general registers.")

(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 "@internal
  Thumb only.  The union of the low registers and the stack register.")

(define_register_constraint "c" "CC_REG"
 "@internal The condition code register.")

(define_register_constraint "Cs" "CALLER_SAVE_REGS"
 "@internal The caller save registers.  Useful for sibcalls.")

(define_constraint "I"
 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  Data Processing instruction.  In Thumb-1 state a constant in the range
  0-255."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
		   : ival >= 0 && ival <= 255")))

(define_constraint "J"
 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  state a constant in the range @minus{}255-@minus{}1."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
		   : (ival >= -255 && ival <= -1)")))

(define_constraint "K"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  inverted.  In Thumb-1 state a constant that satisfies the @code{I}
  constraint multiplied by any power of 2."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
		   : thumb_shiftable_const (ival)")))

(define_constraint "L"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
		   : (ival >= -7 && ival <= 7)")))

;; The ARM state version is internal...
;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
;; power of 2.
(define_constraint "M"
 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
				 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
		   : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))

(define_constraint "N"
 "Thumb-1 state a constant in the range 0-31."
 (and (match_code "const_int")
      (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))

(define_constraint "O"
 "In Thumb-1 state a constant that is a multiple of 4 in the range
  @minus{}508-508."
 (and (match_code "const_int")
      (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
		   && ((ival & 3) == 0)")))

(define_constraint "Pa"
  "@internal In Thumb-1 state a constant in the range -510 to +510"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pb"
  "@internal In Thumb-1 state a constant in the range -262 to +262"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pc"
  "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1
  		    && ival > 1020 && ival <= 1275")))

(define_constraint "Pd"
  "@internal In Thumb state a constant in the range 0 to 7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))

(define_constraint "Pe"
  "@internal In Thumb-1 state a constant in the range 256 to +510"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))

(define_constraint "Ps"
  "@internal In Thumb-2 state a constant in the range -255 to +255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))

(define_constraint "Pt"
  "@internal In Thumb-2 state a constant in the range -7 to +7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))

(define_constraint "Pu"
  "@internal In Thumb-2 state a constant in the range +1 to +8"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))

(define_constraint "Pv"
  "@internal In Thumb-2 state a constant in the range -255 to 0"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))

(define_constraint "Pw"
  "@internal In Thumb-2 state a constant in the range -255 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))

(define_constraint "Px"
  "@internal In Thumb-2 state a constant in the range -7 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))

(define_constraint "Py"
  "@internal In Thumb-2 state a constant in the range 0 to 255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))

(define_constraint "Pz"
  "@internal In Thumb-2 state the constant 0"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && (ival == 0)")))

(define_constraint "G"
 "In ARM/Thumb-2 state the floating-point constant 0."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))

(define_constraint "Dz"
 "@internal
  In ARM/Thumb-2 state a vector of constant zeros."
 (and (match_code "const_vector")
      (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))

(define_constraint "Da"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with two Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))

(define_constraint "Db"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with three Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))

(define_constraint "Dc"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with four Data Processing insns.  This pattern is disabled
  if optimizing for space or when we have load-delay slots to fill."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
		   && !(optimize_size || arm_ld_sched)")))

(define_constraint "Dd"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))

(define_constraint "De"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn anddi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))

(define_constraint "Df"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn iordi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))

(define_constraint "Dg"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn xordi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))

(define_constraint "Di"
 "@internal
  In ARM/Thumb-2 state a const_int or const_double where both the high
  and low SImode words can be generated as immediates in 32-bit instructions."
 (and (match_code "const_double,const_int")
      (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))

(define_constraint "Dn"
 "@internal
  In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
  Neon vmov immediate instruction."
 (and (match_code "const_vector,const_int")
      (match_test "TARGET_32BIT
		   && imm_for_neon_mov_operand (op, GET_MODE (op))")))

(define_constraint "Dl"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
  vbic instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_logic_operand (op, GET_MODE (op))")))

(define_constraint "DL"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
  vand instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))

(define_constraint "Do"
 "@internal
  In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 (and (match_code "const_int")
      (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))

(define_constraint "Dv"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))

(define_constraint "Dy"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))

(define_constraint "Dt" 
 "@internal
  In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
  (and (match_code "const_double")
       (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))

(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")

(define_memory_constraint "Ua"
 "@internal
  An address valid for loading/storing register exclusive"
 (match_operand 0 "mem_noofs_operand"))

(define_memory_constraint "Ut"
 "@internal
  In ARM/Thumb-2 state an address valid for loading/storing opaque structure
  types wider than TImode."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))

(define_memory_constraint "Uv"
 "@internal
  In ARM/Thumb-2 state a valid VFP load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))

(define_memory_constraint "Uy"
 "@internal
  In ARM/Thumb-2 state a valid iWMMX load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))

(define_memory_constraint "Un"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon doubleword vector
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))

(define_memory_constraint "Um"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon element and structure
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))

(define_memory_constraint "Us"
 "@internal
  In ARM/Thumb-2 state a valid address for non-offset loads/stores of
  quad-word values in four ARM registers."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))

(define_memory_constraint "Uq"
 "@internal
  In ARM state an address valid in ldrsb instructions."
 (and (match_code "mem")
      (match_test "TARGET_ARM
		   && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
						      SIGN_EXTEND, 0)")))

(define_memory_constraint "Q"
 "@internal
  In ARM/Thumb-2 state an address that is a single base register."
 (and (match_code "mem")
      (match_test "REG_P (XEXP (op, 0))")))

(define_memory_constraint "Uu"
 "@internal
  In Thumb state an address that is valid in 16bit encoding."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)")))

; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
; are actually LDM/STM instructions, so cannot be used to access unaligned
; data.
(define_memory_constraint "Uw"
 "@internal
  In Thumb state an address that is valid in 16bit encoding, and that can be
  used for unaligned accesses."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)
		   && GET_CODE (XEXP (op, 0)) != POST_INC")))

(define_constraint "US"
 "@internal
  US is a symbol reference."
 (match_code "symbol_ref")
)

;; We used to have constraint letters for S and R in ARM state, but
;; all uses of these now appear to have been removed.

;; Additionally, we used to have a Q constraint in Thumb state, but
;; this wasn't really a valid memory constraint.  Again, all uses of
;; this now seem to have been removed.
Commit	Line	Data
ce92b223	1	;; Constraint definitions for ARM and Thumb
d1e082c2	2	;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
ce92b223 RE	3	;; Contributed by ARM Ltd.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
2f83c7d6	9	;; by the Free Software Foundation; either version 3, or (at your
ce92b223 RE	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>.
ce92b223 RE	20
ce92b223 RE	21	;; The following register constraints have been used:
dae840fc	22	;; - in ARM/Thumb-2 state: t, w, x, y, z
f5c630c3	23	;; - in Thumb state: h, b
0b93d3b6	24	;; - in both states: l, c, k, q, US
ce92b223	25	;; In ARM state, 'l' is an alias for 'r'
dae840fc	26	;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
ce92b223 RE	27
ce92b223 RE	28	;; The following normal constraints have been used:
dae840fc	29	;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
5b3e6663	30	;; in Thumb-1 state: I, J, K, L, M, N, O
dae840fc	31	;; 'H' was previously used for FPA.
ce92b223 RE	32
ce92b223 RE	33	;; The following multi-letter normal constraints have been used:
56289ed2	34	;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dz
572a49c8	35	;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
c2b640a7	36	;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
ce92b223 RE	37
ce92b223 RE	38	;; The following memory constraints have been used:
dc34db56	39	;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
5b3e6663	40	;; in ARM state: Uq
86b60116	41	;; in Thumb state: Uu, Uw
ce92b223 RE	42
ce92b223 RE	43
f1adb0a9 JB	44	(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
	45	"The VFP registers @code{s0}-@code{s31}.")
	46
f1adb0a9	47	(define_register_constraint "w"
302c3d8e	48	"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
f1adb0a9 JB	49	"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
	50
	51	(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
	52	"The VFP registers @code{d0}-@code{d7}.")
ce92b223 RE	53
	54	(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
	55	"The Intel iWMMX co-processor registers.")
	56
	57	(define_register_constraint "z"
	58	"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
	59	"The Intel iWMMX GR registers.")
	60
	61	(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
	62	"In Thumb state the core registers @code{r0}-@code{r7}.")
	63
	64	(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
	65	"In Thumb state the core registers @code{r8}-@code{r15}.")
	66
d58bc084 NS	67	(define_constraint "j"
	68	"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
	69	(and (match_test "TARGET_32BIT && arm_arch_thumb2")
	70	(ior (match_code "high")
	71	(and (match_code "const_int")
	72	(match_test "(ival & 0xffff0000) == 0")))))
	73
c2b640a7 AS	74	(define_constraint "Pj"
	75	"@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
	76	(and (match_code "const_int")
	77	(and (match_test "TARGET_THUMB2")
	78	(match_test "(ival & 0xfffff000) == 0"))))
	79
	80	(define_constraint "PJ"
	81	"@internal A constant that satisfies the Pj constrant if negated."
	82	(and (match_code "const_int")
	83	(and (match_test "TARGET_THUMB2")
	84	(match_test "((-ival) & 0xfffff000) == 0"))))
	85
f5c630c3 PB	86	(define_register_constraint "k" "STACK_REG"
f5c630c3 PB	87	"@internal The stack register.")
ce92b223	88
4542a38a GY	89	(define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
	90	"@internal In ARM state with LDRD support, core registers, otherwise general registers.")
	91
ce92b223 RE	92	(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
	93	"@internal
	94	Thumb only. The union of the low registers and the stack register.")
	95
	96	(define_register_constraint "c" "CC_REG"
a876121d	97	"@internal The condition code register.")
ce92b223	98
9adcfa3c RR	99	(define_register_constraint "Cs" "CALLER_SAVE_REGS"
	100	"@internal The caller save registers. Useful for sibcalls.")
	101
ce92b223	102	(define_constraint "I"
5b3e6663 PB	103	"In ARM/Thumb-2 state a constant that can be used as an immediate value in a
	104	Data Processing instruction. In Thumb-1 state a constant in the range
	105	0-255."
ce92b223	106	(and (match_code "const_int")
5b3e6663	107	(match_test "TARGET_32BIT ? const_ok_for_arm (ival)
ce92b223 RE	108	: ival >= 0 && ival <= 255")))
	109
	110	(define_constraint "J"
5b3e6663 PB	111	"In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
5b3e6663 PB	112	state a constant in the range @minus{}255-@minus{}1."
ce92b223	113	(and (match_code "const_int")
5b3e6663	114	(match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
ce92b223 RE	115	: (ival >= -255 && ival <= -1)")))
	116
	117	(define_constraint "K"
5b3e6663 PB	118	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
	119	inverted. In Thumb-1 state a constant that satisfies the @code{I}
	120	constraint multiplied by any power of 2."
ce92b223	121	(and (match_code "const_int")
5b3e6663	122	(match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
ce92b223 RE	123	: thumb_shiftable_const (ival)")))
	124
	125	(define_constraint "L"
5b3e6663 PB	126	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
5b3e6663 PB	127	negated. In Thumb-1 state a constant in the range @minus{}7-7."
ce92b223	128	(and (match_code "const_int")
5b3e6663	129	(match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
ce92b223 RE	130	: (ival >= -7 && ival <= 7)")))
	131
	132	;; The ARM state version is internal...
5b3e6663 PB	133	;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
5b3e6663 PB	134	;; power of 2.
ce92b223	135	(define_constraint "M"
5b3e6663	136	"In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
ce92b223	137	(and (match_code "const_int")
5b3e6663	138	(match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
29b40d79	139	\|\| (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
16737e76	140	: ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
ce92b223 RE	141
ce92b223 RE	142	(define_constraint "N"
d58bc084	143	"Thumb-1 state a constant in the range 0-31."
ce92b223	144	(and (match_code "const_int")
d58bc084	145	(match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
ce92b223 RE	146
ce92b223 RE	147	(define_constraint "O"
5b3e6663	148	"In Thumb-1 state a constant that is a multiple of 4 in the range
ce92b223 RE	149	@minus{}508-508."
ce92b223 RE	150	(and (match_code "const_int")
5b3e6663	151	(match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
ce92b223 RE	152	&& ((ival & 3) == 0)")))
ce92b223 RE	153
81beb031 RE	154	(define_constraint "Pa"
	155	"@internal In Thumb-1 state a constant in the range -510 to +510"
	156	(and (match_code "const_int")
	157	(match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
	158	&& (ival > 255 \|\| ival < -255)")))
	159
	160	(define_constraint "Pb"
	161	"@internal In Thumb-1 state a constant in the range -262 to +262"
	162	(and (match_code "const_int")
	163	(match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
	164	&& (ival > 255 \|\| ival < -255)")))
	165
16737e76 BS	166	(define_constraint "Pc"
	167	"@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
	168	(and (match_code "const_int")
	169	(match_test "TARGET_THUMB1
	170	&& ival > 1020 && ival <= 1275")))
	171
906668bb	172	(define_constraint "Pd"
5e5f7673	173	"@internal In Thumb state a constant in the range 0 to 7"
906668bb	174	(and (match_code "const_int")
5e5f7673	175	(match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
906668bb	176
572a49c8 JY	177	(define_constraint "Pe"
	178	"@internal In Thumb-1 state a constant in the range 256 to +510"
	179	(and (match_code "const_int")
	180	(match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
	181
85f28bf1 JB	182	(define_constraint "Ps"
	183	"@internal In Thumb-2 state a constant in the range -255 to +255"
	184	(and (match_code "const_int")
	185	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
	186
	187	(define_constraint "Pt"
	188	"@internal In Thumb-2 state a constant in the range -7 to +7"
	189	(and (match_code "const_int")
	190	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
	191
ee4e1706 WG	192	(define_constraint "Pu"
	193	"@internal In Thumb-2 state a constant in the range +1 to +8"
	194	(and (match_code "const_int")
	195	(match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
	196
dcd8b2ee JB	197	(define_constraint "Pv"
	198	"@internal In Thumb-2 state a constant in the range -255 to 0"
	199	(and (match_code "const_int")
	200	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
	201
e6bfe8a2 RE	202	(define_constraint "Pw"
	203	"@internal In Thumb-2 state a constant in the range -255 to -1"
	204	(and (match_code "const_int")
	205	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
	206
	207	(define_constraint "Px"
	208	"@internal In Thumb-2 state a constant in the range -7 to -1"
	209	(and (match_code "const_int")
	210	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
	211
4925d0d5 WG	212	(define_constraint "Py"
	213	"@internal In Thumb-2 state a constant in the range 0 to 255"
	214	(and (match_code "const_int")
	215	(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
	216
5e5f7673 KT	217	(define_constraint "Pz"
	218	"@internal In Thumb-2 state the constant 0"
	219	(and (match_code "const_int")
	220	(match_test "TARGET_THUMB2 && (ival == 0)")))
	221
ce92b223	222	(define_constraint "G"
dae840fc	223	"In ARM/Thumb-2 state the floating-point constant 0."
ce92b223	224	(and (match_code "const_double")
5b3e6663	225	(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
ce92b223	226
5bfc5baa JB	227	(define_constraint "Dz"
	228	"@internal
	229	In ARM/Thumb-2 state a vector of constant zeros."
	230	(and (match_code "const_vector")
	231	(match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
	232
ce92b223 RE	233	(define_constraint "Da"
ce92b223 RE	234	"@internal
5b3e6663	235	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	236	be generated with two Data Processing insns."
ce92b223 RE	237	(and (match_code "const_double,const_int,const_vector")
5b3e6663	238	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
ce92b223 RE	239
	240	(define_constraint "Db"
	241	"@internal
5b3e6663	242	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	243	be generated with three Data Processing insns."
ce92b223 RE	244	(and (match_code "const_double,const_int,const_vector")
5b3e6663	245	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
ce92b223 RE	246
	247	(define_constraint "Dc"
	248	"@internal
5b3e6663	249	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	250	be generated with four Data Processing insns. This pattern is disabled
	251	if optimizing for space or when we have load-delay slots to fill."
	252	(and (match_code "const_double,const_int,const_vector")
5b3e6663	253	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
ce92b223 RE	254	&& !(optimize_size \|\| arm_ld_sched)")))
ce92b223 RE	255
44cd6810 WG	256	(define_constraint "Dd"
	257	"@internal
	258	In ARM/Thumb-2 state a const_int that can be used by insn adddi."
	259	(and (match_code "const_int")
	260	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
	261
1c50eada KT	262	(define_constraint "De"
	263	"@internal
	264	In ARM/Thumb-2 state a const_int that can be used by insn anddi."
	265	(and (match_code "const_int")
	266	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
	267
33e49835 KT	268	(define_constraint "Df"
	269	"@internal
	270	In ARM/Thumb-2 state a const_int that can be used by insn iordi."
	271	(and (match_code "const_int")
	272	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
	273
79678d04 KT	274	(define_constraint "Dg"
	275	"@internal
	276	In ARM/Thumb-2 state a const_int that can be used by insn xordi."
	277	(and (match_code "const_int")
	278	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
	279
73160ba9 DJ	280	(define_constraint "Di"
	281	"@internal
	282	In ARM/Thumb-2 state a const_int or const_double where both the high
	283	and low SImode words can be generated as immediates in 32-bit instructions."
	284	(and (match_code "const_double,const_int")
	285	(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
	286
88f77cba JB	287	(define_constraint "Dn"
88f77cba JB	288	"@internal
00a3a76a AS	289	In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
	290	Neon vmov immediate instruction."
	291	(and (match_code "const_vector,const_int")
88f77cba JB	292	(match_test "TARGET_32BIT
	293	&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
	294
	295	(define_constraint "Dl"
	296	"@internal
	297	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
	298	vbic instruction."
	299	(and (match_code "const_vector")
	300	(match_test "TARGET_32BIT
	301	&& imm_for_neon_logic_operand (op, GET_MODE (op))")))
	302
	303	(define_constraint "DL"
	304	"@internal
	305	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
	306	vand instruction."
	307	(and (match_code "const_vector")
	308	(match_test "TARGET_32BIT
	309	&& imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
	310
56289ed2 SD	311	(define_constraint "Do"
	312	"@internal
	313	In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
	314	(and (match_code "const_int")
	315	(match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
	316
f1adb0a9 JB	317	(define_constraint "Dv"
	318	"@internal
	319	In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
e0dc3601	320	instruction."
f1adb0a9 JB	321	(and (match_code "const_double")
	322	(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
	323
e0dc3601 PB	324	(define_constraint "Dy"
	325	"@internal
	326	In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
	327	instruction."
	328	(and (match_code "const_double")
	329	(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
	330
7f3d8f56 RR	331	(define_constraint "Dt"
	332	"@internal
	333	In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
	334	(and (match_code "const_double")
	335	(match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
	336
956a95a5 KT	337	(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
	338	"For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
	339
18f0fe6b RH	340	(define_memory_constraint "Ua"
	341	"@internal
	342	An address valid for loading/storing register exclusive"
	343	(match_operand 0 "mem_noofs_operand"))
	344
88f77cba JB	345	(define_memory_constraint "Ut"
	346	"@internal
	347	In ARM/Thumb-2 state an address valid for loading/storing opaque structure
	348	types wider than TImode."
	349	(and (match_code "mem")
	350	(match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
	351
ce92b223 RE	352	(define_memory_constraint "Uv"
ce92b223 RE	353	"@internal
5b3e6663	354	In ARM/Thumb-2 state a valid VFP load/store address."
ce92b223	355	(and (match_code "mem")
5b3e6663	356	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
ce92b223 RE	357
	358	(define_memory_constraint "Uy"
	359	"@internal
5b3e6663	360	In ARM/Thumb-2 state a valid iWMMX load/store address."
ce92b223	361	(and (match_code "mem")
5b3e6663	362	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
ce92b223	363
88f77cba	364	(define_memory_constraint "Un"
dc34db56 PB	365	"@internal
	366	In ARM/Thumb-2 state a valid address for Neon doubleword vector
	367	load/store instructions."
	368	(and (match_code "mem")
33255ae3	369	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
dc34db56 PB	370
dc34db56 PB	371	(define_memory_constraint "Um"
88f77cba JB	372	"@internal
	373	In ARM/Thumb-2 state a valid address for Neon element and structure
	374	load/store instructions."
	375	(and (match_code "mem")
33255ae3	376	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
88f77cba JB	377
	378	(define_memory_constraint "Us"
	379	"@internal
	380	In ARM/Thumb-2 state a valid address for non-offset loads/stores of
	381	quad-word values in four ARM registers."
	382	(and (match_code "mem")
33255ae3	383	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
88f77cba	384
ce92b223 RE	385	(define_memory_constraint "Uq"
	386	"@internal
	387	In ARM state an address valid in ldrsb instructions."
	388	(and (match_code "mem")
	389	(match_test "TARGET_ARM
c6c3dba9 PB	390	&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
c6c3dba9 PB	391	SIGN_EXTEND, 0)")))
ce92b223 RE	392
	393	(define_memory_constraint "Q"
	394	"@internal
5b3e6663	395	In ARM/Thumb-2 state an address that is a single base register."
ce92b223 RE	396	(and (match_code "mem")
	397	(match_test "REG_P (XEXP (op, 0))")))
	398
363ee90e WG	399	(define_memory_constraint "Uu"
	400	"@internal
	401	In Thumb state an address that is valid in 16bit encoding."
	402	(and (match_code "mem")
	403	(match_test "TARGET_THUMB
	404	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	405	0)")))
	406
86b60116 JB	407	; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
	408	; are actually LDM/STM instructions, so cannot be used to access unaligned
	409	; data.
	410	(define_memory_constraint "Uw"
	411	"@internal
	412	In Thumb state an address that is valid in 16bit encoding, and that can be
	413	used for unaligned accesses."
	414	(and (match_code "mem")
	415	(match_test "TARGET_THUMB
	416	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	417	0)
	418	&& GET_CODE (XEXP (op, 0)) != POST_INC")))
	419
0b93d3b6 RR	420	(define_constraint "US"
	421	"@internal
	422	US is a symbol reference."
	423	(match_code "symbol_ref")
	424	)
	425
ce92b223 RE	426	;; We used to have constraint letters for S and R in ARM state, but
	427	;; all uses of these now appear to have been removed.
	428
	429	;; Additionally, we used to have a Q constraint in Thumb state, but
	430	;; this wasn't really a valid memory constraint. Again, all uses of
	431	;; this now seem to have been removed.
9adcfa3c	432