[thirdparty/gcc.git] / gcc / config / arm / constraints.md

;; Constraint definitions for ARM and Thumb
;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; The following register constraints have been used:
;; - in ARM/Thumb-2 state: t, w, x, y, z
;; - in Thumb state: h, b
;; - in both states: l, c, k, q, Cs, Ts, US
;; In ARM state, 'l' is an alias for 'r'
;; 'f' and 'v' were previously used for FPA and MAVERICK registers.

;; The following normal constraints have been used:
;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
;; in Thumb-1 state: I, J, K, L, M, N, O
;; 'H' was previously used for FPA.

;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp,
;;			 Dz, Tu
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
;; in all states: Pf

;; The following memory constraints have been used:
;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
;; in ARM state: Uq
;; in Thumb state: Uu, Uw
;; in all states: Q


(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
 "The VFP registers @code{s0}-@code{s31}.")

(define_register_constraint "w"
  "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")

(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
 "The VFP registers @code{d0}-@code{d7}.")

(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
 "The Intel iWMMX co-processor registers.")

(define_register_constraint "z"
 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
 "The Intel iWMMX GR registers.")

(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
 "In Thumb state the core registers @code{r0}-@code{r7}.")

(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
 "In Thumb state the core registers @code{r8}-@code{r15}.")

(define_constraint "j"
 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
 (and (match_test "TARGET_HAVE_MOVT")
      (ior (and (match_code "high")
		(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
	   (and (match_code "const_int")
                (match_test "(ival & 0xffff0000) == 0")))))

(define_constraint "Pj"
 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "(ival & 0xfffff000) == 0"))))

(define_constraint "PJ"
 "@internal A constant that satisfies the Pj constrant if negated."
 (and (match_code "const_int")
      (and (match_test "TARGET_THUMB2")
	   (match_test "((-ival) & 0xfffff000) == 0"))))

(define_register_constraint "k" "STACK_REG"
 "@internal The stack register.")

(define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
  "@internal In ARM state with LDRD support, core registers, otherwise general registers.")

(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 "@internal
  Thumb only.  The union of the low registers and the stack register.")

(define_register_constraint "c" "CC_REG"
 "@internal The condition code register.")

(define_register_constraint "Cs" "CALLER_SAVE_REGS"
 "@internal The caller save registers.  Useful for sibcalls.")

(define_constraint "I"
 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
  Data Processing instruction.  In Thumb-1 state a constant in the range
  0-255."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
		   : ival >= 0 && ival <= 255")))

(define_constraint "J"
 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
  state a constant in the range @minus{}255-@minus{}1."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
		   : (ival >= -255 && ival <= -1)")))

(define_constraint "K"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  inverted.  In Thumb-1 state a constant that satisfies the @code{I}
  constraint multiplied by any power of 2."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
		   : thumb_shiftable_const (ival)")))

(define_constraint "L"
 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
  negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
		   : (ival >= -7 && ival <= 7)")))

;; The ARM state version is internal...
;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
;; power of 2.
(define_constraint "M"
 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
				 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
		   : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))

(define_constraint "N"
 "Thumb-1 state a constant in the range 0-31."
 (and (match_code "const_int")
      (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))

(define_constraint "O"
 "In Thumb-1 state a constant that is a multiple of 4 in the range
  @minus{}508-508."
 (and (match_code "const_int")
      (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
		   && ((ival & 3) == 0)")))

(define_constraint "Pa"
  "@internal In Thumb-1 state a constant in the range -510 to +510"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pb"
  "@internal In Thumb-1 state a constant in the range -262 to +262"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
		    && (ival > 255 || ival < -255)")))

(define_constraint "Pc"
  "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1
  		    && ival > 1020 && ival <= 1275")))

(define_constraint "Pd"
  "@internal In Thumb state a constant in the range 0 to 7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))

(define_constraint "Pe"
  "@internal In Thumb-1 state a constant in the range 256 to +510"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))

(define_constraint "Pf"
  "Memory models except relaxed, consume or release ones."
  (and (match_code "const_int")
       (match_test "!is_mm_relaxed (memmodel_from_int (ival))
		    && !is_mm_consume (memmodel_from_int (ival))
		    && !is_mm_release (memmodel_from_int (ival))")))

(define_constraint "Ps"
  "@internal In Thumb-2 state a constant in the range -255 to +255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))

(define_constraint "Pt"
  "@internal In Thumb-2 state a constant in the range -7 to +7"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))

(define_constraint "Pu"
  "@internal In Thumb-2 state a constant in the range +1 to +8"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))

(define_constraint "Pv"
  "@internal In Thumb-2 state a constant in the range -255 to 0"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))

(define_constraint "Pw"
  "@internal In Thumb-2 state a constant in the range -255 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))

(define_constraint "Px"
  "@internal In Thumb-2 state a constant in the range -7 to -1"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))

(define_constraint "Py"
  "@internal In Thumb-2 state a constant in the range 0 to 255"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))

(define_constraint "Pz"
  "@internal In Thumb-2 state the constant 0"
  (and (match_code "const_int")
       (match_test "TARGET_THUMB2 && (ival == 0)")))

(define_constraint "G"
 "In ARM/Thumb-2 state the floating-point constant 0."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))

(define_constraint "Ha"
  "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
  (and (match_code "const_double")
       (match_test "satisfies_constraint_E (op)")
       (match_test "!arm_disable_literal_pool")))

(define_constraint "Dz"
 "@internal
  In ARM/Thumb-2 state a vector of constant zeros."
 (and (match_code "const_vector")
      (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))

(define_constraint "Da"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with two Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))

(define_constraint "Db"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with three Data Processing insns."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))

(define_constraint "Dc"
 "@internal
  In ARM/Thumb-2 state a const_int, const_double or const_vector that can
  be generated with four Data Processing insns.  This pattern is disabled
  if optimizing for space or when we have load-delay slots to fill."
 (and (match_code "const_double,const_int,const_vector")
      (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
		   && !(optimize_size || arm_ld_sched)")))

(define_constraint "Dd"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))

(define_constraint "De"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn anddi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))

(define_constraint "Df"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn iordi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))

(define_constraint "Dg"
 "@internal
  In ARM/Thumb-2 state a const_int that can be used by insn xordi."
 (and (match_code "const_int")
      (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))

(define_constraint "Di"
 "@internal
  In ARM/Thumb-2 state a const_int or const_double where both the high
  and low SImode words can be generated as immediates in 32-bit instructions."
 (and (match_code "const_double,const_int")
      (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))

(define_constraint "Dn"
 "@internal
  In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
  Neon vmov immediate instruction."
 (and (match_code "const_vector,const_int")
      (match_test "TARGET_32BIT
		   && imm_for_neon_mov_operand (op, GET_MODE (op))")))

(define_constraint "Dl"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
  vbic instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_logic_operand (op, GET_MODE (op))")))

(define_constraint "DL"
 "@internal
  In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
  vand instruction."
 (and (match_code "const_vector")
      (match_test "TARGET_32BIT
		   && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))

(define_constraint "Do"
 "@internal
  In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 (and (match_code "const_int")
      (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))

(define_constraint "Dv"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))

(define_constraint "Dy"
 "@internal
  In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
  instruction."
 (and (match_code "const_double")
      (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))

(define_constraint "Dt"
 "@internal
  In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
  (and (match_code "const_double")
       (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))

(define_constraint "Dp"
 "@internal
  In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
  (and (match_code "const_double")
       (match_test "TARGET_32BIT
		    && vfp3_const_double_for_bits (op) > 0")))

(define_constraint "Tu"
  "@internal In ARM / Thumb-2 an integer constant iff literal pools are
   allowed."
  (and (match_test "CONSTANT_P (op)")
       (match_test "!arm_disable_literal_pool")))

(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")

(define_memory_constraint "Ua"
 "@internal
  An address valid for loading/storing register exclusive"
 (match_operand 0 "mem_noofs_operand"))

(define_memory_constraint "Uh"
 "@internal
  An address suitable for byte and half-word loads which does not point inside a constant pool"
 (and (match_code "mem")
      (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))

(define_memory_constraint "Ut"
 "@internal
  In ARM/Thumb-2 state an address valid for loading/storing opaque structure
  types wider than TImode."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))

(define_memory_constraint "Uv"
 "@internal
  In ARM/Thumb-2 state a valid VFP load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))

(define_memory_constraint "Uy"
 "@internal
  In ARM/Thumb-2 state a valid iWMMX load/store address."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))

(define_memory_constraint "Un"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon doubleword vector
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))

(define_memory_constraint "Um"
 "@internal
  In ARM/Thumb-2 state a valid address for Neon element and structure
  load/store instructions."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))

(define_memory_constraint "Us"
 "@internal
  In ARM/Thumb-2 state a valid address for non-offset loads/stores of
  quad-word values in four ARM registers."
 (and (match_code "mem")
      (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))

(define_memory_constraint "Uq"
 "@internal
  In ARM state an address valid in ldrsb instructions."
 (and (match_code "mem")
      (match_test "TARGET_ARM
		   && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
						      SIGN_EXTEND, 0)
		   && !arm_is_constant_pool_ref (op)")))

(define_memory_constraint "Q"
 "@internal
  An address that is a single base register."
 (and (match_code "mem")
      (match_test "REG_P (XEXP (op, 0))")))

(define_memory_constraint "Uu"
 "@internal
  In Thumb state an address that is valid in 16bit encoding."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)")))

; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
; are actually LDM/STM instructions, so cannot be used to access unaligned
; data.
(define_memory_constraint "Uw"
 "@internal
  In Thumb state an address that is valid in 16bit encoding, and that can be
  used for unaligned accesses."
 (and (match_code "mem")
      (match_test "TARGET_THUMB
		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
						   0)
		   && GET_CODE (XEXP (op, 0)) != POST_INC")))

(define_constraint "US"
 "@internal
  US is a symbol reference."
 (match_code "symbol_ref")
)

(define_memory_constraint "Uz"
 "@internal
  A memory access that is accessible as an LDC/STC operand"
 (and (match_code "mem")
      (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))

;; We used to have constraint letters for S and R in ARM state, but
;; all uses of these now appear to have been removed.

;; Additionally, we used to have a Q constraint in Thumb state, but
;; this wasn't really a valid memory constraint.  Again, all uses of
;; this now seem to have been removed.
Commit	Line	Data
ce92b223	1	;; Constraint definitions for ARM and Thumb
a5544970	2	;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
ce92b223 RE	3	;; Contributed by ARM Ltd.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
2f83c7d6	9	;; by the Free Software Foundation; either version 3, or (at your
ce92b223 RE	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>.
ce92b223 RE	20
ce92b223 RE	21	;; The following register constraints have been used:
dae840fc	22	;; - in ARM/Thumb-2 state: t, w, x, y, z
f5c630c3	23	;; - in Thumb state: h, b
e36dbdfe	24	;; - in both states: l, c, k, q, Cs, Ts, US
ce92b223	25	;; In ARM state, 'l' is an alias for 'r'
dae840fc	26	;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
ce92b223 RE	27
ce92b223 RE	28	;; The following normal constraints have been used:
dae840fc	29	;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
5b3e6663	30	;; in Thumb-1 state: I, J, K, L, M, N, O
dae840fc	31	;; 'H' was previously used for FPA.
ce92b223 RE	32
ce92b223 RE	33	;; The following multi-letter normal constraints have been used:
8d33eae8 TP	34	;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp,
8d33eae8 TP	35	;; Dz, Tu
572a49c8	36	;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
8d33eae8	37	;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
84c20253	38	;; in all states: Pf
ce92b223 RE	39
ce92b223 RE	40	;; The following memory constraints have been used:
84c20253	41	;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
5b3e6663	42	;; in ARM state: Uq
86b60116	43	;; in Thumb state: Uu, Uw
84c20253	44	;; in all states: Q
ce92b223 RE	45
ce92b223 RE	46
f1adb0a9 JB	47	(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
	48	"The VFP registers @code{s0}-@code{s31}.")
	49
f1adb0a9	50	(define_register_constraint "w"
302c3d8e	51	"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
f1adb0a9 JB	52	"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
	53
	54	(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
	55	"The VFP registers @code{d0}-@code{d7}.")
ce92b223 RE	56
	57	(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
	58	"The Intel iWMMX co-processor registers.")
	59
	60	(define_register_constraint "z"
	61	"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
	62	"The Intel iWMMX GR registers.")
	63
	64	(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
	65	"In Thumb state the core registers @code{r0}-@code{r7}.")
	66
	67	(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
	68	"In Thumb state the core registers @code{r8}-@code{r15}.")
	69
d58bc084 NS	70	(define_constraint "j"
d58bc084 NS	71	"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
33427b46	72	(and (match_test "TARGET_HAVE_MOVT")
6ce43645 RL	73	(ior (and (match_code "high")
6ce43645 RL	74	(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
d58bc084 NS	75	(and (match_code "const_int")
	76	(match_test "(ival & 0xffff0000) == 0")))))
	77
c2b640a7 AS	78	(define_constraint "Pj"
	79	"@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
	80	(and (match_code "const_int")
	81	(and (match_test "TARGET_THUMB2")
	82	(match_test "(ival & 0xfffff000) == 0"))))
	83
	84	(define_constraint "PJ"
	85	"@internal A constant that satisfies the Pj constrant if negated."
	86	(and (match_code "const_int")
	87	(and (match_test "TARGET_THUMB2")
	88	(match_test "((-ival) & 0xfffff000) == 0"))))
	89
f5c630c3 PB	90	(define_register_constraint "k" "STACK_REG"
f5c630c3 PB	91	"@internal The stack register.")
ce92b223	92
4542a38a GY	93	(define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
	94	"@internal In ARM state with LDRD support, core registers, otherwise general registers.")
	95
ce92b223 RE	96	(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
	97	"@internal
	98	Thumb only. The union of the low registers and the stack register.")
	99
	100	(define_register_constraint "c" "CC_REG"
a876121d	101	"@internal The condition code register.")
ce92b223	102
9adcfa3c RR	103	(define_register_constraint "Cs" "CALLER_SAVE_REGS"
	104	"@internal The caller save registers. Useful for sibcalls.")
	105
ce92b223	106	(define_constraint "I"
5b3e6663 PB	107	"In ARM/Thumb-2 state a constant that can be used as an immediate value in a
	108	Data Processing instruction. In Thumb-1 state a constant in the range
	109	0-255."
ce92b223	110	(and (match_code "const_int")
5b3e6663	111	(match_test "TARGET_32BIT ? const_ok_for_arm (ival)
ce92b223 RE	112	: ival >= 0 && ival <= 255")))
	113
	114	(define_constraint "J"
5b3e6663 PB	115	"In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
5b3e6663 PB	116	state a constant in the range @minus{}255-@minus{}1."
ce92b223	117	(and (match_code "const_int")
5b3e6663	118	(match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
ce92b223 RE	119	: (ival >= -255 && ival <= -1)")))
	120
	121	(define_constraint "K"
5b3e6663 PB	122	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
	123	inverted. In Thumb-1 state a constant that satisfies the @code{I}
	124	constraint multiplied by any power of 2."
ce92b223	125	(and (match_code "const_int")
5b3e6663	126	(match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
ce92b223 RE	127	: thumb_shiftable_const (ival)")))
	128
	129	(define_constraint "L"
5b3e6663 PB	130	"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
5b3e6663 PB	131	negated. In Thumb-1 state a constant in the range @minus{}7-7."
ce92b223	132	(and (match_code "const_int")
5b3e6663	133	(match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
ce92b223 RE	134	: (ival >= -7 && ival <= 7)")))
	135
	136	;; The ARM state version is internal...
5b3e6663 PB	137	;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
5b3e6663 PB	138	;; power of 2.
ce92b223	139	(define_constraint "M"
5b3e6663	140	"In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
ce92b223	141	(and (match_code "const_int")
5b3e6663	142	(match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
29b40d79	143	\|\| (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
16737e76	144	: ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
ce92b223 RE	145
ce92b223 RE	146	(define_constraint "N"
d58bc084	147	"Thumb-1 state a constant in the range 0-31."
ce92b223	148	(and (match_code "const_int")
d58bc084	149	(match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
ce92b223 RE	150
ce92b223 RE	151	(define_constraint "O"
5b3e6663	152	"In Thumb-1 state a constant that is a multiple of 4 in the range
ce92b223 RE	153	@minus{}508-508."
ce92b223 RE	154	(and (match_code "const_int")
5b3e6663	155	(match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
ce92b223 RE	156	&& ((ival & 3) == 0)")))
ce92b223 RE	157
81beb031 RE	158	(define_constraint "Pa"
	159	"@internal In Thumb-1 state a constant in the range -510 to +510"
	160	(and (match_code "const_int")
	161	(match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
	162	&& (ival > 255 \|\| ival < -255)")))
	163
	164	(define_constraint "Pb"
	165	"@internal In Thumb-1 state a constant in the range -262 to +262"
	166	(and (match_code "const_int")
	167	(match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
	168	&& (ival > 255 \|\| ival < -255)")))
	169
16737e76 BS	170	(define_constraint "Pc"
	171	"@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
	172	(and (match_code "const_int")
	173	(match_test "TARGET_THUMB1
	174	&& ival > 1020 && ival <= 1275")))
	175
906668bb	176	(define_constraint "Pd"
5e5f7673	177	"@internal In Thumb state a constant in the range 0 to 7"
906668bb	178	(and (match_code "const_int")
5e5f7673	179	(match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
906668bb	180
572a49c8 JY	181	(define_constraint "Pe"
	182	"@internal In Thumb-1 state a constant in the range 256 to +510"
	183	(and (match_code "const_int")
	184	(match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
	185
84c20253 TP	186	(define_constraint "Pf"
	187	"Memory models except relaxed, consume or release ones."
	188	(and (match_code "const_int")
	189	(match_test "!is_mm_relaxed (memmodel_from_int (ival))
	190	&& !is_mm_consume (memmodel_from_int (ival))
	191	&& !is_mm_release (memmodel_from_int (ival))")))
	192
85f28bf1 JB	193	(define_constraint "Ps"
	194	"@internal In Thumb-2 state a constant in the range -255 to +255"
	195	(and (match_code "const_int")
	196	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
	197
	198	(define_constraint "Pt"
	199	"@internal In Thumb-2 state a constant in the range -7 to +7"
	200	(and (match_code "const_int")
	201	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
	202
ee4e1706 WG	203	(define_constraint "Pu"
	204	"@internal In Thumb-2 state a constant in the range +1 to +8"
	205	(and (match_code "const_int")
	206	(match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
	207
dcd8b2ee JB	208	(define_constraint "Pv"
	209	"@internal In Thumb-2 state a constant in the range -255 to 0"
	210	(and (match_code "const_int")
	211	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
	212
e6bfe8a2 RE	213	(define_constraint "Pw"
	214	"@internal In Thumb-2 state a constant in the range -255 to -1"
	215	(and (match_code "const_int")
	216	(match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
	217
	218	(define_constraint "Px"
	219	"@internal In Thumb-2 state a constant in the range -7 to -1"
	220	(and (match_code "const_int")
	221	(match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
	222
4925d0d5 WG	223	(define_constraint "Py"
	224	"@internal In Thumb-2 state a constant in the range 0 to 255"
	225	(and (match_code "const_int")
	226	(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
	227
5e5f7673 KT	228	(define_constraint "Pz"
	229	"@internal In Thumb-2 state the constant 0"
	230	(and (match_code "const_int")
	231	(match_test "TARGET_THUMB2 && (ival == 0)")))
	232
ce92b223	233	(define_constraint "G"
dae840fc	234	"In ARM/Thumb-2 state the floating-point constant 0."
ce92b223	235	(and (match_code "const_double")
5b3e6663	236	(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
ce92b223	237
8d33eae8 TP	238	(define_constraint "Ha"
	239	"@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
	240	(and (match_code "const_double")
	241	(match_test "satisfies_constraint_E (op)")
	242	(match_test "!arm_disable_literal_pool")))
	243
5bfc5baa JB	244	(define_constraint "Dz"
	245	"@internal
	246	In ARM/Thumb-2 state a vector of constant zeros."
	247	(and (match_code "const_vector")
	248	(match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
	249
ce92b223 RE	250	(define_constraint "Da"
ce92b223 RE	251	"@internal
5b3e6663	252	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	253	be generated with two Data Processing insns."
ce92b223 RE	254	(and (match_code "const_double,const_int,const_vector")
5b3e6663	255	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
ce92b223 RE	256
	257	(define_constraint "Db"
	258	"@internal
5b3e6663	259	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	260	be generated with three Data Processing insns."
ce92b223 RE	261	(and (match_code "const_double,const_int,const_vector")
5b3e6663	262	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
ce92b223 RE	263
	264	(define_constraint "Dc"
	265	"@internal
5b3e6663	266	In ARM/Thumb-2 state a const_int, const_double or const_vector that can
ce92b223 RE	267	be generated with four Data Processing insns. This pattern is disabled
	268	if optimizing for space or when we have load-delay slots to fill."
	269	(and (match_code "const_double,const_int,const_vector")
5b3e6663	270	(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
ce92b223 RE	271	&& !(optimize_size \|\| arm_ld_sched)")))
ce92b223 RE	272
44cd6810 WG	273	(define_constraint "Dd"
	274	"@internal
	275	In ARM/Thumb-2 state a const_int that can be used by insn adddi."
	276	(and (match_code "const_int")
	277	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
	278
1c50eada KT	279	(define_constraint "De"
	280	"@internal
	281	In ARM/Thumb-2 state a const_int that can be used by insn anddi."
	282	(and (match_code "const_int")
	283	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
	284
33e49835 KT	285	(define_constraint "Df"
	286	"@internal
	287	In ARM/Thumb-2 state a const_int that can be used by insn iordi."
	288	(and (match_code "const_int")
	289	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
	290
79678d04 KT	291	(define_constraint "Dg"
	292	"@internal
	293	In ARM/Thumb-2 state a const_int that can be used by insn xordi."
	294	(and (match_code "const_int")
	295	(match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
	296
73160ba9 DJ	297	(define_constraint "Di"
	298	"@internal
	299	In ARM/Thumb-2 state a const_int or const_double where both the high
	300	and low SImode words can be generated as immediates in 32-bit instructions."
	301	(and (match_code "const_double,const_int")
	302	(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
	303
88f77cba JB	304	(define_constraint "Dn"
88f77cba JB	305	"@internal
00a3a76a AS	306	In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
	307	Neon vmov immediate instruction."
	308	(and (match_code "const_vector,const_int")
88f77cba JB	309	(match_test "TARGET_32BIT
	310	&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
	311
	312	(define_constraint "Dl"
	313	"@internal
	314	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
	315	vbic instruction."
	316	(and (match_code "const_vector")
	317	(match_test "TARGET_32BIT
	318	&& imm_for_neon_logic_operand (op, GET_MODE (op))")))
	319
	320	(define_constraint "DL"
	321	"@internal
	322	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
	323	vand instruction."
	324	(and (match_code "const_vector")
	325	(match_test "TARGET_32BIT
	326	&& imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
	327
56289ed2 SD	328	(define_constraint "Do"
	329	"@internal
	330	In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
	331	(and (match_code "const_int")
	332	(match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
	333
f1adb0a9 JB	334	(define_constraint "Dv"
	335	"@internal
	336	In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
e0dc3601	337	instruction."
f1adb0a9 JB	338	(and (match_code "const_double")
	339	(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
	340
e0dc3601 PB	341	(define_constraint "Dy"
	342	"@internal
	343	In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
	344	instruction."
	345	(and (match_code "const_double")
	346	(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
	347
c75d51aa	348	(define_constraint "Dt"
7f3d8f56 RR	349	"@internal
	350	In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
	351	(and (match_code "const_double")
00ea1506	352	(match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
7f3d8f56	353
c75d51aa RL	354	(define_constraint "Dp"
	355	"@internal
	356	In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
	357	(and (match_code "const_double")
00ea1506	358	(match_test "TARGET_32BIT
85f5231d	359	&& vfp3_const_double_for_bits (op) > 0")))
c75d51aa	360
8d33eae8 TP	361	(define_constraint "Tu"
	362	"@internal In ARM / Thumb-2 an integer constant iff literal pools are
	363	allowed."
	364	(and (match_test "CONSTANT_P (op)")
	365	(match_test "!arm_disable_literal_pool")))
	366
956a95a5 KT	367	(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
	368	"For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
	369
18f0fe6b RH	370	(define_memory_constraint "Ua"
	371	"@internal
	372	An address valid for loading/storing register exclusive"
	373	(match_operand 0 "mem_noofs_operand"))
	374
aed773a2 CB	375	(define_memory_constraint "Uh"
	376	"@internal
	377	An address suitable for byte and half-word loads which does not point inside a constant pool"
	378	(and (match_code "mem")
	379	(match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
	380
88f77cba JB	381	(define_memory_constraint "Ut"
	382	"@internal
	383	In ARM/Thumb-2 state an address valid for loading/storing opaque structure
	384	types wider than TImode."
	385	(and (match_code "mem")
	386	(match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
	387
ce92b223 RE	388	(define_memory_constraint "Uv"
ce92b223 RE	389	"@internal
5b3e6663	390	In ARM/Thumb-2 state a valid VFP load/store address."
ce92b223	391	(and (match_code "mem")
5b3e6663	392	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
ce92b223 RE	393
	394	(define_memory_constraint "Uy"
	395	"@internal
5b3e6663	396	In ARM/Thumb-2 state a valid iWMMX load/store address."
ce92b223	397	(and (match_code "mem")
5b3e6663	398	(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
ce92b223	399
88f77cba	400	(define_memory_constraint "Un"
dc34db56 PB	401	"@internal
	402	In ARM/Thumb-2 state a valid address for Neon doubleword vector
	403	load/store instructions."
	404	(and (match_code "mem")
33255ae3	405	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
dc34db56 PB	406
dc34db56 PB	407	(define_memory_constraint "Um"
88f77cba JB	408	"@internal
	409	In ARM/Thumb-2 state a valid address for Neon element and structure
	410	load/store instructions."
	411	(and (match_code "mem")
33255ae3	412	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
88f77cba JB	413
	414	(define_memory_constraint "Us"
	415	"@internal
	416	In ARM/Thumb-2 state a valid address for non-offset loads/stores of
	417	quad-word values in four ARM registers."
	418	(and (match_code "mem")
33255ae3	419	(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
88f77cba	420
ce92b223 RE	421	(define_memory_constraint "Uq"
	422	"@internal
	423	In ARM state an address valid in ldrsb instructions."
	424	(and (match_code "mem")
	425	(match_test "TARGET_ARM
c6c3dba9	426	&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
aed773a2 CB	427	SIGN_EXTEND, 0)
aed773a2 CB	428	&& !arm_is_constant_pool_ref (op)")))
ce92b223 RE	429
	430	(define_memory_constraint "Q"
	431	"@internal
84c20253	432	An address that is a single base register."
ce92b223 RE	433	(and (match_code "mem")
	434	(match_test "REG_P (XEXP (op, 0))")))
	435
363ee90e WG	436	(define_memory_constraint "Uu"
	437	"@internal
	438	In Thumb state an address that is valid in 16bit encoding."
	439	(and (match_code "mem")
	440	(match_test "TARGET_THUMB
	441	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	442	0)")))
	443
86b60116 JB	444	; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
	445	; are actually LDM/STM instructions, so cannot be used to access unaligned
	446	; data.
	447	(define_memory_constraint "Uw"
	448	"@internal
	449	In Thumb state an address that is valid in 16bit encoding, and that can be
	450	used for unaligned accesses."
	451	(and (match_code "mem")
	452	(match_test "TARGET_THUMB
	453	&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
	454	0)
	455	&& GET_CODE (XEXP (op, 0)) != POST_INC")))
	456
0b93d3b6 RR	457	(define_constraint "US"
	458	"@internal
	459	US is a symbol reference."
	460	(match_code "symbol_ref")
	461	)
	462
3811581f AV	463	(define_memory_constraint "Uz"
	464	"@internal
	465	A memory access that is accessible as an LDC/STC operand"
	466	(and (match_code "mem")
	467	(match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
	468
ce92b223 RE	469	;; We used to have constraint letters for S and R in ARM state, but
	470	;; all uses of these now appear to have been removed.
	471
	472	;; Additionally, we used to have a Q constraint in Thumb state, but
	473	;; this wasn't really a valid memory constraint. Again, all uses of
	474	;; this now seem to have been removed.
9adcfa3c	475