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ef578491 | 1 | ;; ARM Cortex-A15 pipeline description |
a5544970 | 2 | ;; Copyright (C) 2011-2019 Free Software Foundation, Inc. |
ef578491 MGD |
3 | ;; |
4 | ;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | |
5 | ||
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify it | |
9 | ;; under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 3, or (at your option) | |
11 | ;; any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, but | |
14 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | ;; General Public License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | (define_automaton "cortex_a15") | |
23 | ||
24 | ;; The Cortex-A15 core is modelled as a triple issue pipeline that has | |
25 | ;; the following dispatch units. | |
26 | ;; 1. Two pipelines for simple integer operations: SX1, SX2 | |
855828f1 | 27 | ;; 2. Individual units for Neon and FP operations as in cortex-a15-neon.md |
ef578491 MGD |
28 | ;; 3. One pipeline for branch operations: BX |
29 | ;; 4. One pipeline for integer multiply and divide operations: MX | |
30 | ;; 5. Two pipelines for load and store operations: LS1, LS2 | |
31 | ;; | |
32 | ;; We can issue into three pipelines per-cycle. | |
33 | ;; | |
34 | ;; We assume that where we have unit pairs xx1 is always filled before xx2. | |
35 | ||
36 | ;; The three issue units | |
37 | (define_cpu_unit "ca15_i0, ca15_i1, ca15_i2" "cortex_a15") | |
38 | ||
39 | (define_reservation "ca15_issue1" "(ca15_i0|ca15_i1|ca15_i2)") | |
40 | (define_reservation "ca15_issue2" "((ca15_i0+ca15_i1)|(ca15_i1+ca15_i2))") | |
41 | (define_reservation "ca15_issue3" "(ca15_i0+ca15_i1+ca15_i2)") | |
42 | (final_presence_set "ca15_i1" "ca15_i0") | |
43 | (final_presence_set "ca15_i2" "ca15_i1") | |
44 | ||
45 | ;; The main dispatch units | |
46 | (define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15") | |
ef578491 MGD |
47 | (define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15") |
48 | (define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15") | |
49 | ||
50 | (define_reservation "ca15_ls" "(ca15_ls1|ca15_ls2)") | |
51 | ||
52 | ;; The extended load-store pipeline | |
53 | (define_cpu_unit "ca15_ldr, ca15_str" "cortex_a15") | |
54 | ||
55 | ;; The extended ALU pipeline | |
56 | (define_cpu_unit "ca15_sx1_alu, ca15_sx1_shf, ca15_sx1_sat" "cortex_a15") | |
57 | (define_cpu_unit "ca15_sx2_alu, ca15_sx2_shf, ca15_sx2_sat" "cortex_a15") | |
58 | ||
59 | ;; Simple Execution Unit: | |
60 | ;; | |
61 | ;; Simple ALU without shift | |
62 | (define_insn_reservation "cortex_a15_alu" 2 | |
63 | (and (eq_attr "tune" "cortexa15") | |
6e4150e1 | 64 | (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ |
1d61feeb | 65 | alu_sreg,alus_sreg,logic_reg,logics_reg,\ |
6e4150e1 | 66 | adc_imm,adcs_imm,adc_reg,adcs_reg,\ |
1d61feeb | 67 | adr,bfm,clz,rbit,rev,alu_dsp_reg,\ |
6e4150e1 JG |
68 | shift_imm,shift_reg,\ |
69 | mov_imm,mov_reg,\ | |
594726e4 | 70 | mvn_imm,mvn_reg,\ |
8c48eecd | 71 | mrs,multiple,no_insn")) |
ef578491 MGD |
72 | "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") |
73 | ||
74 | ;; ALU ops with immediate shift | |
ad784b91 KT |
75 | ;; crc is also included here so that appropriate scheduling of CRC32 ARMv8-A |
76 | ;; instructions can be performed when tuning for the Cortex-A57 since that | |
77 | ;; core reuses the Cortex-A15 pipeline description for the moment. | |
ef578491 MGD |
78 | (define_insn_reservation "cortex_a15_alu_shift" 3 |
79 | (and (eq_attr "tune" "cortexa15") | |
6e4150e1 JG |
80 | (eq_attr "type" "extend,\ |
81 | alu_shift_imm,alus_shift_imm,\ | |
ad784b91 | 82 | crc,logic_shift_imm,logics_shift_imm,\ |
6e4150e1 | 83 | mov_shift,mvn_shift")) |
ef578491 MGD |
84 | "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ |
85 | |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") | |
86 | ||
87 | ;; ALU ops with register controlled shift | |
88 | (define_insn_reservation "cortex_a15_alu_shift_reg" 3 | |
89 | (and (eq_attr "tune" "cortexa15") | |
6e4150e1 JG |
90 | (eq_attr "type" "alu_shift_reg,alus_shift_reg,\ |
91 | logic_shift_reg,logics_shift_reg,\ | |
92 | mov_shift_reg,mvn_shift_reg")) | |
ef578491 MGD |
93 | "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\ |
94 | |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\ | |
95 | |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)") | |
96 | ||
97 | ;; Multiply Execution Unit: | |
98 | ;; | |
99 | ;; 32-bit multiplies | |
100 | (define_insn_reservation "cortex_a15_mult32" 3 | |
101 | (and (eq_attr "tune" "cortexa15") | |
003bb7f3 | 102 | (eq_attr "mul32" "yes")) |
ef578491 MGD |
103 | "ca15_issue1,ca15_mx") |
104 | ||
105 | ;; 64-bit multiplies | |
106 | (define_insn_reservation "cortex_a15_mult64" 4 | |
107 | (and (eq_attr "tune" "cortexa15") | |
f51c724c | 108 | (eq_attr "widen_mul64" "yes")) |
ef578491 MGD |
109 | "ca15_issue1,ca15_mx*2") |
110 | ||
111 | ;; Integer divide | |
112 | (define_insn_reservation "cortex_a15_udiv" 9 | |
113 | (and (eq_attr "tune" "cortexa15") | |
09485a08 | 114 | (eq_attr "type" "udiv")) |
ef578491 MGD |
115 | "ca15_issue1,ca15_mx") |
116 | ||
117 | (define_insn_reservation "cortex_a15_sdiv" 10 | |
118 | (and (eq_attr "tune" "cortexa15") | |
09485a08 | 119 | (eq_attr "type" "sdiv")) |
ef578491 MGD |
120 | "ca15_issue1,ca15_mx") |
121 | ||
122 | ;; Block all issue pipes for a cycle | |
123 | (define_insn_reservation "cortex_a15_block" 1 | |
124 | (and (eq_attr "tune" "cortexa15") | |
003bb7f3 | 125 | (eq_attr "type" "block")) |
ef578491 MGD |
126 | "ca15_issue3") |
127 | ||
128 | ;; Branch execution Unit | |
129 | ;; | |
130 | ;; Branches take one issue slot. | |
131 | ;; No latency as there is no result | |
132 | (define_insn_reservation "cortex_a15_branch" 0 | |
133 | (and (eq_attr "tune" "cortexa15") | |
003bb7f3 | 134 | (eq_attr "type" "branch")) |
ef578491 MGD |
135 | "ca15_issue1,ca15_bx") |
136 | ||
ef578491 MGD |
137 | ;; Load-store execution Unit |
138 | ;; | |
139 | ;; Loads of up to two words. | |
140 | (define_insn_reservation "cortex_a15_load1" 4 | |
141 | (and (eq_attr "tune" "cortexa15") | |
89b2133e | 142 | (eq_attr "type" "load_byte,load_4,load_8")) |
ef578491 MGD |
143 | "ca15_issue1,ca15_ls,ca15_ldr,nothing") |
144 | ||
145 | ;; Loads of three or four words. | |
146 | (define_insn_reservation "cortex_a15_load3" 5 | |
147 | (and (eq_attr "tune" "cortexa15") | |
89b2133e | 148 | (eq_attr "type" "load_12,load_16")) |
ef578491 MGD |
149 | "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing") |
150 | ||
151 | ;; Stores of up to two words. | |
152 | (define_insn_reservation "cortex_a15_store1" 0 | |
153 | (and (eq_attr "tune" "cortexa15") | |
89b2133e | 154 | (eq_attr "type" "store_4,store_8")) |
ef578491 MGD |
155 | "ca15_issue1,ca15_ls,ca15_str") |
156 | ||
157 | ;; Stores of three or four words. | |
158 | (define_insn_reservation "cortex_a15_store3" 0 | |
159 | (and (eq_attr "tune" "cortexa15") | |
89b2133e | 160 | (eq_attr "type" "store_12,store_16")) |
ef578491 MGD |
161 | "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str") |
162 | ||
855828f1 | 163 | ;; We include Neon.md here to ensure that the branch can block the Neon units. |
1763249f | 164 | (include "../arm/cortex-a15-neon.md") |
855828f1 MGD |
165 | |
166 | ;; We lie with calls. They take up all issue slots, and form a block in the | |
167 | ;; pipeline. The result however is available the next cycle. | |
168 | (define_insn_reservation "cortex_a15_call" 1 | |
169 | (and (eq_attr "tune" "cortexa15") | |
003bb7f3 | 170 | (eq_attr "type" "call")) |
855828f1 MGD |
171 | "ca15_issue3,\ |
172 | ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\ | |
173 | ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\ | |
174 | ca15_cx_acc+ca15_cx_fmul1+ca15_cx_fmul2+ca15_cx_fmul3+ca15_cx_fmul4+\ | |
175 | ca15_cx_falu1+ca15_cx_falu2+ca15_cx_falu3+ca15_cx_falu4+ca15_cx_vfp_i,\ | |
176 | ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+\ | |
177 | ca15_sx2_shf+ca15_sx2_sat+ca15_ldr+ca15_str") | |
178 | ||
ef578491 MGD |
179 | ;; Simple execution unit bypasses |
180 | (define_bypass 1 "cortex_a15_alu" | |
181 | "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg") | |
182 | (define_bypass 2 "cortex_a15_alu_shift" | |
183 | "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg") | |
184 | (define_bypass 2 "cortex_a15_alu_shift_reg" | |
185 | "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg") | |
186 | (define_bypass 1 "cortex_a15_alu" "cortex_a15_load1,cortex_a15_load3") | |
187 | (define_bypass 2 "cortex_a15_alu_shift" "cortex_a15_load1,cortex_a15_load3") | |
188 | (define_bypass 2 "cortex_a15_alu_shift_reg" | |
189 | "cortex_a15_load1,cortex_a15_load3") |