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e0ae0288 | 1 | ;; ARM Cortex-A57 pipeline description |
a5544970 | 2 | ;; Copyright (C) 2014-2019 Free Software Foundation, Inc. |
e0ae0288 JG |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but | |
12 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
e0ae0288 JG |
14 | ;; General Public License for more details. |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_automaton "cortex_a57") | |
21 | ||
22 | (define_attr "cortex_a57_neon_type" | |
23 | "neon_abd, neon_abd_q, neon_arith_acc, neon_arith_acc_q, | |
24 | neon_arith_basic, neon_arith_complex, | |
25 | neon_reduc_add_acc, neon_multiply, neon_multiply_q, | |
26 | neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long, | |
27 | neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic, | |
28 | neon_shift_imm_complex, | |
29 | neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex, | |
30 | neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith, | |
31 | neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int, | |
32 | neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul, | |
33 | neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte, | |
34 | neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q, | |
35 | neon_bitops, neon_bitops_q, neon_from_gp, | |
36 | neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp, | |
37 | neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e, | |
38 | neon_load_f, neon_store_a, neon_store_b, neon_store_complex, | |
39 | unknown" | |
40 | (cond [ | |
41 | (eq_attr "type" "neon_abd, neon_abd_long") | |
42 | (const_string "neon_abd") | |
43 | (eq_attr "type" "neon_abd_q") | |
44 | (const_string "neon_abd_q") | |
45 | (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\ | |
46 | neon_reduc_add_acc_q") | |
47 | (const_string "neon_arith_acc") | |
48 | (eq_attr "type" "neon_arith_acc_q") | |
49 | (const_string "neon_arith_acc_q") | |
50 | (eq_attr "type" "neon_add, neon_add_q, neon_add_long,\ | |
51 | neon_add_widen, neon_neg, neon_neg_q,\ | |
52 | neon_reduc_add, neon_reduc_add_q,\ | |
53 | neon_reduc_add_long, neon_sub, neon_sub_q,\ | |
54 | neon_sub_long, neon_sub_widen, neon_logic,\ | |
55 | neon_logic_q, neon_tst, neon_tst_q") | |
56 | (const_string "neon_arith_basic") | |
57 | (eq_attr "type" "neon_abs, neon_abs_q, neon_add_halve_narrow_q,\ | |
58 | neon_add_halve, neon_add_halve_q,\ | |
59 | neon_sub_halve, neon_sub_halve_q, neon_qabs,\ | |
60 | neon_qabs_q, neon_qadd, neon_qadd_q, neon_qneg,\ | |
61 | neon_qneg_q, neon_qsub, neon_qsub_q,\ | |
62 | neon_sub_halve_narrow_q,\ | |
63 | neon_compare, neon_compare_q,\ | |
64 | neon_compare_zero, neon_compare_zero_q,\ | |
65 | neon_minmax, neon_minmax_q, neon_reduc_minmax,\ | |
66 | neon_reduc_minmax_q") | |
67 | (const_string "neon_arith_complex") | |
68 | ||
69 | (eq_attr "type" "neon_mul_b, neon_mul_h, neon_mul_s,\ | |
70 | neon_mul_h_scalar, neon_mul_s_scalar,\ | |
71 | neon_sat_mul_b, neon_sat_mul_h,\ | |
72 | neon_sat_mul_s, neon_sat_mul_h_scalar,\ | |
73 | neon_sat_mul_s_scalar,\ | |
74 | neon_mul_b_long, neon_mul_h_long,\ | |
75 | neon_mul_s_long, neon_mul_d_long,\ | |
76 | neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ | |
77 | neon_sat_mul_b_long, neon_sat_mul_h_long,\ | |
78 | neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ | |
a2074e9c | 79 | neon_sat_mul_s_scalar_long, crypto_pmull") |
e0ae0288 JG |
80 | (const_string "neon_multiply") |
81 | (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ | |
82 | neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ | |
83 | neon_sat_mul_b_q, neon_sat_mul_h_q,\ | |
84 | neon_sat_mul_s_q, neon_sat_mul_h_scalar_q,\ | |
85 | neon_sat_mul_s_scalar_q") | |
86 | (const_string "neon_multiply_q") | |
87 | (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\ | |
88 | neon_mla_h_scalar, neon_mla_s_scalar,\ | |
89 | neon_mla_b_long, neon_mla_h_long,\ | |
90 | neon_mla_s_long,\ | |
91 | neon_mla_h_scalar_long, neon_mla_s_scalar_long") | |
92 | (const_string "neon_mla") | |
93 | (eq_attr "type" "neon_mla_b_q, neon_mla_h_q, neon_mla_s_q,\ | |
94 | neon_mla_h_scalar_q, neon_mla_s_scalar_q") | |
95 | (const_string "neon_mla_q") | |
96 | (eq_attr "type" "neon_sat_mla_b_long, neon_sat_mla_h_long,\ | |
97 | neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ | |
98 | neon_sat_mla_s_scalar_long") | |
99 | (const_string "neon_sat_mla_long") | |
100 | ||
101 | (eq_attr "type" "neon_shift_acc, neon_shift_acc_q") | |
102 | (const_string "neon_shift_acc") | |
103 | (eq_attr "type" "neon_shift_imm, neon_shift_imm_q,\ | |
104 | neon_shift_imm_narrow_q, neon_shift_imm_long") | |
105 | (const_string "neon_shift_imm_basic") | |
106 | (eq_attr "type" "neon_sat_shift_imm, neon_sat_shift_imm_q,\ | |
107 | neon_sat_shift_imm_narrow_q") | |
108 | (const_string "neon_shift_imm_complex") | |
109 | (eq_attr "type" "neon_shift_reg") | |
110 | (const_string "neon_shift_reg_basic") | |
111 | (eq_attr "type" "neon_shift_reg_q") | |
112 | (const_string "neon_shift_reg_basic_q") | |
113 | (eq_attr "type" "neon_sat_shift_reg") | |
114 | (const_string "neon_shift_reg_complex") | |
115 | (eq_attr "type" "neon_sat_shift_reg_q") | |
116 | (const_string "neon_shift_reg_complex_q") | |
117 | ||
118 | (eq_attr "type" "neon_fp_neg_s, neon_fp_neg_s_q,\ | |
119 | neon_fp_abs_s, neon_fp_abs_s_q,\ | |
120 | neon_fp_neg_d, neon_fp_neg_d_q,\ | |
121 | neon_fp_abs_d, neon_fp_abs_d_q") | |
122 | (const_string "neon_fp_negabs") | |
123 | (eq_attr "type" "neon_fp_addsub_s, neon_fp_abd_s,\ | |
124 | neon_fp_reduc_add_s, neon_fp_compare_s,\ | |
125 | neon_fp_minmax_s, neon_fp_round_s,\ | |
126 | neon_fp_addsub_d, neon_fp_abd_d,\ | |
127 | neon_fp_reduc_add_d, neon_fp_compare_d,\ | |
128 | neon_fp_minmax_d, neon_fp_round_d,\ | |
129 | neon_fp_reduc_minmax_s, neon_fp_reduc_minmax_d") | |
130 | (const_string "neon_fp_arith") | |
131 | (eq_attr "type" "neon_fp_addsub_s_q, neon_fp_abd_s_q,\ | |
132 | neon_fp_reduc_add_s_q, neon_fp_compare_s_q,\ | |
133 | neon_fp_minmax_s_q, neon_fp_round_s_q,\ | |
134 | neon_fp_addsub_d_q, neon_fp_abd_d_q,\ | |
135 | neon_fp_reduc_add_d_q, neon_fp_compare_d_q,\ | |
136 | neon_fp_minmax_d_q, neon_fp_round_d_q") | |
137 | (const_string "neon_fp_arith_q") | |
138 | (eq_attr "type" "neon_fp_reduc_minmax_s_q,\ | |
139 | neon_fp_reduc_minmax_d_q,\ | |
140 | neon_fp_reduc_add_s_q, neon_fp_reduc_add_d_q") | |
141 | (const_string "neon_fp_reductions_q") | |
142 | (eq_attr "type" "neon_fp_to_int_s, neon_int_to_fp_s,\ | |
143 | neon_fp_to_int_d, neon_int_to_fp_d") | |
144 | (const_string "neon_fp_cvt_int") | |
145 | (eq_attr "type" "neon_fp_to_int_s_q, neon_int_to_fp_s_q,\ | |
146 | neon_fp_to_int_d_q, neon_int_to_fp_d_q") | |
147 | (const_string "neon_fp_cvt_int_q") | |
148 | (eq_attr "type" "neon_fp_cvt_narrow_s_q, neon_fp_cvt_widen_h") | |
149 | (const_string "neon_fp_cvt16") | |
150 | (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_s_scalar,\ | |
151 | neon_fp_mul_d") | |
152 | (const_string "neon_fp_mul") | |
153 | (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_s_scalar_q,\ | |
154 | neon_fp_mul_d_q, neon_fp_mul_d_scalar_q") | |
155 | (const_string "neon_fp_mul_q") | |
156 | (eq_attr "type" "neon_fp_mla_s, neon_fp_mla_s_scalar,\ | |
157 | neon_fp_mla_d") | |
158 | (const_string "neon_fp_mla") | |
159 | (eq_attr "type" "neon_fp_mla_s_q, neon_fp_mla_s_scalar_q, | |
160 | neon_fp_mla_d_q, neon_fp_mla_d_scalar_q") | |
161 | (const_string "neon_fp_mla_q") | |
162 | (eq_attr "type" "neon_fp_recpe_s, neon_fp_rsqrte_s,\ | |
163 | neon_fp_recpx_s,\ | |
164 | neon_fp_recpe_d, neon_fp_rsqrte_d,\ | |
165 | neon_fp_recpx_d") | |
166 | (const_string "neon_fp_recpe_rsqrte") | |
167 | (eq_attr "type" "neon_fp_recpe_s_q, neon_fp_rsqrte_s_q,\ | |
168 | neon_fp_recpx_s_q,\ | |
169 | neon_fp_recpe_d_q, neon_fp_rsqrte_d_q,\ | |
170 | neon_fp_recpx_d_q") | |
171 | (const_string "neon_fp_recpe_rsqrte_q") | |
172 | (eq_attr "type" "neon_fp_recps_s, neon_fp_rsqrts_s,\ | |
173 | neon_fp_recps_d, neon_fp_rsqrts_d") | |
174 | (const_string "neon_fp_recps_rsqrts") | |
175 | (eq_attr "type" "neon_fp_recps_s_q, neon_fp_rsqrts_s_q,\ | |
176 | neon_fp_recps_d_q, neon_fp_rsqrts_d_q") | |
177 | (const_string "neon_fp_recps_rsqrts_q") | |
178 | (eq_attr "type" "neon_bsl, neon_cls, neon_cnt,\ | |
179 | neon_rev, neon_permute, neon_rbit,\ | |
180 | neon_tbl1, neon_tbl2, neon_zip,\ | |
181 | neon_dup, neon_dup_q, neon_ext, neon_ext_q,\ | |
182 | neon_move, neon_move_q, neon_move_narrow_q") | |
183 | (const_string "neon_bitops") | |
184 | (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\ | |
185 | neon_rev_q, neon_permute_q, neon_rbit_q") | |
186 | (const_string "neon_bitops_q") | |
187 | (eq_attr "type" "neon_from_gp,f_mcr,f_mcrr") | |
188 | (const_string "neon_from_gp") | |
189 | (eq_attr "type" "neon_from_gp_q") | |
190 | (const_string "neon_from_gp_q") | |
191 | (eq_attr "type" "neon_tbl3, neon_tbl4") | |
192 | (const_string "neon_tbl3_tbl4") | |
193 | (eq_attr "type" "neon_zip_q") | |
194 | (const_string "neon_zip_q") | |
195 | (eq_attr "type" "neon_to_gp, neon_to_gp_q,f_mrc,f_mrrc") | |
196 | (const_string "neon_to_gp") | |
197 | ||
198 | (eq_attr "type" "f_loads, f_loadd,\ | |
199 | neon_load1_1reg, neon_load1_1reg_q,\ | |
200 | neon_load1_2reg, neon_load1_2reg_q") | |
201 | (const_string "neon_load_a") | |
202 | (eq_attr "type" "neon_load1_3reg, neon_load1_3reg_q,\ | |
203 | neon_load1_4reg, neon_load1_4reg_q") | |
204 | (const_string "neon_load_b") | |
5c4b7f1c EM |
205 | (eq_attr "type" "neon_ldp, neon_ldp_q,\ |
206 | neon_load1_one_lane, neon_load1_one_lane_q,\ | |
e0ae0288 JG |
207 | neon_load1_all_lanes, neon_load1_all_lanes_q,\ |
208 | neon_load2_2reg, neon_load2_2reg_q,\ | |
209 | neon_load2_all_lanes, neon_load2_all_lanes_q") | |
210 | (const_string "neon_load_c") | |
211 | (eq_attr "type" "neon_load2_4reg, neon_load2_4reg_q,\ | |
212 | neon_load3_3reg, neon_load3_3reg_q,\ | |
213 | neon_load3_one_lane, neon_load3_one_lane_q,\ | |
214 | neon_load4_4reg, neon_load4_4reg_q") | |
215 | (const_string "neon_load_d") | |
216 | (eq_attr "type" "neon_load2_one_lane, neon_load2_one_lane_q,\ | |
217 | neon_load3_all_lanes, neon_load3_all_lanes_q,\ | |
218 | neon_load4_all_lanes, neon_load4_all_lanes_q") | |
219 | (const_string "neon_load_e") | |
220 | (eq_attr "type" "neon_load4_one_lane, neon_load4_one_lane_q") | |
221 | (const_string "neon_load_f") | |
222 | ||
223 | (eq_attr "type" "f_stores, f_stored,\ | |
224 | neon_store1_1reg") | |
225 | (const_string "neon_store_a") | |
226 | (eq_attr "type" "neon_store1_2reg, neon_store1_1reg_q") | |
227 | (const_string "neon_store_b") | |
5c4b7f1c EM |
228 | (eq_attr "type" "neon_stp, neon_stp_q,\ |
229 | neon_store1_3reg, neon_store1_3reg_q,\ | |
e0ae0288 JG |
230 | neon_store3_3reg, neon_store3_3reg_q,\ |
231 | neon_store2_4reg, neon_store2_4reg_q,\ | |
232 | neon_store4_4reg, neon_store4_4reg_q,\ | |
233 | neon_store2_2reg, neon_store2_2reg_q,\ | |
234 | neon_store3_one_lane, neon_store3_one_lane_q,\ | |
235 | neon_store4_one_lane, neon_store4_one_lane_q,\ | |
236 | neon_store1_4reg, neon_store1_4reg_q,\ | |
237 | neon_store1_one_lane, neon_store1_one_lane_q,\ | |
238 | neon_store2_one_lane, neon_store2_one_lane_q") | |
239 | (const_string "neon_store_complex")] | |
240 | (const_string "unknown"))) | |
241 | ||
242 | ;; The Cortex-A57 core is modelled as a triple issue pipeline that has | |
243 | ;; the following functional units. | |
244 | ;; 1. Two pipelines for integer operations: SX1, SX2 | |
245 | ||
246 | (define_cpu_unit "ca57_sx1_issue" "cortex_a57") | |
247 | (define_reservation "ca57_sx1" "ca57_sx1_issue") | |
248 | ||
249 | (define_cpu_unit "ca57_sx2_issue" "cortex_a57") | |
250 | (define_reservation "ca57_sx2" "ca57_sx2_issue") | |
251 | ||
252 | ;; 2. One pipeline for complex integer operations: MX | |
253 | ||
254 | (define_cpu_unit "ca57_mx_issue" | |
255 | "cortex_a57") | |
256 | (define_reservation "ca57_mx" "ca57_mx_issue") | |
257 | (define_reservation "ca57_mx_block" "ca57_mx_issue") | |
258 | ||
259 | ;; 3. Two asymmetric pipelines for Neon and FP operations: CX1, CX2 | |
260 | (define_automaton "cortex_a57_cx") | |
261 | ||
262 | (define_cpu_unit "ca57_cx1_issue" | |
263 | "cortex_a57_cx") | |
264 | (define_cpu_unit "ca57_cx2_issue" | |
265 | "cortex_a57_cx") | |
266 | ||
267 | (define_reservation "ca57_cx1" "ca57_cx1_issue") | |
268 | ||
269 | (define_reservation "ca57_cx2" "ca57_cx2_issue") | |
270 | (define_reservation "ca57_cx2_block" "ca57_cx2_issue*2") | |
271 | ||
272 | ;; 4. One pipeline for branch operations: BX | |
273 | ||
274 | (define_cpu_unit "ca57_bx_issue" "cortex_a57") | |
275 | (define_reservation "ca57_bx" "ca57_bx_issue") | |
276 | ||
277 | ;; 5. Two pipelines for load and store operations: LS1, LS2. The most | |
278 | ;; valuable thing we can do is force a structural hazard to split | |
279 | ;; up loads/stores. | |
280 | ||
281 | (define_cpu_unit "ca57_ls_issue" "cortex_a57") | |
282 | (define_cpu_unit "ca57_ldr, ca57_str" "cortex_a57") | |
283 | (define_reservation "ca57_load_model" "ca57_ls_issue,ca57_ldr*2") | |
284 | (define_reservation "ca57_store_model" "ca57_ls_issue,ca57_str") | |
285 | ||
286 | ;; Block all issue queues. | |
287 | ||
288 | (define_reservation "ca57_block" "ca57_cx1_issue + ca57_cx2_issue | |
289 | + ca57_mx_issue + ca57_sx1_issue | |
290 | + ca57_sx2_issue + ca57_ls_issue") | |
291 | ||
292 | ;; Simple Execution Unit: | |
293 | ;; | |
294 | ;; Simple ALU without shift | |
295 | (define_insn_reservation "cortex_a57_alu" 2 | |
296 | (and (eq_attr "tune" "cortexa57") | |
297 | (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ | |
298 | alu_sreg,alus_sreg,logic_reg,logics_reg,\ | |
299 | adc_imm,adcs_imm,adc_reg,adcs_reg,\ | |
f6b9a2a0 | 300 | adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\ |
b81f1ee3 | 301 | rotate_imm,shift_imm,shift_reg,\ |
e0ae0288 JG |
302 | mov_imm,mov_reg,\ |
303 | mvn_imm,mvn_reg,\ | |
304 | mrs,multiple,no_insn")) | |
305 | "ca57_sx1|ca57_sx2") | |
306 | ||
307 | ;; ALU ops with immediate shift | |
308 | (define_insn_reservation "cortex_a57_alu_shift" 3 | |
309 | (and (eq_attr "tune" "cortexa57") | |
f6b9a2a0 | 310 | (eq_attr "type" "bfm,\ |
e0ae0288 JG |
311 | alu_shift_imm,alus_shift_imm,\ |
312 | crc,logic_shift_imm,logics_shift_imm,\ | |
313 | mov_shift,mvn_shift")) | |
314 | "ca57_mx") | |
315 | ||
316 | ;; Multi-Cycle Execution Unit: | |
317 | ;; | |
318 | ;; ALU ops with register controlled shift | |
319 | (define_insn_reservation "cortex_a57_alu_shift_reg" 3 | |
320 | (and (eq_attr "tune" "cortexa57") | |
321 | (eq_attr "type" "alu_shift_reg,alus_shift_reg,\ | |
322 | logic_shift_reg,logics_shift_reg,\ | |
323 | mov_shift_reg,mvn_shift_reg")) | |
324 | "ca57_mx") | |
325 | ||
326 | ;; All multiplies | |
9c582551 | 327 | ;; TODO: AArch32 and AArch64 have different behavior |
e0ae0288 JG |
328 | (define_insn_reservation "cortex_a57_mult32" 3 |
329 | (and (eq_attr "tune" "cortexa57") | |
330 | (ior (eq_attr "mul32" "yes") | |
f51c724c | 331 | (eq_attr "widen_mul64" "yes"))) |
e0ae0288 JG |
332 | "ca57_mx") |
333 | ||
334 | ;; Integer divide | |
335 | (define_insn_reservation "cortex_a57_div" 10 | |
336 | (and (eq_attr "tune" "cortexa57") | |
337 | (eq_attr "type" "udiv,sdiv")) | |
338 | "ca57_mx_issue,ca57_mx_block*3") | |
339 | ||
340 | ;; Block all issue pipes for a cycle | |
341 | (define_insn_reservation "cortex_a57_block" 1 | |
342 | (and (eq_attr "tune" "cortexa57") | |
343 | (eq_attr "type" "block")) | |
344 | "ca57_block") | |
345 | ||
346 | ;; Branch execution Unit | |
347 | ;; | |
348 | ;; Branches take one issue slot. | |
349 | ;; No latency as there is no result | |
350 | (define_insn_reservation "cortex_a57_branch" 0 | |
351 | (and (eq_attr "tune" "cortexa57") | |
352 | (eq_attr "type" "branch")) | |
353 | "ca57_bx") | |
354 | ||
355 | ;; Load-store execution Unit | |
356 | ;; | |
357 | ;; Loads of up to two words. | |
358 | (define_insn_reservation "cortex_a57_load1" 5 | |
359 | (and (eq_attr "tune" "cortexa57") | |
89b2133e | 360 | (eq_attr "type" "load_byte,load_4,load_8")) |
e0ae0288 JG |
361 | "ca57_load_model") |
362 | ||
363 | ;; Loads of three or four words. | |
364 | (define_insn_reservation "cortex_a57_load3" 5 | |
365 | (and (eq_attr "tune" "cortexa57") | |
89b2133e | 366 | (eq_attr "type" "load_12,load_16")) |
e0ae0288 JG |
367 | "ca57_ls_issue*2,ca57_load_model") |
368 | ||
369 | ;; Stores of up to two words. | |
370 | (define_insn_reservation "cortex_a57_store1" 0 | |
371 | (and (eq_attr "tune" "cortexa57") | |
89b2133e | 372 | (eq_attr "type" "store_4,store_8")) |
e0ae0288 JG |
373 | "ca57_store_model") |
374 | ||
375 | ;; Stores of three or four words. | |
376 | (define_insn_reservation "cortex_a57_store3" 0 | |
377 | (and (eq_attr "tune" "cortexa57") | |
89b2133e | 378 | (eq_attr "type" "store_12,store_16")) |
e0ae0288 JG |
379 | "ca57_ls_issue*2,ca57_store_model") |
380 | ||
381 | ;; Advanced SIMD Unit - Integer Arithmetic Instructions. | |
382 | ||
383 | (define_insn_reservation "cortex_a57_neon_abd" 5 | |
384 | (and (eq_attr "tune" "cortexa57") | |
385 | (eq_attr "cortex_a57_neon_type" "neon_abd")) | |
386 | "ca57_cx1|ca57_cx2") | |
387 | ||
388 | (define_insn_reservation "cortex_a57_neon_abd_q" 5 | |
389 | (and (eq_attr "tune" "cortexa57") | |
390 | (eq_attr "cortex_a57_neon_type" "neon_abd_q")) | |
391 | "ca57_cx1+ca57_cx2") | |
392 | ||
393 | (define_insn_reservation "cortex_a57_neon_aba" 7 | |
394 | (and (eq_attr "tune" "cortexa57") | |
395 | (eq_attr "cortex_a57_neon_type" "neon_arith_acc")) | |
396 | "ca57_cx2") | |
397 | ||
398 | (define_insn_reservation "cortex_a57_neon_aba_q" 8 | |
399 | (and (eq_attr "tune" "cortexa57") | |
400 | (eq_attr "cortex_a57_neon_type" "neon_arith_acc_q")) | |
401 | "ca57_cx2+(ca57_cx2_issue,ca57_cx2)") | |
402 | ||
403 | (define_insn_reservation "cortex_a57_neon_arith_basic" 4 | |
404 | (and (eq_attr "tune" "cortexa57") | |
405 | (eq_attr "cortex_a57_neon_type" "neon_arith_basic")) | |
406 | "ca57_cx1|ca57_cx2") | |
407 | ||
408 | (define_insn_reservation "cortex_a57_neon_arith_complex" 5 | |
409 | (and (eq_attr "tune" "cortexa57") | |
410 | (eq_attr "cortex_a57_neon_type" "neon_arith_complex")) | |
411 | "ca57_cx1|ca57_cx2") | |
412 | ||
413 | ;; Integer Multiply Instructions. | |
414 | ||
415 | (define_insn_reservation "cortex_a57_neon_multiply" 6 | |
416 | (and (eq_attr "tune" "cortexa57") | |
417 | (eq_attr "cortex_a57_neon_type" "neon_multiply")) | |
418 | "ca57_cx1") | |
419 | ||
420 | (define_insn_reservation "cortex_a57_neon_multiply_q" 7 | |
421 | (and (eq_attr "tune" "cortexa57") | |
422 | (eq_attr "cortex_a57_neon_type" "neon_multiply_q")) | |
423 | "ca57_cx1+(ca57_cx1_issue,ca57_cx1)") | |
424 | ||
425 | (define_insn_reservation "cortex_a57_neon_mla" 6 | |
426 | (and (eq_attr "tune" "cortexa57") | |
427 | (eq_attr "cortex_a57_neon_type" "neon_mla")) | |
428 | "ca57_cx1") | |
429 | ||
430 | (define_insn_reservation "cortex_a57_neon_mla_q" 7 | |
431 | (and (eq_attr "tune" "cortexa57") | |
432 | (eq_attr "cortex_a57_neon_type" "neon_mla_q")) | |
433 | "ca57_cx1+(ca57_cx1_issue,ca57_cx1)") | |
434 | ||
435 | (define_insn_reservation "cortex_a57_neon_sat_mla_long" 6 | |
436 | (and (eq_attr "tune" "cortexa57") | |
437 | (eq_attr "cortex_a57_neon_type" "neon_sat_mla_long")) | |
438 | "ca57_cx1") | |
439 | ||
440 | ;; Integer Shift Instructions. | |
441 | ||
442 | (define_insn_reservation | |
443 | "cortex_a57_neon_shift_acc" 7 | |
444 | (and (eq_attr "tune" "cortexa57") | |
445 | (eq_attr "cortex_a57_neon_type" "neon_shift_acc")) | |
446 | "ca57_cx2") | |
447 | ||
448 | (define_insn_reservation | |
449 | "cortex_a57_neon_shift_imm_basic" 4 | |
450 | (and (eq_attr "tune" "cortexa57") | |
451 | (eq_attr "cortex_a57_neon_type" "neon_shift_imm_basic")) | |
452 | "ca57_cx2") | |
453 | ||
454 | (define_insn_reservation | |
455 | "cortex_a57_neon_shift_imm_complex" 5 | |
456 | (and (eq_attr "tune" "cortexa57") | |
457 | (eq_attr "cortex_a57_neon_type" "neon_shift_imm_complex")) | |
458 | "ca57_cx2") | |
459 | ||
460 | (define_insn_reservation | |
461 | "cortex_a57_neon_shift_reg_basic" 4 | |
462 | (and (eq_attr "tune" "cortexa57") | |
463 | (eq_attr "cortex_a57_neon_type" "neon_shift_reg_basic")) | |
464 | "ca57_cx2") | |
465 | ||
466 | (define_insn_reservation | |
467 | "cortex_a57_neon_shift_reg_basic_q" 5 | |
468 | (and (eq_attr "tune" "cortexa57") | |
469 | (eq_attr "cortex_a57_neon_type" "neon_shift_reg_basic_q")) | |
470 | "ca57_cx2+(ca57_cx2_issue,ca57_cx2)") | |
471 | ||
472 | (define_insn_reservation | |
473 | "cortex_a57_neon_shift_reg_complex" 5 | |
474 | (and (eq_attr "tune" "cortexa57") | |
475 | (eq_attr "cortex_a57_neon_type" "neon_shift_reg_complex")) | |
476 | "ca57_cx2") | |
477 | ||
478 | (define_insn_reservation | |
479 | "cortex_a57_neon_shift_reg_complex_q" 6 | |
480 | (and (eq_attr "tune" "cortexa57") | |
481 | (eq_attr "cortex_a57_neon_type" "neon_shift_reg_complex_q")) | |
482 | "ca57_cx2+(ca57_cx2_issue,ca57_cx2)") | |
483 | ||
484 | ;; Floating Point Instructions. | |
485 | ||
486 | (define_insn_reservation | |
487 | "cortex_a57_neon_fp_negabs" 4 | |
488 | (and (eq_attr "tune" "cortexa57") | |
489 | (eq_attr "cortex_a57_neon_type" "neon_fp_negabs")) | |
490 | "(ca57_cx1|ca57_cx2)") | |
491 | ||
492 | (define_insn_reservation | |
493 | "cortex_a57_neon_fp_arith" 6 | |
494 | (and (eq_attr "tune" "cortexa57") | |
495 | (eq_attr "cortex_a57_neon_type" "neon_fp_arith")) | |
496 | "(ca57_cx1|ca57_cx2)") | |
497 | ||
498 | (define_insn_reservation | |
499 | "cortex_a57_neon_fp_arith_q" 6 | |
500 | (and (eq_attr "tune" "cortexa57") | |
501 | (eq_attr "cortex_a57_neon_type" "neon_fp_arith_q")) | |
502 | "(ca57_cx1+ca57_cx2)") | |
503 | ||
504 | (define_insn_reservation | |
505 | "cortex_a57_neon_fp_reductions_q" 10 | |
506 | (and (eq_attr "tune" "cortexa57") | |
507 | (eq_attr "cortex_a57_neon_type" "neon_fp_reductions_q")) | |
508 | "(ca57_cx1+ca57_cx2),(ca57_cx1|ca57_cx2)") | |
509 | ||
510 | (define_insn_reservation | |
511 | "cortex_a57_neon_fp_cvt_int" 6 | |
512 | (and (eq_attr "tune" "cortexa57") | |
513 | (eq_attr "cortex_a57_neon_type" "neon_fp_cvt_int")) | |
514 | "(ca57_cx1|ca57_cx2)") | |
515 | ||
516 | (define_insn_reservation | |
517 | "cortex_a57_neon_fp_cvt_int_q" 6 | |
518 | (and (eq_attr "tune" "cortexa57") | |
519 | (eq_attr "cortex_a57_neon_type" "neon_fp_cvt_int_q")) | |
520 | "(ca57_cx1+ca57_cx2)") | |
521 | ||
522 | (define_insn_reservation | |
523 | "cortex_a57_neon_fp_cvt16" 10 | |
524 | (and (eq_attr "tune" "cortexa57") | |
525 | (eq_attr "cortex_a57_neon_type" "neon_fp_cvt16")) | |
526 | "(ca57_cx1_issue+ca57_cx2_issue),(ca57_cx1|ca57_cx2)") | |
527 | ||
528 | (define_insn_reservation | |
529 | "cortex_a57_neon_fp_mul" 5 | |
530 | (and (eq_attr "tune" "cortexa57") | |
531 | (eq_attr "cortex_a57_neon_type" "neon_fp_mul")) | |
532 | "(ca57_cx1|ca57_cx2)") | |
533 | ||
534 | (define_insn_reservation | |
535 | "cortex_a57_neon_fp_mul_q" 5 | |
536 | (and (eq_attr "tune" "cortexa57") | |
537 | (eq_attr "cortex_a57_neon_type" "neon_fp_mul_q")) | |
538 | "(ca57_cx1+ca57_cx2)") | |
539 | ||
540 | (define_insn_reservation | |
541 | "cortex_a57_neon_fp_mla" 9 | |
542 | (and (eq_attr "tune" "cortexa57") | |
543 | (eq_attr "cortex_a57_neon_type" "neon_fp_mla")) | |
544 | "(ca57_cx1,ca57_cx1)|(ca57_cx2,ca57_cx2)") | |
545 | ||
546 | (define_insn_reservation | |
547 | "cortex_a57_neon_fp_mla_q" 9 | |
548 | (and (eq_attr "tune" "cortexa57") | |
549 | (eq_attr "cortex_a57_neon_type" "neon_fp_mla_q")) | |
550 | "(ca57_cx1+ca57_cx2),(ca57_cx1,ca57_cx2)") | |
551 | ||
552 | (define_insn_reservation | |
553 | "cortex_a57_neon_fp_recpe_rsqrte" 6 | |
554 | (and (eq_attr "tune" "cortexa57") | |
555 | (eq_attr "cortex_a57_neon_type" "neon_fp_recpe_rsqrte")) | |
556 | "(ca57_cx1|ca57_cx2)") | |
557 | ||
558 | (define_insn_reservation | |
559 | "cortex_a57_neon_fp_recpe_rsqrte_q" 6 | |
560 | (and (eq_attr "tune" "cortexa57") | |
561 | (eq_attr "cortex_a57_neon_type" "neon_fp_recpe_rsqrte_q")) | |
562 | "(ca57_cx1+ca57_cx2)") | |
563 | ||
564 | (define_insn_reservation | |
565 | "cortex_a57_neon_fp_recps_rsqrts" 10 | |
566 | (and (eq_attr "tune" "cortexa57") | |
567 | (eq_attr "cortex_a57_neon_type" "neon_fp_recps_rsqrts")) | |
568 | "(ca57_cx1|ca57_cx2)") | |
569 | ||
570 | (define_insn_reservation | |
571 | "cortex_a57_neon_fp_recps_rsqrts_q" 10 | |
572 | (and (eq_attr "tune" "cortexa57") | |
573 | (eq_attr "cortex_a57_neon_type" "neon_fp_recps_rsqrts_q")) | |
574 | "(ca57_cx1+ca57_cx2)") | |
575 | ||
576 | ;; Miscellaneous Instructions. | |
577 | ||
578 | (define_insn_reservation | |
579 | "cortex_a57_neon_bitops" 4 | |
580 | (and (eq_attr "tune" "cortexa57") | |
581 | (eq_attr "cortex_a57_neon_type" "neon_bitops")) | |
582 | "(ca57_cx1|ca57_cx2)") | |
583 | ||
584 | (define_insn_reservation | |
585 | "cortex_a57_neon_bitops_q" 4 | |
586 | (and (eq_attr "tune" "cortexa57") | |
587 | (eq_attr "cortex_a57_neon_type" "neon_bitops_q")) | |
588 | "(ca57_cx1+ca57_cx2)") | |
589 | ||
590 | (define_insn_reservation | |
591 | "cortex_a57_neon_from_gp" 9 | |
592 | (and (eq_attr "tune" "cortexa57") | |
593 | (eq_attr "cortex_a57_neon_type" "neon_from_gp")) | |
594 | "(ca57_ls_issue+ca57_cx1_issue,ca57_cx1) | |
595 | |(ca57_ls_issue+ca57_cx2_issue,ca57_cx2)") | |
596 | ||
597 | (define_insn_reservation | |
598 | "cortex_a57_neon_from_gp_q" 9 | |
599 | (and (eq_attr "tune" "cortexa57") | |
600 | (eq_attr "cortex_a57_neon_type" "neon_from_gp_q")) | |
601 | "(ca57_ls_issue+ca57_cx1_issue,ca57_cx1) | |
602 | +(ca57_ls_issue+ca57_cx2_issue,ca57_cx2)") | |
603 | ||
604 | (define_insn_reservation | |
605 | "cortex_a57_neon_tbl3_tbl4" 7 | |
606 | (and (eq_attr "tune" "cortexa57") | |
607 | (eq_attr "cortex_a57_neon_type" "neon_tbl3_tbl4")) | |
608 | "(ca57_cx1_issue,ca57_cx1) | |
609 | +(ca57_cx2_issue,ca57_cx2)") | |
610 | ||
611 | (define_insn_reservation | |
612 | "cortex_a57_neon_zip_q" 7 | |
613 | (and (eq_attr "tune" "cortexa57") | |
614 | (eq_attr "cortex_a57_neon_type" "neon_zip_q")) | |
615 | "(ca57_cx1_issue,ca57_cx1) | |
616 | +(ca57_cx2_issue,ca57_cx2)") | |
617 | ||
618 | (define_insn_reservation | |
619 | "cortex_a57_neon_to_gp" 7 | |
620 | (and (eq_attr "tune" "cortexa57") | |
621 | (eq_attr "cortex_a57_neon_type" "neon_to_gp")) | |
622 | "((ca57_ls_issue+ca57_sx1_issue),ca57_sx1) | |
623 | |((ca57_ls_issue+ca57_sx2_issue),ca57_sx2)") | |
624 | ||
625 | ;; Load Instructions. | |
626 | ||
627 | (define_insn_reservation | |
628 | "cortex_a57_neon_load_a" 6 | |
629 | (and (eq_attr "tune" "cortexa57") | |
630 | (eq_attr "cortex_a57_neon_type" "neon_load_a")) | |
631 | "ca57_load_model") | |
632 | ||
633 | (define_insn_reservation | |
634 | "cortex_a57_neon_load_b" 7 | |
635 | (and (eq_attr "tune" "cortexa57") | |
636 | (eq_attr "cortex_a57_neon_type" "neon_load_b")) | |
637 | "ca57_ls_issue,ca57_ls_issue+ca57_ldr,ca57_ldr*2") | |
638 | ||
639 | (define_insn_reservation | |
640 | "cortex_a57_neon_load_c" 9 | |
641 | (and (eq_attr "tune" "cortexa57") | |
642 | (eq_attr "cortex_a57_neon_type" "neon_load_c")) | |
643 | "ca57_load_model+(ca57_cx1|ca57_cx2)") | |
644 | ||
645 | (define_insn_reservation | |
646 | "cortex_a57_neon_load_d" 11 | |
647 | (and (eq_attr "tune" "cortexa57") | |
648 | (eq_attr "cortex_a57_neon_type" "neon_load_d")) | |
649 | "ca57_cx1_issue+ca57_cx2_issue, | |
650 | ca57_ls_issue+ca57_ls_issue,ca57_ldr*2") | |
651 | ||
652 | (define_insn_reservation | |
653 | "cortex_a57_neon_load_e" 9 | |
654 | (and (eq_attr "tune" "cortexa57") | |
655 | (eq_attr "cortex_a57_neon_type" "neon_load_e")) | |
656 | "ca57_load_model+(ca57_cx1|ca57_cx2)") | |
657 | ||
658 | (define_insn_reservation | |
659 | "cortex_a57_neon_load_f" 11 | |
660 | (and (eq_attr "tune" "cortexa57") | |
661 | (eq_attr "cortex_a57_neon_type" "neon_load_f")) | |
662 | "ca57_cx1_issue+ca57_cx2_issue, | |
663 | ca57_ls_issue+ca57_ls_issue,ca57_ldr*2") | |
664 | ||
665 | ;; Store Instructions. | |
666 | ||
667 | (define_insn_reservation | |
668 | "cortex_a57_neon_store_a" 0 | |
669 | (and (eq_attr "tune" "cortexa57") | |
670 | (eq_attr "cortex_a57_neon_type" "neon_store_a")) | |
671 | "ca57_store_model") | |
672 | ||
673 | (define_insn_reservation | |
674 | "cortex_a57_neon_store_b" 0 | |
675 | (and (eq_attr "tune" "cortexa57") | |
676 | (eq_attr "cortex_a57_neon_type" "neon_store_b")) | |
677 | "ca57_store_model") | |
678 | ||
679 | ;; These block issue for a number of cycles proportional to the number | |
680 | ;; of 64-bit chunks they will store, we don't attempt to model that | |
681 | ;; precisely, treat them as blocking execution for two cycles when | |
682 | ;; issued. | |
683 | (define_insn_reservation | |
684 | "cortex_a57_neon_store_complex" 0 | |
685 | (and (eq_attr "tune" "cortexa57") | |
686 | (eq_attr "cortex_a57_neon_type" "neon_store_complex")) | |
687 | "ca57_block*2") | |
688 | ||
689 | ;; Floating-Point Operations. | |
690 | ||
691 | (define_insn_reservation "cortex_a57_fp_const" 4 | |
692 | (and (eq_attr "tune" "cortexa57") | |
693 | (eq_attr "type" "fconsts,fconstd")) | |
694 | "(ca57_cx1|ca57_cx2)") | |
695 | ||
696 | (define_insn_reservation "cortex_a57_fp_add_sub" 6 | |
697 | (and (eq_attr "tune" "cortexa57") | |
698 | (eq_attr "type" "fadds,faddd")) | |
699 | "(ca57_cx1|ca57_cx2)") | |
700 | ||
701 | (define_insn_reservation "cortex_a57_fp_mul" 6 | |
702 | (and (eq_attr "tune" "cortexa57") | |
703 | (eq_attr "type" "fmuls,fmuld")) | |
704 | "(ca57_cx1|ca57_cx2)") | |
705 | ||
706 | (define_insn_reservation "cortex_a57_fp_mac" 10 | |
707 | (and (eq_attr "tune" "cortexa57") | |
708 | (eq_attr "type" "fmacs,ffmas,fmacd,ffmad")) | |
709 | "(ca57_cx1,nothing,nothing,ca57_cx1) \ | |
710 | |(ca57_cx2,nothing,nothing,ca57_cx2)") | |
711 | ||
712 | (define_insn_reservation "cortex_a57_fp_cvt" 6 | |
713 | (and (eq_attr "tune" "cortexa57") | |
714 | (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f")) | |
715 | "(ca57_cx1|ca57_cx2)") | |
716 | ||
717 | (define_insn_reservation "cortex_a57_fp_cmp" 7 | |
718 | (and (eq_attr "tune" "cortexa57") | |
c297d256 | 719 | (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd")) |
e0ae0288 JG |
720 | "ca57_cx2") |
721 | ||
722 | (define_insn_reservation "cortex_a57_fp_arith" 4 | |
723 | (and (eq_attr "tune" "cortexa57") | |
724 | (eq_attr "type" "ffariths,ffarithd")) | |
725 | "(ca57_cx1|ca57_cx2)") | |
726 | ||
727 | (define_insn_reservation "cortex_a57_fp_cpys" 4 | |
728 | (and (eq_attr "tune" "cortexa57") | |
1db6c46d | 729 | (eq_attr "type" "fmov,fcsel")) |
e0ae0288 JG |
730 | "(ca57_cx1|ca57_cx2)") |
731 | ||
732 | (define_insn_reservation "cortex_a57_fp_divs" 12 | |
733 | (and (eq_attr "tune" "cortexa57") | |
734 | (eq_attr "type" "fdivs, fsqrts,\ | |
735 | neon_fp_div_s, neon_fp_sqrt_s")) | |
736 | "ca57_cx2_block*5") | |
737 | ||
738 | (define_insn_reservation "cortex_a57_fp_divd" 16 | |
739 | (and (eq_attr "tune" "cortexa57") | |
740 | (eq_attr "type" "fdivd, fsqrtd, neon_fp_div_d, neon_fp_sqrt_d")) | |
741 | "ca57_cx2_block*3") | |
742 | ||
743 | (define_insn_reservation "cortex_a57_neon_fp_div_q" 20 | |
744 | (and (eq_attr "tune" "cortexa57") | |
745 | (eq_attr "type" "fdivd, fsqrtd,\ | |
746 | neon_fp_div_s_q, neon_fp_div_d_q,\ | |
747 | neon_fp_sqrt_s_q, neon_fp_sqrt_d_q")) | |
748 | "ca57_cx2_block*3") | |
749 | ||
00a8574a | 750 | (define_insn_reservation "cortex_a57_crypto_simple" 3 |
e0ae0288 | 751 | (and (eq_attr "tune" "cortexa57") |
4c3e13df | 752 | (eq_attr "type" "crypto_aese,crypto_aesmc,crypto_sha1_fast,crypto_sha256_fast")) |
00a8574a | 753 | "ca57_cx1") |
e0ae0288 | 754 | |
00a8574a | 755 | (define_insn_reservation "cortex_a57_crypto_complex" 6 |
e0ae0288 | 756 | (and (eq_attr "tune" "cortexa57") |
4c3e13df | 757 | (eq_attr "type" "crypto_sha1_slow,crypto_sha256_slow")) |
00a8574a | 758 | "ca57_cx1*2") |
e0ae0288 | 759 | |
00a8574a | 760 | (define_insn_reservation "cortex_a57_crypto_xor" 6 |
e0ae0288 JG |
761 | (and (eq_attr "tune" "cortexa57") |
762 | (eq_attr "type" "crypto_sha1_xor")) | |
00a8574a | 763 | "(ca57_cx1*2)|(ca57_cx2*2)") |
e0ae0288 JG |
764 | |
765 | ;; We lie with calls. They take up all issue slots, but are otherwise | |
766 | ;; not harmful. | |
767 | (define_insn_reservation "cortex_a57_call" 1 | |
768 | (and (eq_attr "tune" "cortexa57") | |
769 | (eq_attr "type" "call")) | |
770 | "ca57_sx1_issue+ca57_sx2_issue+ca57_cx1_issue+ca57_cx2_issue\ | |
771 | +ca57_mx_issue+ca57_bx_issue+ca57_ls_issue" | |
772 | ) | |
773 | ||
774 | ;; Simple execution unit bypasses | |
775 | (define_bypass 1 "cortex_a57_alu" | |
776 | "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg") | |
777 | (define_bypass 2 "cortex_a57_alu_shift" | |
778 | "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg") | |
779 | (define_bypass 2 "cortex_a57_alu_shift_reg" | |
780 | "cortex_a57_alu,cortex_a57_alu_shift,cortex_a57_alu_shift_reg") | |
781 | (define_bypass 1 "cortex_a57_alu" "cortex_a57_load1,cortex_a57_load3") | |
782 | (define_bypass 2 "cortex_a57_alu_shift" "cortex_a57_load1,cortex_a57_load3") | |
783 | (define_bypass 2 "cortex_a57_alu_shift_reg" | |
784 | "cortex_a57_load1,cortex_a57_load3") | |
785 | ||
786 | ;; An MLA or a MUL can feed a dependent MLA. | |
787 | (define_bypass 5 "cortex_a57_neon_*mla*,cortex_a57_neon_*mul*" | |
788 | "cortex_a57_neon_*mla*") | |
789 | ||
790 | (define_bypass 5 "cortex_a57_fp_mul,cortex_a57_fp_mac" | |
791 | "cortex_a57_fp_mac") | |
792 | ||
793 | ;; We don't need to care about control hazards, either the branch is | |
794 | ;; predicted in which case we pay no penalty, or the branch is | |
795 | ;; mispredicted in which case instruction scheduling will be unlikely to | |
796 | ;; help. | |
797 | (define_bypass 1 "cortex_a57_*" | |
798 | "cortex_a57_call,cortex_a57_branch") | |
799 | ||
00a8574a WD |
800 | ;; AESE+AESMC and AESD+AESIMC pairs forward with zero latency |
801 | (define_bypass 0 "cortex_a57_crypto_simple" | |
802 | "cortex_a57_crypto_simple" | |
803 | "aarch_crypto_can_dual_issue") | |
804 |