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c956e102 MS |
1 | ;; ARM Cortex-A8 scheduling description. |
2 | ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
3 | ;; Contributed by CodeSourcery. | |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
2f83c7d6 NC |
7 | ;; GCC is free software; you can redistribute it and/or modify it |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
c956e102 MS |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
c956e102 MS |
20 | |
21 | (define_automaton "cortex_a8") | |
22 | ||
23 | ;; Only one load/store instruction can be issued per cycle | |
24 | ;; (although reservation of this unit is only required for single | |
25 | ;; loads and stores -- see below). | |
26 | (define_cpu_unit "cortex_a8_issue_ls" "cortex_a8") | |
27 | ||
28 | ;; Only one branch instruction can be issued per cycle. | |
29 | (define_cpu_unit "cortex_a8_issue_branch" "cortex_a8") | |
30 | ||
31 | ;; The two ALU pipelines. | |
32 | (define_cpu_unit "cortex_a8_alu0" "cortex_a8") | |
33 | (define_cpu_unit "cortex_a8_alu1" "cortex_a8") | |
34 | ||
35 | ;; The usual flow of an instruction through the pipelines. | |
36 | (define_reservation "cortex_a8_default" | |
37 | "cortex_a8_alu0|cortex_a8_alu1") | |
38 | ||
39 | ;; The flow of a branch instruction through the pipelines. | |
40 | (define_reservation "cortex_a8_branch" | |
41 | "(cortex_a8_alu0+cortex_a8_issue_branch)|\ | |
42 | (cortex_a8_alu1+cortex_a8_issue_branch)") | |
43 | ||
44 | ;; The flow of a load or store instruction through the pipeline in | |
45 | ;; the case where that instruction consists of only one micro-op... | |
46 | (define_reservation "cortex_a8_load_store_1" | |
47 | "(cortex_a8_alu0+cortex_a8_issue_ls)|\ | |
48 | (cortex_a8_alu1+cortex_a8_issue_ls)") | |
49 | ||
50 | ;; ...and in the case of two micro-ops. We don't need to reserve | |
51 | ;; cortex_a8_issue_ls here because dual issue is altogether forbidden | |
52 | ;; during the issue cycle of the first micro-op. (Instead of modelling | |
53 | ;; a separate issue unit, we instead reserve alu0 and alu1 to | |
54 | ;; prevent any other instructions from being issued upon that first cycle.) | |
55 | ;; Even though the load/store pipeline is usually available in either | |
56 | ;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This | |
57 | ;; reservation is therefore the same as cortex_a8_multiply_2 below. | |
58 | (define_reservation "cortex_a8_load_store_2" | |
59 | "cortex_a8_alu0+cortex_a8_alu1,\ | |
60 | cortex_a8_alu0") | |
61 | ||
62 | ;; The flow of a single-cycle multiplication. | |
63 | (define_reservation "cortex_a8_multiply" | |
64 | "cortex_a8_alu0") | |
65 | ||
66 | ;; The flow of a multiplication instruction that gets decomposed into | |
67 | ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on | |
68 | ;; successive cycles. Dual issue cannot happen at the same time as the | |
69 | ;; first of the micro-ops. | |
70 | (define_reservation "cortex_a8_multiply_2" | |
71 | "cortex_a8_alu0+cortex_a8_alu1,\ | |
72 | cortex_a8_alu0") | |
73 | ||
74 | ;; Similarly, the flow of a multiplication instruction that gets | |
75 | ;; decomposed into three micro-ops. Dual issue cannot occur except on | |
76 | ;; the cycle upon which the third micro-op is issued. | |
77 | (define_reservation "cortex_a8_multiply_3" | |
78 | "cortex_a8_alu0+cortex_a8_alu1,\ | |
79 | cortex_a8_alu0+cortex_a8_alu1,\ | |
80 | cortex_a8_alu0") | |
81 | ||
82 | ;; The model given here assumes that all instructions are unconditional. | |
83 | ||
84 | ;; Data processing instructions, but not move instructions. | |
85 | ||
86 | ;; We include CLZ with these since it has the same execution pattern | |
87 | ;; (source read in E2 and destination available at the end of that cycle). | |
88 | (define_insn_reservation "cortex_a8_alu" 2 | |
89 | (and (eq_attr "tune" "cortexa8") | |
eab3f92e JZ |
90 | (ior (and (and (eq_attr "type" "alu") |
91 | (eq_attr "neon_type" "none")) | |
92 | (not (eq_attr "insn" "mov,mvn"))) | |
c956e102 MS |
93 | (eq_attr "insn" "clz"))) |
94 | "cortex_a8_default") | |
95 | ||
96 | (define_insn_reservation "cortex_a8_alu_shift" 2 | |
97 | (and (eq_attr "tune" "cortexa8") | |
98 | (and (eq_attr "type" "alu_shift") | |
99 | (not (eq_attr "insn" "mov,mvn")))) | |
100 | "cortex_a8_default") | |
101 | ||
102 | (define_insn_reservation "cortex_a8_alu_shift_reg" 2 | |
103 | (and (eq_attr "tune" "cortexa8") | |
104 | (and (eq_attr "type" "alu_shift_reg") | |
105 | (not (eq_attr "insn" "mov,mvn")))) | |
106 | "cortex_a8_default") | |
107 | ||
108 | ;; Move instructions. | |
109 | ||
110 | (define_insn_reservation "cortex_a8_mov" 1 | |
111 | (and (eq_attr "tune" "cortexa8") | |
112 | (and (eq_attr "type" "alu,alu_shift,alu_shift_reg") | |
113 | (eq_attr "insn" "mov,mvn"))) | |
114 | "cortex_a8_default") | |
115 | ||
116 | ;; Exceptions to the default latencies for data processing instructions. | |
117 | ||
118 | ;; A move followed by an ALU instruction with no early dep. | |
119 | ;; (Such a pair can be issued in parallel, hence latency zero.) | |
120 | (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu") | |
121 | (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift" | |
122 | "arm_no_early_alu_shift_dep") | |
123 | (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift_reg" | |
124 | "arm_no_early_alu_shift_value_dep") | |
125 | ||
126 | ;; An ALU instruction followed by an ALU instruction with no early dep. | |
127 | (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
128 | "cortex_a8_alu") | |
129 | (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
130 | "cortex_a8_alu_shift" | |
131 | "arm_no_early_alu_shift_dep") | |
132 | (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
133 | "cortex_a8_alu_shift_reg" | |
134 | "arm_no_early_alu_shift_value_dep") | |
135 | ||
136 | ;; Multiplication instructions. These are categorized according to their | |
cea618ac | 137 | ;; reservation behavior and the need below to distinguish certain |
c956e102 MS |
138 | ;; varieties for bypasses. Results are available at the E5 stage |
139 | ;; (but some of these are multi-cycle instructions which explains the | |
140 | ;; latencies below). | |
141 | ||
142 | (define_insn_reservation "cortex_a8_mul" 6 | |
143 | (and (eq_attr "tune" "cortexa8") | |
144 | (eq_attr "insn" "mul,smulxy,smmul")) | |
145 | "cortex_a8_multiply_2") | |
146 | ||
147 | (define_insn_reservation "cortex_a8_mla" 6 | |
148 | (and (eq_attr "tune" "cortexa8") | |
149 | (eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd")) | |
150 | "cortex_a8_multiply_2") | |
151 | ||
152 | (define_insn_reservation "cortex_a8_mull" 7 | |
153 | (and (eq_attr "tune" "cortexa8") | |
154 | (eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy")) | |
155 | "cortex_a8_multiply_3") | |
156 | ||
157 | (define_insn_reservation "cortex_a8_smulwy" 5 | |
158 | (and (eq_attr "tune" "cortexa8") | |
159 | (eq_attr "insn" "smulwy,smuad,smusd")) | |
160 | "cortex_a8_multiply") | |
161 | ||
162 | ;; smlald and smlsld are multiply-accumulate instructions but do not | |
163 | ;; received bypassed data from other multiplication results; thus, they | |
164 | ;; cannot go in cortex_a8_mla above. (See below for bypass details.) | |
165 | (define_insn_reservation "cortex_a8_smlald" 6 | |
166 | (and (eq_attr "tune" "cortexa8") | |
167 | (eq_attr "insn" "smlald,smlsld")) | |
168 | "cortex_a8_multiply_2") | |
169 | ||
170 | ;; A multiply with a single-register result or an MLA, followed by an | |
171 | ;; MLA with an accumulator dependency, has its result forwarded so two | |
172 | ;; such instructions can issue back-to-back. | |
173 | (define_bypass 1 "cortex_a8_mul,cortex_a8_mla,cortex_a8_smulwy" | |
174 | "cortex_a8_mla" | |
175 | "arm_mac_accumulator_is_mul_result") | |
176 | ||
177 | ;; A multiply followed by an ALU instruction needing the multiply | |
178 | ;; result only at E2 has lower latency than one needing it at E1. | |
179 | (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
180 | cortex_a8_smulwy,cortex_a8_smlald" | |
181 | "cortex_a8_alu") | |
182 | (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
183 | cortex_a8_smulwy,cortex_a8_smlald" | |
184 | "cortex_a8_alu_shift" | |
185 | "arm_no_early_alu_shift_dep") | |
186 | (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
187 | cortex_a8_smulwy,cortex_a8_smlald" | |
188 | "cortex_a8_alu_shift_reg" | |
189 | "arm_no_early_alu_shift_value_dep") | |
190 | ||
191 | ;; Load instructions. | |
192 | ;; The presence of any register writeback is ignored here. | |
193 | ||
194 | ;; A load result has latency 3 unless the dependent instruction has | |
195 | ;; no early dep, in which case it is only latency two. | |
196 | ;; We assume 64-bit alignment for doubleword loads. | |
197 | (define_insn_reservation "cortex_a8_load1_2" 3 | |
198 | (and (eq_attr "tune" "cortexa8") | |
199 | (eq_attr "type" "load1,load2,load_byte")) | |
200 | "cortex_a8_load_store_1") | |
201 | ||
202 | (define_bypass 2 "cortex_a8_load1_2" | |
203 | "cortex_a8_alu") | |
204 | (define_bypass 2 "cortex_a8_load1_2" | |
205 | "cortex_a8_alu_shift" | |
206 | "arm_no_early_alu_shift_dep") | |
207 | (define_bypass 2 "cortex_a8_load1_2" | |
208 | "cortex_a8_alu_shift_reg" | |
209 | "arm_no_early_alu_shift_value_dep") | |
210 | ||
211 | ;; We do not currently model the fact that loads with scaled register | |
212 | ;; offsets that are not LSL #2 have an extra cycle latency (they issue | |
213 | ;; as two micro-ops). | |
214 | ||
215 | ;; A load multiple of three registers is usually issued as two micro-ops. | |
216 | ;; The first register will be available at E3 of the first iteration, | |
217 | ;; the second at E3 of the second iteration, and the third at E4 of | |
218 | ;; the second iteration. A load multiple of four registers is usually | |
219 | ;; issued as two micro-ops. | |
220 | (define_insn_reservation "cortex_a8_load3_4" 5 | |
221 | (and (eq_attr "tune" "cortexa8") | |
222 | (eq_attr "type" "load3,load4")) | |
223 | "cortex_a8_load_store_2") | |
224 | ||
225 | (define_bypass 4 "cortex_a8_load3_4" | |
226 | "cortex_a8_alu") | |
227 | (define_bypass 4 "cortex_a8_load3_4" | |
228 | "cortex_a8_alu_shift" | |
229 | "arm_no_early_alu_shift_dep") | |
230 | (define_bypass 4 "cortex_a8_load3_4" | |
231 | "cortex_a8_alu_shift_reg" | |
232 | "arm_no_early_alu_shift_value_dep") | |
233 | ||
234 | ;; Store instructions. | |
235 | ;; Writeback is again ignored. | |
236 | ||
237 | (define_insn_reservation "cortex_a8_store1_2" 0 | |
238 | (and (eq_attr "tune" "cortexa8") | |
239 | (eq_attr "type" "store1,store2")) | |
240 | "cortex_a8_load_store_1") | |
241 | ||
242 | (define_insn_reservation "cortex_a8_store3_4" 0 | |
243 | (and (eq_attr "tune" "cortexa8") | |
244 | (eq_attr "type" "store3,store4")) | |
245 | "cortex_a8_load_store_2") | |
246 | ||
247 | ;; An ALU instruction acting as a producer for a store instruction | |
248 | ;; that only uses the result as the value to be stored (as opposed to | |
249 | ;; using it to calculate the address) has latency zero; the store | |
250 | ;; reads the value to be stored at the start of E3 and the ALU insn | |
251 | ;; writes it at the end of E2. Move instructions actually produce the | |
252 | ;; result at the end of E1, but since we don't have delay slots, the | |
cea618ac | 253 | ;; scheduling behavior will be the same. |
c956e102 MS |
254 | (define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\ |
255 | cortex_a8_alu_shift_reg,cortex_a8_mov" | |
256 | "cortex_a8_store1_2,cortex_a8_store3_4" | |
257 | "arm_no_early_store_addr_dep") | |
258 | ||
259 | ;; Branch instructions | |
260 | ||
261 | (define_insn_reservation "cortex_a8_branch" 0 | |
262 | (and (eq_attr "tune" "cortexa8") | |
263 | (eq_attr "type" "branch")) | |
264 | "cortex_a8_branch") | |
265 | ||
266 | ;; Call latencies are not predictable. A semi-arbitrary very large | |
267 | ;; number is used as "positive infinity" so that everything should be | |
268 | ;; finished by the time of return. | |
269 | (define_insn_reservation "cortex_a8_call" 32 | |
270 | (and (eq_attr "tune" "cortexa8") | |
271 | (eq_attr "type" "call")) | |
272 | "cortex_a8_issue_branch") | |
273 | ||
274 | ;; NEON (including VFP) instructions. | |
275 | ||
276 | (include "cortex-a8-neon.md") | |
277 |