]>
Commit | Line | Data |
---|---|---|
46527cc8 | 1 | ;; ARM Cortex-A9 pipeline description |
d652f226 | 2 | ;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. |
46527cc8 RR |
3 | ;; Originally written by CodeSourcery for VFP. |
4 | ;; | |
b0c13111 RR |
5 | ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> |
6 | ;; Integer Pipeline description contributed by ARM Ltd. | |
7 | ;; VFP Pipeline description rewritten and contributed by ARM Ltd. | |
8 | ||
7612f14d PB |
9 | ;; This file is part of GCC. |
10 | ;; | |
11 | ;; GCC is free software; you can redistribute it and/or modify it | |
12 | ;; under the terms of the GNU General Public License as published by | |
13 | ;; the Free Software Foundation; either version 3, or (at your option) | |
14 | ;; any later version. | |
15 | ;; | |
16 | ;; GCC is distributed in the hope that it will be useful, but | |
17 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | ;; General Public License for more details. | |
20 | ;; | |
21 | ;; You should have received a copy of the GNU General Public License | |
22 | ;; along with GCC; see the file COPYING3. If not see | |
23 | ;; <http://www.gnu.org/licenses/>. | |
24 | ||
25 | (define_automaton "cortex_a9") | |
26 | ||
b0c13111 | 27 | ;; The Cortex-A9 core is modelled as a dual issue pipeline that has |
46527cc8 RR |
28 | ;; the following components. |
29 | ;; 1. 1 Load Store Pipeline. | |
30 | ;; 2. P0 / main pipeline for data processing instructions. | |
31 | ;; 3. P1 / Dual pipeline for Data processing instructions. | |
32 | ;; 4. MAC pipeline for multiply as well as multiply | |
33 | ;; and accumulate instructions. | |
b0c13111 RR |
34 | ;; 5. 1 VFP and an optional Neon unit. |
35 | ;; The Load/Store, VFP and Neon issue pipeline are multiplexed. | |
46527cc8 RR |
36 | ;; The P0 / main pipeline and M1 stage of the MAC pipeline are |
37 | ;; multiplexed. | |
38 | ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are | |
39 | ;; multiplexed. | |
b0c13111 | 40 | ;; There are only 4 integer register read ports and hence at any point of |
46527cc8 RR |
41 | ;; time we can't have issue down the E1 and the E2 ports unless |
42 | ;; of course there are bypass paths that get exercised. | |
43 | ;; Both P0 and P1 have 2 stages E1 and E2. | |
44 | ;; Data processing instructions issue to E1 or E2 depending on | |
45 | ;; whether they have an early shift or not. | |
46 | ||
b0c13111 | 47 | (define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9") |
46527cc8 RR |
48 | (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9") |
49 | (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9") | |
50 | (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9") | |
51 | (define_cpu_unit "cortex_a9_mac_m1, cortex_a9_mac_m2" "cortex_a9") | |
52 | (define_cpu_unit "cortex_a9_branch, cortex_a9_issue_branch" "cortex_a9") | |
53 | ||
54 | (define_reservation "cortex_a9_p0_default" "cortex_a9_p0_e2, cortex_a9_p0_wb") | |
55 | (define_reservation "cortex_a9_p1_default" "cortex_a9_p1_e2, cortex_a9_p1_wb") | |
56 | (define_reservation "cortex_a9_p0_shift" "cortex_a9_p0_e1, cortex_a9_p0_default") | |
57 | (define_reservation "cortex_a9_p1_shift" "cortex_a9_p1_e1, cortex_a9_p1_default") | |
58 | ||
59 | (define_reservation "cortex_a9_multcycle1" | |
60 | "cortex_a9_p0_e2 + cortex_a9_mac_m1 + cortex_a9_mac_m2 + \ | |
61 | cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") | |
62 | ||
63 | (define_reservation "cortex_a9_mult16" | |
64 | "cortex_a9_mac_m1, cortex_a9_mac_m2, cortex_a9_p0_wb") | |
65 | (define_reservation "cortex_a9_mac16" | |
66 | "cortex_a9_multcycle1, cortex_a9_mac_m2, cortex_a9_p0_wb") | |
67 | (define_reservation "cortex_a9_mult" | |
68 | "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb") | |
69 | (define_reservation "cortex_a9_mac" | |
70 | "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb") | |
71 | ||
72 | ||
73 | ;; Issue at the same time along the load store pipeline and | |
74 | ;; the VFP / Neon pipeline is not possible. | |
b0c13111 | 75 | (exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon") |
46527cc8 RR |
76 | |
77 | ;; Default data processing instruction without any shift | |
78 | ;; The only exception to this is the mov instruction | |
79 | ;; which can go down E2 without any problem. | |
80 | (define_insn_reservation "cortex_a9_dp" 2 | |
81 | (and (eq_attr "tune" "cortexa9") | |
82 | (ior (eq_attr "type" "alu") | |
a8c171c1 RR |
83 | (ior (and (eq_attr "type" "alu_shift_reg, alu_shift") |
84 | (eq_attr "insn" "mov")) | |
85 | (eq_attr "neon_type" "none")))) | |
46527cc8 RR |
86 | "cortex_a9_p0_default|cortex_a9_p1_default") |
87 | ||
88 | ;; An instruction using the shifter will go down E1. | |
89 | (define_insn_reservation "cortex_a9_dp_shift" 3 | |
90 | (and (eq_attr "tune" "cortexa9") | |
91 | (and (eq_attr "type" "alu_shift_reg, alu_shift") | |
92 | (not (eq_attr "insn" "mov")))) | |
93 | "cortex_a9_p0_shift | cortex_a9_p1_shift") | |
94 | ||
95 | ;; Loads have a latency of 4 cycles. | |
96 | ;; We don't model autoincrement instructions. These | |
97 | ;; instructions use the load store pipeline and 1 of | |
98 | ;; the E2 units to write back the result of the increment. | |
99 | ||
100 | (define_insn_reservation "cortex_a9_load1_2" 4 | |
101 | (and (eq_attr "tune" "cortexa9") | |
b0c13111 | 102 | (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd")) |
46527cc8 RR |
103 | "cortex_a9_ls") |
104 | ||
105 | ;; Loads multiples and store multiples can't be issued for 2 cycles in a | |
106 | ;; row. The description below assumes that addresses are 64 bit aligned. | |
107 | ;; If not, there is an extra cycle latency which is not modelled. | |
108 | ||
46527cc8 RR |
109 | (define_insn_reservation "cortex_a9_load3_4" 5 |
110 | (and (eq_attr "tune" "cortexa9") | |
111 | (eq_attr "type" "load3, load4")) | |
112 | "cortex_a9_ls, cortex_a9_ls") | |
113 | ||
114 | (define_insn_reservation "cortex_a9_store1_2" 0 | |
115 | (and (eq_attr "tune" "cortexa9") | |
b0c13111 | 116 | (eq_attr "type" "store1, store2, f_stores, f_stored")) |
46527cc8 RR |
117 | "cortex_a9_ls") |
118 | ||
119 | ;; Almost all our store multiples use an auto-increment | |
120 | ;; form. Don't issue back to back load and store multiples | |
121 | ;; because the load store unit will stall. | |
b0c13111 | 122 | |
46527cc8 RR |
123 | (define_insn_reservation "cortex_a9_store3_4" 0 |
124 | (and (eq_attr "tune" "cortexa9") | |
125 | (eq_attr "type" "store3, store4")) | |
126 | "cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls") | |
127 | ||
128 | ;; We get 16*16 multiply / mac results in 3 cycles. | |
129 | (define_insn_reservation "cortex_a9_mult16" 3 | |
130 | (and (eq_attr "tune" "cortexa9") | |
131 | (eq_attr "insn" "smulxy")) | |
132 | "cortex_a9_mult16") | |
133 | ||
134 | ;; The 16*16 mac is slightly different that it | |
135 | ;; reserves M1 and M2 in the same cycle. | |
136 | (define_insn_reservation "cortex_a9_mac16" 3 | |
137 | (and (eq_attr "tune" "cortexa9") | |
138 | (eq_attr "insn" "smlaxy")) | |
139 | "cortex_a9_mac16") | |
140 | ||
141 | ||
142 | (define_insn_reservation "cortex_a9_multiply" 4 | |
143 | (and (eq_attr "tune" "cortexa9") | |
144 | (eq_attr "insn" "mul")) | |
145 | "cortex_a9_mult") | |
146 | ||
147 | (define_insn_reservation "cortex_a9_mac" 4 | |
148 | (and (eq_attr "tune" "cortexa9") | |
149 | (eq_attr "insn" "mla")) | |
150 | "cortex_a9_mac") | |
151 | ||
152 | ;; An instruction with a result in E2 can be forwarded | |
153 | ;; to E2 or E1 or M1 or the load store unit in the next cycle. | |
154 | ||
155 | (define_bypass 1 "cortex_a9_dp" | |
156 | "cortex_a9_dp_shift, cortex_a9_multiply, | |
157 | cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2, | |
158 | cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4") | |
159 | ||
160 | (define_bypass 2 "cortex_a9_dp_shift" | |
161 | "cortex_a9_dp_shift, cortex_a9_multiply, | |
162 | cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2, | |
163 | cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4") | |
164 | ||
165 | ;; An instruction in the load store pipeline can provide | |
166 | ;; read access to a DP instruction in the P0 default pipeline | |
167 | ;; before the writeback stage. | |
168 | ||
169 | (define_bypass 3 "cortex_a9_load1_2" "cortex_a9_dp, cortex_a9_load1_2, | |
170 | cortex_a9_store3_4, cortex_a9_store1_2") | |
171 | ||
172 | (define_bypass 4 "cortex_a9_load3_4" "cortex_a9_dp, cortex_a9_load1_2, | |
173 | cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") | |
174 | ||
175 | ;; Calls and branches. | |
176 | ||
177 | ;; Branch instructions | |
178 | ||
179 | (define_insn_reservation "cortex_a9_branch" 0 | |
180 | (and (eq_attr "tune" "cortexa9") | |
181 | (eq_attr "type" "branch")) | |
182 | "cortex_a9_branch") | |
183 | ||
184 | ;; Call latencies are essentially 0 but make sure | |
185 | ;; dual issue doesn't happen i.e the next instruction | |
186 | ;; starts at the next cycle. | |
187 | (define_insn_reservation "cortex_a9_call" 0 | |
188 | (and (eq_attr "tune" "cortexa9") | |
189 | (eq_attr "type" "call")) | |
b0c13111 | 190 | "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon") |
46527cc8 RR |
191 | |
192 | ||
193 | ;; Pipelining for VFP instructions. | |
b0c13111 RR |
194 | ;; Issue happens either along load store unit or the VFP / Neon unit. |
195 | ;; Pipeline Instruction Classification. | |
196 | ;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r | |
197 | ;; FP_ADD - fadds, faddd, fcmps (1) | |
198 | ;; FPMUL - fmul{s,d}, fmac{s,d} | |
199 | ;; FPDIV - fdiv{s,d} | |
200 | (define_cpu_unit "ca9fps" "cortex_a9") | |
201 | (define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9") | |
202 | (define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9") | |
203 | (define_cpu_unit "ca9fp_ds1" "cortex_a9") | |
204 | ||
205 | ||
206 | ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. | |
207 | (define_insn_reservation "cortex_a9_fps" 2 | |
7612f14d | 208 | (and (eq_attr "tune" "cortexa9") |
b0c13111 RR |
209 | (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag")) |
210 | "ca9_issue_vfp_neon + ca9fps") | |
211 | ||
212 | (define_bypass 1 | |
213 | "cortex_a9_fps" | |
214 | "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply") | |
215 | ||
216 | ;; Scheduling on the FP_ADD pipeline. | |
217 | (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4") | |
7612f14d PB |
218 | |
219 | (define_insn_reservation "cortex_a9_fadd" 4 | |
b0c13111 RR |
220 | (and (eq_attr "tune" "cortexa9") |
221 | (eq_attr "type" "fadds, faddd, f_cvt")) | |
222 | "ca9fp_add") | |
7612f14d | 223 | |
b0c13111 RR |
224 | (define_insn_reservation "cortex_a9_fcmp" 1 |
225 | (and (eq_attr "tune" "cortexa9") | |
226 | (eq_attr "type" "fcmps, fcmpd")) | |
227 | "ca9_issue_vfp_neon + ca9fp_add1") | |
7612f14d | 228 | |
b0c13111 RR |
229 | ;; Scheduling for the Multiply and MAC instructions. |
230 | (define_reservation "ca9fmuls" | |
231 | "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") | |
232 | ||
233 | (define_reservation "ca9fmuld" | |
234 | "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") | |
235 | ||
236 | (define_insn_reservation "cortex_a9_fmuls" 4 | |
237 | (and (eq_attr "tune" "cortexa9") | |
238 | (eq_attr "type" "fmuls")) | |
239 | "ca9fmuls") | |
240 | ||
241 | (define_insn_reservation "cortex_a9_fmuld" 5 | |
242 | (and (eq_attr "tune" "cortexa9") | |
243 | (eq_attr "type" "fmuld")) | |
244 | "ca9fmuld") | |
7612f14d PB |
245 | |
246 | (define_insn_reservation "cortex_a9_fmacs" 8 | |
b0c13111 RR |
247 | (and (eq_attr "tune" "cortexa9") |
248 | (eq_attr "type" "fmacs")) | |
249 | "ca9fmuls, ca9fp_add") | |
7612f14d | 250 | |
b0c13111 RR |
251 | (define_insn_reservation "cortex_a9_fmacd" 9 |
252 | (and (eq_attr "tune" "cortexa9") | |
253 | (eq_attr "type" "fmacd")) | |
254 | "ca9fmuld, ca9fp_add") | |
7612f14d | 255 | |
b0c13111 | 256 | ;; Division pipeline description. |
7612f14d | 257 | (define_insn_reservation "cortex_a9_fdivs" 15 |
b0c13111 RR |
258 | (and (eq_attr "tune" "cortexa9") |
259 | (eq_attr "type" "fdivs")) | |
260 | "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14") | |
7612f14d PB |
261 | |
262 | (define_insn_reservation "cortex_a9_fdivd" 25 | |
b0c13111 RR |
263 | (and (eq_attr "tune" "cortexa9") |
264 | (eq_attr "type" "fdivd")) | |
265 | "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") |