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47d8f18d | 1 | ;; ARM Cortex-M4 pipeline description |
d1e082c2 | 2 | ;; Copyright (C) 2010-2013 Free Software Foundation, Inc. |
47d8f18d JZ |
3 | ;; Contributed by CodeSourcery. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | (define_automaton "cortex_m4") | |
22 | ||
23 | ;; We model the pipelining of LDR instructions by using two artificial units. | |
24 | ||
25 | (define_cpu_unit "cortex_m4_a" "cortex_m4") | |
26 | ||
27 | (define_cpu_unit "cortex_m4_b" "cortex_m4") | |
28 | ||
29 | (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b") | |
30 | ||
31 | ;; ALU and multiply is one cycle. | |
32 | (define_insn_reservation "cortex_m4_alu" 1 | |
33 | (and (eq_attr "tune" "cortexm4") | |
006bd006 | 34 | (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\ |
859abddd SN |
35 | arlo_shift,arlo_shift_reg,\ |
36 | mov_imm,mov_reg,mov_shift,mov_shift_reg,\ | |
37 | mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg") | |
09485a08 SN |
38 | (ior (eq_attr "mul32" "yes") |
39 | (eq_attr "mul64" "yes")))) | |
47d8f18d JZ |
40 | "cortex_m4_ex") |
41 | ||
42 | ;; Byte, half-word and word load is two cycles. | |
43 | (define_insn_reservation "cortex_m4_load1" 2 | |
44 | (and (eq_attr "tune" "cortexm4") | |
45 | (eq_attr "type" "load_byte,load1")) | |
46 | "cortex_m4_a, cortex_m4_b") | |
47 | ||
48 | ;; str rx, [ry, #imm] is always one cycle. | |
49 | (define_insn_reservation "cortex_m4_store1_1" 1 | |
50 | (and (and (eq_attr "tune" "cortexm4") | |
51 | (eq_attr "type" "store1")) | |
b75b1be2 | 52 | (match_test "arm_address_offset_is_imm (insn)")) |
47d8f18d JZ |
53 | "cortex_m4_a") |
54 | ||
55 | ;; Other byte, half-word and word load is two cycles. | |
56 | (define_insn_reservation "cortex_m4_store1_2" 2 | |
57 | (and (and (eq_attr "tune" "cortexm4") | |
58 | (eq_attr "type" "store1")) | |
b75b1be2 | 59 | (not (match_test "arm_address_offset_is_imm (insn)"))) |
47d8f18d JZ |
60 | "cortex_m4_a*2") |
61 | ||
62 | (define_insn_reservation "cortex_m4_load2" 3 | |
63 | (and (eq_attr "tune" "cortexm4") | |
64 | (eq_attr "type" "load2")) | |
65 | "cortex_m4_ex*3") | |
66 | ||
67 | (define_insn_reservation "cortex_m4_store2" 3 | |
68 | (and (eq_attr "tune" "cortexm4") | |
69 | (eq_attr "type" "store2")) | |
70 | "cortex_m4_ex*3") | |
71 | ||
72 | (define_insn_reservation "cortex_m4_load3" 4 | |
73 | (and (eq_attr "tune" "cortexm4") | |
74 | (eq_attr "type" "load3")) | |
75 | "cortex_m4_ex*4") | |
76 | ||
77 | (define_insn_reservation "cortex_m4_store3" 4 | |
78 | (and (eq_attr "tune" "cortexm4") | |
79 | (eq_attr "type" "store3")) | |
80 | "cortex_m4_ex*4") | |
81 | ||
82 | (define_insn_reservation "cortex_m4_load4" 5 | |
83 | (and (eq_attr "tune" "cortexm4") | |
84 | (eq_attr "type" "load4")) | |
85 | "cortex_m4_ex*5") | |
86 | ||
87 | (define_insn_reservation "cortex_m4_store4" 5 | |
88 | (and (eq_attr "tune" "cortexm4") | |
89 | (eq_attr "type" "store4")) | |
90 | "cortex_m4_ex*5") | |
91 | ||
10a88311 TG |
92 | (define_bypass 1 "cortex_m4_load1" |
93 | "cortex_m4_store1_1,cortex_m4_store1_2" | |
94 | "arm_no_early_store_addr_dep") | |
95 | ||
47d8f18d JZ |
96 | ;; If the address of load or store depends on the result of the preceding |
97 | ;; instruction, the latency is increased by one. | |
98 | ||
99 | (define_bypass 2 "cortex_m4_alu" | |
100 | "cortex_m4_load1" | |
101 | "arm_early_load_addr_dep") | |
102 | ||
103 | (define_bypass 2 "cortex_m4_alu" | |
104 | "cortex_m4_store1_1,cortex_m4_store1_2" | |
105 | "arm_early_store_addr_dep") | |
106 | ||
107 | (define_insn_reservation "cortex_m4_branch" 3 | |
108 | (and (eq_attr "tune" "cortexm4") | |
109 | (eq_attr "type" "branch")) | |
110 | "cortex_m4_ex*3") | |
111 | ||
112 | (define_insn_reservation "cortex_m4_call" 3 | |
113 | (and (eq_attr "tune" "cortexm4") | |
114 | (eq_attr "type" "call")) | |
115 | "cortex_m4_ex*3") | |
116 | ||
117 | (define_insn_reservation "cortex_m4_block" 1 | |
118 | (and (eq_attr "tune" "cortexm4") | |
119 | (eq_attr "type" "block")) | |
120 | "cortex_m4_ex") |