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c02a5ccb | 1 | ;; Faraday FA526 Pipeline Description |
a945c346 | 2 | ;; Copyright (C) 2010-2024 Free Software Foundation, Inc. |
c02a5ccb SL |
3 | ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it under | |
8 | ;; the terms of the GNU General Public License as published by the Free | |
9 | ;; Software Foundation; either version 3, or (at your option) any later | |
10 | ;; version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | ;; for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ;; These descriptions are based on the information contained in the | |
22 | ;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp. | |
23 | ;; | |
24 | ;; Modeled pipeline characteristics: | |
25 | ;; LD -> any use: latency = 3 (2 cycle penalty). | |
26 | ;; ALU -> any use: latency = 2 (1 cycle penalty). | |
27 | ||
28 | ;; This automaton provides a pipeline description for the Faraday | |
29 | ;; FA526 core. | |
30 | ;; | |
31 | ;; The model given here assumes that the condition for all conditional | |
32 | ;; instructions is "true", i.e., that all of the instructions are | |
33 | ;; actually executed. | |
34 | ||
35 | (define_automaton "fa526") | |
36 | ||
37 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
38 | ;; Pipelines | |
39 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
40 | ||
41 | ;; There is a single pipeline | |
42 | ;; | |
43 | ;; The ALU pipeline has fetch, decode, execute, memory, and | |
44 | ;; write stages. We only need to model the execute, memory and write | |
45 | ;; stages. | |
46 | ||
47 | ;; S E M W | |
48 | ||
49 | (define_cpu_unit "fa526_core" "fa526") | |
50 | ||
51 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
52 | ;; ALU Instructions | |
53 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
54 | ||
55 | ;; ALU instructions require two cycles to execute, and use the ALU | |
56 | ;; pipeline in each of the three stages. The results are available | |
026c3cfd | 57 | ;; after the execute stage has finished. |
c02a5ccb SL |
58 | ;; |
59 | ;; If the destination register is the PC, the pipelines are stalled | |
60 | ;; for several cycles. That case is not modeled here. | |
61 | ||
62 | ;; ALU operations | |
63 | (define_insn_reservation "526_alu_op" 1 | |
64 | (and (eq_attr "tune" "fa526") | |
6e4150e1 | 65 | (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ |
1d61feeb | 66 | alu_sreg,alus_sreg,logic_reg,logics_reg,\ |
6e4150e1 JG |
67 | adc_imm,adcs_imm,adc_reg,adcs_reg,\ |
68 | adr,bfm,rev,\ | |
69 | shift_imm,shift_reg,\ | |
594726e4 | 70 | mov_imm,mov_reg,mvn_imm,mvn_reg,\ |
f62281dc | 71 | mrs,multiple")) |
c02a5ccb SL |
72 | "fa526_core") |
73 | ||
74 | (define_insn_reservation "526_alu_shift_op" 2 | |
75 | (and (eq_attr "tune" "fa526") | |
6e4150e1 | 76 | (eq_attr "type" "extend,\ |
ae27ce51 | 77 | alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ |
6e4150e1 JG |
78 | logic_shift_imm,logics_shift_imm,\ |
79 | alu_shift_reg,alus_shift_reg,\ | |
80 | logic_shift_reg,logics_shift_reg,\ | |
859abddd SN |
81 | mov_shift,mov_shift_reg,\ |
82 | mvn_shift,mvn_shift_reg")) | |
c02a5ccb SL |
83 | "fa526_core") |
84 | ||
85 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
86 | ;; Multiplication Instructions | |
87 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
88 | ||
89 | (define_insn_reservation "526_mult1" 2 | |
90 | (and (eq_attr "tune" "fa526") | |
09485a08 | 91 | (eq_attr "type" "smlalxy,smulxy,smlaxy,smlalxy")) |
c02a5ccb SL |
92 | "fa526_core") |
93 | ||
94 | (define_insn_reservation "526_mult2" 5 | |
95 | (and (eq_attr "tune" "fa526") | |
09485a08 | 96 | (eq_attr "type" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ |
c02a5ccb SL |
97 | umlals,smulls,smlals,smlawx")) |
98 | "fa526_core*4") | |
99 | ||
100 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
101 | ;; Load/Store Instructions | |
102 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
103 | ||
104 | ;; The models for load/store instructions do not accurately describe | |
105 | ;; the difference between operations with a base register writeback | |
106 | ;; (such as "ldm!"). These models assume that all memory references | |
107 | ;; hit in dcache. | |
108 | ||
109 | (define_insn_reservation "526_load1_op" 3 | |
110 | (and (eq_attr "tune" "fa526") | |
89b2133e | 111 | (eq_attr "type" "load_4,load_byte")) |
c02a5ccb SL |
112 | "fa526_core") |
113 | ||
114 | (define_insn_reservation "526_load2_op" 4 | |
115 | (and (eq_attr "tune" "fa526") | |
89b2133e | 116 | (eq_attr "type" "load_8")) |
c02a5ccb SL |
117 | "fa526_core*2") |
118 | ||
119 | (define_insn_reservation "526_load3_op" 5 | |
120 | (and (eq_attr "tune" "fa526") | |
89b2133e | 121 | (eq_attr "type" "load_12")) |
c02a5ccb SL |
122 | "fa526_core*3") |
123 | ||
124 | (define_insn_reservation "526_load4_op" 6 | |
125 | (and (eq_attr "tune" "fa526") | |
89b2133e | 126 | (eq_attr "type" "load_16")) |
c02a5ccb SL |
127 | "fa526_core*4") |
128 | ||
129 | (define_insn_reservation "526_store1_op" 0 | |
130 | (and (eq_attr "tune" "fa526") | |
89b2133e | 131 | (eq_attr "type" "store_4")) |
c02a5ccb SL |
132 | "fa526_core") |
133 | ||
134 | (define_insn_reservation "526_store2_op" 1 | |
135 | (and (eq_attr "tune" "fa526") | |
89b2133e | 136 | (eq_attr "type" "store_8")) |
c02a5ccb SL |
137 | "fa526_core*2") |
138 | ||
139 | (define_insn_reservation "526_store3_op" 2 | |
140 | (and (eq_attr "tune" "fa526") | |
89b2133e | 141 | (eq_attr "type" "store_12")) |
c02a5ccb SL |
142 | "fa526_core*3") |
143 | ||
144 | (define_insn_reservation "526_store4_op" 3 | |
145 | (and (eq_attr "tune" "fa526") | |
89b2133e | 146 | (eq_attr "type" "store_16")) |
c02a5ccb SL |
147 | "fa526_core*4") |
148 | ||
149 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
150 | ;; Branch and Call Instructions | |
151 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
152 | ||
153 | ;; Branch instructions are difficult to model accurately. The FA526 | |
154 | ;; core can predict most branches. If the branch is predicted | |
155 | ;; correctly, and predicted early enough, the branch can be completely | |
156 | ;; eliminated from the instruction stream. Some branches can | |
157 | ;; therefore appear to require zero cycle to execute. We assume that | |
158 | ;; all branches are predicted correctly, and that the latency is | |
159 | ;; therefore the minimum value. | |
160 | ||
161 | (define_insn_reservation "526_branch_op" 0 | |
162 | (and (eq_attr "tune" "fa526") | |
163 | (eq_attr "type" "branch")) | |
164 | "fa526_core") | |
165 | ||
166 | ;; The latency for a call is actually the latency when the result is available. | |
167 | ;; i.e. R0 ready for int return value. For most cases, the return value is set | |
168 | ;; by a mov instruction, which has 1 cycle latency. | |
169 | (define_insn_reservation "526_call_op" 1 | |
170 | (and (eq_attr "tune" "fa526") | |
171 | (eq_attr "type" "call")) | |
172 | "fa526_core") | |
173 |