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1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
2 | ;; Copyright (C) 2010 Free Software Foundation, Inc. | |
3 | ;; Contributed by ARM Ltd. | |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;;---------------------------------------------------------------------------- | |
23 | ;; Mode iterators | |
24 | ;;---------------------------------------------------------------------------- | |
25 | ||
26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
27 | ;; some splits that are the same for all modes when operating on ARM | |
28 | ;; registers. | |
29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) | |
30 | ||
31 | ;; A list of integer modes that are up to one word long | |
32 | (define_mode_iterator QHSI [QI HI SI]) | |
33 | ||
34 | ;; Integer element sizes implemented by IWMMXT. | |
35 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
36 | ||
37 | ;; Integer element sizes for shifts. | |
38 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
39 | ||
40 | ;; Integer and float modes supported by Neon and IWMMXT. | |
41 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
42 | ||
43 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
44 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
45 | ||
46 | ;; Integer modes supported by Neon and IWMMXT | |
47 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
48 | ||
49 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
50 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
51 | ||
52 | ;; Double-width vector modes. | |
53 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | |
54 | ||
55 | ;; Double-width vector modes plus 64-bit elements. | |
56 | (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) | |
57 | ||
58 | ;; Double-width vector modes without floating-point elements. | |
59 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
60 | ||
61 | ;; Quad-width vector modes. | |
62 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) | |
63 | ||
64 | ;; Quad-width vector modes plus 64-bit elements. | |
65 | (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) | |
66 | ||
67 | ;; Quad-width vector modes without floating-point elements. | |
68 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
69 | ||
70 | ;; Quad-width vector modes, with TImode added, for moves. | |
71 | (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) | |
72 | ||
73 | ;; Opaque structure types wider than TImode. | |
74 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
75 | ||
76 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
77 | (define_mode_iterator VTAB [TI EI OI]) | |
78 | ||
79 | ;; Widenable modes. | |
80 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
81 | ||
82 | ;; Narrowable modes. | |
83 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
84 | ||
85 | ;; All supported vector modes (except singleton DImode). | |
86 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) | |
87 | ||
88 | ;; All supported vector modes (except those with 64-bit integer elements). | |
89 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
90 | ||
91 | ;; Supported integer vector modes (not 64 bit elements). | |
92 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
93 | ||
94 | ;; Supported integer vector modes (not singleton DI) | |
95 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
96 | ||
97 | ;; Vector modes, including 64-bit integer elements. | |
98 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) | |
99 | ||
100 | ;; Vector modes including 64-bit integer elements, but no floats. | |
101 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
102 | ||
103 | ;; Vector modes for float->int conversions. | |
104 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
105 | ||
106 | ;; Vector modes form int->float conversions. | |
107 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
108 | ||
109 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. | |
110 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
111 | ||
112 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
113 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
114 | ||
115 | ;; Above modes combined. | |
116 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
117 | ||
118 | ;; As VMD, but integer modes only. | |
119 | (define_mode_iterator VMDI [V4HI V2SI]) | |
120 | ||
121 | ;; As VMQ, but integer modes only. | |
122 | (define_mode_iterator VMQI [V8HI V4SI]) | |
123 | ||
124 | ;; Above modes combined. | |
125 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
126 | ||
127 | ;; Modes with 8-bit and 16-bit elements. | |
128 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
129 | ||
130 | ;; Modes with 8-bit elements. | |
131 | (define_mode_iterator VE [V8QI V16QI]) | |
132 | ||
133 | ;; Modes with 64-bit elements only. | |
134 | (define_mode_iterator V64 [DI V2DI]) | |
135 | ||
136 | ;; Modes with 32-bit elements only. | |
137 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
138 | ||
46b57af1 TB |
139 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
140 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
141 | ||
ceddf62c SN |
142 | ;;---------------------------------------------------------------------------- |
143 | ;; Code iterators | |
144 | ;;---------------------------------------------------------------------------- | |
145 | ||
146 | ;; A list of condition codes used in compare instructions where | |
147 | ;; the carry flag from the addition is used instead of doing the | |
148 | ;; compare a second time. | |
149 | (define_code_iterator LTUGEU [ltu geu]) | |
150 | ||
151 | ;; A list of ... | |
152 | (define_code_iterator ior_xor [ior xor]) | |
153 | ||
154 | ;; Operations on two halves of a quadword vector. | |
155 | (define_code_iterator vqh_ops [plus smin smax umin umax]) | |
156 | ||
157 | ;; Operations on two halves of a quadword vector, | |
158 | ;; without unsigned variants (for use with *SFmode pattern). | |
159 | (define_code_iterator vqhs_ops [plus smin smax]) | |
160 | ||
46b57af1 TB |
161 | ;; A list of widening operators |
162 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c SN |
163 | |
164 | ;;---------------------------------------------------------------------------- | |
165 | ;; Mode attributes | |
166 | ;;---------------------------------------------------------------------------- | |
167 | ||
168 | ;; Determine element size suffix from vector mode. | |
169 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
170 | ||
171 | ;; vtbl<n> suffix for NEON vector modes. | |
172 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
173 | ||
174 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
175 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
176 | (V4SI "V4SF") (V4SF "V4SI")]) | |
177 | ||
178 | ;; Define element mode for each vector mode. | |
179 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
180 | (V4HI "HI") (V8HI "HI") | |
181 | (V2SI "SI") (V4SI "SI") | |
182 | (V2SF "SF") (V4SF "SF") | |
183 | (DI "DI") (V2DI "DI")]) | |
184 | ||
185 | ;; Element modes for vector extraction, padded up to register size. | |
186 | ||
187 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
188 | (V4HI "SI") (V8HI "SI") | |
189 | (V2SI "SI") (V4SI "SI") | |
190 | (V2SF "SF") (V4SF "SF") | |
191 | (DI "DI") (V2DI "DI")]) | |
192 | ||
193 | ;; Mode of pair of elements for each vector mode, to define transfer | |
194 | ;; size for structure lane/dup loads and stores. | |
195 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") | |
196 | (V4HI "SI") (V8HI "SI") | |
197 | (V2SI "V2SI") (V4SI "V2SI") | |
198 | (V2SF "V2SF") (V4SF "V2SF") | |
199 | (DI "V2DI") (V2DI "V2DI")]) | |
200 | ||
201 | ;; Similar, for three elements. | |
202 | ;; ??? Should we define extra modes so that sizes of all three-element | |
203 | ;; accesses can be accurately represented? | |
204 | (define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") | |
205 | (V4HI "V4HI") (V8HI "V4HI") | |
206 | (V2SI "V4SI") (V4SI "V4SI") | |
207 | (V2SF "V4SF") (V4SF "V4SF") | |
208 | (DI "EI") (V2DI "EI")]) | |
209 | ||
210 | ;; Similar, for four elements. | |
211 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
212 | (V4HI "V4HI") (V8HI "V4HI") | |
213 | (V2SI "V4SI") (V4SI "V4SI") | |
214 | (V2SF "V4SF") (V4SF "V4SF") | |
215 | (DI "OI") (V2DI "OI")]) | |
216 | ||
217 | ;; Register width from element mode | |
218 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
219 | (V4HI "P") (V8HI "q") | |
220 | (V2SI "P") (V4SI "q") | |
221 | (V2SF "P") (V4SF "q") | |
222 | (DI "P") (V2DI "q")]) | |
223 | ||
224 | ;; Wider modes with the same number of elements. | |
225 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
226 | ||
227 | ;; Narrower modes with the same number of elements. | |
228 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
229 | ||
230 | ;; Modes with half the number of equal-sized elements. | |
231 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
232 | (V4SI "V2SI") (V4SF "V2SF") | |
233 | (V2DI "DI")]) | |
234 | ||
235 | ;; Same, but lower-case. | |
236 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
237 | (V4SI "v2si") (V4SF "v2sf") | |
238 | (V2DI "di")]) | |
239 | ||
240 | ;; Modes with twice the number of equal-sized elements. | |
241 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
242 | (V2SI "V4SI") (V2SF "V4SF") | |
243 | (DI "V2DI")]) | |
244 | ||
245 | ;; Same, but lower-case. | |
246 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
247 | (V2SI "v4si") (V2SF "v4sf") | |
248 | (DI "v2di")]) | |
249 | ||
250 | ;; Modes with double-width elements. | |
251 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
252 | (V4HI "V2SI") (V8HI "V4SI") | |
253 | (V2SI "DI") (V4SI "V2DI")]) | |
254 | ||
255 | ;; Double-sized modes with the same element size. | |
256 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
257 | ;; even when the first one is quad. | |
258 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
259 | (V4SI "V2SI") (V4SF "V2SF") | |
260 | (V8QI "V8QI") (V4HI "V4HI") | |
261 | (V2SI "V2SI") (V2SF "V2SF")]) | |
262 | ||
263 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
264 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
265 | (V4HI "V4HI") (V8HI "V8HI") | |
266 | (V2SI "V2SI") (V4SI "V4SI") | |
267 | (V2SF "V2SI") (V4SF "V4SI") | |
268 | (DI "DI") (V2DI "V2DI")]) | |
269 | ||
270 | ;; Get element type from double-width mode, for operations where we | |
271 | ;; don't care about signedness. | |
272 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
273 | (V4HI "i16") (V8HI "i16") | |
274 | (V2SI "i32") (V4SI "i32") | |
275 | (DI "i64") (V2DI "i64") | |
276 | (V2SF "f32") (V4SF "f32")]) | |
277 | ||
278 | ;; Same, but for operations which work on signed values. | |
279 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
280 | (V4HI "s16") (V8HI "s16") | |
281 | (V2SI "s32") (V4SI "s32") | |
282 | (DI "s64") (V2DI "s64") | |
283 | (V2SF "f32") (V4SF "f32")]) | |
284 | ||
285 | ;; Same, but for operations which work on unsigned values. | |
286 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
287 | (V4HI "u16") (V8HI "u16") | |
288 | (V2SI "u32") (V4SI "u32") | |
289 | (DI "u64") (V2DI "u64") | |
290 | (V2SF "f32") (V4SF "f32")]) | |
291 | ||
292 | ;; Element types for extraction of unsigned scalars. | |
293 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
294 | (V4HI "u16") (V8HI "u16") | |
295 | (V2SI "32") (V4SI "32") | |
296 | (V2SF "32") (V4SF "32")]) | |
297 | ||
298 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
299 | (V4HI "16") (V8HI "16") | |
300 | (V2SI "32") (V4SI "32") | |
301 | (DI "64") (V2DI "64") | |
302 | (V2SF "32") (V4SF "32")]) | |
303 | ||
304 | ;; Element sizes for duplicating ARM registers to all elements of a vector. | |
305 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
306 | ||
307 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
308 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
309 | (V4HI "TI") (V8HI "OI") | |
310 | (V2SI "TI") (V4SI "OI") | |
311 | (V2SF "TI") (V4SF "OI") | |
312 | (DI "TI") (V2DI "OI")]) | |
313 | ||
314 | ;; Same, but lower-case. | |
315 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
316 | (V4HI "ti") (V8HI "oi") | |
317 | (V2SI "ti") (V4SI "oi") | |
318 | (V2SF "ti") (V4SF "oi") | |
319 | (DI "ti") (V2DI "oi")]) | |
320 | ||
321 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
322 | ;; names which we don't want to define). | |
323 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
324 | (V4HI "") (V8HI "") | |
325 | (V2SI "") (V4SI "") | |
326 | (V2SF "") (V4SF "") | |
327 | (DI "_neon") (V2DI "")]) | |
328 | ||
329 | ||
330 | ;; Scalars to be presented to scalar multiplication instructions | |
331 | ;; must satisfy the following constraints. | |
332 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
333 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
334 | ||
335 | ;; This mode attribute is used to obtain the correct register constraints. | |
336 | ||
337 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
338 | (V8HI "x") (V4SI "t") (V4SF "t")]) | |
339 | ||
340 | ;; Predicates used for setting neon_type | |
341 | ||
342 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
343 | (V4HI "false") (V8HI "false") | |
344 | (V2SI "false") (V4SI "false") | |
345 | (V2SF "true") (V4SF "true") | |
346 | (DI "false") (V2DI "false")]) | |
347 | ||
348 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
349 | (V4HI "true") (V8HI "true") | |
350 | (V2SI "false") (V4SI "false") | |
351 | (V2SF "false") (V4SF "false") | |
352 | (DI "false") (V2DI "false")]) | |
353 | ||
354 | ||
355 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
356 | (V4HI "true") (V8HI "false") | |
357 | (V2SI "true") (V4SI "false") | |
358 | (V2SF "true") (V4SF "false") | |
359 | (DI "true") (V2DI "false")]) | |
360 | ||
361 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
362 | (V4HI "4") (V8HI "8") | |
363 | (V2SI "2") (V4SI "4") | |
364 | (V2SF "2") (V4SF "4") | |
365 | (DI "1") (V2DI "2")]) | |
366 | ||
46b57af1 TB |
367 | ;; Same as V_widen, but lower-case. |
368 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
369 | ||
370 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
371 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c SN |
372 | |
373 | ;;---------------------------------------------------------------------------- | |
374 | ;; Code attributes | |
375 | ;;---------------------------------------------------------------------------- | |
376 | ||
377 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. | |
378 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
379 | (umin "vmin") (umax "vmax")]) | |
380 | ||
381 | ;; Signs of above, where relevant. | |
382 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
383 | (umax "u")]) | |
384 | ||
385 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | |
386 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | |
46b57af1 TB |
387 | |
388 | ;; Assembler mnemonics for signedness of widening operations. | |
389 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) |