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ceddf62c | 1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
cbe34bb5 | 2 | ;; Copyright (C) 2010-2017 Free Software Foundation, Inc. |
ceddf62c SN |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;;---------------------------------------------------------------------------- | |
23 | ;; Mode iterators | |
24 | ;;---------------------------------------------------------------------------- | |
25 | ||
26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
27 | ;; some splits that are the same for all modes when operating on ARM | |
28 | ;; registers. | |
29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) | |
30 | ||
0f38f229 TB |
31 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
32 | ||
ceddf62c SN |
33 | ;; A list of integer modes that are up to one word long |
34 | (define_mode_iterator QHSI [QI HI SI]) | |
35 | ||
a46b23e1 RR |
36 | ;; A list of integer modes that are half and one word long |
37 | (define_mode_iterator HSI [HI SI]) | |
38 | ||
cfe52743 DAG |
39 | ;; A list of integer modes that are less than a word |
40 | (define_mode_iterator NARROW [QI HI]) | |
41 | ||
073a8998 | 42 | ;; A list of all the integer modes up to 64bit |
cfe52743 DAG |
43 | (define_mode_iterator QHSD [QI HI SI DI]) |
44 | ||
45 | ;; A list of the 32bit and 64bit integer modes | |
46 | (define_mode_iterator SIDI [SI DI]) | |
47 | ||
3cff0135 TP |
48 | ;; A list of atomic compare and swap success return modes |
49 | (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) | |
50 | ||
76f722f4 | 51 | ;; A list of modes which the VFP unit can handle |
00ea1506 | 52 | (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) |
76f722f4 | 53 | |
ceddf62c SN |
54 | ;; Integer element sizes implemented by IWMMXT. |
55 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
56 | ||
8fd03515 XQ |
57 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
58 | ||
ceddf62c SN |
59 | ;; Integer element sizes for shifts. |
60 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
61 | ||
62 | ;; Integer and float modes supported by Neon and IWMMXT. | |
63 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
64 | ||
65 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
66 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
67 | ||
68 | ;; Integer modes supported by Neon and IWMMXT | |
69 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
70 | ||
71 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
72 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
73 | ||
4b644867 | 74 | ;; Double-width vector modes, on which we support arithmetic (no HF!) |
ceddf62c SN |
75 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) |
76 | ||
4b644867 AL |
77 | ;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate. |
78 | (define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI]) | |
79 | ||
ceddf62c | 80 | ;; Double-width vector modes plus 64-bit elements. |
4b644867 AL |
81 | (define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI]) |
82 | ||
83 | ;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane. | |
84 | (define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF]) | |
ceddf62c SN |
85 | |
86 | ;; Double-width vector modes without floating-point elements. | |
87 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
88 | ||
4b644867 | 89 | ;; Quad-width vector modes supporting arithmetic (no HF!). |
ceddf62c SN |
90 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) |
91 | ||
4b644867 AL |
92 | ;; Quad-width vector modes, including V8HF. |
93 | (define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF]) | |
94 | ||
95 | ;; Quad-width vector modes with 16- or 32-bit elements | |
96 | (define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF]) | |
97 | ||
ceddf62c | 98 | ;; Quad-width vector modes plus 64-bit elements. |
4b644867 | 99 | (define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI]) |
ceddf62c SN |
100 | |
101 | ;; Quad-width vector modes without floating-point elements. | |
102 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
103 | ||
104 | ;; Quad-width vector modes, with TImode added, for moves. | |
92422235 | 105 | (define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI]) |
ceddf62c SN |
106 | |
107 | ;; Opaque structure types wider than TImode. | |
108 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
109 | ||
110 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
111 | (define_mode_iterator VTAB [TI EI OI]) | |
112 | ||
113 | ;; Widenable modes. | |
114 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
115 | ||
116 | ;; Narrowable modes. | |
117 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
118 | ||
119 | ;; All supported vector modes (except singleton DImode). | |
92422235 | 120 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) |
ceddf62c SN |
121 | |
122 | ;; All supported vector modes (except those with 64-bit integer elements). | |
123 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
124 | ||
b1a970a5 MW |
125 | ;; All supported vector modes including 16-bit float modes. |
126 | (define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF | |
127 | V8HF V4HF]) | |
128 | ||
ceddf62c SN |
129 | ;; Supported integer vector modes (not 64 bit elements). |
130 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
131 | ||
132 | ;; Supported integer vector modes (not singleton DI) | |
133 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
134 | ||
135 | ;; Vector modes, including 64-bit integer elements. | |
4b644867 AL |
136 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI |
137 | V4HF V8HF V2SF V4SF DI V2DI]) | |
ceddf62c SN |
138 | |
139 | ;; Vector modes including 64-bit integer elements, but no floats. | |
140 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
141 | ||
7a10ea9f KT |
142 | ;; Vector modes for H, S and D types. |
143 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
144 | ||
ceddf62c SN |
145 | ;; Vector modes for float->int conversions. |
146 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
147 | ||
148 | ;; Vector modes form int->float conversions. | |
149 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
150 | ||
55a9b91b MW |
151 | ;; Vector modes for int->half conversions. |
152 | (define_mode_iterator VCVTHI [V4HI V8HI]) | |
153 | ||
ceddf62c SN |
154 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. |
155 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
156 | ||
157 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
158 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
159 | ||
160 | ;; Above modes combined. | |
161 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
162 | ||
163 | ;; As VMD, but integer modes only. | |
164 | (define_mode_iterator VMDI [V4HI V2SI]) | |
165 | ||
166 | ;; As VMQ, but integer modes only. | |
167 | (define_mode_iterator VMQI [V8HI V4SI]) | |
168 | ||
169 | ;; Above modes combined. | |
170 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
171 | ||
172 | ;; Modes with 8-bit and 16-bit elements. | |
173 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
174 | ||
175 | ;; Modes with 8-bit elements. | |
176 | (define_mode_iterator VE [V8QI V16QI]) | |
177 | ||
178 | ;; Modes with 64-bit elements only. | |
179 | (define_mode_iterator V64 [DI V2DI]) | |
180 | ||
181 | ;; Modes with 32-bit elements only. | |
182 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
183 | ||
46b57af1 TB |
184 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
185 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
655b30bf | 186 | |
b1a970a5 MW |
187 | ;; Vector modes for 16-bit floating-point support. |
188 | (define_mode_iterator VH [V8HF V4HF]) | |
189 | ||
655b30bf JB |
190 | ;; Iterators used for fixed-point support. |
191 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
192 | ||
193 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
194 | ||
195 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
196 | ||
197 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
198 | ||
199 | (define_mode_iterator QMUL [HQ HA]) | |
200 | ||
94f0f2cc JG |
201 | ;; Modes for polynomial or float values. |
202 | (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) | |
203 | ||
ceddf62c SN |
204 | ;;---------------------------------------------------------------------------- |
205 | ;; Code iterators | |
206 | ;;---------------------------------------------------------------------------- | |
207 | ||
d403b8d4 MW |
208 | ;; A list of condition codes used in compare instructions where |
209 | ;; the carry flag from the addition is used instead of doing the | |
ceddf62c SN |
210 | ;; compare a second time. |
211 | (define_code_iterator LTUGEU [ltu geu]) | |
212 | ||
381811fa KT |
213 | ;; The signed gt, ge comparisons |
214 | (define_code_iterator GTGE [gt ge]) | |
215 | ||
d403b8d4 MW |
216 | ;; The signed gt, ge, lt, le comparisons |
217 | (define_code_iterator GLTE [gt ge lt le]) | |
218 | ||
381811fa KT |
219 | ;; The unsigned gt, ge comparisons |
220 | (define_code_iterator GTUGEU [gtu geu]) | |
221 | ||
222 | ;; Comparisons for vc<cmp> | |
223 | (define_code_iterator COMPARISONS [eq gt ge le lt]) | |
224 | ||
ceddf62c | 225 | ;; A list of ... |
728dc153 | 226 | (define_code_iterator IOR_XOR [ior xor]) |
ceddf62c SN |
227 | |
228 | ;; Operations on two halves of a quadword vector. | |
728dc153 | 229 | (define_code_iterator VQH_OPS [plus smin smax umin umax]) |
ceddf62c SN |
230 | |
231 | ;; Operations on two halves of a quadword vector, | |
232 | ;; without unsigned variants (for use with *SFmode pattern). | |
728dc153 | 233 | (define_code_iterator VQHS_OPS [plus smin smax]) |
ceddf62c | 234 | |
46b57af1 TB |
235 | ;; A list of widening operators |
236 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c | 237 | |
3f2dc806 | 238 | ;; Right shifts |
728dc153 | 239 | (define_code_iterator RSHIFTS [ashiftrt lshiftrt]) |
3f2dc806 | 240 | |
ababd936 KT |
241 | ;; Iterator for integer conversions |
242 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
243 | ||
004d3809 | 244 | ;; Binary operators whose second operand can be shifted. |
728dc153 | 245 | (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) |
004d3809 | 246 | |
d403b8d4 MW |
247 | ;; Operations on the sign of a number. |
248 | (define_code_iterator ABSNEG [abs neg]) | |
249 | ||
250 | ;; Conversions. | |
251 | (define_code_iterator FCVT [unsigned_float float]) | |
252 | ||
728dc153 | 253 | ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows |
004d3809 RE |
254 | ;; a stack pointer opoerand. The minus operation is a candidate for an rsub |
255 | ;; and hence only plus is supported. | |
256 | (define_code_attr t2_binop0 | |
257 | [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) | |
258 | ||
728dc153 | 259 | ;; The instruction to use when a SHIFTABLE_OPS has a shift operation as |
004d3809 RE |
260 | ;; its first operand. |
261 | (define_code_attr arith_shift_insn | |
262 | [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) | |
263 | ||
381811fa KT |
264 | (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") |
265 | (gtu "gt") (geu "ge")]) | |
266 | ||
267 | (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) | |
268 | ||
1dd4fe1f KT |
269 | ;;---------------------------------------------------------------------------- |
270 | ;; Int iterators | |
271 | ;;---------------------------------------------------------------------------- | |
272 | ||
273 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
274 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
275 | ||
55a9b91b MW |
276 | (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE |
277 | UNSPEC_VCLT UNSPEC_VCLE]) | |
381811fa KT |
278 | |
279 | (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) | |
280 | ||
55a9b91b MW |
281 | (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT |
282 | UNSPEC_VCALE UNSPEC_VCALT]) | |
283 | ||
ababd936 KT |
284 | (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) |
285 | ||
79739965 KT |
286 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
287 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
288 | ||
e9e67af1 KT |
289 | (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) |
290 | ||
94f0f2cc JG |
291 | (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) |
292 | ||
293 | (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) | |
294 | ||
295 | (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U | |
296 | UNSPEC_VHADD_S UNSPEC_VHADD_U]) | |
297 | ||
298 | (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) | |
299 | ||
300 | (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) | |
301 | ||
302 | (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) | |
303 | ||
304 | (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) | |
305 | ||
306 | (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) | |
307 | ||
308 | (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) | |
309 | ||
310 | (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) | |
311 | ||
312 | (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) | |
313 | ||
314 | (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) | |
315 | ||
316 | (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) | |
317 | ||
318 | (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) | |
319 | ||
320 | (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) | |
321 | ||
322 | (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) | |
323 | ||
324 | (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) | |
325 | ||
326 | (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) | |
327 | ||
328 | (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) | |
329 | ||
330 | (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) | |
331 | ||
332 | (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U | |
333 | UNSPEC_VMIN UNSPEC_VMIN_U]) | |
334 | ||
335 | (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) | |
336 | ||
0a18c19f DS |
337 | (define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) |
338 | ||
94f0f2cc JG |
339 | (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) |
340 | ||
341 | (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) | |
342 | ||
343 | (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U | |
344 | UNSPEC_VPMIN UNSPEC_VPMIN_U]) | |
345 | ||
346 | (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) | |
347 | ||
348 | (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) | |
349 | ||
350 | (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) | |
351 | ||
d403b8d4 MW |
352 | (define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N]) |
353 | ||
354 | (define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N]) | |
355 | ||
356 | (define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U | |
357 | UNSPEC_VCVTM_S UNSPEC_VCVTM_U | |
358 | UNSPEC_VCVTN_S UNSPEC_VCVTN_U | |
359 | UNSPEC_VCVTP_S UNSPEC_VCVTP_U]) | |
360 | ||
361 | (define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U]) | |
362 | ||
363 | ;; Operators for FP16 instructions. | |
364 | (define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA | |
365 | UNSPEC_VRNDM UNSPEC_VRNDN | |
366 | UNSPEC_VRNDP UNSPEC_VRNDX]) | |
367 | ||
94f0f2cc JG |
368 | (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) |
369 | ||
370 | (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) | |
371 | ||
372 | (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U | |
373 | UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) | |
374 | ||
375 | (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U | |
376 | UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) | |
377 | ||
378 | (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N | |
379 | UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) | |
380 | ||
381 | (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) | |
382 | ||
383 | (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N | |
384 | UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) | |
385 | ||
386 | (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) | |
387 | ||
388 | (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) | |
389 | ||
390 | (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) | |
391 | ||
392 | (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N | |
393 | UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) | |
394 | ||
582e2e43 KT |
395 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
396 | UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) | |
397 | ||
021b5e6b KT |
398 | (define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) |
399 | ||
400 | (define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE | |
401 | UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) | |
402 | ||
403 | (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H | |
404 | UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) | |
405 | ||
406 | (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M | |
407 | UNSPEC_SHA1P]) | |
408 | ||
5f2ca3b2 MW |
409 | (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) |
410 | ||
55a9b91b MW |
411 | (define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE]) |
412 | ||
ceddf62c SN |
413 | ;;---------------------------------------------------------------------------- |
414 | ;; Mode attributes | |
415 | ;;---------------------------------------------------------------------------- | |
416 | ||
3cff0135 TP |
417 | ;; Determine name of atomic compare and swap from success result mode. This |
418 | ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. | |
419 | (define_mode_attr arch [(CC_Z "32") (SI "t1")]) | |
420 | ||
ceddf62c SN |
421 | ;; Determine element size suffix from vector mode. |
422 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
423 | ||
424 | ;; vtbl<n> suffix for NEON vector modes. | |
425 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
426 | ||
427 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
428 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
429 | (V4SI "V4SF") (V4SF "V4SI")]) | |
430 | ||
5bf4dcf2 DP |
431 | ;; As above but in lower case. |
432 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
433 | (V4SI "v4sf") (V4SF "v4si")]) | |
434 | ||
55a9b91b MW |
435 | ;; (Opposite) mode to convert to/from for vector-half mode conversions. |
436 | (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") | |
437 | (V8HI "V8HF") (V8HF "V8HI")]) | |
438 | ||
ceddf62c SN |
439 | ;; Define element mode for each vector mode. |
440 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
4b644867 AL |
441 | (V4HI "HI") (V8HI "HI") |
442 | (V4HF "HF") (V8HF "HF") | |
ceddf62c SN |
443 | (V2SI "SI") (V4SI "SI") |
444 | (V2SF "SF") (V4SF "SF") | |
445 | (DI "DI") (V2DI "DI")]) | |
446 | ||
447 | ;; Element modes for vector extraction, padded up to register size. | |
448 | ||
449 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
450 | (V4HI "SI") (V8HI "SI") | |
451 | (V2SI "SI") (V4SI "SI") | |
452 | (V2SF "SF") (V4SF "SF") | |
453 | (DI "DI") (V2DI "DI")]) | |
454 | ||
455 | ;; Mode of pair of elements for each vector mode, to define transfer | |
456 | ;; size for structure lane/dup loads and stores. | |
6308e208 RS |
457 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
458 | (V4HI "SI") (V8HI "SI") | |
4b644867 | 459 | (V4HF "SF") (V8HF "SF") |
ceddf62c SN |
460 | (V2SI "V2SI") (V4SI "V2SI") |
461 | (V2SF "V2SF") (V4SF "V2SF") | |
462 | (DI "V2DI") (V2DI "V2DI")]) | |
463 | ||
464 | ;; Similar, for three elements. | |
6308e208 RS |
465 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
466 | (V4HI "BLK") (V8HI "BLK") | |
4b644867 | 467 | (V4HF "BLK") (V8HF "BLK") |
6308e208 RS |
468 | (V2SI "BLK") (V4SI "BLK") |
469 | (V2SF "BLK") (V4SF "BLK") | |
470 | (DI "EI") (V2DI "EI")]) | |
ceddf62c SN |
471 | |
472 | ;; Similar, for four elements. | |
473 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
6308e208 | 474 | (V4HI "V4HI") (V8HI "V4HI") |
4b644867 | 475 | (V4HF "V4HF") (V8HF "V4HF") |
ceddf62c SN |
476 | (V2SI "V4SI") (V4SI "V4SI") |
477 | (V2SF "V4SF") (V4SF "V4SF") | |
478 | (DI "OI") (V2DI "OI")]) | |
479 | ||
480 | ;; Register width from element mode | |
481 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
55a9b91b MW |
482 | (V4HI "P") (V8HI "q") |
483 | (V4HF "P") (V8HF "q") | |
484 | (V2SI "P") (V4SI "q") | |
485 | (V2SF "P") (V4SF "q") | |
486 | (DI "P") (V2DI "q") | |
487 | (SF "") (DF "P") | |
488 | (HF "")]) | |
ceddf62c SN |
489 | |
490 | ;; Wider modes with the same number of elements. | |
491 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
492 | ||
493 | ;; Narrower modes with the same number of elements. | |
494 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
495 | ||
0f38f229 TB |
496 | ;; Narrower modes with double the number of elements. |
497 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
498 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
499 | ||
ceddf62c SN |
500 | ;; Modes with half the number of equal-sized elements. |
501 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
4b644867 AL |
502 | (V8HF "V4HF") (V4SI "V2SI") |
503 | (V4SF "V2SF") (V2DF "DF") | |
55a9b91b | 504 | (V2DI "DI") (V4HF "HF")]) |
ceddf62c SN |
505 | |
506 | ;; Same, but lower-case. | |
507 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
508 | (V4SI "v2si") (V4SF "v2sf") | |
509 | (V2DI "di")]) | |
510 | ||
511 | ;; Modes with twice the number of equal-sized elements. | |
512 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
4b644867 AL |
513 | (V2SI "V4SI") (V4HF "V8HF") |
514 | (V2SF "V4SF") (DF "V2DF") | |
515 | (DI "V2DI")]) | |
ceddf62c SN |
516 | |
517 | ;; Same, but lower-case. | |
518 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
519 | (V2SI "v4si") (V2SF "v4sf") | |
520 | (DI "v2di")]) | |
521 | ||
522 | ;; Modes with double-width elements. | |
523 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
524 | (V4HI "V2SI") (V8HI "V4SI") | |
525 | (V2SI "DI") (V4SI "V2DI")]) | |
526 | ||
527 | ;; Double-sized modes with the same element size. | |
528 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
529 | ;; even when the first one is quad. | |
530 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
b1a970a5 MW |
531 | (V4SI "V2SI") (V4SF "V2SF") |
532 | (V8QI "V8QI") (V4HI "V4HI") | |
533 | (V2SI "V2SI") (V2SF "V2SF") | |
534 | (V8HF "V4HF") (V4HF "V4HF")]) | |
ceddf62c SN |
535 | |
536 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
537 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
4b644867 | 538 | (V4HI "V4HI") (V8HI "V8HI") |
ceddf62c | 539 | (V2SI "V2SI") (V4SI "V4SI") |
4b644867 | 540 | (V4HF "V4HI") (V8HF "V8HI") |
ceddf62c SN |
541 | (V2SF "V2SI") (V4SF "V4SI") |
542 | (DI "DI") (V2DI "V2DI")]) | |
543 | ||
f35c297f KT |
544 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
545 | (V4HI "v4hi") (V8HI "v8hi") | |
546 | (V2SI "v2si") (V4SI "v4si") | |
547 | (DI "di") (V2DI "v2di") | |
548 | (V2SF "v2si") (V4SF "v4si")]) | |
549 | ||
ceddf62c SN |
550 | ;; Get element type from double-width mode, for operations where we |
551 | ;; don't care about signedness. | |
552 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
55a9b91b MW |
553 | (V4HI "i16") (V8HI "i16") |
554 | (V2SI "i32") (V4SI "i32") | |
555 | (DI "i64") (V2DI "i64") | |
556 | (V2SF "f32") (V4SF "f32") | |
557 | (SF "f32") (DF "f64") | |
558 | (HF "f16") (V4HF "f16") | |
559 | (V8HF "f16")]) | |
ceddf62c SN |
560 | |
561 | ;; Same, but for operations which work on signed values. | |
562 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
55a9b91b MW |
563 | (V4HI "s16") (V8HI "s16") |
564 | (V2SI "s32") (V4SI "s32") | |
565 | (DI "s64") (V2DI "s64") | |
566 | (V2SF "f32") (V4SF "f32") | |
567 | (HF "f16") (V4HF "f16") | |
568 | (V8HF "f16")]) | |
ceddf62c SN |
569 | |
570 | ;; Same, but for operations which work on unsigned values. | |
571 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
572 | (V4HI "u16") (V8HI "u16") | |
573 | (V2SI "u32") (V4SI "u32") | |
574 | (DI "u64") (V2DI "u64") | |
575 | (V2SF "f32") (V4SF "f32")]) | |
576 | ||
577 | ;; Element types for extraction of unsigned scalars. | |
578 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
579 | (V4HI "u16") (V8HI "u16") | |
580 | (V2SI "32") (V4SI "32") | |
4b644867 | 581 | (V4HF "u16") (V8HF "u16") |
ceddf62c SN |
582 | (V2SF "32") (V4SF "32")]) |
583 | ||
584 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
55a9b91b MW |
585 | (V4HI "16") (V8HI "16") |
586 | (V2SI "32") (V4SI "32") | |
587 | (DI "64") (V2DI "64") | |
4b644867 | 588 | (V4HF "16") (V8HF "16") |
55a9b91b | 589 | (V2SF "32") (V4SF "32")]) |
ceddf62c | 590 | |
f7379e5e | 591 | (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") |
55a9b91b MW |
592 | (V4HI "h") (V8HI "h") |
593 | (V2SI "s") (V4SI "s") | |
594 | (DI "d") (V2DI "d") | |
595 | (V2SF "s") (V4SF "s") | |
596 | (V2SF "s") (V4SF "s")]) | |
597 | ||
598 | (define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s") | |
599 | (V4HF "s") (V8HF "s") | |
600 | (HF "s")]) | |
f7379e5e | 601 | |
ceddf62c SN |
602 | ;; Element sizes for duplicating ARM registers to all elements of a vector. |
603 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
604 | ||
605 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
606 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
607 | (V4HI "TI") (V8HI "OI") | |
608 | (V2SI "TI") (V4SI "OI") | |
609 | (V2SF "TI") (V4SF "OI") | |
610 | (DI "TI") (V2DI "OI")]) | |
611 | ||
612 | ;; Same, but lower-case. | |
613 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
614 | (V4HI "ti") (V8HI "oi") | |
615 | (V2SI "ti") (V4SI "oi") | |
616 | (V2SF "ti") (V4SF "oi") | |
617 | (DI "ti") (V2DI "oi")]) | |
618 | ||
619 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
620 | ;; names which we don't want to define). | |
621 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
622 | (V4HI "") (V8HI "") | |
623 | (V2SI "") (V4SI "") | |
624 | (V2SF "") (V4SF "") | |
625 | (DI "_neon") (V2DI "")]) | |
626 | ||
627 | ||
628 | ;; Scalars to be presented to scalar multiplication instructions | |
629 | ;; must satisfy the following constraints. | |
630 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
631 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
632 | ||
633 | ;; This mode attribute is used to obtain the correct register constraints. | |
634 | ||
635 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
55a9b91b MW |
636 | (V8HI "x") (V4SI "t") (V4SF "t") |
637 | (V8HF "x") (V4HF "x")]) | |
ceddf62c | 638 | |
003bb7f3 | 639 | ;; Predicates used for setting type for neon instructions |
ceddf62c SN |
640 | |
641 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
55a9b91b MW |
642 | (V4HI "false") (V8HI "false") |
643 | (V2SI "false") (V4SI "false") | |
644 | (V4HF "true") (V8HF "true") | |
645 | (V2SF "true") (V4SF "true") | |
646 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
647 | |
648 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
b1a970a5 MW |
649 | (V4HI "true") (V8HI "true") |
650 | (V2SI "false") (V4SI "false") | |
651 | (V2SF "false") (V4SF "false") | |
652 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
653 | |
654 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
55a9b91b MW |
655 | (V4HI "true") (V8HI "false") |
656 | (V2SI "true") (V4SI "false") | |
657 | (V2SF "true") (V4SF "false") | |
658 | (DI "true") (V2DI "false") | |
b1a970a5 | 659 | (V4HF "true") (V8HF "false")]) |
ceddf62c SN |
660 | |
661 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
4b644867 | 662 | (V4HF "4") (V8HF "8") |
ceddf62c SN |
663 | (V4HI "4") (V8HI "8") |
664 | (V2SI "2") (V4SI "4") | |
665 | (V2SF "2") (V4SF "4") | |
0f38f229 TB |
666 | (DI "1") (V2DI "2") |
667 | (DF "1") (V2DF "2")]) | |
ceddf62c | 668 | |
46b57af1 TB |
669 | ;; Same as V_widen, but lower-case. |
670 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
671 | ||
672 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
673 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c | 674 | |
da0a441d BS |
675 | ;; Conditions to be used in extend<mode>di patterns. |
676 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
677 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
678 | (QI "&& arm_arch6")]) | |
8d4f1548 | 679 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
c9cdcaa5 BS |
680 | (HI "nonimmediate_operand") |
681 | (QI "nonimmediate_operand")]) | |
8d4f1548 RR |
682 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
683 | (HI "nonimmediate_operand") | |
684 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
e0237780 GY |
685 | (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) |
686 | (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) | |
da0a441d | 687 | |
655b30bf JB |
688 | ;; Mode attributes used for fixed-point support. |
689 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
690 | (V2UHA "16") (UHA "16") | |
691 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
692 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
693 | ||
36ba4aae IR |
694 | ;; Mode attribute for vshll. |
695 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
696 | ||
1dd4fe1f | 697 | ;; Mode attributes used for VFP support. |
76f722f4 | 698 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
1dd4fe1f KT |
699 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
700 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
76f722f4 | 701 | |
f7379e5e JG |
702 | ;; Mode attribute used to build the "type" attribute. |
703 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
55a9b91b MW |
704 | (V4HI "") (V8HI "_q") |
705 | (V2SI "") (V4SI "_q") | |
4b644867 | 706 | (V4HF "") (V8HF "_q") |
55a9b91b MW |
707 | (V2SF "") (V4SF "_q") |
708 | (V4HF "") (V8HF "_q") | |
709 | (DI "") (V2DI "_q") | |
710 | (DF "") (V2DF "_q") | |
711 | (HF "")]) | |
f7379e5e | 712 | |
94f0f2cc JG |
713 | (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) |
714 | ||
ceddf62c SN |
715 | ;;---------------------------------------------------------------------------- |
716 | ;; Code attributes | |
717 | ;;---------------------------------------------------------------------------- | |
718 | ||
719 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. | |
720 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
721 | (umin "vmin") (umax "vmax")]) | |
722 | ||
f7379e5e JG |
723 | ;; Type attributes for vqh_ops and vqhs_ops iterators. |
724 | (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") | |
725 | (umin "minmax") (umax "minmax")]) | |
726 | ||
ceddf62c SN |
727 | ;; Signs of above, where relevant. |
728 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
729 | (umax "u")]) | |
730 | ||
731 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | |
732 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | |
46b57af1 TB |
733 | |
734 | ;; Assembler mnemonics for signedness of widening operations. | |
735 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
3f2dc806 | 736 | |
ababd936 KT |
737 | ;; Signedness suffix for float->fixed conversions. Empty for signed |
738 | ;; conversion. | |
739 | (define_code_attr su_optab [(fix "") (unsigned_fix "u")]) | |
740 | ||
741 | ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. | |
742 | (define_code_attr su [(fix "s") (unsigned_fix "u")]) | |
743 | ||
3f2dc806 AS |
744 | ;; Right shifts |
745 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
746 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
747 | ||
d403b8d4 MW |
748 | ;; String reprentations of operations on the sign of a number. |
749 | (define_code_attr absneg_str [(abs "abs") (neg "neg")]) | |
750 | ||
751 | ;; Conversions. | |
752 | (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) | |
753 | ||
55a9b91b MW |
754 | (define_code_attr float_sup [(unsigned_float "u") (float "s")]) |
755 | ||
756 | (define_code_attr float_SUP [(unsigned_float "U") (float "S")]) | |
757 | ||
1dd4fe1f KT |
758 | ;;---------------------------------------------------------------------------- |
759 | ;; Int attributes | |
760 | ;;---------------------------------------------------------------------------- | |
761 | ||
94f0f2cc JG |
762 | ;; Mapping between vector UNSPEC operations and the signed ('s'), |
763 | ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. | |
764 | (define_int_attr sup [ | |
765 | (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") | |
766 | (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") | |
767 | (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") | |
768 | (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") | |
769 | (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") | |
770 | (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") | |
771 | (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") | |
772 | (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") | |
773 | (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") | |
774 | (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") | |
775 | (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") | |
776 | (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") | |
777 | (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") | |
778 | (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") | |
779 | (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") | |
780 | (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") | |
781 | (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") | |
782 | (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") | |
783 | (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") | |
784 | (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") | |
785 | (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") | |
786 | (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") | |
787 | (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") | |
788 | (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") | |
d403b8d4 MW |
789 | (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u") |
790 | (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u") | |
791 | (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u") | |
792 | (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u") | |
94f0f2cc | 793 | (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") |
d403b8d4 MW |
794 | (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u") |
795 | (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u") | |
94f0f2cc JG |
796 | (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") |
797 | (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") | |
798 | (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") | |
799 | (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") | |
800 | (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") | |
801 | (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") | |
802 | (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") | |
803 | (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") | |
804 | (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") | |
805 | (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") | |
806 | (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") | |
807 | (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") | |
808 | (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") | |
809 | (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") | |
d403b8d4 | 810 | (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u") |
94f0f2cc JG |
811 | ]) |
812 | ||
d403b8d4 MW |
813 | (define_int_attr vcvth_op |
814 | [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a") | |
815 | (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m") | |
816 | (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n") | |
817 | (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")]) | |
818 | ||
819 | (define_int_attr fp16_rnd_str | |
820 | [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda") | |
821 | (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn") | |
822 | (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")]) | |
823 | ||
824 | (define_int_attr fp16_rnd_insn | |
825 | [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta") | |
826 | (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn") | |
827 | (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")]) | |
828 | ||
381811fa | 829 | (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") |
55a9b91b MW |
830 | (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") |
831 | (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") | |
832 | (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le") | |
833 | (UNSPEC_VCALT "lt")]) | |
381811fa | 834 | |
94f0f2cc JG |
835 | (define_int_attr r [ |
836 | (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") | |
837 | (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") | |
838 | (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") | |
839 | (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") | |
840 | (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") | |
841 | (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") | |
842 | ]) | |
843 | ||
844 | (define_int_attr maxmin [ | |
845 | (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") | |
846 | (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") | |
847 | (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") | |
848 | (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") | |
849 | ]) | |
850 | ||
0a18c19f DS |
851 | (define_int_attr fmaxmin [ |
852 | (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) | |
853 | ||
854 | (define_int_attr fmaxmin_op [ | |
855 | (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") | |
856 | ]) | |
857 | ||
94f0f2cc JG |
858 | (define_int_attr shift_op [ |
859 | (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") | |
860 | (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") | |
861 | (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") | |
862 | (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") | |
863 | (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") | |
864 | (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") | |
865 | (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") | |
866 | (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") | |
867 | (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") | |
868 | (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") | |
869 | (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") | |
870 | (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") | |
871 | ]) | |
872 | ||
1dd4fe1f KT |
873 | ;; Standard names for floating point to integral rounding instructions. |
874 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
875 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
876 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
877 | ||
878 | ;; Suffixes for vrint instructions specifying rounding modes. | |
879 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
880 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
881 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
882 | ||
883 | ;; Some of the vrint instuctions are predicable. | |
884 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
885 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
886 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
79739965 | 887 | |
fca0efeb KT |
888 | (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") |
889 | (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") | |
890 | (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) | |
891 | ||
79739965 KT |
892 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") |
893 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
894 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) | |
582e2e43 KT |
895 | |
896 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") | |
897 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") | |
898 | (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) | |
899 | ||
900 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
901 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") | |
902 | (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) | |
903 | ||
021b5e6b KT |
904 | (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") |
905 | (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") | |
906 | (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") | |
907 | (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") | |
908 | (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") | |
909 | (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") | |
910 | (UNSPEC_SHA256H2 "sha256h2") | |
911 | (UNSPEC_SHA256SU1 "sha256su1")]) | |
912 | ||
913 | (define_int_attr crypto_type | |
b10baa95 KT |
914 | [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") |
915 | (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") | |
021b5e6b KT |
916 | (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") |
917 | (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") | |
918 | (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") | |
919 | (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") | |
920 | (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) | |
921 | ||
922 | (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") | |
923 | (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") | |
924 | (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") | |
925 | (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") | |
926 | (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") | |
927 | (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") | |
928 | (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) | |
929 | ||
930 | (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") | |
931 | (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") | |
932 | (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") | |
933 | (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") | |
934 | (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") | |
935 | (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") | |
936 | (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) | |
937 | ||
24d5b097 | 938 | ;; Both kinds of return insn. |
728dc153 | 939 | (define_code_iterator RETURNS [return simple_return]) |
24d5b097 XG |
940 | (define_code_attr return_str [(return "") (simple_return "simple_")]) |
941 | (define_code_attr return_simple_p [(return "false") (simple_return "true")]) | |
942 | (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") | |
943 | (simple_return " && use_simple_return_p ()")]) | |
944 | (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") | |
945 | (simple_return " && use_simple_return_p ()")]) | |
5f2ca3b2 MW |
946 | |
947 | ;; Attributes for VQRDMLAH/VQRDMLSH | |
948 | (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) | |
55a9b91b MW |
949 | |
950 | ;; Attributes for VFMA_LANE/ VFMS_LANE | |
951 | (define_int_attr neon_vfm_lane_as | |
952 | [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")]) | |
d57daa0c AV |
953 | |
954 | ;; An iterator for the CDP coprocessor instructions | |
955 | (define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2]) | |
956 | (define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")]) | |
957 | (define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")]) | |
3811581f AV |
958 | |
959 | ;; An iterator for the LDC coprocessor instruction | |
960 | (define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2 | |
961 | VUNSPEC_LDCL VUNSPEC_LDC2L]) | |
962 | (define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2") | |
963 | (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")]) | |
964 | (define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2") | |
965 | (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")]) | |
966 | ||
967 | ;; An iterator for the STC coprocessor instructions | |
968 | (define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2 | |
969 | VUNSPEC_STCL VUNSPEC_STC2L]) | |
970 | (define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2") | |
971 | (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")]) | |
972 | (define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2") | |
973 | (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")]) | |
ecc9a25b AV |
974 | |
975 | ;; An iterator for the MCR coprocessor instructions | |
976 | (define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2]) | |
977 | ||
978 | (define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")]) | |
979 | (define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")]) | |
980 | ||
981 | ;; An iterator for the MRC coprocessor instructions | |
982 | (define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2]) | |
983 | ||
984 | (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) | |
985 | (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) | |
f3caa118 AV |
986 | |
987 | ;; An iterator for the MCRR coprocessor instructions | |
988 | (define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) | |
989 | ||
990 | (define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) | |
991 | (define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) | |
992 | ||
993 | ;; An iterator for the MRRC coprocessor instructions | |
994 | (define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) | |
995 | ||
996 | (define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) | |
997 | (define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) |