[thirdparty/gcc.git] / gcc / config / arm / iterators.md

;; Code and mode itertator and attribute definitions for the ARM backend
;; Copyright (C) 2010 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.


;;----------------------------------------------------------------------------
;; Mode iterators
;;----------------------------------------------------------------------------

;; A list of modes that are exactly 64 bits in size. This is used to expand
;; some splits that are the same for all modes when operating on ARM 
;; registers.
(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])

(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])

;; A list of integer modes that are up to one word long
(define_mode_iterator QHSI [QI HI SI])

;; A list of integer modes that are less than a word
(define_mode_iterator NARROW [QI HI])

;; A list of all the integer modes up to 64bit
(define_mode_iterator QHSD [QI HI SI DI])

;; A list of the 32bit and 64bit integer modes
(define_mode_iterator SIDI [SI DI])

;; Integer element sizes implemented by IWMMXT.
(define_mode_iterator VMMX [V2SI V4HI V8QI])

;; Integer element sizes for shifts.
(define_mode_iterator VSHFT [V4HI V2SI DI])

;; Integer and float modes supported by Neon and IWMMXT.
(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])

;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])

;; Integer modes supported by Neon and IWMMXT
(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])

;; Integer modes supported by Neon and IWMMXT, except V2DI
(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])

;; Double-width vector modes.
(define_mode_iterator VD [V8QI V4HI V2SI V2SF])

;; Double-width vector modes plus 64-bit elements.
(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])

;; Double-width vector modes without floating-point elements.
(define_mode_iterator VDI [V8QI V4HI V2SI])

;; Quad-width vector modes.
(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])

;; Quad-width vector modes plus 64-bit elements.
(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])

;; Quad-width vector modes without floating-point elements.
(define_mode_iterator VQI [V16QI V8HI V4SI])

;; Quad-width vector modes, with TImode added, for moves.
(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])

;; Opaque structure types wider than TImode.
(define_mode_iterator VSTRUCT [EI OI CI XI])

;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
(define_mode_iterator VTAB [TI EI OI])

;; Widenable modes.
(define_mode_iterator VW [V8QI V4HI V2SI])

;; Narrowable modes.
(define_mode_iterator VN [V8HI V4SI V2DI])

;; All supported vector modes (except singleton DImode).
(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])

;; All supported vector modes (except those with 64-bit integer elements).
(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])

;; Supported integer vector modes (not 64 bit elements).
(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])

;; Supported integer vector modes (not singleton DI)
(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])

;; Vector modes, including 64-bit integer elements.
(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])

;; Vector modes including 64-bit integer elements, but no floats.
(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])

;; Vector modes for float->int conversions.
(define_mode_iterator VCVTF [V2SF V4SF])

;; Vector modes form int->float conversions.
(define_mode_iterator VCVTI [V2SI V4SI])

;; Vector modes for doubleword multiply-accumulate, etc. insns.
(define_mode_iterator VMD [V4HI V2SI V2SF])

;; Vector modes for quadword multiply-accumulate, etc. insns.
(define_mode_iterator VMQ [V8HI V4SI V4SF])

;; Above modes combined.
(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])

;; As VMD, but integer modes only.
(define_mode_iterator VMDI [V4HI V2SI])

;; As VMQ, but integer modes only.
(define_mode_iterator VMQI [V8HI V4SI])

;; Above modes combined.
(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])

;; Modes with 8-bit and 16-bit elements.
(define_mode_iterator VX [V8QI V4HI V16QI V8HI])

;; Modes with 8-bit elements.
(define_mode_iterator VE [V8QI V16QI])

;; Modes with 64-bit elements only.
(define_mode_iterator V64 [DI V2DI])

;; Modes with 32-bit elements only.
(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])

;; Modes with 8-bit, 16-bit and 32-bit elements.
(define_mode_iterator VU [V16QI V8HI V4SI])

;; Iterators used for fixed-point support.
(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])

(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])

(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])

(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])

(define_mode_iterator QMUL [HQ HA])

;;----------------------------------------------------------------------------
;; Code iterators
;;----------------------------------------------------------------------------

;; A list of condition codes used in compare instructions where 
;; the carry flag from the addition is used instead of doing the 
;; compare a second time.
(define_code_iterator LTUGEU [ltu geu])

;; A list of ...
(define_code_iterator ior_xor [ior xor])

;; Operations on two halves of a quadword vector.
(define_code_iterator vqh_ops [plus smin smax umin umax])

;; Operations on two halves of a quadword vector,
;; without unsigned variants (for use with *SFmode pattern).
(define_code_iterator vqhs_ops [plus smin smax])

;; A list of widening operators
(define_code_iterator SE [sign_extend zero_extend])

;;----------------------------------------------------------------------------
;; Mode attributes
;;----------------------------------------------------------------------------

;; Determine element size suffix from vector mode.
(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])

;; vtbl<n> suffix for NEON vector modes.
(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])

;; (Opposite) mode to convert to/from for NEON mode conversions.
(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
               (V4SI "V4SF") (V4SF "V4SI")])

;; As above but in lower case.
(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
                           (V4SI "v4sf") (V4SF "v4si")])

;; Define element mode for each vector mode.
(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
              (V4HI "HI") (V8HI "HI")
                          (V2SI "SI") (V4SI "SI")
                          (V2SF "SF") (V4SF "SF")
                          (DI "DI")   (V2DI "DI")])

;; Element modes for vector extraction, padded up to register size.

(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
             (V4HI "SI") (V8HI "SI")
             (V2SI "SI") (V4SI "SI")
             (V2SF "SF") (V4SF "SF")
             (DI "DI") (V2DI "DI")])

;; Mode of pair of elements for each vector mode, to define transfer
;; size for structure lane/dup loads and stores.
(define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
                              (V4HI "SI")   (V8HI "SI")
                              (V2SI "V2SI") (V4SI "V2SI")
                              (V2SF "V2SF") (V4SF "V2SF")
                              (DI "V2DI")   (V2DI "V2DI")])

;; Similar, for three elements.
(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
                                (V4HI "BLK") (V8HI "BLK")
                                (V2SI "BLK") (V4SI "BLK")
                                (V2SF "BLK") (V4SF "BLK")
                                (DI "EI")    (V2DI "EI")])

;; Similar, for four elements.
(define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
                               (V4HI "V4HI") (V8HI "V4HI")
                               (V2SI "V4SI") (V4SI "V4SI")
                               (V2SF "V4SF") (V4SF "V4SF")
                               (DI "OI")     (V2DI "OI")])

;; Register width from element mode
(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
                         (V4HI "P") (V8HI  "q")
                         (V2SI "P") (V4SI  "q")
                         (V2SF "P") (V4SF  "q")
                         (DI   "P") (V2DI  "q")])

;; Wider modes with the same number of elements.
(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])

;; Narrower modes with the same number of elements.
(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])

;; Narrower modes with double the number of elements.
(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
				 (V4HI "V8QI") (V2SI "V4HI")  (DI "V2SI")])

;; Modes with half the number of equal-sized elements.
(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
              (V4SI  "V2SI") (V4SF "V2SF") (V2DF "DF")
                          (V2DI "DI")])

;; Same, but lower-case.
(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
              (V4SI  "v2si") (V4SF "v2sf")
                          (V2DI "di")])

;; Modes with twice the number of equal-sized elements.
(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
                (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
                            (DI "V2DI")])

;; Same, but lower-case.
(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
                (V2SI "v4si") (V2SF "v4sf")
                            (DI "v2di")])

;; Modes with double-width elements.
(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
                  (V4HI "V2SI") (V8HI "V4SI")
                  (V2SI "DI")   (V4SI "V2DI")])

;; Double-sized modes with the same element size.
;; Used for neon_vdup_lane, where the second operand is double-sized
;; even when the first one is quad.
(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
                                        (V4SI "V2SI") (V4SF "V2SF")
                                        (V8QI "V8QI") (V4HI "V4HI")
                                        (V2SI "V2SI") (V2SF "V2SF")])

;; Mode of result of comparison operations (and bit-select operand 1).
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
                    (V4HI "V4HI") (V8HI  "V8HI")
                                (V2SI "V2SI") (V4SI  "V4SI")
                                (V2SF "V2SI") (V4SF  "V4SI")
                                (DI   "DI")   (V2DI  "V2DI")])

;; Get element type from double-width mode, for operations where we 
;; don't care about signedness.
(define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
                 (V4HI "i16") (V8HI  "i16")
                             (V2SI "i32") (V4SI  "i32")
                             (DI   "i64") (V2DI  "i64")
                 (V2SF "f32") (V4SF  "f32")])

;; Same, but for operations which work on signed values.
(define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
                (V4HI "s16") (V8HI  "s16")
                            (V2SI "s32") (V4SI  "s32")
                            (DI   "s64") (V2DI  "s64")
                (V2SF "f32") (V4SF  "f32")])

;; Same, but for operations which work on unsigned values.
(define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
                (V4HI "u16") (V8HI  "u16")
                            (V2SI "u32") (V4SI  "u32")
                            (DI   "u64") (V2DI  "u64")
                            (V2SF "f32") (V4SF  "f32")])

;; Element types for extraction of unsigned scalars.
(define_mode_attr V_uf_sclr [(V8QI "u8")  (V16QI "u8")
                 (V4HI "u16") (V8HI "u16")
                             (V2SI "32") (V4SI "32")
                             (V2SF "32") (V4SF "32")])

(define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
                 (V4HI "16") (V8HI  "16")
                             (V2SI "32") (V4SI  "32")
                             (DI   "64") (V2DI  "64")
                 (V2SF "32") (V4SF  "32")])

;; Element sizes for duplicating ARM registers to all elements of a vector.
(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])

;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
              (V4HI "TI") (V8HI  "OI")
                          (V2SI "TI") (V4SI  "OI")
                          (V2SF "TI") (V4SF  "OI")
                          (DI   "TI") (V2DI  "OI")])

;; Same, but lower-case.
(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
              (V4HI "ti") (V8HI  "oi")
                          (V2SI "ti") (V4SI  "oi")
                          (V2SF "ti") (V4SF  "oi")
                          (DI   "ti") (V2DI  "oi")])

;; Extra suffix on some 64-bit insn names (to avoid collision with standard
;; names which we don't want to define).
(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
                           (V4HI "") (V8HI "")
                           (V2SI "") (V4SI "")
                           (V2SF "") (V4SF "")
                           (DI "_neon") (V2DI "")])


;; Scalars to be presented to scalar multiplication instructions
;; must satisfy the following constraints.
;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.

;; This mode attribute is used to obtain the correct register constraints.

(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
                                         (V8HI "x") (V4SI "t") (V4SF "t")])

;; Predicates used for setting neon_type

(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
                 (V4HI "false") (V8HI "false")
                 (V2SI "false") (V4SI "false")
                 (V2SF "true") (V4SF "true")
                 (DI "false") (V2DI "false")])

(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
                   (V4HI "true") (V8HI "true")
                   (V2SI "false") (V4SI "false")
                   (V2SF "false") (V4SF "false")
                   (DI "false") (V2DI "false")])


(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
                            (V4HI "true") (V8HI  "false")
                            (V2SI "true") (V4SI  "false")
                            (V2SF "true") (V4SF  "false")
                            (DI   "true") (V2DI  "false")])

(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
                                 (V4HI "4") (V8HI "8")
                                 (V2SI "2") (V4SI "4")
                                 (V2SF "2") (V4SF "4")
                                 (DI "1")   (V2DI "2")
                                 (DF "1")   (V2DF "2")])

;; Same as V_widen, but lower-case.
(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])

;; Widen. Result is half the number of elements, but widened to double-width.
(define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])

;; Conditions to be used in extend<mode>di patterns.
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
				      (QI "&& arm_arch6")])
(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
				   (HI "nonimmediate_operand")
				   (QI "nonimmediate_operand")])
(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
				   (HI "nonimmediate_operand")
				   (QI "arm_reg_or_extendqisi_mem_op")])
(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])

;; Mode attributes used for fixed-point support.
(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
			       (V2UHA "16") (UHA "16")
			       (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
			       (V2HA "16") (HA "16") (SQ "") (SA "")])

;; Mode attribute for vshll.
(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])

;;----------------------------------------------------------------------------
;; Code attributes
;;----------------------------------------------------------------------------

;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
                (umin "vmin") (umax "vmax")])

;; Signs of above, where relevant.
(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
                (umax "u")])

(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
(define_code_attr optab [(ltu "ltu") (geu "geu")])

;; Assembler mnemonics for signedness of widening operations.
(define_code_attr US [(sign_extend "s") (zero_extend "u")])
Commit	Line	Data
ceddf62c SN	1	;; Code and mode itertator and attribute definitions for the ARM backend
	2	;; Copyright (C) 2010 Free Software Foundation, Inc.
	3	;; Contributed by ARM Ltd.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
	9	;; by the Free Software Foundation; either version 3, or (at your
	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20
	21
	22	;;----------------------------------------------------------------------------
	23	;; Mode iterators
	24	;;----------------------------------------------------------------------------
	25
	26	;; A list of modes that are exactly 64 bits in size. This is used to expand
	27	;; some splits that are the same for all modes when operating on ARM
	28	;; registers.
	29	(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
	30
0f38f229 TB	31	(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
0f38f229 TB	32
ceddf62c SN	33	;; A list of integer modes that are up to one word long
	34	(define_mode_iterator QHSI [QI HI SI])
	35
cfe52743 DAG	36	;; A list of integer modes that are less than a word
	37	(define_mode_iterator NARROW [QI HI])
	38
073a8998	39	;; A list of all the integer modes up to 64bit
cfe52743 DAG	40	(define_mode_iterator QHSD [QI HI SI DI])
	41
	42	;; A list of the 32bit and 64bit integer modes
	43	(define_mode_iterator SIDI [SI DI])
	44
ceddf62c SN	45	;; Integer element sizes implemented by IWMMXT.
	46	(define_mode_iterator VMMX [V2SI V4HI V8QI])
	47
	48	;; Integer element sizes for shifts.
	49	(define_mode_iterator VSHFT [V4HI V2SI DI])
	50
	51	;; Integer and float modes supported by Neon and IWMMXT.
	52	(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
	53
	54	;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
	55	(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
	56
	57	;; Integer modes supported by Neon and IWMMXT
	58	(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
	59
	60	;; Integer modes supported by Neon and IWMMXT, except V2DI
	61	(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
	62
	63	;; Double-width vector modes.
	64	(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
	65
	66	;; Double-width vector modes plus 64-bit elements.
	67	(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
	68
	69	;; Double-width vector modes without floating-point elements.
	70	(define_mode_iterator VDI [V8QI V4HI V2SI])
	71
	72	;; Quad-width vector modes.
	73	(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
	74
	75	;; Quad-width vector modes plus 64-bit elements.
	76	(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
	77
	78	;; Quad-width vector modes without floating-point elements.
	79	(define_mode_iterator VQI [V16QI V8HI V4SI])
	80
	81	;; Quad-width vector modes, with TImode added, for moves.
	82	(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
	83
	84	;; Opaque structure types wider than TImode.
	85	(define_mode_iterator VSTRUCT [EI OI CI XI])
	86
	87	;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
	88	(define_mode_iterator VTAB [TI EI OI])
	89
	90	;; Widenable modes.
	91	(define_mode_iterator VW [V8QI V4HI V2SI])
	92
	93	;; Narrowable modes.
	94	(define_mode_iterator VN [V8HI V4SI V2DI])
	95
	96	;; All supported vector modes (except singleton DImode).
	97	(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
	98
	99	;; All supported vector modes (except those with 64-bit integer elements).
	100	(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
	101
	102	;; Supported integer vector modes (not 64 bit elements).
	103	(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
	104
	105	;; Supported integer vector modes (not singleton DI)
	106	(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
	107
	108	;; Vector modes, including 64-bit integer elements.
109	(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
110
111	;; Vector modes including 64-bit integer elements, but no floats.
112	(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
113
114	;; Vector modes for float->int conversions.
115	(define_mode_iterator VCVTF [V2SF V4SF])
116
117	;; Vector modes form int->float conversions.
118	(define_mode_iterator VCVTI [V2SI V4SI])
119
120	;; Vector modes for doubleword multiply-accumulate, etc. insns.
121	(define_mode_iterator VMD [V4HI V2SI V2SF])
122
123	;; Vector modes for quadword multiply-accumulate, etc. insns.
124	(define_mode_iterator VMQ [V8HI V4SI V4SF])
125
126	;; Above modes combined.
127	(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
128
129	;; As VMD, but integer modes only.
130	(define_mode_iterator VMDI [V4HI V2SI])
131
132	;; As VMQ, but integer modes only.
133	(define_mode_iterator VMQI [V8HI V4SI])
134
135	;; Above modes combined.
136	(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
137
138	;; Modes with 8-bit and 16-bit elements.
139	(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
140
141	;; Modes with 8-bit elements.
142	(define_mode_iterator VE [V8QI V16QI])
143
144	;; Modes with 64-bit elements only.
145	(define_mode_iterator V64 [DI V2DI])
146
147	;; Modes with 32-bit elements only.
148	(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
149
46b57af1 TB	150	;; Modes with 8-bit, 16-bit and 32-bit elements.
46b57af1 TB	151	(define_mode_iterator VU [V16QI V8HI V4SI])
655b30bf JB	152
	153	;; Iterators used for fixed-point support.
	154	(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
	155
	156	(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
	157
	158	(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
	159
	160	(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
	161
	162	(define_mode_iterator QMUL [HQ HA])
	163
ceddf62c SN	164	;;----------------------------------------------------------------------------
	165	;; Code iterators
	166	;;----------------------------------------------------------------------------
	167
	168	;; A list of condition codes used in compare instructions where
	169	;; the carry flag from the addition is used instead of doing the
	170	;; compare a second time.
	171	(define_code_iterator LTUGEU [ltu geu])
	172
	173	;; A list of ...
	174	(define_code_iterator ior_xor [ior xor])
	175
	176	;; Operations on two halves of a quadword vector.
	177	(define_code_iterator vqh_ops [plus smin smax umin umax])
	178
	179	;; Operations on two halves of a quadword vector,
	180	;; without unsigned variants (for use with *SFmode pattern).
	181	(define_code_iterator vqhs_ops [plus smin smax])
	182
46b57af1 TB	183	;; A list of widening operators
46b57af1 TB	184	(define_code_iterator SE [sign_extend zero_extend])
ceddf62c SN	185
	186	;;----------------------------------------------------------------------------
	187	;; Mode attributes
	188	;;----------------------------------------------------------------------------
	189
	190	;; Determine element size suffix from vector mode.
	191	(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
	192
	193	;; vtbl<n> suffix for NEON vector modes.
	194	(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
	195
	196	;; (Opposite) mode to convert to/from for NEON mode conversions.
	197	(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
	198	(V4SI "V4SF") (V4SF "V4SI")])
	199
5bf4dcf2 DP	200	;; As above but in lower case.
	201	(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
	202	(V4SI "v4sf") (V4SF "v4si")])
	203
ceddf62c SN	204	;; Define element mode for each vector mode.
	205	(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
	206	(V4HI "HI") (V8HI "HI")
	207	(V2SI "SI") (V4SI "SI")
	208	(V2SF "SF") (V4SF "SF")
	209	(DI "DI") (V2DI "DI")])
	210
	211	;; Element modes for vector extraction, padded up to register size.
	212
	213	(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
	214	(V4HI "SI") (V8HI "SI")
	215	(V2SI "SI") (V4SI "SI")
	216	(V2SF "SF") (V4SF "SF")
	217	(DI "DI") (V2DI "DI")])
	218
	219	;; Mode of pair of elements for each vector mode, to define transfer
	220	;; size for structure lane/dup loads and stores.
6308e208 RS	221	(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
6308e208 RS	222	(V4HI "SI") (V8HI "SI")
ceddf62c SN	223	(V2SI "V2SI") (V4SI "V2SI")
	224	(V2SF "V2SF") (V4SF "V2SF")
	225	(DI "V2DI") (V2DI "V2DI")])
	226
	227	;; Similar, for three elements.
6308e208 RS	228	(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
	229	(V4HI "BLK") (V8HI "BLK")
	230	(V2SI "BLK") (V4SI "BLK")
	231	(V2SF "BLK") (V4SF "BLK")
	232	(DI "EI") (V2DI "EI")])
ceddf62c SN	233
	234	;; Similar, for four elements.
	235	(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
6308e208	236	(V4HI "V4HI") (V8HI "V4HI")
ceddf62c SN	237	(V2SI "V4SI") (V4SI "V4SI")
	238	(V2SF "V4SF") (V4SF "V4SF")
	239	(DI "OI") (V2DI "OI")])
	240
	241	;; Register width from element mode
	242	(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
	243	(V4HI "P") (V8HI "q")
	244	(V2SI "P") (V4SI "q")
	245	(V2SF "P") (V4SF "q")
	246	(DI "P") (V2DI "q")])
	247
	248	;; Wider modes with the same number of elements.
	249	(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
	250
	251	;; Narrower modes with the same number of elements.
	252	(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
	253
0f38f229 TB	254	;; Narrower modes with double the number of elements.
	255	(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
	256	(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
	257
ceddf62c SN	258	;; Modes with half the number of equal-sized elements.
ceddf62c SN	259	(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
0f38f229	260	(V4SI "V2SI") (V4SF "V2SF") (V2DF "DF")
ceddf62c SN	261	(V2DI "DI")])
	262
	263	;; Same, but lower-case.
	264	(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
	265	(V4SI "v2si") (V4SF "v2sf")
	266	(V2DI "di")])
	267
	268	;; Modes with twice the number of equal-sized elements.
	269	(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
0f38f229	270	(V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
ceddf62c SN	271	(DI "V2DI")])
	272
	273	;; Same, but lower-case.
	274	(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
	275	(V2SI "v4si") (V2SF "v4sf")
	276	(DI "v2di")])
	277
	278	;; Modes with double-width elements.
	279	(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
	280	(V4HI "V2SI") (V8HI "V4SI")
	281	(V2SI "DI") (V4SI "V2DI")])
	282
	283	;; Double-sized modes with the same element size.
	284	;; Used for neon_vdup_lane, where the second operand is double-sized
	285	;; even when the first one is quad.
	286	(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
	287	(V4SI "V2SI") (V4SF "V2SF")
	288	(V8QI "V8QI") (V4HI "V4HI")
	289	(V2SI "V2SI") (V2SF "V2SF")])
	290
	291	;; Mode of result of comparison operations (and bit-select operand 1).
	292	(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
	293	(V4HI "V4HI") (V8HI "V8HI")
	294	(V2SI "V2SI") (V4SI "V4SI")
	295	(V2SF "V2SI") (V4SF "V4SI")
	296	(DI "DI") (V2DI "V2DI")])
	297
	298	;; Get element type from double-width mode, for operations where we
	299	;; don't care about signedness.
	300	(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
	301	(V4HI "i16") (V8HI "i16")
	302	(V2SI "i32") (V4SI "i32")
	303	(DI "i64") (V2DI "i64")
	304	(V2SF "f32") (V4SF "f32")])
	305
	306	;; Same, but for operations which work on signed values.
	307	(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
	308	(V4HI "s16") (V8HI "s16")
	309	(V2SI "s32") (V4SI "s32")
	310	(DI "s64") (V2DI "s64")
	311	(V2SF "f32") (V4SF "f32")])
	312
	313	;; Same, but for operations which work on unsigned values.
	314	(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
	315	(V4HI "u16") (V8HI "u16")
	316	(V2SI "u32") (V4SI "u32")
	317	(DI "u64") (V2DI "u64")
	318	(V2SF "f32") (V4SF "f32")])
	319
	320	;; Element types for extraction of unsigned scalars.
	321	(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
	322	(V4HI "u16") (V8HI "u16")
	323	(V2SI "32") (V4SI "32")
	324	(V2SF "32") (V4SF "32")])
	325
	326	(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
	327	(V4HI "16") (V8HI "16")
	328	(V2SI "32") (V4SI "32")
	329	(DI "64") (V2DI "64")
	330	(V2SF "32") (V4SF "32")])
	331
	332	;; Element sizes for duplicating ARM registers to all elements of a vector.
	333	(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
	334
335	;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
336	(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
337	(V4HI "TI") (V8HI "OI")
338	(V2SI "TI") (V4SI "OI")
339	(V2SF "TI") (V4SF "OI")
340	(DI "TI") (V2DI "OI")])
341
342	;; Same, but lower-case.
343	(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
344	(V4HI "ti") (V8HI "oi")
345	(V2SI "ti") (V4SI "oi")
346	(V2SF "ti") (V4SF "oi")
347	(DI "ti") (V2DI "oi")])
348
349	;; Extra suffix on some 64-bit insn names (to avoid collision with standard
350	;; names which we don't want to define).
351	(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
352	(V4HI "") (V8HI "")
353	(V2SI "") (V4SI "")
354	(V2SF "") (V4SF "")
355	(DI "_neon") (V2DI "")])
356
357
358	;; Scalars to be presented to scalar multiplication instructions
359	;; must satisfy the following constraints.
360	;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
361	;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
362
363	;; This mode attribute is used to obtain the correct register constraints.
364
365	(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
366	(V8HI "x") (V4SI "t") (V4SF "t")])
367
368	;; Predicates used for setting neon_type
369
370	(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
371	(V4HI "false") (V8HI "false")
372	(V2SI "false") (V4SI "false")
373	(V2SF "true") (V4SF "true")
374	(DI "false") (V2DI "false")])
375
376	(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
377	(V4HI "true") (V8HI "true")
378	(V2SI "false") (V4SI "false")
379	(V2SF "false") (V4SF "false")
380	(DI "false") (V2DI "false")])
381
382
383	(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
384	(V4HI "true") (V8HI "false")
385	(V2SI "true") (V4SI "false")
386	(V2SF "true") (V4SF "false")
387	(DI "true") (V2DI "false")])
388
389	(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
390	(V4HI "4") (V8HI "8")
391	(V2SI "2") (V4SI "4")
392	(V2SF "2") (V4SF "4")
0f38f229 TB	393	(DI "1") (V2DI "2")
0f38f229 TB	394	(DF "1") (V2DF "2")])
ceddf62c	395
46b57af1 TB	396	;; Same as V_widen, but lower-case.
	397	(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
	398
	399	;; Widen. Result is half the number of elements, but widened to double-width.
	400	(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
ceddf62c	401
da0a441d BS	402	;; Conditions to be used in extend<mode>di patterns.
	403	(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
	404	(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
	405	(QI "&& arm_arch6")])
8d4f1548	406	(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
c9cdcaa5 BS	407	(HI "nonimmediate_operand")
c9cdcaa5 BS	408	(QI "nonimmediate_operand")])
8d4f1548 RR	409	(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
	410	(HI "nonimmediate_operand")
	411	(QI "arm_reg_or_extendqisi_mem_op")])
	412	(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
	413	(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
da0a441d	414
655b30bf JB	415	;; Mode attributes used for fixed-point support.
	416	(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
	417	(V2UHA "16") (UHA "16")
	418	(V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
	419	(V2HA "16") (HA "16") (SQ "") (SA "")])
	420
36ba4aae IR	421	;; Mode attribute for vshll.
	422	(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
	423
ceddf62c SN	424	;;----------------------------------------------------------------------------
	425	;; Code attributes
	426	;;----------------------------------------------------------------------------
	427
	428	;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
	429	(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
	430	(umin "vmin") (umax "vmax")])
	431
	432	;; Signs of above, where relevant.
	433	(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
	434	(umax "u")])
	435
	436	(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
	437	(define_code_attr optab [(ltu "ltu") (geu "geu")])
46b57af1 TB	438
	439	;; Assembler mnemonics for signedness of widening operations.
	440	(define_code_attr US [(sign_extend "s") (zero_extend "u")])