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ceddf62c | 1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
5624e564 | 2 | ;; Copyright (C) 2010-2015 Free Software Foundation, Inc. |
ceddf62c SN |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;;---------------------------------------------------------------------------- | |
23 | ;; Mode iterators | |
24 | ;;---------------------------------------------------------------------------- | |
25 | ||
26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
27 | ;; some splits that are the same for all modes when operating on ARM | |
28 | ;; registers. | |
29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) | |
30 | ||
0f38f229 TB |
31 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
32 | ||
ceddf62c SN |
33 | ;; A list of integer modes that are up to one word long |
34 | (define_mode_iterator QHSI [QI HI SI]) | |
35 | ||
cfe52743 DAG |
36 | ;; A list of integer modes that are less than a word |
37 | (define_mode_iterator NARROW [QI HI]) | |
38 | ||
073a8998 | 39 | ;; A list of all the integer modes up to 64bit |
cfe52743 DAG |
40 | (define_mode_iterator QHSD [QI HI SI DI]) |
41 | ||
42 | ;; A list of the 32bit and 64bit integer modes | |
43 | (define_mode_iterator SIDI [SI DI]) | |
44 | ||
76f722f4 MGD |
45 | ;; A list of modes which the VFP unit can handle |
46 | (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) | |
47 | ||
ceddf62c SN |
48 | ;; Integer element sizes implemented by IWMMXT. |
49 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
50 | ||
8fd03515 XQ |
51 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
52 | ||
ceddf62c SN |
53 | ;; Integer element sizes for shifts. |
54 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
55 | ||
56 | ;; Integer and float modes supported by Neon and IWMMXT. | |
57 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
58 | ||
59 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
60 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
61 | ||
62 | ;; Integer modes supported by Neon and IWMMXT | |
63 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
64 | ||
65 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
66 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
67 | ||
68 | ;; Double-width vector modes. | |
69 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | |
70 | ||
71 | ;; Double-width vector modes plus 64-bit elements. | |
72 | (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) | |
73 | ||
74 | ;; Double-width vector modes without floating-point elements. | |
75 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
76 | ||
77 | ;; Quad-width vector modes. | |
78 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) | |
79 | ||
80 | ;; Quad-width vector modes plus 64-bit elements. | |
81 | (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) | |
82 | ||
83 | ;; Quad-width vector modes without floating-point elements. | |
84 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
85 | ||
86 | ;; Quad-width vector modes, with TImode added, for moves. | |
87 | (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) | |
88 | ||
89 | ;; Opaque structure types wider than TImode. | |
90 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
91 | ||
92 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
93 | (define_mode_iterator VTAB [TI EI OI]) | |
94 | ||
95 | ;; Widenable modes. | |
96 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
97 | ||
98 | ;; Narrowable modes. | |
99 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
100 | ||
101 | ;; All supported vector modes (except singleton DImode). | |
102 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) | |
103 | ||
104 | ;; All supported vector modes (except those with 64-bit integer elements). | |
105 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
106 | ||
107 | ;; Supported integer vector modes (not 64 bit elements). | |
108 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
109 | ||
110 | ;; Supported integer vector modes (not singleton DI) | |
111 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
112 | ||
113 | ;; Vector modes, including 64-bit integer elements. | |
114 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) | |
115 | ||
116 | ;; Vector modes including 64-bit integer elements, but no floats. | |
117 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
118 | ||
7a10ea9f KT |
119 | ;; Vector modes for H, S and D types. |
120 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
121 | ||
ceddf62c SN |
122 | ;; Vector modes for float->int conversions. |
123 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
124 | ||
125 | ;; Vector modes form int->float conversions. | |
126 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
127 | ||
128 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. | |
129 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
130 | ||
131 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
132 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
133 | ||
134 | ;; Above modes combined. | |
135 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
136 | ||
137 | ;; As VMD, but integer modes only. | |
138 | (define_mode_iterator VMDI [V4HI V2SI]) | |
139 | ||
140 | ;; As VMQ, but integer modes only. | |
141 | (define_mode_iterator VMQI [V8HI V4SI]) | |
142 | ||
143 | ;; Above modes combined. | |
144 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
145 | ||
146 | ;; Modes with 8-bit and 16-bit elements. | |
147 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
148 | ||
149 | ;; Modes with 8-bit elements. | |
150 | (define_mode_iterator VE [V8QI V16QI]) | |
151 | ||
152 | ;; Modes with 64-bit elements only. | |
153 | (define_mode_iterator V64 [DI V2DI]) | |
154 | ||
155 | ;; Modes with 32-bit elements only. | |
156 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
157 | ||
46b57af1 TB |
158 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
159 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
655b30bf JB |
160 | |
161 | ;; Iterators used for fixed-point support. | |
162 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
163 | ||
164 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
165 | ||
166 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
167 | ||
168 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
169 | ||
170 | (define_mode_iterator QMUL [HQ HA]) | |
171 | ||
94f0f2cc JG |
172 | ;; Modes for polynomial or float values. |
173 | (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) | |
174 | ||
ceddf62c SN |
175 | ;;---------------------------------------------------------------------------- |
176 | ;; Code iterators | |
177 | ;;---------------------------------------------------------------------------- | |
178 | ||
179 | ;; A list of condition codes used in compare instructions where | |
180 | ;; the carry flag from the addition is used instead of doing the | |
181 | ;; compare a second time. | |
182 | (define_code_iterator LTUGEU [ltu geu]) | |
183 | ||
381811fa KT |
184 | ;; The signed gt, ge comparisons |
185 | (define_code_iterator GTGE [gt ge]) | |
186 | ||
187 | ;; The unsigned gt, ge comparisons | |
188 | (define_code_iterator GTUGEU [gtu geu]) | |
189 | ||
190 | ;; Comparisons for vc<cmp> | |
191 | (define_code_iterator COMPARISONS [eq gt ge le lt]) | |
192 | ||
ceddf62c SN |
193 | ;; A list of ... |
194 | (define_code_iterator ior_xor [ior xor]) | |
195 | ||
196 | ;; Operations on two halves of a quadword vector. | |
197 | (define_code_iterator vqh_ops [plus smin smax umin umax]) | |
198 | ||
199 | ;; Operations on two halves of a quadword vector, | |
200 | ;; without unsigned variants (for use with *SFmode pattern). | |
201 | (define_code_iterator vqhs_ops [plus smin smax]) | |
202 | ||
46b57af1 TB |
203 | ;; A list of widening operators |
204 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c | 205 | |
3f2dc806 AS |
206 | ;; Right shifts |
207 | (define_code_iterator rshifts [ashiftrt lshiftrt]) | |
208 | ||
ababd936 KT |
209 | ;; Iterator for integer conversions |
210 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
211 | ||
004d3809 RE |
212 | ;; Binary operators whose second operand can be shifted. |
213 | (define_code_iterator shiftable_ops [plus minus ior xor and]) | |
214 | ||
215 | ;; plus and minus are the only shiftable_ops for which Thumb2 allows | |
216 | ;; a stack pointer opoerand. The minus operation is a candidate for an rsub | |
217 | ;; and hence only plus is supported. | |
218 | (define_code_attr t2_binop0 | |
219 | [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) | |
220 | ||
221 | ;; The instruction to use when a shiftable_ops has a shift operation as | |
222 | ;; its first operand. | |
223 | (define_code_attr arith_shift_insn | |
224 | [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) | |
225 | ||
381811fa KT |
226 | (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") |
227 | (gtu "gt") (geu "ge")]) | |
228 | ||
229 | (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) | |
230 | ||
1dd4fe1f KT |
231 | ;;---------------------------------------------------------------------------- |
232 | ;; Int iterators | |
233 | ;;---------------------------------------------------------------------------- | |
234 | ||
235 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
236 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
237 | ||
381811fa KT |
238 | (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE UNSPEC_VCLT UNSPEC_VCLE]) |
239 | ||
240 | (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) | |
241 | ||
ababd936 KT |
242 | (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) |
243 | ||
79739965 KT |
244 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
245 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
246 | ||
e9e67af1 KT |
247 | (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) |
248 | ||
94f0f2cc JG |
249 | (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) |
250 | ||
251 | (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) | |
252 | ||
253 | (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U | |
254 | UNSPEC_VHADD_S UNSPEC_VHADD_U]) | |
255 | ||
256 | (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) | |
257 | ||
258 | (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) | |
259 | ||
260 | (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) | |
261 | ||
262 | (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) | |
263 | ||
264 | (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) | |
265 | ||
266 | (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) | |
267 | ||
268 | (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) | |
269 | ||
270 | (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) | |
271 | ||
272 | (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) | |
273 | ||
274 | (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) | |
275 | ||
276 | (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) | |
277 | ||
278 | (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) | |
279 | ||
280 | (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) | |
281 | ||
282 | (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) | |
283 | ||
284 | (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) | |
285 | ||
286 | (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) | |
287 | ||
288 | (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) | |
289 | ||
290 | (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U | |
291 | UNSPEC_VMIN UNSPEC_VMIN_U]) | |
292 | ||
293 | (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) | |
294 | ||
295 | (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) | |
296 | ||
297 | (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) | |
298 | ||
299 | (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U | |
300 | UNSPEC_VPMIN UNSPEC_VPMIN_U]) | |
301 | ||
302 | (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) | |
303 | ||
304 | (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) | |
305 | ||
306 | (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) | |
307 | ||
308 | (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) | |
309 | ||
310 | (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) | |
311 | ||
312 | (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U | |
313 | UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) | |
314 | ||
315 | (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U | |
316 | UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) | |
317 | ||
318 | (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N | |
319 | UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) | |
320 | ||
321 | (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) | |
322 | ||
323 | (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N | |
324 | UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) | |
325 | ||
326 | (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) | |
327 | ||
328 | (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) | |
329 | ||
330 | (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) | |
331 | ||
332 | (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N | |
333 | UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) | |
334 | ||
582e2e43 KT |
335 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
336 | UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) | |
337 | ||
021b5e6b KT |
338 | (define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) |
339 | ||
340 | (define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE | |
341 | UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) | |
342 | ||
343 | (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H | |
344 | UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) | |
345 | ||
346 | (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M | |
347 | UNSPEC_SHA1P]) | |
348 | ||
ceddf62c SN |
349 | ;;---------------------------------------------------------------------------- |
350 | ;; Mode attributes | |
351 | ;;---------------------------------------------------------------------------- | |
352 | ||
353 | ;; Determine element size suffix from vector mode. | |
354 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
355 | ||
356 | ;; vtbl<n> suffix for NEON vector modes. | |
357 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
358 | ||
359 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
360 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
361 | (V4SI "V4SF") (V4SF "V4SI")]) | |
362 | ||
5bf4dcf2 DP |
363 | ;; As above but in lower case. |
364 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
365 | (V4SI "v4sf") (V4SF "v4si")]) | |
366 | ||
ceddf62c SN |
367 | ;; Define element mode for each vector mode. |
368 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
369 | (V4HI "HI") (V8HI "HI") | |
370 | (V2SI "SI") (V4SI "SI") | |
371 | (V2SF "SF") (V4SF "SF") | |
372 | (DI "DI") (V2DI "DI")]) | |
373 | ||
374 | ;; Element modes for vector extraction, padded up to register size. | |
375 | ||
376 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
377 | (V4HI "SI") (V8HI "SI") | |
378 | (V2SI "SI") (V4SI "SI") | |
379 | (V2SF "SF") (V4SF "SF") | |
380 | (DI "DI") (V2DI "DI")]) | |
381 | ||
382 | ;; Mode of pair of elements for each vector mode, to define transfer | |
383 | ;; size for structure lane/dup loads and stores. | |
6308e208 RS |
384 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
385 | (V4HI "SI") (V8HI "SI") | |
ceddf62c SN |
386 | (V2SI "V2SI") (V4SI "V2SI") |
387 | (V2SF "V2SF") (V4SF "V2SF") | |
388 | (DI "V2DI") (V2DI "V2DI")]) | |
389 | ||
390 | ;; Similar, for three elements. | |
6308e208 RS |
391 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
392 | (V4HI "BLK") (V8HI "BLK") | |
393 | (V2SI "BLK") (V4SI "BLK") | |
394 | (V2SF "BLK") (V4SF "BLK") | |
395 | (DI "EI") (V2DI "EI")]) | |
ceddf62c SN |
396 | |
397 | ;; Similar, for four elements. | |
398 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
6308e208 | 399 | (V4HI "V4HI") (V8HI "V4HI") |
ceddf62c SN |
400 | (V2SI "V4SI") (V4SI "V4SI") |
401 | (V2SF "V4SF") (V4SF "V4SF") | |
402 | (DI "OI") (V2DI "OI")]) | |
403 | ||
404 | ;; Register width from element mode | |
405 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
406 | (V4HI "P") (V8HI "q") | |
407 | (V2SI "P") (V4SI "q") | |
408 | (V2SF "P") (V4SF "q") | |
76f722f4 MGD |
409 | (DI "P") (V2DI "q") |
410 | (SF "") (DF "P")]) | |
ceddf62c SN |
411 | |
412 | ;; Wider modes with the same number of elements. | |
413 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
414 | ||
415 | ;; Narrower modes with the same number of elements. | |
416 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
417 | ||
0f38f229 TB |
418 | ;; Narrower modes with double the number of elements. |
419 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
420 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
421 | ||
ceddf62c SN |
422 | ;; Modes with half the number of equal-sized elements. |
423 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
0f38f229 | 424 | (V4SI "V2SI") (V4SF "V2SF") (V2DF "DF") |
ceddf62c SN |
425 | (V2DI "DI")]) |
426 | ||
427 | ;; Same, but lower-case. | |
428 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
429 | (V4SI "v2si") (V4SF "v2sf") | |
430 | (V2DI "di")]) | |
431 | ||
432 | ;; Modes with twice the number of equal-sized elements. | |
433 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
0f38f229 | 434 | (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF") |
ceddf62c SN |
435 | (DI "V2DI")]) |
436 | ||
437 | ;; Same, but lower-case. | |
438 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
439 | (V2SI "v4si") (V2SF "v4sf") | |
440 | (DI "v2di")]) | |
441 | ||
442 | ;; Modes with double-width elements. | |
443 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
444 | (V4HI "V2SI") (V8HI "V4SI") | |
445 | (V2SI "DI") (V4SI "V2DI")]) | |
446 | ||
447 | ;; Double-sized modes with the same element size. | |
448 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
449 | ;; even when the first one is quad. | |
450 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
451 | (V4SI "V2SI") (V4SF "V2SF") | |
452 | (V8QI "V8QI") (V4HI "V4HI") | |
453 | (V2SI "V2SI") (V2SF "V2SF")]) | |
454 | ||
455 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
456 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
457 | (V4HI "V4HI") (V8HI "V8HI") | |
458 | (V2SI "V2SI") (V4SI "V4SI") | |
459 | (V2SF "V2SI") (V4SF "V4SI") | |
460 | (DI "DI") (V2DI "V2DI")]) | |
461 | ||
f35c297f KT |
462 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
463 | (V4HI "v4hi") (V8HI "v8hi") | |
464 | (V2SI "v2si") (V4SI "v4si") | |
465 | (DI "di") (V2DI "v2di") | |
466 | (V2SF "v2si") (V4SF "v4si")]) | |
467 | ||
ceddf62c SN |
468 | ;; Get element type from double-width mode, for operations where we |
469 | ;; don't care about signedness. | |
470 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
471 | (V4HI "i16") (V8HI "i16") | |
472 | (V2SI "i32") (V4SI "i32") | |
473 | (DI "i64") (V2DI "i64") | |
76f722f4 MGD |
474 | (V2SF "f32") (V4SF "f32") |
475 | (SF "f32") (DF "f64")]) | |
ceddf62c SN |
476 | |
477 | ;; Same, but for operations which work on signed values. | |
478 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
479 | (V4HI "s16") (V8HI "s16") | |
480 | (V2SI "s32") (V4SI "s32") | |
481 | (DI "s64") (V2DI "s64") | |
482 | (V2SF "f32") (V4SF "f32")]) | |
483 | ||
484 | ;; Same, but for operations which work on unsigned values. | |
485 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
486 | (V4HI "u16") (V8HI "u16") | |
487 | (V2SI "u32") (V4SI "u32") | |
488 | (DI "u64") (V2DI "u64") | |
489 | (V2SF "f32") (V4SF "f32")]) | |
490 | ||
491 | ;; Element types for extraction of unsigned scalars. | |
492 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
493 | (V4HI "u16") (V8HI "u16") | |
494 | (V2SI "32") (V4SI "32") | |
495 | (V2SF "32") (V4SF "32")]) | |
496 | ||
497 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
498 | (V4HI "16") (V8HI "16") | |
499 | (V2SI "32") (V4SI "32") | |
500 | (DI "64") (V2DI "64") | |
501 | (V2SF "32") (V4SF "32")]) | |
502 | ||
f7379e5e JG |
503 | (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") |
504 | (V4HI "h") (V8HI "h") | |
505 | (V2SI "s") (V4SI "s") | |
506 | (DI "d") (V2DI "d") | |
507 | (V2SF "s") (V4SF "s")]) | |
508 | ||
ceddf62c SN |
509 | ;; Element sizes for duplicating ARM registers to all elements of a vector. |
510 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
511 | ||
512 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
513 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
514 | (V4HI "TI") (V8HI "OI") | |
515 | (V2SI "TI") (V4SI "OI") | |
516 | (V2SF "TI") (V4SF "OI") | |
517 | (DI "TI") (V2DI "OI")]) | |
518 | ||
519 | ;; Same, but lower-case. | |
520 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
521 | (V4HI "ti") (V8HI "oi") | |
522 | (V2SI "ti") (V4SI "oi") | |
523 | (V2SF "ti") (V4SF "oi") | |
524 | (DI "ti") (V2DI "oi")]) | |
525 | ||
526 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
527 | ;; names which we don't want to define). | |
528 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
529 | (V4HI "") (V8HI "") | |
530 | (V2SI "") (V4SI "") | |
531 | (V2SF "") (V4SF "") | |
532 | (DI "_neon") (V2DI "")]) | |
533 | ||
534 | ||
535 | ;; Scalars to be presented to scalar multiplication instructions | |
536 | ;; must satisfy the following constraints. | |
537 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
538 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
539 | ||
540 | ;; This mode attribute is used to obtain the correct register constraints. | |
541 | ||
542 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
543 | (V8HI "x") (V4SI "t") (V4SF "t")]) | |
544 | ||
003bb7f3 | 545 | ;; Predicates used for setting type for neon instructions |
ceddf62c SN |
546 | |
547 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
548 | (V4HI "false") (V8HI "false") | |
549 | (V2SI "false") (V4SI "false") | |
550 | (V2SF "true") (V4SF "true") | |
551 | (DI "false") (V2DI "false")]) | |
552 | ||
553 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
554 | (V4HI "true") (V8HI "true") | |
555 | (V2SI "false") (V4SI "false") | |
556 | (V2SF "false") (V4SF "false") | |
557 | (DI "false") (V2DI "false")]) | |
558 | ||
559 | ||
560 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
561 | (V4HI "true") (V8HI "false") | |
562 | (V2SI "true") (V4SI "false") | |
563 | (V2SF "true") (V4SF "false") | |
564 | (DI "true") (V2DI "false")]) | |
565 | ||
566 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
567 | (V4HI "4") (V8HI "8") | |
568 | (V2SI "2") (V4SI "4") | |
569 | (V2SF "2") (V4SF "4") | |
0f38f229 TB |
570 | (DI "1") (V2DI "2") |
571 | (DF "1") (V2DF "2")]) | |
ceddf62c | 572 | |
46b57af1 TB |
573 | ;; Same as V_widen, but lower-case. |
574 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
575 | ||
576 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
577 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c | 578 | |
da0a441d BS |
579 | ;; Conditions to be used in extend<mode>di patterns. |
580 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
581 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
582 | (QI "&& arm_arch6")]) | |
8d4f1548 | 583 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
c9cdcaa5 BS |
584 | (HI "nonimmediate_operand") |
585 | (QI "nonimmediate_operand")]) | |
8d4f1548 RR |
586 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
587 | (HI "nonimmediate_operand") | |
588 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
e0237780 GY |
589 | (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) |
590 | (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) | |
da0a441d | 591 | |
655b30bf JB |
592 | ;; Mode attributes used for fixed-point support. |
593 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
594 | (V2UHA "16") (UHA "16") | |
595 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
596 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
597 | ||
36ba4aae IR |
598 | ;; Mode attribute for vshll. |
599 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
600 | ||
1dd4fe1f | 601 | ;; Mode attributes used for VFP support. |
76f722f4 | 602 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
1dd4fe1f KT |
603 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
604 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
76f722f4 | 605 | |
f7379e5e JG |
606 | ;; Mode attribute used to build the "type" attribute. |
607 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
608 | (V4HI "") (V8HI "_q") | |
609 | (V2SI "") (V4SI "_q") | |
610 | (V2SF "") (V4SF "_q") | |
611 | (DI "") (V2DI "_q") | |
612 | (DF "") (V2DF "_q")]) | |
613 | ||
94f0f2cc JG |
614 | (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) |
615 | ||
ceddf62c SN |
616 | ;;---------------------------------------------------------------------------- |
617 | ;; Code attributes | |
618 | ;;---------------------------------------------------------------------------- | |
619 | ||
620 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. | |
621 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
622 | (umin "vmin") (umax "vmax")]) | |
623 | ||
f7379e5e JG |
624 | ;; Type attributes for vqh_ops and vqhs_ops iterators. |
625 | (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") | |
626 | (umin "minmax") (umax "minmax")]) | |
627 | ||
ceddf62c SN |
628 | ;; Signs of above, where relevant. |
629 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
630 | (umax "u")]) | |
631 | ||
632 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | |
633 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | |
46b57af1 TB |
634 | |
635 | ;; Assembler mnemonics for signedness of widening operations. | |
636 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
3f2dc806 | 637 | |
ababd936 KT |
638 | ;; Signedness suffix for float->fixed conversions. Empty for signed |
639 | ;; conversion. | |
640 | (define_code_attr su_optab [(fix "") (unsigned_fix "u")]) | |
641 | ||
642 | ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. | |
643 | (define_code_attr su [(fix "s") (unsigned_fix "u")]) | |
644 | ||
3f2dc806 AS |
645 | ;; Right shifts |
646 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
647 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
648 | ||
1dd4fe1f KT |
649 | ;;---------------------------------------------------------------------------- |
650 | ;; Int attributes | |
651 | ;;---------------------------------------------------------------------------- | |
652 | ||
94f0f2cc JG |
653 | ;; Mapping between vector UNSPEC operations and the signed ('s'), |
654 | ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. | |
655 | (define_int_attr sup [ | |
656 | (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") | |
657 | (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") | |
658 | (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") | |
659 | (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") | |
660 | (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") | |
661 | (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") | |
662 | (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") | |
663 | (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") | |
664 | (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") | |
665 | (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") | |
666 | (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") | |
667 | (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") | |
668 | (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") | |
669 | (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") | |
670 | (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") | |
671 | (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") | |
672 | (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") | |
673 | (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") | |
674 | (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") | |
675 | (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") | |
676 | (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") | |
677 | (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") | |
678 | (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") | |
679 | (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") | |
680 | (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") | |
681 | (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") | |
682 | (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") | |
683 | (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") | |
684 | (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") | |
685 | (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") | |
686 | (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") | |
687 | (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") | |
688 | (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") | |
689 | (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") | |
690 | (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") | |
691 | (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") | |
692 | (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") | |
693 | (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") | |
694 | (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") | |
695 | ||
696 | ]) | |
697 | ||
381811fa KT |
698 | (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") |
699 | (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") | |
700 | (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") | |
701 | (UNSPEC_VCAGT "gt")]) | |
702 | ||
94f0f2cc JG |
703 | (define_int_attr r [ |
704 | (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") | |
705 | (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") | |
706 | (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") | |
707 | (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") | |
708 | (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") | |
709 | (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") | |
710 | ]) | |
711 | ||
712 | (define_int_attr maxmin [ | |
713 | (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") | |
714 | (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") | |
715 | (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") | |
716 | (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") | |
717 | ]) | |
718 | ||
719 | (define_int_attr shift_op [ | |
720 | (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") | |
721 | (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") | |
722 | (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") | |
723 | (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") | |
724 | (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") | |
725 | (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") | |
726 | (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") | |
727 | (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") | |
728 | (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") | |
729 | (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") | |
730 | (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") | |
731 | (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") | |
732 | ]) | |
733 | ||
1dd4fe1f KT |
734 | ;; Standard names for floating point to integral rounding instructions. |
735 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
736 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
737 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
738 | ||
739 | ;; Suffixes for vrint instructions specifying rounding modes. | |
740 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
741 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
742 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
743 | ||
744 | ;; Some of the vrint instuctions are predicable. | |
745 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
746 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
747 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
79739965 | 748 | |
fca0efeb KT |
749 | (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") |
750 | (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") | |
751 | (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) | |
752 | ||
79739965 KT |
753 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") |
754 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
755 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) | |
582e2e43 KT |
756 | |
757 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") | |
758 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") | |
759 | (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) | |
760 | ||
761 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
762 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") | |
763 | (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) | |
764 | ||
021b5e6b KT |
765 | (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") |
766 | (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") | |
767 | (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") | |
768 | (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") | |
769 | (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") | |
770 | (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") | |
771 | (UNSPEC_SHA256H2 "sha256h2") | |
772 | (UNSPEC_SHA256SU1 "sha256su1")]) | |
773 | ||
774 | (define_int_attr crypto_type | |
b10baa95 KT |
775 | [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") |
776 | (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") | |
021b5e6b KT |
777 | (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") |
778 | (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") | |
779 | (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") | |
780 | (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") | |
781 | (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) | |
782 | ||
783 | (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") | |
784 | (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") | |
785 | (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") | |
786 | (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") | |
787 | (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") | |
788 | (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") | |
789 | (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) | |
790 | ||
791 | (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") | |
792 | (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") | |
793 | (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") | |
794 | (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") | |
795 | (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") | |
796 | (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") | |
797 | (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) | |
798 | ||
24d5b097 XG |
799 | ;; Both kinds of return insn. |
800 | (define_code_iterator returns [return simple_return]) | |
801 | (define_code_attr return_str [(return "") (simple_return "simple_")]) | |
802 | (define_code_attr return_simple_p [(return "false") (simple_return "true")]) | |
803 | (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") | |
804 | (simple_return " && use_simple_return_p ()")]) | |
805 | (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") | |
806 | (simple_return " && use_simple_return_p ()")]) |