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ceddf62c | 1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
d1e082c2 | 2 | ;; Copyright (C) 2010-2013 Free Software Foundation, Inc. |
ceddf62c SN |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;;---------------------------------------------------------------------------- | |
23 | ;; Mode iterators | |
24 | ;;---------------------------------------------------------------------------- | |
25 | ||
26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
27 | ;; some splits that are the same for all modes when operating on ARM | |
28 | ;; registers. | |
29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) | |
30 | ||
0f38f229 TB |
31 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
32 | ||
ceddf62c SN |
33 | ;; A list of integer modes that are up to one word long |
34 | (define_mode_iterator QHSI [QI HI SI]) | |
35 | ||
cfe52743 DAG |
36 | ;; A list of integer modes that are less than a word |
37 | (define_mode_iterator NARROW [QI HI]) | |
38 | ||
073a8998 | 39 | ;; A list of all the integer modes up to 64bit |
cfe52743 DAG |
40 | (define_mode_iterator QHSD [QI HI SI DI]) |
41 | ||
42 | ;; A list of the 32bit and 64bit integer modes | |
43 | (define_mode_iterator SIDI [SI DI]) | |
44 | ||
76f722f4 MGD |
45 | ;; A list of modes which the VFP unit can handle |
46 | (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) | |
47 | ||
ceddf62c SN |
48 | ;; Integer element sizes implemented by IWMMXT. |
49 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
50 | ||
8fd03515 XQ |
51 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
52 | ||
ceddf62c SN |
53 | ;; Integer element sizes for shifts. |
54 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
55 | ||
56 | ;; Integer and float modes supported by Neon and IWMMXT. | |
57 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
58 | ||
59 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
60 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
61 | ||
62 | ;; Integer modes supported by Neon and IWMMXT | |
63 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
64 | ||
65 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
66 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
67 | ||
68 | ;; Double-width vector modes. | |
69 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | |
70 | ||
71 | ;; Double-width vector modes plus 64-bit elements. | |
72 | (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) | |
73 | ||
74 | ;; Double-width vector modes without floating-point elements. | |
75 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
76 | ||
77 | ;; Quad-width vector modes. | |
78 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) | |
79 | ||
80 | ;; Quad-width vector modes plus 64-bit elements. | |
81 | (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) | |
82 | ||
83 | ;; Quad-width vector modes without floating-point elements. | |
84 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
85 | ||
86 | ;; Quad-width vector modes, with TImode added, for moves. | |
87 | (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) | |
88 | ||
89 | ;; Opaque structure types wider than TImode. | |
90 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
91 | ||
92 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
93 | (define_mode_iterator VTAB [TI EI OI]) | |
94 | ||
95 | ;; Widenable modes. | |
96 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
97 | ||
98 | ;; Narrowable modes. | |
99 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
100 | ||
101 | ;; All supported vector modes (except singleton DImode). | |
102 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) | |
103 | ||
104 | ;; All supported vector modes (except those with 64-bit integer elements). | |
105 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
106 | ||
107 | ;; Supported integer vector modes (not 64 bit elements). | |
108 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
109 | ||
110 | ;; Supported integer vector modes (not singleton DI) | |
111 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
112 | ||
113 | ;; Vector modes, including 64-bit integer elements. | |
114 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) | |
115 | ||
116 | ;; Vector modes including 64-bit integer elements, but no floats. | |
117 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
118 | ||
119 | ;; Vector modes for float->int conversions. | |
120 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
121 | ||
122 | ;; Vector modes form int->float conversions. | |
123 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
124 | ||
125 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. | |
126 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
127 | ||
128 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
129 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
130 | ||
131 | ;; Above modes combined. | |
132 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
133 | ||
134 | ;; As VMD, but integer modes only. | |
135 | (define_mode_iterator VMDI [V4HI V2SI]) | |
136 | ||
137 | ;; As VMQ, but integer modes only. | |
138 | (define_mode_iterator VMQI [V8HI V4SI]) | |
139 | ||
140 | ;; Above modes combined. | |
141 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
142 | ||
143 | ;; Modes with 8-bit and 16-bit elements. | |
144 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
145 | ||
146 | ;; Modes with 8-bit elements. | |
147 | (define_mode_iterator VE [V8QI V16QI]) | |
148 | ||
149 | ;; Modes with 64-bit elements only. | |
150 | (define_mode_iterator V64 [DI V2DI]) | |
151 | ||
152 | ;; Modes with 32-bit elements only. | |
153 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
154 | ||
46b57af1 TB |
155 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
156 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
655b30bf JB |
157 | |
158 | ;; Iterators used for fixed-point support. | |
159 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
160 | ||
161 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
162 | ||
163 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
164 | ||
165 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
166 | ||
167 | (define_mode_iterator QMUL [HQ HA]) | |
168 | ||
ceddf62c SN |
169 | ;;---------------------------------------------------------------------------- |
170 | ;; Code iterators | |
171 | ;;---------------------------------------------------------------------------- | |
172 | ||
173 | ;; A list of condition codes used in compare instructions where | |
174 | ;; the carry flag from the addition is used instead of doing the | |
175 | ;; compare a second time. | |
176 | (define_code_iterator LTUGEU [ltu geu]) | |
177 | ||
178 | ;; A list of ... | |
179 | (define_code_iterator ior_xor [ior xor]) | |
180 | ||
181 | ;; Operations on two halves of a quadword vector. | |
182 | (define_code_iterator vqh_ops [plus smin smax umin umax]) | |
183 | ||
184 | ;; Operations on two halves of a quadword vector, | |
185 | ;; without unsigned variants (for use with *SFmode pattern). | |
186 | (define_code_iterator vqhs_ops [plus smin smax]) | |
187 | ||
46b57af1 TB |
188 | ;; A list of widening operators |
189 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c | 190 | |
3f2dc806 AS |
191 | ;; Right shifts |
192 | (define_code_iterator rshifts [ashiftrt lshiftrt]) | |
193 | ||
1dd4fe1f KT |
194 | ;;---------------------------------------------------------------------------- |
195 | ;; Int iterators | |
196 | ;;---------------------------------------------------------------------------- | |
197 | ||
198 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
199 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
200 | ||
79739965 KT |
201 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
202 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
203 | ||
ceddf62c SN |
204 | ;;---------------------------------------------------------------------------- |
205 | ;; Mode attributes | |
206 | ;;---------------------------------------------------------------------------- | |
207 | ||
208 | ;; Determine element size suffix from vector mode. | |
209 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
210 | ||
211 | ;; vtbl<n> suffix for NEON vector modes. | |
212 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
213 | ||
214 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
215 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
216 | (V4SI "V4SF") (V4SF "V4SI")]) | |
217 | ||
5bf4dcf2 DP |
218 | ;; As above but in lower case. |
219 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
220 | (V4SI "v4sf") (V4SF "v4si")]) | |
221 | ||
ceddf62c SN |
222 | ;; Define element mode for each vector mode. |
223 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
224 | (V4HI "HI") (V8HI "HI") | |
225 | (V2SI "SI") (V4SI "SI") | |
226 | (V2SF "SF") (V4SF "SF") | |
227 | (DI "DI") (V2DI "DI")]) | |
228 | ||
229 | ;; Element modes for vector extraction, padded up to register size. | |
230 | ||
231 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
232 | (V4HI "SI") (V8HI "SI") | |
233 | (V2SI "SI") (V4SI "SI") | |
234 | (V2SF "SF") (V4SF "SF") | |
235 | (DI "DI") (V2DI "DI")]) | |
236 | ||
237 | ;; Mode of pair of elements for each vector mode, to define transfer | |
238 | ;; size for structure lane/dup loads and stores. | |
6308e208 RS |
239 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
240 | (V4HI "SI") (V8HI "SI") | |
ceddf62c SN |
241 | (V2SI "V2SI") (V4SI "V2SI") |
242 | (V2SF "V2SF") (V4SF "V2SF") | |
243 | (DI "V2DI") (V2DI "V2DI")]) | |
244 | ||
245 | ;; Similar, for three elements. | |
6308e208 RS |
246 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
247 | (V4HI "BLK") (V8HI "BLK") | |
248 | (V2SI "BLK") (V4SI "BLK") | |
249 | (V2SF "BLK") (V4SF "BLK") | |
250 | (DI "EI") (V2DI "EI")]) | |
ceddf62c SN |
251 | |
252 | ;; Similar, for four elements. | |
253 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
6308e208 | 254 | (V4HI "V4HI") (V8HI "V4HI") |
ceddf62c SN |
255 | (V2SI "V4SI") (V4SI "V4SI") |
256 | (V2SF "V4SF") (V4SF "V4SF") | |
257 | (DI "OI") (V2DI "OI")]) | |
258 | ||
259 | ;; Register width from element mode | |
260 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
261 | (V4HI "P") (V8HI "q") | |
262 | (V2SI "P") (V4SI "q") | |
263 | (V2SF "P") (V4SF "q") | |
76f722f4 MGD |
264 | (DI "P") (V2DI "q") |
265 | (SF "") (DF "P")]) | |
ceddf62c SN |
266 | |
267 | ;; Wider modes with the same number of elements. | |
268 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
269 | ||
270 | ;; Narrower modes with the same number of elements. | |
271 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
272 | ||
0f38f229 TB |
273 | ;; Narrower modes with double the number of elements. |
274 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
275 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
276 | ||
ceddf62c SN |
277 | ;; Modes with half the number of equal-sized elements. |
278 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
0f38f229 | 279 | (V4SI "V2SI") (V4SF "V2SF") (V2DF "DF") |
ceddf62c SN |
280 | (V2DI "DI")]) |
281 | ||
282 | ;; Same, but lower-case. | |
283 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
284 | (V4SI "v2si") (V4SF "v2sf") | |
285 | (V2DI "di")]) | |
286 | ||
287 | ;; Modes with twice the number of equal-sized elements. | |
288 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
0f38f229 | 289 | (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF") |
ceddf62c SN |
290 | (DI "V2DI")]) |
291 | ||
292 | ;; Same, but lower-case. | |
293 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
294 | (V2SI "v4si") (V2SF "v4sf") | |
295 | (DI "v2di")]) | |
296 | ||
297 | ;; Modes with double-width elements. | |
298 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
299 | (V4HI "V2SI") (V8HI "V4SI") | |
300 | (V2SI "DI") (V4SI "V2DI")]) | |
301 | ||
302 | ;; Double-sized modes with the same element size. | |
303 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
304 | ;; even when the first one is quad. | |
305 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
306 | (V4SI "V2SI") (V4SF "V2SF") | |
307 | (V8QI "V8QI") (V4HI "V4HI") | |
308 | (V2SI "V2SI") (V2SF "V2SF")]) | |
309 | ||
310 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
311 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
312 | (V4HI "V4HI") (V8HI "V8HI") | |
313 | (V2SI "V2SI") (V4SI "V4SI") | |
314 | (V2SF "V2SI") (V4SF "V4SI") | |
315 | (DI "DI") (V2DI "V2DI")]) | |
316 | ||
f35c297f KT |
317 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
318 | (V4HI "v4hi") (V8HI "v8hi") | |
319 | (V2SI "v2si") (V4SI "v4si") | |
320 | (DI "di") (V2DI "v2di") | |
321 | (V2SF "v2si") (V4SF "v4si")]) | |
322 | ||
ceddf62c SN |
323 | ;; Get element type from double-width mode, for operations where we |
324 | ;; don't care about signedness. | |
325 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
326 | (V4HI "i16") (V8HI "i16") | |
327 | (V2SI "i32") (V4SI "i32") | |
328 | (DI "i64") (V2DI "i64") | |
76f722f4 MGD |
329 | (V2SF "f32") (V4SF "f32") |
330 | (SF "f32") (DF "f64")]) | |
ceddf62c SN |
331 | |
332 | ;; Same, but for operations which work on signed values. | |
333 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
334 | (V4HI "s16") (V8HI "s16") | |
335 | (V2SI "s32") (V4SI "s32") | |
336 | (DI "s64") (V2DI "s64") | |
337 | (V2SF "f32") (V4SF "f32")]) | |
338 | ||
339 | ;; Same, but for operations which work on unsigned values. | |
340 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
341 | (V4HI "u16") (V8HI "u16") | |
342 | (V2SI "u32") (V4SI "u32") | |
343 | (DI "u64") (V2DI "u64") | |
344 | (V2SF "f32") (V4SF "f32")]) | |
345 | ||
346 | ;; Element types for extraction of unsigned scalars. | |
347 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
348 | (V4HI "u16") (V8HI "u16") | |
349 | (V2SI "32") (V4SI "32") | |
350 | (V2SF "32") (V4SF "32")]) | |
351 | ||
352 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
353 | (V4HI "16") (V8HI "16") | |
354 | (V2SI "32") (V4SI "32") | |
355 | (DI "64") (V2DI "64") | |
356 | (V2SF "32") (V4SF "32")]) | |
357 | ||
358 | ;; Element sizes for duplicating ARM registers to all elements of a vector. | |
359 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
360 | ||
361 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
362 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
363 | (V4HI "TI") (V8HI "OI") | |
364 | (V2SI "TI") (V4SI "OI") | |
365 | (V2SF "TI") (V4SF "OI") | |
366 | (DI "TI") (V2DI "OI")]) | |
367 | ||
368 | ;; Same, but lower-case. | |
369 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
370 | (V4HI "ti") (V8HI "oi") | |
371 | (V2SI "ti") (V4SI "oi") | |
372 | (V2SF "ti") (V4SF "oi") | |
373 | (DI "ti") (V2DI "oi")]) | |
374 | ||
375 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
376 | ;; names which we don't want to define). | |
377 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
378 | (V4HI "") (V8HI "") | |
379 | (V2SI "") (V4SI "") | |
380 | (V2SF "") (V4SF "") | |
381 | (DI "_neon") (V2DI "")]) | |
382 | ||
383 | ||
384 | ;; Scalars to be presented to scalar multiplication instructions | |
385 | ;; must satisfy the following constraints. | |
386 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
387 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
388 | ||
389 | ;; This mode attribute is used to obtain the correct register constraints. | |
390 | ||
391 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
392 | (V8HI "x") (V4SI "t") (V4SF "t")]) | |
393 | ||
394 | ;; Predicates used for setting neon_type | |
395 | ||
396 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
397 | (V4HI "false") (V8HI "false") | |
398 | (V2SI "false") (V4SI "false") | |
399 | (V2SF "true") (V4SF "true") | |
400 | (DI "false") (V2DI "false")]) | |
401 | ||
402 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
403 | (V4HI "true") (V8HI "true") | |
404 | (V2SI "false") (V4SI "false") | |
405 | (V2SF "false") (V4SF "false") | |
406 | (DI "false") (V2DI "false")]) | |
407 | ||
408 | ||
409 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
410 | (V4HI "true") (V8HI "false") | |
411 | (V2SI "true") (V4SI "false") | |
412 | (V2SF "true") (V4SF "false") | |
413 | (DI "true") (V2DI "false")]) | |
414 | ||
415 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
416 | (V4HI "4") (V8HI "8") | |
417 | (V2SI "2") (V4SI "4") | |
418 | (V2SF "2") (V4SF "4") | |
0f38f229 TB |
419 | (DI "1") (V2DI "2") |
420 | (DF "1") (V2DF "2")]) | |
ceddf62c | 421 | |
46b57af1 TB |
422 | ;; Same as V_widen, but lower-case. |
423 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
424 | ||
425 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
426 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c | 427 | |
da0a441d BS |
428 | ;; Conditions to be used in extend<mode>di patterns. |
429 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
430 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
431 | (QI "&& arm_arch6")]) | |
8d4f1548 | 432 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
c9cdcaa5 BS |
433 | (HI "nonimmediate_operand") |
434 | (QI "nonimmediate_operand")]) | |
8d4f1548 RR |
435 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
436 | (HI "nonimmediate_operand") | |
437 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
e0237780 GY |
438 | (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) |
439 | (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) | |
da0a441d | 440 | |
655b30bf JB |
441 | ;; Mode attributes used for fixed-point support. |
442 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
443 | (V2UHA "16") (UHA "16") | |
444 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
445 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
446 | ||
36ba4aae IR |
447 | ;; Mode attribute for vshll. |
448 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
449 | ||
1dd4fe1f | 450 | ;; Mode attributes used for VFP support. |
76f722f4 | 451 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
1dd4fe1f KT |
452 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
453 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
76f722f4 | 454 | |
ceddf62c SN |
455 | ;;---------------------------------------------------------------------------- |
456 | ;; Code attributes | |
457 | ;;---------------------------------------------------------------------------- | |
458 | ||
459 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. | |
460 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
461 | (umin "vmin") (umax "vmax")]) | |
462 | ||
463 | ;; Signs of above, where relevant. | |
464 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
465 | (umax "u")]) | |
466 | ||
467 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | |
468 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | |
46b57af1 TB |
469 | |
470 | ;; Assembler mnemonics for signedness of widening operations. | |
471 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
3f2dc806 AS |
472 | |
473 | ;; Right shifts | |
474 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
475 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
476 | ||
1dd4fe1f KT |
477 | ;;---------------------------------------------------------------------------- |
478 | ;; Int attributes | |
479 | ;;---------------------------------------------------------------------------- | |
480 | ||
481 | ;; Standard names for floating point to integral rounding instructions. | |
482 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
483 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
484 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
485 | ||
486 | ;; Suffixes for vrint instructions specifying rounding modes. | |
487 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
488 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
489 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
490 | ||
491 | ;; Some of the vrint instuctions are predicable. | |
492 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
493 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
494 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
79739965 KT |
495 | |
496 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") | |
497 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
498 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) |