projects / thirdparty / gcc.git / blame
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| ceddf62c | 1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
| 23a5b65a | 2 | ;; Copyright (C) 2010-2014 Free Software Foundation, Inc. |
| ceddf62c SN |
3 | ;; Contributed by ARM Ltd. |
| 4 | ;; | |
| 5 | ;; This file is part of GCC. | |
| 6 | ;; | |
| 7 | ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 | ;; under the terms of the GNU General Public License as published | |
| 9 | ;; by the Free Software Foundation; either version 3, or (at your | |
| 10 | ;; option) any later version. | |
| 11 | ||
| 12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | ;; License for more details. | |
| 16 | ||
| 17 | ;; You should have received a copy of the GNU General Public License | |
| 18 | ;; along with GCC; see the file COPYING3. If not see | |
| 19 | ;; <http://www.gnu.org/licenses/>. | |
| 20 | ||
| 21 | ||
| 22 | ;;---------------------------------------------------------------------------- | |
| 23 | ;; Mode iterators | |
| 24 | ;;---------------------------------------------------------------------------- | |
| 25 | ||
| 26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
| 27 | ;; some splits that are the same for all modes when operating on ARM | |
| 28 | ;; registers. | |
| 29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) | |
| 30 | ||
| 0f38f229 TB |
31 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
| 32 | ||
| ceddf62c SN |
33 | ;; A list of integer modes that are up to one word long |
| 34 | (define_mode_iterator QHSI [QI HI SI]) | |
| 35 | ||
| cfe52743 DAG |
36 | ;; A list of integer modes that are less than a word |
| 37 | (define_mode_iterator NARROW [QI HI]) | |
| 38 | ||
| 073a8998 | 39 | ;; A list of all the integer modes up to 64bit |
| cfe52743 DAG |
40 | (define_mode_iterator QHSD [QI HI SI DI]) |
| 41 | ||
| 42 | ;; A list of the 32bit and 64bit integer modes | |
| 43 | (define_mode_iterator SIDI [SI DI]) | |
| 44 | ||
| 76f722f4 MGD |
45 | ;; A list of modes which the VFP unit can handle |
| 46 | (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) | |
| 47 | ||
| ceddf62c SN |
48 | ;; Integer element sizes implemented by IWMMXT. |
| 49 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
| 50 | ||
| 8fd03515 XQ |
51 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
| 52 | ||
| ceddf62c SN |
53 | ;; Integer element sizes for shifts. |
| 54 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
| 55 | ||
| 56 | ;; Integer and float modes supported by Neon and IWMMXT. | |
| 57 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
| 58 | ||
| 59 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
| 60 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
| 61 | ||
| 62 | ;; Integer modes supported by Neon and IWMMXT | |
| 63 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
| 64 | ||
| 65 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
| 66 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
| 67 | ||
| 68 | ;; Double-width vector modes. | |
| 69 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | |
| 70 | ||
| 71 | ;; Double-width vector modes plus 64-bit elements. | |
| 72 | (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) | |
| 73 | ||
| 74 | ;; Double-width vector modes without floating-point elements. | |
| 75 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
| 76 | ||
| 77 | ;; Quad-width vector modes. | |
| 78 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) | |
| 79 | ||
| 80 | ;; Quad-width vector modes plus 64-bit elements. | |
| 81 | (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) | |
| 82 | ||
| 83 | ;; Quad-width vector modes without floating-point elements. | |
| 84 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
| 85 | ||
| 86 | ;; Quad-width vector modes, with TImode added, for moves. | |
| 87 | (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) | |
| 88 | ||
| 89 | ;; Opaque structure types wider than TImode. | |
| 90 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
| 91 | ||
| 92 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
| 93 | (define_mode_iterator VTAB [TI EI OI]) | |
| 94 | ||
| 95 | ;; Widenable modes. | |
| 96 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
| 97 | ||
| 98 | ;; Narrowable modes. | |
| 99 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
| 100 | ||
| 101 | ;; All supported vector modes (except singleton DImode). | |
| 102 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) | |
| 103 | ||
| 104 | ;; All supported vector modes (except those with 64-bit integer elements). | |
| 105 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
| 106 | ||
| 107 | ;; Supported integer vector modes (not 64 bit elements). | |
| 108 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
| 109 | ||
| 110 | ;; Supported integer vector modes (not singleton DI) | |
| 111 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
| 112 | ||
| 113 | ;; Vector modes, including 64-bit integer elements. | |
| 114 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) | |
| 115 | ||
| 116 | ;; Vector modes including 64-bit integer elements, but no floats. | |
| 117 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
| 118 | ||
| 7a10ea9f KT |
119 | ;; Vector modes for H, S and D types. |
| 120 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
| 121 | ||
| ceddf62c SN |
122 | ;; Vector modes for float->int conversions. |
| 123 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
| 124 | ||
| 125 | ;; Vector modes form int->float conversions. | |
| 126 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
| 127 | ||
| 128 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. | |
| 129 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
| 130 | ||
| 131 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
| 132 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
| 133 | ||
| 134 | ;; Above modes combined. | |
| 135 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
| 136 | ||
| 137 | ;; As VMD, but integer modes only. | |
| 138 | (define_mode_iterator VMDI [V4HI V2SI]) | |
| 139 | ||
| 140 | ;; As VMQ, but integer modes only. | |
| 141 | (define_mode_iterator VMQI [V8HI V4SI]) | |
| 142 | ||
| 143 | ;; Above modes combined. | |
| 144 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
| 145 | ||
| 146 | ;; Modes with 8-bit and 16-bit elements. | |
| 147 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
| 148 | ||
| 149 | ;; Modes with 8-bit elements. | |
| 150 | (define_mode_iterator VE [V8QI V16QI]) | |
| 151 | ||
| 152 | ;; Modes with 64-bit elements only. | |
| 153 | (define_mode_iterator V64 [DI V2DI]) | |
| 154 | ||
| 155 | ;; Modes with 32-bit elements only. | |
| 156 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
| 157 | ||
| 46b57af1 TB |
158 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
| 159 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
| 655b30bf JB |
160 | |
| 161 | ;; Iterators used for fixed-point support. | |
| 162 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
| 163 | ||
| 164 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
| 165 | ||
| 166 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
| 167 | ||
| 168 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
| 169 | ||
| 170 | (define_mode_iterator QMUL [HQ HA]) | |
| 171 | ||
| ceddf62c SN |
172 | ;;---------------------------------------------------------------------------- |
| 173 | ;; Code iterators | |
| 174 | ;;---------------------------------------------------------------------------- | |
| 175 | ||
| 176 | ;; A list of condition codes used in compare instructions where | |
| 177 | ;; the carry flag from the addition is used instead of doing the | |
| 178 | ;; compare a second time. | |
| 179 | (define_code_iterator LTUGEU [ltu geu]) | |
| 180 | ||
| 181 | ;; A list of ... | |
| 182 | (define_code_iterator ior_xor [ior xor]) | |
| 183 | ||
| 184 | ;; Operations on two halves of a quadword vector. | |
| 185 | (define_code_iterator vqh_ops [plus smin smax umin umax]) | |
| 186 | ||
| 187 | ;; Operations on two halves of a quadword vector, | |
| 188 | ;; without unsigned variants (for use with *SFmode pattern). | |
| 189 | (define_code_iterator vqhs_ops [plus smin smax]) | |
| 190 | ||
| 46b57af1 TB |
191 | ;; A list of widening operators |
| 192 | (define_code_iterator SE [sign_extend zero_extend]) | |
| ceddf62c | 193 | |
| 3f2dc806 AS |
194 | ;; Right shifts |
| 195 | (define_code_iterator rshifts [ashiftrt lshiftrt]) | |
| 196 | ||
| 1dd4fe1f KT |
197 | ;;---------------------------------------------------------------------------- |
| 198 | ;; Int iterators | |
| 199 | ;;---------------------------------------------------------------------------- | |
| 200 | ||
| 201 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
| 202 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
| 203 | ||
| 79739965 KT |
204 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
| 205 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
| 206 | ||
| 582e2e43 KT |
207 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
| 208 | UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) | |
| 209 | ||
| 021b5e6b KT |
210 | (define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) |
| 211 | ||
| 212 | (define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE | |
| 213 | UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) | |
| 214 | ||
| 215 | (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H | |
| 216 | UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) | |
| 217 | ||
| 218 | (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M | |
| 219 | UNSPEC_SHA1P]) | |
| 220 | ||
| ceddf62c SN |
221 | ;;---------------------------------------------------------------------------- |
| 222 | ;; Mode attributes | |
| 223 | ;;---------------------------------------------------------------------------- | |
| 224 | ||
| 225 | ;; Determine element size suffix from vector mode. | |
| 226 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
| 227 | ||
| 228 | ;; vtbl<n> suffix for NEON vector modes. | |
| 229 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
| 230 | ||
| 231 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
| 232 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
| 233 | (V4SI "V4SF") (V4SF "V4SI")]) | |
| 234 | ||
| 5bf4dcf2 DP |
235 | ;; As above but in lower case. |
| 236 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
| 237 | (V4SI "v4sf") (V4SF "v4si")]) | |
| 238 | ||
| ceddf62c SN |
239 | ;; Define element mode for each vector mode. |
| 240 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
| 241 | (V4HI "HI") (V8HI "HI") | |
| 242 | (V2SI "SI") (V4SI "SI") | |
| 243 | (V2SF "SF") (V4SF "SF") | |
| 244 | (DI "DI") (V2DI "DI")]) | |
| 245 | ||
| 246 | ;; Element modes for vector extraction, padded up to register size. | |
| 247 | ||
| 248 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
| 249 | (V4HI "SI") (V8HI "SI") | |
| 250 | (V2SI "SI") (V4SI "SI") | |
| 251 | (V2SF "SF") (V4SF "SF") | |
| 252 | (DI "DI") (V2DI "DI")]) | |
| 253 | ||
| 254 | ;; Mode of pair of elements for each vector mode, to define transfer | |
| 255 | ;; size for structure lane/dup loads and stores. | |
| 6308e208 RS |
256 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
| 257 | (V4HI "SI") (V8HI "SI") | |
| ceddf62c SN |
258 | (V2SI "V2SI") (V4SI "V2SI") |
| 259 | (V2SF "V2SF") (V4SF "V2SF") | |
| 260 | (DI "V2DI") (V2DI "V2DI")]) | |
| 261 | ||
| 262 | ;; Similar, for three elements. | |
| 6308e208 RS |
263 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
| 264 | (V4HI "BLK") (V8HI "BLK") | |
| 265 | (V2SI "BLK") (V4SI "BLK") | |
| 266 | (V2SF "BLK") (V4SF "BLK") | |
| 267 | (DI "EI") (V2DI "EI")]) | |
| ceddf62c SN |
268 | |
| 269 | ;; Similar, for four elements. | |
| 270 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
| 6308e208 | 271 | (V4HI "V4HI") (V8HI "V4HI") |
| ceddf62c SN |
272 | (V2SI "V4SI") (V4SI "V4SI") |
| 273 | (V2SF "V4SF") (V4SF "V4SF") | |
| 274 | (DI "OI") (V2DI "OI")]) | |
| 275 | ||
| 276 | ;; Register width from element mode | |
| 277 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
| 278 | (V4HI "P") (V8HI "q") | |
| 279 | (V2SI "P") (V4SI "q") | |
| 280 | (V2SF "P") (V4SF "q") | |
| 76f722f4 MGD |
281 | (DI "P") (V2DI "q") |
| 282 | (SF "") (DF "P")]) | |
| ceddf62c SN |
283 | |
| 284 | ;; Wider modes with the same number of elements. | |
| 285 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
| 286 | ||
| 287 | ;; Narrower modes with the same number of elements. | |
| 288 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
| 289 | ||
| 0f38f229 TB |
290 | ;; Narrower modes with double the number of elements. |
| 291 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
| 292 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
| 293 | ||
| ceddf62c SN |
294 | ;; Modes with half the number of equal-sized elements. |
| 295 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
| 0f38f229 | 296 | (V4SI "V2SI") (V4SF "V2SF") (V2DF "DF") |
| ceddf62c SN |
297 | (V2DI "DI")]) |
| 298 | ||
| 299 | ;; Same, but lower-case. | |
| 300 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
| 301 | (V4SI "v2si") (V4SF "v2sf") | |
| 302 | (V2DI "di")]) | |
| 303 | ||
| 304 | ;; Modes with twice the number of equal-sized elements. | |
| 305 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
| 0f38f229 | 306 | (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF") |
| ceddf62c SN |
307 | (DI "V2DI")]) |
| 308 | ||
| 309 | ;; Same, but lower-case. | |
| 310 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
| 311 | (V2SI "v4si") (V2SF "v4sf") | |
| 312 | (DI "v2di")]) | |
| 313 | ||
| 314 | ;; Modes with double-width elements. | |
| 315 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
| 316 | (V4HI "V2SI") (V8HI "V4SI") | |
| 317 | (V2SI "DI") (V4SI "V2DI")]) | |
| 318 | ||
| 319 | ;; Double-sized modes with the same element size. | |
| 320 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
| 321 | ;; even when the first one is quad. | |
| 322 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
| 323 | (V4SI "V2SI") (V4SF "V2SF") | |
| 324 | (V8QI "V8QI") (V4HI "V4HI") | |
| 325 | (V2SI "V2SI") (V2SF "V2SF")]) | |
| 326 | ||
| 327 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
| 328 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
| 329 | (V4HI "V4HI") (V8HI "V8HI") | |
| 330 | (V2SI "V2SI") (V4SI "V4SI") | |
| 331 | (V2SF "V2SI") (V4SF "V4SI") | |
| 332 | (DI "DI") (V2DI "V2DI")]) | |
| 333 | ||
| f35c297f KT |
334 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
| 335 | (V4HI "v4hi") (V8HI "v8hi") | |
| 336 | (V2SI "v2si") (V4SI "v4si") | |
| 337 | (DI "di") (V2DI "v2di") | |
| 338 | (V2SF "v2si") (V4SF "v4si")]) | |
| 339 | ||
| ceddf62c SN |
340 | ;; Get element type from double-width mode, for operations where we |
| 341 | ;; don't care about signedness. | |
| 342 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
| 343 | (V4HI "i16") (V8HI "i16") | |
| 344 | (V2SI "i32") (V4SI "i32") | |
| 345 | (DI "i64") (V2DI "i64") | |
| 76f722f4 MGD |
346 | (V2SF "f32") (V4SF "f32") |
| 347 | (SF "f32") (DF "f64")]) | |
| ceddf62c SN |
348 | |
| 349 | ;; Same, but for operations which work on signed values. | |
| 350 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
| 351 | (V4HI "s16") (V8HI "s16") | |
| 352 | (V2SI "s32") (V4SI "s32") | |
| 353 | (DI "s64") (V2DI "s64") | |
| 354 | (V2SF "f32") (V4SF "f32")]) | |
| 355 | ||
| 356 | ;; Same, but for operations which work on unsigned values. | |
| 357 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
| 358 | (V4HI "u16") (V8HI "u16") | |
| 359 | (V2SI "u32") (V4SI "u32") | |
| 360 | (DI "u64") (V2DI "u64") | |
| 361 | (V2SF "f32") (V4SF "f32")]) | |
| 362 | ||
| 363 | ;; Element types for extraction of unsigned scalars. | |
| 364 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
| 365 | (V4HI "u16") (V8HI "u16") | |
| 366 | (V2SI "32") (V4SI "32") | |
| 367 | (V2SF "32") (V4SF "32")]) | |
| 368 | ||
| 369 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
| 370 | (V4HI "16") (V8HI "16") | |
| 371 | (V2SI "32") (V4SI "32") | |
| 372 | (DI "64") (V2DI "64") | |
| 373 | (V2SF "32") (V4SF "32")]) | |
| 374 | ||
| f7379e5e JG |
375 | (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") |
| 376 | (V4HI "h") (V8HI "h") | |
| 377 | (V2SI "s") (V4SI "s") | |
| 378 | (DI "d") (V2DI "d") | |
| 379 | (V2SF "s") (V4SF "s")]) | |
| 380 | ||
| ceddf62c SN |
381 | ;; Element sizes for duplicating ARM registers to all elements of a vector. |
| 382 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
| 383 | ||
| 384 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
| 385 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
| 386 | (V4HI "TI") (V8HI "OI") | |
| 387 | (V2SI "TI") (V4SI "OI") | |
| 388 | (V2SF "TI") (V4SF "OI") | |
| 389 | (DI "TI") (V2DI "OI")]) | |
| 390 | ||
| 391 | ;; Same, but lower-case. | |
| 392 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
| 393 | (V4HI "ti") (V8HI "oi") | |
| 394 | (V2SI "ti") (V4SI "oi") | |
| 395 | (V2SF "ti") (V4SF "oi") | |
| 396 | (DI "ti") (V2DI "oi")]) | |
| 397 | ||
| 398 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
| 399 | ;; names which we don't want to define). | |
| 400 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
| 401 | (V4HI "") (V8HI "") | |
| 402 | (V2SI "") (V4SI "") | |
| 403 | (V2SF "") (V4SF "") | |
| 404 | (DI "_neon") (V2DI "")]) | |
| 405 | ||
| 406 | ||
| 407 | ;; Scalars to be presented to scalar multiplication instructions | |
| 408 | ;; must satisfy the following constraints. | |
| 409 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
| 410 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
| 411 | ||
| 412 | ;; This mode attribute is used to obtain the correct register constraints. | |
| 413 | ||
| 414 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
| 415 | (V8HI "x") (V4SI "t") (V4SF "t")]) | |
| 416 | ||
| 003bb7f3 | 417 | ;; Predicates used for setting type for neon instructions |
| ceddf62c SN |
418 | |
| 419 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
| 420 | (V4HI "false") (V8HI "false") | |
| 421 | (V2SI "false") (V4SI "false") | |
| 422 | (V2SF "true") (V4SF "true") | |
| 423 | (DI "false") (V2DI "false")]) | |
| 424 | ||
| 425 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
| 426 | (V4HI "true") (V8HI "true") | |
| 427 | (V2SI "false") (V4SI "false") | |
| 428 | (V2SF "false") (V4SF "false") | |
| 429 | (DI "false") (V2DI "false")]) | |
| 430 | ||
| 431 | ||
| 432 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
| 433 | (V4HI "true") (V8HI "false") | |
| 434 | (V2SI "true") (V4SI "false") | |
| 435 | (V2SF "true") (V4SF "false") | |
| 436 | (DI "true") (V2DI "false")]) | |
| 437 | ||
| 438 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
| 439 | (V4HI "4") (V8HI "8") | |
| 440 | (V2SI "2") (V4SI "4") | |
| 441 | (V2SF "2") (V4SF "4") | |
| 0f38f229 TB |
442 | (DI "1") (V2DI "2") |
| 443 | (DF "1") (V2DF "2")]) | |
| ceddf62c | 444 | |
| 46b57af1 TB |
445 | ;; Same as V_widen, but lower-case. |
| 446 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
| 447 | ||
| 448 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
| 449 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
| ceddf62c | 450 | |
| da0a441d BS |
451 | ;; Conditions to be used in extend<mode>di patterns. |
| 452 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
| 453 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
| 454 | (QI "&& arm_arch6")]) | |
| 8d4f1548 | 455 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
| c9cdcaa5 BS |
456 | (HI "nonimmediate_operand") |
| 457 | (QI "nonimmediate_operand")]) | |
| 8d4f1548 RR |
458 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
| 459 | (HI "nonimmediate_operand") | |
| 460 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
| e0237780 GY |
461 | (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) |
| 462 | (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) | |
| da0a441d | 463 | |
| 655b30bf JB |
464 | ;; Mode attributes used for fixed-point support. |
| 465 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
| 466 | (V2UHA "16") (UHA "16") | |
| 467 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
| 468 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
| 469 | ||
| 36ba4aae IR |
470 | ;; Mode attribute for vshll. |
| 471 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
| 472 | ||
| 1dd4fe1f | 473 | ;; Mode attributes used for VFP support. |
| 76f722f4 | 474 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
| 1dd4fe1f KT |
475 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
| 476 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
| 76f722f4 | 477 | |
| f7379e5e JG |
478 | ;; Mode attribute used to build the "type" attribute. |
| 479 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
| 480 | (V4HI "") (V8HI "_q") | |
| 481 | (V2SI "") (V4SI "_q") | |
| 482 | (V2SF "") (V4SF "_q") | |
| 483 | (DI "") (V2DI "_q") | |
| 484 | (DF "") (V2DF "_q")]) | |
| 485 | ||
| ceddf62c SN |
486 | ;;---------------------------------------------------------------------------- |
| 487 | ;; Code attributes | |
| 488 | ;;---------------------------------------------------------------------------- | |
| 489 | ||
| 490 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. | |
| 491 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
| 492 | (umin "vmin") (umax "vmax")]) | |
| 493 | ||
| f7379e5e JG |
494 | ;; Type attributes for vqh_ops and vqhs_ops iterators. |
| 495 | (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") | |
| 496 | (umin "minmax") (umax "minmax")]) | |
| 497 | ||
| ceddf62c SN |
498 | ;; Signs of above, where relevant. |
| 499 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
| 500 | (umax "u")]) | |
| 501 | ||
| 502 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | |
| 503 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | |
| 46b57af1 TB |
504 | |
| 505 | ;; Assembler mnemonics for signedness of widening operations. | |
| 506 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
| 3f2dc806 AS |
507 | |
| 508 | ;; Right shifts | |
| 509 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
| 510 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
| 511 | ||
| 1dd4fe1f KT |
512 | ;;---------------------------------------------------------------------------- |
| 513 | ;; Int attributes | |
| 514 | ;;---------------------------------------------------------------------------- | |
| 515 | ||
| 516 | ;; Standard names for floating point to integral rounding instructions. | |
| 517 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
| 518 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
| 519 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
| 520 | ||
| 521 | ;; Suffixes for vrint instructions specifying rounding modes. | |
| 522 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
| 523 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
| 524 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
| 525 | ||
| 526 | ;; Some of the vrint instuctions are predicable. | |
| 527 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
| 528 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
| 529 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
| 79739965 | 530 | |
| fca0efeb KT |
531 | (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") |
| 532 | (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") | |
| 533 | (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) | |
| 534 | ||
| 79739965 KT |
535 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") |
| 536 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
| 537 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) | |
| 582e2e43 KT |
538 | |
| 539 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") | |
| 540 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") | |
| 541 | (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) | |
| 542 | ||
| 543 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
| 544 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") | |
| 545 | (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) | |
| 546 | ||
| 021b5e6b KT |
547 | (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") |
| 548 | (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") | |
| 549 | (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") | |
| 550 | (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") | |
| 551 | (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") | |
| 552 | (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") | |
| 553 | (UNSPEC_SHA256H2 "sha256h2") | |
| 554 | (UNSPEC_SHA256SU1 "sha256su1")]) | |
| 555 | ||
| 556 | (define_int_attr crypto_type | |
| b10baa95 KT |
557 | [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") |
| 558 | (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") | |
| 021b5e6b KT |
559 | (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") |
| 560 | (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") | |
| 561 | (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") | |
| 562 | (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") | |
| 563 | (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) | |
| 564 | ||
| 565 | (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") | |
| 566 | (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") | |
| 567 | (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") | |
| 568 | (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") | |
| 569 | (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") | |
| 570 | (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") | |
| 571 | (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) | |
| 572 | ||
| 573 | (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") | |
| 574 | (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") | |
| 575 | (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") | |
| 576 | (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") | |
| 577 | (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") | |
| 578 | (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") | |
| 579 | (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) | |
| 580 | ||
| 24d5b097 XG |
581 | ;; Both kinds of return insn. |
| 582 | (define_code_iterator returns [return simple_return]) | |
| 583 | (define_code_attr return_str [(return "") (simple_return "simple_")]) | |
| 584 | (define_code_attr return_simple_p [(return "false") (simple_return "true")]) | |
| 585 | (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") | |
| 586 | (simple_return " && use_simple_return_p ()")]) | |
| 587 | (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") | |
| 588 | (simple_return " && use_simple_return_p ()")]) |