[thirdparty/gcc.git] / gcc / config / arm / iterators.md

;; Code and mode itertator and attribute definitions for the ARM backend
;; Copyright (C) 2010 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.


;;----------------------------------------------------------------------------
;; Mode iterators
;;----------------------------------------------------------------------------

;; A list of modes that are exactly 64 bits in size. This is used to expand
;; some splits that are the same for all modes when operating on ARM 
;; registers.
(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])

;; A list of integer modes that are up to one word long
(define_mode_iterator QHSI [QI HI SI])

;; Integer element sizes implemented by IWMMXT.
(define_mode_iterator VMMX [V2SI V4HI V8QI])

;; Integer element sizes for shifts.
(define_mode_iterator VSHFT [V4HI V2SI DI])

;; Integer and float modes supported by Neon and IWMMXT.
(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])

;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])

;; Integer modes supported by Neon and IWMMXT
(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])

;; Integer modes supported by Neon and IWMMXT, except V2DI
(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])

;; Double-width vector modes.
(define_mode_iterator VD [V8QI V4HI V2SI V2SF])

;; Double-width vector modes plus 64-bit elements.
(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])

;; Double-width vector modes without floating-point elements.
(define_mode_iterator VDI [V8QI V4HI V2SI])

;; Quad-width vector modes.
(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])

;; Quad-width vector modes plus 64-bit elements.
(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])

;; Quad-width vector modes without floating-point elements.
(define_mode_iterator VQI [V16QI V8HI V4SI])

;; Quad-width vector modes, with TImode added, for moves.
(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])

;; Opaque structure types wider than TImode.
(define_mode_iterator VSTRUCT [EI OI CI XI])

;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
(define_mode_iterator VTAB [TI EI OI])

;; Widenable modes.
(define_mode_iterator VW [V8QI V4HI V2SI])

;; Narrowable modes.
(define_mode_iterator VN [V8HI V4SI V2DI])

;; All supported vector modes (except singleton DImode).
(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])

;; All supported vector modes (except those with 64-bit integer elements).
(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])

;; Supported integer vector modes (not 64 bit elements).
(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])

;; Supported integer vector modes (not singleton DI)
(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])

;; Vector modes, including 64-bit integer elements.
(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])

;; Vector modes including 64-bit integer elements, but no floats.
(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])

;; Vector modes for float->int conversions.
(define_mode_iterator VCVTF [V2SF V4SF])

;; Vector modes form int->float conversions.
(define_mode_iterator VCVTI [V2SI V4SI])

;; Vector modes for doubleword multiply-accumulate, etc. insns.
(define_mode_iterator VMD [V4HI V2SI V2SF])

;; Vector modes for quadword multiply-accumulate, etc. insns.
(define_mode_iterator VMQ [V8HI V4SI V4SF])

;; Above modes combined.
(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])

;; As VMD, but integer modes only.
(define_mode_iterator VMDI [V4HI V2SI])

;; As VMQ, but integer modes only.
(define_mode_iterator VMQI [V8HI V4SI])

;; Above modes combined.
(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])

;; Modes with 8-bit and 16-bit elements.
(define_mode_iterator VX [V8QI V4HI V16QI V8HI])

;; Modes with 8-bit elements.
(define_mode_iterator VE [V8QI V16QI])

;; Modes with 64-bit elements only.
(define_mode_iterator V64 [DI V2DI])

;; Modes with 32-bit elements only.
(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])


;;----------------------------------------------------------------------------
;; Code iterators
;;----------------------------------------------------------------------------

;; A list of condition codes used in compare instructions where 
;; the carry flag from the addition is used instead of doing the 
;; compare a second time.
(define_code_iterator LTUGEU [ltu geu])

;; A list of ...
(define_code_iterator ior_xor [ior xor])

;; Operations on two halves of a quadword vector.
(define_code_iterator vqh_ops [plus smin smax umin umax])

;; Operations on two halves of a quadword vector,
;; without unsigned variants (for use with *SFmode pattern).
(define_code_iterator vqhs_ops [plus smin smax])


;;----------------------------------------------------------------------------
;; Mode attributes
;;----------------------------------------------------------------------------

;; Determine element size suffix from vector mode.
(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])

;; vtbl<n> suffix for NEON vector modes.
(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])

;; (Opposite) mode to convert to/from for NEON mode conversions.
(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
               (V4SI "V4SF") (V4SF "V4SI")])

;; Define element mode for each vector mode.
(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
              (V4HI "HI") (V8HI "HI")
                          (V2SI "SI") (V4SI "SI")
                          (V2SF "SF") (V4SF "SF")
                          (DI "DI")   (V2DI "DI")])

;; Element modes for vector extraction, padded up to register size.

(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
             (V4HI "SI") (V8HI "SI")
             (V2SI "SI") (V4SI "SI")
             (V2SF "SF") (V4SF "SF")
             (DI "DI") (V2DI "DI")])

;; Mode of pair of elements for each vector mode, to define transfer
;; size for structure lane/dup loads and stores.
(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
                  (V4HI "SI") (V8HI "SI")
                              (V2SI "V2SI") (V4SI "V2SI")
                              (V2SF "V2SF") (V4SF "V2SF")
                              (DI "V2DI")   (V2DI "V2DI")])

;; Similar, for three elements.
;; ??? Should we define extra modes so that sizes of all three-element
;; accesses can be accurately represented?
(define_mode_attr V_three_elem [(V8QI "SI")   (V16QI "SI")
                    (V4HI "V4HI") (V8HI "V4HI")
                                (V2SI "V4SI") (V4SI "V4SI")
                                (V2SF "V4SF") (V4SF "V4SF")
                                (DI "EI")     (V2DI "EI")])

;; Similar, for four elements.
(define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
                   (V4HI "V4HI") (V8HI "V4HI")
                               (V2SI "V4SI") (V4SI "V4SI")
                               (V2SF "V4SF") (V4SF "V4SF")
                               (DI "OI")     (V2DI "OI")])

;; Register width from element mode
(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
                         (V4HI "P") (V8HI  "q")
                         (V2SI "P") (V4SI  "q")
                         (V2SF "P") (V4SF  "q")
                         (DI   "P") (V2DI  "q")])

;; Wider modes with the same number of elements.
(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])

;; Narrower modes with the same number of elements.
(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])

;; Modes with half the number of equal-sized elements.
(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
              (V4SI  "V2SI") (V4SF "V2SF")
                          (V2DI "DI")])

;; Same, but lower-case.
(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
              (V4SI  "v2si") (V4SF "v2sf")
                          (V2DI "di")])

;; Modes with twice the number of equal-sized elements.
(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
                (V2SI "V4SI") (V2SF "V4SF")
                            (DI "V2DI")])

;; Same, but lower-case.
(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
                (V2SI "v4si") (V2SF "v4sf")
                            (DI "v2di")])

;; Modes with double-width elements.
(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
                  (V4HI "V2SI") (V8HI "V4SI")
                  (V2SI "DI")   (V4SI "V2DI")])

;; Double-sized modes with the same element size.
;; Used for neon_vdup_lane, where the second operand is double-sized
;; even when the first one is quad.
(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
                                        (V4SI "V2SI") (V4SF "V2SF")
                                        (V8QI "V8QI") (V4HI "V4HI")
                                        (V2SI "V2SI") (V2SF "V2SF")])

;; Mode of result of comparison operations (and bit-select operand 1).
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
                    (V4HI "V4HI") (V8HI  "V8HI")
                                (V2SI "V2SI") (V4SI  "V4SI")
                                (V2SF "V2SI") (V4SF  "V4SI")
                                (DI   "DI")   (V2DI  "V2DI")])

;; Get element type from double-width mode, for operations where we 
;; don't care about signedness.
(define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
                 (V4HI "i16") (V8HI  "i16")
                             (V2SI "i32") (V4SI  "i32")
                             (DI   "i64") (V2DI  "i64")
                 (V2SF "f32") (V4SF  "f32")])

;; Same, but for operations which work on signed values.
(define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
                (V4HI "s16") (V8HI  "s16")
                            (V2SI "s32") (V4SI  "s32")
                            (DI   "s64") (V2DI  "s64")
                (V2SF "f32") (V4SF  "f32")])

;; Same, but for operations which work on unsigned values.
(define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
                (V4HI "u16") (V8HI  "u16")
                            (V2SI "u32") (V4SI  "u32")
                            (DI   "u64") (V2DI  "u64")
                            (V2SF "f32") (V4SF  "f32")])

;; Element types for extraction of unsigned scalars.
(define_mode_attr V_uf_sclr [(V8QI "u8")  (V16QI "u8")
                 (V4HI "u16") (V8HI "u16")
                             (V2SI "32") (V4SI "32")
                             (V2SF "32") (V4SF "32")])

(define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
                 (V4HI "16") (V8HI  "16")
                             (V2SI "32") (V4SI  "32")
                             (DI   "64") (V2DI  "64")
                 (V2SF "32") (V4SF  "32")])

;; Element sizes for duplicating ARM registers to all elements of a vector.
(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])

;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
              (V4HI "TI") (V8HI  "OI")
                          (V2SI "TI") (V4SI  "OI")
                          (V2SF "TI") (V4SF  "OI")
                          (DI   "TI") (V2DI  "OI")])

;; Same, but lower-case.
(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
              (V4HI "ti") (V8HI  "oi")
                          (V2SI "ti") (V4SI  "oi")
                          (V2SF "ti") (V4SF  "oi")
                          (DI   "ti") (V2DI  "oi")])

;; Extra suffix on some 64-bit insn names (to avoid collision with standard
;; names which we don't want to define).
(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
                           (V4HI "") (V8HI "")
                           (V2SI "") (V4SI "")
                           (V2SF "") (V4SF "")
                           (DI "_neon") (V2DI "")])


;; Scalars to be presented to scalar multiplication instructions
;; must satisfy the following constraints.
;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.

;; This mode attribute is used to obtain the correct register constraints.

(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
                                         (V8HI "x") (V4SI "t") (V4SF "t")])

;; Predicates used for setting neon_type

(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
                 (V4HI "false") (V8HI "false")
                 (V2SI "false") (V4SI "false")
                 (V2SF "true") (V4SF "true")
                 (DI "false") (V2DI "false")])

(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
                   (V4HI "true") (V8HI "true")
                   (V2SI "false") (V4SI "false")
                   (V2SF "false") (V4SF "false")
                   (DI "false") (V2DI "false")])


(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
                            (V4HI "true") (V8HI  "false")
                            (V2SI "true") (V4SI  "false")
                            (V2SF "true") (V4SF  "false")
                            (DI   "true") (V2DI  "false")])

(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
                                 (V4HI "4") (V8HI "8")
                                 (V2SI "2") (V4SI "4")
                                 (V2SF "2") (V4SF "4")
                                 (DI "1")   (V2DI "2")])


;;----------------------------------------------------------------------------
;; Code attributes
;;----------------------------------------------------------------------------

;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
                (umin "vmin") (umax "vmax")])

;; Signs of above, where relevant.
(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
                (umax "u")])

(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
(define_code_attr optab [(ltu "ltu") (geu "geu")])
Commit	Line	Data
ceddf62c SN	1	;; Code and mode itertator and attribute definitions for the ARM backend
	2	;; Copyright (C) 2010 Free Software Foundation, Inc.
	3	;; Contributed by ARM Ltd.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
	9	;; by the Free Software Foundation; either version 3, or (at your
	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20
	21
	22	;;----------------------------------------------------------------------------
	23	;; Mode iterators
	24	;;----------------------------------------------------------------------------
	25
	26	;; A list of modes that are exactly 64 bits in size. This is used to expand
	27	;; some splits that are the same for all modes when operating on ARM
	28	;; registers.
	29	(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
	30
	31	;; A list of integer modes that are up to one word long
	32	(define_mode_iterator QHSI [QI HI SI])
	33
	34	;; Integer element sizes implemented by IWMMXT.
	35	(define_mode_iterator VMMX [V2SI V4HI V8QI])
	36
	37	;; Integer element sizes for shifts.
	38	(define_mode_iterator VSHFT [V4HI V2SI DI])
	39
	40	;; Integer and float modes supported by Neon and IWMMXT.
	41	(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
	42
	43	;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
	44	(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
	45
	46	;; Integer modes supported by Neon and IWMMXT
	47	(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
	48
	49	;; Integer modes supported by Neon and IWMMXT, except V2DI
	50	(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
	51
	52	;; Double-width vector modes.
	53	(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
	54
	55	;; Double-width vector modes plus 64-bit elements.
	56	(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
	57
	58	;; Double-width vector modes without floating-point elements.
	59	(define_mode_iterator VDI [V8QI V4HI V2SI])
	60
	61	;; Quad-width vector modes.
	62	(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
	63
	64	;; Quad-width vector modes plus 64-bit elements.
65	(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
66
67	;; Quad-width vector modes without floating-point elements.
68	(define_mode_iterator VQI [V16QI V8HI V4SI])
69
70	;; Quad-width vector modes, with TImode added, for moves.
71	(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
72
73	;; Opaque structure types wider than TImode.
74	(define_mode_iterator VSTRUCT [EI OI CI XI])
75
76	;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
77	(define_mode_iterator VTAB [TI EI OI])
78
79	;; Widenable modes.
80	(define_mode_iterator VW [V8QI V4HI V2SI])
81
82	;; Narrowable modes.
83	(define_mode_iterator VN [V8HI V4SI V2DI])
84
85	;; All supported vector modes (except singleton DImode).
86	(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
87
88	;; All supported vector modes (except those with 64-bit integer elements).
89	(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
90
91	;; Supported integer vector modes (not 64 bit elements).
92	(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
93
94	;; Supported integer vector modes (not singleton DI)
95	(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
96
97	;; Vector modes, including 64-bit integer elements.
98	(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
99
100	;; Vector modes including 64-bit integer elements, but no floats.
101	(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
102
103	;; Vector modes for float->int conversions.
104	(define_mode_iterator VCVTF [V2SF V4SF])
105
106	;; Vector modes form int->float conversions.
107	(define_mode_iterator VCVTI [V2SI V4SI])
108
109	;; Vector modes for doubleword multiply-accumulate, etc. insns.
110	(define_mode_iterator VMD [V4HI V2SI V2SF])
111
112	;; Vector modes for quadword multiply-accumulate, etc. insns.
113	(define_mode_iterator VMQ [V8HI V4SI V4SF])
114
115	;; Above modes combined.
116	(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
117
118	;; As VMD, but integer modes only.
119	(define_mode_iterator VMDI [V4HI V2SI])
120
121	;; As VMQ, but integer modes only.
122	(define_mode_iterator VMQI [V8HI V4SI])
123
124	;; Above modes combined.
125	(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
126
127	;; Modes with 8-bit and 16-bit elements.
128	(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
129
130	;; Modes with 8-bit elements.
131	(define_mode_iterator VE [V8QI V16QI])
132
133	;; Modes with 64-bit elements only.
134	(define_mode_iterator V64 [DI V2DI])
135
136	;; Modes with 32-bit elements only.
137	(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
138
139
140	;;----------------------------------------------------------------------------
141	;; Code iterators
142	;;----------------------------------------------------------------------------
143
144	;; A list of condition codes used in compare instructions where
145	;; the carry flag from the addition is used instead of doing the
146	;; compare a second time.
147	(define_code_iterator LTUGEU [ltu geu])
148
149	;; A list of ...
150	(define_code_iterator ior_xor [ior xor])
151
152	;; Operations on two halves of a quadword vector.
153	(define_code_iterator vqh_ops [plus smin smax umin umax])
154
155	;; Operations on two halves of a quadword vector,
156	;; without unsigned variants (for use with *SFmode pattern).
157	(define_code_iterator vqhs_ops [plus smin smax])
158
159
160	;;----------------------------------------------------------------------------
161	;; Mode attributes
162	;;----------------------------------------------------------------------------
163
164	;; Determine element size suffix from vector mode.
165	(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
166
167	;; vtbl<n> suffix for NEON vector modes.
168	(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
169
170	;; (Opposite) mode to convert to/from for NEON mode conversions.
171	(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
172	(V4SI "V4SF") (V4SF "V4SI")])
173
174	;; Define element mode for each vector mode.
175	(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
176	(V4HI "HI") (V8HI "HI")
177	(V2SI "SI") (V4SI "SI")
178	(V2SF "SF") (V4SF "SF")
179	(DI "DI") (V2DI "DI")])
180
181	;; Element modes for vector extraction, padded up to register size.
182
183	(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
184	(V4HI "SI") (V8HI "SI")
185	(V2SI "SI") (V4SI "SI")
186	(V2SF "SF") (V4SF "SF")
187	(DI "DI") (V2DI "DI")])
188
189	;; Mode of pair of elements for each vector mode, to define transfer
190	;; size for structure lane/dup loads and stores.
191	(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
192	(V4HI "SI") (V8HI "SI")
193	(V2SI "V2SI") (V4SI "V2SI")
194	(V2SF "V2SF") (V4SF "V2SF")
195	(DI "V2DI") (V2DI "V2DI")])
196
197	;; Similar, for three elements.
198	;; ??? Should we define extra modes so that sizes of all three-element
199	;; accesses can be accurately represented?
200	(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
201	(V4HI "V4HI") (V8HI "V4HI")
202	(V2SI "V4SI") (V4SI "V4SI")
203	(V2SF "V4SF") (V4SF "V4SF")
204	(DI "EI") (V2DI "EI")])
205
206	;; Similar, for four elements.
207	(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
208	(V4HI "V4HI") (V8HI "V4HI")
209	(V2SI "V4SI") (V4SI "V4SI")
210	(V2SF "V4SF") (V4SF "V4SF")
211	(DI "OI") (V2DI "OI")])
212
213	;; Register width from element mode
214	(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
215	(V4HI "P") (V8HI "q")
216	(V2SI "P") (V4SI "q")
217	(V2SF "P") (V4SF "q")
218	(DI "P") (V2DI "q")])
219
220	;; Wider modes with the same number of elements.
221	(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
222
223	;; Narrower modes with the same number of elements.
224	(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
225
226	;; Modes with half the number of equal-sized elements.
227	(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
228	(V4SI "V2SI") (V4SF "V2SF")
229	(V2DI "DI")])
230
231	;; Same, but lower-case.
232	(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
233	(V4SI "v2si") (V4SF "v2sf")
234	(V2DI "di")])
235
236	;; Modes with twice the number of equal-sized elements.
237	(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
238	(V2SI "V4SI") (V2SF "V4SF")
239	(DI "V2DI")])
240
241	;; Same, but lower-case.
242	(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
243	(V2SI "v4si") (V2SF "v4sf")
244	(DI "v2di")])
245
246	;; Modes with double-width elements.
247	(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
248	(V4HI "V2SI") (V8HI "V4SI")
249	(V2SI "DI") (V4SI "V2DI")])
250
251	;; Double-sized modes with the same element size.
252	;; Used for neon_vdup_lane, where the second operand is double-sized
253	;; even when the first one is quad.
254	(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
255	(V4SI "V2SI") (V4SF "V2SF")
256	(V8QI "V8QI") (V4HI "V4HI")
257	(V2SI "V2SI") (V2SF "V2SF")])
258
259	;; Mode of result of comparison operations (and bit-select operand 1).
260	(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
261	(V4HI "V4HI") (V8HI "V8HI")
262	(V2SI "V2SI") (V4SI "V4SI")
263	(V2SF "V2SI") (V4SF "V4SI")
264	(DI "DI") (V2DI "V2DI")])
265
266	;; Get element type from double-width mode, for operations where we
267	;; don't care about signedness.
268	(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
269	(V4HI "i16") (V8HI "i16")
270	(V2SI "i32") (V4SI "i32")
271	(DI "i64") (V2DI "i64")
272	(V2SF "f32") (V4SF "f32")])
273
274	;; Same, but for operations which work on signed values.
275	(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
276	(V4HI "s16") (V8HI "s16")
277	(V2SI "s32") (V4SI "s32")
278	(DI "s64") (V2DI "s64")
279	(V2SF "f32") (V4SF "f32")])
280
281	;; Same, but for operations which work on unsigned values.
282	(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
283	(V4HI "u16") (V8HI "u16")
284	(V2SI "u32") (V4SI "u32")
285	(DI "u64") (V2DI "u64")
286	(V2SF "f32") (V4SF "f32")])
287
288	;; Element types for extraction of unsigned scalars.
289	(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
290	(V4HI "u16") (V8HI "u16")
291	(V2SI "32") (V4SI "32")
292	(V2SF "32") (V4SF "32")])
293
294	(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
295	(V4HI "16") (V8HI "16")
296	(V2SI "32") (V4SI "32")
297	(DI "64") (V2DI "64")
298	(V2SF "32") (V4SF "32")])
299
300	;; Element sizes for duplicating ARM registers to all elements of a vector.
301	(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
302
303	;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
304	(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
305	(V4HI "TI") (V8HI "OI")
306	(V2SI "TI") (V4SI "OI")
307	(V2SF "TI") (V4SF "OI")
308	(DI "TI") (V2DI "OI")])
309
310	;; Same, but lower-case.
311	(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
312	(V4HI "ti") (V8HI "oi")
313	(V2SI "ti") (V4SI "oi")
314	(V2SF "ti") (V4SF "oi")
315	(DI "ti") (V2DI "oi")])
316
317	;; Extra suffix on some 64-bit insn names (to avoid collision with standard
318	;; names which we don't want to define).
319	(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
320	(V4HI "") (V8HI "")
321	(V2SI "") (V4SI "")
322	(V2SF "") (V4SF "")
323	(DI "_neon") (V2DI "")])
324
325
326	;; Scalars to be presented to scalar multiplication instructions
327	;; must satisfy the following constraints.
328	;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
329	;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
330
331	;; This mode attribute is used to obtain the correct register constraints.
332
333	(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
334	(V8HI "x") (V4SI "t") (V4SF "t")])
335
336	;; Predicates used for setting neon_type
337
338	(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
339	(V4HI "false") (V8HI "false")
340	(V2SI "false") (V4SI "false")
341	(V2SF "true") (V4SF "true")
342	(DI "false") (V2DI "false")])
343
344	(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
345	(V4HI "true") (V8HI "true")
346	(V2SI "false") (V4SI "false")
347	(V2SF "false") (V4SF "false")
348	(DI "false") (V2DI "false")])
349
350
351	(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
352	(V4HI "true") (V8HI "false")
353	(V2SI "true") (V4SI "false")
354	(V2SF "true") (V4SF "false")
355	(DI "true") (V2DI "false")])
356
357	(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
358	(V4HI "4") (V8HI "8")
359	(V2SI "2") (V4SI "4")
360	(V2SF "2") (V4SF "4")
361	(DI "1") (V2DI "2")])
362
363
364	;;----------------------------------------------------------------------------
365	;; Code attributes
366	;;----------------------------------------------------------------------------
367
368	;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
369	(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
370	(umin "vmin") (umax "vmax")])
371
372	;; Signs of above, where relevant.
373	(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
374	(umax "u")])
375
376	(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
377	(define_code_attr optab [(ltu "ltu") (geu "geu")])