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0c1eb901 | 1 | |
ceddf62c | 2 | ;; Code and mode itertator and attribute definitions for the ARM backend |
a945c346 | 3 | ;; Copyright (C) 2010-2024 Free Software Foundation, Inc. |
ceddf62c SN |
4 | ;; Contributed by ARM Ltd. |
5 | ;; | |
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify it | |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 3, or (at your | |
11 | ;; option) any later version. | |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | ||
23 | ;;---------------------------------------------------------------------------- | |
24 | ;; Mode iterators | |
25 | ;;---------------------------------------------------------------------------- | |
26 | ||
27 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
2a26aed6 | 28 | ;; some splits that are the same for all modes when operating on ARM |
ceddf62c | 29 | ;; registers. |
2a26aed6 | 30 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF]) |
ceddf62c | 31 | |
2e87b2f4 SMW |
32 | ;; Additional definition of ANY64 that also includes the special V4BF mode. |
33 | ;; BFmode is allowed only on define_split between ARM registers. | |
34 | (define_mode_iterator ANY64_BF [DI DF V8QI V4HI V4BF V4HF V2SI V2SF]) | |
35 | ||
0f38f229 TB |
36 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
37 | ||
ceddf62c SN |
38 | ;; A list of integer modes that are up to one word long |
39 | (define_mode_iterator QHSI [QI HI SI]) | |
40 | ||
a46b23e1 RR |
41 | ;; A list of integer modes that are half and one word long |
42 | (define_mode_iterator HSI [HI SI]) | |
43 | ||
cfe52743 DAG |
44 | ;; A list of integer modes that are less than a word |
45 | (define_mode_iterator NARROW [QI HI]) | |
46 | ||
073a8998 | 47 | ;; A list of all the integer modes up to 64bit |
cfe52743 DAG |
48 | (define_mode_iterator QHSD [QI HI SI DI]) |
49 | ||
50 | ;; A list of the 32bit and 64bit integer modes | |
51 | (define_mode_iterator SIDI [SI DI]) | |
52 | ||
236d6fef SV |
53 | ;; A list of the 64bit modes for thumb1. |
54 | (define_mode_iterator DIDF [DI DF]) | |
55 | ||
3cff0135 TP |
56 | ;; A list of atomic compare and swap success return modes |
57 | (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) | |
58 | ||
76f722f4 | 59 | ;; A list of modes which the VFP unit can handle |
00ea1506 | 60 | (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) |
76f722f4 | 61 | |
ceddf62c SN |
62 | ;; Integer element sizes implemented by IWMMXT. |
63 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
64 | ||
8fd03515 XQ |
65 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
66 | ||
ceddf62c SN |
67 | ;; Integer element sizes for shifts. |
68 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
69 | ||
70 | ;; Integer and float modes supported by Neon and IWMMXT. | |
71 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
72 | ||
63c8f7d6 SP |
73 | ;; Integer and float modes supported by Neon, IWMMXT and MVE. |
74 | (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) | |
75 | ||
76 | ;; Integer and float modes supported by Neon and IWMMXT but not MVE. | |
77 | (define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF]) | |
78 | ||
ceddf62c SN |
79 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. |
80 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
81 | ||
82 | ;; Integer modes supported by Neon and IWMMXT | |
83 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
84 | ||
85 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
86 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
87 | ||
4b644867 | 88 | ;; Double-width vector modes, on which we support arithmetic (no HF!) |
ceddf62c SN |
89 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) |
90 | ||
4b644867 AL |
91 | ;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate. |
92 | (define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI]) | |
93 | ||
ceddf62c | 94 | ;; Double-width vector modes plus 64-bit elements. |
17a13507 | 95 | (define_mode_iterator VDX [V8QI V4HI V4HF V4BF V2SI V2SF DI]) |
4b644867 | 96 | |
ff229375 DB |
97 | ;; Double-width vector modes plus 64-bit elements, including V4BF. |
98 | (define_mode_iterator VDXBF [V8QI V4HI V4HF (V4BF "TARGET_BF16_SIMD") V2SI V2SF DI]) | |
99 | ||
eb637e76 DB |
100 | ;; Double-width vector modes plus 64-bit elements, V4BF and V8BF. |
101 | (define_mode_iterator VDXBF2 [V8QI V4HI V4HF V2SI V2SF DI (V4BF "TARGET_BF16_SIMD") (V8BF ("TARGET_BF16_SIMD"))]) | |
102 | ||
2e87b2f4 SMW |
103 | ;; Double-width vector modes plus 64-bit elements, |
104 | ;; with V4BFmode added, suitable for moves. | |
105 | (define_mode_iterator VDXMOV [V8QI V4HI V4HF V4BF V2SI V2SF DI]) | |
106 | ||
4b644867 | 107 | ;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane. |
17a13507 | 108 | (define_mode_iterator VD_LANE [V8QI V4HI V4HF V4BF V2SI V2SF]) |
ceddf62c SN |
109 | |
110 | ;; Double-width vector modes without floating-point elements. | |
111 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
112 | ||
4b644867 | 113 | ;; Quad-width vector modes supporting arithmetic (no HF!). |
ceddf62c SN |
114 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) |
115 | ||
4b644867 AL |
116 | ;; Quad-width vector modes, including V8HF. |
117 | (define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF]) | |
118 | ||
ff229375 DB |
119 | ;; Quad-width vector modes, including V8BF. |
120 | (define_mode_iterator VQ2BF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF]) | |
121 | ||
4b644867 | 122 | ;; Quad-width vector modes with 16- or 32-bit elements |
1528f343 | 123 | (define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF (V8BF "TARGET_BF16_SIMD")]) |
4b644867 | 124 | |
ceddf62c | 125 | ;; Quad-width vector modes plus 64-bit elements. |
17a13507 | 126 | (define_mode_iterator VQX [V16QI V8HI V8HF V8BF V4SI V4SF V2DI]) |
ceddf62c | 127 | |
1a5c27b1 SP |
128 | ;; Quad-width vector modes plus 64-bit elements. |
129 | (define_mode_iterator VQX_NOBF [V16QI V8HI V8HF V4SI V4SF V2DI]) | |
130 | ||
2d22ab64 KT |
131 | ;; Quad-width vector modes plus 64-bit elements and V8BF. |
132 | (define_mode_iterator VQXBF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF V2DI]) | |
133 | ||
ceddf62c SN |
134 | ;; Quad-width vector modes without floating-point elements. |
135 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
136 | ||
2e87b2f4 SMW |
137 | ;; Quad-width vector modes, with TImode and V8BFmode added, suitable for moves. |
138 | (define_mode_iterator VQXMOV [V16QI V8HI V8HF V8BF V4SI V4SF V2DI TI]) | |
ceddf62c SN |
139 | |
140 | ;; Opaque structure types wider than TImode. | |
14782c81 SP |
141 | (define_mode_iterator VSTRUCT [(EI "!TARGET_HAVE_MVE") OI |
142 | (CI "!TARGET_HAVE_MVE") XI]) | |
ceddf62c SN |
143 | |
144 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
145 | (define_mode_iterator VTAB [TI EI OI]) | |
146 | ||
ccf041da ES |
147 | ;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q. |
148 | (define_mode_iterator VMEMX2 [TI OI]) | |
149 | ||
ceddf62c SN |
150 | ;; Widenable modes. |
151 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
152 | ||
153 | ;; Narrowable modes. | |
154 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
155 | ||
156 | ;; All supported vector modes (except singleton DImode). | |
e36ce56e | 157 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) |
ceddf62c | 158 | |
d0b6b5a7 KT |
159 | ;; All supported floating-point vector modes (except V2DF). |
160 | (define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST") | |
161 | (V8HF "TARGET_NEON_FP16INST") V2SF V4SF]) | |
162 | ||
c2b7062d TC |
163 | ;; Double vector modes. |
164 | (define_mode_iterator VDF [V2SF V4HF]) | |
165 | ||
166 | ;; Quad vector Float modes with half/single elements. | |
167 | (define_mode_iterator VQ_HSF [V8HF V4SF]) | |
168 | ||
169 | ||
ceddf62c SN |
170 | ;; All supported vector modes (except those with 64-bit integer elements). |
171 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
172 | ||
b1a970a5 MW |
173 | ;; All supported vector modes including 16-bit float modes. |
174 | (define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF | |
175 | V8HF V4HF]) | |
176 | ||
ceddf62c SN |
177 | ;; Supported integer vector modes (not 64 bit elements). |
178 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
179 | ||
180 | ;; Supported integer vector modes (not singleton DI) | |
181 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
182 | ||
183 | ;; Vector modes, including 64-bit integer elements. | |
4b644867 | 184 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI |
17a13507 | 185 | V4HF V8HF V4BF V8BF V2SF V4SF DI V2DI]) |
ceddf62c SN |
186 | |
187 | ;; Vector modes including 64-bit integer elements, but no floats. | |
188 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
189 | ||
7a10ea9f KT |
190 | ;; Vector modes for H, S and D types. |
191 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
192 | ||
ceddf62c SN |
193 | ;; Vector modes for float->int conversions. |
194 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
195 | ||
196 | ;; Vector modes form int->float conversions. | |
197 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
198 | ||
55a9b91b MW |
199 | ;; Vector modes for int->half conversions. |
200 | (define_mode_iterator VCVTHI [V4HI V8HI]) | |
201 | ||
ceddf62c SN |
202 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. |
203 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
204 | ||
205 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
206 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
207 | ||
208 | ;; Above modes combined. | |
209 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
210 | ||
211 | ;; As VMD, but integer modes only. | |
212 | (define_mode_iterator VMDI [V4HI V2SI]) | |
213 | ||
214 | ;; As VMQ, but integer modes only. | |
215 | (define_mode_iterator VMQI [V8HI V4SI]) | |
216 | ||
217 | ;; Above modes combined. | |
218 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
219 | ||
220 | ;; Modes with 8-bit and 16-bit elements. | |
221 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
222 | ||
223 | ;; Modes with 8-bit elements. | |
224 | (define_mode_iterator VE [V8QI V16QI]) | |
225 | ||
8ba8ebff RS |
226 | ;; V2DI only (for use with @ patterns). |
227 | (define_mode_iterator V2DI_ONLY [V2DI]) | |
228 | ||
ceddf62c SN |
229 | ;; Modes with 64-bit elements only. |
230 | (define_mode_iterator V64 [DI V2DI]) | |
231 | ||
232 | ;; Modes with 32-bit elements only. | |
233 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
234 | ||
46b57af1 TB |
235 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
236 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
655b30bf | 237 | |
b1a970a5 MW |
238 | ;; Vector modes for 16-bit floating-point support. |
239 | (define_mode_iterator VH [V8HF V4HF]) | |
240 | ||
76068651 CL |
241 | ;; Modes with 16-bit elements only. |
242 | (define_mode_iterator V16 [V4HI V4HF V8HI V8HF]) | |
243 | ||
2e87b2f4 SMW |
244 | ;; 16-bit floating-point vector modes suitable for moving (includes BFmode). |
245 | (define_mode_iterator VHFBF [V8HF V4HF V4BF V8BF]) | |
246 | ||
63c8f7d6 SP |
247 | ;; 16-bit floating-point vector modes suitable for moving (includes BFmode, |
248 | ;; without V8HF ). | |
249 | (define_mode_iterator VHFBF_split [V4HF V4BF V8BF]) | |
250 | ||
2e87b2f4 SMW |
251 | ;; 16-bit floating-point scalar modes suitable for moving (includes BFmode). |
252 | (define_mode_iterator HFBF [HF BF]) | |
253 | ||
655b30bf JB |
254 | ;; Iterators used for fixed-point support. |
255 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
256 | ||
257 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
258 | ||
259 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
260 | ||
261 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
262 | ||
263 | (define_mode_iterator QMUL [HQ HA]) | |
264 | ||
94f0f2cc JG |
265 | ;; Modes for polynomial or float values. |
266 | (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) | |
267 | ||
8e6d0dba DZ |
268 | ;; Modes for BF16 convert instructions. |
269 | (define_mode_iterator VBFCVT [V4BF V8BF]) | |
270 | (define_mode_iterator VBFCVTM [V2SI SF]) | |
271 | ||
a9a88a0a SP |
272 | ;; MVE mode iterator. |
273 | (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) | |
67d56b27 | 274 | (define_mode_iterator MVE_vecs [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) |
a9a88a0a SP |
275 | (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) |
276 | (define_mode_iterator MVE_0 [V8HF V4SF]) | |
277 | (define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI]) | |
278 | (define_mode_iterator MVE_3 [V16QI V8HI]) | |
279 | (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) | |
280 | (define_mode_iterator MVE_5 [V8HI V4SI]) | |
e0bc13d3 AV |
281 | (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI]) |
282 | (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI]) | |
0c1eb901 CL |
283 | (define_mode_iterator MVE_V8HF [V8HF]) |
284 | (define_mode_iterator MVE_V16QI [V16QI]) | |
a9a88a0a | 285 | |
ceddf62c SN |
286 | ;;---------------------------------------------------------------------------- |
287 | ;; Code iterators | |
288 | ;;---------------------------------------------------------------------------- | |
289 | ||
381811fa KT |
290 | ;; The signed gt, ge comparisons |
291 | (define_code_iterator GTGE [gt ge]) | |
292 | ||
d403b8d4 MW |
293 | ;; The signed gt, ge, lt, le comparisons |
294 | (define_code_iterator GLTE [gt ge lt le]) | |
295 | ||
381811fa KT |
296 | ;; The unsigned gt, ge comparisons |
297 | (define_code_iterator GTUGEU [gtu geu]) | |
298 | ||
299 | ;; Comparisons for vc<cmp> | |
300 | (define_code_iterator COMPARISONS [eq gt ge le lt]) | |
d083fbf7 CL |
301 | ;; Comparisons for MVE |
302 | (define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne]) | |
902692c1 | 303 | (define_code_iterator MVE_FP_COMPARISONS [eq ge gt le lt ne]) |
381811fa | 304 | |
ceddf62c | 305 | ;; A list of ... |
728dc153 | 306 | (define_code_iterator IOR_XOR [ior xor]) |
ceddf62c | 307 | |
1ea95660 WD |
308 | (define_code_iterator LOGICAL [and ior xor]) |
309 | ||
ceddf62c | 310 | ;; Operations on two halves of a quadword vector. |
728dc153 | 311 | (define_code_iterator VQH_OPS [plus smin smax umin umax]) |
ceddf62c SN |
312 | |
313 | ;; Operations on two halves of a quadword vector, | |
314 | ;; without unsigned variants (for use with *SFmode pattern). | |
728dc153 | 315 | (define_code_iterator VQHS_OPS [plus smin smax]) |
ceddf62c | 316 | |
46b57af1 TB |
317 | ;; A list of widening operators |
318 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c | 319 | |
3f2dc806 | 320 | ;; Right shifts |
728dc153 | 321 | (define_code_iterator RSHIFTS [ashiftrt lshiftrt]) |
3f2dc806 | 322 | |
ababd936 KT |
323 | ;; Iterator for integer conversions |
324 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
325 | ||
004d3809 | 326 | ;; Binary operators whose second operand can be shifted. |
728dc153 | 327 | (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) |
004d3809 | 328 | |
d403b8d4 MW |
329 | ;; Operations on the sign of a number. |
330 | (define_code_iterator ABSNEG [abs neg]) | |
331 | ||
06e95715 KT |
332 | ;; The PLUS and MINUS operators. |
333 | (define_code_iterator PLUSMINUS [plus minus]) | |
334 | ||
d403b8d4 MW |
335 | ;; Conversions. |
336 | (define_code_iterator FCVT [unsigned_float float]) | |
337 | ||
e56d199b KT |
338 | ;; Saturating addition, subtraction |
339 | (define_code_iterator SSPLUSMINUS [ss_plus ss_minus]) | |
340 | ||
bcf66a4d CL |
341 | ;; Max/Min iterator, to factorize MVE patterns |
342 | (define_code_iterator MAX_MIN_SU [smax umax smin umin]) | |
343 | ||
5ea7a47c CL |
344 | ;; Floating-point Max/Min iterator, to factorize MVE patterns |
345 | (define_code_iterator MAX_MIN_F [smax smin]) | |
346 | ||
7734b991 CL |
347 | ;; MVE integer unary operations. |
348 | (define_int_iterator MVE_INT_M_UNARY [ | |
349 | VABSQ_M_S | |
350 | VCLSQ_M_S | |
351 | VCLZQ_M_S VCLZQ_M_U | |
352 | VNEGQ_M_S | |
353 | VQABSQ_M_S | |
354 | VQNEGQ_M_S | |
355 | ]) | |
356 | ||
357 | (define_int_iterator MVE_INT_UNARY [ | |
358 | VCLSQ_S | |
359 | VQABSQ_S | |
360 | VQNEGQ_S | |
361 | ]) | |
362 | ||
363 | (define_int_iterator MVE_FP_UNARY [ | |
364 | VRNDQ_F | |
365 | VRNDAQ_F | |
366 | VRNDMQ_F | |
367 | VRNDNQ_F | |
368 | VRNDPQ_F | |
369 | VRNDXQ_F | |
370 | ]) | |
371 | ||
372 | (define_int_iterator MVE_FP_M_UNARY [ | |
373 | VABSQ_M_F | |
374 | VNEGQ_M_F | |
375 | VRNDAQ_M_F | |
376 | VRNDMQ_M_F | |
377 | VRNDNQ_M_F | |
378 | VRNDPQ_M_F | |
379 | VRNDQ_M_F | |
380 | VRNDXQ_M_F | |
381 | ]) | |
382 | ||
0c1eb901 CL |
383 | (define_int_iterator MVE_FP_VREV64Q_ONLY [ |
384 | VREV64Q_F | |
385 | ]) | |
386 | ||
387 | (define_int_iterator MVE_FP_M_VREV64Q_ONLY [ | |
388 | VREV64Q_M_F | |
389 | ]) | |
390 | ||
391 | (define_int_iterator MVE_FP_VREV32Q_ONLY [ | |
392 | VREV32Q_F | |
393 | ]) | |
394 | ||
395 | (define_int_iterator MVE_FP_M_VREV32Q_ONLY [ | |
396 | VREV32Q_M_F | |
397 | ]) | |
398 | ||
fc468102 CL |
399 | (define_int_iterator MVE_FP_M_N_VDUPQ_ONLY [ |
400 | VDUPQ_M_N_F | |
401 | ]) | |
402 | ||
403 | (define_int_iterator MVE_FP_N_VDUPQ_ONLY [ | |
404 | VDUPQ_N_F | |
405 | ]) | |
406 | ||
b0b3a5e9 CL |
407 | ;; MVE integer binary operations. |
408 | (define_code_iterator MVE_INT_BINARY_RTX [plus minus mult]) | |
409 | ||
410 | (define_int_iterator MVE_INT_M_BINARY [ | |
411 | VADDQ_M_S VADDQ_M_U | |
412 | VMULQ_M_S VMULQ_M_U | |
413 | VSUBQ_M_S VSUBQ_M_U | |
414 | ]) | |
415 | ||
5cbe0c09 CL |
416 | (define_int_iterator MVE_INT_SU_M_BINARY [ |
417 | VABDQ_M_S VABDQ_M_U | |
418 | VHADDQ_M_S VHADDQ_M_U | |
419 | VHSUBQ_M_S VHSUBQ_M_U | |
420 | VMAXQ_M_S VMAXQ_M_U | |
421 | VMINQ_M_S VMINQ_M_U | |
422 | VMULHQ_M_S VMULHQ_M_U | |
423 | VQADDQ_M_S VQADDQ_M_U | |
424 | VQDMLADHQ_M_S | |
425 | VQDMLADHXQ_M_S | |
426 | VQDMLSDHQ_M_S | |
427 | VQDMLSDHXQ_M_S | |
428 | VQDMULHQ_M_S | |
429 | VQRDMLADHQ_M_S | |
430 | VQRDMLADHXQ_M_S | |
431 | VQRDMLSDHQ_M_S | |
432 | VQRDMLSDHXQ_M_S | |
433 | VQRDMULHQ_M_S | |
434 | VQRSHLQ_M_S VQRSHLQ_M_U | |
435 | VQSHLQ_M_S VQSHLQ_M_U | |
436 | VQSUBQ_M_S VQSUBQ_M_U | |
437 | VRHADDQ_M_S VRHADDQ_M_U | |
438 | VRMULHQ_M_S VRMULHQ_M_U | |
439 | VRSHLQ_M_S VRSHLQ_M_U | |
440 | VSHLQ_M_S VSHLQ_M_U | |
441 | ]) | |
442 | ||
67e4e591 CL |
443 | (define_int_iterator MVE_INT_M_BINARY_LOGIC [ |
444 | VANDQ_M_S VANDQ_M_U | |
445 | VBICQ_M_S VBICQ_M_U | |
446 | VEORQ_M_S VEORQ_M_U | |
447 | VORRQ_M_S VORRQ_M_U | |
448 | ]) | |
449 | ||
b0b3a5e9 CL |
450 | (define_int_iterator MVE_INT_M_N_BINARY [ |
451 | VADDQ_M_N_S VADDQ_M_N_U | |
452 | VMULQ_M_N_S VMULQ_M_N_U | |
453 | VSUBQ_M_N_S VSUBQ_M_N_U | |
454 | ]) | |
455 | ||
67e4e591 CL |
456 | (define_int_iterator MVE_INT_M_N_BINARY_LOGIC [ |
457 | VBICQ_M_N_S VBICQ_M_N_U | |
458 | VORRQ_M_N_S VORRQ_M_N_U | |
459 | ]) | |
460 | ||
a7cbd5f9 CL |
461 | (define_int_iterator MVE_INT_SU_M_N_BINARY [ |
462 | VHADDQ_M_N_S VHADDQ_M_N_U | |
463 | VHSUBQ_M_N_S VHSUBQ_M_N_U | |
464 | VMLAQ_M_N_S VMLAQ_M_N_U | |
465 | VMLASQ_M_N_S VMLASQ_M_N_U | |
466 | VQDMLAHQ_M_N_S | |
467 | VQDMLASHQ_M_N_S | |
468 | VQRDMLAHQ_M_N_S | |
469 | VQRDMLASHQ_M_N_S | |
470 | VQADDQ_M_N_S VQADDQ_M_N_U | |
471 | VQSUBQ_M_N_S VQSUBQ_M_N_U | |
472 | VQDMULHQ_M_N_S | |
473 | VQRDMULHQ_M_N_S | |
474 | ]) | |
475 | ||
b0b3a5e9 CL |
476 | (define_int_iterator MVE_INT_N_BINARY [ |
477 | VADDQ_N_S VADDQ_N_U | |
478 | VMULQ_N_S VMULQ_N_U | |
479 | VSUBQ_N_S VSUBQ_N_U | |
480 | ]) | |
481 | ||
6bb8a5bd CL |
482 | (define_int_iterator MVE_VSHRQ_M_N [ |
483 | VRSHRQ_M_N_S VRSHRQ_M_N_U | |
484 | VSHRQ_M_N_S VSHRQ_M_N_U | |
485 | ]) | |
486 | ||
487 | (define_int_iterator MVE_VSHRQ_N [ | |
488 | VRSHRQ_N_S VRSHRQ_N_U | |
489 | VSHRQ_N_S VSHRQ_N_U | |
490 | ]) | |
491 | ||
111f474f CL |
492 | (define_int_iterator MVE_INT_SU_N_BINARY [ |
493 | VHADDQ_N_S VHADDQ_N_U | |
494 | VHSUBQ_N_S VHSUBQ_N_U | |
495 | VQADDQ_N_S VQADDQ_N_U | |
496 | VQDMULHQ_N_S | |
497 | VQRDMULHQ_N_S | |
498 | VQSUBQ_N_S VQSUBQ_N_U | |
499 | ]) | |
500 | ||
3fe5a244 CL |
501 | (define_int_iterator MVE_INT_SU_BINARY [ |
502 | VABDQ_S VABDQ_U | |
503 | VHADDQ_S VHADDQ_U | |
504 | VHSUBQ_S VHSUBQ_U | |
505 | VMULHQ_S VMULHQ_U | |
506 | VQADDQ_S VQADDQ_U | |
507 | VQDMULHQ_S | |
508 | VQRDMULHQ_S | |
509 | VQRSHLQ_S VQRSHLQ_U | |
510 | VQSHLQ_S VQSHLQ_U | |
511 | VQSUBQ_S VQSUBQ_U | |
512 | VRHADDQ_S VRHADDQ_U | |
513 | VRMULHQ_S VRMULHQ_U | |
514 | VRSHLQ_S VRSHLQ_U | |
515 | ]) | |
516 | ||
67e4e591 CL |
517 | (define_int_iterator MVE_INT_N_BINARY_LOGIC [ |
518 | VBICQ_N_S VBICQ_N_U | |
519 | VORRQ_N_S VORRQ_N_U | |
520 | ]) | |
521 | ||
7e6c39a3 CL |
522 | (define_int_iterator MVE_SHIFT_M_R [ |
523 | VQSHLQ_M_R_S VQSHLQ_M_R_U | |
524 | VSHLQ_M_R_S VSHLQ_M_R_U | |
525 | ]) | |
526 | ||
527 | (define_int_iterator MVE_SHIFT_M_N [ | |
528 | VQSHLQ_M_N_S VQSHLQ_M_N_U | |
529 | VSHLQ_M_N_S VSHLQ_M_N_U | |
530 | ]) | |
531 | ||
532 | (define_int_iterator MVE_SHIFT_N [ | |
533 | VQSHLQ_N_S VQSHLQ_N_U | |
534 | VSHLQ_N_S VSHLQ_N_U | |
535 | ]) | |
536 | ||
537 | (define_int_iterator MVE_SHIFT_R [ | |
538 | VQSHLQ_R_S VQSHLQ_R_U | |
539 | VSHLQ_R_S VSHLQ_R_U | |
540 | ]) | |
541 | ||
c4d4e62b CL |
542 | (define_int_iterator MVE_RSHIFT_M_N [ |
543 | VQRSHLQ_M_N_S VQRSHLQ_M_N_U | |
544 | VRSHLQ_M_N_S VRSHLQ_M_N_U | |
545 | ]) | |
546 | ||
547 | (define_int_iterator MVE_RSHIFT_N [ | |
548 | VQRSHLQ_N_S VQRSHLQ_N_U | |
549 | VRSHLQ_N_S VRSHLQ_N_U | |
550 | ]) | |
551 | ||
e2f992f7 CL |
552 | (define_int_iterator MVE_SHRN_N [ |
553 | VQRSHRNBQ_N_S VQRSHRNBQ_N_U | |
554 | VQRSHRNTQ_N_S VQRSHRNTQ_N_U | |
8f5b7d21 CL |
555 | VQRSHRUNBQ_N_S |
556 | VQRSHRUNTQ_N_S | |
e2f992f7 CL |
557 | VQSHRNBQ_N_S VQSHRNBQ_N_U |
558 | VQSHRNTQ_N_S VQSHRNTQ_N_U | |
8f5b7d21 CL |
559 | VQSHRUNBQ_N_S |
560 | VQSHRUNTQ_N_S | |
e2f992f7 CL |
561 | VRSHRNBQ_N_S VRSHRNBQ_N_U |
562 | VRSHRNTQ_N_S VRSHRNTQ_N_U | |
563 | VSHRNBQ_N_S VSHRNBQ_N_U | |
564 | VSHRNTQ_N_S VSHRNTQ_N_U | |
565 | ]) | |
566 | ||
567 | (define_int_iterator MVE_SHRN_M_N [ | |
568 | VQRSHRNBQ_M_N_S VQRSHRNBQ_M_N_U | |
569 | VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U | |
8f5b7d21 CL |
570 | VQRSHRUNBQ_M_N_S |
571 | VQRSHRUNTQ_M_N_S | |
e2f992f7 CL |
572 | VQSHRNBQ_M_N_S VQSHRNBQ_M_N_U |
573 | VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U | |
8f5b7d21 CL |
574 | VQSHRUNBQ_M_N_S |
575 | VQSHRUNTQ_M_N_S | |
e2f992f7 CL |
576 | VRSHRNBQ_M_N_S VRSHRNBQ_M_N_U |
577 | VRSHRNTQ_M_N_S VRSHRNTQ_M_N_U | |
578 | VSHRNBQ_M_N_S VSHRNBQ_M_N_U | |
579 | VSHRNTQ_M_N_S VSHRNTQ_M_N_U | |
580 | ]) | |
581 | ||
b0b3a5e9 | 582 | (define_int_iterator MVE_FP_M_BINARY [ |
1736f4af | 583 | VABDQ_M_F |
b0b3a5e9 | 584 | VADDQ_M_F |
fbab00f0 CL |
585 | VFMAQ_M_F |
586 | VFMSQ_M_F | |
5ea7a47c CL |
587 | VMAXNMQ_M_F |
588 | VMINNMQ_M_F | |
b0b3a5e9 CL |
589 | VMULQ_M_F |
590 | VSUBQ_M_F | |
591 | ]) | |
592 | ||
67e4e591 CL |
593 | (define_int_iterator MVE_FP_M_BINARY_LOGIC [ |
594 | VANDQ_M_F | |
595 | VBICQ_M_F | |
596 | VEORQ_M_F | |
597 | VORRQ_M_F | |
598 | ]) | |
599 | ||
b0b3a5e9 CL |
600 | (define_int_iterator MVE_FP_M_N_BINARY [ |
601 | VADDQ_M_N_F | |
fbab00f0 CL |
602 | VFMAQ_M_N_F |
603 | VFMASQ_M_N_F | |
b0b3a5e9 CL |
604 | VMULQ_M_N_F |
605 | VSUBQ_M_N_F | |
606 | ]) | |
607 | ||
608 | (define_int_iterator MVE_FP_N_BINARY [ | |
609 | VADDQ_N_F | |
610 | VMULQ_N_F | |
611 | VSUBQ_N_F | |
612 | ]) | |
613 | ||
1736f4af CL |
614 | (define_int_iterator MVE_FP_VABDQ_ONLY [ |
615 | VABDQ_F | |
616 | ]) | |
617 | ||
dd04568f CL |
618 | (define_int_iterator MVE_FP_CREATE_ONLY [ |
619 | VCREATEQ_F | |
620 | ]) | |
621 | ||
6ff07398 CL |
622 | (define_int_iterator MVE_VBRSR_M_N_FP [ |
623 | VBRSRQ_M_N_F | |
624 | ]) | |
625 | ||
626 | (define_int_iterator MVE_VBRSR_N_FP [ | |
627 | VBRSRQ_N_F | |
628 | ]) | |
629 | ||
6a08718a CL |
630 | ;; MVE comparison iterators |
631 | (define_int_iterator MVE_CMP_M [ | |
632 | VCMPCSQ_M_U | |
633 | VCMPEQQ_M_S VCMPEQQ_M_U | |
634 | VCMPGEQ_M_S | |
635 | VCMPGTQ_M_S | |
636 | VCMPHIQ_M_U | |
637 | VCMPLEQ_M_S | |
638 | VCMPLTQ_M_S | |
639 | VCMPNEQ_M_S VCMPNEQ_M_U | |
640 | ]) | |
641 | ||
642 | (define_int_iterator MVE_CMP_M_F [ | |
643 | VCMPEQQ_M_F | |
644 | VCMPGEQ_M_F | |
645 | VCMPGTQ_M_F | |
646 | VCMPLEQ_M_F | |
647 | VCMPLTQ_M_F | |
648 | VCMPNEQ_M_F | |
649 | ]) | |
650 | ||
651 | (define_int_iterator MVE_CMP_M_N [ | |
652 | VCMPCSQ_M_N_U | |
653 | VCMPEQQ_M_N_S VCMPEQQ_M_N_U | |
654 | VCMPGEQ_M_N_S | |
655 | VCMPGTQ_M_N_S | |
656 | VCMPHIQ_M_N_U | |
657 | VCMPLEQ_M_N_S | |
658 | VCMPLTQ_M_N_S | |
659 | VCMPNEQ_M_N_S VCMPNEQ_M_N_U | |
660 | ]) | |
661 | ||
662 | (define_int_iterator MVE_CMP_M_N_F [ | |
663 | VCMPEQQ_M_N_F | |
664 | VCMPGEQ_M_N_F | |
665 | VCMPGTQ_M_N_F | |
666 | VCMPLEQ_M_N_F | |
667 | VCMPLTQ_M_N_F | |
668 | VCMPNEQ_M_N_F | |
669 | ]) | |
670 | ||
fbab00f0 CL |
671 | (define_int_iterator MVE_VFMxQ_F [ |
672 | VFMAQ_F VFMSQ_F | |
673 | ]) | |
674 | ||
675 | (define_int_iterator MVE_VFMAxQ_N_F [ | |
676 | VFMAQ_N_F VFMASQ_N_F | |
677 | ]) | |
678 | ||
16c5aca6 CL |
679 | (define_int_iterator MVE_VMAXVQ_VMINVQ [ |
680 | VMAXAVQ_S | |
681 | VMAXVQ_S VMAXVQ_U | |
682 | VMINAVQ_S | |
683 | VMINVQ_S VMINVQ_U | |
684 | ]) | |
685 | ||
686 | (define_int_iterator MVE_VMAXVQ_VMINVQ_P [ | |
687 | VMAXAVQ_P_S | |
688 | VMAXVQ_P_S VMAXVQ_P_U | |
689 | VMINAVQ_P_S | |
690 | VMINVQ_P_S VMINVQ_P_U | |
691 | ]) | |
692 | ||
d814dc9d CL |
693 | (define_int_iterator MVE_VMAXNMxV_MINNMxVQ [ |
694 | VMAXNMAVQ_F | |
695 | VMAXNMVQ_F | |
696 | VMINNMAVQ_F | |
697 | VMINNMVQ_F | |
698 | ]) | |
699 | ||
700 | (define_int_iterator MVE_VMAXNMxV_MINNMxVQ_P [ | |
701 | VMAXNMAVQ_P_F | |
702 | VMAXNMVQ_P_F | |
703 | VMINNMAVQ_P_F | |
704 | VMINNMVQ_P_F | |
705 | ]) | |
706 | ||
26d6e02c CL |
707 | (define_int_iterator MVE_VMAXNMA_VMINNMAQ [ |
708 | VMAXNMAQ_F | |
709 | VMINNMAQ_F | |
710 | ]) | |
711 | ||
712 | (define_int_iterator MVE_VMAXNMA_VMINNMAQ_M [ | |
713 | VMAXNMAQ_M_F | |
714 | VMINNMAQ_M_F | |
715 | ]) | |
716 | ||
dcc05862 CL |
717 | (define_int_iterator MVE_VMAXAVMINAQ [ |
718 | VMAXAQ_S | |
719 | VMINAQ_S | |
720 | ]) | |
721 | ||
722 | (define_int_iterator MVE_VMAXAVMINAQ_M [ | |
723 | VMAXAQ_M_S | |
724 | VMINAQ_M_S | |
725 | ]) | |
726 | ||
f2fd708a CL |
727 | (define_int_iterator MVE_VMLxQ_N [ |
728 | VMLAQ_N_S VMLAQ_N_U | |
729 | VMLASQ_N_S VMLASQ_N_U | |
730 | VQDMLAHQ_N_S | |
731 | VQDMLASHQ_N_S | |
732 | VQRDMLAHQ_N_S | |
733 | VQRDMLASHQ_N_S | |
734 | ]) | |
735 | ||
1817749d CL |
736 | (define_int_iterator MVE_VMLxDAVQ [ |
737 | VMLADAVQ_S VMLADAVQ_U | |
738 | VMLADAVXQ_S | |
739 | VMLSDAVQ_S | |
740 | VMLSDAVXQ_S | |
741 | ]) | |
742 | ||
743 | (define_int_iterator MVE_VMLxDAVQ_P [ | |
744 | VMLADAVQ_P_S VMLADAVQ_P_U | |
745 | VMLADAVXQ_P_S | |
746 | VMLSDAVQ_P_S | |
747 | VMLSDAVXQ_P_S | |
748 | ]) | |
749 | ||
750 | (define_int_iterator MVE_VMLxDAVAQ [ | |
751 | VMLADAVAQ_S VMLADAVAQ_U | |
752 | VMLSDAVAXQ_S | |
753 | VMLSDAVAQ_S | |
754 | VMLADAVAXQ_S | |
755 | ]) | |
756 | ||
757 | (define_int_iterator MVE_VMLxDAVAQ_P [ | |
758 | VMLADAVAQ_P_S VMLADAVAQ_P_U | |
759 | VMLSDAVAXQ_P_S | |
760 | VMLSDAVAQ_P_S | |
761 | VMLADAVAXQ_P_S | |
762 | ]) | |
763 | ||
c1e068e4 CL |
764 | (define_int_iterator MVE_VMLxLDAVxQ [ |
765 | VMLALDAVQ_S VMLALDAVQ_U | |
766 | VMLALDAVXQ_S | |
767 | VMLSLDAVQ_S | |
768 | VMLSLDAVXQ_S | |
769 | ]) | |
770 | ||
771 | (define_int_iterator MVE_VMLxLDAVxQ_P [ | |
772 | VMLALDAVQ_P_S VMLALDAVQ_P_U | |
773 | VMLALDAVXQ_P_S | |
774 | VMLSLDAVQ_P_S | |
775 | VMLSLDAVXQ_P_S | |
776 | ]) | |
777 | ||
c68ccdf2 CL |
778 | (define_int_iterator MVE_VMLxLDAVAxQ [ |
779 | VMLALDAVAQ_S VMLALDAVAQ_U | |
780 | VMLALDAVAXQ_S | |
781 | VMLSLDAVAQ_S | |
782 | VMLSLDAVAXQ_S | |
783 | ]) | |
784 | ||
785 | (define_int_iterator MVE_VMLxLDAVAxQ_P [ | |
786 | VMLALDAVAQ_P_S VMLALDAVAQ_P_U | |
787 | VMLALDAVAXQ_P_S | |
788 | VMLSLDAVAQ_P_S | |
789 | VMLSLDAVAXQ_P_S | |
790 | ]) | |
791 | ||
c71b5c78 CL |
792 | (define_int_iterator MVE_VQDMULLxQ [ |
793 | VQDMULLBQ_S | |
794 | VQDMULLTQ_S | |
795 | ]) | |
796 | ||
797 | (define_int_iterator MVE_VQDMULLxQ_M [ | |
798 | VQDMULLBQ_M_S | |
799 | VQDMULLTQ_M_S | |
800 | ]) | |
801 | ||
802 | (define_int_iterator MVE_VQDMULLxQ_M_N [ | |
803 | VQDMULLBQ_M_N_S | |
804 | VQDMULLTQ_M_N_S | |
805 | ]) | |
806 | ||
807 | (define_int_iterator MVE_VQDMULLxQ_N [ | |
808 | VQDMULLBQ_N_S | |
809 | VQDMULLTQ_N_S | |
810 | ]) | |
811 | ||
3bf67ec9 CL |
812 | (define_int_iterator MVE_VQxDMLxDHxQ_S [ |
813 | VQDMLADHQ_S | |
814 | VQDMLADHXQ_S | |
815 | VQDMLSDHQ_S | |
816 | VQDMLSDHXQ_S | |
817 | VQRDMLADHQ_S | |
818 | VQRDMLADHXQ_S | |
819 | VQRDMLSDHQ_S | |
820 | VQRDMLSDHXQ_S | |
821 | ]) | |
822 | ||
e044696f CL |
823 | (define_int_iterator MVE_VRMLxLDAVxQ [ |
824 | VRMLALDAVHQ_S VRMLALDAVHQ_U | |
825 | VRMLALDAVHXQ_S | |
826 | VRMLSLDAVHQ_S | |
827 | VRMLSLDAVHXQ_S | |
828 | ]) | |
829 | ||
830 | (define_int_iterator MVE_VRMLxLDAVHxQ_P [ | |
831 | VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U | |
832 | VRMLALDAVHXQ_P_S | |
833 | VRMLSLDAVHQ_P_S | |
834 | VRMLSLDAVHXQ_P_S | |
835 | ]) | |
836 | ||
e18f715b CL |
837 | (define_int_iterator MVE_VRMLxLDAVHAxQ [ |
838 | VRMLALDAVHAQ_S VRMLALDAVHAQ_U | |
839 | VRMLALDAVHAXQ_S | |
840 | VRMLSLDAVHAQ_S | |
841 | VRMLSLDAVHAXQ_S | |
842 | ]) | |
843 | ||
844 | (define_int_iterator MVE_VRMLxLDAVHAxQ_P [ | |
845 | VRMLALDAVHAQ_P_S VRMLALDAVHAQ_P_U | |
846 | VRMLALDAVHAXQ_P_S | |
847 | VRMLSLDAVHAQ_P_S | |
848 | VRMLSLDAVHAXQ_P_S | |
849 | ]) | |
850 | ||
7f49b4a0 CL |
851 | (define_int_iterator MVE_MOVN [ |
852 | VMOVNBQ_S VMOVNBQ_U | |
853 | VMOVNTQ_S VMOVNTQ_U | |
854 | VQMOVNBQ_S VQMOVNBQ_U | |
855 | VQMOVNTQ_S VQMOVNTQ_U | |
856 | VQMOVUNBQ_S | |
857 | VQMOVUNTQ_S | |
858 | ]) | |
859 | ||
860 | (define_int_iterator MVE_MOVN_M [ | |
861 | VMOVNBQ_M_S VMOVNBQ_M_U | |
862 | VMOVNTQ_M_S VMOVNTQ_M_U | |
863 | VQMOVNBQ_M_S VQMOVNBQ_M_U | |
864 | VQMOVNTQ_M_S VQMOVNTQ_M_U | |
865 | VQMOVUNBQ_M_S | |
866 | VQMOVUNTQ_M_S | |
867 | ]) | |
868 | ||
b0b3a5e9 CL |
869 | (define_code_attr mve_addsubmul [ |
870 | (minus "vsub") | |
871 | (mult "vmul") | |
872 | (plus "vadd") | |
873 | ]) | |
874 | ||
8594dfed AV |
875 | (define_int_attr mve_vmaxmin_safe_imp [ |
876 | (VMAXVQ_U "yes") | |
877 | (VMAXVQ_S "no") | |
878 | (VMAXAVQ_S "yes") | |
879 | (VMINVQ_U "no") | |
880 | (VMINVQ_S "no") | |
881 | (VMINAVQ_S "no")]) | |
882 | ||
6a08718a CL |
883 | (define_int_attr mve_cmp_op1 [ |
884 | (VCMPCSQ_M_U "cs") | |
885 | (VCMPEQQ_M_S "eq") (VCMPEQQ_M_U "eq") | |
886 | (VCMPGEQ_M_S "ge") | |
887 | (VCMPGTQ_M_S "gt") | |
888 | (VCMPHIQ_M_U "hi") | |
889 | (VCMPLEQ_M_S "le") | |
890 | (VCMPLTQ_M_S "lt") | |
891 | (VCMPNEQ_M_S "ne") (VCMPNEQ_M_U "ne") | |
892 | (VCMPEQQ_M_F "eq") | |
893 | (VCMPGEQ_M_F "ge") | |
894 | (VCMPGTQ_M_F "gt") | |
895 | (VCMPLEQ_M_F "le") | |
896 | (VCMPLTQ_M_F "lt") | |
897 | (VCMPNEQ_M_F "ne") | |
898 | (VCMPCSQ_M_N_U "cs") | |
899 | (VCMPEQQ_M_N_S "eq") (VCMPEQQ_M_N_U "eq") | |
900 | (VCMPGEQ_M_N_S "ge") | |
901 | (VCMPGTQ_M_N_S "gt") | |
902 | (VCMPHIQ_M_N_U "hi") | |
903 | (VCMPLEQ_M_N_S "le") | |
904 | (VCMPLTQ_M_N_S "lt") | |
905 | (VCMPNEQ_M_N_S "ne") (VCMPNEQ_M_N_U "ne") | |
906 | (VCMPEQQ_M_N_F "eq") | |
907 | (VCMPGEQ_M_N_F "ge") | |
908 | (VCMPGTQ_M_N_F "gt") | |
909 | (VCMPLEQ_M_N_F "le") | |
910 | (VCMPLTQ_M_N_F "lt") | |
911 | (VCMPNEQ_M_N_F "ne") | |
912 | ]) | |
913 | ||
f7196b72 CL |
914 | (define_int_iterator MVE_VPSELQ_F [ |
915 | VPSELQ_F | |
916 | ]) | |
917 | ||
0c5ba73a CL |
918 | (define_int_iterator MVE_VCADDQ_VCMULQ [ |
919 | UNSPEC_VCADD90 UNSPEC_VCADD270 | |
920 | UNSPEC_VCMUL UNSPEC_VCMUL90 UNSPEC_VCMUL180 UNSPEC_VCMUL270 | |
921 | ]) | |
922 | ||
923 | (define_int_iterator MVE_VCADDQ_VCMULQ_M [ | |
924 | VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F | |
925 | VCMULQ_M_F VCMULQ_ROT90_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F | |
926 | ]) | |
927 | ||
6ae2fba5 CL |
928 | (define_int_iterator MVE_VCMLAQ_M [ |
929 | VCMLAQ_M_F VCMLAQ_ROT90_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F | |
930 | ]) | |
931 | ||
b0b3a5e9 | 932 | (define_int_attr mve_insn [ |
b22e70e8 | 933 | (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd") |
195cc201 | 934 | (UNSPEC_VCMLA "vcmla") (UNSPEC_VCMLA90 "vcmla") (UNSPEC_VCMLA180 "vcmla") (UNSPEC_VCMLA270 "vcmla") |
0c5ba73a | 935 | (UNSPEC_VCMUL "vcmul") (UNSPEC_VCMUL90 "vcmul") (UNSPEC_VCMUL180 "vcmul") (UNSPEC_VCMUL270 "vcmul") |
1af6d1db CL |
936 | (VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav") |
937 | (VABAVQ_S "vabav") (VABAVQ_U "vabav") | |
1736f4af CL |
938 | (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd") |
939 | (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd") | |
7734b991 CL |
940 | (VABSQ_M_F "vabs") |
941 | (VABSQ_M_S "vabs") | |
42c94cce CL |
942 | (VADDLVAQ_P_S "vaddlva") (VADDLVAQ_P_U "vaddlva") |
943 | (VADDLVAQ_S "vaddlva") (VADDLVAQ_U "vaddlva") | |
fa2c9dbb CL |
944 | (VADDLVQ_P_S "vaddlv") (VADDLVQ_P_U "vaddlv") |
945 | (VADDLVQ_S "vaddlv") (VADDLVQ_U "vaddlv") | |
b0b3a5e9 CL |
946 | (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd") |
947 | (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd") | |
948 | (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd") | |
782eb6bb CL |
949 | (VADDVAQ_P_S "vaddva") (VADDVAQ_P_U "vaddva") |
950 | (VADDVAQ_S "vaddva") (VADDVAQ_U "vaddva") | |
eb1ded46 CL |
951 | (VADDVQ_P_S "vaddv") (VADDVQ_P_U "vaddv") |
952 | (VADDVQ_S "vaddv") (VADDVQ_U "vaddv") | |
67e4e591 CL |
953 | (VANDQ_M_S "vand") (VANDQ_M_U "vand") (VANDQ_M_F "vand") |
954 | (VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic") | |
955 | (VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic") | |
956 | (VBICQ_N_S "vbic") (VBICQ_N_U "vbic") | |
6ff07398 CL |
957 | (VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F "vbrsr") |
958 | (VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr") | |
68ec7d75 SMW |
959 | (VCADDQ_ROT270_M "vcadd") (VCADDQ_ROT270_M_F "vcadd") |
960 | (VCADDQ_ROT90_M "vcadd") (VCADDQ_ROT90_M_F "vcadd") | |
7734b991 CL |
961 | (VCLSQ_M_S "vcls") |
962 | (VCLSQ_S "vcls") | |
963 | (VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz") | |
6ae2fba5 | 964 | (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla") |
0c5ba73a | 965 | (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") |
dd04568f | 966 | (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") |
fc468102 CL |
967 | (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup") |
968 | (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup") | |
67e4e591 | 969 | (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor") |
fbab00f0 CL |
970 | (VFMAQ_F "vfma") |
971 | (VFMAQ_M_F "vfma") | |
972 | (VFMAQ_M_N_F "vfma") | |
973 | (VFMAQ_N_F "vfma") | |
974 | (VFMASQ_M_N_F "vfmas") | |
975 | (VFMASQ_N_F "vfmas") | |
976 | (VFMSQ_F "vfms") | |
977 | (VFMSQ_M_F "vfms") | |
a7cbd5f9 | 978 | (VHADDQ_M_N_S "vhadd") (VHADDQ_M_N_U "vhadd") |
5cbe0c09 | 979 | (VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd") |
111f474f | 980 | (VHADDQ_N_S "vhadd") (VHADDQ_N_U "vhadd") |
3fe5a244 | 981 | (VHADDQ_S "vhadd") (VHADDQ_U "vhadd") |
b22e70e8 CL |
982 | (VHCADDQ_ROT90_M_S "vhcadd") (VHCADDQ_ROT270_M_S "vhcadd") |
983 | (VHCADDQ_ROT90_S "vhcadd") (VHCADDQ_ROT270_S "vhcadd") | |
a7cbd5f9 | 984 | (VHSUBQ_M_N_S "vhsub") (VHSUBQ_M_N_U "vhsub") |
5cbe0c09 | 985 | (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub") |
111f474f | 986 | (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub") |
3fe5a244 | 987 | (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub") |
dcc05862 CL |
988 | (VMAXAQ_M_S "vmaxa") |
989 | (VMAXAQ_S "vmaxa") | |
16c5aca6 CL |
990 | (VMAXAVQ_P_S "vmaxav") |
991 | (VMAXAVQ_S "vmaxav") | |
26d6e02c CL |
992 | (VMAXNMAQ_F "vmaxnma") |
993 | (VMAXNMAQ_M_F "vmaxnma") | |
d814dc9d CL |
994 | (VMAXNMAVQ_F "vmaxnmav") |
995 | (VMAXNMAVQ_P_F "vmaxnmav") | |
5ea7a47c | 996 | (VMAXNMQ_M_F "vmaxnm") |
d814dc9d CL |
997 | (VMAXNMVQ_F "vmaxnmv") |
998 | (VMAXNMVQ_P_F "vmaxnmv") | |
5cbe0c09 | 999 | (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax") |
16c5aca6 CL |
1000 | (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv") |
1001 | (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv") | |
dcc05862 CL |
1002 | (VMINAQ_M_S "vmina") |
1003 | (VMINAQ_S "vmina") | |
16c5aca6 CL |
1004 | (VMINAVQ_P_S "vminav") |
1005 | (VMINAVQ_S "vminav") | |
26d6e02c CL |
1006 | (VMINNMAQ_F "vminnma") |
1007 | (VMINNMAQ_M_F "vminnma") | |
d814dc9d CL |
1008 | (VMINNMAVQ_F "vminnmav") |
1009 | (VMINNMAVQ_P_F "vminnmav") | |
5ea7a47c | 1010 | (VMINNMQ_M_F "vminnm") |
d814dc9d CL |
1011 | (VMINNMVQ_F "vminnmv") |
1012 | (VMINNMVQ_P_F "vminnmv") | |
5cbe0c09 | 1013 | (VMINQ_M_S "vmin") (VMINQ_M_U "vmin") |
16c5aca6 CL |
1014 | (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv") |
1015 | (VMINVQ_S "vminv") (VMINVQ_U "vminv") | |
1817749d CL |
1016 | (VMLADAVAQ_P_S "vmladava") (VMLADAVAQ_P_U "vmladava") |
1017 | (VMLADAVAQ_S "vmladava") (VMLADAVAQ_U "vmladava") | |
1018 | (VMLADAVAXQ_P_S "vmladavax") | |
1019 | (VMLADAVAXQ_S "vmladavax") | |
1020 | (VMLADAVQ_P_S "vmladav") (VMLADAVQ_P_U "vmladav") | |
1021 | (VMLADAVQ_S "vmladav") (VMLADAVQ_U "vmladav") | |
1022 | (VMLADAVXQ_P_S "vmladavx") | |
1023 | (VMLADAVXQ_S "vmladavx") | |
c68ccdf2 CL |
1024 | (VMLALDAVAQ_P_S "vmlaldava") (VMLALDAVAQ_P_U "vmlaldava") |
1025 | (VMLALDAVAQ_S "vmlaldava") (VMLALDAVAQ_U "vmlaldava") | |
1026 | (VMLALDAVAXQ_P_S "vmlaldavax") | |
1027 | (VMLALDAVAXQ_S "vmlaldavax") | |
c1e068e4 CL |
1028 | (VMLALDAVQ_P_S "vmlaldav") (VMLALDAVQ_P_U "vmlaldav") |
1029 | (VMLALDAVQ_S "vmlaldav") (VMLALDAVQ_U "vmlaldav") | |
1030 | (VMLALDAVXQ_P_S "vmlaldavx") | |
1031 | (VMLALDAVXQ_S "vmlaldavx") | |
a7cbd5f9 | 1032 | (VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla") |
f2fd708a | 1033 | (VMLAQ_N_S "vmla") (VMLAQ_N_U "vmla") |
a7cbd5f9 | 1034 | (VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas") |
f2fd708a | 1035 | (VMLASQ_N_S "vmlas") (VMLASQ_N_U "vmlas") |
1817749d CL |
1036 | (VMLSDAVAQ_P_S "vmlsdava") |
1037 | (VMLSDAVAQ_S "vmlsdava") | |
1038 | (VMLSDAVAXQ_P_S "vmlsdavax") | |
1039 | (VMLSDAVAXQ_S "vmlsdavax") | |
1040 | (VMLSDAVQ_P_S "vmlsdav") | |
1041 | (VMLSDAVQ_S "vmlsdav") | |
1042 | (VMLSDAVXQ_P_S "vmlsdavx") | |
1043 | (VMLSDAVXQ_S "vmlsdavx") | |
c68ccdf2 CL |
1044 | (VMLSLDAVAQ_P_S "vmlsldava") |
1045 | (VMLSLDAVAQ_S "vmlsldava") | |
1046 | (VMLSLDAVAXQ_P_S "vmlsldavax") | |
1047 | (VMLSLDAVAXQ_S "vmlsldavax") | |
c1e068e4 CL |
1048 | (VMLSLDAVQ_P_S "vmlsldav") |
1049 | (VMLSLDAVQ_S "vmlsldav") | |
1050 | (VMLSLDAVXQ_P_S "vmlsldavx") | |
1051 | (VMLSLDAVXQ_S "vmlsldavx") | |
51fca3e1 CL |
1052 | (VMOVLBQ_M_S "vmovlb") (VMOVLBQ_M_U "vmovlb") |
1053 | (VMOVLBQ_S "vmovlb") (VMOVLBQ_U "vmovlb") | |
1054 | (VMOVLTQ_M_S "vmovlt") (VMOVLTQ_M_U "vmovlt") | |
1055 | (VMOVLTQ_S "vmovlt") (VMOVLTQ_U "vmovlt") | |
7f49b4a0 CL |
1056 | (VMOVNBQ_M_S "vmovnb") (VMOVNBQ_M_U "vmovnb") |
1057 | (VMOVNBQ_S "vmovnb") (VMOVNBQ_U "vmovnb") | |
1058 | (VMOVNTQ_M_S "vmovnt") (VMOVNTQ_M_U "vmovnt") | |
1059 | (VMOVNTQ_S "vmovnt") (VMOVNTQ_U "vmovnt") | |
5cbe0c09 | 1060 | (VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh") |
3fe5a244 | 1061 | (VMULHQ_S "vmulh") (VMULHQ_U "vmulh") |
195cc201 CL |
1062 | (VMULLBQ_INT_M_S "vmullb") (VMULLBQ_INT_M_U "vmullb") |
1063 | (VMULLBQ_INT_S "vmullb") (VMULLBQ_INT_U "vmullb") | |
1064 | (VMULLBQ_POLY_M_P "vmullb") (VMULLTQ_POLY_M_P "vmullt") | |
1065 | (VMULLBQ_POLY_P "vmullb") | |
1066 | (VMULLTQ_INT_M_S "vmullt") (VMULLTQ_INT_M_U "vmullt") | |
1067 | (VMULLTQ_INT_S "vmullt") (VMULLTQ_INT_U "vmullt") | |
1068 | (VMULLTQ_POLY_P "vmullt") | |
b0b3a5e9 CL |
1069 | (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul") |
1070 | (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul") | |
1071 | (VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul") | |
b74d6acf CL |
1072 | (VMVNQ_M_N_S "vmvn") (VMVNQ_M_N_U "vmvn") |
1073 | (VMVNQ_M_S "vmvn") (VMVNQ_M_U "vmvn") | |
1074 | (VMVNQ_N_S "vmvn") (VMVNQ_N_U "vmvn") | |
7734b991 CL |
1075 | (VNEGQ_M_F "vneg") |
1076 | (VNEGQ_M_S "vneg") | |
67e4e591 CL |
1077 | (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr") |
1078 | (VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr") | |
1079 | (VORRQ_N_S "vorr") (VORRQ_N_U "vorr") | |
f7196b72 | 1080 | (VPSELQ_S "vpsel") (VPSELQ_U "vpsel") (VPSELQ_F "vpsel") |
7734b991 CL |
1081 | (VQABSQ_M_S "vqabs") |
1082 | (VQABSQ_S "vqabs") | |
a7cbd5f9 | 1083 | (VQADDQ_M_N_S "vqadd") (VQADDQ_M_N_U "vqadd") |
5cbe0c09 | 1084 | (VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd") |
111f474f | 1085 | (VQADDQ_N_S "vqadd") (VQADDQ_N_U "vqadd") |
3fe5a244 | 1086 | (VQADDQ_S "vqadd") (VQADDQ_U "vqadd") |
5cbe0c09 | 1087 | (VQDMLADHQ_M_S "vqdmladh") |
3bf67ec9 | 1088 | (VQDMLADHQ_S "vqdmladh") |
5cbe0c09 | 1089 | (VQDMLADHXQ_M_S "vqdmladhx") |
3bf67ec9 | 1090 | (VQDMLADHXQ_S "vqdmladhx") |
a7cbd5f9 | 1091 | (VQDMLAHQ_M_N_S "vqdmlah") |
f2fd708a | 1092 | (VQDMLAHQ_N_S "vqdmlah") |
a7cbd5f9 | 1093 | (VQDMLASHQ_M_N_S "vqdmlash") |
f2fd708a | 1094 | (VQDMLASHQ_N_S "vqdmlash") |
5cbe0c09 | 1095 | (VQDMLSDHQ_M_S "vqdmlsdh") |
3bf67ec9 | 1096 | (VQDMLSDHQ_S "vqdmlsdh") |
5cbe0c09 | 1097 | (VQDMLSDHXQ_M_S "vqdmlsdhx") |
3bf67ec9 | 1098 | (VQDMLSDHXQ_S "vqdmlsdhx") |
a7cbd5f9 | 1099 | (VQDMULHQ_M_N_S "vqdmulh") |
5cbe0c09 | 1100 | (VQDMULHQ_M_S "vqdmulh") |
111f474f | 1101 | (VQDMULHQ_N_S "vqdmulh") |
3fe5a244 | 1102 | (VQDMULHQ_S "vqdmulh") |
c71b5c78 CL |
1103 | (VQDMULLBQ_M_N_S "vqdmullb") |
1104 | (VQDMULLBQ_M_S "vqdmullb") | |
1105 | (VQDMULLBQ_N_S "vqdmullb") | |
1106 | (VQDMULLBQ_S "vqdmullb") | |
1107 | (VQDMULLTQ_M_N_S "vqdmullt") | |
1108 | (VQDMULLTQ_M_S "vqdmullt") | |
1109 | (VQDMULLTQ_N_S "vqdmullt") | |
1110 | (VQDMULLTQ_S "vqdmullt") | |
7f49b4a0 CL |
1111 | (VQMOVNBQ_M_S "vqmovnb") (VQMOVNBQ_M_U "vqmovnb") |
1112 | (VQMOVNBQ_S "vqmovnb") (VQMOVNBQ_U "vqmovnb") | |
1113 | (VQMOVNTQ_M_S "vqmovnt") (VQMOVNTQ_M_U "vqmovnt") | |
1114 | (VQMOVNTQ_S "vqmovnt") (VQMOVNTQ_U "vqmovnt") | |
1115 | (VQMOVUNBQ_M_S "vqmovunb") | |
1116 | (VQMOVUNBQ_S "vqmovunb") | |
1117 | (VQMOVUNTQ_M_S "vqmovunt") | |
1118 | (VQMOVUNTQ_S "vqmovunt") | |
7734b991 CL |
1119 | (VQNEGQ_M_S "vqneg") |
1120 | (VQNEGQ_S "vqneg") | |
5cbe0c09 | 1121 | (VQRDMLADHQ_M_S "vqrdmladh") |
3bf67ec9 | 1122 | (VQRDMLADHQ_S "vqrdmladh") |
5cbe0c09 | 1123 | (VQRDMLADHXQ_M_S "vqrdmladhx") |
3bf67ec9 | 1124 | (VQRDMLADHXQ_S "vqrdmladhx") |
a7cbd5f9 | 1125 | (VQRDMLAHQ_M_N_S "vqrdmlah") |
f2fd708a | 1126 | (VQRDMLAHQ_N_S "vqrdmlah") |
a7cbd5f9 | 1127 | (VQRDMLASHQ_M_N_S "vqrdmlash") |
f2fd708a | 1128 | (VQRDMLASHQ_N_S "vqrdmlash") |
5cbe0c09 | 1129 | (VQRDMLSDHQ_M_S "vqrdmlsdh") |
3bf67ec9 | 1130 | (VQRDMLSDHQ_S "vqrdmlsdh") |
5cbe0c09 | 1131 | (VQRDMLSDHXQ_M_S "vqrdmlsdhx") |
3bf67ec9 | 1132 | (VQRDMLSDHXQ_S "vqrdmlsdhx") |
a7cbd5f9 | 1133 | (VQRDMULHQ_M_N_S "vqrdmulh") |
5cbe0c09 | 1134 | (VQRDMULHQ_M_S "vqrdmulh") |
111f474f | 1135 | (VQRDMULHQ_N_S "vqrdmulh") |
3fe5a244 | 1136 | (VQRDMULHQ_S "vqrdmulh") |
c4d4e62b | 1137 | (VQRSHLQ_M_N_S "vqrshl") (VQRSHLQ_M_N_U "vqrshl") |
5cbe0c09 | 1138 | (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl") |
c4d4e62b | 1139 | (VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl") |
3fe5a244 | 1140 | (VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl") |
e2f992f7 CL |
1141 | (VQRSHRNBQ_M_N_S "vqrshrnb") (VQRSHRNBQ_M_N_U "vqrshrnb") |
1142 | (VQRSHRNBQ_N_S "vqrshrnb") (VQRSHRNBQ_N_U "vqrshrnb") | |
1143 | (VQRSHRNTQ_M_N_S "vqrshrnt") (VQRSHRNTQ_M_N_U "vqrshrnt") | |
1144 | (VQRSHRNTQ_N_S "vqrshrnt") (VQRSHRNTQ_N_U "vqrshrnt") | |
8f5b7d21 CL |
1145 | (VQRSHRUNBQ_M_N_S "vqrshrunb") |
1146 | (VQRSHRUNBQ_N_S "vqrshrunb") | |
1147 | (VQRSHRUNTQ_M_N_S "vqrshrunt") | |
1148 | (VQRSHRUNTQ_N_S "vqrshrunt") | |
7e6c39a3 CL |
1149 | (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl") |
1150 | (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl") | |
5cbe0c09 | 1151 | (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl") |
7e6c39a3 CL |
1152 | (VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl") |
1153 | (VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl") | |
3fe5a244 | 1154 | (VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl") |
85c463f5 CL |
1155 | (VQSHLUQ_M_N_S "vqshlu") |
1156 | (VQSHLUQ_N_S "vqshlu") | |
e2f992f7 CL |
1157 | (VQSHRNBQ_M_N_S "vqshrnb") (VQSHRNBQ_M_N_U "vqshrnb") |
1158 | (VQSHRNBQ_N_S "vqshrnb") (VQSHRNBQ_N_U "vqshrnb") | |
1159 | (VQSHRNTQ_M_N_S "vqshrnt") (VQSHRNTQ_M_N_U "vqshrnt") | |
1160 | (VQSHRNTQ_N_S "vqshrnt") (VQSHRNTQ_N_U "vqshrnt") | |
8f5b7d21 CL |
1161 | (VQSHRUNBQ_M_N_S "vqshrunb") |
1162 | (VQSHRUNBQ_N_S "vqshrunb") | |
1163 | (VQSHRUNTQ_M_N_S "vqshrunt") | |
1164 | (VQSHRUNTQ_N_S "vqshrunt") | |
a7cbd5f9 | 1165 | (VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub") |
5cbe0c09 | 1166 | (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub") |
111f474f | 1167 | (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub") |
3fe5a244 | 1168 | (VQSUBQ_S "vqsub") (VQSUBQ_U "vqsub") |
0c1eb901 CL |
1169 | (VREV16Q_M_S "vrev16") (VREV16Q_M_U "vrev16") |
1170 | (VREV16Q_S "vrev16") (VREV16Q_U "vrev16") | |
1171 | (VREV32Q_M_S "vrev32") (VREV32Q_M_U "vrev32") (VREV32Q_M_F "vrev32") | |
1172 | (VREV32Q_S "vrev32") (VREV32Q_U "vrev32") (VREV32Q_F "vrev32") | |
1173 | (VREV64Q_M_S "vrev64") (VREV64Q_M_U "vrev64") (VREV64Q_M_F "vrev64") | |
1174 | (VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64") | |
5cbe0c09 | 1175 | (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd") |
3fe5a244 | 1176 | (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd") |
e18f715b CL |
1177 | (VRMLALDAVHAQ_P_S "vrmlaldavha") (VRMLALDAVHAQ_P_U "vrmlaldavha") |
1178 | (VRMLALDAVHAQ_S "vrmlaldavha") (VRMLALDAVHAQ_U "vrmlaldavha") | |
1179 | (VRMLALDAVHAXQ_P_S "vrmlaldavhax") | |
1180 | (VRMLALDAVHAXQ_S "vrmlaldavhax") | |
e044696f CL |
1181 | (VRMLALDAVHQ_P_S "vrmlaldavh") (VRMLALDAVHQ_P_U "vrmlaldavh") |
1182 | (VRMLALDAVHQ_S "vrmlaldavh") (VRMLALDAVHQ_U "vrmlaldavh") | |
1183 | (VRMLALDAVHXQ_P_S "vrmlaldavhx") | |
1184 | (VRMLALDAVHXQ_S "vrmlaldavhx") | |
e18f715b CL |
1185 | (VRMLSLDAVHAQ_P_S "vrmlsldavha") |
1186 | (VRMLSLDAVHAQ_S "vrmlsldavha") | |
1187 | (VRMLSLDAVHAXQ_P_S "vrmlsldavhax") | |
1188 | (VRMLSLDAVHAXQ_S "vrmlsldavhax") | |
e044696f CL |
1189 | (VRMLSLDAVHQ_P_S "vrmlsldavh") |
1190 | (VRMLSLDAVHQ_S "vrmlsldavh") | |
1191 | (VRMLSLDAVHXQ_P_S "vrmlsldavhx") | |
1192 | (VRMLSLDAVHXQ_S "vrmlsldavhx") | |
5cbe0c09 | 1193 | (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh") |
3fe5a244 | 1194 | (VRMULHQ_S "vrmulh") (VRMULHQ_U "vrmulh") |
7734b991 CL |
1195 | (VRNDAQ_F "vrnda") (VRNDAQ_M_F "vrnda") |
1196 | (VRNDMQ_F "vrndm") (VRNDMQ_M_F "vrndm") | |
1197 | (VRNDNQ_F "vrndn") (VRNDNQ_M_F "vrndn") | |
1198 | (VRNDPQ_F "vrndp") (VRNDPQ_M_F "vrndp") | |
1199 | (VRNDQ_F "vrnd") (VRNDQ_M_F "vrnd") | |
1200 | (VRNDXQ_F "vrndx") (VRNDXQ_M_F "vrndx") | |
c4d4e62b | 1201 | (VRSHLQ_M_N_S "vrshl") (VRSHLQ_M_N_U "vrshl") |
5cbe0c09 | 1202 | (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl") |
c4d4e62b | 1203 | (VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl") |
3fe5a244 | 1204 | (VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl") |
e2f992f7 CL |
1205 | (VRSHRNBQ_M_N_S "vrshrnb") (VRSHRNBQ_M_N_U "vrshrnb") |
1206 | (VRSHRNBQ_N_S "vrshrnb") (VRSHRNBQ_N_U "vrshrnb") | |
1207 | (VRSHRNTQ_M_N_S "vrshrnt") (VRSHRNTQ_M_N_U "vrshrnt") | |
1208 | (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt") | |
6bb8a5bd CL |
1209 | (VRSHRQ_M_N_S "vrshr") (VRSHRQ_M_N_U "vrshr") |
1210 | (VRSHRQ_N_S "vrshr") (VRSHRQ_N_U "vrshr") | |
2cc50fd9 CL |
1211 | (VSHLLBQ_M_N_S "vshllb") (VSHLLBQ_M_N_U "vshllb") |
1212 | (VSHLLBQ_N_S "vshllb") (VSHLLBQ_N_U "vshllb") | |
1213 | (VSHLLTQ_M_N_S "vshllt") (VSHLLTQ_M_N_U "vshllt") | |
1214 | (VSHLLTQ_N_S "vshllt") (VSHLLTQ_N_U "vshllt") | |
7e6c39a3 CL |
1215 | (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl") |
1216 | (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl") | |
5cbe0c09 | 1217 | (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl") |
7e6c39a3 CL |
1218 | (VSHLQ_N_S "vshl") (VSHLQ_N_U "vshl") |
1219 | (VSHLQ_R_S "vshl") (VSHLQ_R_U "vshl") | |
1220 | (VSHLQ_S "vshl") (VSHLQ_U "vshl") | |
e2f992f7 CL |
1221 | (VSHRNBQ_M_N_S "vshrnb") (VSHRNBQ_M_N_U "vshrnb") |
1222 | (VSHRNBQ_N_S "vshrnb") (VSHRNBQ_N_U "vshrnb") | |
1223 | (VSHRNTQ_M_N_S "vshrnt") (VSHRNTQ_M_N_U "vshrnt") | |
1224 | (VSHRNTQ_N_S "vshrnt") (VSHRNTQ_N_U "vshrnt") | |
6bb8a5bd CL |
1225 | (VSHRQ_M_N_S "vshr") (VSHRQ_M_N_U "vshr") |
1226 | (VSHRQ_N_S "vshr") (VSHRQ_N_U "vshr") | |
3767c7fe CL |
1227 | (VSLIQ_M_N_S "vsli") (VSLIQ_M_N_U "vsli") |
1228 | (VSLIQ_N_S "vsli") (VSLIQ_N_U "vsli") | |
be373b54 CL |
1229 | (VSRIQ_M_N_S "vsri") (VSRIQ_M_N_U "vsri") |
1230 | (VSRIQ_N_S "vsri") (VSRIQ_N_U "vsri") | |
b0b3a5e9 CL |
1231 | (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub") |
1232 | (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub") | |
1233 | (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub") | |
1234 | ]) | |
1235 | ||
e2f992f7 | 1236 | (define_int_attr isu [ |
b22e70e8 | 1237 | (UNSPEC_VCADD90 "i") (UNSPEC_VCADD270 "i") |
7734b991 | 1238 | (VABSQ_M_S "s") |
68ec7d75 SMW |
1239 | (VCADDQ_ROT270_M "i") |
1240 | (VCADDQ_ROT90_M "i") | |
7734b991 CL |
1241 | (VCLSQ_M_S "s") |
1242 | (VCLZQ_M_S "i") | |
1243 | (VCLZQ_M_U "i") | |
6a08718a CL |
1244 | (VCMPCSQ_M_N_U "u") |
1245 | (VCMPCSQ_M_U "u") | |
1246 | (VCMPEQQ_M_N_S "i") | |
1247 | (VCMPEQQ_M_N_U "i") | |
1248 | (VCMPEQQ_M_S "i") | |
1249 | (VCMPEQQ_M_U "i") | |
1250 | (VCMPGEQ_M_N_S "s") | |
1251 | (VCMPGEQ_M_S "s") | |
1252 | (VCMPGTQ_M_N_S "s") | |
1253 | (VCMPGTQ_M_S "s") | |
1254 | (VCMPHIQ_M_N_U "u") | |
1255 | (VCMPHIQ_M_U "u") | |
1256 | (VCMPLEQ_M_N_S "s") | |
1257 | (VCMPLEQ_M_S "s") | |
1258 | (VCMPLTQ_M_N_S "s") | |
1259 | (VCMPLTQ_M_S "s") | |
1260 | (VCMPNEQ_M_N_S "i") | |
1261 | (VCMPNEQ_M_N_U "i") | |
1262 | (VCMPNEQ_M_S "i") | |
1263 | (VCMPNEQ_M_U "i") | |
b22e70e8 CL |
1264 | (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S "s") |
1265 | (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s") | |
7f49b4a0 CL |
1266 | (VMOVNBQ_M_S "i") (VMOVNBQ_M_U "i") |
1267 | (VMOVNBQ_S "i") (VMOVNBQ_U "i") | |
1268 | (VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i") | |
1269 | (VMOVNTQ_S "i") (VMOVNTQ_U "i") | |
195cc201 CL |
1270 | (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") |
1271 | (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") | |
7734b991 CL |
1272 | (VNEGQ_M_S "s") |
1273 | (VQABSQ_M_S "s") | |
7f49b4a0 CL |
1274 | (VQMOVNBQ_M_S "s") (VQMOVNBQ_M_U "u") |
1275 | (VQMOVNBQ_S "s") (VQMOVNBQ_U "u") | |
1276 | (VQMOVNTQ_M_S "s") (VQMOVNTQ_M_U "u") | |
1277 | (VQMOVNTQ_S "s") (VQMOVNTQ_U "u") | |
1278 | (VQMOVUNBQ_M_S "s") | |
1279 | (VQMOVUNBQ_S "s") | |
1280 | (VQMOVUNTQ_M_S "s") | |
1281 | (VQMOVUNTQ_S "s") | |
7734b991 | 1282 | (VQNEGQ_M_S "s") |
e2f992f7 CL |
1283 | (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") |
1284 | (VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u") | |
1285 | (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") | |
1286 | (VQRSHRNTQ_N_S "s") (VQRSHRNTQ_N_U "u") | |
8f5b7d21 CL |
1287 | (VQRSHRUNBQ_M_N_S "s") |
1288 | (VQRSHRUNBQ_N_S "s") | |
1289 | (VQRSHRUNTQ_M_N_S "s") | |
1290 | (VQRSHRUNTQ_N_S "s") | |
e2f992f7 CL |
1291 | (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u") |
1292 | (VQSHRNBQ_N_S "s") (VQSHRNBQ_N_U "u") | |
1293 | (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u") | |
1294 | (VQSHRNTQ_N_S "s") (VQSHRNTQ_N_U "u") | |
8f5b7d21 CL |
1295 | (VQSHRUNBQ_M_N_S "s") |
1296 | (VQSHRUNBQ_N_S "s") | |
1297 | (VQSHRUNTQ_M_N_S "s") | |
1298 | (VQSHRUNTQ_N_S "s") | |
e2f992f7 CL |
1299 | (VRSHRNBQ_M_N_S "i") (VRSHRNBQ_M_N_U "i") |
1300 | (VRSHRNBQ_N_S "i") (VRSHRNBQ_N_U "i") | |
1301 | (VRSHRNTQ_M_N_S "i") (VRSHRNTQ_M_N_U "i") | |
1302 | (VRSHRNTQ_N_S "i") (VRSHRNTQ_N_U "i") | |
1303 | (VSHRNBQ_M_N_S "i") (VSHRNBQ_M_N_U "i") | |
1304 | (VSHRNBQ_N_S "i") (VSHRNBQ_N_U "i") | |
1305 | (VSHRNTQ_M_N_S "i") (VSHRNTQ_M_N_U "i") | |
1306 | (VSHRNTQ_N_S "i") (VSHRNTQ_N_U "i") | |
1307 | ]) | |
1308 | ||
7734b991 CL |
1309 | (define_int_attr mve_mnemo [ |
1310 | (VABSQ_M_S "vabs") (VABSQ_M_F "vabs") | |
1311 | (VNEGQ_M_S "vneg") (VNEGQ_M_F "vneg") | |
1312 | (VRNDAQ_F "vrinta") (VRNDAQ_M_F "vrinta") | |
1313 | (VRNDMQ_F "vrintm") (VRNDMQ_M_F "vrintm") | |
1314 | (VRNDNQ_F "vrintn") (VRNDNQ_M_F "vrintn") | |
1315 | (VRNDPQ_F "vrintp") (VRNDPQ_M_F "vrintp") | |
1316 | (VRNDQ_F "vrintz") (VRNDQ_M_F "vrintz") | |
1317 | (VRNDXQ_F "vrintx") (VRNDXQ_M_F "vrintx") | |
1318 | ]) | |
1319 | ||
728dc153 | 1320 | ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows |
f3b3331a | 1321 | ;; a stack pointer operand. The minus operation is a candidate for an rsub |
004d3809 RE |
1322 | ;; and hence only plus is supported. |
1323 | (define_code_attr t2_binop0 | |
1324 | [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) | |
1325 | ||
728dc153 | 1326 | ;; The instruction to use when a SHIFTABLE_OPS has a shift operation as |
004d3809 RE |
1327 | ;; its first operand. |
1328 | (define_code_attr arith_shift_insn | |
1329 | [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) | |
1330 | ||
381811fa KT |
1331 | (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") |
1332 | (gtu "gt") (geu "ge")]) | |
1333 | ||
d083fbf7 CL |
1334 | (define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") |
1335 | (gtu "hi") (geu "cs") (ne "ne")]) | |
1336 | ||
381811fa KT |
1337 | (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) |
1338 | ||
d083fbf7 CL |
1339 | (define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s") |
1340 | (gtu "u") (geu "u") (ne "i")]) | |
1341 | ||
06e95715 KT |
1342 | (define_code_attr vfml_op [(plus "a") (minus "s")]) |
1343 | ||
e56d199b KT |
1344 | (define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")]) |
1345 | ||
1dd4fe1f KT |
1346 | ;;---------------------------------------------------------------------------- |
1347 | ;; Int iterators | |
1348 | ;;---------------------------------------------------------------------------- | |
1349 | ||
1350 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
1351 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
1352 | ||
55a9b91b MW |
1353 | (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE |
1354 | UNSPEC_VCLT UNSPEC_VCLE]) | |
381811fa | 1355 | |
55a9b91b MW |
1356 | (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT |
1357 | UNSPEC_VCALE UNSPEC_VCALT]) | |
1358 | ||
ababd936 KT |
1359 | (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) |
1360 | ||
79739965 KT |
1361 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
1362 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
1363 | ||
e9e67af1 KT |
1364 | (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) |
1365 | ||
94f0f2cc JG |
1366 | (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) |
1367 | ||
1368 | (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) | |
1369 | ||
1370 | (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U | |
1371 | UNSPEC_VHADD_S UNSPEC_VHADD_U]) | |
1372 | ||
1373 | (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) | |
1374 | ||
1375 | (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) | |
1376 | ||
1377 | (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) | |
1378 | ||
1379 | (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) | |
1380 | ||
1381 | (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) | |
1382 | ||
1383 | (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) | |
1384 | ||
1385 | (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) | |
1386 | ||
1387 | (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) | |
1388 | ||
1389 | (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) | |
1390 | ||
1391 | (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) | |
1392 | ||
1393 | (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) | |
1394 | ||
1395 | (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) | |
1396 | ||
1397 | (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) | |
1398 | ||
1399 | (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) | |
1400 | ||
1401 | (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) | |
1402 | ||
84ae7213 PW |
1403 | (define_int_iterator VABAL [UNSPEC_VABAL_S UNSPEC_VABAL_U]) |
1404 | ||
94f0f2cc JG |
1405 | (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) |
1406 | ||
1407 | (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) | |
1408 | ||
1409 | (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U | |
1410 | UNSPEC_VMIN UNSPEC_VMIN_U]) | |
1411 | ||
1412 | (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) | |
1413 | ||
0a18c19f DS |
1414 | (define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) |
1415 | ||
94f0f2cc JG |
1416 | (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) |
1417 | ||
1418 | (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) | |
1419 | ||
1420 | (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U | |
1421 | UNSPEC_VPMIN UNSPEC_VPMIN_U]) | |
1422 | ||
1423 | (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) | |
1424 | ||
1425 | (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) | |
1426 | ||
1427 | (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) | |
1428 | ||
d403b8d4 MW |
1429 | (define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N]) |
1430 | ||
1431 | (define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N]) | |
1432 | ||
1433 | (define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U | |
1434 | UNSPEC_VCVTM_S UNSPEC_VCVTM_U | |
1435 | UNSPEC_VCVTN_S UNSPEC_VCVTN_U | |
1436 | UNSPEC_VCVTP_S UNSPEC_VCVTP_U]) | |
1437 | ||
1438 | (define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U]) | |
1439 | ||
1440 | ;; Operators for FP16 instructions. | |
1441 | (define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA | |
1442 | UNSPEC_VRNDM UNSPEC_VRNDN | |
1443 | UNSPEC_VRNDP UNSPEC_VRNDX]) | |
1444 | ||
94f0f2cc JG |
1445 | (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) |
1446 | ||
1447 | (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) | |
1448 | ||
1449 | (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U | |
1450 | UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) | |
1451 | ||
1452 | (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U | |
1453 | UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) | |
1454 | ||
1455 | (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N | |
1456 | UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) | |
1457 | ||
1458 | (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) | |
1459 | ||
1460 | (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N | |
1461 | UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) | |
1462 | ||
1463 | (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) | |
1464 | ||
1465 | (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) | |
1466 | ||
1467 | (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) | |
1468 | ||
1469 | (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N | |
1470 | UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) | |
1471 | ||
582e2e43 KT |
1472 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
1473 | UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) | |
1474 | ||
4c12dc05 | 1475 | (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) |
021b5e6b | 1476 | |
4c12dc05 ST |
1477 | (define_int_iterator CRYPTO_AES [UNSPEC_AESD UNSPEC_AESE]) |
1478 | ||
1479 | (define_int_iterator CRYPTO_BINARY [UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) | |
021b5e6b KT |
1480 | |
1481 | (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H | |
1482 | UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) | |
1483 | ||
1484 | (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M | |
1485 | UNSPEC_SHA1P]) | |
1486 | ||
53cd0ac6 KT |
1487 | (define_int_iterator USXTB16 [UNSPEC_SXTB16 UNSPEC_UXTB16]) |
1488 | (define_int_iterator SIMD32_NOGE_BINOP | |
1489 | [UNSPEC_QADD8 UNSPEC_QSUB8 UNSPEC_SHADD8 | |
1490 | UNSPEC_SHSUB8 UNSPEC_UHADD8 UNSPEC_UHSUB8 | |
1491 | UNSPEC_UQADD8 UNSPEC_UQSUB8 | |
1492 | UNSPEC_QADD16 UNSPEC_QASX UNSPEC_QSAX | |
1493 | UNSPEC_QSUB16 UNSPEC_SHADD16 UNSPEC_SHASX | |
1494 | UNSPEC_SHSAX UNSPEC_SHSUB16 UNSPEC_UHADD16 | |
1495 | UNSPEC_UHASX UNSPEC_UHSAX UNSPEC_UHSUB16 | |
1496 | UNSPEC_UQADD16 UNSPEC_UQASX UNSPEC_UQSAX | |
1497 | UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX | |
1498 | UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8]) | |
1499 | ||
2b5b5e24 KT |
1500 | (define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX |
1501 | UNSPEC_SMLSLD UNSPEC_SMLSLDX]) | |
1502 | ||
08836731 KT |
1503 | (define_int_iterator SMLAWBT [UNSPEC_SMLAWB UNSPEC_SMLAWT]) |
1504 | ||
16155ccf KT |
1505 | (define_int_iterator SIMD32_GE [UNSPEC_SADD8 UNSPEC_SSUB8 UNSPEC_UADD8 |
1506 | UNSPEC_USUB8 UNSPEC_SADD16 UNSPEC_SASX | |
1507 | UNSPEC_SSAX UNSPEC_SSUB16 UNSPEC_UADD16 | |
1508 | UNSPEC_UASX UNSPEC_USAX UNSPEC_USUB16]) | |
1509 | ||
65dd610d KT |
1510 | (define_int_iterator SIMD32_TERNOP_Q [UNSPEC_SMLAD UNSPEC_SMLADX UNSPEC_SMLSD |
1511 | UNSPEC_SMLSDX]) | |
1512 | ||
1513 | (define_int_iterator SIMD32_BINOP_Q [UNSPEC_SMUAD UNSPEC_SMUADX]) | |
1514 | ||
0775830a KT |
1515 | (define_int_iterator USSAT16 [UNSPEC_SSAT16 UNSPEC_USAT16]) |
1516 | ||
5f2ca3b2 MW |
1517 | (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) |
1518 | ||
55a9b91b MW |
1519 | (define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE]) |
1520 | ||
f8e109ba TC |
1521 | (define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U]) |
1522 | ||
f348846e SMW |
1523 | (define_int_iterator DOTPROD_I8MM [UNSPEC_DOT_US UNSPEC_DOT_SU]) |
1524 | ||
06e95715 KT |
1525 | (define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI]) |
1526 | ||
c2b7062d TC |
1527 | (define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270]) |
1528 | (define_int_iterator VCMLA [UNSPEC_VCMLA UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270]) | |
1529 | ||
436016f4 DZ |
1530 | (define_int_iterator MATMUL [UNSPEC_MATMUL_S UNSPEC_MATMUL_U UNSPEC_MATMUL_US]) |
1531 | ||
2d22ab64 KT |
1532 | (define_int_iterator BF_MA [UNSPEC_BFMAB UNSPEC_BFMAT]) |
1533 | ||
ef684c78 MM |
1534 | (define_int_iterator CDE_VCX [UNSPEC_VCDE UNSPEC_VCDEA]) |
1535 | ||
ceddf62c SN |
1536 | ;;---------------------------------------------------------------------------- |
1537 | ;; Mode attributes | |
1538 | ;;---------------------------------------------------------------------------- | |
1539 | ||
3cff0135 TP |
1540 | ;; Determine name of atomic compare and swap from success result mode. This |
1541 | ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. | |
1542 | (define_mode_attr arch [(CC_Z "32") (SI "t1")]) | |
1543 | ||
ceddf62c SN |
1544 | ;; Determine element size suffix from vector mode. |
1545 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
1546 | ||
1547 | ;; vtbl<n> suffix for NEON vector modes. | |
1548 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
1549 | ||
ccf041da ES |
1550 | ;; Suffix for x2 variants of vld1 and vst1. |
1551 | (define_mode_attr VMEMX2_q [(TI "") (OI "q")]) | |
1552 | ||
2e87b2f4 SMW |
1553 | ;; fp16 or bf16 marker for 16-bit float modes. |
1554 | (define_mode_attr fporbf [(HF "fp16") (BF "bf16")]) | |
1555 | ||
ceddf62c SN |
1556 | ;; (Opposite) mode to convert to/from for NEON mode conversions. |
1557 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
1558 | (V4SI "V4SF") (V4SF "V4SI")]) | |
1559 | ||
5bf4dcf2 DP |
1560 | ;; As above but in lower case. |
1561 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
1562 | (V4SI "v4sf") (V4SF "v4si")]) | |
1563 | ||
55a9b91b MW |
1564 | ;; (Opposite) mode to convert to/from for vector-half mode conversions. |
1565 | (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") | |
1566 | (V8HI "V8HF") (V8HF "V8HI")]) | |
76068651 CL |
1567 | (define_mode_attr VH_cvtto [(V4HI "v4hf") (V4HF "v4hi") |
1568 | (V8HI "v8hf") (V8HF "v8hi")]) | |
55a9b91b | 1569 | |
ceddf62c SN |
1570 | ;; Define element mode for each vector mode. |
1571 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
4b644867 AL |
1572 | (V4HI "HI") (V8HI "HI") |
1573 | (V4HF "HF") (V8HF "HF") | |
17a13507 | 1574 | (V4BF "BF") (V8BF "BF") |
67d56b27 AC |
1575 | (V2SI "SI") (V4SI "SI") |
1576 | (V2SF "SF") (V4SF "SF") | |
1577 | (DI "DI") (V2DI "DI") | |
1578 | (V2DF "DF")]) | |
ceddf62c | 1579 | |
ff03930a JJ |
1580 | ;; As above but in lower case. |
1581 | (define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi") | |
1582 | (V4HI "hi") (V8HI "hi") | |
1583 | (V4HF "hf") (V8HF "hf") | |
17a13507 | 1584 | (V4BF "bf") (V8BF "bf") |
ff03930a JJ |
1585 | (V2SI "si") (V4SI "si") |
1586 | (V2SF "sf") (V4SF "sf") | |
1587 | (DI "di") (V2DI "di")]) | |
1588 | ||
ceddf62c SN |
1589 | ;; Element modes for vector extraction, padded up to register size. |
1590 | ||
1591 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
1592 | (V4HI "SI") (V8HI "SI") | |
1593 | (V2SI "SI") (V4SI "SI") | |
1594 | (V2SF "SF") (V4SF "SF") | |
1595 | (DI "DI") (V2DI "DI")]) | |
1596 | ||
1597 | ;; Mode of pair of elements for each vector mode, to define transfer | |
1598 | ;; size for structure lane/dup loads and stores. | |
6308e208 RS |
1599 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
1600 | (V4HI "SI") (V8HI "SI") | |
4b644867 | 1601 | (V4HF "SF") (V8HF "SF") |
17a13507 | 1602 | (V4BF "BF") (V8BF "BF") |
ceddf62c SN |
1603 | (V2SI "V2SI") (V4SI "V2SI") |
1604 | (V2SF "V2SF") (V4SF "V2SF") | |
1605 | (DI "V2DI") (V2DI "V2DI")]) | |
1606 | ||
06e95715 KT |
1607 | ;; Mode mapping for VFM[A,S]L instructions. |
1608 | (define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")]) | |
1609 | ||
1610 | ;; Mode mapping for VFM[A,S]L instructions for the vec_select result. | |
1611 | (define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")]) | |
1612 | ||
eccf4d70 KT |
1613 | ;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms. |
1614 | (define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")]) | |
1615 | ||
1616 | ;; Same as the above, but lowercase. | |
1617 | (define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")]) | |
1618 | ||
ceddf62c | 1619 | ;; Similar, for three elements. |
6308e208 RS |
1620 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
1621 | (V4HI "BLK") (V8HI "BLK") | |
4b644867 | 1622 | (V4HF "BLK") (V8HF "BLK") |
17a13507 | 1623 | (V4BF "BLK") (V8BF "BLK") |
6308e208 RS |
1624 | (V2SI "BLK") (V4SI "BLK") |
1625 | (V2SF "BLK") (V4SF "BLK") | |
1626 | (DI "EI") (V2DI "EI")]) | |
ceddf62c SN |
1627 | |
1628 | ;; Similar, for four elements. | |
1629 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
6308e208 | 1630 | (V4HI "V4HI") (V8HI "V4HI") |
4b644867 | 1631 | (V4HF "V4HF") (V8HF "V4HF") |
17a13507 | 1632 | (V4BF "V4BF") (V8BF "V4BF") |
ceddf62c SN |
1633 | (V2SI "V4SI") (V4SI "V4SI") |
1634 | (V2SF "V4SF") (V4SF "V4SF") | |
1635 | (DI "OI") (V2DI "OI")]) | |
1636 | ||
1637 | ;; Register width from element mode | |
1638 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
55a9b91b MW |
1639 | (V4HI "P") (V8HI "q") |
1640 | (V4HF "P") (V8HF "q") | |
17a13507 | 1641 | (V4BF "P") (V8BF "q") |
55a9b91b MW |
1642 | (V2SI "P") (V4SI "q") |
1643 | (V2SF "P") (V4SF "q") | |
1644 | (DI "P") (V2DI "q") | |
07b9bfd0 | 1645 | (V2HF "") (SF "") (SI "") |
06e95715 KT |
1646 | (DF "P") (HF "")]) |
1647 | ||
1648 | ;; Output template to select the high VFP register of a mult-register value. | |
1649 | (define_mode_attr V_hi [(V2SF "p") (V4SF "f")]) | |
1650 | ||
1651 | ;; Output template to select the low VFP register of a mult-register value. | |
1652 | (define_mode_attr V_lo [(V2SF "") (V4SF "e")]) | |
ceddf62c | 1653 | |
eccf4d70 KT |
1654 | ;; Helper attribute for printing output templates for awkward forms of |
1655 | ;; vfmlal/vfmlsl intrinsics. | |
1656 | (define_mode_attr V_lane_reg [(V2SF "") (V4SF "P")]) | |
1657 | ||
ceddf62c SN |
1658 | ;; Wider modes with the same number of elements. |
1659 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
1660 | ||
1661 | ;; Narrower modes with the same number of elements. | |
1662 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
1663 | ||
0f38f229 TB |
1664 | ;; Narrower modes with double the number of elements. |
1665 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
1666 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
1667 | ||
ceddf62c SN |
1668 | ;; Modes with half the number of equal-sized elements. |
1669 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
4b644867 AL |
1670 | (V8HF "V4HF") (V4SI "V2SI") |
1671 | (V4SF "V2SF") (V2DF "DF") | |
17a13507 MI |
1672 | (V2DI "DI") (V4HF "HF") |
1673 | (V4BF "BF") (V8BF "V4BF")]) | |
ceddf62c SN |
1674 | |
1675 | ;; Same, but lower-case. | |
1676 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
1677 | (V4SI "v2si") (V4SF "v2sf") | |
1678 | (V2DI "di")]) | |
1679 | ||
1680 | ;; Modes with twice the number of equal-sized elements. | |
1681 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
4b644867 AL |
1682 | (V2SI "V4SI") (V4HF "V8HF") |
1683 | (V2SF "V4SF") (DF "V2DF") | |
17a13507 | 1684 | (DI "V2DI") (V4BF "V8BF")]) |
ceddf62c SN |
1685 | |
1686 | ;; Same, but lower-case. | |
1687 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
1688 | (V2SI "v4si") (V2SF "v4sf") | |
1689 | (DI "v2di")]) | |
1690 | ||
1691 | ;; Modes with double-width elements. | |
1692 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
1693 | (V4HI "V2SI") (V8HI "V4SI") | |
1694 | (V2SI "DI") (V4SI "V2DI")]) | |
1695 | ||
1696 | ;; Double-sized modes with the same element size. | |
1697 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
1698 | ;; even when the first one is quad. | |
1699 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
b1a970a5 MW |
1700 | (V4SI "V2SI") (V4SF "V2SF") |
1701 | (V8QI "V8QI") (V4HI "V4HI") | |
1702 | (V2SI "V2SI") (V2SF "V2SF") | |
17a13507 | 1703 | (V8BF "V4BF") (V4BF "V4BF") |
b1a970a5 | 1704 | (V8HF "V4HF") (V4HF "V4HF")]) |
ceddf62c SN |
1705 | |
1706 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
1707 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
4b644867 | 1708 | (V4HI "V4HI") (V8HI "V8HI") |
ceddf62c | 1709 | (V2SI "V2SI") (V4SI "V4SI") |
4b644867 | 1710 | (V4HF "V4HI") (V8HF "V8HI") |
17a13507 | 1711 | (V4BF "V4HI") (V8BF "V8HI") |
ceddf62c SN |
1712 | (V2SF "V2SI") (V4SF "V4SI") |
1713 | (DI "DI") (V2DI "V2DI")]) | |
1714 | ||
f35c297f KT |
1715 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
1716 | (V4HI "v4hi") (V8HI "v8hi") | |
1717 | (V2SI "v2si") (V4SI "v4si") | |
76068651 | 1718 | (V4HF "v4hi") (V8HF "v8hi") |
f35c297f KT |
1719 | (DI "di") (V2DI "v2di") |
1720 | (V2SF "v2si") (V4SF "v4si")]) | |
1721 | ||
ceddf62c SN |
1722 | ;; Get element type from double-width mode, for operations where we |
1723 | ;; don't care about signedness. | |
1724 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
55a9b91b MW |
1725 | (V4HI "i16") (V8HI "i16") |
1726 | (V2SI "i32") (V4SI "i32") | |
1727 | (DI "i64") (V2DI "i64") | |
1728 | (V2SF "f32") (V4SF "f32") | |
1729 | (SF "f32") (DF "f64") | |
1730 | (HF "f16") (V4HF "f16") | |
1731 | (V8HF "f16")]) | |
ceddf62c SN |
1732 | |
1733 | ;; Same, but for operations which work on signed values. | |
1734 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
55a9b91b MW |
1735 | (V4HI "s16") (V8HI "s16") |
1736 | (V2SI "s32") (V4SI "s32") | |
1737 | (DI "s64") (V2DI "s64") | |
1738 | (V2SF "f32") (V4SF "f32") | |
1739 | (HF "f16") (V4HF "f16") | |
1740 | (V8HF "f16")]) | |
ceddf62c SN |
1741 | |
1742 | ;; Same, but for operations which work on unsigned values. | |
1743 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
1744 | (V4HI "u16") (V8HI "u16") | |
1745 | (V2SI "u32") (V4SI "u32") | |
1746 | (DI "u64") (V2DI "u64") | |
1747 | (V2SF "f32") (V4SF "f32")]) | |
1748 | ||
1749 | ;; Element types for extraction of unsigned scalars. | |
1750 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
1751 | (V4HI "u16") (V8HI "u16") | |
1752 | (V2SI "32") (V4SI "32") | |
4b644867 | 1753 | (V4HF "u16") (V8HF "u16") |
17a13507 | 1754 | (V4BF "u16") (V8BF "u16") |
ceddf62c SN |
1755 | (V2SF "32") (V4SF "32")]) |
1756 | ||
1757 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
55a9b91b MW |
1758 | (V4HI "16") (V8HI "16") |
1759 | (V2SI "32") (V4SI "32") | |
1760 | (DI "64") (V2DI "64") | |
4b644867 | 1761 | (V4HF "16") (V8HF "16") |
17a13507 | 1762 | (V4BF "16") (V8BF "16") |
55a9b91b | 1763 | (V2SF "32") (V4SF "32")]) |
ceddf62c | 1764 | |
f7379e5e | 1765 | (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") |
55a9b91b MW |
1766 | (V4HI "h") (V8HI "h") |
1767 | (V2SI "s") (V4SI "s") | |
1768 | (DI "d") (V2DI "d") | |
1769 | (V2SF "s") (V4SF "s") | |
1770 | (V2SF "s") (V4SF "s")]) | |
1771 | ||
1772 | (define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s") | |
1773 | (V4HF "s") (V8HF "s") | |
1774 | (HF "s")]) | |
f7379e5e | 1775 | |
ceddf62c SN |
1776 | ;; Element sizes for duplicating ARM registers to all elements of a vector. |
1777 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
1778 | ||
1779 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
1780 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
1781 | (V4HI "TI") (V8HI "OI") | |
1782 | (V2SI "TI") (V4SI "OI") | |
1783 | (V2SF "TI") (V4SF "OI") | |
1784 | (DI "TI") (V2DI "OI")]) | |
1785 | ||
1786 | ;; Same, but lower-case. | |
1787 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
1788 | (V4HI "ti") (V8HI "oi") | |
1789 | (V2SI "ti") (V4SI "oi") | |
1790 | (V2SF "ti") (V4SF "oi") | |
1791 | (DI "ti") (V2DI "oi")]) | |
1792 | ||
1793 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
1794 | ;; names which we don't want to define). | |
1795 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
1796 | (V4HI "") (V8HI "") | |
1797 | (V2SI "") (V4SI "") | |
1798 | (V2SF "") (V4SF "") | |
1799 | (DI "_neon") (V2DI "")]) | |
1800 | ||
8e6d0dba DZ |
1801 | ;; To select the low 64 bits of a vector. |
1802 | (define_mode_attr V_bf_low [(V4BF "P") (V8BF "e")]) | |
1803 | ||
1804 | ;; To generate intermediate modes for BF16 scalar convert. | |
1805 | (define_mode_attr V_bf_cvt_m [(V2SI "BF") (SF "V2SI")]) | |
1806 | ||
ceddf62c SN |
1807 | |
1808 | ;; Scalars to be presented to scalar multiplication instructions | |
1809 | ;; must satisfy the following constraints. | |
1810 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
1811 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
1812 | ||
1813 | ;; This mode attribute is used to obtain the correct register constraints. | |
1814 | ||
1815 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
55a9b91b MW |
1816 | (V8HI "x") (V4SI "t") (V4SF "t") |
1817 | (V8HF "x") (V4HF "x")]) | |
ceddf62c | 1818 | |
003bb7f3 | 1819 | ;; Predicates used for setting type for neon instructions |
ceddf62c SN |
1820 | |
1821 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
55a9b91b MW |
1822 | (V4HI "false") (V8HI "false") |
1823 | (V2SI "false") (V4SI "false") | |
1824 | (V4HF "true") (V8HF "true") | |
1825 | (V2SF "true") (V4SF "true") | |
1826 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
1827 | |
1828 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
b1a970a5 MW |
1829 | (V4HI "true") (V8HI "true") |
1830 | (V2SI "false") (V4SI "false") | |
1831 | (V2SF "false") (V4SF "false") | |
1832 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
1833 | |
1834 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
55a9b91b MW |
1835 | (V4HI "true") (V8HI "false") |
1836 | (V2SI "true") (V4SI "false") | |
1837 | (V2SF "true") (V4SF "false") | |
1838 | (DI "true") (V2DI "false") | |
17a13507 | 1839 | (V4BF "true") (V8BF "false") |
b1a970a5 | 1840 | (V4HF "true") (V8HF "false")]) |
ceddf62c SN |
1841 | |
1842 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
4b644867 | 1843 | (V4HF "4") (V8HF "8") |
17a13507 | 1844 | (V4BF "4") (V8BF "8") |
ceddf62c SN |
1845 | (V4HI "4") (V8HI "8") |
1846 | (V2SI "2") (V4SI "4") | |
1847 | (V2SF "2") (V4SF "4") | |
0f38f229 TB |
1848 | (DI "1") (V2DI "2") |
1849 | (DF "1") (V2DF "2")]) | |
ceddf62c | 1850 | |
46b57af1 TB |
1851 | ;; Same as V_widen, but lower-case. |
1852 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
1853 | ||
1854 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
1855 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c | 1856 | |
da0a441d BS |
1857 | ;; Conditions to be used in extend<mode>di patterns. |
1858 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
1859 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
1860 | (QI "&& arm_arch6")]) | |
8d4f1548 | 1861 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
c9cdcaa5 BS |
1862 | (HI "nonimmediate_operand") |
1863 | (QI "nonimmediate_operand")]) | |
8d4f1548 RR |
1864 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
1865 | (HI "nonimmediate_operand") | |
1866 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
5c7c6c5f WD |
1867 | (define_mode_attr qhs_extenddi_cstr [(SI "0,r,r") (HI "0,rm,rm") (QI "0,rUq,rm")]) |
1868 | (define_mode_attr qhs_zextenddi_cstr [(SI "0,r") (HI "0,rm") (QI "0,rm")]) | |
da0a441d | 1869 | |
655b30bf JB |
1870 | ;; Mode attributes used for fixed-point support. |
1871 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
1872 | (V2UHA "16") (UHA "16") | |
1873 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
1874 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
1875 | ||
cf16f980 KT |
1876 | (define_mode_attr qaddsub_clob_q [(V4UQQ "0") (V2UHQ "0") (UQQ "0") (UHQ "0") |
1877 | (V2UHA "0") (UHA "0") | |
1878 | (V4QQ "0") (V2HQ "0") (QQ "0") (HQ "0") | |
1879 | (V2HA "0") (HA "0") (SQ "ARM_Q_BIT_READ") | |
1880 | (SA "ARM_Q_BIT_READ")]) | |
1881 | ||
36ba4aae IR |
1882 | ;; Mode attribute for vshll. |
1883 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
1884 | ||
1dd4fe1f | 1885 | ;; Mode attributes used for VFP support. |
76f722f4 | 1886 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
1dd4fe1f KT |
1887 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
1888 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
c2b7062d | 1889 | (define_mode_attr VF_constraint [(V4HF "t") (V8HF "t") (V2SF "t") (V4SF "w")]) |
76f722f4 | 1890 | |
f7379e5e JG |
1891 | ;; Mode attribute used to build the "type" attribute. |
1892 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
55a9b91b MW |
1893 | (V4HI "") (V8HI "_q") |
1894 | (V2SI "") (V4SI "_q") | |
4b644867 | 1895 | (V4HF "") (V8HF "_q") |
55a9b91b MW |
1896 | (V2SF "") (V4SF "_q") |
1897 | (V4HF "") (V8HF "_q") | |
2e87b2f4 | 1898 | (V4BF "") (V8BF "_q") |
55a9b91b MW |
1899 | (DI "") (V2DI "_q") |
1900 | (DF "") (V2DF "_q") | |
1901 | (HF "")]) | |
f7379e5e | 1902 | |
94f0f2cc JG |
1903 | (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) |
1904 | ||
f8e109ba TC |
1905 | (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) |
1906 | (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) | |
1907 | ||
eb7ba6c3 DZ |
1908 | (define_mode_attr VSF2BF [(V2SF "V4BF") (V4SF "V8BF")]) |
1909 | ||
a5f3c89e MM |
1910 | (define_mode_attr cde_suffix [(SI "") (DI "d")]) |
1911 | (define_mode_attr cde_dest [(SI "%0") (DI "%0, %H0")]) | |
1912 | ||
a9a88a0a SP |
1913 | ;;MVE mode attribute. |
1914 | (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") | |
1915 | (V4SF "V4SI")]) | |
1916 | (define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")]) | |
1917 | ||
1918 | (define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")]) | |
1919 | (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) | |
1920 | (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf") | |
1921 | (V8HF "Rd") (V4SF "Rf")]) | |
1922 | (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")]) | |
1923 | ||
1924 | (define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15") | |
1925 | (V4SI "mve_imm_31")]) | |
1926 | (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) | |
1927 | (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") | |
1928 | (V4SI "mve_imm_32") | |
1929 | (V8HF "mve_imm_16") (V4SF "mve_imm_32")]) | |
1930 | (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")]) | |
1931 | ||
1932 | (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) | |
1933 | (define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")]) | |
1934 | ||
1935 | (define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h") | |
1936 | (V4SF "w")]) | |
1937 | (define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16") (V4SI "32") | |
1938 | (V8HF "u16") (V4SF "32")]) | |
1939 | (define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w") | |
1940 | (V8HF "=w") (V4SF "=&w")]) | |
91224cf6 | 1941 | (define_mode_attr MVE_VPRED [(V16QI "V16BI") (V8HI "V8BI") (V4SI "V4BI") |
e0bc13d3 | 1942 | (V8HF "V8BI") (V4SF "V4BI") (V2DI "V2QI")]) |
91224cf6 | 1943 | (define_mode_attr MVE_vpred [(V16QI "v16bi") (V8HI "v8bi") (V4SI "v4bi") |
e0bc13d3 AV |
1944 | (V8HF "v8bi") (V4SF "v4bi") |
1945 | (V16BI "v16bi") (V8BI "v8bi") (V4BI "v4bi") | |
1946 | (V2QI "v2qi")]) | |
1947 | (define_mode_attr MVE_vctp [(V16BI "8") (V8BI "16") (V4BI "32") (V2QI "64")]) | |
a9a88a0a | 1948 | |
ceddf62c SN |
1949 | ;;---------------------------------------------------------------------------- |
1950 | ;; Code attributes | |
1951 | ;;---------------------------------------------------------------------------- | |
1952 | ||
8b8ab8f4 RE |
1953 | ;; Determine the mode of a 'wide compare', ie where the carry flag is |
1954 | ;; propagated into the comparison. | |
1955 | (define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_B")]) | |
1956 | ||
ceddf62c SN |
1957 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. |
1958 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
1959 | (umin "vmin") (umax "vmax")]) | |
1960 | ||
f7379e5e JG |
1961 | ;; Type attributes for vqh_ops and vqhs_ops iterators. |
1962 | (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") | |
1963 | (umin "minmax") (umax "minmax")]) | |
1964 | ||
ceddf62c SN |
1965 | ;; Signs of above, where relevant. |
1966 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
1967 | (umax "u")]) | |
1968 | ||
40858b9d WD |
1969 | ;; Map rtl operator codes to optab names |
1970 | (define_code_attr optab | |
1e271bee | 1971 | [(and "and") |
40858b9d WD |
1972 | (ior "ior") |
1973 | (xor "xor")]) | |
46b57af1 TB |
1974 | |
1975 | ;; Assembler mnemonics for signedness of widening operations. | |
1976 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
22a8ab77 | 1977 | (define_code_attr Us [(sign_extend "") (zero_extend "u")]) |
3f2dc806 | 1978 | |
ababd936 KT |
1979 | ;; Signedness suffix for float->fixed conversions. Empty for signed |
1980 | ;; conversion. | |
1981 | (define_code_attr su_optab [(fix "") (unsigned_fix "u")]) | |
1982 | ||
1983 | ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. | |
1984 | (define_code_attr su [(fix "s") (unsigned_fix "u")]) | |
1985 | ||
3f2dc806 AS |
1986 | ;; Right shifts |
1987 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
1988 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
1989 | ||
d403b8d4 MW |
1990 | ;; String reprentations of operations on the sign of a number. |
1991 | (define_code_attr absneg_str [(abs "abs") (neg "neg")]) | |
1992 | ||
1993 | ;; Conversions. | |
1994 | (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) | |
1995 | ||
55a9b91b MW |
1996 | (define_code_attr float_sup [(unsigned_float "u") (float "s")]) |
1997 | ||
1998 | (define_code_attr float_SUP [(unsigned_float "U") (float "S")]) | |
1999 | ||
bcf66a4d CL |
2000 | ;; max/min for MVE |
2001 | (define_code_attr max_min_su_str [(smax "vmax") (umax "vmax") (smin "vmin") (umin "vmin")]) | |
2002 | ||
2003 | (define_code_attr max_min_supf [ | |
2004 | (smax "s") (umax "u") | |
2005 | (smin "s") (umin "u") | |
2006 | ]) | |
2007 | ||
5ea7a47c CL |
2008 | ;; Floating-point max/min for MVE |
2009 | (define_code_attr max_min_f_str [(smax "vmaxnm") (smin "vminnm")]) | |
2010 | ||
1dd4fe1f KT |
2011 | ;;---------------------------------------------------------------------------- |
2012 | ;; Int attributes | |
2013 | ;;---------------------------------------------------------------------------- | |
2014 | ||
94f0f2cc JG |
2015 | ;; Mapping between vector UNSPEC operations and the signed ('s'), |
2016 | ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. | |
2017 | (define_int_attr sup [ | |
53cd0ac6 | 2018 | (UNSPEC_SXTB16 "s") (UNSPEC_UXTB16 "u") |
94f0f2cc JG |
2019 | (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") |
2020 | (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") | |
2021 | (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") | |
2022 | (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") | |
2023 | (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") | |
2024 | (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") | |
2025 | (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") | |
2026 | (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") | |
2027 | (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") | |
2028 | (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") | |
2029 | (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") | |
2030 | (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") | |
2031 | (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") | |
2032 | (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") | |
2033 | (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") | |
84ae7213 | 2034 | (UNSPEC_VABAL_S "s") (UNSPEC_VABAL_U "u") |
94f0f2cc JG |
2035 | (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") |
2036 | (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") | |
2037 | (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") | |
2038 | (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") | |
2039 | (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") | |
2040 | (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") | |
2041 | (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") | |
2042 | (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") | |
2043 | (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") | |
d403b8d4 MW |
2044 | (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u") |
2045 | (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u") | |
2046 | (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u") | |
2047 | (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u") | |
94f0f2cc | 2048 | (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") |
d403b8d4 MW |
2049 | (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u") |
2050 | (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u") | |
94f0f2cc JG |
2051 | (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") |
2052 | (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") | |
2053 | (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") | |
2054 | (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") | |
2055 | (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") | |
2056 | (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") | |
2057 | (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") | |
2058 | (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") | |
2059 | (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") | |
2060 | (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") | |
2061 | (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") | |
2062 | (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") | |
2063 | (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") | |
2064 | (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") | |
d403b8d4 | 2065 | (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u") |
f8e109ba | 2066 | (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u") |
f348846e | 2067 | (UNSPEC_DOT_US "us") (UNSPEC_DOT_SU "su") |
0775830a | 2068 | (UNSPEC_SSAT16 "s") (UNSPEC_USAT16 "u") |
436016f4 | 2069 | (UNSPEC_MATMUL_S "s") (UNSPEC_MATMUL_U "u") (UNSPEC_MATMUL_US "us") |
94f0f2cc JG |
2070 | ]) |
2071 | ||
06e95715 KT |
2072 | (define_int_attr vfml_half |
2073 | [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")]) | |
2074 | ||
2075 | (define_int_attr vfml_half_selector | |
2076 | [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")]) | |
2077 | ||
d403b8d4 MW |
2078 | (define_int_attr vcvth_op |
2079 | [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a") | |
2080 | (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m") | |
2081 | (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n") | |
2082 | (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")]) | |
2083 | ||
2084 | (define_int_attr fp16_rnd_str | |
2085 | [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda") | |
2086 | (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn") | |
2087 | (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")]) | |
2088 | ||
2089 | (define_int_attr fp16_rnd_insn | |
2090 | [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta") | |
2091 | (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn") | |
2092 | (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")]) | |
2093 | ||
381811fa | 2094 | (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") |
55a9b91b MW |
2095 | (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") |
2096 | (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") | |
2097 | (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le") | |
2098 | (UNSPEC_VCALT "lt")]) | |
381811fa | 2099 | |
94f0f2cc JG |
2100 | (define_int_attr r [ |
2101 | (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") | |
2102 | (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") | |
2103 | (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") | |
2104 | (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") | |
2105 | (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") | |
2106 | (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") | |
2107 | ]) | |
2108 | ||
2109 | (define_int_attr maxmin [ | |
2110 | (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") | |
2111 | (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") | |
2112 | (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") | |
2113 | (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") | |
2114 | ]) | |
2115 | ||
0a18c19f DS |
2116 | (define_int_attr fmaxmin [ |
2117 | (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) | |
2118 | ||
2119 | (define_int_attr fmaxmin_op [ | |
2120 | (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") | |
2121 | ]) | |
2122 | ||
94f0f2cc JG |
2123 | (define_int_attr shift_op [ |
2124 | (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") | |
2125 | (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") | |
2126 | (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") | |
2127 | (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") | |
2128 | (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") | |
2129 | (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") | |
2130 | (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") | |
2131 | (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") | |
2132 | (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") | |
2133 | (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") | |
2134 | (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") | |
2135 | (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") | |
2136 | ]) | |
2137 | ||
1dd4fe1f KT |
2138 | ;; Standard names for floating point to integral rounding instructions. |
2139 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
2140 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
2141 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
2142 | ||
2143 | ;; Suffixes for vrint instructions specifying rounding modes. | |
2144 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
2145 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
2146 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
2147 | ||
2148 | ;; Some of the vrint instuctions are predicable. | |
2149 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
2150 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
2151 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
79739965 | 2152 | |
fca0efeb KT |
2153 | (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") |
2154 | (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") | |
2155 | (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) | |
2156 | ||
7313381d RS |
2157 | (define_int_attr nvrint_pattern [(UNSPEC_NVRINTZ "btrunc") |
2158 | (UNSPEC_NVRINTP "ceil") | |
2159 | (UNSPEC_NVRINTA "round") | |
2160 | (UNSPEC_NVRINTM "floor") | |
2161 | (UNSPEC_NVRINTX "rint") | |
2162 | (UNSPEC_NVRINTN "roundeven")]) | |
2163 | ||
79739965 KT |
2164 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") |
2165 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
2166 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) | |
582e2e43 KT |
2167 | |
2168 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") | |
2169 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") | |
2170 | (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) | |
2171 | ||
2172 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
2173 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") | |
2174 | (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) | |
2175 | ||
021b5e6b KT |
2176 | (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") |
2177 | (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") | |
2178 | (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") | |
2179 | (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") | |
2180 | (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") | |
2181 | (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") | |
2182 | (UNSPEC_SHA256H2 "sha256h2") | |
2183 | (UNSPEC_SHA256SU1 "sha256su1")]) | |
2184 | ||
2185 | (define_int_attr crypto_type | |
b10baa95 KT |
2186 | [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") |
2187 | (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") | |
021b5e6b KT |
2188 | (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") |
2189 | (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") | |
2190 | (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") | |
2191 | (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") | |
2192 | (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) | |
2193 | ||
2194 | (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") | |
2195 | (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") | |
2196 | (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") | |
2197 | (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") | |
2198 | (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") | |
2199 | (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") | |
2200 | (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) | |
2201 | ||
2202 | (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") | |
2203 | (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") | |
2204 | (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") | |
2205 | (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") | |
2206 | (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") | |
2207 | (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") | |
2208 | (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) | |
2209 | ||
c2b7062d TC |
2210 | (define_int_attr rot [(UNSPEC_VCADD90 "90") |
2211 | (UNSPEC_VCADD270 "270") | |
b22e70e8 | 2212 | (VCADDQ_ROT90_M_F "90") |
68ec7d75 | 2213 | (VCADDQ_ROT90_M "90") |
b22e70e8 | 2214 | (VCADDQ_ROT270_M_F "270") |
68ec7d75 | 2215 | (VCADDQ_ROT270_M "270") |
b22e70e8 CL |
2216 | (VHCADDQ_ROT90_S "90") |
2217 | (VHCADDQ_ROT270_S "270") | |
2218 | (VHCADDQ_ROT90_M_S "90") | |
2219 | (VHCADDQ_ROT270_M_S "270") | |
bcac2871 TC |
2220 | (UNSPEC_VCMUL "0") |
2221 | (UNSPEC_VCMUL90 "90") | |
2222 | (UNSPEC_VCMUL180 "180") | |
2223 | (UNSPEC_VCMUL270 "270") | |
c2b7062d TC |
2224 | (UNSPEC_VCMLA "0") |
2225 | (UNSPEC_VCMLA90 "90") | |
2226 | (UNSPEC_VCMLA180 "180") | |
0c5ba73a CL |
2227 | (UNSPEC_VCMLA270 "270") |
2228 | (VCMULQ_M_F "0") | |
2229 | (VCMULQ_ROT90_M_F "90") | |
2230 | (VCMULQ_ROT180_M_F "180") | |
6ae2fba5 CL |
2231 | (VCMULQ_ROT270_M_F "270") |
2232 | (VCMLAQ_M_F "0") | |
2233 | (VCMLAQ_ROT90_M_F "90") | |
2234 | (VCMLAQ_ROT180_M_F "180") | |
2235 | (VCMLAQ_ROT270_M_F "270") | |
2236 | ]) | |
c2b7062d | 2237 | |
389b67fe TC |
2238 | ;; The complex operations when performed on a real complex number require two |
2239 | ;; instructions to perform the operation. e.g. complex multiplication requires | |
2240 | ;; two VCMUL with a particular rotation value. | |
2241 | ;; | |
2242 | ;; These values can be looked up in rotsplit1 and rotsplit2. as an example | |
2243 | ;; VCMUL needs the first instruction to use #0 and the second #90. | |
2244 | (define_int_attr rotsplit1 [(UNSPEC_VCMLA "0") | |
2245 | (UNSPEC_VCMLA_CONJ "0") | |
2246 | (UNSPEC_VCMUL "0") | |
2247 | (UNSPEC_VCMUL_CONJ "0") | |
2248 | (UNSPEC_VCMLA180 "180") | |
2249 | (UNSPEC_VCMLA180_CONJ "180")]) | |
2250 | ||
2251 | (define_int_attr rotsplit2 [(UNSPEC_VCMLA "90") | |
2252 | (UNSPEC_VCMLA_CONJ "270") | |
2253 | (UNSPEC_VCMUL "90") | |
2254 | (UNSPEC_VCMUL_CONJ "270") | |
2255 | (UNSPEC_VCMLA180 "270") | |
2256 | (UNSPEC_VCMLA180_CONJ "90")]) | |
2257 | ||
2258 | (define_int_attr conj_op [(UNSPEC_VCMLA180 "") | |
2259 | (UNSPEC_VCMLA180_CONJ "_conj") | |
2260 | (UNSPEC_VCMLA "") | |
2261 | (UNSPEC_VCMLA_CONJ "_conj") | |
2262 | (UNSPEC_VCMUL "") | |
2263 | (UNSPEC_VCMUL_CONJ "_conj")]) | |
2264 | ||
9732dc85 | 2265 | (define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90") |
db253e8b | 2266 | (UNSPEC_VCADD270 "_rot270") |
b22e70e8 | 2267 | (VCADDQ_ROT90_M_F "_rot90") |
68ec7d75 | 2268 | (VCADDQ_ROT90_M "_rot90") |
b22e70e8 | 2269 | (VCADDQ_ROT270_M_F "_rot270") |
68ec7d75 | 2270 | (VCADDQ_ROT270_M "_rot270") |
b22e70e8 CL |
2271 | (VHCADDQ_ROT90_S "_rot90") |
2272 | (VHCADDQ_ROT270_S "_rot270") | |
2273 | (VHCADDQ_ROT90_M_S "_rot90") | |
2274 | (VHCADDQ_ROT270_M_S "_rot270") | |
db253e8b TC |
2275 | (UNSPEC_VCMLA "") |
2276 | (UNSPEC_VCMLA90 "_rot90") | |
2277 | (UNSPEC_VCMLA180 "_rot180") | |
2278 | (UNSPEC_VCMLA270 "_rot270") | |
2279 | (UNSPEC_VCMUL "") | |
2280 | (UNSPEC_VCMUL90 "_rot90") | |
2281 | (UNSPEC_VCMUL180 "_rot180") | |
0c5ba73a CL |
2282 | (UNSPEC_VCMUL270 "_rot270") |
2283 | (VCMULQ_M_F "") | |
2284 | (VCMULQ_ROT90_M_F "_rot90") | |
2285 | (VCMULQ_ROT180_M_F "_rot180") | |
6ae2fba5 CL |
2286 | (VCMULQ_ROT270_M_F "_rot270") |
2287 | (VCMLAQ_M_F "") | |
2288 | (VCMLAQ_ROT90_M_F "_rot90") | |
2289 | (VCMLAQ_ROT180_M_F "_rot180") | |
2290 | (VCMLAQ_ROT270_M_F "_rot270")]) | |
9732dc85 | 2291 | |
389b67fe TC |
2292 | (define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a") |
2293 | (UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")]) | |
2294 | ||
53cd0ac6 KT |
2295 | (define_int_attr simd32_op [(UNSPEC_QADD8 "qadd8") (UNSPEC_QSUB8 "qsub8") |
2296 | (UNSPEC_SHADD8 "shadd8") (UNSPEC_SHSUB8 "shsub8") | |
2297 | (UNSPEC_UHADD8 "uhadd8") (UNSPEC_UHSUB8 "uhsub8") | |
2298 | (UNSPEC_UQADD8 "uqadd8") (UNSPEC_UQSUB8 "uqsub8") | |
2299 | (UNSPEC_QADD16 "qadd16") (UNSPEC_QASX "qasx") | |
2300 | (UNSPEC_QSAX "qsax") (UNSPEC_QSUB16 "qsub16") | |
2301 | (UNSPEC_SHADD16 "shadd16") (UNSPEC_SHASX "shasx") | |
2302 | (UNSPEC_SHSAX "shsax") (UNSPEC_SHSUB16 "shsub16") | |
2303 | (UNSPEC_UHADD16 "uhadd16") (UNSPEC_UHASX "uhasx") | |
2304 | (UNSPEC_UHSAX "uhsax") (UNSPEC_UHSUB16 "uhsub16") | |
2305 | (UNSPEC_UQADD16 "uqadd16") (UNSPEC_UQASX "uqasx") | |
2306 | (UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16") | |
2307 | (UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx") | |
2308 | (UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16") | |
2b5b5e24 KT |
2309 | (UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald") |
2310 | (UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld") | |
16155ccf KT |
2311 | (UNSPEC_SMLSLDX "smlsldx")(UNSPEC_SADD8 "sadd8") |
2312 | (UNSPEC_UADD8 "uadd8") (UNSPEC_SSUB8 "ssub8") | |
2313 | (UNSPEC_USUB8 "usub8") (UNSPEC_SADD16 "sadd16") | |
2314 | (UNSPEC_SASX "sasx") (UNSPEC_SSAX "ssax") | |
2315 | (UNSPEC_SSUB16 "ssub16") (UNSPEC_UADD16 "uadd16") | |
2316 | (UNSPEC_UASX "uasx") (UNSPEC_USAX "usax") | |
65dd610d KT |
2317 | (UNSPEC_USUB16 "usub16") (UNSPEC_SMLAD "smlad") |
2318 | (UNSPEC_SMLADX "smladx") (UNSPEC_SMLSD "smlsd") | |
2319 | (UNSPEC_SMLSDX "smlsdx") (UNSPEC_SMUAD "smuad") | |
0775830a KT |
2320 | (UNSPEC_SMUADX "smuadx") (UNSPEC_SSAT16 "ssat16") |
2321 | (UNSPEC_USAT16 "usat16")]) | |
53cd0ac6 | 2322 | |
436016f4 DZ |
2323 | (define_int_attr mmla_sfx [(UNSPEC_MATMUL_S "s8") (UNSPEC_MATMUL_U "u8") |
2324 | (UNSPEC_MATMUL_US "s8")]) | |
a9a88a0a SP |
2325 | ;;MVE int attribute. |
2326 | (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") | |
2327 | (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") | |
2328 | (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") | |
fd436034 | 2329 | (VREV64Q_U "u") |
a9a88a0a SP |
2330 | (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") |
2331 | (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") | |
2332 | (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") | |
2333 | (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u") | |
2334 | (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s") | |
2335 | (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") | |
7969d9c8 | 2336 | (VREV32Q_U "u") |
a9a88a0a SP |
2337 | (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") |
2338 | (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u") | |
2339 | (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") | |
2340 | (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u") | |
2341 | (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s") | |
a6eacbf1 | 2342 | (VADDLVQ_P_U "u") |
a9a88a0a SP |
2343 | (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s") |
2344 | (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u") | |
9732dc85 | 2345 | (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VBRSRQ_N_S "s") |
a6eacbf1 | 2346 | (VBRSRQ_N_U "u") |
a9a88a0a SP |
2347 | (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") |
2348 | (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") | |
2349 | (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") | |
2350 | (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u") | |
2351 | (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s") | |
2352 | (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u") | |
2353 | (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s") | |
2354 | (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u") | |
195cc201 CL |
2355 | (VMULLBQ_POLY_P "p") |
2356 | (VMULLTQ_POLY_P "p") | |
2357 | (VMULLBQ_POLY_M_P "p") | |
2358 | (VMULLTQ_POLY_M_P "p") | |
a9a88a0a | 2359 | (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s") |
250fd9fb | 2360 | (VMULQ_U "u") |
75de6a28 | 2361 | (VQADDQ_N_S "s") (VQADDQ_N_U "u") |
a9a88a0a SP |
2362 | (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s") |
2363 | (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u") | |
2364 | (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s") | |
2365 | (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u") | |
2366 | (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s") | |
2367 | (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u") | |
2368 | (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s") | |
2369 | (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u") | |
2370 | (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s") | |
2371 | (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u") | |
2372 | (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") | |
2373 | (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u") | |
2374 | (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u") | |
8e92b66f | 2375 | (VMLALDAVQ_S "s") (VMLALDAVXQ_S "s") |
a9a88a0a SP |
2376 | (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u") |
2377 | (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u") | |
2378 | (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") | |
2379 | (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s") | |
2380 | (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u") | |
2381 | (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u") | |
2382 | (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s") | |
2383 | (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s") | |
2384 | (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u") | |
2385 | (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s") | |
2386 | (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u") | |
2387 | (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s") | |
2388 | (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u") | |
2389 | (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s") | |
2390 | (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u") | |
2391 | (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s") | |
2392 | (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u") | |
2393 | (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s") | |
2394 | (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u") | |
2395 | (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s") | |
237f12da | 2396 | (VPSELQ_U "u") (VQDMLAHQ_N_S "s") |
afb198ee | 2397 | (VQDMLASHQ_N_S "s") |
237f12da CL |
2398 | (VQRDMLAHQ_N_S "s") |
2399 | (VQRDMLASHQ_N_S "s") | |
a9a88a0a SP |
2400 | (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u") |
2401 | (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s") | |
2402 | (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u") | |
2403 | (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s") | |
2404 | (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u") | |
2405 | (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s") | |
2406 | (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s") | |
2407 | (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s") | |
2408 | (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s") | |
2409 | (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s") | |
2410 | (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s") | |
2411 | (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u") | |
2412 | (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u") | |
2413 | (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u") | |
2414 | (VREV16Q_M_S "s") (VREV16Q_M_U "u") | |
2415 | (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u") | |
2416 | (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u") | |
8e92b66f AV |
2417 | (VRSHRNBQ_N_U "u") |
2418 | (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") | |
a9a88a0a SP |
2419 | (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s") |
2420 | (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u") | |
2421 | (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s") | |
2422 | (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s") | |
2423 | (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u") | |
2424 | (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u") | |
2425 | (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u") | |
2426 | (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u") | |
2427 | (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s") | |
2428 | (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s") | |
2429 | (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u") | |
2430 | (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u") | |
2431 | (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s") | |
68ec7d75 | 2432 | (VEORQ_M_U "u") (VSHRQ_M_N_U "u") |
a9a88a0a SP |
2433 | (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s") |
2434 | (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s") | |
2435 | (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u") | |
2436 | (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u") | |
2437 | (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u") | |
2438 | (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u") | |
afb198ee | 2439 | (VQDMLASHQ_M_N_S "s") |
a9a88a0a | 2440 | (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s") |
68ec7d75 | 2441 | (VORNQ_M_S "s") (VCADDQ_ROT270_M "") (VRHADDQ_M_U "u") |
a9a88a0a SP |
2442 | (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u") |
2443 | (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s") | |
2444 | (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s") | |
2445 | (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u") | |
2446 | (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u") | |
2447 | (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u") | |
68ec7d75 | 2448 | (VQADDQ_M_U "u") |
a9a88a0a SP |
2449 | (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u") |
2450 | (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s") | |
68ec7d75 | 2451 | (VCADDQ_ROT90_M "") (VRMULHQ_M_S "s") (VANDQ_M_U "u") |
a9a88a0a SP |
2452 | (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u") |
2453 | (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u") | |
2454 | (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s") | |
2455 | (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s") | |
2456 | (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u") | |
2457 | (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s") | |
2458 | (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u") | |
2459 | (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u") | |
2460 | (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s") | |
2461 | (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u") | |
2462 | (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s") | |
2463 | (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u") | |
2464 | (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u") | |
2465 | (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u") | |
2466 | (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u") | |
2467 | (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s") | |
2468 | (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s") | |
2469 | (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u") | |
2470 | (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") | |
2471 | (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") | |
237f12da | 2472 | (VMLALDAVAXQ_P_S "s") |
a9a88a0a SP |
2473 | (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") |
2474 | (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") | |
2475 | (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u") | |
2476 | (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s") | |
2477 | (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u") | |
2478 | (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s") | |
2479 | (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u") | |
2480 | (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s") | |
2481 | (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u") | |
2482 | (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s") | |
2483 | (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u") | |
2484 | (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s") | |
2485 | (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u") | |
2486 | (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s") | |
2487 | (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u") | |
2488 | (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s") | |
2489 | (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u") | |
2490 | (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u") | |
2491 | (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u") | |
2492 | (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s") | |
2493 | (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s") | |
2494 | (VSTRDQSBWB_U "u") (VSBCQ_U "u") (VSBCQ_M_U "u") | |
2495 | (VSBCQ_S "s") (VSBCQ_M_S "s") (VSBCIQ_U "u") | |
2496 | (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s") | |
2497 | (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s") | |
2498 | (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s") | |
2499 | (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48") | |
2500 | (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s") | |
5cbe0c09 CL |
2501 | (VSHLCQ_M_U "u") |
2502 | (VQDMLADHQ_M_S "s") | |
2503 | (VQDMLADHXQ_M_S "s") | |
2504 | (VQDMLSDHQ_M_S "s") | |
2505 | (VQDMLSDHXQ_M_S "s") | |
2506 | (VQDMULHQ_M_S "s") | |
2507 | (VQRDMLADHQ_M_S "s") | |
2508 | (VQRDMLADHXQ_M_S "s") | |
2509 | (VQRDMLSDHQ_M_S "s") | |
2510 | (VQRDMLSDHXQ_M_S "s") | |
2511 | (VQRDMULHQ_M_S "s") | |
111f474f CL |
2512 | (VQDMULHQ_N_S "s") |
2513 | (VQRDMULHQ_N_S "s") | |
a7cbd5f9 CL |
2514 | (VQDMLAHQ_M_N_S "s") |
2515 | (VQDMLASHQ_M_N_S "s") | |
2516 | (VQRDMLAHQ_M_N_S "s") | |
2517 | (VQRDMLASHQ_M_N_S "s") | |
2518 | (VQDMULHQ_M_N_S "s") | |
2519 | (VQRDMULHQ_M_N_S "s") | |
3fe5a244 CL |
2520 | (VQDMULHQ_S "s") |
2521 | (VQRDMULHQ_S "s") | |
8f5b7d21 CL |
2522 | (VQRSHRUNBQ_M_N_S "s") |
2523 | (VQRSHRUNBQ_N_S "s") | |
2524 | (VQRSHRUNTQ_M_N_S "s") | |
2525 | (VQRSHRUNTQ_N_S "s") | |
2526 | (VQSHRUNBQ_M_N_S "s") | |
2527 | (VQSHRUNBQ_N_S "s") | |
2528 | (VQSHRUNTQ_M_N_S "s") | |
2529 | (VQSHRUNTQ_N_S "s") | |
7734b991 CL |
2530 | (VABSQ_M_S "s") |
2531 | (VCLSQ_M_S "s") | |
2532 | (VCLZQ_M_S "s") (VCLZQ_M_U "u") | |
2533 | (VNEGQ_M_S "s") | |
2534 | (VQABSQ_M_S "s") | |
2535 | (VQNEGQ_M_S "s") | |
2536 | (VCLSQ_S "s") | |
2537 | (VQABSQ_S "s") | |
2538 | (VQNEGQ_S "s") | |
7f49b4a0 CL |
2539 | (VQMOVUNBQ_M_S "s") |
2540 | (VQMOVUNBQ_S "s") | |
2541 | (VQMOVUNTQ_M_S "s") | |
2542 | (VQMOVUNTQ_S "s") | |
16c5aca6 CL |
2543 | (VMAXAVQ_S "s") |
2544 | (VMAXAVQ_P_S "s") | |
2545 | (VMINAVQ_S "s") | |
2546 | (VMINAVQ_P_S "s") | |
dcc05862 CL |
2547 | (VMAXAQ_S "s") |
2548 | (VMAXAQ_M_S "s") | |
2549 | (VMINAQ_S "s") | |
2550 | (VMINAQ_M_S "s") | |
6a08718a CL |
2551 | (VCMPCSQ_M_N_U "u") |
2552 | (VCMPCSQ_M_U "u") | |
2553 | (VCMPEQQ_M_N_S "s") (VCMPEQQ_M_N_U "u") | |
2554 | (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u") | |
2555 | (VCMPGEQ_M_N_S "s") | |
2556 | (VCMPGEQ_M_S "s") | |
2557 | (VCMPGTQ_M_N_S "s") | |
2558 | (VCMPGTQ_M_S "s") | |
2559 | (VCMPHIQ_M_N_U "u") | |
2560 | (VCMPHIQ_M_U "u") | |
2561 | (VCMPLEQ_M_N_S "s") | |
2562 | (VCMPLEQ_M_S "s") | |
2563 | (VCMPLTQ_M_N_S "s") | |
2564 | (VCMPLTQ_M_S "s") | |
2565 | (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") | |
2566 | (VCMPNEQ_M_S "s") (VCMPNEQ_M_U "u") | |
1817749d CL |
2567 | (VMLADAVAXQ_P_S "s") |
2568 | (VMLADAVAXQ_S "s") | |
2569 | (VMLADAVXQ_P_S "s") | |
2570 | (VMLADAVXQ_S "s") | |
2571 | (VMLSDAVAQ_P_S "s") | |
2572 | (VMLSDAVAQ_S "s") | |
2573 | (VMLSDAVAXQ_P_S "s") | |
2574 | (VMLSDAVAXQ_S "s") | |
2575 | (VMLSDAVQ_P_S "s") | |
2576 | (VMLSDAVQ_S "s") | |
2577 | (VMLSDAVXQ_P_S "s") | |
2578 | (VMLSDAVXQ_S "s") | |
c1e068e4 CL |
2579 | (VMLALDAVXQ_S "s") |
2580 | (VMLSLDAVQ_S "s") | |
2581 | (VMLSLDAVXQ_S "s") | |
2582 | (VMLALDAVXQ_P_S "s") | |
2583 | (VMLSLDAVQ_P_S "s") | |
2584 | (VMLSLDAVXQ_P_S "s") | |
e044696f CL |
2585 | (VRMLALDAVHXQ_P_S "s") |
2586 | (VRMLALDAVHXQ_S "s") | |
2587 | (VRMLSLDAVHQ_P_S "s") | |
2588 | (VRMLSLDAVHQ_S "s") | |
2589 | (VRMLSLDAVHXQ_P_S "s") | |
2590 | (VRMLSLDAVHXQ_S "s") | |
c68ccdf2 CL |
2591 | (VMLALDAVAXQ_P_S "s") |
2592 | (VMLALDAVAXQ_S "s") | |
2593 | (VMLSLDAVAQ_P_S "s") | |
2594 | (VMLSLDAVAQ_S "s") | |
2595 | (VMLSLDAVAXQ_P_S "s") | |
2596 | (VMLSLDAVAXQ_S "s") | |
3bf67ec9 CL |
2597 | (VQDMLADHQ_S "s") |
2598 | (VQDMLADHXQ_S "s") | |
2599 | (VQDMLSDHQ_S "s") | |
2600 | (VQDMLSDHXQ_S "s") | |
2601 | (VQRDMLADHQ_S "s") | |
2602 | (VQRDMLADHXQ_S "s") | |
2603 | (VQRDMLSDHQ_S "s") | |
2604 | (VQRDMLSDHXQ_S "s") | |
f2fd708a CL |
2605 | (VQDMLAHQ_N_S "s") |
2606 | (VQDMLASHQ_N_S "s") | |
2607 | (VQRDMLAHQ_N_S "s") | |
2608 | (VQRDMLASHQ_N_S "s") | |
c71b5c78 CL |
2609 | (VQDMULLBQ_S "s") |
2610 | (VQDMULLBQ_M_S "s") | |
2611 | (VQDMULLBQ_M_N_S "s") | |
2612 | (VQDMULLBQ_N_S "s") | |
2613 | (VQDMULLTQ_S "s") | |
2614 | (VQDMULLTQ_M_S "s") | |
2615 | (VQDMULLTQ_M_N_S "s") | |
2616 | (VQDMULLTQ_N_S "s") | |
e18f715b CL |
2617 | (VRMLALDAVHAXQ_P_S "s") |
2618 | (VRMLALDAVHAXQ_S "s") | |
2619 | (VRMLSLDAVHAQ_P_S "s") | |
2620 | (VRMLSLDAVHAQ_S "s") | |
2621 | (VRMLSLDAVHAXQ_P_S "s") | |
2622 | (VRMLSLDAVHAXQ_S "s") | |
2623 | (VRMLALDAVHAQ_P_S "s") (VRMLALDAVHAQ_P_U "u") | |
85c463f5 CL |
2624 | (VQSHLUQ_M_N_S "s") |
2625 | (VQSHLUQ_N_S "s") | |
b22e70e8 CL |
2626 | (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S "s") |
2627 | (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s") | |
2628 | (UNSPEC_VCADD90 "") (UNSPEC_VCADD270 "") | |
5cbe0c09 CL |
2629 | ]) |
2630 | ||
24d5b097 | 2631 | ;; Both kinds of return insn. |
728dc153 | 2632 | (define_code_iterator RETURNS [return simple_return]) |
24d5b097 XG |
2633 | (define_code_attr return_str [(return "") (simple_return "simple_")]) |
2634 | (define_code_attr return_simple_p [(return "false") (simple_return "true")]) | |
2635 | (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") | |
2636 | (simple_return " && use_simple_return_p ()")]) | |
2637 | (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") | |
2638 | (simple_return " && use_simple_return_p ()")]) | |
5f2ca3b2 MW |
2639 | |
2640 | ;; Attributes for VQRDMLAH/VQRDMLSH | |
2641 | (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) | |
55a9b91b MW |
2642 | |
2643 | ;; Attributes for VFMA_LANE/ VFMS_LANE | |
2644 | (define_int_attr neon_vfm_lane_as | |
2645 | [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")]) | |
d57daa0c AV |
2646 | |
2647 | ;; An iterator for the CDP coprocessor instructions | |
2648 | (define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2]) | |
2649 | (define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")]) | |
2650 | (define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")]) | |
3811581f AV |
2651 | |
2652 | ;; An iterator for the LDC coprocessor instruction | |
2653 | (define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2 | |
2654 | VUNSPEC_LDCL VUNSPEC_LDC2L]) | |
2655 | (define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2") | |
2656 | (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")]) | |
2657 | (define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2") | |
2658 | (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")]) | |
2659 | ||
2660 | ;; An iterator for the STC coprocessor instructions | |
2661 | (define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2 | |
2662 | VUNSPEC_STCL VUNSPEC_STC2L]) | |
2663 | (define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2") | |
2664 | (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")]) | |
2665 | (define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2") | |
2666 | (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")]) | |
ecc9a25b AV |
2667 | |
2668 | ;; An iterator for the MCR coprocessor instructions | |
2669 | (define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2]) | |
2670 | ||
2671 | (define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")]) | |
2672 | (define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")]) | |
2673 | ||
2674 | ;; An iterator for the MRC coprocessor instructions | |
2675 | (define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2]) | |
2676 | ||
2677 | (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) | |
2678 | (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) | |
f3caa118 AV |
2679 | |
2680 | ;; An iterator for the MCRR coprocessor instructions | |
2681 | (define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) | |
2682 | ||
2683 | (define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) | |
2684 | (define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) | |
2685 | ||
2686 | ;; An iterator for the MRRC coprocessor instructions | |
2687 | (define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) | |
2688 | ||
2689 | (define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) | |
2690 | (define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) | |
f8e109ba | 2691 | |
3dfc28db AV |
2692 | (define_int_attr dlstp_elemsize [(DLSTP8 "8") (DLSTP16 "16") (DLSTP32 "32") |
2693 | (DLSTP64 "64")]) | |
2694 | ||
2695 | (define_int_attr letp_num_lanes [(LETP8 "16") (LETP16 "8") (LETP32 "4") | |
2696 | (LETP64 "2")]) | |
2697 | (define_int_attr letp_num_lanes_neg [(LETP8 "-16") (LETP16 "-8") (LETP32 "-4") | |
2698 | (LETP64 "-2")]) | |
2699 | ||
2700 | (define_int_attr letp_num_lanes_minus_1 [(LETP8 "15") (LETP16 "7") (LETP32 "3") | |
2701 | (LETP64 "1")]) | |
2702 | ||
f8e109ba | 2703 | (define_int_attr opsuffix [(UNSPEC_DOT_S "s8") |
f348846e SMW |
2704 | (UNSPEC_DOT_U "u8") |
2705 | (UNSPEC_DOT_US "s8") | |
2706 | (UNSPEC_DOT_SU "u8") | |
2707 | ]) | |
08836731 KT |
2708 | |
2709 | (define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")]) | |
2d22ab64 KT |
2710 | |
2711 | ;; An iterator for VFMA<bt> | |
2712 | (define_int_attr bt [(UNSPEC_BFMAB "b") (UNSPEC_BFMAT "t")]) | |
ef684c78 MM |
2713 | |
2714 | ;; An iterator for CDE MVE accumulator/non-accumulator versions. | |
2715 | (define_int_attr a [(UNSPEC_VCDE "") (UNSPEC_VCDEA "a")]) | |
a9a88a0a SP |
2716 | |
2717 | ;; MVE int iterator. | |
2718 | (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) | |
2719 | (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) | |
2720 | (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) | |
2721 | (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) | |
2722 | (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) | |
2723 | (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) | |
a9a88a0a | 2724 | (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) |
a9a88a0a SP |
2725 | (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) |
2726 | (define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S]) | |
51fca3e1 | 2727 | (define_int_iterator VMOVLxQ [VMOVLBQ_S VMOVLBQ_U VMOVLTQ_U VMOVLTQ_S]) |
a9a88a0a SP |
2728 | (define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U]) |
2729 | (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) | |
2730 | (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) | |
2731 | (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) | |
a9a88a0a SP |
2732 | (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) |
2733 | (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) | |
2734 | (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) | |
2735 | (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) | |
2736 | (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U]) | |
a9a88a0a SP |
2737 | (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U]) |
2738 | (define_int_iterator VABDQ [VABDQ_S VABDQ_U]) | |
2739 | (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U]) | |
2740 | (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U]) | |
2741 | (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S]) | |
a9a88a0a | 2742 | (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S]) |
a9a88a0a SP |
2743 | (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) |
2744 | (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) | |
2745 | (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) | |
2746 | (define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S]) | |
2747 | (define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S]) | |
2748 | (define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S]) | |
2749 | (define_int_iterator VMINQ [VMINQ_S VMINQ_U]) | |
2750 | (define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S]) | |
2751 | (define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S]) | |
2752 | (define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U]) | |
195cc201 CL |
2753 | (define_int_iterator VMULLxQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S VMULLTQ_INT_U VMULLTQ_INT_S]) |
2754 | (define_int_iterator VMULLxQ_POLY [VMULLBQ_POLY_P VMULLTQ_POLY_P]) | |
a9a88a0a SP |
2755 | (define_int_iterator VMULQ [VMULQ_U VMULQ_S]) |
2756 | (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S]) | |
a9a88a0a SP |
2757 | (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S]) |
2758 | (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U]) | |
2759 | (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U]) | |
2760 | (define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U]) | |
2761 | (define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U]) | |
2762 | (define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U]) | |
2763 | (define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S]) | |
2764 | (define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S]) | |
2765 | (define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U]) | |
2766 | (define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U]) | |
2767 | (define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U]) | |
2768 | (define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U]) | |
2769 | (define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S]) | |
2770 | (define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U]) | |
2771 | (define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S]) | |
2772 | (define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U]) | |
2773 | (define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U]) | |
2774 | (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U]) | |
2775 | (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U]) | |
2776 | (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U]) | |
2777 | (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S]) | |
a9a88a0a SP |
2778 | (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S]) |
2779 | (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) | |
2780 | (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) | |
2781 | (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S]) | |
2782 | (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S]) | |
2cc50fd9 | 2783 | (define_int_iterator VSHLLxQ_N [VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_S VSHLLTQ_N_U]) |
a9a88a0a SP |
2784 | (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) |
2785 | (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U]) | |
2786 | (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U]) | |
2787 | (define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U]) | |
2788 | (define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S]) | |
2789 | (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U]) | |
2790 | (define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U]) | |
2791 | (define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U]) | |
2792 | (define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U]) | |
2793 | (define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U]) | |
2794 | (define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U]) | |
2795 | (define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U]) | |
2796 | (define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U]) | |
2797 | (define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U]) | |
2798 | (define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U]) | |
2799 | (define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U]) | |
2800 | (define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U]) | |
2801 | (define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U]) | |
2802 | (define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U]) | |
2803 | (define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U]) | |
2804 | (define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U]) | |
2805 | (define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U]) | |
2806 | (define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U]) | |
237f12da | 2807 | (define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S]) |
afb198ee | 2808 | (define_int_iterator VQDMLASHQ_N [VQDMLASHQ_N_S]) |
237f12da CL |
2809 | (define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S]) |
2810 | (define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S]) | |
a9a88a0a SP |
2811 | (define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U]) |
2812 | (define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U]) | |
2813 | (define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U]) | |
2814 | (define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U]) | |
2815 | (define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U]) | |
2816 | (define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U]) | |
2817 | (define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U]) | |
2818 | (define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S]) | |
2819 | (define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U]) | |
51fca3e1 | 2820 | (define_int_iterator VMOVLxQ_M [VMOVLBQ_M_U VMOVLBQ_M_S VMOVLTQ_M_U VMOVLTQ_M_S]) |
a9a88a0a SP |
2821 | (define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S]) |
2822 | (define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S]) | |
2823 | (define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U]) | |
2824 | (define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U]) | |
2825 | (define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U]) | |
2826 | (define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S]) | |
2827 | (define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S]) | |
a9a88a0a SP |
2828 | (define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U]) |
2829 | (define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S]) | |
2830 | (define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S]) | |
2831 | (define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U]) | |
a9a88a0a SP |
2832 | (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S]) |
2833 | (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S]) | |
2834 | (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S]) | |
a9a88a0a SP |
2835 | (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U]) |
2836 | (define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U]) | |
2837 | (define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U]) | |
2838 | (define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U]) | |
2839 | (define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U]) | |
2840 | (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S]) | |
2841 | (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U]) | |
2842 | (define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S]) | |
2843 | (define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U]) | |
2844 | (define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U]) | |
2845 | (define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U]) | |
2846 | (define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S]) | |
2847 | (define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S]) | |
2848 | (define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U]) | |
2849 | (define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S]) | |
2850 | (define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U]) | |
2851 | (define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U]) | |
195cc201 CL |
2852 | (define_int_iterator VMULLxQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S VMULLTQ_INT_M_U VMULLTQ_INT_M_S]) |
2853 | (define_int_iterator VMULLxQ_POLY_M [VMULLBQ_POLY_M_P VMULLTQ_POLY_M_P]) | |
a9a88a0a SP |
2854 | (define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U]) |
2855 | (define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U]) | |
2856 | (define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U]) | |
2857 | (define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U]) | |
2858 | (define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U]) | |
2859 | (define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S]) | |
2860 | (define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S]) | |
2861 | (define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U]) | |
2862 | (define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S]) | |
2863 | (define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S]) | |
2864 | (define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S]) | |
2865 | (define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S]) | |
2866 | (define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S]) | |
2867 | (define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S]) | |
2868 | (define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S]) | |
2869 | (define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U]) | |
b22e70e8 CL |
2870 | (define_int_iterator VCADDQ_M_F [VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F]) |
2871 | (define_int_iterator VxCADDQ [UNSPEC_VCADD90 UNSPEC_VCADD270 VHCADDQ_ROT90_S VHCADDQ_ROT270_S]) | |
68ec7d75 | 2872 | (define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S VCADDQ_ROT90_M VCADDQ_ROT270_M]) |
a9a88a0a SP |
2873 | (define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S]) |
2874 | (define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S]) | |
2875 | (define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U]) | |
2876 | (define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U]) | |
2877 | (define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S]) | |
2878 | (define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S]) | |
2879 | (define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S]) | |
2880 | (define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S]) | |
2881 | (define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S]) | |
a9a88a0a SP |
2882 | (define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U]) |
2883 | (define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U]) | |
2884 | (define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U]) | |
2885 | (define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U]) | |
2886 | (define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U]) | |
2887 | (define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U]) | |
2888 | (define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U]) | |
2889 | (define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S]) | |
237f12da | 2890 | (define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_S]) |
a9a88a0a SP |
2891 | (define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S]) |
2892 | (define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U]) | |
2893 | (define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S]) | |
2894 | (define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U]) | |
2895 | (define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S]) | |
2896 | (define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S]) | |
2cc50fd9 | 2897 | (define_int_iterator VSHLLxQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) |
a9a88a0a SP |
2898 | (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) |
2899 | (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) | |
2900 | (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) | |
2901 | (define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) | |
2902 | (define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) | |
2903 | (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U]) | |
2904 | (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) | |
2905 | (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U]) | |
2906 | (define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U]) | |
2907 | (define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U]) | |
2908 | (define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U]) | |
2909 | (define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U]) | |
2910 | (define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U]) | |
2911 | (define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U]) | |
2912 | (define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U]) | |
2913 | (define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U]) | |
2914 | (define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U]) | |
2915 | (define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U]) | |
2916 | (define_int_iterator VST1Q [VST1Q_S VST1Q_U]) | |
2917 | (define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U]) | |
2918 | (define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U]) | |
2919 | (define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U]) | |
2920 | (define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U]) | |
2921 | (define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U]) | |
2922 | (define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U]) | |
2923 | (define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U]) | |
2924 | (define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U]) | |
2925 | (define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U]) | |
2926 | (define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U]) | |
2927 | (define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U]) | |
2928 | (define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U]) | |
2929 | (define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U]) | |
2930 | (define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S]) | |
2931 | (define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S]) | |
2932 | (define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S]) | |
2933 | (define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S]) | |
2934 | (define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S]) | |
2935 | (define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S]) | |
2936 | (define_int_iterator VADCQ [VADCQ_U VADCQ_S]) | |
2937 | (define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S]) | |
2938 | (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48]) | |
2939 | (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48]) | |
2940 | (define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U]) | |
85c463f5 CL |
2941 | (define_int_iterator VQSHLUQ_M_N [VQSHLUQ_M_N_S]) |
2942 | (define_int_iterator VQSHLUQ_N [VQSHLUQ_N_S]) | |
3dfc28db AV |
2943 | (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32 |
2944 | DLSTP64]) | |
2945 | (define_int_iterator LETP [LETP8 LETP16 LETP32 | |
2946 | LETP64]) | |
389b67fe TC |
2947 | |
2948 | ;; Define iterators for VCMLA operations | |
2949 | (define_int_iterator VCMLA_OP [UNSPEC_VCMLA | |
2950 | UNSPEC_VCMLA_CONJ | |
2951 | UNSPEC_VCMLA180 | |
2952 | UNSPEC_VCMLA180_CONJ]) | |
2953 | ||
2954 | ;; Define iterators for VCMLA operations as MUL | |
2955 | (define_int_iterator VCMUL_OP [UNSPEC_VCMUL | |
2956 | UNSPEC_VCMUL_CONJ]) |