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92607e41 | 1 | ;; Marvell ARM Processor Pipeline Description |
8e87740b | 2 | ;; Copyright (C) 2010-2013 Free Software Foundation, Inc. |
92607e41 YHH |
3 | ;; Contributed by Marvell. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; Pipeline description for the Marvell PJ4, aka "Flareon". | |
22 | (define_automaton "pj4") | |
23 | ||
24 | ;; Issue resources | |
25 | (define_cpu_unit "pj4_is1,pj4_is2" "pj4") | |
26 | (define_reservation "pj4_is" "(pj4_is1|pj4_is2)") | |
27 | (define_reservation "pj4_isb" "(pj4_is1+pj4_is2)") | |
28 | ||
29 | ;; Functional units | |
30 | (define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4") | |
31 | ||
32 | ;; Completion ports | |
33 | (define_cpu_unit "pj4_w1,pj4_w2" "pj4") | |
34 | ||
35 | ;; Complete/Retire control | |
36 | (define_cpu_unit "pj4_c1,pj4_c2" "pj4") | |
37 | (define_reservation "pj4_cp" "(pj4_c1|pj4_c2)") | |
38 | (define_reservation "pj4_cpb" "(pj4_c1+pj4_c2)") | |
39 | ||
40 | ;; Integer arithmetic instructions | |
41 | ||
42 | (define_insn_reservation "pj4_alu_e1" 1 | |
43 | (and (eq_attr "tune" "marvell_pj4") | |
859abddd SN |
44 | (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") |
45 | (not (eq_attr "conds" "set"))) | |
92607e41 YHH |
46 | "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") |
47 | ||
48 | (define_insn_reservation "pj4_alu_e1_conds" 4 | |
49 | (and (eq_attr "tune" "marvell_pj4") | |
859abddd SN |
50 | (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") |
51 | (eq_attr "conds" "set")) | |
92607e41 YHH |
52 | "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") |
53 | ||
54 | (define_insn_reservation "pj4_alu" 1 | |
55 | (and (eq_attr "tune" "marvell_pj4") | |
006bd006 | 56 | (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") |
859abddd | 57 | (not (eq_attr "conds" "set"))) |
92607e41 YHH |
58 | "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") |
59 | ||
60 | (define_insn_reservation "pj4_alu_conds" 4 | |
61 | (and (eq_attr "tune" "marvell_pj4") | |
006bd006 | 62 | (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") |
859abddd | 63 | (eq_attr "conds" "set")) |
92607e41 YHH |
64 | "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") |
65 | ||
66 | (define_insn_reservation "pj4_shift" 1 | |
67 | (and (eq_attr "tune" "marvell_pj4") | |
859abddd SN |
68 | (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ |
69 | mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") | |
92607e41 YHH |
70 | (not (eq_attr "conds" "set")) |
71 | (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") | |
72 | ||
73 | (define_insn_reservation "pj4_shift_conds" 4 | |
74 | (and (eq_attr "tune" "marvell_pj4") | |
859abddd SN |
75 | (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ |
76 | mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") | |
92607e41 YHH |
77 | (eq_attr "conds" "set") |
78 | (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") | |
79 | ||
80 | (define_insn_reservation "pj4_alu_shift" 1 | |
81 | (and (eq_attr "tune" "marvell_pj4") | |
82 | (not (eq_attr "conds" "set")) | |
859abddd SN |
83 | (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ |
84 | mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) | |
92607e41 YHH |
85 | "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") |
86 | ||
87 | (define_insn_reservation "pj4_alu_shift_conds" 4 | |
88 | (and (eq_attr "tune" "marvell_pj4") | |
89 | (eq_attr "conds" "set") | |
859abddd SN |
90 | (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ |
91 | mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) | |
92607e41 YHH |
92 | "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") |
93 | ||
94 | (define_bypass 2 "pj4_alu_shift,pj4_shift" | |
95 | "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") | |
96 | ||
97 | (define_insn_reservation "pj4_ir_mul" 3 | |
09485a08 SN |
98 | (and (eq_attr "tune" "marvell_pj4") |
99 | (ior (eq_attr "mul32" "yes") | |
100 | (eq_attr "mul64" "yes"))) | |
101 | "pj4_is,pj4_mul,nothing*2,pj4_cp") | |
92607e41 YHH |
102 | |
103 | (define_insn_reservation "pj4_ir_div" 20 | |
09485a08 SN |
104 | (and (eq_attr "tune" "marvell_pj4") |
105 | (eq_attr "type" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp") | |
92607e41 YHH |
106 | |
107 | ;; Branches and calls. | |
108 | ||
109 | (define_insn_reservation "pj4_branches" 0 | |
110 | (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is") | |
111 | ||
112 | (define_insn_reservation "pj4_calls" 32 | |
113 | (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is") | |
114 | ||
115 | ;; Load/store instructions | |
116 | ||
117 | (define_insn_reservation "pj4_ldr" 3 | |
118 | (and (eq_attr "tune" "marvell_pj4") | |
119 | (eq_attr "type" "load_byte,load1")) | |
120 | "pj4_is,pj4_alu1,nothing*2,pj4_cp") | |
121 | ||
122 | (define_insn_reservation "pj4_ldrd" 3 | |
123 | (and (eq_attr "tune" "marvell_pj4") | |
124 | (eq_attr "type" "load2")) | |
125 | "pj4_is,pj4_alu1,nothing*2,pj4_cpb") | |
126 | ||
127 | (define_insn_reservation "pj4_str" 1 | |
128 | (and (eq_attr "tune" "marvell_pj4") | |
129 | (eq_attr "type" "store1")) | |
130 | "pj4_is,pj4_alu1,nothing*2,pj4_cp") | |
131 | ||
132 | (define_insn_reservation "pj4_strd" 1 | |
133 | (and (eq_attr "tune" "marvell_pj4") | |
134 | (eq_attr "type" "store2")) | |
135 | "pj4_is,pj4_alu1,nothing*2,pj4_cpb") | |
136 | ||
137 | (define_insn_reservation "pj4_ldm" 4 | |
138 | (and (eq_attr "tune" "marvell_pj4") | |
139 | (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp") | |
140 | ||
141 | (define_insn_reservation "pj4_stm" 2 | |
142 | (and (eq_attr "tune" "marvell_pj4") | |
143 | (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp") | |
144 | ||
145 | ;; Loads forward at WR-stage to ALU pipes | |
146 | (define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu") | |
147 | (define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shift_dep") | |
148 | ||
149 | (define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") | |
150 | (define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") | |
151 | ||
152 | ;; Loads to stores can back-to-back forward | |
153 | (define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store_addr_dep") | |
154 | ||
155 | ;; PJ4 VFP floating point unit | |
156 | (define_automaton "pj4_vfp") | |
157 | ||
158 | (define_cpu_unit "vissue" "pj4_vfp") | |
159 | (define_cpu_unit "vadd" "pj4_vfp") | |
160 | (define_cpu_unit "vmul" "pj4_vfp") | |
161 | (define_cpu_unit "vdiv" "pj4_vfp") | |
162 | (define_cpu_unit "vfast" "pj4_vfp") | |
163 | ||
164 | (define_insn_reservation "pj4_vfp_add" 5 | |
165 | (and (eq_attr "tune" "marvell_pj4") | |
166 | (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothing*3") | |
167 | ||
168 | (define_insn_reservation "pj4_vfp_mul" 6 | |
169 | (and (eq_attr "tune" "marvell_pj4") | |
170 | (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothing*4") | |
171 | ||
172 | (define_insn_reservation "pj4_vfp_divs" 20 | |
173 | (and (eq_attr "tune" "marvell_pj4") | |
174 | (eq_attr "type" "fdivs")) "pj4_is,nothing*2,vissue,vdiv*18,nothing") | |
175 | ||
176 | (define_insn_reservation "pj4_vfp_divd" 34 | |
177 | (and (eq_attr "tune" "marvell_pj4") | |
178 | (eq_attr "type" "fdivd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing") | |
179 | ||
180 | (define_insn_reservation "pj4_vfp_mac" 9 | |
181 | (and (eq_attr "tune" "marvell_pj4") | |
182 | (eq_attr "type" "fmacs,fmacd")) | |
183 | "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothing*3") | |
184 | ||
185 | (define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep") | |
186 | ||
187 | (define_insn_reservation "pj4_vfp_cpy" 4 | |
188 | (and (eq_attr "tune" "marvell_pj4") | |
189 | (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\ | |
190 | fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfast,nothing*2") | |
191 | ||
192 | ;; Enlarge latency, and wish that more nondependent insns are | |
193 | ;; scheduled immediately after VFP load. | |
194 | (define_insn_reservation "pj4_vfp_load" 4 | |
195 | (and (eq_attr "tune" "marvell_pj4") | |
196 | (eq_attr "type" "f_loads,f_loadd")) "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp") | |
197 | ||
198 | (define_insn_reservation "pj4_vfp_store" 1 | |
199 | (and (eq_attr "tune" "marvell_pj4") | |
200 | (eq_attr "type" "f_stores,f_stored")) "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp") | |
201 | ||
202 | (define_insn_reservation "pj4_vfp_to_core" 7 | |
203 | (and (eq_attr "tune" "marvell_pj4") | |
003bb7f3 | 204 | (eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2") |
92607e41 YHH |
205 | |
206 | (define_insn_reservation "pj4_core_to_vfp" 2 | |
207 | (and (eq_attr "tune" "marvell_pj4") | |
003bb7f3 | 208 | (eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp") |
92607e41 | 209 |