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[ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix.
[thirdparty/gcc.git] / gcc / config / arm / mve.md
CommitLineData
63c8f7d6
SP		 1;; Arm M-profile Vector Extension Machine Description
2;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful, but
12;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14;; General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
19
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SP		 20(define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
21 (V2DI "u64")])
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SP		 22(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
23(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
a50f6abf 24(define_mode_iterator MVE_0 [V8HF V4SF])
f166a8cd 25(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
6df4618c 26(define_mode_iterator MVE_3 [V16QI V8HI])
5db0eb95
SP		 27(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
28(define_mode_iterator MVE_5 [V8HI V4SI])
14782c81 29
a50f6abf
SP		 30(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
31 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
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SP		 32 VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
33 VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
34 VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
35 VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
36 VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
37 VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
38 VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
39 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
4be8cf77
SP		 40 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
41 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
f166a8cd 42 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
d71dba7b 43 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
33203b4c
SP		 44 VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
45 VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
46 VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
47 VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
48 VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
49 VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
50 VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
51 VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
52 VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
53 VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
54 VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
55 VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
56 VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
57 VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
58 VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
59 VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
60 VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
61 VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
62 VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
63 VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
64 VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
65 VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
66 VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
67 VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
68 VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
f9355dee
SP		 69 VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
70 VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
71 VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
72 VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
73 VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
74 VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
75 VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
76 VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
77 VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
78 VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
79 VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
80 VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
81 VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
82 VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
83 VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
84 VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
85 VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
86 VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
87 VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
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SP		 88 VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
89 VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
90 VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
91 VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
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SP		 92 VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
93 VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
94 VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
95 VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
96 VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
97 VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
98 VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
99 VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
100 VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
101 VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
102 VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
103 VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
104 VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
105 VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
106 VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
107 VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
108 VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
109 VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
110 VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
111 VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
112 VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
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SP		 113 VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
114 VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
115 VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
116 VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
117 VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
118 VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
119 VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
120 VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
121 VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
122 VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
123 VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
124 VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
125 VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
126 VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
127 VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
128 VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
129 VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
130 VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
131 VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
132 VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
133 VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
134 VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
135 VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
136 VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
137 VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
138 VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
139 VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
140 VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
141 VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
142 VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
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SP		 143 VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
144 VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
145 VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
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SP		 146 VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
147 VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
148 VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
149 VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
150 VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
151 VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
152 VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
153 VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
154 VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
155 VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
156 VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
157 VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
158 VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
159 VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
160 VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
161 VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
162 VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
163 VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
164 VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
165 VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
166 VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
167 VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
168 VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
169 VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
170 VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
171 VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
172 VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
173 VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
174 VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
175 VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
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SP		 176 VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
177 VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
178 VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
179 VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
180 VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
181 VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
182 VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
183 VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
184 VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
185 VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
186 VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
187 VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
188 VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
532e9e24
SP		 189 VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
190 VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
191 VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
192 VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
193 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
4ff68575 194 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
535a8645
SP		 195 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
196 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U])
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SP		 197
198(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
199 (V8HF "V8HI") (V4SF "V4SI")])
200
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SP		 201(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
202 (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
203 (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
204 (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
205 (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
206 (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
207 (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
208 (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
209 (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
210 (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
211 (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
4be8cf77 212 (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
f166a8cd
SP		 213 (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
214 (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
d71dba7b
SP		 215 (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
216 (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
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SP		 217 (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
218 (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
219 (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
220 (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
221 (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
222 (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
223 (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
224 (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
225 (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
226 (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
227 (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
228 (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
229 (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
230 (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
231 (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
232 (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
233 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
234 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
235 (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
236 (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
237 (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
238 (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
239 (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
240 (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
241 (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
242 (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
243 (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
244 (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
245 (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
246 (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
247 (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
248 (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
f9355dee
SP		 249 (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
250 (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
251 (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
252 (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
253 (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
254 (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
255 (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
256 (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
0dad5b33
SP		 257 (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
258 (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
259 (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
260 (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
261 (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
8165795c
SP		 262 (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
263 (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
264 (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
265 (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
266 (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
267 (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
268 (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
269 (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
270 (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
271 (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
272 (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
273 (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
274 (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
275 (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
276 (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
277 (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
278 (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
e3678b44
SP		 279 (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
280 (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
281 (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
282 (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
283 (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
284 (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
285 (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
286 (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
287 (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
288 (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
289 (VREV16Q_M_S "s") (VREV16Q_M_U "u")
290 (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
291 (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
292 (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
293 (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
294 (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
295 (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
296 (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
297 (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
298 (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
299 (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
db5db9d2
SP		 300 (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
301 (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
302 (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
303 (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
8eb3b6b9
SP		 304 (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
305 (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
306 (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
307 (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
308 (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
309 (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
310 (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
311 (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
312 (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
313 (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
314 (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
315 (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
316 (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
317 (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
318 (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
319 (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
320 (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
321 (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
322 (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
323 (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
324 (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
325 (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
326 (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
327 (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
328 (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
329 (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
330 (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
331 (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
332 (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
333 (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
f2170a37
SP		 334 (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
335 (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
336 (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
337 (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
338 (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
339 (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
340 (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
341 (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
342 (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
343 (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
344 (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
345 (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
346 (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
4ff68575
SP		 347 (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
348 (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
535a8645
SP		 349 (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
350 (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
351 (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")])
5db0eb95 352
a475f153 353(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
f9355dee
SP		 354 (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
355 (VCTP32Q_M "32") (VCTP64Q_M "64")])
f166a8cd
SP		 356(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
357 (V4SI "mve_imm_32")])
358(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
33203b4c 359(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
8165795c
SP		 360(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
361(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
362 (V4SI "mve_imm_31")])
e3678b44
SP		 363(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
364(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
365
366(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
367(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
4ff68575 368(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
a475f153 369
a50f6abf 370(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
5db0eb95
SP		 371(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
372(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
373(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
6df4618c
SP		 374(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
375(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
376(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
377(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
378(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
379(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
380(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
381(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
382(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
383(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
384(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
385(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
386(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
a475f153 387(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
f9355dee 388(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
4be8cf77 389(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
f166a8cd
SP		 390(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
391(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
392(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
d71dba7b
SP		 393(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
394(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
395(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
33203b4c
SP		 396(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
397(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
398(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
399(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
400(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
401(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
402(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
403(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
404(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
405(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
406(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
407(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
408(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
409(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
410(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
411(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
412(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
413(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
414(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
415(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
416(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
417(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
418(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
419(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
420(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
421(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
422(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
423(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
424(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
425(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
426(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
427(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
428(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
429(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
430(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
431(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
432(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
433(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
434(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
435(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
436(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
437(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
438(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
439(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
440(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
441(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
442(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
f9355dee
SP		 443(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
444(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
445(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
446(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
447(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
448(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
449(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
450(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
451(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
452(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
453(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
454(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
0dad5b33
SP		 455(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
456(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
457(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
458(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
459(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
460(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
461(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
8165795c
SP		 462(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
463(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
464(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
465(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
466(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
467(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
468(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
469(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
470(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
471(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
472(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
473(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
474(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
475(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
476(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
477(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
478(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
479(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
480(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
481(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
482(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
483(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
484(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
485(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
486(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
e3678b44
SP		 487(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
488(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
489(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
490(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
491(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
492(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
493(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
494(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
495(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
496(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
497(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
498(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
499(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
500(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
501(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
502(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
503(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
504(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
505(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
506(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
507(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
508(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
509(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
510(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
511(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
512(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
513(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
514(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
db5db9d2
SP		 515(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
516(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
517(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
518(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
519(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
8eb3b6b9
SP		 520(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
521(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
522(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
523(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
524(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
525(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
526(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
527(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
528(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
529(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
530(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
531(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
532(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
533(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
534(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
535(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
536(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
537(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
538(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
539(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
540(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
541(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
542(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
543(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
544(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
545(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
546(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
547(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
548(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
549(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
550(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
551(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
552(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
553(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
554(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
555(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
556(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
557(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
558(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
559(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
f2170a37
SP		 560(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
561(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
562(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
563(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
564(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
565(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
566(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
567(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
568(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
569(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
570(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
571(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
4ff68575
SP		 572(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
573(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
574(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
535a8645
SP		 575(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
576(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
577(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
63c8f7d6
SP		 578
579(define_insn "*mve_mov<mode>"
580 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
581 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
582 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
583{
584 if (which_alternative == 3 || which_alternative == 6)
585 {
586 int width, is_valid;
587 static char templ[40];
588
589 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
590 &operands[1], &width);
591
592 gcc_assert (is_valid != 0);
593
594 if (width == 0)
595 return "vmov.f32\t%q0, %1 @ <mode>";
596 else
597 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
598 return templ;
599 }
600 switch (which_alternative)
601 {
602 case 0:
603 return "vmov\t%q0, %q1";
604 case 1:
605 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
606 case 2:
607 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
608 case 4:
609 if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
610 || (MEM_P (operands[1])
611 && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
612 return output_move_neon (operands);
613 else
614 return "vldrb.8 %q0, %E1";
615 case 5:
616 return output_move_neon (operands);
617 case 7:
618 return "vstrb.8 %q1, %E0";
619 default:
620 gcc_unreachable ();
621 return "";
622 }
623}
624 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
625 (set_attr "length" "4,8,8,4,8,8,4,4")
626 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
627 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
628
629(define_insn "*mve_mov<mode>"
630 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
631 (vec_duplicate:MVE_types
632 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
633 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
634{
635 if (which_alternative == 0)
636 return "vdup.<V_sz_elem>\t%q0, %1";
637 return "vmov.<V_sz_elem>\t%q0, %1";
638}
639 [(set_attr "length" "4,4")
640 (set_attr "type" "mve_move,mve_move")])
14782c81
SP		 641
642;;
643;; [vst4q])
644;;
645(define_insn "mve_vst4q<mode>"
646 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
647 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
648 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
649 VST4Q))
650 ]
651 "TARGET_HAVE_MVE"
652{
653 rtx ops[6];
654 int regno = REGNO (operands[1]);
655 ops[0] = gen_rtx_REG (TImode, regno);
656 ops[1] = gen_rtx_REG (TImode, regno+4);
657 ops[2] = gen_rtx_REG (TImode, regno+8);
658 ops[3] = gen_rtx_REG (TImode, regno+12);
659 rtx reg = operands[0];
660 while (reg && !REG_P (reg))
661 reg = XEXP (reg, 0);
662 gcc_assert (REG_P (reg));
663 ops[4] = reg;
664 ops[5] = operands[0];
665 /* Here in first three instructions data is stored to ops[4]'s location but
666 in the fourth instruction data is stored to operands[0], this is to
667 support the writeback. */
668 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
669 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
670 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
671 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
672 return "";
673}
674 [(set_attr "length" "16")])
a50f6abf 675
e3678b44
SP		 676;;
677;; [vrndq_m_f])
678;;
679(define_insn "mve_vrndq_m_f<mode>"
680 [
681 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
682 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
683 (match_operand:MVE_0 2 "s_register_operand" "w")
684 (match_operand:HI 3 "vpr_register_operand" "Up")]
685 VRNDQ_M_F))
686 ]
687 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
688 "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
689 [(set_attr "type" "mve_move")
690 (set_attr "length""8")])
691
a50f6abf
SP		 692;;
693;; [vrndxq_f])
694;;
695(define_insn "mve_vrndxq_f<mode>"
696 [
697 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
698 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
699 VRNDXQ_F))
700 ]
701 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
702 "vrintx.f%#<V_sz_elem> %q0, %q1"
703 [(set_attr "type" "mve_move")
704])
705
706;;
707;; [vrndq_f])
708;;
709(define_insn "mve_vrndq_f<mode>"
710 [
711 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
712 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
713 VRNDQ_F))
714 ]
715 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
716 "vrintz.f%#<V_sz_elem> %q0, %q1"
717 [(set_attr "type" "mve_move")
718])
719
720;;
721;; [vrndpq_f])
722;;
723(define_insn "mve_vrndpq_f<mode>"
724 [
725 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
726 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
727 VRNDPQ_F))
728 ]
729 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
730 "vrintp.f%#<V_sz_elem> %q0, %q1"
731 [(set_attr "type" "mve_move")
732])
733
734;;
735;; [vrndnq_f])
736;;
737(define_insn "mve_vrndnq_f<mode>"
738 [
739 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
740 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
741 VRNDNQ_F))
742 ]
743 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
744 "vrintn.f%#<V_sz_elem> %q0, %q1"
745 [(set_attr "type" "mve_move")
746])
747
748;;
749;; [vrndmq_f])
750;;
751(define_insn "mve_vrndmq_f<mode>"
752 [
753 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
754 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
755 VRNDMQ_F))
756 ]
757 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
758 "vrintm.f%#<V_sz_elem> %q0, %q1"
759 [(set_attr "type" "mve_move")
760])
761
762;;
763;; [vrndaq_f])
764;;
765(define_insn "mve_vrndaq_f<mode>"
766 [
767 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
768 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
769 VRNDAQ_F))
770 ]
771 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
772 "vrinta.f%#<V_sz_elem> %q0, %q1"
773 [(set_attr "type" "mve_move")
774])
775
776;;
777;; [vrev64q_f])
778;;
779(define_insn "mve_vrev64q_f<mode>"
780 [
781 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
782 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
783 VREV64Q_F))
784 ]
785 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
786 "vrev64.%#<V_sz_elem> %q0, %q1"
787 [(set_attr "type" "mve_move")
788])
789
790;;
791;; [vnegq_f])
792;;
793(define_insn "mve_vnegq_f<mode>"
794 [
795 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
796 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
797 VNEGQ_F))
798 ]
799 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
800 "vneg.f%#<V_sz_elem> %q0, %q1"
801 [(set_attr "type" "mve_move")
802])
803
804;;
805;; [vdupq_n_f])
806;;
807(define_insn "mve_vdupq_n_f<mode>"
808 [
809 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
810 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
811 VDUPQ_N_F))
812 ]
813 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
814 "vdup.%#<V_sz_elem> %q0, %1"
815 [(set_attr "type" "mve_move")
816])
817
818;;
819;; [vabsq_f])
820;;
821(define_insn "mve_vabsq_f<mode>"
822 [
823 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
824 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
825 VABSQ_F))
826 ]
827 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
828 "vabs.f%#<V_sz_elem> %q0, %q1"
829 [(set_attr "type" "mve_move")
830])
831
832;;
833;; [vrev32q_f])
834;;
835(define_insn "mve_vrev32q_fv8hf"
836 [
837 (set (match_operand:V8HF 0 "s_register_operand" "=w")
838 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
839 VREV32Q_F))
840 ]
841 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
842 "vrev32.16 %q0, %q1"
843 [(set_attr "type" "mve_move")
844])
845;;
846;; [vcvttq_f32_f16])
847;;
848(define_insn "mve_vcvttq_f32_f16v4sf"
849 [
850 (set (match_operand:V4SF 0 "s_register_operand" "=w")
851 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
852 VCVTTQ_F32_F16))
853 ]
854 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
855 "vcvtt.f32.f16 %q0, %q1"
856 [(set_attr "type" "mve_move")
857])
858
859;;
860;; [vcvtbq_f32_f16])
861;;
862(define_insn "mve_vcvtbq_f32_f16v4sf"
863 [
864 (set (match_operand:V4SF 0 "s_register_operand" "=w")
865 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
866 VCVTBQ_F32_F16))
867 ]
868 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
869 "vcvtb.f32.f16 %q0, %q1"
870 [(set_attr "type" "mve_move")
871])
872
873;;
874;; [vcvtq_to_f_s, vcvtq_to_f_u])
875;;
876(define_insn "mve_vcvtq_to_f_<supf><mode>"
877 [
878 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
879 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
880 VCVTQ_TO_F))
881 ]
882 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
883 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
884 [(set_attr "type" "mve_move")
885])
5db0eb95
SP		 886
887;;
888;; [vrev64q_u, vrev64q_s])
889;;
890(define_insn "mve_vrev64q_<supf><mode>"
891 [
892 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
893 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
894 VREV64Q))
895 ]
896 "TARGET_HAVE_MVE"
897 "vrev64.%#<V_sz_elem> %q0, %q1"
898 [(set_attr "type" "mve_move")
899])
900
901;;
902;; [vcvtq_from_f_s, vcvtq_from_f_u])
903;;
904(define_insn "mve_vcvtq_from_f_<supf><mode>"
905 [
906 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
907 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
908 VCVTQ_FROM_F))
909 ]
910 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
911 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
912 [(set_attr "type" "mve_move")
913])
6df4618c
SP		 914;; [vqnegq_s])
915;;
916(define_insn "mve_vqnegq_s<mode>"
917 [
918 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
919 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
920 VQNEGQ_S))
921 ]
922 "TARGET_HAVE_MVE"
923 "vqneg.s%#<V_sz_elem> %q0, %q1"
924 [(set_attr "type" "mve_move")
925])
926
927;;
928;; [vqabsq_s])
929;;
930(define_insn "mve_vqabsq_s<mode>"
931 [
932 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
933 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
934 VQABSQ_S))
935 ]
936 "TARGET_HAVE_MVE"
937 "vqabs.s%#<V_sz_elem> %q0, %q1"
938 [(set_attr "type" "mve_move")
939])
940
941;;
942;; [vnegq_s])
943;;
944(define_insn "mve_vnegq_s<mode>"
945 [
946 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
947 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
948 VNEGQ_S))
949 ]
950 "TARGET_HAVE_MVE"
951 "vneg.s%#<V_sz_elem> %q0, %q1"
952 [(set_attr "type" "mve_move")
953])
954
955;;
956;; [vmvnq_u, vmvnq_s])
957;;
958(define_insn "mve_vmvnq_<supf><mode>"
959 [
960 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
961 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
962 VMVNQ))
963 ]
964 "TARGET_HAVE_MVE"
965 "vmvn %q0, %q1"
966 [(set_attr "type" "mve_move")
967])
968
969;;
970;; [vdupq_n_u, vdupq_n_s])
971;;
972(define_insn "mve_vdupq_n_<supf><mode>"
973 [
974 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
975 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
976 VDUPQ_N))
977 ]
978 "TARGET_HAVE_MVE"
979 "vdup.%#<V_sz_elem> %q0, %1"
980 [(set_attr "type" "mve_move")
981])
982
983;;
984;; [vclzq_u, vclzq_s])
985;;
986(define_insn "mve_vclzq_<supf><mode>"
987 [
988 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
989 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
990 VCLZQ))
991 ]
992 "TARGET_HAVE_MVE"
993 "vclz.i%#<V_sz_elem> %q0, %q1"
994 [(set_attr "type" "mve_move")
995])
996
997;;
998;; [vclsq_s])
999;;
1000(define_insn "mve_vclsq_s<mode>"
1001 [
1002 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1003 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1004 VCLSQ_S))
1005 ]
1006 "TARGET_HAVE_MVE"
1007 "vcls.s%#<V_sz_elem> %q0, %q1"
1008 [(set_attr "type" "mve_move")
1009])
1010
1011;;
1012;; [vaddvq_s, vaddvq_u])
1013;;
1014(define_insn "mve_vaddvq_<supf><mode>"
1015 [
1016 (set (match_operand:SI 0 "s_register_operand" "=e")
1017 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
1018 VADDVQ))
1019 ]
1020 "TARGET_HAVE_MVE"
1021 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
1022 [(set_attr "type" "mve_move")
1023])
1024
1025;;
1026;; [vabsq_s])
1027;;
1028(define_insn "mve_vabsq_s<mode>"
1029 [
1030 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1031 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1032 VABSQ_S))
1033 ]
1034 "TARGET_HAVE_MVE"
1035 "vabs.s%#<V_sz_elem>\t%q0, %q1"
1036 [(set_attr "type" "mve_move")
1037])
1038
1039;;
1040;; [vrev32q_u, vrev32q_s])
1041;;
1042(define_insn "mve_vrev32q_<supf><mode>"
1043 [
1044 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
1045 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
1046 VREV32Q))
1047 ]
1048 "TARGET_HAVE_MVE"
1049 "vrev32.%#<V_sz_elem>\t%q0, %q1"
1050 [(set_attr "type" "mve_move")
1051])
1052
1053;;
1054;; [vmovltq_u, vmovltq_s])
1055;;
1056(define_insn "mve_vmovltq_<supf><mode>"
1057 [
1058 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1059 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1060 VMOVLTQ))
1061 ]
1062 "TARGET_HAVE_MVE"
1063 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
1064 [(set_attr "type" "mve_move")
1065])
1066
1067;;
1068;; [vmovlbq_s, vmovlbq_u])
1069;;
1070(define_insn "mve_vmovlbq_<supf><mode>"
1071 [
1072 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1073 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1074 VMOVLBQ))
1075 ]
1076 "TARGET_HAVE_MVE"
1077 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
1078 [(set_attr "type" "mve_move")
1079])
1080
1081;;
1082;; [vcvtpq_s, vcvtpq_u])
1083;;
1084(define_insn "mve_vcvtpq_<supf><mode>"
1085 [
1086 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1087 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1088 VCVTPQ))
1089 ]
1090 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1091 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1092 [(set_attr "type" "mve_move")
1093])
1094
1095;;
1096;; [vcvtnq_s, vcvtnq_u])
1097;;
1098(define_insn "mve_vcvtnq_<supf><mode>"
1099 [
1100 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1101 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1102 VCVTNQ))
1103 ]
1104 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1105 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1106 [(set_attr "type" "mve_move")
1107])
1108
1109;;
1110;; [vcvtmq_s, vcvtmq_u])
1111;;
1112(define_insn "mve_vcvtmq_<supf><mode>"
1113 [
1114 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1115 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1116 VCVTMQ))
1117 ]
1118 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1119 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1120 [(set_attr "type" "mve_move")
1121])
1122
1123;;
1124;; [vcvtaq_u, vcvtaq_s])
1125;;
1126(define_insn "mve_vcvtaq_<supf><mode>"
1127 [
1128 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1129 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1130 VCVTAQ))
1131 ]
1132 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1133 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1134 [(set_attr "type" "mve_move")
1135])
5db0eb95
SP		 1136
1137;;
1138;; [vmvnq_n_u, vmvnq_n_s])
1139;;
1140(define_insn "mve_vmvnq_n_<supf><mode>"
1141 [
1142 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1143 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
1144 VMVNQ_N))
1145 ]
1146 "TARGET_HAVE_MVE"
1147 "vmvn.i%#<V_sz_elem> %q0, %1"
1148 [(set_attr "type" "mve_move")
1149])
6df4618c
SP		 1150
1151;;
1152;; [vrev16q_u, vrev16q_s])
1153;;
1154(define_insn "mve_vrev16q_<supf>v16qi"
1155 [
1156 (set (match_operand:V16QI 0 "s_register_operand" "=w")
1157 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
1158 VREV16Q))
1159 ]
1160 "TARGET_HAVE_MVE"
1161 "vrev16.8 %q0, %q1"
1162 [(set_attr "type" "mve_move")
1163])
1164
1165;;
1166;; [vaddlvq_s vaddlvq_u])
1167;;
1168(define_insn "mve_vaddlvq_<supf>v4si"
1169 [
1170 (set (match_operand:DI 0 "s_register_operand" "=r")
1171 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
1172 VADDLVQ))
1173 ]
1174 "TARGET_HAVE_MVE"
1175 "vaddlv.<supf>32 %Q0, %R0, %q1"
1176 [(set_attr "type" "mve_move")
1177])
a475f153
SP		 1178
1179;;
1180;; [vctp8q vctp16q vctp32q vctp64q])
1181;;
1182(define_insn "mve_vctp<mode1>qhi"
1183 [
1184 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1185 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
1186 VCTPQ))
1187 ]
1188 "TARGET_HAVE_MVE"
1189 "vctp.<mode1> %1"
1190 [(set_attr "type" "mve_move")
1191])
1192
1193;;
1194;; [vpnot])
1195;;
1196(define_insn "mve_vpnothi"
1197 [
1198 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1199 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
1200 VPNOT))
1201 ]
1202 "TARGET_HAVE_MVE"
1203 "vpnot"
1204 [(set_attr "type" "mve_move")
1205])
4be8cf77
SP		 1206
1207;;
1208;; [vsubq_n_f])
1209;;
1210(define_insn "mve_vsubq_n_f<mode>"
1211 [
1212 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1213 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1214 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1215 VSUBQ_N_F))
1216 ]
1217 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1218 "vsub.f<V_sz_elem> %q0, %q1, %2"
1219 [(set_attr "type" "mve_move")
1220])
1221
1222;;
1223;; [vbrsrq_n_f])
1224;;
1225(define_insn "mve_vbrsrq_n_f<mode>"
1226 [
1227 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1228 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1229 (match_operand:SI 2 "s_register_operand" "r")]
1230 VBRSRQ_N_F))
1231 ]
1232 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1233 "vbrsr.<V_sz_elem> %q0, %q1, %2"
1234 [(set_attr "type" "mve_move")
1235])
1236
1237;;
1238;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
1239;;
1240(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
1241 [
1242 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1243 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1244 (match_operand:SI 2 "mve_imm_16" "Rd")]
1245 VCVTQ_N_TO_F))
1246 ]
1247 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1248 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
1249 [(set_attr "type" "mve_move")
1250])
1251
1252;; [vcreateq_f])
1253;;
1254(define_insn "mve_vcreateq_f<mode>"
1255 [
1256 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1257 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
1258 (match_operand:DI 2 "s_register_operand" "r")]
1259 VCREATEQ_F))
1260 ]
1261 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1262 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1263 [(set_attr "type" "mve_move")
1264 (set_attr "length""8")])
f166a8cd
SP		 1265
1266;;
1267;; [vcreateq_u, vcreateq_s])
1268;;
1269(define_insn "mve_vcreateq_<supf><mode>"
1270 [
1271 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1272 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
1273 (match_operand:DI 2 "s_register_operand" "r")]
1274 VCREATEQ))
1275 ]
1276 "TARGET_HAVE_MVE"
1277 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1278 [(set_attr "type" "mve_move")
1279 (set_attr "length""8")])
1280
1281;;
1282;; [vshrq_n_s, vshrq_n_u])
1283;;
1284(define_insn "mve_vshrq_n_<supf><mode>"
1285 [
1286 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1287 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1288 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1289 VSHRQ_N))
1290 ]
1291 "TARGET_HAVE_MVE"
1292 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
1293 [(set_attr "type" "mve_move")
1294])
1295
1296;;
1297;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
1298;;
1299(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
1300 [
1301 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1302 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1303 (match_operand:SI 2 "mve_imm_16" "Rd")]
1304 VCVTQ_N_FROM_F))
1305 ]
1306 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1307 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
1308 [(set_attr "type" "mve_move")
1309])
d71dba7b
SP		 1310
1311;;
1312;; [vaddlvq_p_s])
1313;;
1314(define_insn "mve_vaddlvq_p_<supf>v4si"
1315 [
1316 (set (match_operand:DI 0 "s_register_operand" "=r")
1317 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1318 (match_operand:HI 2 "vpr_register_operand" "Up")]
1319 VADDLVQ_P))
1320 ]
1321 "TARGET_HAVE_MVE"
1322 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
1323 [(set_attr "type" "mve_move")
1324 (set_attr "length""8")])
1325
1326;;
1327;; [vcmpneq_u, vcmpneq_s])
1328;;
1329(define_insn "mve_vcmpneq_<supf><mode>"
1330 [
1331 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1332 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1333 (match_operand:MVE_2 2 "s_register_operand" "w")]
1334 VCMPNEQ))
1335 ]
1336 "TARGET_HAVE_MVE"
1337 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
1338 [(set_attr "type" "mve_move")
1339])
1340
1341;;
1342;; [vshlq_s, vshlq_u])
1343;;
1344(define_insn "mve_vshlq_<supf><mode>"
1345 [
1346 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1347 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1348 (match_operand:MVE_2 2 "s_register_operand" "w")]
1349 VSHLQ))
1350 ]
1351 "TARGET_HAVE_MVE"
1352 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1353 [(set_attr "type" "mve_move")
1354])
33203b4c
SP		 1355
1356;;
1357;; [vabdq_s, vabdq_u])
1358;;
1359(define_insn "mve_vabdq_<supf><mode>"
1360 [
1361 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1362 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1363 (match_operand:MVE_2 2 "s_register_operand" "w")]
1364 VABDQ))
1365 ]
1366 "TARGET_HAVE_MVE"
1367 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
1368 [(set_attr "type" "mve_move")
1369])
1370
1371;;
1372;; [vaddq_n_s, vaddq_n_u])
1373;;
1374(define_insn "mve_vaddq_n_<supf><mode>"
1375 [
1376 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1377 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1378 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1379 VADDQ_N))
1380 ]
1381 "TARGET_HAVE_MVE"
1382 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
1383 [(set_attr "type" "mve_move")
1384])
1385
1386;;
1387;; [vaddvaq_s, vaddvaq_u])
1388;;
1389(define_insn "mve_vaddvaq_<supf><mode>"
1390 [
1391 (set (match_operand:SI 0 "s_register_operand" "=e")
1392 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1393 (match_operand:MVE_2 2 "s_register_operand" "w")]
1394 VADDVAQ))
1395 ]
1396 "TARGET_HAVE_MVE"
1397 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
1398 [(set_attr "type" "mve_move")
1399])
1400
1401;;
1402;; [vaddvq_p_u, vaddvq_p_s])
1403;;
1404(define_insn "mve_vaddvq_p_<supf><mode>"
1405 [
1406 (set (match_operand:SI 0 "s_register_operand" "=e")
1407 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1408 (match_operand:HI 2 "vpr_register_operand" "Up")]
1409 VADDVQ_P))
1410 ]
1411 "TARGET_HAVE_MVE"
1412 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
1413 [(set_attr "type" "mve_move")
1414 (set_attr "length""8")])
1415
1416;;
1417;; [vandq_u, vandq_s])
1418;;
1419(define_insn "mve_vandq_<supf><mode>"
1420 [
1421 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1422 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1423 (match_operand:MVE_2 2 "s_register_operand" "w")]
1424 VANDQ))
1425 ]
1426 "TARGET_HAVE_MVE"
1427 "vand %q0, %q1, %q2"
1428 [(set_attr "type" "mve_move")
1429])
1430
1431;;
1432;; [vbicq_s, vbicq_u])
1433;;
1434(define_insn "mve_vbicq_<supf><mode>"
1435 [
1436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1437 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1438 (match_operand:MVE_2 2 "s_register_operand" "w")]
1439 VBICQ))
1440 ]
1441 "TARGET_HAVE_MVE"
1442 "vbic %q0, %q1, %q2"
1443 [(set_attr "type" "mve_move")
1444])
1445
1446;;
1447;; [vbrsrq_n_u, vbrsrq_n_s])
1448;;
1449(define_insn "mve_vbrsrq_n_<supf><mode>"
1450 [
1451 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1452 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1453 (match_operand:SI 2 "s_register_operand" "r")]
1454 VBRSRQ_N))
1455 ]
1456 "TARGET_HAVE_MVE"
1457 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
1458 [(set_attr "type" "mve_move")
1459])
1460
1461;;
1462;; [vcaddq_rot270_s, vcaddq_rot270_u])
1463;;
1464(define_insn "mve_vcaddq_rot270_<supf><mode>"
1465 [
1466 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1467 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1468 (match_operand:MVE_2 2 "s_register_operand" "w")]
1469 VCADDQ_ROT270))
1470 ]
1471 "TARGET_HAVE_MVE"
1472 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1473 [(set_attr "type" "mve_move")
1474])
1475
1476;;
1477;; [vcaddq_rot90_u, vcaddq_rot90_s])
1478;;
1479(define_insn "mve_vcaddq_rot90_<supf><mode>"
1480 [
1481 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1482 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1483 (match_operand:MVE_2 2 "s_register_operand" "w")]
1484 VCADDQ_ROT90))
1485 ]
1486 "TARGET_HAVE_MVE"
1487 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1488 [(set_attr "type" "mve_move")
1489])
1490
1491;;
1492;; [vcmpcsq_n_u])
1493;;
1494(define_insn "mve_vcmpcsq_n_u<mode>"
1495 [
1496 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1497 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1498 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1499 VCMPCSQ_N_U))
1500 ]
1501 "TARGET_HAVE_MVE"
1502 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1503 [(set_attr "type" "mve_move")
1504])
1505
1506;;
1507;; [vcmpcsq_u])
1508;;
1509(define_insn "mve_vcmpcsq_u<mode>"
1510 [
1511 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1512 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1513 (match_operand:MVE_2 2 "s_register_operand" "w")]
1514 VCMPCSQ_U))
1515 ]
1516 "TARGET_HAVE_MVE"
1517 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1518 [(set_attr "type" "mve_move")
1519])
1520
1521;;
1522;; [vcmpeqq_n_s, vcmpeqq_n_u])
1523;;
1524(define_insn "mve_vcmpeqq_n_<supf><mode>"
1525 [
1526 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1527 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1528 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1529 VCMPEQQ_N))
1530 ]
1531 "TARGET_HAVE_MVE"
1532 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1533 [(set_attr "type" "mve_move")
1534])
1535
1536;;
1537;; [vcmpeqq_u, vcmpeqq_s])
1538;;
1539(define_insn "mve_vcmpeqq_<supf><mode>"
1540 [
1541 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1542 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1543 (match_operand:MVE_2 2 "s_register_operand" "w")]
1544 VCMPEQQ))
1545 ]
1546 "TARGET_HAVE_MVE"
1547 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1548 [(set_attr "type" "mve_move")
1549])
1550
1551;;
1552;; [vcmpgeq_n_s])
1553;;
1554(define_insn "mve_vcmpgeq_n_s<mode>"
1555 [
1556 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1557 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1558 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1559 VCMPGEQ_N_S))
1560 ]
1561 "TARGET_HAVE_MVE"
1562 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1563 [(set_attr "type" "mve_move")
1564])
1565
1566;;
1567;; [vcmpgeq_s])
1568;;
1569(define_insn "mve_vcmpgeq_s<mode>"
1570 [
1571 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1572 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1573 (match_operand:MVE_2 2 "s_register_operand" "w")]
1574 VCMPGEQ_S))
1575 ]
1576 "TARGET_HAVE_MVE"
1577 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1578 [(set_attr "type" "mve_move")
1579])
1580
1581;;
1582;; [vcmpgtq_n_s])
1583;;
1584(define_insn "mve_vcmpgtq_n_s<mode>"
1585 [
1586 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1587 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1588 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1589 VCMPGTQ_N_S))
1590 ]
1591 "TARGET_HAVE_MVE"
1592 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1593 [(set_attr "type" "mve_move")
1594])
1595
1596;;
1597;; [vcmpgtq_s])
1598;;
1599(define_insn "mve_vcmpgtq_s<mode>"
1600 [
1601 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1602 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1603 (match_operand:MVE_2 2 "s_register_operand" "w")]
1604 VCMPGTQ_S))
1605 ]
1606 "TARGET_HAVE_MVE"
1607 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1608 [(set_attr "type" "mve_move")
1609])
1610
1611;;
1612;; [vcmphiq_n_u])
1613;;
1614(define_insn "mve_vcmphiq_n_u<mode>"
1615 [
1616 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1617 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1618 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1619 VCMPHIQ_N_U))
1620 ]
1621 "TARGET_HAVE_MVE"
1622 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1623 [(set_attr "type" "mve_move")
1624])
1625
1626;;
1627;; [vcmphiq_u])
1628;;
1629(define_insn "mve_vcmphiq_u<mode>"
1630 [
1631 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1632 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1633 (match_operand:MVE_2 2 "s_register_operand" "w")]
1634 VCMPHIQ_U))
1635 ]
1636 "TARGET_HAVE_MVE"
1637 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1638 [(set_attr "type" "mve_move")
1639])
1640
1641;;
1642;; [vcmpleq_n_s])
1643;;
1644(define_insn "mve_vcmpleq_n_s<mode>"
1645 [
1646 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1647 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1648 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1649 VCMPLEQ_N_S))
1650 ]
1651 "TARGET_HAVE_MVE"
1652 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1653 [(set_attr "type" "mve_move")
1654])
1655
1656;;
1657;; [vcmpleq_s])
1658;;
1659(define_insn "mve_vcmpleq_s<mode>"
1660 [
1661 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1662 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1663 (match_operand:MVE_2 2 "s_register_operand" "w")]
1664 VCMPLEQ_S))
1665 ]
1666 "TARGET_HAVE_MVE"
1667 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1668 [(set_attr "type" "mve_move")
1669])
1670
1671;;
1672;; [vcmpltq_n_s])
1673;;
1674(define_insn "mve_vcmpltq_n_s<mode>"
1675 [
1676 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1677 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1678 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1679 VCMPLTQ_N_S))
1680 ]
1681 "TARGET_HAVE_MVE"
1682 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1683 [(set_attr "type" "mve_move")
1684])
1685
1686;;
1687;; [vcmpltq_s])
1688;;
1689(define_insn "mve_vcmpltq_s<mode>"
1690 [
1691 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1692 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1693 (match_operand:MVE_2 2 "s_register_operand" "w")]
1694 VCMPLTQ_S))
1695 ]
1696 "TARGET_HAVE_MVE"
1697 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1698 [(set_attr "type" "mve_move")
1699])
1700
1701;;
1702;; [vcmpneq_n_u, vcmpneq_n_s])
1703;;
1704(define_insn "mve_vcmpneq_n_<supf><mode>"
1705 [
1706 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1707 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1708 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1709 VCMPNEQ_N))
1710 ]
1711 "TARGET_HAVE_MVE"
1712 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1713 [(set_attr "type" "mve_move")
1714])
1715
1716;;
1717;; [veorq_u, veorq_s])
1718;;
1719(define_insn "mve_veorq_<supf><mode>"
1720 [
1721 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1722 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1723 (match_operand:MVE_2 2 "s_register_operand" "w")]
1724 VEORQ))
1725 ]
1726 "TARGET_HAVE_MVE"
1727 "veor %q0, %q1, %q2"
1728 [(set_attr "type" "mve_move")
1729])
1730
1731;;
1732;; [vhaddq_n_u, vhaddq_n_s])
1733;;
1734(define_insn "mve_vhaddq_n_<supf><mode>"
1735 [
1736 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1737 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1738 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1739 VHADDQ_N))
1740 ]
1741 "TARGET_HAVE_MVE"
1742 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1743 [(set_attr "type" "mve_move")
1744])
1745
1746;;
1747;; [vhaddq_s, vhaddq_u])
1748;;
1749(define_insn "mve_vhaddq_<supf><mode>"
1750 [
1751 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1752 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1753 (match_operand:MVE_2 2 "s_register_operand" "w")]
1754 VHADDQ))
1755 ]
1756 "TARGET_HAVE_MVE"
1757 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1758 [(set_attr "type" "mve_move")
1759])
1760
1761;;
1762;; [vhcaddq_rot270_s])
1763;;
1764(define_insn "mve_vhcaddq_rot270_s<mode>"
1765 [
1766 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1767 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1768 (match_operand:MVE_2 2 "s_register_operand" "w")]
1769 VHCADDQ_ROT270_S))
1770 ]
1771 "TARGET_HAVE_MVE"
1772 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1773 [(set_attr "type" "mve_move")
1774])
1775
1776;;
1777;; [vhcaddq_rot90_s])
1778;;
1779(define_insn "mve_vhcaddq_rot90_s<mode>"
1780 [
1781 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1782 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1783 (match_operand:MVE_2 2 "s_register_operand" "w")]
1784 VHCADDQ_ROT90_S))
1785 ]
1786 "TARGET_HAVE_MVE"
1787 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1788 [(set_attr "type" "mve_move")
1789])
1790
1791;;
1792;; [vhsubq_n_u, vhsubq_n_s])
1793;;
1794(define_insn "mve_vhsubq_n_<supf><mode>"
1795 [
1796 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1797 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1798 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1799 VHSUBQ_N))
1800 ]
1801 "TARGET_HAVE_MVE"
1802 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1803 [(set_attr "type" "mve_move")
1804])
1805
1806;;
1807;; [vhsubq_s, vhsubq_u])
1808;;
1809(define_insn "mve_vhsubq_<supf><mode>"
1810 [
1811 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1812 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1813 (match_operand:MVE_2 2 "s_register_operand" "w")]
1814 VHSUBQ))
1815 ]
1816 "TARGET_HAVE_MVE"
1817 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1818 [(set_attr "type" "mve_move")
1819])
1820
1821;;
1822;; [vmaxaq_s])
1823;;
1824(define_insn "mve_vmaxaq_s<mode>"
1825 [
1826 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1827 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1828 (match_operand:MVE_2 2 "s_register_operand" "w")]
1829 VMAXAQ_S))
1830 ]
1831 "TARGET_HAVE_MVE"
1832 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1833 [(set_attr "type" "mve_move")
1834])
1835
1836;;
1837;; [vmaxavq_s])
1838;;
1839(define_insn "mve_vmaxavq_s<mode>"
1840 [
1841 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1842 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1843 (match_operand:MVE_2 2 "s_register_operand" "w")]
1844 VMAXAVQ_S))
1845 ]
1846 "TARGET_HAVE_MVE"
1847 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1848 [(set_attr "type" "mve_move")
1849])
1850
1851;;
1852;; [vmaxq_u, vmaxq_s])
1853;;
1854(define_insn "mve_vmaxq_<supf><mode>"
1855 [
1856 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1857 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1858 (match_operand:MVE_2 2 "s_register_operand" "w")]
1859 VMAXQ))
1860 ]
1861 "TARGET_HAVE_MVE"
1862 "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1863 [(set_attr "type" "mve_move")
1864])
1865
1866;;
1867;; [vmaxvq_u, vmaxvq_s])
1868;;
1869(define_insn "mve_vmaxvq_<supf><mode>"
1870 [
1871 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1872 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1873 (match_operand:MVE_2 2 "s_register_operand" "w")]
1874 VMAXVQ))
1875 ]
1876 "TARGET_HAVE_MVE"
1877 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1878 [(set_attr "type" "mve_move")
1879])
1880
1881;;
1882;; [vminaq_s])
1883;;
1884(define_insn "mve_vminaq_s<mode>"
1885 [
1886 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1887 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1888 (match_operand:MVE_2 2 "s_register_operand" "w")]
1889 VMINAQ_S))
1890 ]
1891 "TARGET_HAVE_MVE"
1892 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1893 [(set_attr "type" "mve_move")
1894])
1895
1896;;
1897;; [vminavq_s])
1898;;
1899(define_insn "mve_vminavq_s<mode>"
1900 [
1901 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1902 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1903 (match_operand:MVE_2 2 "s_register_operand" "w")]
1904 VMINAVQ_S))
1905 ]
1906 "TARGET_HAVE_MVE"
1907 "vminav.s%#<V_sz_elem>\t%0, %q2"
1908 [(set_attr "type" "mve_move")
1909])
1910
1911;;
1912;; [vminq_s, vminq_u])
1913;;
1914(define_insn "mve_vminq_<supf><mode>"
1915 [
1916 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1917 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1918 (match_operand:MVE_2 2 "s_register_operand" "w")]
1919 VMINQ))
1920 ]
1921 "TARGET_HAVE_MVE"
1922 "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1923 [(set_attr "type" "mve_move")
1924])
1925
1926;;
1927;; [vminvq_u, vminvq_s])
1928;;
1929(define_insn "mve_vminvq_<supf><mode>"
1930 [
1931 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1932 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1933 (match_operand:MVE_2 2 "s_register_operand" "w")]
1934 VMINVQ))
1935 ]
1936 "TARGET_HAVE_MVE"
1937 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1938 [(set_attr "type" "mve_move")
1939])
1940
1941;;
1942;; [vmladavq_u, vmladavq_s])
1943;;
1944(define_insn "mve_vmladavq_<supf><mode>"
1945 [
1946 (set (match_operand:SI 0 "s_register_operand" "=e")
1947 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1948 (match_operand:MVE_2 2 "s_register_operand" "w")]
1949 VMLADAVQ))
1950 ]
1951 "TARGET_HAVE_MVE"
1952 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1953 [(set_attr "type" "mve_move")
1954])
1955
1956;;
1957;; [vmladavxq_s])
1958;;
1959(define_insn "mve_vmladavxq_s<mode>"
1960 [
1961 (set (match_operand:SI 0 "s_register_operand" "=e")
1962 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1963 (match_operand:MVE_2 2 "s_register_operand" "w")]
1964 VMLADAVXQ_S))
1965 ]
1966 "TARGET_HAVE_MVE"
1967 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1968 [(set_attr "type" "mve_move")
1969])
1970
1971;;
1972;; [vmlsdavq_s])
1973;;
1974(define_insn "mve_vmlsdavq_s<mode>"
1975 [
1976 (set (match_operand:SI 0 "s_register_operand" "=e")
1977 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1978 (match_operand:MVE_2 2 "s_register_operand" "w")]
1979 VMLSDAVQ_S))
1980 ]
1981 "TARGET_HAVE_MVE"
1982 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
1983 [(set_attr "type" "mve_move")
1984])
1985
1986;;
1987;; [vmlsdavxq_s])
1988;;
1989(define_insn "mve_vmlsdavxq_s<mode>"
1990 [
1991 (set (match_operand:SI 0 "s_register_operand" "=e")
1992 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1993 (match_operand:MVE_2 2 "s_register_operand" "w")]
1994 VMLSDAVXQ_S))
1995 ]
1996 "TARGET_HAVE_MVE"
1997 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1998 [(set_attr "type" "mve_move")
1999])
2000
2001;;
2002;; [vmulhq_s, vmulhq_u])
2003;;
2004(define_insn "mve_vmulhq_<supf><mode>"
2005 [
2006 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2007 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2008 (match_operand:MVE_2 2 "s_register_operand" "w")]
2009 VMULHQ))
2010 ]
2011 "TARGET_HAVE_MVE"
2012 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2013 [(set_attr "type" "mve_move")
2014])
2015
2016;;
2017;; [vmullbq_int_u, vmullbq_int_s])
2018;;
2019(define_insn "mve_vmullbq_int_<supf><mode>"
2020 [
2021 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2022 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2023 (match_operand:MVE_2 2 "s_register_operand" "w")]
2024 VMULLBQ_INT))
2025 ]
2026 "TARGET_HAVE_MVE"
2027 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2028 [(set_attr "type" "mve_move")
2029])
2030
2031;;
2032;; [vmulltq_int_u, vmulltq_int_s])
2033;;
2034(define_insn "mve_vmulltq_int_<supf><mode>"
2035 [
2036 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2037 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2038 (match_operand:MVE_2 2 "s_register_operand" "w")]
2039 VMULLTQ_INT))
2040 ]
2041 "TARGET_HAVE_MVE"
2042 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2043 [(set_attr "type" "mve_move")
2044])
2045
2046;;
2047;; [vmulq_n_u, vmulq_n_s])
2048;;
2049(define_insn "mve_vmulq_n_<supf><mode>"
2050 [
2051 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2052 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2053 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2054 VMULQ_N))
2055 ]
2056 "TARGET_HAVE_MVE"
2057 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
2058 [(set_attr "type" "mve_move")
2059])
2060
2061;;
2062;; [vmulq_u, vmulq_s])
2063;;
2064(define_insn "mve_vmulq_<supf><mode>"
2065 [
2066 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2067 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2068 (match_operand:MVE_2 2 "s_register_operand" "w")]
2069 VMULQ))
2070 ]
2071 "TARGET_HAVE_MVE"
2072 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
2073 [(set_attr "type" "mve_move")
2074])
2075
2076;;
2077;; [vornq_u, vornq_s])
2078;;
2079(define_insn "mve_vornq_<supf><mode>"
2080 [
2081 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2082 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2083 (match_operand:MVE_2 2 "s_register_operand" "w")]
2084 VORNQ))
2085 ]
2086 "TARGET_HAVE_MVE"
2087 "vorn %q0, %q1, %q2"
2088 [(set_attr "type" "mve_move")
2089])
2090
2091;;
2092;; [vorrq_s, vorrq_u])
2093;;
2094(define_insn "mve_vorrq_<supf><mode>"
2095 [
2096 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2097 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2098 (match_operand:MVE_2 2 "s_register_operand" "w")]
2099 VORRQ))
2100 ]
2101 "TARGET_HAVE_MVE"
2102 "vorr %q0, %q1, %q2"
2103 [(set_attr "type" "mve_move")
2104])
2105
2106;;
2107;; [vqaddq_n_s, vqaddq_n_u])
2108;;
2109(define_insn "mve_vqaddq_n_<supf><mode>"
2110 [
2111 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2112 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2113 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2114 VQADDQ_N))
2115 ]
2116 "TARGET_HAVE_MVE"
2117 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2118 [(set_attr "type" "mve_move")
2119])
2120
2121;;
2122;; [vqaddq_u, vqaddq_s])
2123;;
2124(define_insn "mve_vqaddq_<supf><mode>"
2125 [
2126 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2127 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2128 (match_operand:MVE_2 2 "s_register_operand" "w")]
2129 VQADDQ))
2130 ]
2131 "TARGET_HAVE_MVE"
2132 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2133 [(set_attr "type" "mve_move")
2134])
2135
2136;;
2137;; [vqdmulhq_n_s])
2138;;
2139(define_insn "mve_vqdmulhq_n_s<mode>"
2140 [
2141 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2142 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2143 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2144 VQDMULHQ_N_S))
2145 ]
2146 "TARGET_HAVE_MVE"
2147 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2148 [(set_attr "type" "mve_move")
2149])
2150
2151;;
2152;; [vqdmulhq_s])
2153;;
2154(define_insn "mve_vqdmulhq_s<mode>"
2155 [
2156 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2157 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2158 (match_operand:MVE_2 2 "s_register_operand" "w")]
2159 VQDMULHQ_S))
2160 ]
2161 "TARGET_HAVE_MVE"
2162 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2163 [(set_attr "type" "mve_move")
2164])
2165
2166;;
2167;; [vqrdmulhq_n_s])
2168;;
2169(define_insn "mve_vqrdmulhq_n_s<mode>"
2170 [
2171 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2172 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2173 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2174 VQRDMULHQ_N_S))
2175 ]
2176 "TARGET_HAVE_MVE"
2177 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2178 [(set_attr "type" "mve_move")
2179])
2180
2181;;
2182;; [vqrdmulhq_s])
2183;;
2184(define_insn "mve_vqrdmulhq_s<mode>"
2185 [
2186 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2187 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2188 (match_operand:MVE_2 2 "s_register_operand" "w")]
2189 VQRDMULHQ_S))
2190 ]
2191 "TARGET_HAVE_MVE"
2192 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2193 [(set_attr "type" "mve_move")
2194])
2195
2196;;
2197;; [vqrshlq_n_s, vqrshlq_n_u])
2198;;
2199(define_insn "mve_vqrshlq_n_<supf><mode>"
2200 [
2201 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2202 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2203 (match_operand:SI 2 "s_register_operand" "r")]
2204 VQRSHLQ_N))
2205 ]
2206 "TARGET_HAVE_MVE"
2207 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2208 [(set_attr "type" "mve_move")
2209])
2210
2211;;
2212;; [vqrshlq_s, vqrshlq_u])
2213;;
2214(define_insn "mve_vqrshlq_<supf><mode>"
2215 [
2216 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2217 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2218 (match_operand:MVE_2 2 "s_register_operand" "w")]
2219 VQRSHLQ))
2220 ]
2221 "TARGET_HAVE_MVE"
2222 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2223 [(set_attr "type" "mve_move")
2224])
2225
2226;;
2227;; [vqshlq_n_s, vqshlq_n_u])
2228;;
2229(define_insn "mve_vqshlq_n_<supf><mode>"
2230 [
2231 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2232 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2233 (match_operand:SI 2 "immediate_operand" "i")]
2234 VQSHLQ_N))
2235 ]
2236 "TARGET_HAVE_MVE"
2237 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2238 [(set_attr "type" "mve_move")
2239])
2240
2241;;
2242;; [vqshlq_r_u, vqshlq_r_s])
2243;;
2244(define_insn "mve_vqshlq_r_<supf><mode>"
2245 [
2246 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2247 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2248 (match_operand:SI 2 "s_register_operand" "r")]
2249 VQSHLQ_R))
2250 ]
2251 "TARGET_HAVE_MVE"
2252 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
2253 [(set_attr "type" "mve_move")
2254])
2255
2256;;
2257;; [vqshlq_s, vqshlq_u])
2258;;
2259(define_insn "mve_vqshlq_<supf><mode>"
2260 [
2261 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2263 (match_operand:MVE_2 2 "s_register_operand" "w")]
2264 VQSHLQ))
2265 ]
2266 "TARGET_HAVE_MVE"
2267 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2268 [(set_attr "type" "mve_move")
2269])
2270
2271;;
2272;; [vqshluq_n_s])
2273;;
2274(define_insn "mve_vqshluq_n_s<mode>"
2275 [
2276 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2277 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2278 (match_operand:SI 2 "mve_imm_7" "Ra")]
2279 VQSHLUQ_N_S))
2280 ]
2281 "TARGET_HAVE_MVE"
2282 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
2283 [(set_attr "type" "mve_move")
2284])
2285
2286;;
2287;; [vqsubq_n_s, vqsubq_n_u])
2288;;
2289(define_insn "mve_vqsubq_n_<supf><mode>"
2290 [
2291 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2292 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2293 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2294 VQSUBQ_N))
2295 ]
2296 "TARGET_HAVE_MVE"
2297 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2298 [(set_attr "type" "mve_move")
2299])
2300
2301;;
2302;; [vqsubq_u, vqsubq_s])
2303;;
2304(define_insn "mve_vqsubq_<supf><mode>"
2305 [
2306 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2307 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2308 (match_operand:MVE_2 2 "s_register_operand" "w")]
2309 VQSUBQ))
2310 ]
2311 "TARGET_HAVE_MVE"
2312 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2313 [(set_attr "type" "mve_move")
2314])
2315
2316;;
2317;; [vrhaddq_s, vrhaddq_u])
2318;;
2319(define_insn "mve_vrhaddq_<supf><mode>"
2320 [
2321 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2322 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2323 (match_operand:MVE_2 2 "s_register_operand" "w")]
2324 VRHADDQ))
2325 ]
2326 "TARGET_HAVE_MVE"
2327 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2328 [(set_attr "type" "mve_move")
2329])
2330
2331;;
2332;; [vrmulhq_s, vrmulhq_u])
2333;;
2334(define_insn "mve_vrmulhq_<supf><mode>"
2335 [
2336 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2337 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2338 (match_operand:MVE_2 2 "s_register_operand" "w")]
2339 VRMULHQ))
2340 ]
2341 "TARGET_HAVE_MVE"
2342 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2343 [(set_attr "type" "mve_move")
2344])
2345
2346;;
2347;; [vrshlq_n_u, vrshlq_n_s])
2348;;
2349(define_insn "mve_vrshlq_n_<supf><mode>"
2350 [
2351 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2352 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2353 (match_operand:SI 2 "s_register_operand" "r")]
2354 VRSHLQ_N))
2355 ]
2356 "TARGET_HAVE_MVE"
2357 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2358 [(set_attr "type" "mve_move")
2359])
2360
2361;;
2362;; [vrshlq_s, vrshlq_u])
2363;;
2364(define_insn "mve_vrshlq_<supf><mode>"
2365 [
2366 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2367 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2368 (match_operand:MVE_2 2 "s_register_operand" "w")]
2369 VRSHLQ))
2370 ]
2371 "TARGET_HAVE_MVE"
2372 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2373 [(set_attr "type" "mve_move")
2374])
2375
2376;;
2377;; [vrshrq_n_s, vrshrq_n_u])
2378;;
2379(define_insn "mve_vrshrq_n_<supf><mode>"
2380 [
2381 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2382 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2383 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2384 VRSHRQ_N))
2385 ]
2386 "TARGET_HAVE_MVE"
2387 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2388 [(set_attr "type" "mve_move")
2389])
2390
2391;;
2392;; [vshlq_n_u, vshlq_n_s])
2393;;
2394(define_insn "mve_vshlq_n_<supf><mode>"
2395 [
2396 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2397 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2398 (match_operand:SI 2 "immediate_operand" "i")]
2399 VSHLQ_N))
2400 ]
2401 "TARGET_HAVE_MVE"
2402 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2403 [(set_attr "type" "mve_move")
2404])
2405
2406;;
2407;; [vshlq_r_s, vshlq_r_u])
2408;;
2409(define_insn "mve_vshlq_r_<supf><mode>"
2410 [
2411 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2412 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2413 (match_operand:SI 2 "s_register_operand" "r")]
2414 VSHLQ_R))
2415 ]
2416 "TARGET_HAVE_MVE"
2417 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2418 [(set_attr "type" "mve_move")
2419])
2420
2421;;
2422;; [vsubq_n_s, vsubq_n_u])
2423;;
2424(define_insn "mve_vsubq_n_<supf><mode>"
2425 [
2426 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2427 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2428 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2429 VSUBQ_N))
2430 ]
2431 "TARGET_HAVE_MVE"
2432 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2433 [(set_attr "type" "mve_move")
2434])
2435
2436;;
2437;; [vsubq_s, vsubq_u])
2438;;
2439(define_insn "mve_vsubq_<supf><mode>"
2440 [
2441 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2442 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2443 (match_operand:MVE_2 2 "s_register_operand" "w")]
2444 VSUBQ))
2445 ]
2446 "TARGET_HAVE_MVE"
2447 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2448 [(set_attr "type" "mve_move")
2449])
f9355dee
SP		 2450
2451;;
2452;; [vabdq_f])
2453;;
2454(define_insn "mve_vabdq_f<mode>"
2455 [
2456 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2457 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2458 (match_operand:MVE_0 2 "s_register_operand" "w")]
2459 VABDQ_F))
2460 ]
2461 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2462 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2463 [(set_attr "type" "mve_move")
2464])
2465
2466;;
2467;; [vaddlvaq_s vaddlvaq_u])
2468;;
2469(define_insn "mve_vaddlvaq_<supf>v4si"
2470 [
2471 (set (match_operand:DI 0 "s_register_operand" "=r")
2472 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2473 (match_operand:V4SI 2 "s_register_operand" "w")]
2474 VADDLVAQ))
2475 ]
2476 "TARGET_HAVE_MVE"
2477 "vaddlva.<supf>32 %Q0, %R0, %q2"
2478 [(set_attr "type" "mve_move")
2479])
2480
2481;;
2482;; [vaddq_n_f])
2483;;
2484(define_insn "mve_vaddq_n_f<mode>"
2485 [
2486 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2487 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2488 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2489 VADDQ_N_F))
2490 ]
2491 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2492 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2493 [(set_attr "type" "mve_move")
2494])
2495
2496;;
2497;; [vandq_f])
2498;;
2499(define_insn "mve_vandq_f<mode>"
2500 [
2501 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2502 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2503 (match_operand:MVE_0 2 "s_register_operand" "w")]
2504 VANDQ_F))
2505 ]
2506 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2507 "vand %q0, %q1, %q2"
2508 [(set_attr "type" "mve_move")
2509])
2510
2511;;
2512;; [vbicq_f])
2513;;
2514(define_insn "mve_vbicq_f<mode>"
2515 [
2516 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2517 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2518 (match_operand:MVE_0 2 "s_register_operand" "w")]
2519 VBICQ_F))
2520 ]
2521 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2522 "vbic %q0, %q1, %q2"
2523 [(set_attr "type" "mve_move")
2524])
2525
2526;;
2527;; [vbicq_n_s, vbicq_n_u])
2528;;
2529(define_insn "mve_vbicq_n_<supf><mode>"
2530 [
2531 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2532 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2533 (match_operand:SI 2 "immediate_operand" "i")]
2534 VBICQ_N))
2535 ]
2536 "TARGET_HAVE_MVE"
2537 "vbic.i%#<V_sz_elem> %q0, %2"
2538 [(set_attr "type" "mve_move")
2539])
2540
2541;;
2542;; [vcaddq_rot270_f])
2543;;
2544(define_insn "mve_vcaddq_rot270_f<mode>"
2545 [
2546 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2547 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2548 (match_operand:MVE_0 2 "s_register_operand" "w")]
2549 VCADDQ_ROT270_F))
2550 ]
2551 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2552 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2553 [(set_attr "type" "mve_move")
2554])
2555
2556;;
2557;; [vcaddq_rot90_f])
2558;;
2559(define_insn "mve_vcaddq_rot90_f<mode>"
2560 [
2561 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2562 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2563 (match_operand:MVE_0 2 "s_register_operand" "w")]
2564 VCADDQ_ROT90_F))
2565 ]
2566 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2567 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2568 [(set_attr "type" "mve_move")
2569])
2570
2571;;
2572;; [vcmpeqq_f])
2573;;
2574(define_insn "mve_vcmpeqq_f<mode>"
2575 [
2576 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2577 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2578 (match_operand:MVE_0 2 "s_register_operand" "w")]
2579 VCMPEQQ_F))
2580 ]
2581 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2582 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2583 [(set_attr "type" "mve_move")
2584])
2585
2586;;
2587;; [vcmpeqq_n_f])
2588;;
2589(define_insn "mve_vcmpeqq_n_f<mode>"
2590 [
2591 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2592 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2593 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2594 VCMPEQQ_N_F))
2595 ]
2596 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2597 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2598 [(set_attr "type" "mve_move")
2599])
2600
2601;;
2602;; [vcmpgeq_f])
2603;;
2604(define_insn "mve_vcmpgeq_f<mode>"
2605 [
2606 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2607 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2608 (match_operand:MVE_0 2 "s_register_operand" "w")]
2609 VCMPGEQ_F))
2610 ]
2611 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2612 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2613 [(set_attr "type" "mve_move")
2614])
2615
2616;;
2617;; [vcmpgeq_n_f])
2618;;
2619(define_insn "mve_vcmpgeq_n_f<mode>"
2620 [
2621 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2622 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2623 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2624 VCMPGEQ_N_F))
2625 ]
2626 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2627 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2628 [(set_attr "type" "mve_move")
2629])
2630
2631;;
2632;; [vcmpgtq_f])
2633;;
2634(define_insn "mve_vcmpgtq_f<mode>"
2635 [
2636 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2637 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2638 (match_operand:MVE_0 2 "s_register_operand" "w")]
2639 VCMPGTQ_F))
2640 ]
2641 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2642 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2643 [(set_attr "type" "mve_move")
2644])
2645
2646;;
2647;; [vcmpgtq_n_f])
2648;;
2649(define_insn "mve_vcmpgtq_n_f<mode>"
2650 [
2651 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2652 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2653 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2654 VCMPGTQ_N_F))
2655 ]
2656 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2657 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2658 [(set_attr "type" "mve_move")
2659])
2660
2661;;
2662;; [vcmpleq_f])
2663;;
2664(define_insn "mve_vcmpleq_f<mode>"
2665 [
2666 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2667 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2668 (match_operand:MVE_0 2 "s_register_operand" "w")]
2669 VCMPLEQ_F))
2670 ]
2671 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2672 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2673 [(set_attr "type" "mve_move")
2674])
2675
2676;;
2677;; [vcmpleq_n_f])
2678;;
2679(define_insn "mve_vcmpleq_n_f<mode>"
2680 [
2681 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2682 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2683 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2684 VCMPLEQ_N_F))
2685 ]
2686 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2687 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2688 [(set_attr "type" "mve_move")
2689])
2690
2691;;
2692;; [vcmpltq_f])
2693;;
2694(define_insn "mve_vcmpltq_f<mode>"
2695 [
2696 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2697 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2698 (match_operand:MVE_0 2 "s_register_operand" "w")]
2699 VCMPLTQ_F))
2700 ]
2701 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2702 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2703 [(set_attr "type" "mve_move")
2704])
2705
2706;;
2707;; [vcmpltq_n_f])
2708;;
2709(define_insn "mve_vcmpltq_n_f<mode>"
2710 [
2711 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2712 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2713 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2714 VCMPLTQ_N_F))
2715 ]
2716 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2717 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2718 [(set_attr "type" "mve_move")
2719])
2720
2721;;
2722;; [vcmpneq_f])
2723;;
2724(define_insn "mve_vcmpneq_f<mode>"
2725 [
2726 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2727 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2728 (match_operand:MVE_0 2 "s_register_operand" "w")]
2729 VCMPNEQ_F))
2730 ]
2731 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2732 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2733 [(set_attr "type" "mve_move")
2734])
2735
2736;;
2737;; [vcmpneq_n_f])
2738;;
2739(define_insn "mve_vcmpneq_n_f<mode>"
2740 [
2741 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2742 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2743 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2744 VCMPNEQ_N_F))
2745 ]
2746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2747 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2748 [(set_attr "type" "mve_move")
2749])
2750
2751;;
2752;; [vcmulq_f])
2753;;
2754(define_insn "mve_vcmulq_f<mode>"
2755 [
2756 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2757 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2758 (match_operand:MVE_0 2 "s_register_operand" "w")]
2759 VCMULQ_F))
2760 ]
2761 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2762 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2763 [(set_attr "type" "mve_move")
2764])
2765
2766;;
2767;; [vcmulq_rot180_f])
2768;;
2769(define_insn "mve_vcmulq_rot180_f<mode>"
2770 [
2771 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2772 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2773 (match_operand:MVE_0 2 "s_register_operand" "w")]
2774 VCMULQ_ROT180_F))
2775 ]
2776 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2777 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2778 [(set_attr "type" "mve_move")
2779])
2780
2781;;
2782;; [vcmulq_rot270_f])
2783;;
2784(define_insn "mve_vcmulq_rot270_f<mode>"
2785 [
2786 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2787 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2788 (match_operand:MVE_0 2 "s_register_operand" "w")]
2789 VCMULQ_ROT270_F))
2790 ]
2791 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2792 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2793 [(set_attr "type" "mve_move")
2794])
2795
2796;;
2797;; [vcmulq_rot90_f])
2798;;
2799(define_insn "mve_vcmulq_rot90_f<mode>"
2800 [
2801 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2802 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2803 (match_operand:MVE_0 2 "s_register_operand" "w")]
2804 VCMULQ_ROT90_F))
2805 ]
2806 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2807 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2808 [(set_attr "type" "mve_move")
2809])
2810
2811;;
2812;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2813;;
2814(define_insn "mve_vctp<mode1>q_mhi"
2815 [
2816 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2817 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2818 (match_operand:HI 2 "vpr_register_operand" "Up")]
2819 VCTPQ_M))
2820 ]
2821 "TARGET_HAVE_MVE"
2822 "vpst\;vctpt.<mode1> %1"
2823 [(set_attr "type" "mve_move")
2824 (set_attr "length""8")])
2825
2826;;
2827;; [vcvtbq_f16_f32])
2828;;
2829(define_insn "mve_vcvtbq_f16_f32v8hf"
2830 [
2831 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2832 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2833 (match_operand:V4SF 2 "s_register_operand" "w")]
2834 VCVTBQ_F16_F32))
2835 ]
2836 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2837 "vcvtb.f16.f32 %q0, %q2"
2838 [(set_attr "type" "mve_move")
2839])
2840
2841;;
2842;; [vcvttq_f16_f32])
2843;;
2844(define_insn "mve_vcvttq_f16_f32v8hf"
2845 [
2846 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2847 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2848 (match_operand:V4SF 2 "s_register_operand" "w")]
2849 VCVTTQ_F16_F32))
2850 ]
2851 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2852 "vcvtt.f16.f32 %q0, %q2"
2853 [(set_attr "type" "mve_move")
2854])
2855
2856;;
2857;; [veorq_f])
2858;;
2859(define_insn "mve_veorq_f<mode>"
2860 [
2861 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2862 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2863 (match_operand:MVE_0 2 "s_register_operand" "w")]
2864 VEORQ_F))
2865 ]
2866 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2867 "veor %q0, %q1, %q2"
2868 [(set_attr "type" "mve_move")
2869])
2870
2871;;
2872;; [vmaxnmaq_f])
2873;;
2874(define_insn "mve_vmaxnmaq_f<mode>"
2875 [
2876 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2877 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2878 (match_operand:MVE_0 2 "s_register_operand" "w")]
2879 VMAXNMAQ_F))
2880 ]
2881 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2882 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2883 [(set_attr "type" "mve_move")
2884])
2885
2886;;
2887;; [vmaxnmavq_f])
2888;;
2889(define_insn "mve_vmaxnmavq_f<mode>"
2890 [
2891 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2892 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2893 (match_operand:MVE_0 2 "s_register_operand" "w")]
2894 VMAXNMAVQ_F))
2895 ]
2896 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2897 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2898 [(set_attr "type" "mve_move")
2899])
2900
2901;;
2902;; [vmaxnmq_f])
2903;;
2904(define_insn "mve_vmaxnmq_f<mode>"
2905 [
2906 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2907 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2908 (match_operand:MVE_0 2 "s_register_operand" "w")]
2909 VMAXNMQ_F))
2910 ]
2911 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2912 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
2913 [(set_attr "type" "mve_move")
2914])
2915
2916;;
2917;; [vmaxnmvq_f])
2918;;
2919(define_insn "mve_vmaxnmvq_f<mode>"
2920 [
2921 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2922 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2923 (match_operand:MVE_0 2 "s_register_operand" "w")]
2924 VMAXNMVQ_F))
2925 ]
2926 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2927 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
2928 [(set_attr "type" "mve_move")
2929])
2930
2931;;
2932;; [vminnmaq_f])
2933;;
2934(define_insn "mve_vminnmaq_f<mode>"
2935 [
2936 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2937 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2938 (match_operand:MVE_0 2 "s_register_operand" "w")]
2939 VMINNMAQ_F))
2940 ]
2941 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2942 "vminnma.f%#<V_sz_elem> %q0, %q2"
2943 [(set_attr "type" "mve_move")
2944])
2945
2946;;
2947;; [vminnmavq_f])
2948;;
2949(define_insn "mve_vminnmavq_f<mode>"
2950 [
2951 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2952 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2953 (match_operand:MVE_0 2 "s_register_operand" "w")]
2954 VMINNMAVQ_F))
2955 ]
2956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2957 "vminnmav.f%#<V_sz_elem> %0, %q2"
2958 [(set_attr "type" "mve_move")
2959])
2960
2961;;
2962;; [vminnmq_f])
2963;;
2964(define_insn "mve_vminnmq_f<mode>"
2965 [
2966 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2967 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2968 (match_operand:MVE_0 2 "s_register_operand" "w")]
2969 VMINNMQ_F))
2970 ]
2971 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2972 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
2973 [(set_attr "type" "mve_move")
2974])
2975
2976;;
2977;; [vminnmvq_f])
2978;;
2979(define_insn "mve_vminnmvq_f<mode>"
2980 [
2981 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2982 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2983 (match_operand:MVE_0 2 "s_register_operand" "w")]
2984 VMINNMVQ_F))
2985 ]
2986 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2987 "vminnmv.f%#<V_sz_elem> %0, %q2"
2988 [(set_attr "type" "mve_move")
2989])
2990
2991;;
2992;; [vmlaldavq_u, vmlaldavq_s])
2993;;
2994(define_insn "mve_vmlaldavq_<supf><mode>"
2995 [
2996 (set (match_operand:DI 0 "s_register_operand" "=r")
2997 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2998 (match_operand:MVE_5 2 "s_register_operand" "w")]
2999 VMLALDAVQ))
3000 ]
3001 "TARGET_HAVE_MVE"
3002 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3003 [(set_attr "type" "mve_move")
3004])
3005
3006;;
3007;; [vmlaldavxq_s])
3008;;
3009(define_insn "mve_vmlaldavxq_s<mode>"
3010 [
3011 (set (match_operand:DI 0 "s_register_operand" "=r")
3012 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3013 (match_operand:MVE_5 2 "s_register_operand" "w")]
3014 VMLALDAVXQ_S))
3015 ]
3016 "TARGET_HAVE_MVE"
3017 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3018 [(set_attr "type" "mve_move")
3019])
3020
3021;;
3022;; [vmlsldavq_s])
3023;;
3024(define_insn "mve_vmlsldavq_s<mode>"
3025 [
3026 (set (match_operand:DI 0 "s_register_operand" "=r")
3027 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3028 (match_operand:MVE_5 2 "s_register_operand" "w")]
3029 VMLSLDAVQ_S))
3030 ]
3031 "TARGET_HAVE_MVE"
3032 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3033 [(set_attr "type" "mve_move")
3034])
3035
3036;;
3037;; [vmlsldavxq_s])
3038;;
3039(define_insn "mve_vmlsldavxq_s<mode>"
3040 [
3041 (set (match_operand:DI 0 "s_register_operand" "=r")
3042 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3043 (match_operand:MVE_5 2 "s_register_operand" "w")]
3044 VMLSLDAVXQ_S))
3045 ]
3046 "TARGET_HAVE_MVE"
3047 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3048 [(set_attr "type" "mve_move")
3049])
3050
3051;;
3052;; [vmovnbq_u, vmovnbq_s])
3053;;
3054(define_insn "mve_vmovnbq_<supf><mode>"
3055 [
3056 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3057 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3058 (match_operand:MVE_5 2 "s_register_operand" "w")]
3059 VMOVNBQ))
3060 ]
3061 "TARGET_HAVE_MVE"
3062 "vmovnb.i%#<V_sz_elem> %q0, %q2"
3063 [(set_attr "type" "mve_move")
3064])
3065
3066;;
3067;; [vmovntq_s, vmovntq_u])
3068;;
3069(define_insn "mve_vmovntq_<supf><mode>"
3070 [
3071 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3072 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3073 (match_operand:MVE_5 2 "s_register_operand" "w")]
3074 VMOVNTQ))
3075 ]
3076 "TARGET_HAVE_MVE"
3077 "vmovnt.i%#<V_sz_elem> %q0, %q2"
3078 [(set_attr "type" "mve_move")
3079])
3080
3081;;
3082;; [vmulq_f])
3083;;
3084(define_insn "mve_vmulq_f<mode>"
3085 [
3086 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3087 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3088 (match_operand:MVE_0 2 "s_register_operand" "w")]
3089 VMULQ_F))
3090 ]
3091 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3092 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
3093 [(set_attr "type" "mve_move")
3094])
3095
3096;;
3097;; [vmulq_n_f])
3098;;
3099(define_insn "mve_vmulq_n_f<mode>"
3100 [
3101 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3102 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3103 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3104 VMULQ_N_F))
3105 ]
3106 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3107 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
3108 [(set_attr "type" "mve_move")
3109])
3110
3111;;
3112;; [vornq_f])
3113;;
3114(define_insn "mve_vornq_f<mode>"
3115 [
3116 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3117 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3118 (match_operand:MVE_0 2 "s_register_operand" "w")]
3119 VORNQ_F))
3120 ]
3121 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3122 "vorn %q0, %q1, %q2"
3123 [(set_attr "type" "mve_move")
3124])
3125
3126;;
3127;; [vorrq_f])
3128;;
3129(define_insn "mve_vorrq_f<mode>"
3130 [
3131 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3132 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3133 (match_operand:MVE_0 2 "s_register_operand" "w")]
3134 VORRQ_F))
3135 ]
3136 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3137 "vorr %q0, %q1, %q2"
3138 [(set_attr "type" "mve_move")
3139])
3140
3141;;
3142;; [vorrq_n_u, vorrq_n_s])
3143;;
3144(define_insn "mve_vorrq_n_<supf><mode>"
3145 [
3146 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3147 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3148 (match_operand:SI 2 "immediate_operand" "i")]
3149 VORRQ_N))
3150 ]
3151 "TARGET_HAVE_MVE"
3152 "vorr.i%#<V_sz_elem> %q0, %2"
3153 [(set_attr "type" "mve_move")
3154])
3155
3156;;
3157;; [vqdmullbq_n_s])
3158;;
3159(define_insn "mve_vqdmullbq_n_s<mode>"
3160 [
3161 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3162 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3163 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3164 VQDMULLBQ_N_S))
3165 ]
3166 "TARGET_HAVE_MVE"
3167 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
3168 [(set_attr "type" "mve_move")
3169])
3170
3171;;
3172;; [vqdmullbq_s])
3173;;
3174(define_insn "mve_vqdmullbq_s<mode>"
3175 [
3176 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3177 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3178 (match_operand:MVE_5 2 "s_register_operand" "w")]
3179 VQDMULLBQ_S))
3180 ]
3181 "TARGET_HAVE_MVE"
3182 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
3183 [(set_attr "type" "mve_move")
3184])
3185
3186;;
3187;; [vqdmulltq_n_s])
3188;;
3189(define_insn "mve_vqdmulltq_n_s<mode>"
3190 [
3191 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3192 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3193 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3194 VQDMULLTQ_N_S))
3195 ]
3196 "TARGET_HAVE_MVE"
3197 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
3198 [(set_attr "type" "mve_move")
3199])
3200
3201;;
3202;; [vqdmulltq_s])
3203;;
3204(define_insn "mve_vqdmulltq_s<mode>"
3205 [
3206 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3207 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3208 (match_operand:MVE_5 2 "s_register_operand" "w")]
3209 VQDMULLTQ_S))
3210 ]
3211 "TARGET_HAVE_MVE"
3212 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
3213 [(set_attr "type" "mve_move")
3214])
3215
3216;;
3217;; [vqmovnbq_u, vqmovnbq_s])
3218;;
3219(define_insn "mve_vqmovnbq_<supf><mode>"
3220 [
3221 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3222 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3223 (match_operand:MVE_5 2 "s_register_operand" "w")]
3224 VQMOVNBQ))
3225 ]
3226 "TARGET_HAVE_MVE"
3227 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
3228 [(set_attr "type" "mve_move")
3229])
3230
3231;;
3232;; [vqmovntq_u, vqmovntq_s])
3233;;
3234(define_insn "mve_vqmovntq_<supf><mode>"
3235 [
3236 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3237 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3238 (match_operand:MVE_5 2 "s_register_operand" "w")]
3239 VQMOVNTQ))
3240 ]
3241 "TARGET_HAVE_MVE"
3242 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
3243 [(set_attr "type" "mve_move")
3244])
3245
3246;;
3247;; [vqmovunbq_s])
3248;;
3249(define_insn "mve_vqmovunbq_s<mode>"
3250 [
3251 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3252 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3253 (match_operand:MVE_5 2 "s_register_operand" "w")]
3254 VQMOVUNBQ_S))
3255 ]
3256 "TARGET_HAVE_MVE"
3257 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
3258 [(set_attr "type" "mve_move")
3259])
3260
3261;;
3262;; [vqmovuntq_s])
3263;;
3264(define_insn "mve_vqmovuntq_s<mode>"
3265 [
3266 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3267 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3268 (match_operand:MVE_5 2 "s_register_operand" "w")]
3269 VQMOVUNTQ_S))
3270 ]
3271 "TARGET_HAVE_MVE"
3272 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
3273 [(set_attr "type" "mve_move")
3274])
3275
3276;;
3277;; [vrmlaldavhxq_s])
3278;;
3279(define_insn "mve_vrmlaldavhxq_sv4si"
3280 [
3281 (set (match_operand:DI 0 "s_register_operand" "=r")
3282 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3283 (match_operand:V4SI 2 "s_register_operand" "w")]
3284 VRMLALDAVHXQ_S))
3285 ]
3286 "TARGET_HAVE_MVE"
3287 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
3288 [(set_attr "type" "mve_move")
3289])
3290
3291;;
3292;; [vrmlsldavhq_s])
3293;;
3294(define_insn "mve_vrmlsldavhq_sv4si"
3295 [
3296 (set (match_operand:DI 0 "s_register_operand" "=r")
3297 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3298 (match_operand:V4SI 2 "s_register_operand" "w")]
3299 VRMLSLDAVHQ_S))
3300 ]
3301 "TARGET_HAVE_MVE"
3302 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
3303 [(set_attr "type" "mve_move")
3304])
3305
3306;;
3307;; [vrmlsldavhxq_s])
3308;;
3309(define_insn "mve_vrmlsldavhxq_sv4si"
3310 [
3311 (set (match_operand:DI 0 "s_register_operand" "=r")
3312 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3313 (match_operand:V4SI 2 "s_register_operand" "w")]
3314 VRMLSLDAVHXQ_S))
3315 ]
3316 "TARGET_HAVE_MVE"
3317 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
3318 [(set_attr "type" "mve_move")
3319])
3320
3321;;
3322;; [vshllbq_n_s, vshllbq_n_u])
3323;;
3324(define_insn "mve_vshllbq_n_<supf><mode>"
3325 [
3326 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3327 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3328 (match_operand:SI 2 "immediate_operand" "i")]
3329 VSHLLBQ_N))
3330 ]
3331 "TARGET_HAVE_MVE"
3332 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3333 [(set_attr "type" "mve_move")
3334])
3335
3336;;
3337;; [vshlltq_n_u, vshlltq_n_s])
3338;;
3339(define_insn "mve_vshlltq_n_<supf><mode>"
3340 [
3341 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3342 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3343 (match_operand:SI 2 "immediate_operand" "i")]
3344 VSHLLTQ_N))
3345 ]
3346 "TARGET_HAVE_MVE"
3347 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3348 [(set_attr "type" "mve_move")
3349])
3350
3351;;
3352;; [vsubq_f])
3353;;
3354(define_insn "mve_vsubq_f<mode>"
3355 [
3356 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3357 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3358 (match_operand:MVE_0 2 "s_register_operand" "w")]
3359 VSUBQ_F))
3360 ]
3361 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3362 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3363 [(set_attr "type" "mve_move")
3364])
3365
3366;;
3367;; [vmulltq_poly_p])
3368;;
3369(define_insn "mve_vmulltq_poly_p<mode>"
3370 [
3371 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3372 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3373 (match_operand:MVE_3 2 "s_register_operand" "w")]
3374 VMULLTQ_POLY_P))
3375 ]
3376 "TARGET_HAVE_MVE"
3377 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3378 [(set_attr "type" "mve_move")
3379])
3380
3381;;
3382;; [vmullbq_poly_p])
3383;;
3384(define_insn "mve_vmullbq_poly_p<mode>"
3385 [
3386 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3387 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3388 (match_operand:MVE_3 2 "s_register_operand" "w")]
3389 VMULLBQ_POLY_P))
3390 ]
3391 "TARGET_HAVE_MVE"
3392 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3393 [(set_attr "type" "mve_move")
3394])
3395
3396;;
3397;; [vrmlaldavhq_u vrmlaldavhq_s])
3398;;
3399(define_insn "mve_vrmlaldavhq_<supf>v4si"
3400 [
3401 (set (match_operand:DI 0 "s_register_operand" "=r")
3402 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3403 (match_operand:V4SI 2 "s_register_operand" "w")]
3404 VRMLALDAVHQ))
3405 ]
3406 "TARGET_HAVE_MVE"
3407 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3408 [(set_attr "type" "mve_move")
3409])
0dad5b33
SP		 3410
3411;;
3412;; [vbicq_m_n_s, vbicq_m_n_u])
3413;;
3414(define_insn "mve_vbicq_m_n_<supf><mode>"
3415 [
3416 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3417 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3418 (match_operand:SI 2 "immediate_operand" "i")
3419 (match_operand:HI 3 "vpr_register_operand" "Up")]
3420 VBICQ_M_N))
3421 ]
3422 "TARGET_HAVE_MVE"
3423 "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
3424 [(set_attr "type" "mve_move")
3425 (set_attr "length""8")])
3426;;
3427;; [vcmpeqq_m_f])
3428;;
3429(define_insn "mve_vcmpeqq_m_f<mode>"
3430 [
3431 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3432 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
3433 (match_operand:MVE_0 2 "s_register_operand" "w")
3434 (match_operand:HI 3 "vpr_register_operand" "Up")]
3435 VCMPEQQ_M_F))
3436 ]
3437 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3438 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
3439 [(set_attr "type" "mve_move")
3440 (set_attr "length""8")])
3441;;
3442;; [vcvtaq_m_u, vcvtaq_m_s])
3443;;
3444(define_insn "mve_vcvtaq_m_<supf><mode>"
3445 [
3446 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3447 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3448 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3449 (match_operand:HI 3 "vpr_register_operand" "Up")]
3450 VCVTAQ_M))
3451 ]
3452 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3453 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3454 [(set_attr "type" "mve_move")
3455 (set_attr "length""8")])
3456;;
3457;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3458;;
3459(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3460 [
3461 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3462 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3463 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3464 (match_operand:HI 3 "vpr_register_operand" "Up")]
3465 VCVTQ_M_TO_F))
3466 ]
3467 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3468 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
3469 [(set_attr "type" "mve_move")
3470 (set_attr "length""8")])
3471;;
3472;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3473;;
3474(define_insn "mve_vqrshrnbq_n_<supf><mode>"
3475 [
3476 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3477 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3478 (match_operand:MVE_5 2 "s_register_operand" "w")
3479 (match_operand:SI 3 "mve_imm_8" "Rb")]
3480 VQRSHRNBQ_N))
3481 ]
3482 "TARGET_HAVE_MVE"
3483 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3484 [(set_attr "type" "mve_move")
3485])
3486;;
3487;; [vqrshrunbq_n_s])
3488;;
3489(define_insn "mve_vqrshrunbq_n_s<mode>"
3490 [
3491 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3492 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3493 (match_operand:MVE_5 2 "s_register_operand" "w")
3494 (match_operand:SI 3 "mve_imm_8" "Rb")]
3495 VQRSHRUNBQ_N_S))
3496 ]
3497 "TARGET_HAVE_MVE"
3498 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3499 [(set_attr "type" "mve_move")
3500])
3501;;
3502;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3503;;
3504(define_insn "mve_vrmlaldavhaq_<supf>v4si"
3505 [
3506 (set (match_operand:DI 0 "s_register_operand" "=r")
3507 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3508 (match_operand:V4SI 2 "s_register_operand" "w")
3509 (match_operand:V4SI 3 "s_register_operand" "w")]
3510 VRMLALDAVHAQ))
3511 ]
3512 "TARGET_HAVE_MVE"
3513 "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3514 [(set_attr "type" "mve_move")
3515])
3516
3517;;
3518;; [vabavq_s, vabavq_u])
3519;;
3520(define_insn "mve_vabavq_<supf><mode>"
3521 [
3522 (set (match_operand:SI 0 "s_register_operand" "=r")
3523 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3524 (match_operand:MVE_2 2 "s_register_operand" "w")
3525 (match_operand:MVE_2 3 "s_register_operand" "w")]
3526 VABAVQ))
3527 ]
3528 "TARGET_HAVE_MVE"
3529 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3530 [(set_attr "type" "mve_move")
3531])
3532
3533;;
3534;; [vshlcq_u vshlcq_s]
3535;;
3536(define_expand "mve_vshlcq_vec_<supf><mode>"
3537 [(match_operand:MVE_2 0 "s_register_operand")
3538 (match_operand:MVE_2 1 "s_register_operand")
3539 (match_operand:SI 2 "s_register_operand")
3540 (match_operand:SI 3 "mve_imm_32")
3541 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3542 "TARGET_HAVE_MVE"
3543{
3544 rtx ignore_wb = gen_reg_rtx (SImode);
3545 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
8165795c 3546 operands[2], operands[3]));
0dad5b33
SP		 3547 DONE;
3548})
3549
3550(define_expand "mve_vshlcq_carry_<supf><mode>"
3551 [(match_operand:SI 0 "s_register_operand")
3552 (match_operand:MVE_2 1 "s_register_operand")
3553 (match_operand:SI 2 "s_register_operand")
3554 (match_operand:SI 3 "mve_imm_32")
3555 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3556 "TARGET_HAVE_MVE"
3557{
3558 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3559 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3560 operands[2], operands[3]));
3561 DONE;
3562})
3563
3564(define_insn "mve_vshlcq_<supf><mode>"
3565 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3566 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3567 (match_operand:SI 3 "s_register_operand" "1")
3568 (match_operand:SI 4 "mve_imm_32" "Rf")]
3569 VSHLCQ))
3570 (set (match_operand:SI 1 "s_register_operand" "=r")
3571 (unspec:SI [(match_dup 2)
3572 (match_dup 3)
3573 (match_dup 4)]
3574 VSHLCQ))]
3575 "TARGET_HAVE_MVE"
3576 "vshlc %q0, %1, %4")
8165795c
SP		 3577
3578;;
3579;; [vabsq_m_s])
3580;;
3581(define_insn "mve_vabsq_m_s<mode>"
3582 [
3583 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3584 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3585 (match_operand:MVE_2 2 "s_register_operand" "w")
3586 (match_operand:HI 3 "vpr_register_operand" "Up")]
3587 VABSQ_M_S))
3588 ]
3589 "TARGET_HAVE_MVE"
3590 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
3591 [(set_attr "type" "mve_move")
3592 (set_attr "length""8")])
3593
3594;;
3595;; [vaddvaq_p_u, vaddvaq_p_s])
3596;;
3597(define_insn "mve_vaddvaq_p_<supf><mode>"
3598 [
3599 (set (match_operand:SI 0 "s_register_operand" "=e")
3600 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3601 (match_operand:MVE_2 2 "s_register_operand" "w")
3602 (match_operand:HI 3 "vpr_register_operand" "Up")]
3603 VADDVAQ_P))
3604 ]
3605 "TARGET_HAVE_MVE"
3606 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2"
3607 [(set_attr "type" "mve_move")
3608 (set_attr "length""8")])
3609
3610;;
3611;; [vclsq_m_s])
3612;;
3613(define_insn "mve_vclsq_m_s<mode>"
3614 [
3615 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3616 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3617 (match_operand:MVE_2 2 "s_register_operand" "w")
3618 (match_operand:HI 3 "vpr_register_operand" "Up")]
3619 VCLSQ_M_S))
3620 ]
3621 "TARGET_HAVE_MVE"
3622 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
3623 [(set_attr "type" "mve_move")
3624 (set_attr "length""8")])
3625
3626;;
3627;; [vclzq_m_s, vclzq_m_u])
3628;;
3629(define_insn "mve_vclzq_m_<supf><mode>"
3630 [
3631 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3632 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3633 (match_operand:MVE_2 2 "s_register_operand" "w")
3634 (match_operand:HI 3 "vpr_register_operand" "Up")]
3635 VCLZQ_M))
3636 ]
3637 "TARGET_HAVE_MVE"
3638 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
3639 [(set_attr "type" "mve_move")
3640 (set_attr "length""8")])
3641
3642;;
3643;; [vcmpcsq_m_n_u])
3644;;
3645(define_insn "mve_vcmpcsq_m_n_u<mode>"
3646 [
3647 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3648 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3649 (match_operand:<V_elem> 2 "s_register_operand" "r")
3650 (match_operand:HI 3 "vpr_register_operand" "Up")]
3651 VCMPCSQ_M_N_U))
3652 ]
3653 "TARGET_HAVE_MVE"
3654 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2"
3655 [(set_attr "type" "mve_move")
3656 (set_attr "length""8")])
3657
3658;;
3659;; [vcmpcsq_m_u])
3660;;
3661(define_insn "mve_vcmpcsq_m_u<mode>"
3662 [
3663 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3664 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3665 (match_operand:MVE_2 2 "s_register_operand" "w")
3666 (match_operand:HI 3 "vpr_register_operand" "Up")]
3667 VCMPCSQ_M_U))
3668 ]
3669 "TARGET_HAVE_MVE"
3670 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2"
3671 [(set_attr "type" "mve_move")
3672 (set_attr "length""8")])
3673
3674;;
3675;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3676;;
3677(define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3678 [
3679 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3680 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3681 (match_operand:<V_elem> 2 "s_register_operand" "r")
3682 (match_operand:HI 3 "vpr_register_operand" "Up")]
3683 VCMPEQQ_M_N))
3684 ]
3685 "TARGET_HAVE_MVE"
3686 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2"
3687 [(set_attr "type" "mve_move")
3688 (set_attr "length""8")])
3689
3690;;
3691;; [vcmpeqq_m_u, vcmpeqq_m_s])
3692;;
3693(define_insn "mve_vcmpeqq_m_<supf><mode>"
3694 [
3695 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3696 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3697 (match_operand:MVE_2 2 "s_register_operand" "w")
3698 (match_operand:HI 3 "vpr_register_operand" "Up")]
3699 VCMPEQQ_M))
3700 ]
3701 "TARGET_HAVE_MVE"
3702 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2"
3703 [(set_attr "type" "mve_move")
3704 (set_attr "length""8")])
3705
3706;;
3707;; [vcmpgeq_m_n_s])
3708;;
3709(define_insn "mve_vcmpgeq_m_n_s<mode>"
3710 [
3711 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3712 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3713 (match_operand:<V_elem> 2 "s_register_operand" "r")
3714 (match_operand:HI 3 "vpr_register_operand" "Up")]
3715 VCMPGEQ_M_N_S))
3716 ]
3717 "TARGET_HAVE_MVE"
3718 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2"
3719 [(set_attr "type" "mve_move")
3720 (set_attr "length""8")])
3721
3722;;
3723;; [vcmpgeq_m_s])
3724;;
3725(define_insn "mve_vcmpgeq_m_s<mode>"
3726 [
3727 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3728 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3729 (match_operand:MVE_2 2 "s_register_operand" "w")
3730 (match_operand:HI 3 "vpr_register_operand" "Up")]
3731 VCMPGEQ_M_S))
3732 ]
3733 "TARGET_HAVE_MVE"
3734 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2"
3735 [(set_attr "type" "mve_move")
3736 (set_attr "length""8")])
3737
3738;;
3739;; [vcmpgtq_m_n_s])
3740;;
3741(define_insn "mve_vcmpgtq_m_n_s<mode>"
3742 [
3743 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3744 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3745 (match_operand:<V_elem> 2 "s_register_operand" "r")
3746 (match_operand:HI 3 "vpr_register_operand" "Up")]
3747 VCMPGTQ_M_N_S))
3748 ]
3749 "TARGET_HAVE_MVE"
3750 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2"
3751 [(set_attr "type" "mve_move")
3752 (set_attr "length""8")])
3753
3754;;
3755;; [vcmpgtq_m_s])
3756;;
3757(define_insn "mve_vcmpgtq_m_s<mode>"
3758 [
3759 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3760 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3761 (match_operand:MVE_2 2 "s_register_operand" "w")
3762 (match_operand:HI 3 "vpr_register_operand" "Up")]
3763 VCMPGTQ_M_S))
3764 ]
3765 "TARGET_HAVE_MVE"
3766 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2"
3767 [(set_attr "type" "mve_move")
3768 (set_attr "length""8")])
3769
3770;;
3771;; [vcmphiq_m_n_u])
3772;;
3773(define_insn "mve_vcmphiq_m_n_u<mode>"
3774 [
3775 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3776 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3777 (match_operand:<V_elem> 2 "s_register_operand" "r")
3778 (match_operand:HI 3 "vpr_register_operand" "Up")]
3779 VCMPHIQ_M_N_U))
3780 ]
3781 "TARGET_HAVE_MVE"
3782 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2"
3783 [(set_attr "type" "mve_move")
3784 (set_attr "length""8")])
3785
3786;;
3787;; [vcmphiq_m_u])
3788;;
3789(define_insn "mve_vcmphiq_m_u<mode>"
3790 [
3791 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3792 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3793 (match_operand:MVE_2 2 "s_register_operand" "w")
3794 (match_operand:HI 3 "vpr_register_operand" "Up")]
3795 VCMPHIQ_M_U))
3796 ]
3797 "TARGET_HAVE_MVE"
3798 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2"
3799 [(set_attr "type" "mve_move")
3800 (set_attr "length""8")])
3801
3802;;
3803;; [vcmpleq_m_n_s])
3804;;
3805(define_insn "mve_vcmpleq_m_n_s<mode>"
3806 [
3807 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3808 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3809 (match_operand:<V_elem> 2 "s_register_operand" "r")
3810 (match_operand:HI 3 "vpr_register_operand" "Up")]
3811 VCMPLEQ_M_N_S))
3812 ]
3813 "TARGET_HAVE_MVE"
3814 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2"
3815 [(set_attr "type" "mve_move")
3816 (set_attr "length""8")])
3817
3818;;
3819;; [vcmpleq_m_s])
3820;;
3821(define_insn "mve_vcmpleq_m_s<mode>"
3822 [
3823 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3824 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3825 (match_operand:MVE_2 2 "s_register_operand" "w")
3826 (match_operand:HI 3 "vpr_register_operand" "Up")]
3827 VCMPLEQ_M_S))
3828 ]
3829 "TARGET_HAVE_MVE"
3830 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2"
3831 [(set_attr "type" "mve_move")
3832 (set_attr "length""8")])
3833
3834;;
3835;; [vcmpltq_m_n_s])
3836;;
3837(define_insn "mve_vcmpltq_m_n_s<mode>"
3838 [
3839 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3840 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3841 (match_operand:<V_elem> 2 "s_register_operand" "r")
3842 (match_operand:HI 3 "vpr_register_operand" "Up")]
3843 VCMPLTQ_M_N_S))
3844 ]
3845 "TARGET_HAVE_MVE"
3846 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2"
3847 [(set_attr "type" "mve_move")
3848 (set_attr "length""8")])
3849
3850;;
3851;; [vcmpltq_m_s])
3852;;
3853(define_insn "mve_vcmpltq_m_s<mode>"
3854 [
3855 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3856 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3857 (match_operand:MVE_2 2 "s_register_operand" "w")
3858 (match_operand:HI 3 "vpr_register_operand" "Up")]
3859 VCMPLTQ_M_S))
3860 ]
3861 "TARGET_HAVE_MVE"
3862 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2"
3863 [(set_attr "type" "mve_move")
3864 (set_attr "length""8")])
3865
3866;;
3867;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3868;;
3869(define_insn "mve_vcmpneq_m_n_<supf><mode>"
3870 [
3871 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3872 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3873 (match_operand:<V_elem> 2 "s_register_operand" "r")
3874 (match_operand:HI 3 "vpr_register_operand" "Up")]
3875 VCMPNEQ_M_N))
3876 ]
3877 "TARGET_HAVE_MVE"
3878 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2"
3879 [(set_attr "type" "mve_move")
3880 (set_attr "length""8")])
3881
3882;;
3883;; [vcmpneq_m_s, vcmpneq_m_u])
3884;;
3885(define_insn "mve_vcmpneq_m_<supf><mode>"
3886 [
3887 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3888 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3889 (match_operand:MVE_2 2 "s_register_operand" "w")
3890 (match_operand:HI 3 "vpr_register_operand" "Up")]
3891 VCMPNEQ_M))
3892 ]
3893 "TARGET_HAVE_MVE"
3894 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2"
3895 [(set_attr "type" "mve_move")
3896 (set_attr "length""8")])
3897
3898;;
3899;; [vdupq_m_n_s, vdupq_m_n_u])
3900;;
3901(define_insn "mve_vdupq_m_n_<supf><mode>"
3902 [
3903 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3904 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3905 (match_operand:<V_elem> 2 "s_register_operand" "r")
3906 (match_operand:HI 3 "vpr_register_operand" "Up")]
3907 VDUPQ_M_N))
3908 ]
3909 "TARGET_HAVE_MVE"
3910 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
3911 [(set_attr "type" "mve_move")
3912 (set_attr "length""8")])
3913
3914;;
3915;; [vmaxaq_m_s])
3916;;
3917(define_insn "mve_vmaxaq_m_s<mode>"
3918 [
3919 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3920 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3921 (match_operand:MVE_2 2 "s_register_operand" "w")
3922 (match_operand:HI 3 "vpr_register_operand" "Up")]
3923 VMAXAQ_M_S))
3924 ]
3925 "TARGET_HAVE_MVE"
3926 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2"
3927 [(set_attr "type" "mve_move")
3928 (set_attr "length""8")])
3929
3930;;
3931;; [vmaxavq_p_s])
3932;;
3933(define_insn "mve_vmaxavq_p_s<mode>"
3934 [
3935 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3936 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3937 (match_operand:MVE_2 2 "s_register_operand" "w")
3938 (match_operand:HI 3 "vpr_register_operand" "Up")]
3939 VMAXAVQ_P_S))
3940 ]
3941 "TARGET_HAVE_MVE"
3942 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
3943 [(set_attr "type" "mve_move")
3944 (set_attr "length""8")])
3945
3946;;
3947;; [vmaxvq_p_u, vmaxvq_p_s])
3948;;
3949(define_insn "mve_vmaxvq_p_<supf><mode>"
3950 [
3951 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3952 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3953 (match_operand:MVE_2 2 "s_register_operand" "w")
3954 (match_operand:HI 3 "vpr_register_operand" "Up")]
3955 VMAXVQ_P))
3956 ]
3957 "TARGET_HAVE_MVE"
3958 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
3959 [(set_attr "type" "mve_move")
3960 (set_attr "length""8")])
3961
3962;;
3963;; [vminaq_m_s])
3964;;
3965(define_insn "mve_vminaq_m_s<mode>"
3966 [
3967 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3968 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3969 (match_operand:MVE_2 2 "s_register_operand" "w")
3970 (match_operand:HI 3 "vpr_register_operand" "Up")]
3971 VMINAQ_M_S))
3972 ]
3973 "TARGET_HAVE_MVE"
3974 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2"
3975 [(set_attr "type" "mve_move")
3976 (set_attr "length""8")])
3977
3978;;
3979;; [vminavq_p_s])
3980;;
3981(define_insn "mve_vminavq_p_s<mode>"
3982 [
3983 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3984 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3985 (match_operand:MVE_2 2 "s_register_operand" "w")
3986 (match_operand:HI 3 "vpr_register_operand" "Up")]
3987 VMINAVQ_P_S))
3988 ]
3989 "TARGET_HAVE_MVE"
3990 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
3991 [(set_attr "type" "mve_move")
3992 (set_attr "length""8")])
3993
3994;;
3995;; [vminvq_p_s, vminvq_p_u])
3996;;
3997(define_insn "mve_vminvq_p_<supf><mode>"
3998 [
3999 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4000 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4001 (match_operand:MVE_2 2 "s_register_operand" "w")
4002 (match_operand:HI 3 "vpr_register_operand" "Up")]
4003 VMINVQ_P))
4004 ]
4005 "TARGET_HAVE_MVE"
4006 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
4007 [(set_attr "type" "mve_move")
4008 (set_attr "length""8")])
4009
4010;;
4011;; [vmladavaq_u, vmladavaq_s])
4012;;
4013(define_insn "mve_vmladavaq_<supf><mode>"
4014 [
4015 (set (match_operand:SI 0 "s_register_operand" "=e")
4016 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4017 (match_operand:MVE_2 2 "s_register_operand" "w")
4018 (match_operand:MVE_2 3 "s_register_operand" "w")]
4019 VMLADAVAQ))
4020 ]
4021 "TARGET_HAVE_MVE"
4022 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
4023 [(set_attr "type" "mve_move")
4024])
4025
4026;;
4027;; [vmladavq_p_u, vmladavq_p_s])
4028;;
4029(define_insn "mve_vmladavq_p_<supf><mode>"
4030 [
4031 (set (match_operand:SI 0 "s_register_operand" "=e")
4032 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4033 (match_operand:MVE_2 2 "s_register_operand" "w")
4034 (match_operand:HI 3 "vpr_register_operand" "Up")]
4035 VMLADAVQ_P))
4036 ]
4037 "TARGET_HAVE_MVE"
4038 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
4039 [(set_attr "type" "mve_move")
4040 (set_attr "length""8")])
4041
4042;;
4043;; [vmladavxq_p_s])
4044;;
4045(define_insn "mve_vmladavxq_p_s<mode>"
4046 [
4047 (set (match_operand:SI 0 "s_register_operand" "=e")
4048 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4049 (match_operand:MVE_2 2 "s_register_operand" "w")
4050 (match_operand:HI 3 "vpr_register_operand" "Up")]
4051 VMLADAVXQ_P_S))
4052 ]
4053 "TARGET_HAVE_MVE"
4054 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
4055 [(set_attr "type" "mve_move")
4056 (set_attr "length""8")])
4057
4058;;
4059;; [vmlaq_n_u, vmlaq_n_s])
4060;;
4061(define_insn "mve_vmlaq_n_<supf><mode>"
4062 [
4063 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4064 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4065 (match_operand:MVE_2 2 "s_register_operand" "w")
4066 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4067 VMLAQ_N))
4068 ]
4069 "TARGET_HAVE_MVE"
4070 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
4071 [(set_attr "type" "mve_move")
4072])
4073
4074;;
4075;; [vmlasq_n_u, vmlasq_n_s])
4076;;
4077(define_insn "mve_vmlasq_n_<supf><mode>"
4078 [
4079 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4080 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4081 (match_operand:MVE_2 2 "s_register_operand" "w")
4082 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4083 VMLASQ_N))
4084 ]
4085 "TARGET_HAVE_MVE"
4086 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3"
4087 [(set_attr "type" "mve_move")
4088])
4089
4090;;
4091;; [vmlsdavq_p_s])
4092;;
4093(define_insn "mve_vmlsdavq_p_s<mode>"
4094 [
4095 (set (match_operand:SI 0 "s_register_operand" "=e")
4096 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4097 (match_operand:MVE_2 2 "s_register_operand" "w")
4098 (match_operand:HI 3 "vpr_register_operand" "Up")]
4099 VMLSDAVQ_P_S))
4100 ]
4101 "TARGET_HAVE_MVE"
4102 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
4103 [(set_attr "type" "mve_move")
4104 (set_attr "length""8")])
4105
4106;;
4107;; [vmlsdavxq_p_s])
4108;;
4109(define_insn "mve_vmlsdavxq_p_s<mode>"
4110 [
4111 (set (match_operand:SI 0 "s_register_operand" "=e")
4112 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4113 (match_operand:MVE_2 2 "s_register_operand" "w")
4114 (match_operand:HI 3 "vpr_register_operand" "Up")]
4115 VMLSDAVXQ_P_S))
4116 ]
4117 "TARGET_HAVE_MVE"
4118 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
4119 [(set_attr "type" "mve_move")
4120 (set_attr "length""8")])
4121
4122;;
4123;; [vmvnq_m_s, vmvnq_m_u])
4124;;
4125(define_insn "mve_vmvnq_m_<supf><mode>"
4126 [
4127 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4128 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4129 (match_operand:MVE_2 2 "s_register_operand" "w")
4130 (match_operand:HI 3 "vpr_register_operand" "Up")]
4131 VMVNQ_M))
4132 ]
4133 "TARGET_HAVE_MVE"
4134 "vpst\;vmvnt %q0, %q2"
4135 [(set_attr "type" "mve_move")
4136 (set_attr "length""8")])
4137
4138;;
4139;; [vnegq_m_s])
4140;;
4141(define_insn "mve_vnegq_m_s<mode>"
4142 [
4143 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4144 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4145 (match_operand:MVE_2 2 "s_register_operand" "w")
4146 (match_operand:HI 3 "vpr_register_operand" "Up")]
4147 VNEGQ_M_S))
4148 ]
4149 "TARGET_HAVE_MVE"
4150 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
4151 [(set_attr "type" "mve_move")
4152 (set_attr "length""8")])
4153
4154;;
4155;; [vpselq_u, vpselq_s])
4156;;
4157(define_insn "mve_vpselq_<supf><mode>"
4158 [
4159 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
4160 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
4161 (match_operand:MVE_1 2 "s_register_operand" "w")
4162 (match_operand:HI 3 "vpr_register_operand" "Up")]
4163 VPSELQ))
4164 ]
4165 "TARGET_HAVE_MVE"
4166 "vpsel %q0, %q1, %q2"
4167 [(set_attr "type" "mve_move")
4168])
4169
4170;;
4171;; [vqabsq_m_s])
4172;;
4173(define_insn "mve_vqabsq_m_s<mode>"
4174 [
4175 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4176 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4177 (match_operand:MVE_2 2 "s_register_operand" "w")
4178 (match_operand:HI 3 "vpr_register_operand" "Up")]
4179 VQABSQ_M_S))
4180 ]
4181 "TARGET_HAVE_MVE"
4182 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
4183 [(set_attr "type" "mve_move")
4184 (set_attr "length""8")])
4185
4186;;
4187;; [vqdmlahq_n_s, vqdmlahq_n_u])
4188;;
4189(define_insn "mve_vqdmlahq_n_<supf><mode>"
4190 [
4191 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4192 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4193 (match_operand:MVE_2 2 "s_register_operand" "w")
4194 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4195 VQDMLAHQ_N))
4196 ]
4197 "TARGET_HAVE_MVE"
4198 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4199 [(set_attr "type" "mve_move")
4200])
4201
4202;;
4203;; [vqnegq_m_s])
4204;;
4205(define_insn "mve_vqnegq_m_s<mode>"
4206 [
4207 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4208 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4209 (match_operand:MVE_2 2 "s_register_operand" "w")
4210 (match_operand:HI 3 "vpr_register_operand" "Up")]
4211 VQNEGQ_M_S))
4212 ]
4213 "TARGET_HAVE_MVE"
4214 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
4215 [(set_attr "type" "mve_move")
4216 (set_attr "length""8")])
4217
4218;;
4219;; [vqrdmladhq_s])
4220;;
4221(define_insn "mve_vqrdmladhq_s<mode>"
4222 [
4223 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4224 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4225 (match_operand:MVE_2 2 "s_register_operand" "w")
4226 (match_operand:MVE_2 3 "s_register_operand" "w")]
4227 VQRDMLADHQ_S))
4228 ]
4229 "TARGET_HAVE_MVE"
4230 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4231 [(set_attr "type" "mve_move")
4232])
4233
4234;;
4235;; [vqrdmladhxq_s])
4236;;
4237(define_insn "mve_vqrdmladhxq_s<mode>"
4238 [
4239 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4240 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4241 (match_operand:MVE_2 2 "s_register_operand" "w")
4242 (match_operand:MVE_2 3 "s_register_operand" "w")]
4243 VQRDMLADHXQ_S))
4244 ]
4245 "TARGET_HAVE_MVE"
4246 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4247 [(set_attr "type" "mve_move")
4248])
4249
4250;;
4251;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
4252;;
4253(define_insn "mve_vqrdmlahq_n_<supf><mode>"
4254 [
4255 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4256 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4257 (match_operand:MVE_2 2 "s_register_operand" "w")
4258 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4259 VQRDMLAHQ_N))
4260 ]
4261 "TARGET_HAVE_MVE"
4262 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4263 [(set_attr "type" "mve_move")
4264])
4265
4266;;
4267;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
4268;;
4269(define_insn "mve_vqrdmlashq_n_<supf><mode>"
4270 [
4271 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4272 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4273 (match_operand:MVE_2 2 "s_register_operand" "w")
4274 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4275 VQRDMLASHQ_N))
4276 ]
4277 "TARGET_HAVE_MVE"
4278 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
4279 [(set_attr "type" "mve_move")
4280])
4281
4282;;
4283;; [vqrdmlsdhq_s])
4284;;
4285(define_insn "mve_vqrdmlsdhq_s<mode>"
4286 [
4287 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4288 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4289 (match_operand:MVE_2 2 "s_register_operand" "w")
4290 (match_operand:MVE_2 3 "s_register_operand" "w")]
4291 VQRDMLSDHQ_S))
4292 ]
4293 "TARGET_HAVE_MVE"
4294 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4295 [(set_attr "type" "mve_move")
4296])
4297
4298;;
4299;; [vqrdmlsdhxq_s])
4300;;
4301(define_insn "mve_vqrdmlsdhxq_s<mode>"
4302 [
4303 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4304 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4305 (match_operand:MVE_2 2 "s_register_operand" "w")
4306 (match_operand:MVE_2 3 "s_register_operand" "w")]
4307 VQRDMLSDHXQ_S))
4308 ]
4309 "TARGET_HAVE_MVE"
4310 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4311 [(set_attr "type" "mve_move")
4312])
4313
4314;;
4315;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
4316;;
4317(define_insn "mve_vqrshlq_m_n_<supf><mode>"
4318 [
4319 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4320 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4321 (match_operand:SI 2 "s_register_operand" "r")
4322 (match_operand:HI 3 "vpr_register_operand" "Up")]
4323 VQRSHLQ_M_N))
4324 ]
4325 "TARGET_HAVE_MVE"
4326 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2"
4327 [(set_attr "type" "mve_move")
4328 (set_attr "length""8")])
4329
4330;;
4331;; [vqshlq_m_r_u, vqshlq_m_r_s])
4332;;
4333(define_insn "mve_vqshlq_m_r_<supf><mode>"
4334 [
4335 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4336 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4337 (match_operand:SI 2 "s_register_operand" "r")
4338 (match_operand:HI 3 "vpr_register_operand" "Up")]
4339 VQSHLQ_M_R))
4340 ]
4341 "TARGET_HAVE_MVE"
4342 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4343 [(set_attr "type" "mve_move")
4344 (set_attr "length""8")])
4345
4346;;
4347;; [vrev64q_m_u, vrev64q_m_s])
4348;;
4349(define_insn "mve_vrev64q_m_<supf><mode>"
4350 [
4351 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4352 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4353 (match_operand:MVE_2 2 "s_register_operand" "w")
4354 (match_operand:HI 3 "vpr_register_operand" "Up")]
4355 VREV64Q_M))
4356 ]
4357 "TARGET_HAVE_MVE"
4358 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
4359 [(set_attr "type" "mve_move")
4360 (set_attr "length""8")])
4361
4362;;
4363;; [vrshlq_m_n_s, vrshlq_m_n_u])
4364;;
4365(define_insn "mve_vrshlq_m_n_<supf><mode>"
4366 [
4367 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4368 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4369 (match_operand:SI 2 "s_register_operand" "r")
4370 (match_operand:HI 3 "vpr_register_operand" "Up")]
4371 VRSHLQ_M_N))
4372 ]
4373 "TARGET_HAVE_MVE"
4374 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4375 [(set_attr "type" "mve_move")
4376 (set_attr "length""8")])
4377
4378;;
4379;; [vshlq_m_r_u, vshlq_m_r_s])
4380;;
4381(define_insn "mve_vshlq_m_r_<supf><mode>"
4382 [
4383 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4384 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4385 (match_operand:SI 2 "s_register_operand" "r")
4386 (match_operand:HI 3 "vpr_register_operand" "Up")]
4387 VSHLQ_M_R))
4388 ]
4389 "TARGET_HAVE_MVE"
4390 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4391 [(set_attr "type" "mve_move")
4392 (set_attr "length""8")])
4393
4394;;
4395;; [vsliq_n_u, vsliq_n_s])
4396;;
4397(define_insn "mve_vsliq_n_<supf><mode>"
4398 [
4399 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4400 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4401 (match_operand:MVE_2 2 "s_register_operand" "w")
4402 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
4403 VSLIQ_N))
4404 ]
4405 "TARGET_HAVE_MVE"
4406 "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
4407 [(set_attr "type" "mve_move")
4408])
4409
4410;;
4411;; [vsriq_n_u, vsriq_n_s])
4412;;
4413(define_insn "mve_vsriq_n_<supf><mode>"
4414 [
4415 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4416 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4417 (match_operand:MVE_2 2 "s_register_operand" "w")
4418 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
4419 VSRIQ_N))
4420 ]
4421 "TARGET_HAVE_MVE"
4422 "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
4423 [(set_attr "type" "mve_move")
4424])
4425
4426;;
4427;; [vqdmlsdhxq_s])
4428;;
4429(define_insn "mve_vqdmlsdhxq_s<mode>"
4430 [
4431 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4432 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4433 (match_operand:MVE_2 2 "s_register_operand" "w")
4434 (match_operand:MVE_2 3 "s_register_operand" "w")]
4435 VQDMLSDHXQ_S))
4436 ]
4437 "TARGET_HAVE_MVE"
4438 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4439 [(set_attr "type" "mve_move")
4440])
4441
4442;;
4443;; [vqdmlsdhq_s])
4444;;
4445(define_insn "mve_vqdmlsdhq_s<mode>"
4446 [
4447 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4448 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4449 (match_operand:MVE_2 2 "s_register_operand" "w")
4450 (match_operand:MVE_2 3 "s_register_operand" "w")]
4451 VQDMLSDHQ_S))
4452 ]
4453 "TARGET_HAVE_MVE"
4454 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4455 [(set_attr "type" "mve_move")
4456])
4457
4458;;
4459;; [vqdmladhxq_s])
4460;;
4461(define_insn "mve_vqdmladhxq_s<mode>"
4462 [
4463 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4464 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4465 (match_operand:MVE_2 2 "s_register_operand" "w")
4466 (match_operand:MVE_2 3 "s_register_operand" "w")]
4467 VQDMLADHXQ_S))
4468 ]
4469 "TARGET_HAVE_MVE"
4470 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4471 [(set_attr "type" "mve_move")
4472])
4473
4474;;
4475;; [vqdmladhq_s])
4476;;
4477(define_insn "mve_vqdmladhq_s<mode>"
4478 [
4479 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4480 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4481 (match_operand:MVE_2 2 "s_register_operand" "w")
4482 (match_operand:MVE_2 3 "s_register_operand" "w")]
4483 VQDMLADHQ_S))
4484 ]
4485 "TARGET_HAVE_MVE"
4486 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4487 [(set_attr "type" "mve_move")
4488])
4489
4490;;
4491;; [vmlsdavaxq_s])
4492;;
4493(define_insn "mve_vmlsdavaxq_s<mode>"
4494 [
4495 (set (match_operand:SI 0 "s_register_operand" "=e")
4496 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4497 (match_operand:MVE_2 2 "s_register_operand" "w")
4498 (match_operand:MVE_2 3 "s_register_operand" "w")]
4499 VMLSDAVAXQ_S))
4500 ]
4501 "TARGET_HAVE_MVE"
4502 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4503 [(set_attr "type" "mve_move")
4504])
4505
4506;;
4507;; [vmlsdavaq_s])
4508;;
4509(define_insn "mve_vmlsdavaq_s<mode>"
4510 [
4511 (set (match_operand:SI 0 "s_register_operand" "=e")
4512 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4513 (match_operand:MVE_2 2 "s_register_operand" "w")
4514 (match_operand:MVE_2 3 "s_register_operand" "w")]
4515 VMLSDAVAQ_S))
4516 ]
4517 "TARGET_HAVE_MVE"
4518 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4519 [(set_attr "type" "mve_move")
4520])
4521
4522;;
4523;; [vmladavaxq_s])
4524;;
4525(define_insn "mve_vmladavaxq_s<mode>"
4526 [
4527 (set (match_operand:SI 0 "s_register_operand" "=e")
4528 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4529 (match_operand:MVE_2 2 "s_register_operand" "w")
4530 (match_operand:MVE_2 3 "s_register_operand" "w")]
4531 VMLADAVAXQ_S))
4532 ]
4533 "TARGET_HAVE_MVE"
4534 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4535 [(set_attr "type" "mve_move")
4536])
e3678b44
SP		 4537;;
4538;; [vabsq_m_f])
4539;;
4540(define_insn "mve_vabsq_m_f<mode>"
4541 [
4542 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4543 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4544 (match_operand:MVE_0 2 "s_register_operand" "w")
4545 (match_operand:HI 3 "vpr_register_operand" "Up")]
4546 VABSQ_M_F))
4547 ]
4548 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4549 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
4550 [(set_attr "type" "mve_move")
4551 (set_attr "length""8")])
4552
4553;;
4554;; [vaddlvaq_p_s vaddlvaq_p_u])
4555;;
4556(define_insn "mve_vaddlvaq_p_<supf>v4si"
4557 [
4558 (set (match_operand:DI 0 "s_register_operand" "=r")
4559 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4560 (match_operand:V4SI 2 "s_register_operand" "w")
4561 (match_operand:HI 3 "vpr_register_operand" "Up")]
4562 VADDLVAQ_P))
4563 ]
4564 "TARGET_HAVE_MVE"
4565 "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4566 [(set_attr "type" "mve_move")
4567 (set_attr "length""8")])
4568;;
4569;; [vcmlaq_f])
4570;;
4571(define_insn "mve_vcmlaq_f<mode>"
4572 [
4573 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4574 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4575 (match_operand:MVE_0 2 "s_register_operand" "w")
4576 (match_operand:MVE_0 3 "s_register_operand" "w")]
4577 VCMLAQ_F))
4578 ]
4579 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4580 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4581 [(set_attr "type" "mve_move")
4582])
4583
4584;;
4585;; [vcmlaq_rot180_f])
4586;;
4587(define_insn "mve_vcmlaq_rot180_f<mode>"
4588 [
4589 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4590 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4591 (match_operand:MVE_0 2 "s_register_operand" "w")
4592 (match_operand:MVE_0 3 "s_register_operand" "w")]
4593 VCMLAQ_ROT180_F))
4594 ]
4595 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4596 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4597 [(set_attr "type" "mve_move")
4598])
4599
4600;;
4601;; [vcmlaq_rot270_f])
4602;;
4603(define_insn "mve_vcmlaq_rot270_f<mode>"
4604 [
4605 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4606 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4607 (match_operand:MVE_0 2 "s_register_operand" "w")
4608 (match_operand:MVE_0 3 "s_register_operand" "w")]
4609 VCMLAQ_ROT270_F))
4610 ]
4611 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4612 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4613 [(set_attr "type" "mve_move")
4614])
4615
4616;;
4617;; [vcmlaq_rot90_f])
4618;;
4619(define_insn "mve_vcmlaq_rot90_f<mode>"
4620 [
4621 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4622 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4623 (match_operand:MVE_0 2 "s_register_operand" "w")
4624 (match_operand:MVE_0 3 "s_register_operand" "w")]
4625 VCMLAQ_ROT90_F))
4626 ]
4627 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4628 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4629 [(set_attr "type" "mve_move")
4630])
4631
4632;;
4633;; [vcmpeqq_m_n_f])
4634;;
4635(define_insn "mve_vcmpeqq_m_n_f<mode>"
4636 [
4637 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4638 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4639 (match_operand:<V_elem> 2 "s_register_operand" "r")
4640 (match_operand:HI 3 "vpr_register_operand" "Up")]
4641 VCMPEQQ_M_N_F))
4642 ]
4643 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4644 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2"
4645 [(set_attr "type" "mve_move")
4646 (set_attr "length""8")])
4647
4648;;
4649;; [vcmpgeq_m_f])
4650;;
4651(define_insn "mve_vcmpgeq_m_f<mode>"
4652 [
4653 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4654 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4655 (match_operand:MVE_0 2 "s_register_operand" "w")
4656 (match_operand:HI 3 "vpr_register_operand" "Up")]
4657 VCMPGEQ_M_F))
4658 ]
4659 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4660 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2"
4661 [(set_attr "type" "mve_move")
4662 (set_attr "length""8")])
4663
4664;;
4665;; [vcmpgeq_m_n_f])
4666;;
4667(define_insn "mve_vcmpgeq_m_n_f<mode>"
4668 [
4669 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4670 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4671 (match_operand:<V_elem> 2 "s_register_operand" "r")
4672 (match_operand:HI 3 "vpr_register_operand" "Up")]
4673 VCMPGEQ_M_N_F))
4674 ]
4675 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4676 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2"
4677 [(set_attr "type" "mve_move")
4678 (set_attr "length""8")])
4679
4680;;
4681;; [vcmpgtq_m_f])
4682;;
4683(define_insn "mve_vcmpgtq_m_f<mode>"
4684 [
4685 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4686 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4687 (match_operand:MVE_0 2 "s_register_operand" "w")
4688 (match_operand:HI 3 "vpr_register_operand" "Up")]
4689 VCMPGTQ_M_F))
4690 ]
4691 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4692 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2"
4693 [(set_attr "type" "mve_move")
4694 (set_attr "length""8")])
4695
4696;;
4697;; [vcmpgtq_m_n_f])
4698;;
4699(define_insn "mve_vcmpgtq_m_n_f<mode>"
4700 [
4701 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4702 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4703 (match_operand:<V_elem> 2 "s_register_operand" "r")
4704 (match_operand:HI 3 "vpr_register_operand" "Up")]
4705 VCMPGTQ_M_N_F))
4706 ]
4707 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4708 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2"
4709 [(set_attr "type" "mve_move")
4710 (set_attr "length""8")])
4711
4712;;
4713;; [vcmpleq_m_f])
4714;;
4715(define_insn "mve_vcmpleq_m_f<mode>"
4716 [
4717 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4718 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4719 (match_operand:MVE_0 2 "s_register_operand" "w")
4720 (match_operand:HI 3 "vpr_register_operand" "Up")]
4721 VCMPLEQ_M_F))
4722 ]
4723 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4724 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2"
4725 [(set_attr "type" "mve_move")
4726 (set_attr "length""8")])
4727
4728;;
4729;; [vcmpleq_m_n_f])
4730;;
4731(define_insn "mve_vcmpleq_m_n_f<mode>"
4732 [
4733 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4734 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4735 (match_operand:<V_elem> 2 "s_register_operand" "r")
4736 (match_operand:HI 3 "vpr_register_operand" "Up")]
4737 VCMPLEQ_M_N_F))
4738 ]
4739 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4740 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2"
4741 [(set_attr "type" "mve_move")
4742 (set_attr "length""8")])
4743
4744;;
4745;; [vcmpltq_m_f])
4746;;
4747(define_insn "mve_vcmpltq_m_f<mode>"
4748 [
4749 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4750 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4751 (match_operand:MVE_0 2 "s_register_operand" "w")
4752 (match_operand:HI 3 "vpr_register_operand" "Up")]
4753 VCMPLTQ_M_F))
4754 ]
4755 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4756 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2"
4757 [(set_attr "type" "mve_move")
4758 (set_attr "length""8")])
4759
4760;;
4761;; [vcmpltq_m_n_f])
4762;;
4763(define_insn "mve_vcmpltq_m_n_f<mode>"
4764 [
4765 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4766 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4767 (match_operand:<V_elem> 2 "s_register_operand" "r")
4768 (match_operand:HI 3 "vpr_register_operand" "Up")]
4769 VCMPLTQ_M_N_F))
4770 ]
4771 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4772 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2"
4773 [(set_attr "type" "mve_move")
4774 (set_attr "length""8")])
4775
4776;;
4777;; [vcmpneq_m_f])
4778;;
4779(define_insn "mve_vcmpneq_m_f<mode>"
4780 [
4781 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4782 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4783 (match_operand:MVE_0 2 "s_register_operand" "w")
4784 (match_operand:HI 3 "vpr_register_operand" "Up")]
4785 VCMPNEQ_M_F))
4786 ]
4787 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4788 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2"
4789 [(set_attr "type" "mve_move")
4790 (set_attr "length""8")])
4791
4792;;
4793;; [vcmpneq_m_n_f])
4794;;
4795(define_insn "mve_vcmpneq_m_n_f<mode>"
4796 [
4797 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4798 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4799 (match_operand:<V_elem> 2 "s_register_operand" "r")
4800 (match_operand:HI 3 "vpr_register_operand" "Up")]
4801 VCMPNEQ_M_N_F))
4802 ]
4803 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4804 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2"
4805 [(set_attr "type" "mve_move")
4806 (set_attr "length""8")])
4807
4808;;
4809;; [vcvtbq_m_f16_f32])
4810;;
4811(define_insn "mve_vcvtbq_m_f16_f32v8hf"
4812 [
4813 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4814 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4815 (match_operand:V4SF 2 "s_register_operand" "w")
4816 (match_operand:HI 3 "vpr_register_operand" "Up")]
4817 VCVTBQ_M_F16_F32))
4818 ]
4819 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4820 "vpst\;vcvtbt.f16.f32 %q0, %q2"
4821 [(set_attr "type" "mve_move")
4822 (set_attr "length""8")])
4823
4824;;
4825;; [vcvtbq_m_f32_f16])
4826;;
4827(define_insn "mve_vcvtbq_m_f32_f16v4sf"
4828 [
4829 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4830 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4831 (match_operand:V8HF 2 "s_register_operand" "w")
4832 (match_operand:HI 3 "vpr_register_operand" "Up")]
4833 VCVTBQ_M_F32_F16))
4834 ]
4835 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4836 "vpst\;vcvtbt.f32.f16 %q0, %q2"
4837 [(set_attr "type" "mve_move")
4838 (set_attr "length""8")])
4839
4840;;
4841;; [vcvttq_m_f16_f32])
4842;;
4843(define_insn "mve_vcvttq_m_f16_f32v8hf"
4844 [
4845 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4846 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4847 (match_operand:V4SF 2 "s_register_operand" "w")
4848 (match_operand:HI 3 "vpr_register_operand" "Up")]
4849 VCVTTQ_M_F16_F32))
4850 ]
4851 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4852 "vpst\;vcvttt.f16.f32 %q0, %q2"
4853 [(set_attr "type" "mve_move")
4854 (set_attr "length""8")])
4855
4856;;
4857;; [vcvttq_m_f32_f16])
4858;;
4859(define_insn "mve_vcvttq_m_f32_f16v4sf"
4860 [
4861 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4862 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4863 (match_operand:V8HF 2 "s_register_operand" "w")
4864 (match_operand:HI 3 "vpr_register_operand" "Up")]
4865 VCVTTQ_M_F32_F16))
4866 ]
4867 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4868 "vpst\;vcvttt.f32.f16 %q0, %q2"
4869 [(set_attr "type" "mve_move")
4870 (set_attr "length""8")])
4871
4872;;
4873;; [vdupq_m_n_f])
4874;;
4875(define_insn "mve_vdupq_m_n_f<mode>"
4876 [
4877 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4878 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4879 (match_operand:<V_elem> 2 "s_register_operand" "r")
4880 (match_operand:HI 3 "vpr_register_operand" "Up")]
4881 VDUPQ_M_N_F))
4882 ]
4883 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4884 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4885 [(set_attr "type" "mve_move")
4886 (set_attr "length""8")])
4887
4888;;
4889;; [vfmaq_f])
4890;;
4891(define_insn "mve_vfmaq_f<mode>"
4892 [
4893 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4894 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4895 (match_operand:MVE_0 2 "s_register_operand" "w")
4896 (match_operand:MVE_0 3 "s_register_operand" "w")]
4897 VFMAQ_F))
4898 ]
4899 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4900 "vfma.f%#<V_sz_elem> %q0, %q2, %q3"
4901 [(set_attr "type" "mve_move")
4902])
4903
4904;;
4905;; [vfmaq_n_f])
4906;;
4907(define_insn "mve_vfmaq_n_f<mode>"
4908 [
4909 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4910 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4911 (match_operand:MVE_0 2 "s_register_operand" "w")
4912 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4913 VFMAQ_N_F))
4914 ]
4915 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4916 "vfma.f%#<V_sz_elem> %q0, %q2, %3"
4917 [(set_attr "type" "mve_move")
4918])
4919
4920;;
4921;; [vfmasq_n_f])
4922;;
4923(define_insn "mve_vfmasq_n_f<mode>"
4924 [
4925 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4926 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4927 (match_operand:MVE_0 2 "s_register_operand" "w")
4928 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4929 VFMASQ_N_F))
4930 ]
4931 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4932 "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
4933 [(set_attr "type" "mve_move")
4934])
4935;;
4936;; [vfmsq_f])
4937;;
4938(define_insn "mve_vfmsq_f<mode>"
4939 [
4940 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4941 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4942 (match_operand:MVE_0 2 "s_register_operand" "w")
4943 (match_operand:MVE_0 3 "s_register_operand" "w")]
4944 VFMSQ_F))
4945 ]
4946 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4947 "vfms.f%#<V_sz_elem> %q0, %q2, %q3"
4948 [(set_attr "type" "mve_move")
4949])
4950
4951;;
4952;; [vmaxnmaq_m_f])
4953;;
4954(define_insn "mve_vmaxnmaq_m_f<mode>"
4955 [
4956 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4957 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4958 (match_operand:MVE_0 2 "s_register_operand" "w")
4959 (match_operand:HI 3 "vpr_register_operand" "Up")]
4960 VMAXNMAQ_M_F))
4961 ]
4962 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4963 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2"
4964 [(set_attr "type" "mve_move")
4965 (set_attr "length""8")])
4966;;
4967;; [vmaxnmavq_p_f])
4968;;
4969(define_insn "mve_vmaxnmavq_p_f<mode>"
4970 [
4971 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4972 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4973 (match_operand:MVE_0 2 "s_register_operand" "w")
4974 (match_operand:HI 3 "vpr_register_operand" "Up")]
4975 VMAXNMAVQ_P_F))
4976 ]
4977 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4978 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2"
4979 [(set_attr "type" "mve_move")
4980 (set_attr "length""8")])
4981
4982;;
4983;; [vmaxnmvq_p_f])
4984;;
4985(define_insn "mve_vmaxnmvq_p_f<mode>"
4986 [
4987 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4988 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4989 (match_operand:MVE_0 2 "s_register_operand" "w")
4990 (match_operand:HI 3 "vpr_register_operand" "Up")]
4991 VMAXNMVQ_P_F))
4992 ]
4993 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4994 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2"
4995 [(set_attr "type" "mve_move")
4996 (set_attr "length""8")])
4997;;
4998;; [vminnmaq_m_f])
4999;;
5000(define_insn "mve_vminnmaq_m_f<mode>"
5001 [
5002 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5003 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5004 (match_operand:MVE_0 2 "s_register_operand" "w")
5005 (match_operand:HI 3 "vpr_register_operand" "Up")]
5006 VMINNMAQ_M_F))
5007 ]
5008 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5009 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2"
5010 [(set_attr "type" "mve_move")
5011 (set_attr "length""8")])
5012
5013;;
5014;; [vminnmavq_p_f])
5015;;
5016(define_insn "mve_vminnmavq_p_f<mode>"
5017 [
5018 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5019 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5020 (match_operand:MVE_0 2 "s_register_operand" "w")
5021 (match_operand:HI 3 "vpr_register_operand" "Up")]
5022 VMINNMAVQ_P_F))
5023 ]
5024 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5025 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2"
5026 [(set_attr "type" "mve_move")
5027 (set_attr "length""8")])
5028;;
5029;; [vminnmvq_p_f])
5030;;
5031(define_insn "mve_vminnmvq_p_f<mode>"
5032 [
5033 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5034 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5035 (match_operand:MVE_0 2 "s_register_operand" "w")
5036 (match_operand:HI 3 "vpr_register_operand" "Up")]
5037 VMINNMVQ_P_F))
5038 ]
5039 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5040 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2"
5041 [(set_attr "type" "mve_move")
5042 (set_attr "length""8")])
5043
5044;;
5045;; [vmlaldavaq_s, vmlaldavaq_u])
5046;;
5047(define_insn "mve_vmlaldavaq_<supf><mode>"
5048 [
5049 (set (match_operand:DI 0 "s_register_operand" "=r")
5050 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5051 (match_operand:MVE_5 2 "s_register_operand" "w")
5052 (match_operand:MVE_5 3 "s_register_operand" "w")]
5053 VMLALDAVAQ))
5054 ]
5055 "TARGET_HAVE_MVE"
5056 "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5057 [(set_attr "type" "mve_move")
5058])
5059
5060;;
5061;; [vmlaldavaxq_s])
5062;;
5063(define_insn "mve_vmlaldavaxq_s<mode>"
5064 [
5065 (set (match_operand:DI 0 "s_register_operand" "=r")
5066 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5067 (match_operand:MVE_5 2 "s_register_operand" "w")
5068 (match_operand:MVE_5 3 "s_register_operand" "w")]
5069 VMLALDAVAXQ_S))
5070 ]
5071 "TARGET_HAVE_MVE"
5072 "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5073 [(set_attr "type" "mve_move")
5074])
5075
5076;;
5077;; [vmlaldavq_p_u, vmlaldavq_p_s])
5078;;
5079(define_insn "mve_vmlaldavq_p_<supf><mode>"
5080 [
5081 (set (match_operand:DI 0 "s_register_operand" "=r")
5082 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5083 (match_operand:MVE_5 2 "s_register_operand" "w")
5084 (match_operand:HI 3 "vpr_register_operand" "Up")]
5085 VMLALDAVQ_P))
5086 ]
5087 "TARGET_HAVE_MVE"
5088 "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5089 [(set_attr "type" "mve_move")
5090 (set_attr "length""8")])
5091
5092;;
5093;; [vmlaldavxq_p_s])
5094;;
5095(define_insn "mve_vmlaldavxq_p_s<mode>"
5096 [
5097 (set (match_operand:DI 0 "s_register_operand" "=r")
5098 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5099 (match_operand:MVE_5 2 "s_register_operand" "w")
5100 (match_operand:HI 3 "vpr_register_operand" "Up")]
5101 VMLALDAVXQ_P_S))
5102 ]
5103 "TARGET_HAVE_MVE"
5104 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
5105 [(set_attr "type" "mve_move")
5106 (set_attr "length""8")])
5107;;
5108;; [vmlsldavaq_s])
5109;;
5110(define_insn "mve_vmlsldavaq_s<mode>"
5111 [
5112 (set (match_operand:DI 0 "s_register_operand" "=r")
5113 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5114 (match_operand:MVE_5 2 "s_register_operand" "w")
5115 (match_operand:MVE_5 3 "s_register_operand" "w")]
5116 VMLSLDAVAQ_S))
5117 ]
5118 "TARGET_HAVE_MVE"
5119 "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5120 [(set_attr "type" "mve_move")
5121])
5122
5123;;
5124;; [vmlsldavaxq_s])
5125;;
5126(define_insn "mve_vmlsldavaxq_s<mode>"
5127 [
5128 (set (match_operand:DI 0 "s_register_operand" "=r")
5129 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5130 (match_operand:MVE_5 2 "s_register_operand" "w")
5131 (match_operand:MVE_5 3 "s_register_operand" "w")]
5132 VMLSLDAVAXQ_S))
5133 ]
5134 "TARGET_HAVE_MVE"
5135 "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5136 [(set_attr "type" "mve_move")
5137])
5138
5139;;
5140;; [vmlsldavq_p_s])
5141;;
5142(define_insn "mve_vmlsldavq_p_s<mode>"
5143 [
5144 (set (match_operand:DI 0 "s_register_operand" "=r")
5145 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5146 (match_operand:MVE_5 2 "s_register_operand" "w")
5147 (match_operand:HI 3 "vpr_register_operand" "Up")]
5148 VMLSLDAVQ_P_S))
5149 ]
5150 "TARGET_HAVE_MVE"
5151 "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5152 [(set_attr "type" "mve_move")
5153 (set_attr "length""8")])
5154
5155;;
5156;; [vmlsldavxq_p_s])
5157;;
5158(define_insn "mve_vmlsldavxq_p_s<mode>"
5159 [
5160 (set (match_operand:DI 0 "s_register_operand" "=r")
5161 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5162 (match_operand:MVE_5 2 "s_register_operand" "w")
5163 (match_operand:HI 3 "vpr_register_operand" "Up")]
5164 VMLSLDAVXQ_P_S))
5165 ]
5166 "TARGET_HAVE_MVE"
5167 "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5168 [(set_attr "type" "mve_move")
5169 (set_attr "length""8")])
5170;;
5171;; [vmovlbq_m_u, vmovlbq_m_s])
5172;;
5173(define_insn "mve_vmovlbq_m_<supf><mode>"
5174 [
5175 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5176 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5177 (match_operand:MVE_3 2 "s_register_operand" "w")
5178 (match_operand:HI 3 "vpr_register_operand" "Up")]
5179 VMOVLBQ_M))
5180 ]
5181 "TARGET_HAVE_MVE"
5182 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2"
5183 [(set_attr "type" "mve_move")
5184 (set_attr "length""8")])
5185;;
5186;; [vmovltq_m_u, vmovltq_m_s])
5187;;
5188(define_insn "mve_vmovltq_m_<supf><mode>"
5189 [
5190 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5191 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5192 (match_operand:MVE_3 2 "s_register_operand" "w")
5193 (match_operand:HI 3 "vpr_register_operand" "Up")]
5194 VMOVLTQ_M))
5195 ]
5196 "TARGET_HAVE_MVE"
5197 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2"
5198 [(set_attr "type" "mve_move")
5199 (set_attr "length""8")])
5200;;
5201;; [vmovnbq_m_u, vmovnbq_m_s])
5202;;
5203(define_insn "mve_vmovnbq_m_<supf><mode>"
5204 [
5205 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5206 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5207 (match_operand:MVE_5 2 "s_register_operand" "w")
5208 (match_operand:HI 3 "vpr_register_operand" "Up")]
5209 VMOVNBQ_M))
5210 ]
5211 "TARGET_HAVE_MVE"
5212 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
5213 [(set_attr "type" "mve_move")
5214 (set_attr "length""8")])
5215
5216;;
5217;; [vmovntq_m_u, vmovntq_m_s])
5218;;
5219(define_insn "mve_vmovntq_m_<supf><mode>"
5220 [
5221 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5222 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5223 (match_operand:MVE_5 2 "s_register_operand" "w")
5224 (match_operand:HI 3 "vpr_register_operand" "Up")]
5225 VMOVNTQ_M))
5226 ]
5227 "TARGET_HAVE_MVE"
5228 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
5229 [(set_attr "type" "mve_move")
5230 (set_attr "length""8")])
5231
5232;;
5233;; [vmvnq_m_n_u, vmvnq_m_n_s])
5234;;
5235(define_insn "mve_vmvnq_m_n_<supf><mode>"
5236 [
5237 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5238 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5239 (match_operand:SI 2 "immediate_operand" "i")
5240 (match_operand:HI 3 "vpr_register_operand" "Up")]
5241 VMVNQ_M_N))
5242 ]
5243 "TARGET_HAVE_MVE"
5244 "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
5245 [(set_attr "type" "mve_move")
5246 (set_attr "length""8")])
5247;;
5248;; [vnegq_m_f])
5249;;
5250(define_insn "mve_vnegq_m_f<mode>"
5251 [
5252 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5253 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5254 (match_operand:MVE_0 2 "s_register_operand" "w")
5255 (match_operand:HI 3 "vpr_register_operand" "Up")]
5256 VNEGQ_M_F))
5257 ]
5258 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5259 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
5260 [(set_attr "type" "mve_move")
5261 (set_attr "length""8")])
5262
5263;;
5264;; [vorrq_m_n_s, vorrq_m_n_u])
5265;;
5266(define_insn "mve_vorrq_m_n_<supf><mode>"
5267 [
5268 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5269 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5270 (match_operand:SI 2 "immediate_operand" "i")
5271 (match_operand:HI 3 "vpr_register_operand" "Up")]
5272 VORRQ_M_N))
5273 ]
5274 "TARGET_HAVE_MVE"
5275 "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
5276 [(set_attr "type" "mve_move")
5277 (set_attr "length""8")])
5278;;
5279;; [vpselq_f])
5280;;
5281(define_insn "mve_vpselq_f<mode>"
5282 [
5283 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5284 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
5285 (match_operand:MVE_0 2 "s_register_operand" "w")
5286 (match_operand:HI 3 "vpr_register_operand" "Up")]
5287 VPSELQ_F))
5288 ]
5289 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5290 "vpsel %q0, %q1, %q2"
5291 [(set_attr "type" "mve_move")
5292])
5293
5294;;
5295;; [vqmovnbq_m_s, vqmovnbq_m_u])
5296;;
5297(define_insn "mve_vqmovnbq_m_<supf><mode>"
5298 [
5299 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5300 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5301 (match_operand:MVE_5 2 "s_register_operand" "w")
5302 (match_operand:HI 3 "vpr_register_operand" "Up")]
5303 VQMOVNBQ_M))
5304 ]
5305 "TARGET_HAVE_MVE"
5306 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2"
5307 [(set_attr "type" "mve_move")
5308 (set_attr "length""8")])
5309
5310;;
5311;; [vqmovntq_m_u, vqmovntq_m_s])
5312;;
5313(define_insn "mve_vqmovntq_m_<supf><mode>"
5314 [
5315 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5316 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5317 (match_operand:MVE_5 2 "s_register_operand" "w")
5318 (match_operand:HI 3 "vpr_register_operand" "Up")]
5319 VQMOVNTQ_M))
5320 ]
5321 "TARGET_HAVE_MVE"
5322 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2"
5323 [(set_attr "type" "mve_move")
5324 (set_attr "length""8")])
5325
5326;;
5327;; [vqmovunbq_m_s])
5328;;
5329(define_insn "mve_vqmovunbq_m_s<mode>"
5330 [
5331 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5332 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5333 (match_operand:MVE_5 2 "s_register_operand" "w")
5334 (match_operand:HI 3 "vpr_register_operand" "Up")]
5335 VQMOVUNBQ_M_S))
5336 ]
5337 "TARGET_HAVE_MVE"
5338 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2"
5339 [(set_attr "type" "mve_move")
5340 (set_attr "length""8")])
5341
5342;;
5343;; [vqmovuntq_m_s])
5344;;
5345(define_insn "mve_vqmovuntq_m_s<mode>"
5346 [
5347 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5348 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5349 (match_operand:MVE_5 2 "s_register_operand" "w")
5350 (match_operand:HI 3 "vpr_register_operand" "Up")]
5351 VQMOVUNTQ_M_S))
5352 ]
5353 "TARGET_HAVE_MVE"
5354 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2"
5355 [(set_attr "type" "mve_move")
5356 (set_attr "length""8")])
5357
5358;;
5359;; [vqrshrntq_n_u, vqrshrntq_n_s])
5360;;
5361(define_insn "mve_vqrshrntq_n_<supf><mode>"
5362 [
5363 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5364 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5365 (match_operand:MVE_5 2 "s_register_operand" "w")
5366 (match_operand:SI 3 "mve_imm_8" "Rb")]
5367 VQRSHRNTQ_N))
5368 ]
5369 "TARGET_HAVE_MVE"
5370 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5371 [(set_attr "type" "mve_move")
5372])
5373
5374;;
5375;; [vqrshruntq_n_s])
5376;;
5377(define_insn "mve_vqrshruntq_n_s<mode>"
5378 [
5379 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5380 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5381 (match_operand:MVE_5 2 "s_register_operand" "w")
5382 (match_operand:SI 3 "mve_imm_8" "Rb")]
5383 VQRSHRUNTQ_N_S))
5384 ]
5385 "TARGET_HAVE_MVE"
5386 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5387 [(set_attr "type" "mve_move")
5388])
5389
5390;;
5391;; [vqshrnbq_n_u, vqshrnbq_n_s])
5392;;
5393(define_insn "mve_vqshrnbq_n_<supf><mode>"
5394 [
5395 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5396 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5397 (match_operand:MVE_5 2 "s_register_operand" "w")
5398 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
5399 VQSHRNBQ_N))
5400 ]
5401 "TARGET_HAVE_MVE"
5402 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5403 [(set_attr "type" "mve_move")
5404])
5405
5406;;
5407;; [vqshrntq_n_u, vqshrntq_n_s])
5408;;
5409(define_insn "mve_vqshrntq_n_<supf><mode>"
5410 [
5411 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5412 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5413 (match_operand:MVE_5 2 "s_register_operand" "w")
5414 (match_operand:SI 3 "mve_imm_8" "Rb")]
5415 VQSHRNTQ_N))
5416 ]
5417 "TARGET_HAVE_MVE"
5418 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5419 [(set_attr "type" "mve_move")
5420])
5421
5422;;
5423;; [vqshrunbq_n_s])
5424;;
5425(define_insn "mve_vqshrunbq_n_s<mode>"
5426 [
5427 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5428 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5429 (match_operand:MVE_5 2 "s_register_operand" "w")
5430 (match_operand:SI 3 "immediate_operand" "i")]
5431 VQSHRUNBQ_N_S))
5432 ]
5433 "TARGET_HAVE_MVE"
5434 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3"
5435 [(set_attr "type" "mve_move")
5436])
5437
5438;;
5439;; [vqshruntq_n_s])
5440;;
5441(define_insn "mve_vqshruntq_n_s<mode>"
5442 [
5443 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5444 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5445 (match_operand:MVE_5 2 "s_register_operand" "w")
5446 (match_operand:SI 3 "mve_imm_8" "Rb")]
5447 VQSHRUNTQ_N_S))
5448 ]
5449 "TARGET_HAVE_MVE"
5450 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5451 [(set_attr "type" "mve_move")
5452])
5453
5454;;
5455;; [vrev32q_m_f])
5456;;
5457(define_insn "mve_vrev32q_m_fv8hf"
5458 [
5459 (set (match_operand:V8HF 0 "s_register_operand" "=w")
5460 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5461 (match_operand:V8HF 2 "s_register_operand" "w")
5462 (match_operand:HI 3 "vpr_register_operand" "Up")]
5463 VREV32Q_M_F))
5464 ]
5465 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5466 "vpst\;vrev32t.16 %q0, %q2"
5467 [(set_attr "type" "mve_move")
5468 (set_attr "length""8")])
5469
5470;;
5471;; [vrev32q_m_s, vrev32q_m_u])
5472;;
5473(define_insn "mve_vrev32q_m_<supf><mode>"
5474 [
5475 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5476 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5477 (match_operand:MVE_3 2 "s_register_operand" "w")
5478 (match_operand:HI 3 "vpr_register_operand" "Up")]
5479 VREV32Q_M))
5480 ]
5481 "TARGET_HAVE_MVE"
5482 "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
5483 [(set_attr "type" "mve_move")
5484 (set_attr "length""8")])
5485
5486;;
5487;; [vrev64q_m_f])
5488;;
5489(define_insn "mve_vrev64q_m_f<mode>"
5490 [
5491 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5492 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5493 (match_operand:MVE_0 2 "s_register_operand" "w")
5494 (match_operand:HI 3 "vpr_register_operand" "Up")]
5495 VREV64Q_M_F))
5496 ]
5497 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5498 "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
5499 [(set_attr "type" "mve_move")
5500 (set_attr "length""8")])
5501
5502;;
5503;; [vrmlaldavhaxq_s])
5504;;
5505(define_insn "mve_vrmlaldavhaxq_sv4si"
5506 [
5507 (set (match_operand:DI 0 "s_register_operand" "=r")
5508 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5509 (match_operand:V4SI 2 "s_register_operand" "w")
5510 (match_operand:V4SI 3 "s_register_operand" "w")]
5511 VRMLALDAVHAXQ_S))
5512 ]
5513 "TARGET_HAVE_MVE"
5514 "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5515 [(set_attr "type" "mve_move")
5516])
5517
5518;;
5519;; [vrmlaldavhxq_p_s])
5520;;
5521(define_insn "mve_vrmlaldavhxq_p_sv4si"
5522 [
5523 (set (match_operand:DI 0 "s_register_operand" "=r")
5524 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5525 (match_operand:V4SI 2 "s_register_operand" "w")
5526 (match_operand:HI 3 "vpr_register_operand" "Up")]
5527 VRMLALDAVHXQ_P_S))
5528 ]
5529 "TARGET_HAVE_MVE"
5530 "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5531 [(set_attr "type" "mve_move")
5532 (set_attr "length""8")])
5533
5534;;
5535;; [vrmlsldavhaxq_s])
5536;;
5537(define_insn "mve_vrmlsldavhaxq_sv4si"
5538 [
5539 (set (match_operand:DI 0 "s_register_operand" "=r")
5540 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5541 (match_operand:V4SI 2 "s_register_operand" "w")
5542 (match_operand:V4SI 3 "s_register_operand" "w")]
5543 VRMLSLDAVHAXQ_S))
5544 ]
5545 "TARGET_HAVE_MVE"
5546 "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5547 [(set_attr "type" "mve_move")
5548])
5549
5550;;
5551;; [vrmlsldavhq_p_s])
5552;;
5553(define_insn "mve_vrmlsldavhq_p_sv4si"
5554 [
5555 (set (match_operand:DI 0 "s_register_operand" "=r")
5556 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5557 (match_operand:V4SI 2 "s_register_operand" "w")
5558 (match_operand:HI 3 "vpr_register_operand" "Up")]
5559 VRMLSLDAVHQ_P_S))
5560 ]
5561 "TARGET_HAVE_MVE"
5562 "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5563 [(set_attr "type" "mve_move")
5564 (set_attr "length""8")])
5565
5566;;
5567;; [vrmlsldavhxq_p_s])
5568;;
5569(define_insn "mve_vrmlsldavhxq_p_sv4si"
5570 [
5571 (set (match_operand:DI 0 "s_register_operand" "=r")
5572 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5573 (match_operand:V4SI 2 "s_register_operand" "w")
5574 (match_operand:HI 3 "vpr_register_operand" "Up")]
5575 VRMLSLDAVHXQ_P_S))
5576 ]
5577 "TARGET_HAVE_MVE"
5578 "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5579 [(set_attr "type" "mve_move")
5580 (set_attr "length""8")])
5581
5582;;
5583;; [vrndaq_m_f])
5584;;
5585(define_insn "mve_vrndaq_m_f<mode>"
5586 [
5587 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5588 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5589 (match_operand:MVE_0 2 "s_register_operand" "w")
5590 (match_operand:HI 3 "vpr_register_operand" "Up")]
5591 VRNDAQ_M_F))
5592 ]
5593 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5594 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5595 [(set_attr "type" "mve_move")
5596 (set_attr "length""8")])
5597
5598;;
5599;; [vrndmq_m_f])
5600;;
5601(define_insn "mve_vrndmq_m_f<mode>"
5602 [
5603 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5604 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5605 (match_operand:MVE_0 2 "s_register_operand" "w")
5606 (match_operand:HI 3 "vpr_register_operand" "Up")]
5607 VRNDMQ_M_F))
5608 ]
5609 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5610 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5611 [(set_attr "type" "mve_move")
5612 (set_attr "length""8")])
5613
5614;;
5615;; [vrndnq_m_f])
5616;;
5617(define_insn "mve_vrndnq_m_f<mode>"
5618 [
5619 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5620 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5621 (match_operand:MVE_0 2 "s_register_operand" "w")
5622 (match_operand:HI 3 "vpr_register_operand" "Up")]
5623 VRNDNQ_M_F))
5624 ]
5625 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5626 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5627 [(set_attr "type" "mve_move")
5628 (set_attr "length""8")])
5629
5630;;
5631;; [vrndpq_m_f])
5632;;
5633(define_insn "mve_vrndpq_m_f<mode>"
5634 [
5635 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5636 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5637 (match_operand:MVE_0 2 "s_register_operand" "w")
5638 (match_operand:HI 3 "vpr_register_operand" "Up")]
5639 VRNDPQ_M_F))
5640 ]
5641 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5642 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5643 [(set_attr "type" "mve_move")
5644 (set_attr "length""8")])
5645
5646;;
5647;; [vrndxq_m_f])
5648;;
5649(define_insn "mve_vrndxq_m_f<mode>"
5650 [
5651 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5652 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5653 (match_operand:MVE_0 2 "s_register_operand" "w")
5654 (match_operand:HI 3 "vpr_register_operand" "Up")]
5655 VRNDXQ_M_F))
5656 ]
5657 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5658 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5659 [(set_attr "type" "mve_move")
5660 (set_attr "length""8")])
5661
5662;;
5663;; [vrshrnbq_n_s, vrshrnbq_n_u])
5664;;
5665(define_insn "mve_vrshrnbq_n_<supf><mode>"
5666 [
5667 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5668 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5669 (match_operand:MVE_5 2 "s_register_operand" "w")
5670 (match_operand:SI 3 "mve_imm_8" "Rb")]
5671 VRSHRNBQ_N))
5672 ]
5673 "TARGET_HAVE_MVE"
5674 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5675 [(set_attr "type" "mve_move")
5676])
5677
5678;;
5679;; [vrshrntq_n_u, vrshrntq_n_s])
5680;;
5681(define_insn "mve_vrshrntq_n_<supf><mode>"
5682 [
5683 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5684 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5685 (match_operand:MVE_5 2 "s_register_operand" "w")
5686 (match_operand:SI 3 "mve_imm_8" "Rb")]
5687 VRSHRNTQ_N))
5688 ]
5689 "TARGET_HAVE_MVE"
5690 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
5691 [(set_attr "type" "mve_move")
5692])
5693
5694;;
5695;; [vshrnbq_n_u, vshrnbq_n_s])
5696;;
5697(define_insn "mve_vshrnbq_n_<supf><mode>"
5698 [
5699 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5700 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5701 (match_operand:MVE_5 2 "s_register_operand" "w")
5702 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5703 VSHRNBQ_N))
5704 ]
5705 "TARGET_HAVE_MVE"
5706 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5707 [(set_attr "type" "mve_move")
5708])
5709
5710;;
5711;; [vshrntq_n_s, vshrntq_n_u])
5712;;
5713(define_insn "mve_vshrntq_n_<supf><mode>"
5714 [
5715 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5716 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5717 (match_operand:MVE_5 2 "s_register_operand" "w")
5718 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5719 VSHRNTQ_N))
5720 ]
5721 "TARGET_HAVE_MVE"
db5db9d2 5722 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5723 [(set_attr "type" "mve_move")
5724])
5725
5726;;
5727;; [vcvtmq_m_s, vcvtmq_m_u])
5728;;
5729(define_insn "mve_vcvtmq_m_<supf><mode>"
5730 [
5731 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5732 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5733 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5734 (match_operand:HI 3 "vpr_register_operand" "Up")]
5735 VCVTMQ_M))
5736 ]
5737 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5738 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5739 [(set_attr "type" "mve_move")
5740 (set_attr "length""8")])
5741
5742;;
5743;; [vcvtpq_m_u, vcvtpq_m_s])
5744;;
5745(define_insn "mve_vcvtpq_m_<supf><mode>"
5746 [
5747 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5748 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5749 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5750 (match_operand:HI 3 "vpr_register_operand" "Up")]
5751 VCVTPQ_M))
5752 ]
5753 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5754 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5755 [(set_attr "type" "mve_move")
5756 (set_attr "length""8")])
5757
5758;;
5759;; [vcvtnq_m_s, vcvtnq_m_u])
5760;;
5761(define_insn "mve_vcvtnq_m_<supf><mode>"
5762 [
5763 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5764 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5765 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5766 (match_operand:HI 3 "vpr_register_operand" "Up")]
5767 VCVTNQ_M))
5768 ]
5769 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5770 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5771 [(set_attr "type" "mve_move")
5772 (set_attr "length""8")])
5773
5774;;
5775;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5776;;
5777(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5778 [
5779 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5780 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5781 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5782 (match_operand:SI 3 "mve_imm_16" "Rd")
5783 (match_operand:HI 4 "vpr_register_operand" "Up")]
5784 VCVTQ_M_N_FROM_F))
5785 ]
5786 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5787 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5788 [(set_attr "type" "mve_move")
5789 (set_attr "length""8")])
5790
5791;;
5792;; [vrev16q_m_u, vrev16q_m_s])
5793;;
5794(define_insn "mve_vrev16q_m_<supf>v16qi"
5795 [
5796 (set (match_operand:V16QI 0 "s_register_operand" "=w")
5797 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5798 (match_operand:V16QI 2 "s_register_operand" "w")
5799 (match_operand:HI 3 "vpr_register_operand" "Up")]
5800 VREV16Q_M))
5801 ]
5802 "TARGET_HAVE_MVE"
5803 "vpst\;vrev16t.8 %q0, %q2"
5804 [(set_attr "type" "mve_move")
5805 (set_attr "length""8")])
5806
5807;;
5808;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5809;;
5810(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5811 [
5812 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5813 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5814 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5815 (match_operand:HI 3 "vpr_register_operand" "Up")]
5816 VCVTQ_M_FROM_F))
5817 ]
5818 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5819 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5820 [(set_attr "type" "mve_move")
5821 (set_attr "length""8")])
5822
5823;;
5824;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5825;;
5826(define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5827 [
5828 (set (match_operand:DI 0 "s_register_operand" "=r")
5829 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5830 (match_operand:V4SI 2 "s_register_operand" "w")
5831 (match_operand:HI 3 "vpr_register_operand" "Up")]
5832 VRMLALDAVHQ_P))
5833 ]
5834 "TARGET_HAVE_MVE"
5835 "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5836 [(set_attr "type" "mve_move")
5837 (set_attr "length""8")])
5838
5839;;
5840;; [vrmlsldavhaq_s])
5841;;
5842(define_insn "mve_vrmlsldavhaq_sv4si"
5843 [
5844 (set (match_operand:DI 0 "s_register_operand" "=r")
5845 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5846 (match_operand:V4SI 2 "s_register_operand" "w")
5847 (match_operand:V4SI 3 "s_register_operand" "w")]
5848 VRMLSLDAVHAQ_S))
5849 ]
5850 "TARGET_HAVE_MVE"
5851 "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5852 [(set_attr "type" "mve_move")
5853])
db5db9d2
SP		 5854
5855;;
5856;; [vabavq_p_s, vabavq_p_u])
5857;;
5858(define_insn "mve_vabavq_p_<supf><mode>"
5859 [
5860 (set (match_operand:SI 0 "s_register_operand" "=r")
5861 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5862 (match_operand:MVE_2 2 "s_register_operand" "w")
5863 (match_operand:MVE_2 3 "s_register_operand" "w")
5864 (match_operand:HI 4 "vpr_register_operand" "Up")]
5865 VABAVQ_P))
5866 ]
5867 "TARGET_HAVE_MVE"
5868 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5869 [(set_attr "type" "mve_move")
5870])
5871
5872;;
5873;; [vqshluq_m_n_s])
5874;;
5875(define_insn "mve_vqshluq_m_n_s<mode>"
5876 [
5877 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5878 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5879 (match_operand:MVE_2 2 "s_register_operand" "w")
5880 (match_operand:SI 3 "mve_imm_7" "Ra")
5881 (match_operand:HI 4 "vpr_register_operand" "Up")]
5882 VQSHLUQ_M_N_S))
5883 ]
5884 "TARGET_HAVE_MVE"
5885 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5886 [(set_attr "type" "mve_move")])
5887
5888;;
5889;; [vshlq_m_s, vshlq_m_u])
5890;;
5891(define_insn "mve_vshlq_m_<supf><mode>"
5892 [
5893 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5894 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5895 (match_operand:MVE_2 2 "s_register_operand" "w")
5896 (match_operand:MVE_2 3 "s_register_operand" "w")
5897 (match_operand:HI 4 "vpr_register_operand" "Up")]
5898 VSHLQ_M))
5899 ]
5900 "TARGET_HAVE_MVE"
5901 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5902 [(set_attr "type" "mve_move")])
5903
5904;;
5905;; [vsriq_m_n_s, vsriq_m_n_u])
5906;;
5907(define_insn "mve_vsriq_m_n_<supf><mode>"
5908 [
5909 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5910 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5911 (match_operand:MVE_2 2 "s_register_operand" "w")
5912 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
5913 (match_operand:HI 4 "vpr_register_operand" "Up")]
5914 VSRIQ_M_N))
5915 ]
5916 "TARGET_HAVE_MVE"
5917 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
5918 [(set_attr "type" "mve_move")])
5919
5920;;
5921;; [vsubq_m_u, vsubq_m_s])
5922;;
5923(define_insn "mve_vsubq_m_<supf><mode>"
5924 [
5925 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5926 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5927 (match_operand:MVE_2 2 "s_register_operand" "w")
5928 (match_operand:MVE_2 3 "s_register_operand" "w")
5929 (match_operand:HI 4 "vpr_register_operand" "Up")]
5930 VSUBQ_M))
5931 ]
5932 "TARGET_HAVE_MVE"
5933 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
5934 [(set_attr "type" "mve_move")])
5935
5936;;
5937;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
5938;;
5939(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
5940 [
5941 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5942 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5943 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5944 (match_operand:SI 3 "mve_imm_16" "Rd")
5945 (match_operand:HI 4 "vpr_register_operand" "Up")]
5946 VCVTQ_M_N_TO_F))
5947 ]
5948 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5949 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5950 [(set_attr "type" "mve_move")
5951 (set_attr "length""8")])
8eb3b6b9
SP		 5952;;
5953;; [vabdq_m_s, vabdq_m_u])
5954;;
5955(define_insn "mve_vabdq_m_<supf><mode>"
5956 [
5957 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5958 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5959 (match_operand:MVE_2 2 "s_register_operand" "w")
5960 (match_operand:MVE_2 3 "s_register_operand" "w")
5961 (match_operand:HI 4 "vpr_register_operand" "Up")]
5962 VABDQ_M))
5963 ]
5964 "TARGET_HAVE_MVE"
5965 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5966 [(set_attr "type" "mve_move")
5967 (set_attr "length""8")])
5968
5969;;
5970;; [vaddq_m_n_s, vaddq_m_n_u])
5971;;
5972(define_insn "mve_vaddq_m_n_<supf><mode>"
5973 [
5974 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5975 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5976 (match_operand:MVE_2 2 "s_register_operand" "w")
5977 (match_operand:<V_elem> 3 "s_register_operand" "r")
5978 (match_operand:HI 4 "vpr_register_operand" "Up")]
5979 VADDQ_M_N))
5980 ]
5981 "TARGET_HAVE_MVE"
5982 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
5983 [(set_attr "type" "mve_move")
5984 (set_attr "length""8")])
5985
5986;;
5987;; [vaddq_m_u, vaddq_m_s])
5988;;
5989(define_insn "mve_vaddq_m_<supf><mode>"
5990 [
5991 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5992 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5993 (match_operand:MVE_2 2 "s_register_operand" "w")
5994 (match_operand:MVE_2 3 "s_register_operand" "w")
5995 (match_operand:HI 4 "vpr_register_operand" "Up")]
5996 VADDQ_M))
5997 ]
5998 "TARGET_HAVE_MVE"
5999 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
6000 [(set_attr "type" "mve_move")
6001 (set_attr "length""8")])
6002
6003;;
6004;; [vandq_m_u, vandq_m_s])
6005;;
6006(define_insn "mve_vandq_m_<supf><mode>"
6007 [
6008 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6009 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6010 (match_operand:MVE_2 2 "s_register_operand" "w")
6011 (match_operand:MVE_2 3 "s_register_operand" "w")
6012 (match_operand:HI 4 "vpr_register_operand" "Up")]
6013 VANDQ_M))
6014 ]
6015 "TARGET_HAVE_MVE"
6016 "vpst\;vandt %q0, %q2, %q3"
6017 [(set_attr "type" "mve_move")
6018 (set_attr "length""8")])
6019
6020;;
6021;; [vbicq_m_u, vbicq_m_s])
6022;;
6023(define_insn "mve_vbicq_m_<supf><mode>"
6024 [
6025 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6026 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6027 (match_operand:MVE_2 2 "s_register_operand" "w")
6028 (match_operand:MVE_2 3 "s_register_operand" "w")
6029 (match_operand:HI 4 "vpr_register_operand" "Up")]
6030 VBICQ_M))
6031 ]
6032 "TARGET_HAVE_MVE"
6033 "vpst\;vbict %q0, %q2, %q3"
6034 [(set_attr "type" "mve_move")
6035 (set_attr "length""8")])
6036
6037;;
6038;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
6039;;
6040(define_insn "mve_vbrsrq_m_n_<supf><mode>"
6041 [
6042 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6043 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6044 (match_operand:MVE_2 2 "s_register_operand" "w")
6045 (match_operand:SI 3 "s_register_operand" "r")
6046 (match_operand:HI 4 "vpr_register_operand" "Up")]
6047 VBRSRQ_M_N))
6048 ]
6049 "TARGET_HAVE_MVE"
6050 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
6051 [(set_attr "type" "mve_move")
6052 (set_attr "length""8")])
6053
6054;;
6055;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
6056;;
6057(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
6058 [
6059 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6060 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6061 (match_operand:MVE_2 2 "s_register_operand" "w")
6062 (match_operand:MVE_2 3 "s_register_operand" "w")
6063 (match_operand:HI 4 "vpr_register_operand" "Up")]
6064 VCADDQ_ROT270_M))
6065 ]
6066 "TARGET_HAVE_MVE"
6067 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
6068 [(set_attr "type" "mve_move")
6069 (set_attr "length""8")])
6070
6071;;
6072;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
6073;;
6074(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
6075 [
6076 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6077 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6078 (match_operand:MVE_2 2 "s_register_operand" "w")
6079 (match_operand:MVE_2 3 "s_register_operand" "w")
6080 (match_operand:HI 4 "vpr_register_operand" "Up")]
6081 VCADDQ_ROT90_M))
6082 ]
6083 "TARGET_HAVE_MVE"
6084 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
6085 [(set_attr "type" "mve_move")
6086 (set_attr "length""8")])
6087
6088;;
6089;; [veorq_m_s, veorq_m_u])
6090;;
6091(define_insn "mve_veorq_m_<supf><mode>"
6092 [
6093 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6094 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6095 (match_operand:MVE_2 2 "s_register_operand" "w")
6096 (match_operand:MVE_2 3 "s_register_operand" "w")
6097 (match_operand:HI 4 "vpr_register_operand" "Up")]
6098 VEORQ_M))
6099 ]
6100 "TARGET_HAVE_MVE"
6101 "vpst\;veort %q0, %q2, %q3"
6102 [(set_attr "type" "mve_move")
6103 (set_attr "length""8")])
6104
6105;;
6106;; [vhaddq_m_n_s, vhaddq_m_n_u])
6107;;
6108(define_insn "mve_vhaddq_m_n_<supf><mode>"
6109 [
6110 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6111 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6112 (match_operand:MVE_2 2 "s_register_operand" "w")
6113 (match_operand:<V_elem> 3 "s_register_operand" "r")
6114 (match_operand:HI 4 "vpr_register_operand" "Up")]
6115 VHADDQ_M_N))
6116 ]
6117 "TARGET_HAVE_MVE"
6118 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6119 [(set_attr "type" "mve_move")
6120 (set_attr "length""8")])
6121
6122;;
6123;; [vhaddq_m_s, vhaddq_m_u])
6124;;
6125(define_insn "mve_vhaddq_m_<supf><mode>"
6126 [
6127 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6128 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6129 (match_operand:MVE_2 2 "s_register_operand" "w")
6130 (match_operand:MVE_2 3 "s_register_operand" "w")
6131 (match_operand:HI 4 "vpr_register_operand" "Up")]
6132 VHADDQ_M))
6133 ]
6134 "TARGET_HAVE_MVE"
6135 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6136 [(set_attr "type" "mve_move")
6137 (set_attr "length""8")])
6138
6139;;
6140;; [vhsubq_m_n_s, vhsubq_m_n_u])
6141;;
6142(define_insn "mve_vhsubq_m_n_<supf><mode>"
6143 [
6144 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6145 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6146 (match_operand:MVE_2 2 "s_register_operand" "w")
6147 (match_operand:<V_elem> 3 "s_register_operand" "r")
6148 (match_operand:HI 4 "vpr_register_operand" "Up")]
6149 VHSUBQ_M_N))
6150 ]
6151 "TARGET_HAVE_MVE"
6152 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6153 [(set_attr "type" "mve_move")
6154 (set_attr "length""8")])
6155
6156;;
6157;; [vhsubq_m_s, vhsubq_m_u])
6158;;
6159(define_insn "mve_vhsubq_m_<supf><mode>"
6160 [
6161 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6162 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6163 (match_operand:MVE_2 2 "s_register_operand" "w")
6164 (match_operand:MVE_2 3 "s_register_operand" "w")
6165 (match_operand:HI 4 "vpr_register_operand" "Up")]
6166 VHSUBQ_M))
6167 ]
6168 "TARGET_HAVE_MVE"
6169 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6170 [(set_attr "type" "mve_move")
6171 (set_attr "length""8")])
6172
6173;;
6174;; [vmaxq_m_s, vmaxq_m_u])
6175;;
6176(define_insn "mve_vmaxq_m_<supf><mode>"
6177 [
6178 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6179 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6180 (match_operand:MVE_2 2 "s_register_operand" "w")
6181 (match_operand:MVE_2 3 "s_register_operand" "w")
6182 (match_operand:HI 4 "vpr_register_operand" "Up")]
6183 VMAXQ_M))
6184 ]
6185 "TARGET_HAVE_MVE"
6186 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6187 [(set_attr "type" "mve_move")
6188 (set_attr "length""8")])
6189
6190;;
6191;; [vminq_m_s, vminq_m_u])
6192;;
6193(define_insn "mve_vminq_m_<supf><mode>"
6194 [
6195 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6196 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6197 (match_operand:MVE_2 2 "s_register_operand" "w")
6198 (match_operand:MVE_2 3 "s_register_operand" "w")
6199 (match_operand:HI 4 "vpr_register_operand" "Up")]
6200 VMINQ_M))
6201 ]
6202 "TARGET_HAVE_MVE"
6203 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6204 [(set_attr "type" "mve_move")
6205 (set_attr "length""8")])
6206
6207;;
6208;; [vmladavaq_p_u, vmladavaq_p_s])
6209;;
6210(define_insn "mve_vmladavaq_p_<supf><mode>"
6211 [
6212 (set (match_operand:SI 0 "s_register_operand" "=e")
6213 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6214 (match_operand:MVE_2 2 "s_register_operand" "w")
6215 (match_operand:MVE_2 3 "s_register_operand" "w")
6216 (match_operand:HI 4 "vpr_register_operand" "Up")]
6217 VMLADAVAQ_P))
6218 ]
6219 "TARGET_HAVE_MVE"
6220 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
6221 [(set_attr "type" "mve_move")
6222 (set_attr "length""8")])
6223
6224;;
6225;; [vmlaq_m_n_s, vmlaq_m_n_u])
6226;;
6227(define_insn "mve_vmlaq_m_n_<supf><mode>"
6228 [
6229 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6230 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6231 (match_operand:MVE_2 2 "s_register_operand" "w")
6232 (match_operand:<V_elem> 3 "s_register_operand" "r")
6233 (match_operand:HI 4 "vpr_register_operand" "Up")]
6234 VMLAQ_M_N))
6235 ]
6236 "TARGET_HAVE_MVE"
6237 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
6238 [(set_attr "type" "mve_move")
6239 (set_attr "length""8")])
6240
6241;;
6242;; [vmlasq_m_n_u, vmlasq_m_n_s])
6243;;
6244(define_insn "mve_vmlasq_m_n_<supf><mode>"
6245 [
6246 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6247 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6248 (match_operand:MVE_2 2 "s_register_operand" "w")
6249 (match_operand:<V_elem> 3 "s_register_operand" "r")
6250 (match_operand:HI 4 "vpr_register_operand" "Up")]
6251 VMLASQ_M_N))
6252 ]
6253 "TARGET_HAVE_MVE"
6254 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
6255 [(set_attr "type" "mve_move")
6256 (set_attr "length""8")])
6257
6258;;
6259;; [vmulhq_m_s, vmulhq_m_u])
6260;;
6261(define_insn "mve_vmulhq_m_<supf><mode>"
6262 [
6263 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6264 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6265 (match_operand:MVE_2 2 "s_register_operand" "w")
6266 (match_operand:MVE_2 3 "s_register_operand" "w")
6267 (match_operand:HI 4 "vpr_register_operand" "Up")]
6268 VMULHQ_M))
6269 ]
6270 "TARGET_HAVE_MVE"
6271 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6272 [(set_attr "type" "mve_move")
6273 (set_attr "length""8")])
6274
6275;;
6276;; [vmullbq_int_m_u, vmullbq_int_m_s])
6277;;
6278(define_insn "mve_vmullbq_int_m_<supf><mode>"
6279 [
6280 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6281 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6282 (match_operand:MVE_2 2 "s_register_operand" "w")
6283 (match_operand:MVE_2 3 "s_register_operand" "w")
6284 (match_operand:HI 4 "vpr_register_operand" "Up")]
6285 VMULLBQ_INT_M))
6286 ]
6287 "TARGET_HAVE_MVE"
6288 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6289 [(set_attr "type" "mve_move")
6290 (set_attr "length""8")])
6291
6292;;
6293;; [vmulltq_int_m_s, vmulltq_int_m_u])
6294;;
6295(define_insn "mve_vmulltq_int_m_<supf><mode>"
6296 [
6297 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6298 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6299 (match_operand:MVE_2 2 "s_register_operand" "w")
6300 (match_operand:MVE_2 3 "s_register_operand" "w")
6301 (match_operand:HI 4 "vpr_register_operand" "Up")]
6302 VMULLTQ_INT_M))
6303 ]
6304 "TARGET_HAVE_MVE"
6305 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6306 [(set_attr "type" "mve_move")
6307 (set_attr "length""8")])
6308
6309;;
6310;; [vmulq_m_n_u, vmulq_m_n_s])
6311;;
6312(define_insn "mve_vmulq_m_n_<supf><mode>"
6313 [
6314 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6315 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6316 (match_operand:MVE_2 2 "s_register_operand" "w")
6317 (match_operand:<V_elem> 3 "s_register_operand" "r")
6318 (match_operand:HI 4 "vpr_register_operand" "Up")]
6319 VMULQ_M_N))
6320 ]
6321 "TARGET_HAVE_MVE"
6322 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
6323 [(set_attr "type" "mve_move")
6324 (set_attr "length""8")])
6325
6326;;
6327;; [vmulq_m_s, vmulq_m_u])
6328;;
6329(define_insn "mve_vmulq_m_<supf><mode>"
6330 [
6331 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6332 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6333 (match_operand:MVE_2 2 "s_register_operand" "w")
6334 (match_operand:MVE_2 3 "s_register_operand" "w")
6335 (match_operand:HI 4 "vpr_register_operand" "Up")]
6336 VMULQ_M))
6337 ]
6338 "TARGET_HAVE_MVE"
6339 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
6340 [(set_attr "type" "mve_move")
6341 (set_attr "length""8")])
6342
6343;;
6344;; [vornq_m_u, vornq_m_s])
6345;;
6346(define_insn "mve_vornq_m_<supf><mode>"
6347 [
6348 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6349 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6350 (match_operand:MVE_2 2 "s_register_operand" "w")
6351 (match_operand:MVE_2 3 "s_register_operand" "w")
6352 (match_operand:HI 4 "vpr_register_operand" "Up")]
6353 VORNQ_M))
6354 ]
6355 "TARGET_HAVE_MVE"
6356 "vpst\;vornt %q0, %q2, %q3"
6357 [(set_attr "type" "mve_move")
6358 (set_attr "length""8")])
6359
6360;;
6361;; [vorrq_m_s, vorrq_m_u])
6362;;
6363(define_insn "mve_vorrq_m_<supf><mode>"
6364 [
6365 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6366 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6367 (match_operand:MVE_2 2 "s_register_operand" "w")
6368 (match_operand:MVE_2 3 "s_register_operand" "w")
6369 (match_operand:HI 4 "vpr_register_operand" "Up")]
6370 VORRQ_M))
6371 ]
6372 "TARGET_HAVE_MVE"
6373 "vpst\;vorrt %q0, %q2, %q3"
6374 [(set_attr "type" "mve_move")
6375 (set_attr "length""8")])
6376
6377;;
6378;; [vqaddq_m_n_u, vqaddq_m_n_s])
6379;;
6380(define_insn "mve_vqaddq_m_n_<supf><mode>"
6381 [
6382 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6383 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6384 (match_operand:MVE_2 2 "s_register_operand" "w")
6385 (match_operand:<V_elem> 3 "s_register_operand" "r")
6386 (match_operand:HI 4 "vpr_register_operand" "Up")]
6387 VQADDQ_M_N))
6388 ]
6389 "TARGET_HAVE_MVE"
6390 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6391 [(set_attr "type" "mve_move")
6392 (set_attr "length""8")])
6393
6394;;
6395;; [vqaddq_m_u, vqaddq_m_s])
6396;;
6397(define_insn "mve_vqaddq_m_<supf><mode>"
6398 [
6399 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6400 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6401 (match_operand:MVE_2 2 "s_register_operand" "w")
6402 (match_operand:MVE_2 3 "s_register_operand" "w")
6403 (match_operand:HI 4 "vpr_register_operand" "Up")]
6404 VQADDQ_M))
6405 ]
6406 "TARGET_HAVE_MVE"
6407 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6408 [(set_attr "type" "mve_move")
6409 (set_attr "length""8")])
6410
6411;;
6412;; [vqdmlahq_m_n_s])
6413;;
6414(define_insn "mve_vqdmlahq_m_n_s<mode>"
6415 [
6416 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6417 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6418 (match_operand:MVE_2 2 "s_register_operand" "w")
6419 (match_operand:<V_elem> 3 "s_register_operand" "r")
6420 (match_operand:HI 4 "vpr_register_operand" "Up")]
6421 VQDMLAHQ_M_N_S))
6422 ]
6423 "TARGET_HAVE_MVE"
6424 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6425 [(set_attr "type" "mve_move")
6426 (set_attr "length""8")])
6427
6428;;
6429;; [vqrdmlahq_m_n_s])
6430;;
6431(define_insn "mve_vqrdmlahq_m_n_s<mode>"
6432 [
6433 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6434 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6435 (match_operand:MVE_2 2 "s_register_operand" "w")
6436 (match_operand:<V_elem> 3 "s_register_operand" "r")
6437 (match_operand:HI 4 "vpr_register_operand" "Up")]
6438 VQRDMLAHQ_M_N_S))
6439 ]
6440 "TARGET_HAVE_MVE"
6441 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6442 [(set_attr "type" "mve_move")
6443 (set_attr "length""8")])
6444
6445;;
6446;; [vqrdmlashq_m_n_s])
6447;;
6448(define_insn "mve_vqrdmlashq_m_n_s<mode>"
6449 [
6450 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6451 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6452 (match_operand:MVE_2 2 "s_register_operand" "w")
6453 (match_operand:<V_elem> 3 "s_register_operand" "r")
6454 (match_operand:HI 4 "vpr_register_operand" "Up")]
6455 VQRDMLASHQ_M_N_S))
6456 ]
6457 "TARGET_HAVE_MVE"
6458 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6459 [(set_attr "type" "mve_move")
6460 (set_attr "length""8")])
6461
6462;;
6463;; [vqrshlq_m_u, vqrshlq_m_s])
6464;;
6465(define_insn "mve_vqrshlq_m_<supf><mode>"
6466 [
6467 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6468 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6469 (match_operand:MVE_2 2 "s_register_operand" "w")
6470 (match_operand:MVE_2 3 "s_register_operand" "w")
6471 (match_operand:HI 4 "vpr_register_operand" "Up")]
6472 VQRSHLQ_M))
6473 ]
6474 "TARGET_HAVE_MVE"
6475 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6476 [(set_attr "type" "mve_move")
6477 (set_attr "length""8")])
6478
6479;;
6480;; [vqshlq_m_n_s, vqshlq_m_n_u])
6481;;
6482(define_insn "mve_vqshlq_m_n_<supf><mode>"
6483 [
6484 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6485 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6486 (match_operand:MVE_2 2 "s_register_operand" "w")
6487 (match_operand:SI 3 "immediate_operand" "i")
6488 (match_operand:HI 4 "vpr_register_operand" "Up")]
6489 VQSHLQ_M_N))
6490 ]
6491 "TARGET_HAVE_MVE"
6492 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6493 [(set_attr "type" "mve_move")
6494 (set_attr "length""8")])
6495
6496;;
6497;; [vqshlq_m_u, vqshlq_m_s])
6498;;
6499(define_insn "mve_vqshlq_m_<supf><mode>"
6500 [
6501 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6502 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6503 (match_operand:MVE_2 2 "s_register_operand" "w")
6504 (match_operand:MVE_2 3 "s_register_operand" "w")
6505 (match_operand:HI 4 "vpr_register_operand" "Up")]
6506 VQSHLQ_M))
6507 ]
6508 "TARGET_HAVE_MVE"
6509 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6510 [(set_attr "type" "mve_move")
6511 (set_attr "length""8")])
6512
6513;;
6514;; [vqsubq_m_n_u, vqsubq_m_n_s])
6515;;
6516(define_insn "mve_vqsubq_m_n_<supf><mode>"
6517 [
6518 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6519 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6520 (match_operand:MVE_2 2 "s_register_operand" "w")
6521 (match_operand:<V_elem> 3 "s_register_operand" "r")
6522 (match_operand:HI 4 "vpr_register_operand" "Up")]
6523 VQSUBQ_M_N))
6524 ]
6525 "TARGET_HAVE_MVE"
6526 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6527 [(set_attr "type" "mve_move")
6528 (set_attr "length""8")])
6529
6530;;
6531;; [vqsubq_m_u, vqsubq_m_s])
6532;;
6533(define_insn "mve_vqsubq_m_<supf><mode>"
6534 [
6535 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6536 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6537 (match_operand:MVE_2 2 "s_register_operand" "w")
6538 (match_operand:MVE_2 3 "s_register_operand" "w")
6539 (match_operand:HI 4 "vpr_register_operand" "Up")]
6540 VQSUBQ_M))
6541 ]
6542 "TARGET_HAVE_MVE"
6543 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6544 [(set_attr "type" "mve_move")
6545 (set_attr "length""8")])
6546
6547;;
6548;; [vrhaddq_m_u, vrhaddq_m_s])
6549;;
6550(define_insn "mve_vrhaddq_m_<supf><mode>"
6551 [
6552 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6553 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6554 (match_operand:MVE_2 2 "s_register_operand" "w")
6555 (match_operand:MVE_2 3 "s_register_operand" "w")
6556 (match_operand:HI 4 "vpr_register_operand" "Up")]
6557 VRHADDQ_M))
6558 ]
6559 "TARGET_HAVE_MVE"
6560 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6561 [(set_attr "type" "mve_move")
6562 (set_attr "length""8")])
6563
6564;;
6565;; [vrmulhq_m_u, vrmulhq_m_s])
6566;;
6567(define_insn "mve_vrmulhq_m_<supf><mode>"
6568 [
6569 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6570 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6571 (match_operand:MVE_2 2 "s_register_operand" "w")
6572 (match_operand:MVE_2 3 "s_register_operand" "w")
6573 (match_operand:HI 4 "vpr_register_operand" "Up")]
6574 VRMULHQ_M))
6575 ]
6576 "TARGET_HAVE_MVE"
6577 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6578 [(set_attr "type" "mve_move")
6579 (set_attr "length""8")])
6580
6581;;
6582;; [vrshlq_m_s, vrshlq_m_u])
6583;;
6584(define_insn "mve_vrshlq_m_<supf><mode>"
6585 [
6586 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6587 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6588 (match_operand:MVE_2 2 "s_register_operand" "w")
6589 (match_operand:MVE_2 3 "s_register_operand" "w")
6590 (match_operand:HI 4 "vpr_register_operand" "Up")]
6591 VRSHLQ_M))
6592 ]
6593 "TARGET_HAVE_MVE"
6594 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6595 [(set_attr "type" "mve_move")
6596 (set_attr "length""8")])
6597
6598;;
6599;; [vrshrq_m_n_s, vrshrq_m_n_u])
6600;;
6601(define_insn "mve_vrshrq_m_n_<supf><mode>"
6602 [
6603 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6604 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6605 (match_operand:MVE_2 2 "s_register_operand" "w")
6606 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6607 (match_operand:HI 4 "vpr_register_operand" "Up")]
6608 VRSHRQ_M_N))
6609 ]
6610 "TARGET_HAVE_MVE"
6611 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6612 [(set_attr "type" "mve_move")
6613 (set_attr "length""8")])
6614
6615;;
6616;; [vshlq_m_n_s, vshlq_m_n_u])
6617;;
6618(define_insn "mve_vshlq_m_n_<supf><mode>"
6619 [
6620 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6621 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6622 (match_operand:MVE_2 2 "s_register_operand" "w")
6623 (match_operand:SI 3 "immediate_operand" "i")
6624 (match_operand:HI 4 "vpr_register_operand" "Up")]
6625 VSHLQ_M_N))
6626 ]
6627 "TARGET_HAVE_MVE"
6628 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6629 [(set_attr "type" "mve_move")
6630 (set_attr "length""8")])
6631
6632;;
6633;; [vshrq_m_n_s, vshrq_m_n_u])
6634;;
6635(define_insn "mve_vshrq_m_n_<supf><mode>"
6636 [
6637 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6638 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6639 (match_operand:MVE_2 2 "s_register_operand" "w")
6640 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6641 (match_operand:HI 4 "vpr_register_operand" "Up")]
6642 VSHRQ_M_N))
6643 ]
6644 "TARGET_HAVE_MVE"
6645 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6646 [(set_attr "type" "mve_move")
6647 (set_attr "length""8")])
6648
6649;;
6650;; [vsliq_m_n_u, vsliq_m_n_s])
6651;;
6652(define_insn "mve_vsliq_m_n_<supf><mode>"
6653 [
6654 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6655 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6656 (match_operand:MVE_2 2 "s_register_operand" "w")
6657 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
6658 (match_operand:HI 4 "vpr_register_operand" "Up")]
6659 VSLIQ_M_N))
6660 ]
6661 "TARGET_HAVE_MVE"
6662 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
6663 [(set_attr "type" "mve_move")
6664 (set_attr "length""8")])
6665
6666;;
6667;; [vsubq_m_n_s, vsubq_m_n_u])
6668;;
6669(define_insn "mve_vsubq_m_n_<supf><mode>"
6670 [
6671 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6672 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6673 (match_operand:MVE_2 2 "s_register_operand" "w")
6674 (match_operand:<V_elem> 3 "s_register_operand" "r")
6675 (match_operand:HI 4 "vpr_register_operand" "Up")]
6676 VSUBQ_M_N))
6677 ]
6678 "TARGET_HAVE_MVE"
6679 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
6680 [(set_attr "type" "mve_move")
6681 (set_attr "length""8")])
6682
6683;;
6684;; [vhcaddq_rot270_m_s])
6685;;
6686(define_insn "mve_vhcaddq_rot270_m_s<mode>"
6687 [
6688 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6689 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6690 (match_operand:MVE_2 2 "s_register_operand" "w")
6691 (match_operand:MVE_2 3 "s_register_operand" "w")
6692 (match_operand:HI 4 "vpr_register_operand" "Up")]
6693 VHCADDQ_ROT270_M_S))
6694 ]
6695 "TARGET_HAVE_MVE"
6696 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
6697 [(set_attr "type" "mve_move")
6698 (set_attr "length""8")])
6699
6700;;
6701;; [vhcaddq_rot90_m_s])
6702;;
6703(define_insn "mve_vhcaddq_rot90_m_s<mode>"
6704 [
6705 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6706 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6707 (match_operand:MVE_2 2 "s_register_operand" "w")
6708 (match_operand:MVE_2 3 "s_register_operand" "w")
6709 (match_operand:HI 4 "vpr_register_operand" "Up")]
6710 VHCADDQ_ROT90_M_S))
6711 ]
6712 "TARGET_HAVE_MVE"
6713 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
6714 [(set_attr "type" "mve_move")
6715 (set_attr "length""8")])
6716
6717;;
6718;; [vmladavaxq_p_s])
6719;;
6720(define_insn "mve_vmladavaxq_p_s<mode>"
6721 [
6722 (set (match_operand:SI 0 "s_register_operand" "=e")
6723 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6724 (match_operand:MVE_2 2 "s_register_operand" "w")
6725 (match_operand:MVE_2 3 "s_register_operand" "w")
6726 (match_operand:HI 4 "vpr_register_operand" "Up")]
6727 VMLADAVAXQ_P_S))
6728 ]
6729 "TARGET_HAVE_MVE"
6730 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6731 [(set_attr "type" "mve_move")
6732 (set_attr "length""8")])
6733
6734;;
6735;; [vmlsdavaq_p_s])
6736;;
6737(define_insn "mve_vmlsdavaq_p_s<mode>"
6738 [
6739 (set (match_operand:SI 0 "s_register_operand" "=e")
6740 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6741 (match_operand:MVE_2 2 "s_register_operand" "w")
6742 (match_operand:MVE_2 3 "s_register_operand" "w")
6743 (match_operand:HI 4 "vpr_register_operand" "Up")]
6744 VMLSDAVAQ_P_S))
6745 ]
6746 "TARGET_HAVE_MVE"
6747 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
6748 [(set_attr "type" "mve_move")
6749 (set_attr "length""8")])
6750
6751;;
6752;; [vmlsdavaxq_p_s])
6753;;
6754(define_insn "mve_vmlsdavaxq_p_s<mode>"
6755 [
6756 (set (match_operand:SI 0 "s_register_operand" "=e")
6757 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6758 (match_operand:MVE_2 2 "s_register_operand" "w")
6759 (match_operand:MVE_2 3 "s_register_operand" "w")
6760 (match_operand:HI 4 "vpr_register_operand" "Up")]
6761 VMLSDAVAXQ_P_S))
6762 ]
6763 "TARGET_HAVE_MVE"
6764 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6765 [(set_attr "type" "mve_move")
6766 (set_attr "length""8")])
6767
6768;;
6769;; [vqdmladhq_m_s])
6770;;
6771(define_insn "mve_vqdmladhq_m_s<mode>"
6772 [
6773 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6774 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6775 (match_operand:MVE_2 2 "s_register_operand" "w")
6776 (match_operand:MVE_2 3 "s_register_operand" "w")
6777 (match_operand:HI 4 "vpr_register_operand" "Up")]
6778 VQDMLADHQ_M_S))
6779 ]
6780 "TARGET_HAVE_MVE"
6781 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6782 [(set_attr "type" "mve_move")
6783 (set_attr "length""8")])
6784
6785;;
6786;; [vqdmladhxq_m_s])
6787;;
6788(define_insn "mve_vqdmladhxq_m_s<mode>"
6789 [
6790 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6791 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6792 (match_operand:MVE_2 2 "s_register_operand" "w")
6793 (match_operand:MVE_2 3 "s_register_operand" "w")
6794 (match_operand:HI 4 "vpr_register_operand" "Up")]
6795 VQDMLADHXQ_M_S))
6796 ]
6797 "TARGET_HAVE_MVE"
6798 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6799 [(set_attr "type" "mve_move")
6800 (set_attr "length""8")])
6801
6802;;
6803;; [vqdmlsdhq_m_s])
6804;;
6805(define_insn "mve_vqdmlsdhq_m_s<mode>"
6806 [
6807 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6808 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6809 (match_operand:MVE_2 2 "s_register_operand" "w")
6810 (match_operand:MVE_2 3 "s_register_operand" "w")
6811 (match_operand:HI 4 "vpr_register_operand" "Up")]
6812 VQDMLSDHQ_M_S))
6813 ]
6814 "TARGET_HAVE_MVE"
6815 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6816 [(set_attr "type" "mve_move")
6817 (set_attr "length""8")])
6818
6819;;
6820;; [vqdmlsdhxq_m_s])
6821;;
6822(define_insn "mve_vqdmlsdhxq_m_s<mode>"
6823 [
6824 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6825 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6826 (match_operand:MVE_2 2 "s_register_operand" "w")
6827 (match_operand:MVE_2 3 "s_register_operand" "w")
6828 (match_operand:HI 4 "vpr_register_operand" "Up")]
6829 VQDMLSDHXQ_M_S))
6830 ]
6831 "TARGET_HAVE_MVE"
6832 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6833 [(set_attr "type" "mve_move")
6834 (set_attr "length""8")])
6835
6836;;
6837;; [vqdmulhq_m_n_s])
6838;;
6839(define_insn "mve_vqdmulhq_m_n_s<mode>"
6840 [
6841 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6842 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6843 (match_operand:MVE_2 2 "s_register_operand" "w")
6844 (match_operand:<V_elem> 3 "s_register_operand" "r")
6845 (match_operand:HI 4 "vpr_register_operand" "Up")]
6846 VQDMULHQ_M_N_S))
6847 ]
6848 "TARGET_HAVE_MVE"
6849 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6850 [(set_attr "type" "mve_move")
6851 (set_attr "length""8")])
6852
6853;;
6854;; [vqdmulhq_m_s])
6855;;
6856(define_insn "mve_vqdmulhq_m_s<mode>"
6857 [
6858 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6859 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6860 (match_operand:MVE_2 2 "s_register_operand" "w")
6861 (match_operand:MVE_2 3 "s_register_operand" "w")
6862 (match_operand:HI 4 "vpr_register_operand" "Up")]
6863 VQDMULHQ_M_S))
6864 ]
6865 "TARGET_HAVE_MVE"
6866 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6867 [(set_attr "type" "mve_move")
6868 (set_attr "length""8")])
6869
6870;;
6871;; [vqrdmladhq_m_s])
6872;;
6873(define_insn "mve_vqrdmladhq_m_s<mode>"
6874 [
6875 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6876 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6877 (match_operand:MVE_2 2 "s_register_operand" "w")
6878 (match_operand:MVE_2 3 "s_register_operand" "w")
6879 (match_operand:HI 4 "vpr_register_operand" "Up")]
6880 VQRDMLADHQ_M_S))
6881 ]
6882 "TARGET_HAVE_MVE"
6883 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6884 [(set_attr "type" "mve_move")
6885 (set_attr "length""8")])
6886
6887;;
6888;; [vqrdmladhxq_m_s])
6889;;
6890(define_insn "mve_vqrdmladhxq_m_s<mode>"
6891 [
6892 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6893 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6894 (match_operand:MVE_2 2 "s_register_operand" "w")
6895 (match_operand:MVE_2 3 "s_register_operand" "w")
6896 (match_operand:HI 4 "vpr_register_operand" "Up")]
6897 VQRDMLADHXQ_M_S))
6898 ]
6899 "TARGET_HAVE_MVE"
6900 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6901 [(set_attr "type" "mve_move")
6902 (set_attr "length""8")])
6903
6904;;
6905;; [vqrdmlsdhq_m_s])
6906;;
6907(define_insn "mve_vqrdmlsdhq_m_s<mode>"
6908 [
6909 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6910 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6911 (match_operand:MVE_2 2 "s_register_operand" "w")
6912 (match_operand:MVE_2 3 "s_register_operand" "w")
6913 (match_operand:HI 4 "vpr_register_operand" "Up")]
6914 VQRDMLSDHQ_M_S))
6915 ]
6916 "TARGET_HAVE_MVE"
6917 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6918 [(set_attr "type" "mve_move")
6919 (set_attr "length""8")])
6920
6921;;
6922;; [vqrdmlsdhxq_m_s])
6923;;
6924(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
6925 [
6926 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6927 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6928 (match_operand:MVE_2 2 "s_register_operand" "w")
6929 (match_operand:MVE_2 3 "s_register_operand" "w")
6930 (match_operand:HI 4 "vpr_register_operand" "Up")]
6931 VQRDMLSDHXQ_M_S))
6932 ]
6933 "TARGET_HAVE_MVE"
6934 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6935 [(set_attr "type" "mve_move")
6936 (set_attr "length""8")])
6937
6938;;
6939;; [vqrdmulhq_m_n_s])
6940;;
6941(define_insn "mve_vqrdmulhq_m_n_s<mode>"
6942 [
6943 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6944 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6945 (match_operand:MVE_2 2 "s_register_operand" "w")
6946 (match_operand:<V_elem> 3 "s_register_operand" "r")
6947 (match_operand:HI 4 "vpr_register_operand" "Up")]
6948 VQRDMULHQ_M_N_S))
6949 ]
6950 "TARGET_HAVE_MVE"
6951 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6952 [(set_attr "type" "mve_move")
6953 (set_attr "length""8")])
6954
6955;;
6956;; [vqrdmulhq_m_s])
6957;;
6958(define_insn "mve_vqrdmulhq_m_s<mode>"
6959 [
6960 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6961 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6962 (match_operand:MVE_2 2 "s_register_operand" "w")
6963 (match_operand:MVE_2 3 "s_register_operand" "w")
6964 (match_operand:HI 4 "vpr_register_operand" "Up")]
6965 VQRDMULHQ_M_S))
6966 ]
6967 "TARGET_HAVE_MVE"
6968 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6969 [(set_attr "type" "mve_move")
6970 (set_attr "length""8")])
6971
f2170a37
SP		 6972;;
6973;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
6974;;
6975(define_insn "mve_vmlaldavaq_p_<supf><mode>"
6976 [
6977 (set (match_operand:DI 0 "s_register_operand" "=r")
6978 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6979 (match_operand:MVE_5 2 "s_register_operand" "w")
6980 (match_operand:MVE_5 3 "s_register_operand" "w")
6981 (match_operand:HI 4 "vpr_register_operand" "Up")]
6982 VMLALDAVAQ_P))
6983 ]
6984 "TARGET_HAVE_MVE"
6985 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
6986 [(set_attr "type" "mve_move")
6987 (set_attr "length""8")])
6988
6989;;
6990;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s])
6991;;
6992(define_insn "mve_vmlaldavaxq_p_<supf><mode>"
6993 [
6994 (set (match_operand:DI 0 "s_register_operand" "=r")
6995 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6996 (match_operand:MVE_5 2 "s_register_operand" "w")
6997 (match_operand:MVE_5 3 "s_register_operand" "w")
6998 (match_operand:HI 4 "vpr_register_operand" "Up")]
6999 VMLALDAVAXQ_P))
7000 ]
7001 "TARGET_HAVE_MVE"
7002 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7003 [(set_attr "type" "mve_move")
7004 (set_attr "length""8")])
7005
7006;;
7007;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
7008;;
7009(define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
7010 [
7011 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7012 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7013 (match_operand:MVE_5 2 "s_register_operand" "w")
7014 (match_operand:SI 3 "mve_imm_8" "Rb")
7015 (match_operand:HI 4 "vpr_register_operand" "Up")]
7016 VQRSHRNBQ_M_N))
7017 ]
7018 "TARGET_HAVE_MVE"
7019 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7020 [(set_attr "type" "mve_move")
7021 (set_attr "length""8")])
7022
7023;;
7024;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
7025;;
7026(define_insn "mve_vqrshrntq_m_n_<supf><mode>"
7027 [
7028 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7029 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7030 (match_operand:MVE_5 2 "s_register_operand" "w")
7031 (match_operand:SI 3 "mve_imm_8" "Rb")
7032 (match_operand:HI 4 "vpr_register_operand" "Up")]
7033 VQRSHRNTQ_M_N))
7034 ]
7035 "TARGET_HAVE_MVE"
7036 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7037 [(set_attr "type" "mve_move")
7038 (set_attr "length""8")])
7039
7040;;
7041;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
7042;;
7043(define_insn "mve_vqshrnbq_m_n_<supf><mode>"
7044 [
7045 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7046 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7047 (match_operand:MVE_5 2 "s_register_operand" "w")
7048 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")
7049 (match_operand:HI 4 "vpr_register_operand" "Up")]
7050 VQSHRNBQ_M_N))
7051 ]
7052 "TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], <MODE>mode, 0)"
7053 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7054 [(set_attr "type" "mve_move")
7055 (set_attr "length""8")])
7056
7057;;
7058;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
7059;;
7060(define_insn "mve_vqshrntq_m_n_<supf><mode>"
7061 [
7062 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7063 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7064 (match_operand:MVE_5 2 "s_register_operand" "w")
7065 (match_operand:SI 3 "mve_imm_8" "Rb")
7066 (match_operand:HI 4 "vpr_register_operand" "Up")]
7067 VQSHRNTQ_M_N))
7068 ]
7069 "TARGET_HAVE_MVE"
7070 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7071 [(set_attr "type" "mve_move")
7072 (set_attr "length""8")])
7073
7074;;
7075;; [vrmlaldavhaq_p_s])
7076;;
7077(define_insn "mve_vrmlaldavhaq_p_sv4si"
7078 [
7079 (set (match_operand:DI 0 "s_register_operand" "=r")
7080 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7081 (match_operand:V4SI 2 "s_register_operand" "w")
7082 (match_operand:V4SI 3 "s_register_operand" "w")
7083 (match_operand:HI 4 "vpr_register_operand" "Up")]
7084 VRMLALDAVHAQ_P_S))
7085 ]
7086 "TARGET_HAVE_MVE"
7087 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
7088 [(set_attr "type" "mve_move")
7089 (set_attr "length""8")])
7090
7091;;
7092;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
7093;;
7094(define_insn "mve_vrshrnbq_m_n_<supf><mode>"
7095 [
7096 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7097 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7098 (match_operand:MVE_5 2 "s_register_operand" "w")
7099 (match_operand:SI 3 "mve_imm_8" "Rb")
7100 (match_operand:HI 4 "vpr_register_operand" "Up")]
7101 VRSHRNBQ_M_N))
7102 ]
7103 "TARGET_HAVE_MVE"
7104 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7105 [(set_attr "type" "mve_move")
7106 (set_attr "length""8")])
7107
7108;;
7109;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
7110;;
7111(define_insn "mve_vrshrntq_m_n_<supf><mode>"
7112 [
7113 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7114 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7115 (match_operand:MVE_5 2 "s_register_operand" "w")
7116 (match_operand:SI 3 "mve_imm_8" "Rb")
7117 (match_operand:HI 4 "vpr_register_operand" "Up")]
7118 VRSHRNTQ_M_N))
7119 ]
7120 "TARGET_HAVE_MVE"
7121 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7122 [(set_attr "type" "mve_move")
7123 (set_attr "length""8")])
7124
7125;;
7126;; [vshllbq_m_n_u, vshllbq_m_n_s])
7127;;
7128(define_insn "mve_vshllbq_m_n_<supf><mode>"
7129 [
7130 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7131 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7132 (match_operand:MVE_3 2 "s_register_operand" "w")
7133 (match_operand:SI 3 "immediate_operand" "i")
7134 (match_operand:HI 4 "vpr_register_operand" "Up")]
7135 VSHLLBQ_M_N))
7136 ]
7137 "TARGET_HAVE_MVE"
7138 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7139 [(set_attr "type" "mve_move")
7140 (set_attr "length""8")])
7141
7142;;
7143;; [vshlltq_m_n_u, vshlltq_m_n_s])
7144;;
7145(define_insn "mve_vshlltq_m_n_<supf><mode>"
7146 [
7147 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7148 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7149 (match_operand:MVE_3 2 "s_register_operand" "w")
7150 (match_operand:SI 3 "immediate_operand" "i")
7151 (match_operand:HI 4 "vpr_register_operand" "Up")]
7152 VSHLLTQ_M_N))
7153 ]
7154 "TARGET_HAVE_MVE"
7155 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7156 [(set_attr "type" "mve_move")
7157 (set_attr "length""8")])
7158
7159;;
7160;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
7161;;
7162(define_insn "mve_vshrnbq_m_n_<supf><mode>"
7163 [
7164 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7165 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7166 (match_operand:MVE_5 2 "s_register_operand" "w")
7167 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7168 (match_operand:HI 4 "vpr_register_operand" "Up")]
7169 VSHRNBQ_M_N))
7170 ]
7171 "TARGET_HAVE_MVE"
7172 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7173 [(set_attr "type" "mve_move")
7174 (set_attr "length""8")])
7175
7176;;
7177;; [vshrntq_m_n_s, vshrntq_m_n_u])
7178;;
7179(define_insn "mve_vshrntq_m_n_<supf><mode>"
7180 [
7181 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7182 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7183 (match_operand:MVE_5 2 "s_register_operand" "w")
7184 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7185 (match_operand:HI 4 "vpr_register_operand" "Up")]
7186 VSHRNTQ_M_N))
7187 ]
7188 "TARGET_HAVE_MVE"
7189 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7190 [(set_attr "type" "mve_move")
7191 (set_attr "length""8")])
7192
7193;;
7194;; [vmlsldavaq_p_s])
7195;;
7196(define_insn "mve_vmlsldavaq_p_s<mode>"
7197 [
7198 (set (match_operand:DI 0 "s_register_operand" "=r")
7199 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7200 (match_operand:MVE_5 2 "s_register_operand" "w")
7201 (match_operand:MVE_5 3 "s_register_operand" "w")
7202 (match_operand:HI 4 "vpr_register_operand" "Up")]
7203 VMLSLDAVAQ_P_S))
7204 ]
7205 "TARGET_HAVE_MVE"
7206 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7207 [(set_attr "type" "mve_move")
7208 (set_attr "length""8")])
7209
7210;;
7211;; [vmlsldavaxq_p_s])
7212;;
7213(define_insn "mve_vmlsldavaxq_p_s<mode>"
7214 [
7215 (set (match_operand:DI 0 "s_register_operand" "=r")
7216 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7217 (match_operand:MVE_5 2 "s_register_operand" "w")
7218 (match_operand:MVE_5 3 "s_register_operand" "w")
7219 (match_operand:HI 4 "vpr_register_operand" "Up")]
7220 VMLSLDAVAXQ_P_S))
7221 ]
7222 "TARGET_HAVE_MVE"
7223 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7224 [(set_attr "type" "mve_move")
7225 (set_attr "length""8")])
7226
7227;;
7228;; [vmullbq_poly_m_p])
7229;;
7230(define_insn "mve_vmullbq_poly_m_p<mode>"
7231 [
7232 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7233 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7234 (match_operand:MVE_3 2 "s_register_operand" "w")
7235 (match_operand:MVE_3 3 "s_register_operand" "w")
7236 (match_operand:HI 4 "vpr_register_operand" "Up")]
7237 VMULLBQ_POLY_M_P))
7238 ]
7239 "TARGET_HAVE_MVE"
7240 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7241 [(set_attr "type" "mve_move")
7242 (set_attr "length""8")])
7243
7244;;
7245;; [vmulltq_poly_m_p])
7246;;
7247(define_insn "mve_vmulltq_poly_m_p<mode>"
7248 [
7249 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7250 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7251 (match_operand:MVE_3 2 "s_register_operand" "w")
7252 (match_operand:MVE_3 3 "s_register_operand" "w")
7253 (match_operand:HI 4 "vpr_register_operand" "Up")]
7254 VMULLTQ_POLY_M_P))
7255 ]
7256 "TARGET_HAVE_MVE"
7257 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7258 [(set_attr "type" "mve_move")
7259 (set_attr "length""8")])
7260
7261;;
7262;; [vqdmullbq_m_n_s])
7263;;
7264(define_insn "mve_vqdmullbq_m_n_s<mode>"
7265 [
7266 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7267 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7268 (match_operand:MVE_5 2 "s_register_operand" "w")
7269 (match_operand:<V_elem> 3 "s_register_operand" "r")
7270 (match_operand:HI 4 "vpr_register_operand" "Up")]
7271 VQDMULLBQ_M_N_S))
7272 ]
7273 "TARGET_HAVE_MVE"
7274 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7275 [(set_attr "type" "mve_move")
7276 (set_attr "length""8")])
7277
7278;;
7279;; [vqdmullbq_m_s])
7280;;
7281(define_insn "mve_vqdmullbq_m_s<mode>"
7282 [
7283 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7284 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7285 (match_operand:MVE_5 2 "s_register_operand" "w")
7286 (match_operand:MVE_5 3 "s_register_operand" "w")
7287 (match_operand:HI 4 "vpr_register_operand" "Up")]
7288 VQDMULLBQ_M_S))
7289 ]
7290 "TARGET_HAVE_MVE"
7291 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7292 [(set_attr "type" "mve_move")
7293 (set_attr "length""8")])
7294
7295;;
7296;; [vqdmulltq_m_n_s])
7297;;
7298(define_insn "mve_vqdmulltq_m_n_s<mode>"
7299 [
7300 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7301 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7302 (match_operand:MVE_5 2 "s_register_operand" "w")
7303 (match_operand:<V_elem> 3 "s_register_operand" "r")
7304 (match_operand:HI 4 "vpr_register_operand" "Up")]
7305 VQDMULLTQ_M_N_S))
7306 ]
7307 "TARGET_HAVE_MVE"
7308 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
7309 [(set_attr "type" "mve_move")
7310 (set_attr "length""8")])
7311
7312;;
7313;; [vqdmulltq_m_s])
7314;;
7315(define_insn "mve_vqdmulltq_m_s<mode>"
7316 [
7317 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7318 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7319 (match_operand:MVE_5 2 "s_register_operand" "w")
7320 (match_operand:MVE_5 3 "s_register_operand" "w")
7321 (match_operand:HI 4 "vpr_register_operand" "Up")]
7322 VQDMULLTQ_M_S))
7323 ]
7324 "TARGET_HAVE_MVE"
7325 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7326 [(set_attr "type" "mve_move")
7327 (set_attr "length""8")])
7328
7329;;
7330;; [vqrshrunbq_m_n_s])
7331;;
7332(define_insn "mve_vqrshrunbq_m_n_s<mode>"
7333 [
7334 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7335 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7336 (match_operand:MVE_5 2 "s_register_operand" "w")
7337 (match_operand:SI 3 "mve_imm_8" "Rb")
7338 (match_operand:HI 4 "vpr_register_operand" "Up")]
7339 VQRSHRUNBQ_M_N_S))
7340 ]
7341 "TARGET_HAVE_MVE"
7342 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7343 [(set_attr "type" "mve_move")
7344 (set_attr "length""8")])
7345
7346;;
7347;; [vqrshruntq_m_n_s])
7348;;
7349(define_insn "mve_vqrshruntq_m_n_s<mode>"
7350 [
7351 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7352 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7353 (match_operand:MVE_5 2 "s_register_operand" "w")
7354 (match_operand:SI 3 "mve_imm_8" "Rb")
7355 (match_operand:HI 4 "vpr_register_operand" "Up")]
7356 VQRSHRUNTQ_M_N_S))
7357 ]
7358 "TARGET_HAVE_MVE"
7359 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7360 [(set_attr "type" "mve_move")
7361 (set_attr "length""8")])
7362
7363;;
7364;; [vqshrunbq_m_n_s])
7365;;
7366(define_insn "mve_vqshrunbq_m_n_s<mode>"
7367 [
7368 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7369 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7370 (match_operand:MVE_5 2 "s_register_operand" "w")
7371 (match_operand:SI 3 "mve_imm_8" "Rb")
7372 (match_operand:HI 4 "vpr_register_operand" "Up")]
7373 VQSHRUNBQ_M_N_S))
7374 ]
7375 "TARGET_HAVE_MVE"
7376 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7377 [(set_attr "type" "mve_move")
7378 (set_attr "length""8")])
7379
7380;;
7381;; [vqshruntq_m_n_s])
7382;;
7383(define_insn "mve_vqshruntq_m_n_s<mode>"
7384 [
7385 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7386 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7387 (match_operand:MVE_5 2 "s_register_operand" "w")
7388 (match_operand:SI 3 "mve_imm_8" "Rb")
7389 (match_operand:HI 4 "vpr_register_operand" "Up")]
7390 VQSHRUNTQ_M_N_S))
7391 ]
7392 "TARGET_HAVE_MVE"
7393 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7394 [(set_attr "type" "mve_move")
7395 (set_attr "length""8")])
7396
7397;;
7398;; [vrmlaldavhaq_p_u])
7399;;
7400(define_insn "mve_vrmlaldavhaq_p_uv4si"
7401 [
7402 (set (match_operand:DI 0 "s_register_operand" "=r")
7403 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7404 (match_operand:V4SI 2 "s_register_operand" "w")
7405 (match_operand:V4SI 3 "s_register_operand" "w")
7406 (match_operand:HI 4 "vpr_register_operand" "Up")]
7407 VRMLALDAVHAQ_P_U))
7408 ]
7409 "TARGET_HAVE_MVE"
7410 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
7411 [(set_attr "type" "mve_move")
7412 (set_attr "length""8")])
7413
7414;;
7415;; [vrmlaldavhaxq_p_s])
7416;;
7417(define_insn "mve_vrmlaldavhaxq_p_sv4si"
7418 [
7419 (set (match_operand:DI 0 "s_register_operand" "=r")
7420 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7421 (match_operand:V4SI 2 "s_register_operand" "w")
7422 (match_operand:V4SI 3 "s_register_operand" "w")
7423 (match_operand:HI 4 "vpr_register_operand" "Up")]
7424 VRMLALDAVHAXQ_P_S))
7425 ]
7426 "TARGET_HAVE_MVE"
7427 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7428 [(set_attr "type" "mve_move")
7429 (set_attr "length""8")])
7430
7431;;
7432;; [vrmlsldavhaq_p_s])
7433;;
7434(define_insn "mve_vrmlsldavhaq_p_sv4si"
7435 [
7436 (set (match_operand:DI 0 "s_register_operand" "=r")
7437 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7438 (match_operand:V4SI 2 "s_register_operand" "w")
7439 (match_operand:V4SI 3 "s_register_operand" "w")
7440 (match_operand:HI 4 "vpr_register_operand" "Up")]
7441 VRMLSLDAVHAQ_P_S))
7442 ]
7443 "TARGET_HAVE_MVE"
7444 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
7445 [(set_attr "type" "mve_move")
7446 (set_attr "length""8")])
7447
7448;;
7449;; [vrmlsldavhaxq_p_s])
7450;;
7451(define_insn "mve_vrmlsldavhaxq_p_sv4si"
7452 [
7453 (set (match_operand:DI 0 "s_register_operand" "=r")
7454 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7455 (match_operand:V4SI 2 "s_register_operand" "w")
7456 (match_operand:V4SI 3 "s_register_operand" "w")
7457 (match_operand:HI 4 "vpr_register_operand" "Up")]
7458 VRMLSLDAVHAXQ_P_S))
7459 ]
7460 "TARGET_HAVE_MVE"
7461 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7462 [(set_attr "type" "mve_move")
7463 (set_attr "length""8")])
532e9e24
SP		 7464;;
7465;; [vabdq_m_f])
7466;;
7467(define_insn "mve_vabdq_m_f<mode>"
7468 [
7469 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7470 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7471 (match_operand:MVE_0 2 "s_register_operand" "w")
7472 (match_operand:MVE_0 3 "s_register_operand" "w")
7473 (match_operand:HI 4 "vpr_register_operand" "Up")]
7474 VABDQ_M_F))
7475 ]
7476 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7477 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3"
7478 [(set_attr "type" "mve_move")
7479 (set_attr "length""8")])
7480
7481;;
7482;; [vaddq_m_f])
7483;;
7484(define_insn "mve_vaddq_m_f<mode>"
7485 [
7486 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7487 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7488 (match_operand:MVE_0 2 "s_register_operand" "w")
7489 (match_operand:MVE_0 3 "s_register_operand" "w")
7490 (match_operand:HI 4 "vpr_register_operand" "Up")]
7491 VADDQ_M_F))
7492 ]
7493 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7494 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3"
7495 [(set_attr "type" "mve_move")
7496 (set_attr "length""8")])
7497
7498;;
7499;; [vaddq_m_n_f])
7500;;
7501(define_insn "mve_vaddq_m_n_f<mode>"
7502 [
7503 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7504 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7505 (match_operand:MVE_0 2 "s_register_operand" "w")
7506 (match_operand:<V_elem> 3 "s_register_operand" "r")
7507 (match_operand:HI 4 "vpr_register_operand" "Up")]
7508 VADDQ_M_N_F))
7509 ]
7510 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7511 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3"
7512 [(set_attr "type" "mve_move")
7513 (set_attr "length""8")])
7514
7515;;
7516;; [vandq_m_f])
7517;;
7518(define_insn "mve_vandq_m_f<mode>"
7519 [
7520 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7521 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7522 (match_operand:MVE_0 2 "s_register_operand" "w")
7523 (match_operand:MVE_0 3 "s_register_operand" "w")
7524 (match_operand:HI 4 "vpr_register_operand" "Up")]
7525 VANDQ_M_F))
7526 ]
7527 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7528 "vpst\;vandt %q0, %q2, %q3"
7529 [(set_attr "type" "mve_move")
7530 (set_attr "length""8")])
7531
7532;;
7533;; [vbicq_m_f])
7534;;
7535(define_insn "mve_vbicq_m_f<mode>"
7536 [
7537 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7538 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7539 (match_operand:MVE_0 2 "s_register_operand" "w")
7540 (match_operand:MVE_0 3 "s_register_operand" "w")
7541 (match_operand:HI 4 "vpr_register_operand" "Up")]
7542 VBICQ_M_F))
7543 ]
7544 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7545 "vpst\;vbict %q0, %q2, %q3"
7546 [(set_attr "type" "mve_move")
7547 (set_attr "length""8")])
7548
7549;;
7550;; [vbrsrq_m_n_f])
7551;;
7552(define_insn "mve_vbrsrq_m_n_f<mode>"
7553 [
7554 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7555 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7556 (match_operand:MVE_0 2 "s_register_operand" "w")
7557 (match_operand:SI 3 "s_register_operand" "r")
7558 (match_operand:HI 4 "vpr_register_operand" "Up")]
7559 VBRSRQ_M_N_F))
7560 ]
7561 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7562 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
7563 [(set_attr "type" "mve_move")
7564 (set_attr "length""8")])
7565
7566;;
7567;; [vcaddq_rot270_m_f])
7568;;
7569(define_insn "mve_vcaddq_rot270_m_f<mode>"
7570 [
7571 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7572 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7573 (match_operand:MVE_0 2 "s_register_operand" "w")
7574 (match_operand:MVE_0 3 "s_register_operand" "w")
7575 (match_operand:HI 4 "vpr_register_operand" "Up")]
7576 VCADDQ_ROT270_M_F))
7577 ]
7578 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7579 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7580 [(set_attr "type" "mve_move")
7581 (set_attr "length""8")])
7582
7583;;
7584;; [vcaddq_rot90_m_f])
7585;;
7586(define_insn "mve_vcaddq_rot90_m_f<mode>"
7587 [
7588 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7589 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7590 (match_operand:MVE_0 2 "s_register_operand" "w")
7591 (match_operand:MVE_0 3 "s_register_operand" "w")
7592 (match_operand:HI 4 "vpr_register_operand" "Up")]
7593 VCADDQ_ROT90_M_F))
7594 ]
7595 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7596 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7597 [(set_attr "type" "mve_move")
7598 (set_attr "length""8")])
7599
7600;;
7601;; [vcmlaq_m_f])
7602;;
7603(define_insn "mve_vcmlaq_m_f<mode>"
7604 [
7605 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7606 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7607 (match_operand:MVE_0 2 "s_register_operand" "w")
7608 (match_operand:MVE_0 3 "s_register_operand" "w")
7609 (match_operand:HI 4 "vpr_register_operand" "Up")]
7610 VCMLAQ_M_F))
7611 ]
7612 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7613 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7614 [(set_attr "type" "mve_move")
7615 (set_attr "length""8")])
7616
7617;;
7618;; [vcmlaq_rot180_m_f])
7619;;
7620(define_insn "mve_vcmlaq_rot180_m_f<mode>"
7621 [
7622 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7623 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7624 (match_operand:MVE_0 2 "s_register_operand" "w")
7625 (match_operand:MVE_0 3 "s_register_operand" "w")
7626 (match_operand:HI 4 "vpr_register_operand" "Up")]
7627 VCMLAQ_ROT180_M_F))
7628 ]
7629 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7630 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7631 [(set_attr "type" "mve_move")
7632 (set_attr "length""8")])
7633
7634;;
7635;; [vcmlaq_rot270_m_f])
7636;;
7637(define_insn "mve_vcmlaq_rot270_m_f<mode>"
7638 [
7639 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7640 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7641 (match_operand:MVE_0 2 "s_register_operand" "w")
7642 (match_operand:MVE_0 3 "s_register_operand" "w")
7643 (match_operand:HI 4 "vpr_register_operand" "Up")]
7644 VCMLAQ_ROT270_M_F))
7645 ]
7646 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7647 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7648 [(set_attr "type" "mve_move")
7649 (set_attr "length""8")])
7650
7651;;
7652;; [vcmlaq_rot90_m_f])
7653;;
7654(define_insn "mve_vcmlaq_rot90_m_f<mode>"
7655 [
7656 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7657 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7658 (match_operand:MVE_0 2 "s_register_operand" "w")
7659 (match_operand:MVE_0 3 "s_register_operand" "w")
7660 (match_operand:HI 4 "vpr_register_operand" "Up")]
7661 VCMLAQ_ROT90_M_F))
7662 ]
7663 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7664 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7665 [(set_attr "type" "mve_move")
7666 (set_attr "length""8")])
7667
7668;;
7669;; [vcmulq_m_f])
7670;;
7671(define_insn "mve_vcmulq_m_f<mode>"
7672 [
7673 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7674 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7675 (match_operand:MVE_0 2 "s_register_operand" "w")
7676 (match_operand:MVE_0 3 "s_register_operand" "w")
7677 (match_operand:HI 4 "vpr_register_operand" "Up")]
7678 VCMULQ_M_F))
7679 ]
7680 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7681 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7682 [(set_attr "type" "mve_move")
7683 (set_attr "length""8")])
7684
7685;;
7686;; [vcmulq_rot180_m_f])
7687;;
7688(define_insn "mve_vcmulq_rot180_m_f<mode>"
7689 [
7690 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7691 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7692 (match_operand:MVE_0 2 "s_register_operand" "w")
7693 (match_operand:MVE_0 3 "s_register_operand" "w")
7694 (match_operand:HI 4 "vpr_register_operand" "Up")]
7695 VCMULQ_ROT180_M_F))
7696 ]
7697 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7698 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7699 [(set_attr "type" "mve_move")
7700 (set_attr "length""8")])
7701
7702;;
7703;; [vcmulq_rot270_m_f])
7704;;
7705(define_insn "mve_vcmulq_rot270_m_f<mode>"
7706 [
7707 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7708 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7709 (match_operand:MVE_0 2 "s_register_operand" "w")
7710 (match_operand:MVE_0 3 "s_register_operand" "w")
7711 (match_operand:HI 4 "vpr_register_operand" "Up")]
7712 VCMULQ_ROT270_M_F))
7713 ]
7714 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7715 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7716 [(set_attr "type" "mve_move")
7717 (set_attr "length""8")])
7718
7719;;
7720;; [vcmulq_rot90_m_f])
7721;;
7722(define_insn "mve_vcmulq_rot90_m_f<mode>"
7723 [
7724 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7725 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7726 (match_operand:MVE_0 2 "s_register_operand" "w")
7727 (match_operand:MVE_0 3 "s_register_operand" "w")
7728 (match_operand:HI 4 "vpr_register_operand" "Up")]
7729 VCMULQ_ROT90_M_F))
7730 ]
7731 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7732 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7733 [(set_attr "type" "mve_move")
7734 (set_attr "length""8")])
7735
7736;;
7737;; [veorq_m_f])
7738;;
7739(define_insn "mve_veorq_m_f<mode>"
7740 [
7741 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7742 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7743 (match_operand:MVE_0 2 "s_register_operand" "w")
7744 (match_operand:MVE_0 3 "s_register_operand" "w")
7745 (match_operand:HI 4 "vpr_register_operand" "Up")]
7746 VEORQ_M_F))
7747 ]
7748 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7749 "vpst\;veort %q0, %q2, %q3"
7750 [(set_attr "type" "mve_move")
7751 (set_attr "length""8")])
7752
7753;;
7754;; [vfmaq_m_f])
7755;;
7756(define_insn "mve_vfmaq_m_f<mode>"
7757 [
7758 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7759 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7760 (match_operand:MVE_0 2 "s_register_operand" "w")
7761 (match_operand:MVE_0 3 "s_register_operand" "w")
7762 (match_operand:HI 4 "vpr_register_operand" "Up")]
7763 VFMAQ_M_F))
7764 ]
7765 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7766 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3"
7767 [(set_attr "type" "mve_move")
7768 (set_attr "length""8")])
7769
7770;;
7771;; [vfmaq_m_n_f])
7772;;
7773(define_insn "mve_vfmaq_m_n_f<mode>"
7774 [
7775 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7776 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7777 (match_operand:MVE_0 2 "s_register_operand" "w")
7778 (match_operand:<V_elem> 3 "s_register_operand" "r")
7779 (match_operand:HI 4 "vpr_register_operand" "Up")]
7780 VFMAQ_M_N_F))
7781 ]
7782 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7783 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3"
7784 [(set_attr "type" "mve_move")
7785 (set_attr "length""8")])
7786
7787;;
7788;; [vfmasq_m_n_f])
7789;;
7790(define_insn "mve_vfmasq_m_n_f<mode>"
7791 [
7792 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7793 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7794 (match_operand:MVE_0 2 "s_register_operand" "w")
7795 (match_operand:<V_elem> 3 "s_register_operand" "r")
7796 (match_operand:HI 4 "vpr_register_operand" "Up")]
7797 VFMASQ_M_N_F))
7798 ]
7799 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7800 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3"
7801 [(set_attr "type" "mve_move")
7802 (set_attr "length""8")])
7803
7804;;
7805;; [vfmsq_m_f])
7806;;
7807(define_insn "mve_vfmsq_m_f<mode>"
7808 [
7809 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7810 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7811 (match_operand:MVE_0 2 "s_register_operand" "w")
7812 (match_operand:MVE_0 3 "s_register_operand" "w")
7813 (match_operand:HI 4 "vpr_register_operand" "Up")]
7814 VFMSQ_M_F))
7815 ]
7816 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7817 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3"
7818 [(set_attr "type" "mve_move")
7819 (set_attr "length""8")])
7820
7821;;
7822;; [vmaxnmq_m_f])
7823;;
7824(define_insn "mve_vmaxnmq_m_f<mode>"
7825 [
7826 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7827 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7828 (match_operand:MVE_0 2 "s_register_operand" "w")
7829 (match_operand:MVE_0 3 "s_register_operand" "w")
7830 (match_operand:HI 4 "vpr_register_operand" "Up")]
7831 VMAXNMQ_M_F))
7832 ]
7833 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7834 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7835 [(set_attr "type" "mve_move")
7836 (set_attr "length""8")])
7837
7838;;
7839;; [vminnmq_m_f])
7840;;
7841(define_insn "mve_vminnmq_m_f<mode>"
7842 [
7843 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7844 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7845 (match_operand:MVE_0 2 "s_register_operand" "w")
7846 (match_operand:MVE_0 3 "s_register_operand" "w")
7847 (match_operand:HI 4 "vpr_register_operand" "Up")]
7848 VMINNMQ_M_F))
7849 ]
7850 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7851 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7852 [(set_attr "type" "mve_move")
7853 (set_attr "length""8")])
7854
7855;;
7856;; [vmulq_m_f])
7857;;
7858(define_insn "mve_vmulq_m_f<mode>"
7859 [
7860 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7861 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7862 (match_operand:MVE_0 2 "s_register_operand" "w")
7863 (match_operand:MVE_0 3 "s_register_operand" "w")
7864 (match_operand:HI 4 "vpr_register_operand" "Up")]
7865 VMULQ_M_F))
7866 ]
7867 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7868 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3"
7869 [(set_attr "type" "mve_move")
7870 (set_attr "length""8")])
7871
7872;;
7873;; [vmulq_m_n_f])
7874;;
7875(define_insn "mve_vmulq_m_n_f<mode>"
7876 [
7877 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7878 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7879 (match_operand:MVE_0 2 "s_register_operand" "w")
7880 (match_operand:<V_elem> 3 "s_register_operand" "r")
7881 (match_operand:HI 4 "vpr_register_operand" "Up")]
7882 VMULQ_M_N_F))
7883 ]
7884 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7885 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3"
7886 [(set_attr "type" "mve_move")
7887 (set_attr "length""8")])
7888
7889;;
7890;; [vornq_m_f])
7891;;
7892(define_insn "mve_vornq_m_f<mode>"
7893 [
7894 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7895 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7896 (match_operand:MVE_0 2 "s_register_operand" "w")
7897 (match_operand:MVE_0 3 "s_register_operand" "w")
7898 (match_operand:HI 4 "vpr_register_operand" "Up")]
7899 VORNQ_M_F))
7900 ]
7901 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7902 "vpst\;vornt %q0, %q2, %q3"
7903 [(set_attr "type" "mve_move")
7904 (set_attr "length""8")])
7905
7906;;
7907;; [vorrq_m_f])
7908;;
7909(define_insn "mve_vorrq_m_f<mode>"
7910 [
7911 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7912 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7913 (match_operand:MVE_0 2 "s_register_operand" "w")
7914 (match_operand:MVE_0 3 "s_register_operand" "w")
7915 (match_operand:HI 4 "vpr_register_operand" "Up")]
7916 VORRQ_M_F))
7917 ]
7918 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7919 "vpst\;vorrt %q0, %q2, %q3"
7920 [(set_attr "type" "mve_move")
7921 (set_attr "length""8")])
7922
7923;;
7924;; [vsubq_m_f])
7925;;
7926(define_insn "mve_vsubq_m_f<mode>"
7927 [
7928 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7929 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7930 (match_operand:MVE_0 2 "s_register_operand" "w")
7931 (match_operand:MVE_0 3 "s_register_operand" "w")
7932 (match_operand:HI 4 "vpr_register_operand" "Up")]
7933 VSUBQ_M_F))
7934 ]
7935 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7936 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3"
7937 [(set_attr "type" "mve_move")
7938 (set_attr "length""8")])
7939
7940;;
7941;; [vsubq_m_n_f])
7942;;
7943(define_insn "mve_vsubq_m_n_f<mode>"
7944 [
7945 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7946 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7947 (match_operand:MVE_0 2 "s_register_operand" "w")
7948 (match_operand:<V_elem> 3 "s_register_operand" "r")
7949 (match_operand:HI 4 "vpr_register_operand" "Up")]
7950 VSUBQ_M_N_F))
7951 ]
7952 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7953 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
7954 [(set_attr "type" "mve_move")
7955 (set_attr "length""8")])
4ff68575
SP		 7956
7957;;
7958;; [vstrbq_s vstrbq_u]
7959;;
7960(define_insn "mve_vstrbq_<supf><mode>"
7961 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
7962 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
7963 VSTRBQ))
7964 ]
7965 "TARGET_HAVE_MVE"
7966{
7967 rtx ops[2];
7968 int regno = REGNO (operands[1]);
7969 ops[1] = gen_rtx_REG (TImode, regno);
7970 ops[0] = operands[0];
7971 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
7972 return "";
7973}
7974 [(set_attr "length" "4")])
7975
7976;;
7977;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
7978;;
7979(define_insn "mve_vstrbq_scatter_offset_<supf><mode>"
7980 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
7981 (unspec:<MVE_B_ELEM>
7982 [(match_operand:MVE_2 1 "s_register_operand" "w")
7983 (match_operand:MVE_2 2 "s_register_operand" "w")]
7984 VSTRBSOQ))
7985 ]
7986 "TARGET_HAVE_MVE"
7987{
7988 rtx ops[3];
7989 ops[0] = operands[0];
7990 ops[1] = operands[1];
7991 ops[2] = operands[2];
7992 output_asm_insn("vstrb.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
7993 return "";
7994}
7995 [(set_attr "length" "4")])
7996
7997;;
7998;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
7999;;
8000(define_insn "mve_vstrwq_scatter_base_<supf>v4si"
8001 [(set (mem:BLK (scratch))
8002 (unspec:BLK
8003 [(match_operand:V4SI 0 "s_register_operand" "w")
8004 (match_operand:SI 1 "immediate_operand" "i")
8005 (match_operand:V4SI 2 "s_register_operand" "w")]
8006 VSTRWSBQ))
8007 ]
8008 "TARGET_HAVE_MVE"
8009{
8010 rtx ops[3];
8011 ops[0] = operands[0];
8012 ops[1] = operands[1];
8013 ops[2] = operands[2];
8014 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
8015 return "";
8016}
8017 [(set_attr "length" "4")])
535a8645
SP		 8018
8019;;
8020;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
8021;;
8022(define_insn "mve_vldrbq_gather_offset_<supf><mode>"
8023 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8024 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8025 (match_operand:MVE_2 2 "s_register_operand" "w")]
8026 VLDRBGOQ))
8027 ]
8028 "TARGET_HAVE_MVE"
8029{
8030 rtx ops[3];
8031 ops[0] = operands[0];
8032 ops[1] = operands[1];
8033 ops[2] = operands[2];
8034 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8035 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
8036 else
8037 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8038 return "";
8039}
8040 [(set_attr "length" "4")])
8041
8042;;
8043;; [vldrbq_s vldrbq_u]
8044;;
8045(define_insn "mve_vldrbq_<supf><mode>"
8046 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8047 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")]
8048 VLDRBQ))
8049 ]
8050 "TARGET_HAVE_MVE"
8051{
8052 rtx ops[2];
8053 int regno = REGNO (operands[0]);
8054 ops[0] = gen_rtx_REG (TImode, regno);
8055 ops[1] = operands[1];
8056 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
8057 return "";
8058}
8059 [(set_attr "length" "4")])
8060
8061;;
8062;; [vldrwq_gather_base_s vldrwq_gather_base_u]
8063;;
8064(define_insn "mve_vldrwq_gather_base_<supf>v4si"
8065 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8066 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8067 (match_operand:SI 2 "immediate_operand" "i")]
8068 VLDRWGBQ))
8069 ]
8070 "TARGET_HAVE_MVE"
8071{
8072 rtx ops[3];
8073 ops[0] = operands[0];
8074 ops[1] = operands[1];
8075 ops[2] = operands[2];
8076 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8077 return "";
8078}
8079 [(set_attr "length" "4")])
405e918c
SP		 8080
8081;;
8082;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
8083;;
8084(define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>"
8085 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8086 (unspec:<MVE_B_ELEM>
8087 [(match_operand:MVE_2 1 "s_register_operand" "w")
8088 (match_operand:MVE_2 2 "s_register_operand" "w")
8089 (match_operand:HI 3 "vpr_register_operand" "Up")]
8090 VSTRBSOQ))
8091 ]
8092 "TARGET_HAVE_MVE"
8093{
8094 rtx ops[3];
8095 ops[0] = operands[0];
8096 ops[1] = operands[1];
8097 ops[2] = operands[2];
8098 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8099 return "";
8100}
8101 [(set_attr "length" "8")])
8102
8103;;
8104;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
8105;;
8106(define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
8107 [(set (mem:BLK (scratch))
8108 (unspec:BLK
8109 [(match_operand:V4SI 0 "s_register_operand" "w")
8110 (match_operand:SI 1 "immediate_operand" "i")
8111 (match_operand:V4SI 2 "s_register_operand" "w")
8112 (match_operand:HI 3 "vpr_register_operand" "Up")]
8113 VSTRWSBQ))
8114 ]
8115 "TARGET_HAVE_MVE"
8116{
8117 rtx ops[3];
8118 ops[0] = operands[0];
8119 ops[1] = operands[1];
8120 ops[2] = operands[2];
8121 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
8122 return "";
8123}
8124 [(set_attr "length" "8")])
8125
8126;;
8127;; [vstrbq_p_s vstrbq_p_u]
8128;;
8129(define_insn "mve_vstrbq_p_<supf><mode>"
8130 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8131 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
8132 (match_operand:HI 2 "vpr_register_operand" "Up")]
8133 VSTRBQ))
8134 ]
8135 "TARGET_HAVE_MVE"
8136{
8137 rtx ops[2];
8138 int regno = REGNO (operands[1]);
8139 ops[1] = gen_rtx_REG (TImode, regno);
8140 ops[0] = operands[0];
8141 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q1, %E0",ops);
8142 return "";
8143}
8144 [(set_attr "length" "8")])
429d607b
SP		 8145
8146;;
8147;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
8148;;
8149(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
8150 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8151 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8152 (match_operand:MVE_2 2 "s_register_operand" "w")
8153 (match_operand:HI 3 "vpr_register_operand" "Up")]
8154 VLDRBGOQ))
8155 ]
8156 "TARGET_HAVE_MVE"
8157{
8158 rtx ops[4];
8159 ops[0] = operands[0];
8160 ops[1] = operands[1];
8161 ops[2] = operands[2];
8162 ops[3] = operands[3];
8163 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8164 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
8165 else
8166 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8167 return "";
8168}
8169 [(set_attr "length" "8")])
8170
8171;;
8172;; [vldrbq_z_s vldrbq_z_u]
8173;;
8174(define_insn "mve_vldrbq_z_<supf><mode>"
8175 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8176 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8177 (match_operand:HI 2 "vpr_register_operand" "Up")]
8178 VLDRBQ))
8179 ]
8180 "TARGET_HAVE_MVE"
8181{
8182 rtx ops[2];
8183 int regno = REGNO (operands[0]);
8184 ops[0] = gen_rtx_REG (TImode, regno);
8185 ops[1] = operands[1];
8186 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
8187 return "";
8188}
8189 [(set_attr "length" "8")])
8190
8191;;
8192;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
8193;;
8194(define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
8195 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8196 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8197 (match_operand:SI 2 "immediate_operand" "i")
8198 (match_operand:HI 3 "vpr_register_operand" "Up")]
8199 VLDRWGBQ))
8200 ]
8201 "TARGET_HAVE_MVE"
8202{
8203 rtx ops[3];
8204 ops[0] = operands[0];
8205 ops[1] = operands[1];
8206 ops[2] = operands[2];
8207 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8208 return "";
8209}
8210 [(set_attr "length" "8")])
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