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[ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory.
[thirdparty/gcc.git] / gcc / config / arm / mve.md
CommitLineData
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SP		 1;; Arm M-profile Vector Extension Machine Description
2;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful, but
12;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14;; General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
19
63c8f7d6
SP		 20(define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
21 (V2DI "u64")])
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SP		 22(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
23(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
a50f6abf 24(define_mode_iterator MVE_0 [V8HF V4SF])
f166a8cd 25(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
6df4618c 26(define_mode_iterator MVE_3 [V16QI V8HI])
5db0eb95
SP		 27(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
28(define_mode_iterator MVE_5 [V8HI V4SI])
bf1e3d5a 29(define_mode_iterator MVE_6 [V8HI V4SI])
14782c81 30
a50f6abf
SP		 31(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
32 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
6df4618c
SP		 33 VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
34 VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
35 VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
36 VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
37 VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
38 VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
39 VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
40 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
4be8cf77
SP		 41 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
42 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
f166a8cd 43 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
d71dba7b 44 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
33203b4c
SP		 45 VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
46 VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
47 VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
48 VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
49 VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
50 VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
51 VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
52 VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
53 VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
54 VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
55 VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
56 VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
57 VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
58 VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
59 VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
60 VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
61 VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
62 VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
63 VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
64 VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
65 VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
66 VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
67 VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
68 VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
69 VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
f9355dee
SP		 70 VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
71 VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
72 VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
73 VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
74 VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
75 VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
76 VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
77 VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
78 VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
79 VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
80 VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
81 VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
82 VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
83 VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
84 VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
85 VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
86 VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
87 VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
88 VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
0dad5b33
SP		 89 VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
90 VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
91 VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
92 VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
8165795c
SP		 93 VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
94 VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
95 VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
96 VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
97 VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
98 VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
99 VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
100 VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
101 VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
102 VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
103 VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
104 VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
105 VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
106 VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
107 VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
108 VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
109 VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
110 VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
111 VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
112 VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
113 VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
e3678b44
SP		 114 VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
115 VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
116 VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
117 VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
118 VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
119 VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
120 VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
121 VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
122 VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
123 VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
124 VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
125 VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
126 VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
127 VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
128 VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
129 VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
130 VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
131 VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
132 VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
133 VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
134 VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
135 VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
136 VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
137 VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
138 VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
139 VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
140 VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
141 VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
142 VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
143 VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
db5db9d2
SP		 144 VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
145 VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
146 VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
8eb3b6b9
SP		 147 VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
148 VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
149 VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
150 VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
151 VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
152 VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
153 VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
154 VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
155 VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
156 VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
157 VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
158 VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
159 VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
160 VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
161 VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
162 VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
163 VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
164 VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
165 VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
166 VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
167 VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
168 VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
169 VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
170 VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
171 VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
172 VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
173 VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
174 VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
175 VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
176 VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
f2170a37
SP		 177 VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
178 VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
179 VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
180 VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
181 VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
182 VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
183 VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
184 VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
185 VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
186 VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
187 VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
188 VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
189 VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
532e9e24
SP		 190 VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
191 VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
192 VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
193 VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
194 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
4ff68575 195 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
535a8645 196 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
bf1e3d5a
SP		 197 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
198 VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
199 VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
4cc23303
SP		 200 VLDRWQ_F VLDRWQ_S VLDRWQ_U VLDRDQGB_S VLDRDQGB_U
201 VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U
202 VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F
203 VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S
5cad47e0
SP		 204 VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S
205 VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S
206 VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F])
a50f6abf 207
bf1e3d5a
SP		 208(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
209 (V4SF "V4SI")])
a50f6abf 210
6df4618c
SP		 211(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
212 (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
213 (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
214 (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
215 (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
216 (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
217 (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
218 (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
219 (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
220 (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
221 (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
4be8cf77 222 (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
f166a8cd
SP		 223 (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
224 (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
d71dba7b
SP		 225 (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
226 (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
33203b4c
SP		 227 (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
228 (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
229 (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
230 (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
231 (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
232 (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
233 (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
234 (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
235 (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
236 (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
237 (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
238 (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
239 (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
240 (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
241 (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
242 (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
243 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
244 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
245 (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
246 (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
247 (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
248 (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
249 (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
250 (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
251 (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
252 (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
253 (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
254 (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
255 (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
256 (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
257 (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
258 (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
f9355dee
SP		 259 (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
260 (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
261 (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
262 (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
263 (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
264 (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
265 (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
266 (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
0dad5b33
SP		 267 (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
268 (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
269 (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
270 (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
271 (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
8165795c
SP		 272 (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
273 (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
274 (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
275 (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
276 (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
277 (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
278 (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
279 (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
280 (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
281 (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
282 (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
283 (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
284 (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
285 (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
286 (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
287 (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
288 (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
e3678b44
SP		 289 (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
290 (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
291 (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
292 (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
293 (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
294 (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
295 (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
296 (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
297 (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
298 (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
299 (VREV16Q_M_S "s") (VREV16Q_M_U "u")
300 (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
301 (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
302 (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
303 (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
304 (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
305 (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
306 (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
307 (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
308 (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
309 (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
db5db9d2
SP		 310 (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
311 (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
312 (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
313 (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
8eb3b6b9
SP		 314 (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
315 (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
316 (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
317 (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
318 (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
319 (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
320 (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
321 (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
322 (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
323 (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
324 (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
325 (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
326 (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
327 (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
328 (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
329 (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
330 (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
331 (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
332 (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
333 (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
334 (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
335 (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
336 (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
337 (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
338 (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
339 (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
340 (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
341 (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
342 (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
343 (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
f2170a37
SP		 344 (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
345 (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
346 (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
347 (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
348 (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
349 (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
350 (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
351 (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
352 (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
353 (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
354 (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
355 (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
356 (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
4ff68575
SP		 357 (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
358 (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
535a8645
SP		 359 (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
360 (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
bf1e3d5a
SP		 361 (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
362 (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
363 (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
364 (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
4cc23303
SP		 365 (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
366 (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
367 (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
5cad47e0
SP		 368 (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
369 (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
370 (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
371 (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")])
5db0eb95 372
a475f153 373(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
f9355dee
SP		 374 (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
375 (VCTP32Q_M "32") (VCTP64Q_M "64")])
f166a8cd
SP		 376(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
377 (V4SI "mve_imm_32")])
378(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
33203b4c 379(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
8165795c
SP		 380(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
381(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
382 (V4SI "mve_imm_31")])
e3678b44
SP		 383(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
384(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
e3678b44
SP		 385(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
386(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
4ff68575 387(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
bf1e3d5a
SP		 388(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
389(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h")
390 (V4SF "w")])
a475f153 391
a50f6abf 392(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
5db0eb95
SP		 393(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
394(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
395(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
6df4618c
SP		 396(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
397(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
398(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
399(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
400(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
401(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
402(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
403(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
404(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
405(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
406(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
407(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
408(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
a475f153 409(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
f9355dee 410(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
4be8cf77 411(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
f166a8cd
SP		 412(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
413(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
414(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
d71dba7b
SP		 415(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
416(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
417(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
33203b4c
SP		 418(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
419(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
420(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
421(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
422(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
423(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
424(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
425(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
426(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
427(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
428(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
429(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
430(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
431(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
432(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
433(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
434(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
435(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
436(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
437(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
438(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
439(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
440(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
441(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
442(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
443(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
444(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
445(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
446(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
447(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
448(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
449(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
450(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
451(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
452(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
453(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
454(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
455(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
456(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
457(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
458(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
459(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
460(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
461(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
462(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
463(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
464(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
f9355dee
SP		 465(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
466(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
467(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
468(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
469(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
470(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
471(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
472(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
473(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
474(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
475(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
476(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
0dad5b33
SP		 477(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
478(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
479(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
480(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
481(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
482(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
483(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
8165795c
SP		 484(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
485(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
486(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
487(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
488(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
489(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
490(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
491(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
492(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
493(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
494(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
495(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
496(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
497(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
498(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
499(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
500(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
501(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
502(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
503(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
504(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
505(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
506(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
507(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
508(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
e3678b44
SP		 509(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
510(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
511(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
512(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
513(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
514(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
515(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
516(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
517(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
518(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
519(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
520(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
521(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
522(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
523(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
524(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
525(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
526(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
527(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
528(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
529(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
530(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
531(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
532(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
533(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
534(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
535(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
536(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
db5db9d2
SP		 537(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
538(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
539(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
540(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
541(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
8eb3b6b9
SP		 542(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
543(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
544(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
545(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
546(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
547(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
548(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
549(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
550(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
551(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
552(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
553(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
554(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
555(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
556(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
557(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
558(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
559(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
560(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
561(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
562(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
563(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
564(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
565(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
566(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
567(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
568(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
569(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
570(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
571(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
572(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
573(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
574(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
575(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
576(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
577(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
578(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
579(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
580(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
581(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
f2170a37
SP		 582(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
583(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
584(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
585(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
586(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
587(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
588(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
589(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
590(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
591(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
592(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
593(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
4ff68575
SP		 594(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
595(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
596(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
535a8645
SP		 597(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
598(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
599(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
bf1e3d5a
SP		 600(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
601(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
602(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
603(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
604(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
4cc23303
SP		 605(define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U])
606(define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U])
607(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
608(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
609(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
5cad47e0
SP		 610(define_int_iterator VST1Q [VST1Q_S VST1Q_U])
611(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
612(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
613(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
614(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
63c8f7d6
SP		 615
616(define_insn "*mve_mov<mode>"
617 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
618 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
619 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
620{
621 if (which_alternative == 3 || which_alternative == 6)
622 {
623 int width, is_valid;
624 static char templ[40];
625
626 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
627 &operands[1], &width);
628
629 gcc_assert (is_valid != 0);
630
631 if (width == 0)
632 return "vmov.f32\t%q0, %1 @ <mode>";
633 else
634 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
635 return templ;
636 }
637 switch (which_alternative)
638 {
639 case 0:
640 return "vmov\t%q0, %q1";
641 case 1:
642 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
643 case 2:
644 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
645 case 4:
646 if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
647 || (MEM_P (operands[1])
648 && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
649 return output_move_neon (operands);
650 else
651 return "vldrb.8 %q0, %E1";
652 case 5:
653 return output_move_neon (operands);
654 case 7:
655 return "vstrb.8 %q1, %E0";
656 default:
657 gcc_unreachable ();
658 return "";
659 }
660}
661 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
662 (set_attr "length" "4,8,8,4,8,8,4,4")
663 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
664 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
665
666(define_insn "*mve_mov<mode>"
667 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
668 (vec_duplicate:MVE_types
669 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
670 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
671{
672 if (which_alternative == 0)
673 return "vdup.<V_sz_elem>\t%q0, %1";
674 return "vmov.<V_sz_elem>\t%q0, %1";
675}
676 [(set_attr "length" "4,4")
677 (set_attr "type" "mve_move,mve_move")])
14782c81
SP		 678
679;;
680;; [vst4q])
681;;
682(define_insn "mve_vst4q<mode>"
683 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
684 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
685 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
686 VST4Q))
687 ]
688 "TARGET_HAVE_MVE"
689{
690 rtx ops[6];
691 int regno = REGNO (operands[1]);
692 ops[0] = gen_rtx_REG (TImode, regno);
693 ops[1] = gen_rtx_REG (TImode, regno+4);
694 ops[2] = gen_rtx_REG (TImode, regno+8);
695 ops[3] = gen_rtx_REG (TImode, regno+12);
696 rtx reg = operands[0];
697 while (reg && !REG_P (reg))
698 reg = XEXP (reg, 0);
699 gcc_assert (REG_P (reg));
700 ops[4] = reg;
701 ops[5] = operands[0];
702 /* Here in first three instructions data is stored to ops[4]'s location but
703 in the fourth instruction data is stored to operands[0], this is to
704 support the writeback. */
705 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
706 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
707 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
708 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
709 return "";
710}
711 [(set_attr "length" "16")])
a50f6abf 712
e3678b44
SP		 713;;
714;; [vrndq_m_f])
715;;
716(define_insn "mve_vrndq_m_f<mode>"
717 [
718 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
719 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
720 (match_operand:MVE_0 2 "s_register_operand" "w")
721 (match_operand:HI 3 "vpr_register_operand" "Up")]
722 VRNDQ_M_F))
723 ]
724 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
725 "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
726 [(set_attr "type" "mve_move")
727 (set_attr "length""8")])
728
a50f6abf
SP		 729;;
730;; [vrndxq_f])
731;;
732(define_insn "mve_vrndxq_f<mode>"
733 [
734 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
735 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
736 VRNDXQ_F))
737 ]
738 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
739 "vrintx.f%#<V_sz_elem> %q0, %q1"
740 [(set_attr "type" "mve_move")
741])
742
743;;
744;; [vrndq_f])
745;;
746(define_insn "mve_vrndq_f<mode>"
747 [
748 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
749 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
750 VRNDQ_F))
751 ]
752 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
753 "vrintz.f%#<V_sz_elem> %q0, %q1"
754 [(set_attr "type" "mve_move")
755])
756
757;;
758;; [vrndpq_f])
759;;
760(define_insn "mve_vrndpq_f<mode>"
761 [
762 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
763 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
764 VRNDPQ_F))
765 ]
766 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
767 "vrintp.f%#<V_sz_elem> %q0, %q1"
768 [(set_attr "type" "mve_move")
769])
770
771;;
772;; [vrndnq_f])
773;;
774(define_insn "mve_vrndnq_f<mode>"
775 [
776 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
777 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
778 VRNDNQ_F))
779 ]
780 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
781 "vrintn.f%#<V_sz_elem> %q0, %q1"
782 [(set_attr "type" "mve_move")
783])
784
785;;
786;; [vrndmq_f])
787;;
788(define_insn "mve_vrndmq_f<mode>"
789 [
790 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
791 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
792 VRNDMQ_F))
793 ]
794 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
795 "vrintm.f%#<V_sz_elem> %q0, %q1"
796 [(set_attr "type" "mve_move")
797])
798
799;;
800;; [vrndaq_f])
801;;
802(define_insn "mve_vrndaq_f<mode>"
803 [
804 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
805 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
806 VRNDAQ_F))
807 ]
808 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
809 "vrinta.f%#<V_sz_elem> %q0, %q1"
810 [(set_attr "type" "mve_move")
811])
812
813;;
814;; [vrev64q_f])
815;;
816(define_insn "mve_vrev64q_f<mode>"
817 [
818 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
819 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
820 VREV64Q_F))
821 ]
822 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
823 "vrev64.%#<V_sz_elem> %q0, %q1"
824 [(set_attr "type" "mve_move")
825])
826
827;;
828;; [vnegq_f])
829;;
830(define_insn "mve_vnegq_f<mode>"
831 [
832 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
833 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
834 VNEGQ_F))
835 ]
836 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
837 "vneg.f%#<V_sz_elem> %q0, %q1"
838 [(set_attr "type" "mve_move")
839])
840
841;;
842;; [vdupq_n_f])
843;;
844(define_insn "mve_vdupq_n_f<mode>"
845 [
846 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
847 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
848 VDUPQ_N_F))
849 ]
850 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
851 "vdup.%#<V_sz_elem> %q0, %1"
852 [(set_attr "type" "mve_move")
853])
854
855;;
856;; [vabsq_f])
857;;
858(define_insn "mve_vabsq_f<mode>"
859 [
860 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
861 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
862 VABSQ_F))
863 ]
864 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
865 "vabs.f%#<V_sz_elem> %q0, %q1"
866 [(set_attr "type" "mve_move")
867])
868
869;;
870;; [vrev32q_f])
871;;
872(define_insn "mve_vrev32q_fv8hf"
873 [
874 (set (match_operand:V8HF 0 "s_register_operand" "=w")
875 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
876 VREV32Q_F))
877 ]
878 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
879 "vrev32.16 %q0, %q1"
880 [(set_attr "type" "mve_move")
881])
882;;
883;; [vcvttq_f32_f16])
884;;
885(define_insn "mve_vcvttq_f32_f16v4sf"
886 [
887 (set (match_operand:V4SF 0 "s_register_operand" "=w")
888 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
889 VCVTTQ_F32_F16))
890 ]
891 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
892 "vcvtt.f32.f16 %q0, %q1"
893 [(set_attr "type" "mve_move")
894])
895
896;;
897;; [vcvtbq_f32_f16])
898;;
899(define_insn "mve_vcvtbq_f32_f16v4sf"
900 [
901 (set (match_operand:V4SF 0 "s_register_operand" "=w")
902 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
903 VCVTBQ_F32_F16))
904 ]
905 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
906 "vcvtb.f32.f16 %q0, %q1"
907 [(set_attr "type" "mve_move")
908])
909
910;;
911;; [vcvtq_to_f_s, vcvtq_to_f_u])
912;;
913(define_insn "mve_vcvtq_to_f_<supf><mode>"
914 [
915 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
916 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
917 VCVTQ_TO_F))
918 ]
919 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
920 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
921 [(set_attr "type" "mve_move")
922])
5db0eb95
SP		 923
924;;
925;; [vrev64q_u, vrev64q_s])
926;;
927(define_insn "mve_vrev64q_<supf><mode>"
928 [
929 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
930 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
931 VREV64Q))
932 ]
933 "TARGET_HAVE_MVE"
934 "vrev64.%#<V_sz_elem> %q0, %q1"
935 [(set_attr "type" "mve_move")
936])
937
938;;
939;; [vcvtq_from_f_s, vcvtq_from_f_u])
940;;
941(define_insn "mve_vcvtq_from_f_<supf><mode>"
942 [
943 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
944 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
945 VCVTQ_FROM_F))
946 ]
947 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
948 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
949 [(set_attr "type" "mve_move")
950])
6df4618c
SP		 951;; [vqnegq_s])
952;;
953(define_insn "mve_vqnegq_s<mode>"
954 [
955 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
956 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
957 VQNEGQ_S))
958 ]
959 "TARGET_HAVE_MVE"
960 "vqneg.s%#<V_sz_elem> %q0, %q1"
961 [(set_attr "type" "mve_move")
962])
963
964;;
965;; [vqabsq_s])
966;;
967(define_insn "mve_vqabsq_s<mode>"
968 [
969 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
970 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
971 VQABSQ_S))
972 ]
973 "TARGET_HAVE_MVE"
974 "vqabs.s%#<V_sz_elem> %q0, %q1"
975 [(set_attr "type" "mve_move")
976])
977
978;;
979;; [vnegq_s])
980;;
981(define_insn "mve_vnegq_s<mode>"
982 [
983 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
984 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
985 VNEGQ_S))
986 ]
987 "TARGET_HAVE_MVE"
988 "vneg.s%#<V_sz_elem> %q0, %q1"
989 [(set_attr "type" "mve_move")
990])
991
992;;
993;; [vmvnq_u, vmvnq_s])
994;;
995(define_insn "mve_vmvnq_<supf><mode>"
996 [
997 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
998 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
999 VMVNQ))
1000 ]
1001 "TARGET_HAVE_MVE"
1002 "vmvn %q0, %q1"
1003 [(set_attr "type" "mve_move")
1004])
1005
1006;;
1007;; [vdupq_n_u, vdupq_n_s])
1008;;
1009(define_insn "mve_vdupq_n_<supf><mode>"
1010 [
1011 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1012 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
1013 VDUPQ_N))
1014 ]
1015 "TARGET_HAVE_MVE"
1016 "vdup.%#<V_sz_elem> %q0, %1"
1017 [(set_attr "type" "mve_move")
1018])
1019
1020;;
1021;; [vclzq_u, vclzq_s])
1022;;
1023(define_insn "mve_vclzq_<supf><mode>"
1024 [
1025 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1026 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1027 VCLZQ))
1028 ]
1029 "TARGET_HAVE_MVE"
1030 "vclz.i%#<V_sz_elem> %q0, %q1"
1031 [(set_attr "type" "mve_move")
1032])
1033
1034;;
1035;; [vclsq_s])
1036;;
1037(define_insn "mve_vclsq_s<mode>"
1038 [
1039 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1040 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1041 VCLSQ_S))
1042 ]
1043 "TARGET_HAVE_MVE"
1044 "vcls.s%#<V_sz_elem> %q0, %q1"
1045 [(set_attr "type" "mve_move")
1046])
1047
1048;;
1049;; [vaddvq_s, vaddvq_u])
1050;;
1051(define_insn "mve_vaddvq_<supf><mode>"
1052 [
1053 (set (match_operand:SI 0 "s_register_operand" "=e")
1054 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
1055 VADDVQ))
1056 ]
1057 "TARGET_HAVE_MVE"
1058 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
1059 [(set_attr "type" "mve_move")
1060])
1061
1062;;
1063;; [vabsq_s])
1064;;
1065(define_insn "mve_vabsq_s<mode>"
1066 [
1067 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1068 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1069 VABSQ_S))
1070 ]
1071 "TARGET_HAVE_MVE"
1072 "vabs.s%#<V_sz_elem>\t%q0, %q1"
1073 [(set_attr "type" "mve_move")
1074])
1075
1076;;
1077;; [vrev32q_u, vrev32q_s])
1078;;
1079(define_insn "mve_vrev32q_<supf><mode>"
1080 [
1081 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
1082 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
1083 VREV32Q))
1084 ]
1085 "TARGET_HAVE_MVE"
1086 "vrev32.%#<V_sz_elem>\t%q0, %q1"
1087 [(set_attr "type" "mve_move")
1088])
1089
1090;;
1091;; [vmovltq_u, vmovltq_s])
1092;;
1093(define_insn "mve_vmovltq_<supf><mode>"
1094 [
1095 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1096 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1097 VMOVLTQ))
1098 ]
1099 "TARGET_HAVE_MVE"
1100 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
1101 [(set_attr "type" "mve_move")
1102])
1103
1104;;
1105;; [vmovlbq_s, vmovlbq_u])
1106;;
1107(define_insn "mve_vmovlbq_<supf><mode>"
1108 [
1109 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1110 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1111 VMOVLBQ))
1112 ]
1113 "TARGET_HAVE_MVE"
1114 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
1115 [(set_attr "type" "mve_move")
1116])
1117
1118;;
1119;; [vcvtpq_s, vcvtpq_u])
1120;;
1121(define_insn "mve_vcvtpq_<supf><mode>"
1122 [
1123 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1124 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1125 VCVTPQ))
1126 ]
1127 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1128 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1129 [(set_attr "type" "mve_move")
1130])
1131
1132;;
1133;; [vcvtnq_s, vcvtnq_u])
1134;;
1135(define_insn "mve_vcvtnq_<supf><mode>"
1136 [
1137 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1138 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1139 VCVTNQ))
1140 ]
1141 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1142 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1143 [(set_attr "type" "mve_move")
1144])
1145
1146;;
1147;; [vcvtmq_s, vcvtmq_u])
1148;;
1149(define_insn "mve_vcvtmq_<supf><mode>"
1150 [
1151 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1152 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1153 VCVTMQ))
1154 ]
1155 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1156 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1157 [(set_attr "type" "mve_move")
1158])
1159
1160;;
1161;; [vcvtaq_u, vcvtaq_s])
1162;;
1163(define_insn "mve_vcvtaq_<supf><mode>"
1164 [
1165 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1166 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1167 VCVTAQ))
1168 ]
1169 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1170 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1171 [(set_attr "type" "mve_move")
1172])
5db0eb95
SP		 1173
1174;;
1175;; [vmvnq_n_u, vmvnq_n_s])
1176;;
1177(define_insn "mve_vmvnq_n_<supf><mode>"
1178 [
1179 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1180 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
1181 VMVNQ_N))
1182 ]
1183 "TARGET_HAVE_MVE"
1184 "vmvn.i%#<V_sz_elem> %q0, %1"
1185 [(set_attr "type" "mve_move")
1186])
6df4618c
SP		 1187
1188;;
1189;; [vrev16q_u, vrev16q_s])
1190;;
1191(define_insn "mve_vrev16q_<supf>v16qi"
1192 [
1193 (set (match_operand:V16QI 0 "s_register_operand" "=w")
1194 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
1195 VREV16Q))
1196 ]
1197 "TARGET_HAVE_MVE"
1198 "vrev16.8 %q0, %q1"
1199 [(set_attr "type" "mve_move")
1200])
1201
1202;;
1203;; [vaddlvq_s vaddlvq_u])
1204;;
1205(define_insn "mve_vaddlvq_<supf>v4si"
1206 [
1207 (set (match_operand:DI 0 "s_register_operand" "=r")
1208 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
1209 VADDLVQ))
1210 ]
1211 "TARGET_HAVE_MVE"
1212 "vaddlv.<supf>32 %Q0, %R0, %q1"
1213 [(set_attr "type" "mve_move")
1214])
a475f153
SP		 1215
1216;;
1217;; [vctp8q vctp16q vctp32q vctp64q])
1218;;
1219(define_insn "mve_vctp<mode1>qhi"
1220 [
1221 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1222 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
1223 VCTPQ))
1224 ]
1225 "TARGET_HAVE_MVE"
1226 "vctp.<mode1> %1"
1227 [(set_attr "type" "mve_move")
1228])
1229
1230;;
1231;; [vpnot])
1232;;
1233(define_insn "mve_vpnothi"
1234 [
1235 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1236 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
1237 VPNOT))
1238 ]
1239 "TARGET_HAVE_MVE"
1240 "vpnot"
1241 [(set_attr "type" "mve_move")
1242])
4be8cf77
SP		 1243
1244;;
1245;; [vsubq_n_f])
1246;;
1247(define_insn "mve_vsubq_n_f<mode>"
1248 [
1249 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1250 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1251 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1252 VSUBQ_N_F))
1253 ]
1254 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1255 "vsub.f<V_sz_elem> %q0, %q1, %2"
1256 [(set_attr "type" "mve_move")
1257])
1258
1259;;
1260;; [vbrsrq_n_f])
1261;;
1262(define_insn "mve_vbrsrq_n_f<mode>"
1263 [
1264 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1265 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1266 (match_operand:SI 2 "s_register_operand" "r")]
1267 VBRSRQ_N_F))
1268 ]
1269 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1270 "vbrsr.<V_sz_elem> %q0, %q1, %2"
1271 [(set_attr "type" "mve_move")
1272])
1273
1274;;
1275;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
1276;;
1277(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
1278 [
1279 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1280 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1281 (match_operand:SI 2 "mve_imm_16" "Rd")]
1282 VCVTQ_N_TO_F))
1283 ]
1284 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1285 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
1286 [(set_attr "type" "mve_move")
1287])
1288
1289;; [vcreateq_f])
1290;;
1291(define_insn "mve_vcreateq_f<mode>"
1292 [
1293 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1294 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
1295 (match_operand:DI 2 "s_register_operand" "r")]
1296 VCREATEQ_F))
1297 ]
1298 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1299 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1300 [(set_attr "type" "mve_move")
1301 (set_attr "length""8")])
f166a8cd
SP		 1302
1303;;
1304;; [vcreateq_u, vcreateq_s])
1305;;
1306(define_insn "mve_vcreateq_<supf><mode>"
1307 [
1308 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1309 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
1310 (match_operand:DI 2 "s_register_operand" "r")]
1311 VCREATEQ))
1312 ]
1313 "TARGET_HAVE_MVE"
1314 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1315 [(set_attr "type" "mve_move")
1316 (set_attr "length""8")])
1317
1318;;
1319;; [vshrq_n_s, vshrq_n_u])
1320;;
1321(define_insn "mve_vshrq_n_<supf><mode>"
1322 [
1323 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1324 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1325 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1326 VSHRQ_N))
1327 ]
1328 "TARGET_HAVE_MVE"
1329 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
1330 [(set_attr "type" "mve_move")
1331])
1332
1333;;
1334;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
1335;;
1336(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
1337 [
1338 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1339 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1340 (match_operand:SI 2 "mve_imm_16" "Rd")]
1341 VCVTQ_N_FROM_F))
1342 ]
1343 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1344 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
1345 [(set_attr "type" "mve_move")
1346])
d71dba7b
SP		 1347
1348;;
1349;; [vaddlvq_p_s])
1350;;
1351(define_insn "mve_vaddlvq_p_<supf>v4si"
1352 [
1353 (set (match_operand:DI 0 "s_register_operand" "=r")
1354 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1355 (match_operand:HI 2 "vpr_register_operand" "Up")]
1356 VADDLVQ_P))
1357 ]
1358 "TARGET_HAVE_MVE"
1359 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
1360 [(set_attr "type" "mve_move")
1361 (set_attr "length""8")])
1362
1363;;
1364;; [vcmpneq_u, vcmpneq_s])
1365;;
1366(define_insn "mve_vcmpneq_<supf><mode>"
1367 [
1368 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1369 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1370 (match_operand:MVE_2 2 "s_register_operand" "w")]
1371 VCMPNEQ))
1372 ]
1373 "TARGET_HAVE_MVE"
1374 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
1375 [(set_attr "type" "mve_move")
1376])
1377
1378;;
1379;; [vshlq_s, vshlq_u])
1380;;
1381(define_insn "mve_vshlq_<supf><mode>"
1382 [
1383 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1384 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1385 (match_operand:MVE_2 2 "s_register_operand" "w")]
1386 VSHLQ))
1387 ]
1388 "TARGET_HAVE_MVE"
1389 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1390 [(set_attr "type" "mve_move")
1391])
33203b4c
SP		 1392
1393;;
1394;; [vabdq_s, vabdq_u])
1395;;
1396(define_insn "mve_vabdq_<supf><mode>"
1397 [
1398 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1399 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1400 (match_operand:MVE_2 2 "s_register_operand" "w")]
1401 VABDQ))
1402 ]
1403 "TARGET_HAVE_MVE"
1404 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
1405 [(set_attr "type" "mve_move")
1406])
1407
1408;;
1409;; [vaddq_n_s, vaddq_n_u])
1410;;
1411(define_insn "mve_vaddq_n_<supf><mode>"
1412 [
1413 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1414 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1415 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1416 VADDQ_N))
1417 ]
1418 "TARGET_HAVE_MVE"
1419 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
1420 [(set_attr "type" "mve_move")
1421])
1422
1423;;
1424;; [vaddvaq_s, vaddvaq_u])
1425;;
1426(define_insn "mve_vaddvaq_<supf><mode>"
1427 [
1428 (set (match_operand:SI 0 "s_register_operand" "=e")
1429 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1430 (match_operand:MVE_2 2 "s_register_operand" "w")]
1431 VADDVAQ))
1432 ]
1433 "TARGET_HAVE_MVE"
1434 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
1435 [(set_attr "type" "mve_move")
1436])
1437
1438;;
1439;; [vaddvq_p_u, vaddvq_p_s])
1440;;
1441(define_insn "mve_vaddvq_p_<supf><mode>"
1442 [
1443 (set (match_operand:SI 0 "s_register_operand" "=e")
1444 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1445 (match_operand:HI 2 "vpr_register_operand" "Up")]
1446 VADDVQ_P))
1447 ]
1448 "TARGET_HAVE_MVE"
1449 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
1450 [(set_attr "type" "mve_move")
1451 (set_attr "length""8")])
1452
1453;;
1454;; [vandq_u, vandq_s])
1455;;
1456(define_insn "mve_vandq_<supf><mode>"
1457 [
1458 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1459 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1460 (match_operand:MVE_2 2 "s_register_operand" "w")]
1461 VANDQ))
1462 ]
1463 "TARGET_HAVE_MVE"
1464 "vand %q0, %q1, %q2"
1465 [(set_attr "type" "mve_move")
1466])
1467
1468;;
1469;; [vbicq_s, vbicq_u])
1470;;
1471(define_insn "mve_vbicq_<supf><mode>"
1472 [
1473 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1474 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1475 (match_operand:MVE_2 2 "s_register_operand" "w")]
1476 VBICQ))
1477 ]
1478 "TARGET_HAVE_MVE"
1479 "vbic %q0, %q1, %q2"
1480 [(set_attr "type" "mve_move")
1481])
1482
1483;;
1484;; [vbrsrq_n_u, vbrsrq_n_s])
1485;;
1486(define_insn "mve_vbrsrq_n_<supf><mode>"
1487 [
1488 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1489 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1490 (match_operand:SI 2 "s_register_operand" "r")]
1491 VBRSRQ_N))
1492 ]
1493 "TARGET_HAVE_MVE"
1494 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
1495 [(set_attr "type" "mve_move")
1496])
1497
1498;;
1499;; [vcaddq_rot270_s, vcaddq_rot270_u])
1500;;
1501(define_insn "mve_vcaddq_rot270_<supf><mode>"
1502 [
1503 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1504 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1505 (match_operand:MVE_2 2 "s_register_operand" "w")]
1506 VCADDQ_ROT270))
1507 ]
1508 "TARGET_HAVE_MVE"
1509 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1510 [(set_attr "type" "mve_move")
1511])
1512
1513;;
1514;; [vcaddq_rot90_u, vcaddq_rot90_s])
1515;;
1516(define_insn "mve_vcaddq_rot90_<supf><mode>"
1517 [
1518 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1519 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1520 (match_operand:MVE_2 2 "s_register_operand" "w")]
1521 VCADDQ_ROT90))
1522 ]
1523 "TARGET_HAVE_MVE"
1524 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1525 [(set_attr "type" "mve_move")
1526])
1527
1528;;
1529;; [vcmpcsq_n_u])
1530;;
1531(define_insn "mve_vcmpcsq_n_u<mode>"
1532 [
1533 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1534 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1535 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1536 VCMPCSQ_N_U))
1537 ]
1538 "TARGET_HAVE_MVE"
1539 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1540 [(set_attr "type" "mve_move")
1541])
1542
1543;;
1544;; [vcmpcsq_u])
1545;;
1546(define_insn "mve_vcmpcsq_u<mode>"
1547 [
1548 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1549 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1550 (match_operand:MVE_2 2 "s_register_operand" "w")]
1551 VCMPCSQ_U))
1552 ]
1553 "TARGET_HAVE_MVE"
1554 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1555 [(set_attr "type" "mve_move")
1556])
1557
1558;;
1559;; [vcmpeqq_n_s, vcmpeqq_n_u])
1560;;
1561(define_insn "mve_vcmpeqq_n_<supf><mode>"
1562 [
1563 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1564 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1565 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1566 VCMPEQQ_N))
1567 ]
1568 "TARGET_HAVE_MVE"
1569 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1570 [(set_attr "type" "mve_move")
1571])
1572
1573;;
1574;; [vcmpeqq_u, vcmpeqq_s])
1575;;
1576(define_insn "mve_vcmpeqq_<supf><mode>"
1577 [
1578 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1579 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1580 (match_operand:MVE_2 2 "s_register_operand" "w")]
1581 VCMPEQQ))
1582 ]
1583 "TARGET_HAVE_MVE"
1584 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1585 [(set_attr "type" "mve_move")
1586])
1587
1588;;
1589;; [vcmpgeq_n_s])
1590;;
1591(define_insn "mve_vcmpgeq_n_s<mode>"
1592 [
1593 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1594 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1595 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1596 VCMPGEQ_N_S))
1597 ]
1598 "TARGET_HAVE_MVE"
1599 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1600 [(set_attr "type" "mve_move")
1601])
1602
1603;;
1604;; [vcmpgeq_s])
1605;;
1606(define_insn "mve_vcmpgeq_s<mode>"
1607 [
1608 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1609 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1610 (match_operand:MVE_2 2 "s_register_operand" "w")]
1611 VCMPGEQ_S))
1612 ]
1613 "TARGET_HAVE_MVE"
1614 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1615 [(set_attr "type" "mve_move")
1616])
1617
1618;;
1619;; [vcmpgtq_n_s])
1620;;
1621(define_insn "mve_vcmpgtq_n_s<mode>"
1622 [
1623 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1624 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1625 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1626 VCMPGTQ_N_S))
1627 ]
1628 "TARGET_HAVE_MVE"
1629 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1630 [(set_attr "type" "mve_move")
1631])
1632
1633;;
1634;; [vcmpgtq_s])
1635;;
1636(define_insn "mve_vcmpgtq_s<mode>"
1637 [
1638 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1639 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1640 (match_operand:MVE_2 2 "s_register_operand" "w")]
1641 VCMPGTQ_S))
1642 ]
1643 "TARGET_HAVE_MVE"
1644 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1645 [(set_attr "type" "mve_move")
1646])
1647
1648;;
1649;; [vcmphiq_n_u])
1650;;
1651(define_insn "mve_vcmphiq_n_u<mode>"
1652 [
1653 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1654 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1655 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1656 VCMPHIQ_N_U))
1657 ]
1658 "TARGET_HAVE_MVE"
1659 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1660 [(set_attr "type" "mve_move")
1661])
1662
1663;;
1664;; [vcmphiq_u])
1665;;
1666(define_insn "mve_vcmphiq_u<mode>"
1667 [
1668 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1669 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1670 (match_operand:MVE_2 2 "s_register_operand" "w")]
1671 VCMPHIQ_U))
1672 ]
1673 "TARGET_HAVE_MVE"
1674 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1675 [(set_attr "type" "mve_move")
1676])
1677
1678;;
1679;; [vcmpleq_n_s])
1680;;
1681(define_insn "mve_vcmpleq_n_s<mode>"
1682 [
1683 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1684 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1685 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1686 VCMPLEQ_N_S))
1687 ]
1688 "TARGET_HAVE_MVE"
1689 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1690 [(set_attr "type" "mve_move")
1691])
1692
1693;;
1694;; [vcmpleq_s])
1695;;
1696(define_insn "mve_vcmpleq_s<mode>"
1697 [
1698 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1699 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1700 (match_operand:MVE_2 2 "s_register_operand" "w")]
1701 VCMPLEQ_S))
1702 ]
1703 "TARGET_HAVE_MVE"
1704 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1705 [(set_attr "type" "mve_move")
1706])
1707
1708;;
1709;; [vcmpltq_n_s])
1710;;
1711(define_insn "mve_vcmpltq_n_s<mode>"
1712 [
1713 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1714 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1715 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1716 VCMPLTQ_N_S))
1717 ]
1718 "TARGET_HAVE_MVE"
1719 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1720 [(set_attr "type" "mve_move")
1721])
1722
1723;;
1724;; [vcmpltq_s])
1725;;
1726(define_insn "mve_vcmpltq_s<mode>"
1727 [
1728 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1729 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1730 (match_operand:MVE_2 2 "s_register_operand" "w")]
1731 VCMPLTQ_S))
1732 ]
1733 "TARGET_HAVE_MVE"
1734 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1735 [(set_attr "type" "mve_move")
1736])
1737
1738;;
1739;; [vcmpneq_n_u, vcmpneq_n_s])
1740;;
1741(define_insn "mve_vcmpneq_n_<supf><mode>"
1742 [
1743 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1744 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1745 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1746 VCMPNEQ_N))
1747 ]
1748 "TARGET_HAVE_MVE"
1749 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1750 [(set_attr "type" "mve_move")
1751])
1752
1753;;
1754;; [veorq_u, veorq_s])
1755;;
1756(define_insn "mve_veorq_<supf><mode>"
1757 [
1758 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1759 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1760 (match_operand:MVE_2 2 "s_register_operand" "w")]
1761 VEORQ))
1762 ]
1763 "TARGET_HAVE_MVE"
1764 "veor %q0, %q1, %q2"
1765 [(set_attr "type" "mve_move")
1766])
1767
1768;;
1769;; [vhaddq_n_u, vhaddq_n_s])
1770;;
1771(define_insn "mve_vhaddq_n_<supf><mode>"
1772 [
1773 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1774 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1775 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1776 VHADDQ_N))
1777 ]
1778 "TARGET_HAVE_MVE"
1779 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1780 [(set_attr "type" "mve_move")
1781])
1782
1783;;
1784;; [vhaddq_s, vhaddq_u])
1785;;
1786(define_insn "mve_vhaddq_<supf><mode>"
1787 [
1788 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1789 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1790 (match_operand:MVE_2 2 "s_register_operand" "w")]
1791 VHADDQ))
1792 ]
1793 "TARGET_HAVE_MVE"
1794 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1795 [(set_attr "type" "mve_move")
1796])
1797
1798;;
1799;; [vhcaddq_rot270_s])
1800;;
1801(define_insn "mve_vhcaddq_rot270_s<mode>"
1802 [
1803 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1804 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1805 (match_operand:MVE_2 2 "s_register_operand" "w")]
1806 VHCADDQ_ROT270_S))
1807 ]
1808 "TARGET_HAVE_MVE"
1809 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1810 [(set_attr "type" "mve_move")
1811])
1812
1813;;
1814;; [vhcaddq_rot90_s])
1815;;
1816(define_insn "mve_vhcaddq_rot90_s<mode>"
1817 [
1818 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1819 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1820 (match_operand:MVE_2 2 "s_register_operand" "w")]
1821 VHCADDQ_ROT90_S))
1822 ]
1823 "TARGET_HAVE_MVE"
1824 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1825 [(set_attr "type" "mve_move")
1826])
1827
1828;;
1829;; [vhsubq_n_u, vhsubq_n_s])
1830;;
1831(define_insn "mve_vhsubq_n_<supf><mode>"
1832 [
1833 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1834 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1835 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1836 VHSUBQ_N))
1837 ]
1838 "TARGET_HAVE_MVE"
1839 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1840 [(set_attr "type" "mve_move")
1841])
1842
1843;;
1844;; [vhsubq_s, vhsubq_u])
1845;;
1846(define_insn "mve_vhsubq_<supf><mode>"
1847 [
1848 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1849 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1850 (match_operand:MVE_2 2 "s_register_operand" "w")]
1851 VHSUBQ))
1852 ]
1853 "TARGET_HAVE_MVE"
1854 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1855 [(set_attr "type" "mve_move")
1856])
1857
1858;;
1859;; [vmaxaq_s])
1860;;
1861(define_insn "mve_vmaxaq_s<mode>"
1862 [
1863 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1864 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1865 (match_operand:MVE_2 2 "s_register_operand" "w")]
1866 VMAXAQ_S))
1867 ]
1868 "TARGET_HAVE_MVE"
1869 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1870 [(set_attr "type" "mve_move")
1871])
1872
1873;;
1874;; [vmaxavq_s])
1875;;
1876(define_insn "mve_vmaxavq_s<mode>"
1877 [
1878 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1879 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1880 (match_operand:MVE_2 2 "s_register_operand" "w")]
1881 VMAXAVQ_S))
1882 ]
1883 "TARGET_HAVE_MVE"
1884 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1885 [(set_attr "type" "mve_move")
1886])
1887
1888;;
1889;; [vmaxq_u, vmaxq_s])
1890;;
1891(define_insn "mve_vmaxq_<supf><mode>"
1892 [
1893 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1894 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1895 (match_operand:MVE_2 2 "s_register_operand" "w")]
1896 VMAXQ))
1897 ]
1898 "TARGET_HAVE_MVE"
1899 "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1900 [(set_attr "type" "mve_move")
1901])
1902
1903;;
1904;; [vmaxvq_u, vmaxvq_s])
1905;;
1906(define_insn "mve_vmaxvq_<supf><mode>"
1907 [
1908 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1909 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1910 (match_operand:MVE_2 2 "s_register_operand" "w")]
1911 VMAXVQ))
1912 ]
1913 "TARGET_HAVE_MVE"
1914 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1915 [(set_attr "type" "mve_move")
1916])
1917
1918;;
1919;; [vminaq_s])
1920;;
1921(define_insn "mve_vminaq_s<mode>"
1922 [
1923 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1924 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1925 (match_operand:MVE_2 2 "s_register_operand" "w")]
1926 VMINAQ_S))
1927 ]
1928 "TARGET_HAVE_MVE"
1929 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1930 [(set_attr "type" "mve_move")
1931])
1932
1933;;
1934;; [vminavq_s])
1935;;
1936(define_insn "mve_vminavq_s<mode>"
1937 [
1938 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1939 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1940 (match_operand:MVE_2 2 "s_register_operand" "w")]
1941 VMINAVQ_S))
1942 ]
1943 "TARGET_HAVE_MVE"
1944 "vminav.s%#<V_sz_elem>\t%0, %q2"
1945 [(set_attr "type" "mve_move")
1946])
1947
1948;;
1949;; [vminq_s, vminq_u])
1950;;
1951(define_insn "mve_vminq_<supf><mode>"
1952 [
1953 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1954 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1955 (match_operand:MVE_2 2 "s_register_operand" "w")]
1956 VMINQ))
1957 ]
1958 "TARGET_HAVE_MVE"
1959 "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1960 [(set_attr "type" "mve_move")
1961])
1962
1963;;
1964;; [vminvq_u, vminvq_s])
1965;;
1966(define_insn "mve_vminvq_<supf><mode>"
1967 [
1968 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1969 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1970 (match_operand:MVE_2 2 "s_register_operand" "w")]
1971 VMINVQ))
1972 ]
1973 "TARGET_HAVE_MVE"
1974 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1975 [(set_attr "type" "mve_move")
1976])
1977
1978;;
1979;; [vmladavq_u, vmladavq_s])
1980;;
1981(define_insn "mve_vmladavq_<supf><mode>"
1982 [
1983 (set (match_operand:SI 0 "s_register_operand" "=e")
1984 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1985 (match_operand:MVE_2 2 "s_register_operand" "w")]
1986 VMLADAVQ))
1987 ]
1988 "TARGET_HAVE_MVE"
1989 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1990 [(set_attr "type" "mve_move")
1991])
1992
1993;;
1994;; [vmladavxq_s])
1995;;
1996(define_insn "mve_vmladavxq_s<mode>"
1997 [
1998 (set (match_operand:SI 0 "s_register_operand" "=e")
1999 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2000 (match_operand:MVE_2 2 "s_register_operand" "w")]
2001 VMLADAVXQ_S))
2002 ]
2003 "TARGET_HAVE_MVE"
2004 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
2005 [(set_attr "type" "mve_move")
2006])
2007
2008;;
2009;; [vmlsdavq_s])
2010;;
2011(define_insn "mve_vmlsdavq_s<mode>"
2012 [
2013 (set (match_operand:SI 0 "s_register_operand" "=e")
2014 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2015 (match_operand:MVE_2 2 "s_register_operand" "w")]
2016 VMLSDAVQ_S))
2017 ]
2018 "TARGET_HAVE_MVE"
2019 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
2020 [(set_attr "type" "mve_move")
2021])
2022
2023;;
2024;; [vmlsdavxq_s])
2025;;
2026(define_insn "mve_vmlsdavxq_s<mode>"
2027 [
2028 (set (match_operand:SI 0 "s_register_operand" "=e")
2029 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2030 (match_operand:MVE_2 2 "s_register_operand" "w")]
2031 VMLSDAVXQ_S))
2032 ]
2033 "TARGET_HAVE_MVE"
2034 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
2035 [(set_attr "type" "mve_move")
2036])
2037
2038;;
2039;; [vmulhq_s, vmulhq_u])
2040;;
2041(define_insn "mve_vmulhq_<supf><mode>"
2042 [
2043 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2044 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2045 (match_operand:MVE_2 2 "s_register_operand" "w")]
2046 VMULHQ))
2047 ]
2048 "TARGET_HAVE_MVE"
2049 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2050 [(set_attr "type" "mve_move")
2051])
2052
2053;;
2054;; [vmullbq_int_u, vmullbq_int_s])
2055;;
2056(define_insn "mve_vmullbq_int_<supf><mode>"
2057 [
2058 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2059 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2060 (match_operand:MVE_2 2 "s_register_operand" "w")]
2061 VMULLBQ_INT))
2062 ]
2063 "TARGET_HAVE_MVE"
2064 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2065 [(set_attr "type" "mve_move")
2066])
2067
2068;;
2069;; [vmulltq_int_u, vmulltq_int_s])
2070;;
2071(define_insn "mve_vmulltq_int_<supf><mode>"
2072 [
2073 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2074 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2075 (match_operand:MVE_2 2 "s_register_operand" "w")]
2076 VMULLTQ_INT))
2077 ]
2078 "TARGET_HAVE_MVE"
2079 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2080 [(set_attr "type" "mve_move")
2081])
2082
2083;;
2084;; [vmulq_n_u, vmulq_n_s])
2085;;
2086(define_insn "mve_vmulq_n_<supf><mode>"
2087 [
2088 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2089 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2090 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2091 VMULQ_N))
2092 ]
2093 "TARGET_HAVE_MVE"
2094 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
2095 [(set_attr "type" "mve_move")
2096])
2097
2098;;
2099;; [vmulq_u, vmulq_s])
2100;;
2101(define_insn "mve_vmulq_<supf><mode>"
2102 [
2103 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2104 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2105 (match_operand:MVE_2 2 "s_register_operand" "w")]
2106 VMULQ))
2107 ]
2108 "TARGET_HAVE_MVE"
2109 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
2110 [(set_attr "type" "mve_move")
2111])
2112
2113;;
2114;; [vornq_u, vornq_s])
2115;;
2116(define_insn "mve_vornq_<supf><mode>"
2117 [
2118 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2119 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2120 (match_operand:MVE_2 2 "s_register_operand" "w")]
2121 VORNQ))
2122 ]
2123 "TARGET_HAVE_MVE"
2124 "vorn %q0, %q1, %q2"
2125 [(set_attr "type" "mve_move")
2126])
2127
2128;;
2129;; [vorrq_s, vorrq_u])
2130;;
2131(define_insn "mve_vorrq_<supf><mode>"
2132 [
2133 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2134 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2135 (match_operand:MVE_2 2 "s_register_operand" "w")]
2136 VORRQ))
2137 ]
2138 "TARGET_HAVE_MVE"
2139 "vorr %q0, %q1, %q2"
2140 [(set_attr "type" "mve_move")
2141])
2142
2143;;
2144;; [vqaddq_n_s, vqaddq_n_u])
2145;;
2146(define_insn "mve_vqaddq_n_<supf><mode>"
2147 [
2148 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2149 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2150 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2151 VQADDQ_N))
2152 ]
2153 "TARGET_HAVE_MVE"
2154 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2155 [(set_attr "type" "mve_move")
2156])
2157
2158;;
2159;; [vqaddq_u, vqaddq_s])
2160;;
2161(define_insn "mve_vqaddq_<supf><mode>"
2162 [
2163 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2164 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2165 (match_operand:MVE_2 2 "s_register_operand" "w")]
2166 VQADDQ))
2167 ]
2168 "TARGET_HAVE_MVE"
2169 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2170 [(set_attr "type" "mve_move")
2171])
2172
2173;;
2174;; [vqdmulhq_n_s])
2175;;
2176(define_insn "mve_vqdmulhq_n_s<mode>"
2177 [
2178 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2179 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2180 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2181 VQDMULHQ_N_S))
2182 ]
2183 "TARGET_HAVE_MVE"
2184 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2185 [(set_attr "type" "mve_move")
2186])
2187
2188;;
2189;; [vqdmulhq_s])
2190;;
2191(define_insn "mve_vqdmulhq_s<mode>"
2192 [
2193 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2194 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2195 (match_operand:MVE_2 2 "s_register_operand" "w")]
2196 VQDMULHQ_S))
2197 ]
2198 "TARGET_HAVE_MVE"
2199 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2200 [(set_attr "type" "mve_move")
2201])
2202
2203;;
2204;; [vqrdmulhq_n_s])
2205;;
2206(define_insn "mve_vqrdmulhq_n_s<mode>"
2207 [
2208 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2209 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2210 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2211 VQRDMULHQ_N_S))
2212 ]
2213 "TARGET_HAVE_MVE"
2214 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2215 [(set_attr "type" "mve_move")
2216])
2217
2218;;
2219;; [vqrdmulhq_s])
2220;;
2221(define_insn "mve_vqrdmulhq_s<mode>"
2222 [
2223 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2224 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2225 (match_operand:MVE_2 2 "s_register_operand" "w")]
2226 VQRDMULHQ_S))
2227 ]
2228 "TARGET_HAVE_MVE"
2229 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2230 [(set_attr "type" "mve_move")
2231])
2232
2233;;
2234;; [vqrshlq_n_s, vqrshlq_n_u])
2235;;
2236(define_insn "mve_vqrshlq_n_<supf><mode>"
2237 [
2238 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2239 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2240 (match_operand:SI 2 "s_register_operand" "r")]
2241 VQRSHLQ_N))
2242 ]
2243 "TARGET_HAVE_MVE"
2244 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2245 [(set_attr "type" "mve_move")
2246])
2247
2248;;
2249;; [vqrshlq_s, vqrshlq_u])
2250;;
2251(define_insn "mve_vqrshlq_<supf><mode>"
2252 [
2253 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2254 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2255 (match_operand:MVE_2 2 "s_register_operand" "w")]
2256 VQRSHLQ))
2257 ]
2258 "TARGET_HAVE_MVE"
2259 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2260 [(set_attr "type" "mve_move")
2261])
2262
2263;;
2264;; [vqshlq_n_s, vqshlq_n_u])
2265;;
2266(define_insn "mve_vqshlq_n_<supf><mode>"
2267 [
2268 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2269 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2270 (match_operand:SI 2 "immediate_operand" "i")]
2271 VQSHLQ_N))
2272 ]
2273 "TARGET_HAVE_MVE"
2274 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2275 [(set_attr "type" "mve_move")
2276])
2277
2278;;
2279;; [vqshlq_r_u, vqshlq_r_s])
2280;;
2281(define_insn "mve_vqshlq_r_<supf><mode>"
2282 [
2283 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2284 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2285 (match_operand:SI 2 "s_register_operand" "r")]
2286 VQSHLQ_R))
2287 ]
2288 "TARGET_HAVE_MVE"
2289 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
2290 [(set_attr "type" "mve_move")
2291])
2292
2293;;
2294;; [vqshlq_s, vqshlq_u])
2295;;
2296(define_insn "mve_vqshlq_<supf><mode>"
2297 [
2298 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2299 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2300 (match_operand:MVE_2 2 "s_register_operand" "w")]
2301 VQSHLQ))
2302 ]
2303 "TARGET_HAVE_MVE"
2304 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2305 [(set_attr "type" "mve_move")
2306])
2307
2308;;
2309;; [vqshluq_n_s])
2310;;
2311(define_insn "mve_vqshluq_n_s<mode>"
2312 [
2313 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2314 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2315 (match_operand:SI 2 "mve_imm_7" "Ra")]
2316 VQSHLUQ_N_S))
2317 ]
2318 "TARGET_HAVE_MVE"
2319 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
2320 [(set_attr "type" "mve_move")
2321])
2322
2323;;
2324;; [vqsubq_n_s, vqsubq_n_u])
2325;;
2326(define_insn "mve_vqsubq_n_<supf><mode>"
2327 [
2328 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2329 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2330 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2331 VQSUBQ_N))
2332 ]
2333 "TARGET_HAVE_MVE"
2334 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2335 [(set_attr "type" "mve_move")
2336])
2337
2338;;
2339;; [vqsubq_u, vqsubq_s])
2340;;
2341(define_insn "mve_vqsubq_<supf><mode>"
2342 [
2343 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2344 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2345 (match_operand:MVE_2 2 "s_register_operand" "w")]
2346 VQSUBQ))
2347 ]
2348 "TARGET_HAVE_MVE"
2349 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2350 [(set_attr "type" "mve_move")
2351])
2352
2353;;
2354;; [vrhaddq_s, vrhaddq_u])
2355;;
2356(define_insn "mve_vrhaddq_<supf><mode>"
2357 [
2358 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2359 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2360 (match_operand:MVE_2 2 "s_register_operand" "w")]
2361 VRHADDQ))
2362 ]
2363 "TARGET_HAVE_MVE"
2364 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2365 [(set_attr "type" "mve_move")
2366])
2367
2368;;
2369;; [vrmulhq_s, vrmulhq_u])
2370;;
2371(define_insn "mve_vrmulhq_<supf><mode>"
2372 [
2373 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2374 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2375 (match_operand:MVE_2 2 "s_register_operand" "w")]
2376 VRMULHQ))
2377 ]
2378 "TARGET_HAVE_MVE"
2379 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2380 [(set_attr "type" "mve_move")
2381])
2382
2383;;
2384;; [vrshlq_n_u, vrshlq_n_s])
2385;;
2386(define_insn "mve_vrshlq_n_<supf><mode>"
2387 [
2388 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2389 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2390 (match_operand:SI 2 "s_register_operand" "r")]
2391 VRSHLQ_N))
2392 ]
2393 "TARGET_HAVE_MVE"
2394 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2395 [(set_attr "type" "mve_move")
2396])
2397
2398;;
2399;; [vrshlq_s, vrshlq_u])
2400;;
2401(define_insn "mve_vrshlq_<supf><mode>"
2402 [
2403 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2404 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2405 (match_operand:MVE_2 2 "s_register_operand" "w")]
2406 VRSHLQ))
2407 ]
2408 "TARGET_HAVE_MVE"
2409 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2410 [(set_attr "type" "mve_move")
2411])
2412
2413;;
2414;; [vrshrq_n_s, vrshrq_n_u])
2415;;
2416(define_insn "mve_vrshrq_n_<supf><mode>"
2417 [
2418 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2419 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2420 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2421 VRSHRQ_N))
2422 ]
2423 "TARGET_HAVE_MVE"
2424 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2425 [(set_attr "type" "mve_move")
2426])
2427
2428;;
2429;; [vshlq_n_u, vshlq_n_s])
2430;;
2431(define_insn "mve_vshlq_n_<supf><mode>"
2432 [
2433 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2434 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2435 (match_operand:SI 2 "immediate_operand" "i")]
2436 VSHLQ_N))
2437 ]
2438 "TARGET_HAVE_MVE"
2439 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2440 [(set_attr "type" "mve_move")
2441])
2442
2443;;
2444;; [vshlq_r_s, vshlq_r_u])
2445;;
2446(define_insn "mve_vshlq_r_<supf><mode>"
2447 [
2448 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2449 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2450 (match_operand:SI 2 "s_register_operand" "r")]
2451 VSHLQ_R))
2452 ]
2453 "TARGET_HAVE_MVE"
2454 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2455 [(set_attr "type" "mve_move")
2456])
2457
2458;;
2459;; [vsubq_n_s, vsubq_n_u])
2460;;
2461(define_insn "mve_vsubq_n_<supf><mode>"
2462 [
2463 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2464 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2465 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2466 VSUBQ_N))
2467 ]
2468 "TARGET_HAVE_MVE"
2469 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2470 [(set_attr "type" "mve_move")
2471])
2472
2473;;
2474;; [vsubq_s, vsubq_u])
2475;;
2476(define_insn "mve_vsubq_<supf><mode>"
2477 [
2478 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2479 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2480 (match_operand:MVE_2 2 "s_register_operand" "w")]
2481 VSUBQ))
2482 ]
2483 "TARGET_HAVE_MVE"
2484 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2485 [(set_attr "type" "mve_move")
2486])
f9355dee
SP		 2487
2488;;
2489;; [vabdq_f])
2490;;
2491(define_insn "mve_vabdq_f<mode>"
2492 [
2493 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2494 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2495 (match_operand:MVE_0 2 "s_register_operand" "w")]
2496 VABDQ_F))
2497 ]
2498 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2499 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2500 [(set_attr "type" "mve_move")
2501])
2502
2503;;
2504;; [vaddlvaq_s vaddlvaq_u])
2505;;
2506(define_insn "mve_vaddlvaq_<supf>v4si"
2507 [
2508 (set (match_operand:DI 0 "s_register_operand" "=r")
2509 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2510 (match_operand:V4SI 2 "s_register_operand" "w")]
2511 VADDLVAQ))
2512 ]
2513 "TARGET_HAVE_MVE"
2514 "vaddlva.<supf>32 %Q0, %R0, %q2"
2515 [(set_attr "type" "mve_move")
2516])
2517
2518;;
2519;; [vaddq_n_f])
2520;;
2521(define_insn "mve_vaddq_n_f<mode>"
2522 [
2523 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2524 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2525 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2526 VADDQ_N_F))
2527 ]
2528 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2529 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2530 [(set_attr "type" "mve_move")
2531])
2532
2533;;
2534;; [vandq_f])
2535;;
2536(define_insn "mve_vandq_f<mode>"
2537 [
2538 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2539 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2540 (match_operand:MVE_0 2 "s_register_operand" "w")]
2541 VANDQ_F))
2542 ]
2543 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2544 "vand %q0, %q1, %q2"
2545 [(set_attr "type" "mve_move")
2546])
2547
2548;;
2549;; [vbicq_f])
2550;;
2551(define_insn "mve_vbicq_f<mode>"
2552 [
2553 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2554 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2555 (match_operand:MVE_0 2 "s_register_operand" "w")]
2556 VBICQ_F))
2557 ]
2558 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2559 "vbic %q0, %q1, %q2"
2560 [(set_attr "type" "mve_move")
2561])
2562
2563;;
2564;; [vbicq_n_s, vbicq_n_u])
2565;;
2566(define_insn "mve_vbicq_n_<supf><mode>"
2567 [
2568 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2569 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2570 (match_operand:SI 2 "immediate_operand" "i")]
2571 VBICQ_N))
2572 ]
2573 "TARGET_HAVE_MVE"
2574 "vbic.i%#<V_sz_elem> %q0, %2"
2575 [(set_attr "type" "mve_move")
2576])
2577
2578;;
2579;; [vcaddq_rot270_f])
2580;;
2581(define_insn "mve_vcaddq_rot270_f<mode>"
2582 [
2583 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2584 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2585 (match_operand:MVE_0 2 "s_register_operand" "w")]
2586 VCADDQ_ROT270_F))
2587 ]
2588 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2589 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2590 [(set_attr "type" "mve_move")
2591])
2592
2593;;
2594;; [vcaddq_rot90_f])
2595;;
2596(define_insn "mve_vcaddq_rot90_f<mode>"
2597 [
2598 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2599 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2600 (match_operand:MVE_0 2 "s_register_operand" "w")]
2601 VCADDQ_ROT90_F))
2602 ]
2603 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2604 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2605 [(set_attr "type" "mve_move")
2606])
2607
2608;;
2609;; [vcmpeqq_f])
2610;;
2611(define_insn "mve_vcmpeqq_f<mode>"
2612 [
2613 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2614 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2615 (match_operand:MVE_0 2 "s_register_operand" "w")]
2616 VCMPEQQ_F))
2617 ]
2618 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2619 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2620 [(set_attr "type" "mve_move")
2621])
2622
2623;;
2624;; [vcmpeqq_n_f])
2625;;
2626(define_insn "mve_vcmpeqq_n_f<mode>"
2627 [
2628 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2629 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2630 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2631 VCMPEQQ_N_F))
2632 ]
2633 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2634 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2635 [(set_attr "type" "mve_move")
2636])
2637
2638;;
2639;; [vcmpgeq_f])
2640;;
2641(define_insn "mve_vcmpgeq_f<mode>"
2642 [
2643 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2644 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2645 (match_operand:MVE_0 2 "s_register_operand" "w")]
2646 VCMPGEQ_F))
2647 ]
2648 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2649 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2650 [(set_attr "type" "mve_move")
2651])
2652
2653;;
2654;; [vcmpgeq_n_f])
2655;;
2656(define_insn "mve_vcmpgeq_n_f<mode>"
2657 [
2658 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2659 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2660 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2661 VCMPGEQ_N_F))
2662 ]
2663 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2664 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2665 [(set_attr "type" "mve_move")
2666])
2667
2668;;
2669;; [vcmpgtq_f])
2670;;
2671(define_insn "mve_vcmpgtq_f<mode>"
2672 [
2673 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2674 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2675 (match_operand:MVE_0 2 "s_register_operand" "w")]
2676 VCMPGTQ_F))
2677 ]
2678 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2679 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2680 [(set_attr "type" "mve_move")
2681])
2682
2683;;
2684;; [vcmpgtq_n_f])
2685;;
2686(define_insn "mve_vcmpgtq_n_f<mode>"
2687 [
2688 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2689 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2690 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2691 VCMPGTQ_N_F))
2692 ]
2693 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2694 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2695 [(set_attr "type" "mve_move")
2696])
2697
2698;;
2699;; [vcmpleq_f])
2700;;
2701(define_insn "mve_vcmpleq_f<mode>"
2702 [
2703 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2704 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2705 (match_operand:MVE_0 2 "s_register_operand" "w")]
2706 VCMPLEQ_F))
2707 ]
2708 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2709 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2710 [(set_attr "type" "mve_move")
2711])
2712
2713;;
2714;; [vcmpleq_n_f])
2715;;
2716(define_insn "mve_vcmpleq_n_f<mode>"
2717 [
2718 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2719 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2720 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2721 VCMPLEQ_N_F))
2722 ]
2723 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2724 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2725 [(set_attr "type" "mve_move")
2726])
2727
2728;;
2729;; [vcmpltq_f])
2730;;
2731(define_insn "mve_vcmpltq_f<mode>"
2732 [
2733 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2734 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2735 (match_operand:MVE_0 2 "s_register_operand" "w")]
2736 VCMPLTQ_F))
2737 ]
2738 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2739 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2740 [(set_attr "type" "mve_move")
2741])
2742
2743;;
2744;; [vcmpltq_n_f])
2745;;
2746(define_insn "mve_vcmpltq_n_f<mode>"
2747 [
2748 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2749 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2750 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2751 VCMPLTQ_N_F))
2752 ]
2753 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2754 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2755 [(set_attr "type" "mve_move")
2756])
2757
2758;;
2759;; [vcmpneq_f])
2760;;
2761(define_insn "mve_vcmpneq_f<mode>"
2762 [
2763 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2764 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2765 (match_operand:MVE_0 2 "s_register_operand" "w")]
2766 VCMPNEQ_F))
2767 ]
2768 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2769 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2770 [(set_attr "type" "mve_move")
2771])
2772
2773;;
2774;; [vcmpneq_n_f])
2775;;
2776(define_insn "mve_vcmpneq_n_f<mode>"
2777 [
2778 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2779 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2780 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2781 VCMPNEQ_N_F))
2782 ]
2783 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2784 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2785 [(set_attr "type" "mve_move")
2786])
2787
2788;;
2789;; [vcmulq_f])
2790;;
2791(define_insn "mve_vcmulq_f<mode>"
2792 [
2793 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2794 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2795 (match_operand:MVE_0 2 "s_register_operand" "w")]
2796 VCMULQ_F))
2797 ]
2798 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2799 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2800 [(set_attr "type" "mve_move")
2801])
2802
2803;;
2804;; [vcmulq_rot180_f])
2805;;
2806(define_insn "mve_vcmulq_rot180_f<mode>"
2807 [
2808 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2809 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2810 (match_operand:MVE_0 2 "s_register_operand" "w")]
2811 VCMULQ_ROT180_F))
2812 ]
2813 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2814 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2815 [(set_attr "type" "mve_move")
2816])
2817
2818;;
2819;; [vcmulq_rot270_f])
2820;;
2821(define_insn "mve_vcmulq_rot270_f<mode>"
2822 [
2823 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2824 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2825 (match_operand:MVE_0 2 "s_register_operand" "w")]
2826 VCMULQ_ROT270_F))
2827 ]
2828 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2829 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2830 [(set_attr "type" "mve_move")
2831])
2832
2833;;
2834;; [vcmulq_rot90_f])
2835;;
2836(define_insn "mve_vcmulq_rot90_f<mode>"
2837 [
2838 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2839 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2840 (match_operand:MVE_0 2 "s_register_operand" "w")]
2841 VCMULQ_ROT90_F))
2842 ]
2843 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2844 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2845 [(set_attr "type" "mve_move")
2846])
2847
2848;;
2849;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2850;;
2851(define_insn "mve_vctp<mode1>q_mhi"
2852 [
2853 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2854 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2855 (match_operand:HI 2 "vpr_register_operand" "Up")]
2856 VCTPQ_M))
2857 ]
2858 "TARGET_HAVE_MVE"
2859 "vpst\;vctpt.<mode1> %1"
2860 [(set_attr "type" "mve_move")
2861 (set_attr "length""8")])
2862
2863;;
2864;; [vcvtbq_f16_f32])
2865;;
2866(define_insn "mve_vcvtbq_f16_f32v8hf"
2867 [
2868 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2869 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2870 (match_operand:V4SF 2 "s_register_operand" "w")]
2871 VCVTBQ_F16_F32))
2872 ]
2873 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2874 "vcvtb.f16.f32 %q0, %q2"
2875 [(set_attr "type" "mve_move")
2876])
2877
2878;;
2879;; [vcvttq_f16_f32])
2880;;
2881(define_insn "mve_vcvttq_f16_f32v8hf"
2882 [
2883 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2884 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2885 (match_operand:V4SF 2 "s_register_operand" "w")]
2886 VCVTTQ_F16_F32))
2887 ]
2888 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2889 "vcvtt.f16.f32 %q0, %q2"
2890 [(set_attr "type" "mve_move")
2891])
2892
2893;;
2894;; [veorq_f])
2895;;
2896(define_insn "mve_veorq_f<mode>"
2897 [
2898 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2899 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2900 (match_operand:MVE_0 2 "s_register_operand" "w")]
2901 VEORQ_F))
2902 ]
2903 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2904 "veor %q0, %q1, %q2"
2905 [(set_attr "type" "mve_move")
2906])
2907
2908;;
2909;; [vmaxnmaq_f])
2910;;
2911(define_insn "mve_vmaxnmaq_f<mode>"
2912 [
2913 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2914 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2915 (match_operand:MVE_0 2 "s_register_operand" "w")]
2916 VMAXNMAQ_F))
2917 ]
2918 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2919 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2920 [(set_attr "type" "mve_move")
2921])
2922
2923;;
2924;; [vmaxnmavq_f])
2925;;
2926(define_insn "mve_vmaxnmavq_f<mode>"
2927 [
2928 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2929 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2930 (match_operand:MVE_0 2 "s_register_operand" "w")]
2931 VMAXNMAVQ_F))
2932 ]
2933 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2934 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2935 [(set_attr "type" "mve_move")
2936])
2937
2938;;
2939;; [vmaxnmq_f])
2940;;
2941(define_insn "mve_vmaxnmq_f<mode>"
2942 [
2943 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2944 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2945 (match_operand:MVE_0 2 "s_register_operand" "w")]
2946 VMAXNMQ_F))
2947 ]
2948 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2949 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
2950 [(set_attr "type" "mve_move")
2951])
2952
2953;;
2954;; [vmaxnmvq_f])
2955;;
2956(define_insn "mve_vmaxnmvq_f<mode>"
2957 [
2958 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2959 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2960 (match_operand:MVE_0 2 "s_register_operand" "w")]
2961 VMAXNMVQ_F))
2962 ]
2963 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2964 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
2965 [(set_attr "type" "mve_move")
2966])
2967
2968;;
2969;; [vminnmaq_f])
2970;;
2971(define_insn "mve_vminnmaq_f<mode>"
2972 [
2973 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2974 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2975 (match_operand:MVE_0 2 "s_register_operand" "w")]
2976 VMINNMAQ_F))
2977 ]
2978 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2979 "vminnma.f%#<V_sz_elem> %q0, %q2"
2980 [(set_attr "type" "mve_move")
2981])
2982
2983;;
2984;; [vminnmavq_f])
2985;;
2986(define_insn "mve_vminnmavq_f<mode>"
2987 [
2988 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2989 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2990 (match_operand:MVE_0 2 "s_register_operand" "w")]
2991 VMINNMAVQ_F))
2992 ]
2993 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2994 "vminnmav.f%#<V_sz_elem> %0, %q2"
2995 [(set_attr "type" "mve_move")
2996])
2997
2998;;
2999;; [vminnmq_f])
3000;;
3001(define_insn "mve_vminnmq_f<mode>"
3002 [
3003 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3004 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3005 (match_operand:MVE_0 2 "s_register_operand" "w")]
3006 VMINNMQ_F))
3007 ]
3008 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3009 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
3010 [(set_attr "type" "mve_move")
3011])
3012
3013;;
3014;; [vminnmvq_f])
3015;;
3016(define_insn "mve_vminnmvq_f<mode>"
3017 [
3018 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3019 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3020 (match_operand:MVE_0 2 "s_register_operand" "w")]
3021 VMINNMVQ_F))
3022 ]
3023 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3024 "vminnmv.f%#<V_sz_elem> %0, %q2"
3025 [(set_attr "type" "mve_move")
3026])
3027
3028;;
3029;; [vmlaldavq_u, vmlaldavq_s])
3030;;
3031(define_insn "mve_vmlaldavq_<supf><mode>"
3032 [
3033 (set (match_operand:DI 0 "s_register_operand" "=r")
3034 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3035 (match_operand:MVE_5 2 "s_register_operand" "w")]
3036 VMLALDAVQ))
3037 ]
3038 "TARGET_HAVE_MVE"
3039 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3040 [(set_attr "type" "mve_move")
3041])
3042
3043;;
3044;; [vmlaldavxq_s])
3045;;
3046(define_insn "mve_vmlaldavxq_s<mode>"
3047 [
3048 (set (match_operand:DI 0 "s_register_operand" "=r")
3049 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3050 (match_operand:MVE_5 2 "s_register_operand" "w")]
3051 VMLALDAVXQ_S))
3052 ]
3053 "TARGET_HAVE_MVE"
3054 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3055 [(set_attr "type" "mve_move")
3056])
3057
3058;;
3059;; [vmlsldavq_s])
3060;;
3061(define_insn "mve_vmlsldavq_s<mode>"
3062 [
3063 (set (match_operand:DI 0 "s_register_operand" "=r")
3064 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3065 (match_operand:MVE_5 2 "s_register_operand" "w")]
3066 VMLSLDAVQ_S))
3067 ]
3068 "TARGET_HAVE_MVE"
3069 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3070 [(set_attr "type" "mve_move")
3071])
3072
3073;;
3074;; [vmlsldavxq_s])
3075;;
3076(define_insn "mve_vmlsldavxq_s<mode>"
3077 [
3078 (set (match_operand:DI 0 "s_register_operand" "=r")
3079 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3080 (match_operand:MVE_5 2 "s_register_operand" "w")]
3081 VMLSLDAVXQ_S))
3082 ]
3083 "TARGET_HAVE_MVE"
3084 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3085 [(set_attr "type" "mve_move")
3086])
3087
3088;;
3089;; [vmovnbq_u, vmovnbq_s])
3090;;
3091(define_insn "mve_vmovnbq_<supf><mode>"
3092 [
3093 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3094 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3095 (match_operand:MVE_5 2 "s_register_operand" "w")]
3096 VMOVNBQ))
3097 ]
3098 "TARGET_HAVE_MVE"
3099 "vmovnb.i%#<V_sz_elem> %q0, %q2"
3100 [(set_attr "type" "mve_move")
3101])
3102
3103;;
3104;; [vmovntq_s, vmovntq_u])
3105;;
3106(define_insn "mve_vmovntq_<supf><mode>"
3107 [
3108 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3109 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3110 (match_operand:MVE_5 2 "s_register_operand" "w")]
3111 VMOVNTQ))
3112 ]
3113 "TARGET_HAVE_MVE"
3114 "vmovnt.i%#<V_sz_elem> %q0, %q2"
3115 [(set_attr "type" "mve_move")
3116])
3117
3118;;
3119;; [vmulq_f])
3120;;
3121(define_insn "mve_vmulq_f<mode>"
3122 [
3123 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3124 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3125 (match_operand:MVE_0 2 "s_register_operand" "w")]
3126 VMULQ_F))
3127 ]
3128 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3129 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
3130 [(set_attr "type" "mve_move")
3131])
3132
3133;;
3134;; [vmulq_n_f])
3135;;
3136(define_insn "mve_vmulq_n_f<mode>"
3137 [
3138 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3139 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3140 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3141 VMULQ_N_F))
3142 ]
3143 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3144 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
3145 [(set_attr "type" "mve_move")
3146])
3147
3148;;
3149;; [vornq_f])
3150;;
3151(define_insn "mve_vornq_f<mode>"
3152 [
3153 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3154 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3155 (match_operand:MVE_0 2 "s_register_operand" "w")]
3156 VORNQ_F))
3157 ]
3158 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3159 "vorn %q0, %q1, %q2"
3160 [(set_attr "type" "mve_move")
3161])
3162
3163;;
3164;; [vorrq_f])
3165;;
3166(define_insn "mve_vorrq_f<mode>"
3167 [
3168 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3169 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3170 (match_operand:MVE_0 2 "s_register_operand" "w")]
3171 VORRQ_F))
3172 ]
3173 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3174 "vorr %q0, %q1, %q2"
3175 [(set_attr "type" "mve_move")
3176])
3177
3178;;
3179;; [vorrq_n_u, vorrq_n_s])
3180;;
3181(define_insn "mve_vorrq_n_<supf><mode>"
3182 [
3183 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3184 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3185 (match_operand:SI 2 "immediate_operand" "i")]
3186 VORRQ_N))
3187 ]
3188 "TARGET_HAVE_MVE"
3189 "vorr.i%#<V_sz_elem> %q0, %2"
3190 [(set_attr "type" "mve_move")
3191])
3192
3193;;
3194;; [vqdmullbq_n_s])
3195;;
3196(define_insn "mve_vqdmullbq_n_s<mode>"
3197 [
3198 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3199 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3200 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3201 VQDMULLBQ_N_S))
3202 ]
3203 "TARGET_HAVE_MVE"
3204 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
3205 [(set_attr "type" "mve_move")
3206])
3207
3208;;
3209;; [vqdmullbq_s])
3210;;
3211(define_insn "mve_vqdmullbq_s<mode>"
3212 [
3213 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3214 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3215 (match_operand:MVE_5 2 "s_register_operand" "w")]
3216 VQDMULLBQ_S))
3217 ]
3218 "TARGET_HAVE_MVE"
3219 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
3220 [(set_attr "type" "mve_move")
3221])
3222
3223;;
3224;; [vqdmulltq_n_s])
3225;;
3226(define_insn "mve_vqdmulltq_n_s<mode>"
3227 [
3228 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3229 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3230 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3231 VQDMULLTQ_N_S))
3232 ]
3233 "TARGET_HAVE_MVE"
3234 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
3235 [(set_attr "type" "mve_move")
3236])
3237
3238;;
3239;; [vqdmulltq_s])
3240;;
3241(define_insn "mve_vqdmulltq_s<mode>"
3242 [
3243 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3244 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3245 (match_operand:MVE_5 2 "s_register_operand" "w")]
3246 VQDMULLTQ_S))
3247 ]
3248 "TARGET_HAVE_MVE"
3249 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
3250 [(set_attr "type" "mve_move")
3251])
3252
3253;;
3254;; [vqmovnbq_u, vqmovnbq_s])
3255;;
3256(define_insn "mve_vqmovnbq_<supf><mode>"
3257 [
3258 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3259 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3260 (match_operand:MVE_5 2 "s_register_operand" "w")]
3261 VQMOVNBQ))
3262 ]
3263 "TARGET_HAVE_MVE"
3264 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
3265 [(set_attr "type" "mve_move")
3266])
3267
3268;;
3269;; [vqmovntq_u, vqmovntq_s])
3270;;
3271(define_insn "mve_vqmovntq_<supf><mode>"
3272 [
3273 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3274 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3275 (match_operand:MVE_5 2 "s_register_operand" "w")]
3276 VQMOVNTQ))
3277 ]
3278 "TARGET_HAVE_MVE"
3279 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
3280 [(set_attr "type" "mve_move")
3281])
3282
3283;;
3284;; [vqmovunbq_s])
3285;;
3286(define_insn "mve_vqmovunbq_s<mode>"
3287 [
3288 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3289 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3290 (match_operand:MVE_5 2 "s_register_operand" "w")]
3291 VQMOVUNBQ_S))
3292 ]
3293 "TARGET_HAVE_MVE"
3294 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
3295 [(set_attr "type" "mve_move")
3296])
3297
3298;;
3299;; [vqmovuntq_s])
3300;;
3301(define_insn "mve_vqmovuntq_s<mode>"
3302 [
3303 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3304 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3305 (match_operand:MVE_5 2 "s_register_operand" "w")]
3306 VQMOVUNTQ_S))
3307 ]
3308 "TARGET_HAVE_MVE"
3309 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
3310 [(set_attr "type" "mve_move")
3311])
3312
3313;;
3314;; [vrmlaldavhxq_s])
3315;;
3316(define_insn "mve_vrmlaldavhxq_sv4si"
3317 [
3318 (set (match_operand:DI 0 "s_register_operand" "=r")
3319 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3320 (match_operand:V4SI 2 "s_register_operand" "w")]
3321 VRMLALDAVHXQ_S))
3322 ]
3323 "TARGET_HAVE_MVE"
3324 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
3325 [(set_attr "type" "mve_move")
3326])
3327
3328;;
3329;; [vrmlsldavhq_s])
3330;;
3331(define_insn "mve_vrmlsldavhq_sv4si"
3332 [
3333 (set (match_operand:DI 0 "s_register_operand" "=r")
3334 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3335 (match_operand:V4SI 2 "s_register_operand" "w")]
3336 VRMLSLDAVHQ_S))
3337 ]
3338 "TARGET_HAVE_MVE"
3339 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
3340 [(set_attr "type" "mve_move")
3341])
3342
3343;;
3344;; [vrmlsldavhxq_s])
3345;;
3346(define_insn "mve_vrmlsldavhxq_sv4si"
3347 [
3348 (set (match_operand:DI 0 "s_register_operand" "=r")
3349 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3350 (match_operand:V4SI 2 "s_register_operand" "w")]
3351 VRMLSLDAVHXQ_S))
3352 ]
3353 "TARGET_HAVE_MVE"
3354 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
3355 [(set_attr "type" "mve_move")
3356])
3357
3358;;
3359;; [vshllbq_n_s, vshllbq_n_u])
3360;;
3361(define_insn "mve_vshllbq_n_<supf><mode>"
3362 [
3363 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3364 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3365 (match_operand:SI 2 "immediate_operand" "i")]
3366 VSHLLBQ_N))
3367 ]
3368 "TARGET_HAVE_MVE"
3369 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3370 [(set_attr "type" "mve_move")
3371])
3372
3373;;
3374;; [vshlltq_n_u, vshlltq_n_s])
3375;;
3376(define_insn "mve_vshlltq_n_<supf><mode>"
3377 [
3378 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3379 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3380 (match_operand:SI 2 "immediate_operand" "i")]
3381 VSHLLTQ_N))
3382 ]
3383 "TARGET_HAVE_MVE"
3384 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3385 [(set_attr "type" "mve_move")
3386])
3387
3388;;
3389;; [vsubq_f])
3390;;
3391(define_insn "mve_vsubq_f<mode>"
3392 [
3393 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3394 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3395 (match_operand:MVE_0 2 "s_register_operand" "w")]
3396 VSUBQ_F))
3397 ]
3398 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3399 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3400 [(set_attr "type" "mve_move")
3401])
3402
3403;;
3404;; [vmulltq_poly_p])
3405;;
3406(define_insn "mve_vmulltq_poly_p<mode>"
3407 [
3408 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3409 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3410 (match_operand:MVE_3 2 "s_register_operand" "w")]
3411 VMULLTQ_POLY_P))
3412 ]
3413 "TARGET_HAVE_MVE"
3414 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3415 [(set_attr "type" "mve_move")
3416])
3417
3418;;
3419;; [vmullbq_poly_p])
3420;;
3421(define_insn "mve_vmullbq_poly_p<mode>"
3422 [
3423 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3424 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3425 (match_operand:MVE_3 2 "s_register_operand" "w")]
3426 VMULLBQ_POLY_P))
3427 ]
3428 "TARGET_HAVE_MVE"
3429 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3430 [(set_attr "type" "mve_move")
3431])
3432
3433;;
3434;; [vrmlaldavhq_u vrmlaldavhq_s])
3435;;
3436(define_insn "mve_vrmlaldavhq_<supf>v4si"
3437 [
3438 (set (match_operand:DI 0 "s_register_operand" "=r")
3439 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3440 (match_operand:V4SI 2 "s_register_operand" "w")]
3441 VRMLALDAVHQ))
3442 ]
3443 "TARGET_HAVE_MVE"
3444 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3445 [(set_attr "type" "mve_move")
3446])
0dad5b33
SP		 3447
3448;;
3449;; [vbicq_m_n_s, vbicq_m_n_u])
3450;;
3451(define_insn "mve_vbicq_m_n_<supf><mode>"
3452 [
3453 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3454 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3455 (match_operand:SI 2 "immediate_operand" "i")
3456 (match_operand:HI 3 "vpr_register_operand" "Up")]
3457 VBICQ_M_N))
3458 ]
3459 "TARGET_HAVE_MVE"
3460 "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
3461 [(set_attr "type" "mve_move")
3462 (set_attr "length""8")])
3463;;
3464;; [vcmpeqq_m_f])
3465;;
3466(define_insn "mve_vcmpeqq_m_f<mode>"
3467 [
3468 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3469 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
3470 (match_operand:MVE_0 2 "s_register_operand" "w")
3471 (match_operand:HI 3 "vpr_register_operand" "Up")]
3472 VCMPEQQ_M_F))
3473 ]
3474 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3475 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
3476 [(set_attr "type" "mve_move")
3477 (set_attr "length""8")])
3478;;
3479;; [vcvtaq_m_u, vcvtaq_m_s])
3480;;
3481(define_insn "mve_vcvtaq_m_<supf><mode>"
3482 [
3483 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3484 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3485 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3486 (match_operand:HI 3 "vpr_register_operand" "Up")]
3487 VCVTAQ_M))
3488 ]
3489 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3490 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3491 [(set_attr "type" "mve_move")
3492 (set_attr "length""8")])
3493;;
3494;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3495;;
3496(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3497 [
3498 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3499 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3500 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3501 (match_operand:HI 3 "vpr_register_operand" "Up")]
3502 VCVTQ_M_TO_F))
3503 ]
3504 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3505 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
3506 [(set_attr "type" "mve_move")
3507 (set_attr "length""8")])
3508;;
3509;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3510;;
3511(define_insn "mve_vqrshrnbq_n_<supf><mode>"
3512 [
3513 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3514 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3515 (match_operand:MVE_5 2 "s_register_operand" "w")
3516 (match_operand:SI 3 "mve_imm_8" "Rb")]
3517 VQRSHRNBQ_N))
3518 ]
3519 "TARGET_HAVE_MVE"
3520 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3521 [(set_attr "type" "mve_move")
3522])
3523;;
3524;; [vqrshrunbq_n_s])
3525;;
3526(define_insn "mve_vqrshrunbq_n_s<mode>"
3527 [
3528 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3529 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3530 (match_operand:MVE_5 2 "s_register_operand" "w")
3531 (match_operand:SI 3 "mve_imm_8" "Rb")]
3532 VQRSHRUNBQ_N_S))
3533 ]
3534 "TARGET_HAVE_MVE"
3535 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3536 [(set_attr "type" "mve_move")
3537])
3538;;
3539;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3540;;
3541(define_insn "mve_vrmlaldavhaq_<supf>v4si"
3542 [
3543 (set (match_operand:DI 0 "s_register_operand" "=r")
3544 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3545 (match_operand:V4SI 2 "s_register_operand" "w")
3546 (match_operand:V4SI 3 "s_register_operand" "w")]
3547 VRMLALDAVHAQ))
3548 ]
3549 "TARGET_HAVE_MVE"
3550 "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3551 [(set_attr "type" "mve_move")
3552])
3553
3554;;
3555;; [vabavq_s, vabavq_u])
3556;;
3557(define_insn "mve_vabavq_<supf><mode>"
3558 [
3559 (set (match_operand:SI 0 "s_register_operand" "=r")
3560 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3561 (match_operand:MVE_2 2 "s_register_operand" "w")
3562 (match_operand:MVE_2 3 "s_register_operand" "w")]
3563 VABAVQ))
3564 ]
3565 "TARGET_HAVE_MVE"
3566 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3567 [(set_attr "type" "mve_move")
3568])
3569
3570;;
3571;; [vshlcq_u vshlcq_s]
3572;;
3573(define_expand "mve_vshlcq_vec_<supf><mode>"
3574 [(match_operand:MVE_2 0 "s_register_operand")
3575 (match_operand:MVE_2 1 "s_register_operand")
3576 (match_operand:SI 2 "s_register_operand")
3577 (match_operand:SI 3 "mve_imm_32")
3578 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3579 "TARGET_HAVE_MVE"
3580{
3581 rtx ignore_wb = gen_reg_rtx (SImode);
3582 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
8165795c 3583 operands[2], operands[3]));
0dad5b33
SP		 3584 DONE;
3585})
3586
3587(define_expand "mve_vshlcq_carry_<supf><mode>"
3588 [(match_operand:SI 0 "s_register_operand")
3589 (match_operand:MVE_2 1 "s_register_operand")
3590 (match_operand:SI 2 "s_register_operand")
3591 (match_operand:SI 3 "mve_imm_32")
3592 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3593 "TARGET_HAVE_MVE"
3594{
3595 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3596 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3597 operands[2], operands[3]));
3598 DONE;
3599})
3600
3601(define_insn "mve_vshlcq_<supf><mode>"
3602 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3603 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3604 (match_operand:SI 3 "s_register_operand" "1")
3605 (match_operand:SI 4 "mve_imm_32" "Rf")]
3606 VSHLCQ))
3607 (set (match_operand:SI 1 "s_register_operand" "=r")
3608 (unspec:SI [(match_dup 2)
3609 (match_dup 3)
3610 (match_dup 4)]
3611 VSHLCQ))]
3612 "TARGET_HAVE_MVE"
3613 "vshlc %q0, %1, %4")
8165795c
SP		 3614
3615;;
3616;; [vabsq_m_s])
3617;;
3618(define_insn "mve_vabsq_m_s<mode>"
3619 [
3620 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3621 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3622 (match_operand:MVE_2 2 "s_register_operand" "w")
3623 (match_operand:HI 3 "vpr_register_operand" "Up")]
3624 VABSQ_M_S))
3625 ]
3626 "TARGET_HAVE_MVE"
3627 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
3628 [(set_attr "type" "mve_move")
3629 (set_attr "length""8")])
3630
3631;;
3632;; [vaddvaq_p_u, vaddvaq_p_s])
3633;;
3634(define_insn "mve_vaddvaq_p_<supf><mode>"
3635 [
3636 (set (match_operand:SI 0 "s_register_operand" "=e")
3637 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3638 (match_operand:MVE_2 2 "s_register_operand" "w")
3639 (match_operand:HI 3 "vpr_register_operand" "Up")]
3640 VADDVAQ_P))
3641 ]
3642 "TARGET_HAVE_MVE"
3643 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2"
3644 [(set_attr "type" "mve_move")
3645 (set_attr "length""8")])
3646
3647;;
3648;; [vclsq_m_s])
3649;;
3650(define_insn "mve_vclsq_m_s<mode>"
3651 [
3652 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3653 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3654 (match_operand:MVE_2 2 "s_register_operand" "w")
3655 (match_operand:HI 3 "vpr_register_operand" "Up")]
3656 VCLSQ_M_S))
3657 ]
3658 "TARGET_HAVE_MVE"
3659 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
3660 [(set_attr "type" "mve_move")
3661 (set_attr "length""8")])
3662
3663;;
3664;; [vclzq_m_s, vclzq_m_u])
3665;;
3666(define_insn "mve_vclzq_m_<supf><mode>"
3667 [
3668 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3669 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3670 (match_operand:MVE_2 2 "s_register_operand" "w")
3671 (match_operand:HI 3 "vpr_register_operand" "Up")]
3672 VCLZQ_M))
3673 ]
3674 "TARGET_HAVE_MVE"
3675 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
3676 [(set_attr "type" "mve_move")
3677 (set_attr "length""8")])
3678
3679;;
3680;; [vcmpcsq_m_n_u])
3681;;
3682(define_insn "mve_vcmpcsq_m_n_u<mode>"
3683 [
3684 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3685 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3686 (match_operand:<V_elem> 2 "s_register_operand" "r")
3687 (match_operand:HI 3 "vpr_register_operand" "Up")]
3688 VCMPCSQ_M_N_U))
3689 ]
3690 "TARGET_HAVE_MVE"
3691 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2"
3692 [(set_attr "type" "mve_move")
3693 (set_attr "length""8")])
3694
3695;;
3696;; [vcmpcsq_m_u])
3697;;
3698(define_insn "mve_vcmpcsq_m_u<mode>"
3699 [
3700 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3701 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3702 (match_operand:MVE_2 2 "s_register_operand" "w")
3703 (match_operand:HI 3 "vpr_register_operand" "Up")]
3704 VCMPCSQ_M_U))
3705 ]
3706 "TARGET_HAVE_MVE"
3707 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2"
3708 [(set_attr "type" "mve_move")
3709 (set_attr "length""8")])
3710
3711;;
3712;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3713;;
3714(define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3715 [
3716 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3717 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3718 (match_operand:<V_elem> 2 "s_register_operand" "r")
3719 (match_operand:HI 3 "vpr_register_operand" "Up")]
3720 VCMPEQQ_M_N))
3721 ]
3722 "TARGET_HAVE_MVE"
3723 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2"
3724 [(set_attr "type" "mve_move")
3725 (set_attr "length""8")])
3726
3727;;
3728;; [vcmpeqq_m_u, vcmpeqq_m_s])
3729;;
3730(define_insn "mve_vcmpeqq_m_<supf><mode>"
3731 [
3732 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3733 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3734 (match_operand:MVE_2 2 "s_register_operand" "w")
3735 (match_operand:HI 3 "vpr_register_operand" "Up")]
3736 VCMPEQQ_M))
3737 ]
3738 "TARGET_HAVE_MVE"
3739 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2"
3740 [(set_attr "type" "mve_move")
3741 (set_attr "length""8")])
3742
3743;;
3744;; [vcmpgeq_m_n_s])
3745;;
3746(define_insn "mve_vcmpgeq_m_n_s<mode>"
3747 [
3748 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3749 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3750 (match_operand:<V_elem> 2 "s_register_operand" "r")
3751 (match_operand:HI 3 "vpr_register_operand" "Up")]
3752 VCMPGEQ_M_N_S))
3753 ]
3754 "TARGET_HAVE_MVE"
3755 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2"
3756 [(set_attr "type" "mve_move")
3757 (set_attr "length""8")])
3758
3759;;
3760;; [vcmpgeq_m_s])
3761;;
3762(define_insn "mve_vcmpgeq_m_s<mode>"
3763 [
3764 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3765 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3766 (match_operand:MVE_2 2 "s_register_operand" "w")
3767 (match_operand:HI 3 "vpr_register_operand" "Up")]
3768 VCMPGEQ_M_S))
3769 ]
3770 "TARGET_HAVE_MVE"
3771 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2"
3772 [(set_attr "type" "mve_move")
3773 (set_attr "length""8")])
3774
3775;;
3776;; [vcmpgtq_m_n_s])
3777;;
3778(define_insn "mve_vcmpgtq_m_n_s<mode>"
3779 [
3780 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3781 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3782 (match_operand:<V_elem> 2 "s_register_operand" "r")
3783 (match_operand:HI 3 "vpr_register_operand" "Up")]
3784 VCMPGTQ_M_N_S))
3785 ]
3786 "TARGET_HAVE_MVE"
3787 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2"
3788 [(set_attr "type" "mve_move")
3789 (set_attr "length""8")])
3790
3791;;
3792;; [vcmpgtq_m_s])
3793;;
3794(define_insn "mve_vcmpgtq_m_s<mode>"
3795 [
3796 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3797 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3798 (match_operand:MVE_2 2 "s_register_operand" "w")
3799 (match_operand:HI 3 "vpr_register_operand" "Up")]
3800 VCMPGTQ_M_S))
3801 ]
3802 "TARGET_HAVE_MVE"
3803 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2"
3804 [(set_attr "type" "mve_move")
3805 (set_attr "length""8")])
3806
3807;;
3808;; [vcmphiq_m_n_u])
3809;;
3810(define_insn "mve_vcmphiq_m_n_u<mode>"
3811 [
3812 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3813 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3814 (match_operand:<V_elem> 2 "s_register_operand" "r")
3815 (match_operand:HI 3 "vpr_register_operand" "Up")]
3816 VCMPHIQ_M_N_U))
3817 ]
3818 "TARGET_HAVE_MVE"
3819 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2"
3820 [(set_attr "type" "mve_move")
3821 (set_attr "length""8")])
3822
3823;;
3824;; [vcmphiq_m_u])
3825;;
3826(define_insn "mve_vcmphiq_m_u<mode>"
3827 [
3828 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3829 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3830 (match_operand:MVE_2 2 "s_register_operand" "w")
3831 (match_operand:HI 3 "vpr_register_operand" "Up")]
3832 VCMPHIQ_M_U))
3833 ]
3834 "TARGET_HAVE_MVE"
3835 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2"
3836 [(set_attr "type" "mve_move")
3837 (set_attr "length""8")])
3838
3839;;
3840;; [vcmpleq_m_n_s])
3841;;
3842(define_insn "mve_vcmpleq_m_n_s<mode>"
3843 [
3844 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3845 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3846 (match_operand:<V_elem> 2 "s_register_operand" "r")
3847 (match_operand:HI 3 "vpr_register_operand" "Up")]
3848 VCMPLEQ_M_N_S))
3849 ]
3850 "TARGET_HAVE_MVE"
3851 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2"
3852 [(set_attr "type" "mve_move")
3853 (set_attr "length""8")])
3854
3855;;
3856;; [vcmpleq_m_s])
3857;;
3858(define_insn "mve_vcmpleq_m_s<mode>"
3859 [
3860 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3861 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3862 (match_operand:MVE_2 2 "s_register_operand" "w")
3863 (match_operand:HI 3 "vpr_register_operand" "Up")]
3864 VCMPLEQ_M_S))
3865 ]
3866 "TARGET_HAVE_MVE"
3867 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2"
3868 [(set_attr "type" "mve_move")
3869 (set_attr "length""8")])
3870
3871;;
3872;; [vcmpltq_m_n_s])
3873;;
3874(define_insn "mve_vcmpltq_m_n_s<mode>"
3875 [
3876 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3877 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3878 (match_operand:<V_elem> 2 "s_register_operand" "r")
3879 (match_operand:HI 3 "vpr_register_operand" "Up")]
3880 VCMPLTQ_M_N_S))
3881 ]
3882 "TARGET_HAVE_MVE"
3883 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2"
3884 [(set_attr "type" "mve_move")
3885 (set_attr "length""8")])
3886
3887;;
3888;; [vcmpltq_m_s])
3889;;
3890(define_insn "mve_vcmpltq_m_s<mode>"
3891 [
3892 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3893 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3894 (match_operand:MVE_2 2 "s_register_operand" "w")
3895 (match_operand:HI 3 "vpr_register_operand" "Up")]
3896 VCMPLTQ_M_S))
3897 ]
3898 "TARGET_HAVE_MVE"
3899 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2"
3900 [(set_attr "type" "mve_move")
3901 (set_attr "length""8")])
3902
3903;;
3904;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3905;;
3906(define_insn "mve_vcmpneq_m_n_<supf><mode>"
3907 [
3908 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3909 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3910 (match_operand:<V_elem> 2 "s_register_operand" "r")
3911 (match_operand:HI 3 "vpr_register_operand" "Up")]
3912 VCMPNEQ_M_N))
3913 ]
3914 "TARGET_HAVE_MVE"
3915 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2"
3916 [(set_attr "type" "mve_move")
3917 (set_attr "length""8")])
3918
3919;;
3920;; [vcmpneq_m_s, vcmpneq_m_u])
3921;;
3922(define_insn "mve_vcmpneq_m_<supf><mode>"
3923 [
3924 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3925 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3926 (match_operand:MVE_2 2 "s_register_operand" "w")
3927 (match_operand:HI 3 "vpr_register_operand" "Up")]
3928 VCMPNEQ_M))
3929 ]
3930 "TARGET_HAVE_MVE"
3931 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2"
3932 [(set_attr "type" "mve_move")
3933 (set_attr "length""8")])
3934
3935;;
3936;; [vdupq_m_n_s, vdupq_m_n_u])
3937;;
3938(define_insn "mve_vdupq_m_n_<supf><mode>"
3939 [
3940 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3941 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3942 (match_operand:<V_elem> 2 "s_register_operand" "r")
3943 (match_operand:HI 3 "vpr_register_operand" "Up")]
3944 VDUPQ_M_N))
3945 ]
3946 "TARGET_HAVE_MVE"
3947 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
3948 [(set_attr "type" "mve_move")
3949 (set_attr "length""8")])
3950
3951;;
3952;; [vmaxaq_m_s])
3953;;
3954(define_insn "mve_vmaxaq_m_s<mode>"
3955 [
3956 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3957 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3958 (match_operand:MVE_2 2 "s_register_operand" "w")
3959 (match_operand:HI 3 "vpr_register_operand" "Up")]
3960 VMAXAQ_M_S))
3961 ]
3962 "TARGET_HAVE_MVE"
3963 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2"
3964 [(set_attr "type" "mve_move")
3965 (set_attr "length""8")])
3966
3967;;
3968;; [vmaxavq_p_s])
3969;;
3970(define_insn "mve_vmaxavq_p_s<mode>"
3971 [
3972 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3973 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3974 (match_operand:MVE_2 2 "s_register_operand" "w")
3975 (match_operand:HI 3 "vpr_register_operand" "Up")]
3976 VMAXAVQ_P_S))
3977 ]
3978 "TARGET_HAVE_MVE"
3979 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
3980 [(set_attr "type" "mve_move")
3981 (set_attr "length""8")])
3982
3983;;
3984;; [vmaxvq_p_u, vmaxvq_p_s])
3985;;
3986(define_insn "mve_vmaxvq_p_<supf><mode>"
3987 [
3988 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3989 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3990 (match_operand:MVE_2 2 "s_register_operand" "w")
3991 (match_operand:HI 3 "vpr_register_operand" "Up")]
3992 VMAXVQ_P))
3993 ]
3994 "TARGET_HAVE_MVE"
3995 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
3996 [(set_attr "type" "mve_move")
3997 (set_attr "length""8")])
3998
3999;;
4000;; [vminaq_m_s])
4001;;
4002(define_insn "mve_vminaq_m_s<mode>"
4003 [
4004 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4005 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4006 (match_operand:MVE_2 2 "s_register_operand" "w")
4007 (match_operand:HI 3 "vpr_register_operand" "Up")]
4008 VMINAQ_M_S))
4009 ]
4010 "TARGET_HAVE_MVE"
4011 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2"
4012 [(set_attr "type" "mve_move")
4013 (set_attr "length""8")])
4014
4015;;
4016;; [vminavq_p_s])
4017;;
4018(define_insn "mve_vminavq_p_s<mode>"
4019 [
4020 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4021 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4022 (match_operand:MVE_2 2 "s_register_operand" "w")
4023 (match_operand:HI 3 "vpr_register_operand" "Up")]
4024 VMINAVQ_P_S))
4025 ]
4026 "TARGET_HAVE_MVE"
4027 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
4028 [(set_attr "type" "mve_move")
4029 (set_attr "length""8")])
4030
4031;;
4032;; [vminvq_p_s, vminvq_p_u])
4033;;
4034(define_insn "mve_vminvq_p_<supf><mode>"
4035 [
4036 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4037 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4038 (match_operand:MVE_2 2 "s_register_operand" "w")
4039 (match_operand:HI 3 "vpr_register_operand" "Up")]
4040 VMINVQ_P))
4041 ]
4042 "TARGET_HAVE_MVE"
4043 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
4044 [(set_attr "type" "mve_move")
4045 (set_attr "length""8")])
4046
4047;;
4048;; [vmladavaq_u, vmladavaq_s])
4049;;
4050(define_insn "mve_vmladavaq_<supf><mode>"
4051 [
4052 (set (match_operand:SI 0 "s_register_operand" "=e")
4053 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4054 (match_operand:MVE_2 2 "s_register_operand" "w")
4055 (match_operand:MVE_2 3 "s_register_operand" "w")]
4056 VMLADAVAQ))
4057 ]
4058 "TARGET_HAVE_MVE"
4059 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
4060 [(set_attr "type" "mve_move")
4061])
4062
4063;;
4064;; [vmladavq_p_u, vmladavq_p_s])
4065;;
4066(define_insn "mve_vmladavq_p_<supf><mode>"
4067 [
4068 (set (match_operand:SI 0 "s_register_operand" "=e")
4069 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4070 (match_operand:MVE_2 2 "s_register_operand" "w")
4071 (match_operand:HI 3 "vpr_register_operand" "Up")]
4072 VMLADAVQ_P))
4073 ]
4074 "TARGET_HAVE_MVE"
4075 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
4076 [(set_attr "type" "mve_move")
4077 (set_attr "length""8")])
4078
4079;;
4080;; [vmladavxq_p_s])
4081;;
4082(define_insn "mve_vmladavxq_p_s<mode>"
4083 [
4084 (set (match_operand:SI 0 "s_register_operand" "=e")
4085 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4086 (match_operand:MVE_2 2 "s_register_operand" "w")
4087 (match_operand:HI 3 "vpr_register_operand" "Up")]
4088 VMLADAVXQ_P_S))
4089 ]
4090 "TARGET_HAVE_MVE"
4091 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
4092 [(set_attr "type" "mve_move")
4093 (set_attr "length""8")])
4094
4095;;
4096;; [vmlaq_n_u, vmlaq_n_s])
4097;;
4098(define_insn "mve_vmlaq_n_<supf><mode>"
4099 [
4100 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4101 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4102 (match_operand:MVE_2 2 "s_register_operand" "w")
4103 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4104 VMLAQ_N))
4105 ]
4106 "TARGET_HAVE_MVE"
4107 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
4108 [(set_attr "type" "mve_move")
4109])
4110
4111;;
4112;; [vmlasq_n_u, vmlasq_n_s])
4113;;
4114(define_insn "mve_vmlasq_n_<supf><mode>"
4115 [
4116 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4117 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4118 (match_operand:MVE_2 2 "s_register_operand" "w")
4119 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4120 VMLASQ_N))
4121 ]
4122 "TARGET_HAVE_MVE"
4123 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3"
4124 [(set_attr "type" "mve_move")
4125])
4126
4127;;
4128;; [vmlsdavq_p_s])
4129;;
4130(define_insn "mve_vmlsdavq_p_s<mode>"
4131 [
4132 (set (match_operand:SI 0 "s_register_operand" "=e")
4133 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4134 (match_operand:MVE_2 2 "s_register_operand" "w")
4135 (match_operand:HI 3 "vpr_register_operand" "Up")]
4136 VMLSDAVQ_P_S))
4137 ]
4138 "TARGET_HAVE_MVE"
4139 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
4140 [(set_attr "type" "mve_move")
4141 (set_attr "length""8")])
4142
4143;;
4144;; [vmlsdavxq_p_s])
4145;;
4146(define_insn "mve_vmlsdavxq_p_s<mode>"
4147 [
4148 (set (match_operand:SI 0 "s_register_operand" "=e")
4149 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4150 (match_operand:MVE_2 2 "s_register_operand" "w")
4151 (match_operand:HI 3 "vpr_register_operand" "Up")]
4152 VMLSDAVXQ_P_S))
4153 ]
4154 "TARGET_HAVE_MVE"
4155 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
4156 [(set_attr "type" "mve_move")
4157 (set_attr "length""8")])
4158
4159;;
4160;; [vmvnq_m_s, vmvnq_m_u])
4161;;
4162(define_insn "mve_vmvnq_m_<supf><mode>"
4163 [
4164 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4165 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4166 (match_operand:MVE_2 2 "s_register_operand" "w")
4167 (match_operand:HI 3 "vpr_register_operand" "Up")]
4168 VMVNQ_M))
4169 ]
4170 "TARGET_HAVE_MVE"
4171 "vpst\;vmvnt %q0, %q2"
4172 [(set_attr "type" "mve_move")
4173 (set_attr "length""8")])
4174
4175;;
4176;; [vnegq_m_s])
4177;;
4178(define_insn "mve_vnegq_m_s<mode>"
4179 [
4180 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4181 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4182 (match_operand:MVE_2 2 "s_register_operand" "w")
4183 (match_operand:HI 3 "vpr_register_operand" "Up")]
4184 VNEGQ_M_S))
4185 ]
4186 "TARGET_HAVE_MVE"
4187 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
4188 [(set_attr "type" "mve_move")
4189 (set_attr "length""8")])
4190
4191;;
4192;; [vpselq_u, vpselq_s])
4193;;
4194(define_insn "mve_vpselq_<supf><mode>"
4195 [
4196 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
4197 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
4198 (match_operand:MVE_1 2 "s_register_operand" "w")
4199 (match_operand:HI 3 "vpr_register_operand" "Up")]
4200 VPSELQ))
4201 ]
4202 "TARGET_HAVE_MVE"
4203 "vpsel %q0, %q1, %q2"
4204 [(set_attr "type" "mve_move")
4205])
4206
4207;;
4208;; [vqabsq_m_s])
4209;;
4210(define_insn "mve_vqabsq_m_s<mode>"
4211 [
4212 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4213 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4214 (match_operand:MVE_2 2 "s_register_operand" "w")
4215 (match_operand:HI 3 "vpr_register_operand" "Up")]
4216 VQABSQ_M_S))
4217 ]
4218 "TARGET_HAVE_MVE"
4219 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
4220 [(set_attr "type" "mve_move")
4221 (set_attr "length""8")])
4222
4223;;
4224;; [vqdmlahq_n_s, vqdmlahq_n_u])
4225;;
4226(define_insn "mve_vqdmlahq_n_<supf><mode>"
4227 [
4228 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4229 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4230 (match_operand:MVE_2 2 "s_register_operand" "w")
4231 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4232 VQDMLAHQ_N))
4233 ]
4234 "TARGET_HAVE_MVE"
4235 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4236 [(set_attr "type" "mve_move")
4237])
4238
4239;;
4240;; [vqnegq_m_s])
4241;;
4242(define_insn "mve_vqnegq_m_s<mode>"
4243 [
4244 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4245 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4246 (match_operand:MVE_2 2 "s_register_operand" "w")
4247 (match_operand:HI 3 "vpr_register_operand" "Up")]
4248 VQNEGQ_M_S))
4249 ]
4250 "TARGET_HAVE_MVE"
4251 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
4252 [(set_attr "type" "mve_move")
4253 (set_attr "length""8")])
4254
4255;;
4256;; [vqrdmladhq_s])
4257;;
4258(define_insn "mve_vqrdmladhq_s<mode>"
4259 [
4260 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4261 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4262 (match_operand:MVE_2 2 "s_register_operand" "w")
4263 (match_operand:MVE_2 3 "s_register_operand" "w")]
4264 VQRDMLADHQ_S))
4265 ]
4266 "TARGET_HAVE_MVE"
4267 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4268 [(set_attr "type" "mve_move")
4269])
4270
4271;;
4272;; [vqrdmladhxq_s])
4273;;
4274(define_insn "mve_vqrdmladhxq_s<mode>"
4275 [
4276 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4277 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4278 (match_operand:MVE_2 2 "s_register_operand" "w")
4279 (match_operand:MVE_2 3 "s_register_operand" "w")]
4280 VQRDMLADHXQ_S))
4281 ]
4282 "TARGET_HAVE_MVE"
4283 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4284 [(set_attr "type" "mve_move")
4285])
4286
4287;;
4288;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
4289;;
4290(define_insn "mve_vqrdmlahq_n_<supf><mode>"
4291 [
4292 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4293 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4294 (match_operand:MVE_2 2 "s_register_operand" "w")
4295 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4296 VQRDMLAHQ_N))
4297 ]
4298 "TARGET_HAVE_MVE"
4299 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4300 [(set_attr "type" "mve_move")
4301])
4302
4303;;
4304;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
4305;;
4306(define_insn "mve_vqrdmlashq_n_<supf><mode>"
4307 [
4308 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4309 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4310 (match_operand:MVE_2 2 "s_register_operand" "w")
4311 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4312 VQRDMLASHQ_N))
4313 ]
4314 "TARGET_HAVE_MVE"
4315 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
4316 [(set_attr "type" "mve_move")
4317])
4318
4319;;
4320;; [vqrdmlsdhq_s])
4321;;
4322(define_insn "mve_vqrdmlsdhq_s<mode>"
4323 [
4324 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4325 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4326 (match_operand:MVE_2 2 "s_register_operand" "w")
4327 (match_operand:MVE_2 3 "s_register_operand" "w")]
4328 VQRDMLSDHQ_S))
4329 ]
4330 "TARGET_HAVE_MVE"
4331 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4332 [(set_attr "type" "mve_move")
4333])
4334
4335;;
4336;; [vqrdmlsdhxq_s])
4337;;
4338(define_insn "mve_vqrdmlsdhxq_s<mode>"
4339 [
4340 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4341 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4342 (match_operand:MVE_2 2 "s_register_operand" "w")
4343 (match_operand:MVE_2 3 "s_register_operand" "w")]
4344 VQRDMLSDHXQ_S))
4345 ]
4346 "TARGET_HAVE_MVE"
4347 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4348 [(set_attr "type" "mve_move")
4349])
4350
4351;;
4352;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
4353;;
4354(define_insn "mve_vqrshlq_m_n_<supf><mode>"
4355 [
4356 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4357 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4358 (match_operand:SI 2 "s_register_operand" "r")
4359 (match_operand:HI 3 "vpr_register_operand" "Up")]
4360 VQRSHLQ_M_N))
4361 ]
4362 "TARGET_HAVE_MVE"
4363 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2"
4364 [(set_attr "type" "mve_move")
4365 (set_attr "length""8")])
4366
4367;;
4368;; [vqshlq_m_r_u, vqshlq_m_r_s])
4369;;
4370(define_insn "mve_vqshlq_m_r_<supf><mode>"
4371 [
4372 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4373 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4374 (match_operand:SI 2 "s_register_operand" "r")
4375 (match_operand:HI 3 "vpr_register_operand" "Up")]
4376 VQSHLQ_M_R))
4377 ]
4378 "TARGET_HAVE_MVE"
4379 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4380 [(set_attr "type" "mve_move")
4381 (set_attr "length""8")])
4382
4383;;
4384;; [vrev64q_m_u, vrev64q_m_s])
4385;;
4386(define_insn "mve_vrev64q_m_<supf><mode>"
4387 [
4388 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4389 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4390 (match_operand:MVE_2 2 "s_register_operand" "w")
4391 (match_operand:HI 3 "vpr_register_operand" "Up")]
4392 VREV64Q_M))
4393 ]
4394 "TARGET_HAVE_MVE"
4395 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
4396 [(set_attr "type" "mve_move")
4397 (set_attr "length""8")])
4398
4399;;
4400;; [vrshlq_m_n_s, vrshlq_m_n_u])
4401;;
4402(define_insn "mve_vrshlq_m_n_<supf><mode>"
4403 [
4404 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4405 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4406 (match_operand:SI 2 "s_register_operand" "r")
4407 (match_operand:HI 3 "vpr_register_operand" "Up")]
4408 VRSHLQ_M_N))
4409 ]
4410 "TARGET_HAVE_MVE"
4411 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4412 [(set_attr "type" "mve_move")
4413 (set_attr "length""8")])
4414
4415;;
4416;; [vshlq_m_r_u, vshlq_m_r_s])
4417;;
4418(define_insn "mve_vshlq_m_r_<supf><mode>"
4419 [
4420 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4421 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4422 (match_operand:SI 2 "s_register_operand" "r")
4423 (match_operand:HI 3 "vpr_register_operand" "Up")]
4424 VSHLQ_M_R))
4425 ]
4426 "TARGET_HAVE_MVE"
4427 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4428 [(set_attr "type" "mve_move")
4429 (set_attr "length""8")])
4430
4431;;
4432;; [vsliq_n_u, vsliq_n_s])
4433;;
4434(define_insn "mve_vsliq_n_<supf><mode>"
4435 [
4436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4437 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4438 (match_operand:MVE_2 2 "s_register_operand" "w")
4439 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
4440 VSLIQ_N))
4441 ]
4442 "TARGET_HAVE_MVE"
4443 "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
4444 [(set_attr "type" "mve_move")
4445])
4446
4447;;
4448;; [vsriq_n_u, vsriq_n_s])
4449;;
4450(define_insn "mve_vsriq_n_<supf><mode>"
4451 [
4452 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4453 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4454 (match_operand:MVE_2 2 "s_register_operand" "w")
4455 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
4456 VSRIQ_N))
4457 ]
4458 "TARGET_HAVE_MVE"
4459 "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
4460 [(set_attr "type" "mve_move")
4461])
4462
4463;;
4464;; [vqdmlsdhxq_s])
4465;;
4466(define_insn "mve_vqdmlsdhxq_s<mode>"
4467 [
4468 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4469 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4470 (match_operand:MVE_2 2 "s_register_operand" "w")
4471 (match_operand:MVE_2 3 "s_register_operand" "w")]
4472 VQDMLSDHXQ_S))
4473 ]
4474 "TARGET_HAVE_MVE"
4475 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4476 [(set_attr "type" "mve_move")
4477])
4478
4479;;
4480;; [vqdmlsdhq_s])
4481;;
4482(define_insn "mve_vqdmlsdhq_s<mode>"
4483 [
4484 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4485 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4486 (match_operand:MVE_2 2 "s_register_operand" "w")
4487 (match_operand:MVE_2 3 "s_register_operand" "w")]
4488 VQDMLSDHQ_S))
4489 ]
4490 "TARGET_HAVE_MVE"
4491 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4492 [(set_attr "type" "mve_move")
4493])
4494
4495;;
4496;; [vqdmladhxq_s])
4497;;
4498(define_insn "mve_vqdmladhxq_s<mode>"
4499 [
4500 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4501 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4502 (match_operand:MVE_2 2 "s_register_operand" "w")
4503 (match_operand:MVE_2 3 "s_register_operand" "w")]
4504 VQDMLADHXQ_S))
4505 ]
4506 "TARGET_HAVE_MVE"
4507 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4508 [(set_attr "type" "mve_move")
4509])
4510
4511;;
4512;; [vqdmladhq_s])
4513;;
4514(define_insn "mve_vqdmladhq_s<mode>"
4515 [
4516 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4517 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4518 (match_operand:MVE_2 2 "s_register_operand" "w")
4519 (match_operand:MVE_2 3 "s_register_operand" "w")]
4520 VQDMLADHQ_S))
4521 ]
4522 "TARGET_HAVE_MVE"
4523 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4524 [(set_attr "type" "mve_move")
4525])
4526
4527;;
4528;; [vmlsdavaxq_s])
4529;;
4530(define_insn "mve_vmlsdavaxq_s<mode>"
4531 [
4532 (set (match_operand:SI 0 "s_register_operand" "=e")
4533 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4534 (match_operand:MVE_2 2 "s_register_operand" "w")
4535 (match_operand:MVE_2 3 "s_register_operand" "w")]
4536 VMLSDAVAXQ_S))
4537 ]
4538 "TARGET_HAVE_MVE"
4539 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4540 [(set_attr "type" "mve_move")
4541])
4542
4543;;
4544;; [vmlsdavaq_s])
4545;;
4546(define_insn "mve_vmlsdavaq_s<mode>"
4547 [
4548 (set (match_operand:SI 0 "s_register_operand" "=e")
4549 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4550 (match_operand:MVE_2 2 "s_register_operand" "w")
4551 (match_operand:MVE_2 3 "s_register_operand" "w")]
4552 VMLSDAVAQ_S))
4553 ]
4554 "TARGET_HAVE_MVE"
4555 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4556 [(set_attr "type" "mve_move")
4557])
4558
4559;;
4560;; [vmladavaxq_s])
4561;;
4562(define_insn "mve_vmladavaxq_s<mode>"
4563 [
4564 (set (match_operand:SI 0 "s_register_operand" "=e")
4565 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4566 (match_operand:MVE_2 2 "s_register_operand" "w")
4567 (match_operand:MVE_2 3 "s_register_operand" "w")]
4568 VMLADAVAXQ_S))
4569 ]
4570 "TARGET_HAVE_MVE"
4571 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4572 [(set_attr "type" "mve_move")
4573])
e3678b44
SP		 4574;;
4575;; [vabsq_m_f])
4576;;
4577(define_insn "mve_vabsq_m_f<mode>"
4578 [
4579 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4580 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4581 (match_operand:MVE_0 2 "s_register_operand" "w")
4582 (match_operand:HI 3 "vpr_register_operand" "Up")]
4583 VABSQ_M_F))
4584 ]
4585 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4586 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
4587 [(set_attr "type" "mve_move")
4588 (set_attr "length""8")])
4589
4590;;
4591;; [vaddlvaq_p_s vaddlvaq_p_u])
4592;;
4593(define_insn "mve_vaddlvaq_p_<supf>v4si"
4594 [
4595 (set (match_operand:DI 0 "s_register_operand" "=r")
4596 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4597 (match_operand:V4SI 2 "s_register_operand" "w")
4598 (match_operand:HI 3 "vpr_register_operand" "Up")]
4599 VADDLVAQ_P))
4600 ]
4601 "TARGET_HAVE_MVE"
4602 "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4603 [(set_attr "type" "mve_move")
4604 (set_attr "length""8")])
4605;;
4606;; [vcmlaq_f])
4607;;
4608(define_insn "mve_vcmlaq_f<mode>"
4609 [
4610 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4611 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4612 (match_operand:MVE_0 2 "s_register_operand" "w")
4613 (match_operand:MVE_0 3 "s_register_operand" "w")]
4614 VCMLAQ_F))
4615 ]
4616 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4617 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4618 [(set_attr "type" "mve_move")
4619])
4620
4621;;
4622;; [vcmlaq_rot180_f])
4623;;
4624(define_insn "mve_vcmlaq_rot180_f<mode>"
4625 [
4626 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4627 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4628 (match_operand:MVE_0 2 "s_register_operand" "w")
4629 (match_operand:MVE_0 3 "s_register_operand" "w")]
4630 VCMLAQ_ROT180_F))
4631 ]
4632 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4633 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4634 [(set_attr "type" "mve_move")
4635])
4636
4637;;
4638;; [vcmlaq_rot270_f])
4639;;
4640(define_insn "mve_vcmlaq_rot270_f<mode>"
4641 [
4642 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4643 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4644 (match_operand:MVE_0 2 "s_register_operand" "w")
4645 (match_operand:MVE_0 3 "s_register_operand" "w")]
4646 VCMLAQ_ROT270_F))
4647 ]
4648 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4649 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4650 [(set_attr "type" "mve_move")
4651])
4652
4653;;
4654;; [vcmlaq_rot90_f])
4655;;
4656(define_insn "mve_vcmlaq_rot90_f<mode>"
4657 [
4658 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4659 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4660 (match_operand:MVE_0 2 "s_register_operand" "w")
4661 (match_operand:MVE_0 3 "s_register_operand" "w")]
4662 VCMLAQ_ROT90_F))
4663 ]
4664 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4665 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4666 [(set_attr "type" "mve_move")
4667])
4668
4669;;
4670;; [vcmpeqq_m_n_f])
4671;;
4672(define_insn "mve_vcmpeqq_m_n_f<mode>"
4673 [
4674 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4675 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4676 (match_operand:<V_elem> 2 "s_register_operand" "r")
4677 (match_operand:HI 3 "vpr_register_operand" "Up")]
4678 VCMPEQQ_M_N_F))
4679 ]
4680 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4681 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2"
4682 [(set_attr "type" "mve_move")
4683 (set_attr "length""8")])
4684
4685;;
4686;; [vcmpgeq_m_f])
4687;;
4688(define_insn "mve_vcmpgeq_m_f<mode>"
4689 [
4690 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4691 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4692 (match_operand:MVE_0 2 "s_register_operand" "w")
4693 (match_operand:HI 3 "vpr_register_operand" "Up")]
4694 VCMPGEQ_M_F))
4695 ]
4696 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4697 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2"
4698 [(set_attr "type" "mve_move")
4699 (set_attr "length""8")])
4700
4701;;
4702;; [vcmpgeq_m_n_f])
4703;;
4704(define_insn "mve_vcmpgeq_m_n_f<mode>"
4705 [
4706 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4707 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4708 (match_operand:<V_elem> 2 "s_register_operand" "r")
4709 (match_operand:HI 3 "vpr_register_operand" "Up")]
4710 VCMPGEQ_M_N_F))
4711 ]
4712 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4713 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2"
4714 [(set_attr "type" "mve_move")
4715 (set_attr "length""8")])
4716
4717;;
4718;; [vcmpgtq_m_f])
4719;;
4720(define_insn "mve_vcmpgtq_m_f<mode>"
4721 [
4722 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4723 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4724 (match_operand:MVE_0 2 "s_register_operand" "w")
4725 (match_operand:HI 3 "vpr_register_operand" "Up")]
4726 VCMPGTQ_M_F))
4727 ]
4728 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4729 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2"
4730 [(set_attr "type" "mve_move")
4731 (set_attr "length""8")])
4732
4733;;
4734;; [vcmpgtq_m_n_f])
4735;;
4736(define_insn "mve_vcmpgtq_m_n_f<mode>"
4737 [
4738 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4739 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4740 (match_operand:<V_elem> 2 "s_register_operand" "r")
4741 (match_operand:HI 3 "vpr_register_operand" "Up")]
4742 VCMPGTQ_M_N_F))
4743 ]
4744 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4745 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2"
4746 [(set_attr "type" "mve_move")
4747 (set_attr "length""8")])
4748
4749;;
4750;; [vcmpleq_m_f])
4751;;
4752(define_insn "mve_vcmpleq_m_f<mode>"
4753 [
4754 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4755 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4756 (match_operand:MVE_0 2 "s_register_operand" "w")
4757 (match_operand:HI 3 "vpr_register_operand" "Up")]
4758 VCMPLEQ_M_F))
4759 ]
4760 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4761 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2"
4762 [(set_attr "type" "mve_move")
4763 (set_attr "length""8")])
4764
4765;;
4766;; [vcmpleq_m_n_f])
4767;;
4768(define_insn "mve_vcmpleq_m_n_f<mode>"
4769 [
4770 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4771 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4772 (match_operand:<V_elem> 2 "s_register_operand" "r")
4773 (match_operand:HI 3 "vpr_register_operand" "Up")]
4774 VCMPLEQ_M_N_F))
4775 ]
4776 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4777 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2"
4778 [(set_attr "type" "mve_move")
4779 (set_attr "length""8")])
4780
4781;;
4782;; [vcmpltq_m_f])
4783;;
4784(define_insn "mve_vcmpltq_m_f<mode>"
4785 [
4786 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4787 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4788 (match_operand:MVE_0 2 "s_register_operand" "w")
4789 (match_operand:HI 3 "vpr_register_operand" "Up")]
4790 VCMPLTQ_M_F))
4791 ]
4792 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4793 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2"
4794 [(set_attr "type" "mve_move")
4795 (set_attr "length""8")])
4796
4797;;
4798;; [vcmpltq_m_n_f])
4799;;
4800(define_insn "mve_vcmpltq_m_n_f<mode>"
4801 [
4802 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4803 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4804 (match_operand:<V_elem> 2 "s_register_operand" "r")
4805 (match_operand:HI 3 "vpr_register_operand" "Up")]
4806 VCMPLTQ_M_N_F))
4807 ]
4808 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4809 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2"
4810 [(set_attr "type" "mve_move")
4811 (set_attr "length""8")])
4812
4813;;
4814;; [vcmpneq_m_f])
4815;;
4816(define_insn "mve_vcmpneq_m_f<mode>"
4817 [
4818 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4819 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4820 (match_operand:MVE_0 2 "s_register_operand" "w")
4821 (match_operand:HI 3 "vpr_register_operand" "Up")]
4822 VCMPNEQ_M_F))
4823 ]
4824 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4825 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2"
4826 [(set_attr "type" "mve_move")
4827 (set_attr "length""8")])
4828
4829;;
4830;; [vcmpneq_m_n_f])
4831;;
4832(define_insn "mve_vcmpneq_m_n_f<mode>"
4833 [
4834 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4835 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4836 (match_operand:<V_elem> 2 "s_register_operand" "r")
4837 (match_operand:HI 3 "vpr_register_operand" "Up")]
4838 VCMPNEQ_M_N_F))
4839 ]
4840 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4841 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2"
4842 [(set_attr "type" "mve_move")
4843 (set_attr "length""8")])
4844
4845;;
4846;; [vcvtbq_m_f16_f32])
4847;;
4848(define_insn "mve_vcvtbq_m_f16_f32v8hf"
4849 [
4850 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4851 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4852 (match_operand:V4SF 2 "s_register_operand" "w")
4853 (match_operand:HI 3 "vpr_register_operand" "Up")]
4854 VCVTBQ_M_F16_F32))
4855 ]
4856 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4857 "vpst\;vcvtbt.f16.f32 %q0, %q2"
4858 [(set_attr "type" "mve_move")
4859 (set_attr "length""8")])
4860
4861;;
4862;; [vcvtbq_m_f32_f16])
4863;;
4864(define_insn "mve_vcvtbq_m_f32_f16v4sf"
4865 [
4866 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4867 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4868 (match_operand:V8HF 2 "s_register_operand" "w")
4869 (match_operand:HI 3 "vpr_register_operand" "Up")]
4870 VCVTBQ_M_F32_F16))
4871 ]
4872 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4873 "vpst\;vcvtbt.f32.f16 %q0, %q2"
4874 [(set_attr "type" "mve_move")
4875 (set_attr "length""8")])
4876
4877;;
4878;; [vcvttq_m_f16_f32])
4879;;
4880(define_insn "mve_vcvttq_m_f16_f32v8hf"
4881 [
4882 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4883 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4884 (match_operand:V4SF 2 "s_register_operand" "w")
4885 (match_operand:HI 3 "vpr_register_operand" "Up")]
4886 VCVTTQ_M_F16_F32))
4887 ]
4888 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4889 "vpst\;vcvttt.f16.f32 %q0, %q2"
4890 [(set_attr "type" "mve_move")
4891 (set_attr "length""8")])
4892
4893;;
4894;; [vcvttq_m_f32_f16])
4895;;
4896(define_insn "mve_vcvttq_m_f32_f16v4sf"
4897 [
4898 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4899 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4900 (match_operand:V8HF 2 "s_register_operand" "w")
4901 (match_operand:HI 3 "vpr_register_operand" "Up")]
4902 VCVTTQ_M_F32_F16))
4903 ]
4904 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4905 "vpst\;vcvttt.f32.f16 %q0, %q2"
4906 [(set_attr "type" "mve_move")
4907 (set_attr "length""8")])
4908
4909;;
4910;; [vdupq_m_n_f])
4911;;
4912(define_insn "mve_vdupq_m_n_f<mode>"
4913 [
4914 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4915 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4916 (match_operand:<V_elem> 2 "s_register_operand" "r")
4917 (match_operand:HI 3 "vpr_register_operand" "Up")]
4918 VDUPQ_M_N_F))
4919 ]
4920 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4921 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4922 [(set_attr "type" "mve_move")
4923 (set_attr "length""8")])
4924
4925;;
4926;; [vfmaq_f])
4927;;
4928(define_insn "mve_vfmaq_f<mode>"
4929 [
4930 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4931 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4932 (match_operand:MVE_0 2 "s_register_operand" "w")
4933 (match_operand:MVE_0 3 "s_register_operand" "w")]
4934 VFMAQ_F))
4935 ]
4936 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4937 "vfma.f%#<V_sz_elem> %q0, %q2, %q3"
4938 [(set_attr "type" "mve_move")
4939])
4940
4941;;
4942;; [vfmaq_n_f])
4943;;
4944(define_insn "mve_vfmaq_n_f<mode>"
4945 [
4946 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4947 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4948 (match_operand:MVE_0 2 "s_register_operand" "w")
4949 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4950 VFMAQ_N_F))
4951 ]
4952 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4953 "vfma.f%#<V_sz_elem> %q0, %q2, %3"
4954 [(set_attr "type" "mve_move")
4955])
4956
4957;;
4958;; [vfmasq_n_f])
4959;;
4960(define_insn "mve_vfmasq_n_f<mode>"
4961 [
4962 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4963 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4964 (match_operand:MVE_0 2 "s_register_operand" "w")
4965 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4966 VFMASQ_N_F))
4967 ]
4968 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4969 "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
4970 [(set_attr "type" "mve_move")
4971])
4972;;
4973;; [vfmsq_f])
4974;;
4975(define_insn "mve_vfmsq_f<mode>"
4976 [
4977 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4978 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4979 (match_operand:MVE_0 2 "s_register_operand" "w")
4980 (match_operand:MVE_0 3 "s_register_operand" "w")]
4981 VFMSQ_F))
4982 ]
4983 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4984 "vfms.f%#<V_sz_elem> %q0, %q2, %q3"
4985 [(set_attr "type" "mve_move")
4986])
4987
4988;;
4989;; [vmaxnmaq_m_f])
4990;;
4991(define_insn "mve_vmaxnmaq_m_f<mode>"
4992 [
4993 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4994 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4995 (match_operand:MVE_0 2 "s_register_operand" "w")
4996 (match_operand:HI 3 "vpr_register_operand" "Up")]
4997 VMAXNMAQ_M_F))
4998 ]
4999 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5000 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2"
5001 [(set_attr "type" "mve_move")
5002 (set_attr "length""8")])
5003;;
5004;; [vmaxnmavq_p_f])
5005;;
5006(define_insn "mve_vmaxnmavq_p_f<mode>"
5007 [
5008 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5009 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5010 (match_operand:MVE_0 2 "s_register_operand" "w")
5011 (match_operand:HI 3 "vpr_register_operand" "Up")]
5012 VMAXNMAVQ_P_F))
5013 ]
5014 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5015 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2"
5016 [(set_attr "type" "mve_move")
5017 (set_attr "length""8")])
5018
5019;;
5020;; [vmaxnmvq_p_f])
5021;;
5022(define_insn "mve_vmaxnmvq_p_f<mode>"
5023 [
5024 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5025 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5026 (match_operand:MVE_0 2 "s_register_operand" "w")
5027 (match_operand:HI 3 "vpr_register_operand" "Up")]
5028 VMAXNMVQ_P_F))
5029 ]
5030 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5031 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2"
5032 [(set_attr "type" "mve_move")
5033 (set_attr "length""8")])
5034;;
5035;; [vminnmaq_m_f])
5036;;
5037(define_insn "mve_vminnmaq_m_f<mode>"
5038 [
5039 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5040 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5041 (match_operand:MVE_0 2 "s_register_operand" "w")
5042 (match_operand:HI 3 "vpr_register_operand" "Up")]
5043 VMINNMAQ_M_F))
5044 ]
5045 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5046 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2"
5047 [(set_attr "type" "mve_move")
5048 (set_attr "length""8")])
5049
5050;;
5051;; [vminnmavq_p_f])
5052;;
5053(define_insn "mve_vminnmavq_p_f<mode>"
5054 [
5055 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5056 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5057 (match_operand:MVE_0 2 "s_register_operand" "w")
5058 (match_operand:HI 3 "vpr_register_operand" "Up")]
5059 VMINNMAVQ_P_F))
5060 ]
5061 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5062 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2"
5063 [(set_attr "type" "mve_move")
5064 (set_attr "length""8")])
5065;;
5066;; [vminnmvq_p_f])
5067;;
5068(define_insn "mve_vminnmvq_p_f<mode>"
5069 [
5070 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5071 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5072 (match_operand:MVE_0 2 "s_register_operand" "w")
5073 (match_operand:HI 3 "vpr_register_operand" "Up")]
5074 VMINNMVQ_P_F))
5075 ]
5076 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5077 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2"
5078 [(set_attr "type" "mve_move")
5079 (set_attr "length""8")])
5080
5081;;
5082;; [vmlaldavaq_s, vmlaldavaq_u])
5083;;
5084(define_insn "mve_vmlaldavaq_<supf><mode>"
5085 [
5086 (set (match_operand:DI 0 "s_register_operand" "=r")
5087 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5088 (match_operand:MVE_5 2 "s_register_operand" "w")
5089 (match_operand:MVE_5 3 "s_register_operand" "w")]
5090 VMLALDAVAQ))
5091 ]
5092 "TARGET_HAVE_MVE"
5093 "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5094 [(set_attr "type" "mve_move")
5095])
5096
5097;;
5098;; [vmlaldavaxq_s])
5099;;
5100(define_insn "mve_vmlaldavaxq_s<mode>"
5101 [
5102 (set (match_operand:DI 0 "s_register_operand" "=r")
5103 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5104 (match_operand:MVE_5 2 "s_register_operand" "w")
5105 (match_operand:MVE_5 3 "s_register_operand" "w")]
5106 VMLALDAVAXQ_S))
5107 ]
5108 "TARGET_HAVE_MVE"
5109 "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5110 [(set_attr "type" "mve_move")
5111])
5112
5113;;
5114;; [vmlaldavq_p_u, vmlaldavq_p_s])
5115;;
5116(define_insn "mve_vmlaldavq_p_<supf><mode>"
5117 [
5118 (set (match_operand:DI 0 "s_register_operand" "=r")
5119 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5120 (match_operand:MVE_5 2 "s_register_operand" "w")
5121 (match_operand:HI 3 "vpr_register_operand" "Up")]
5122 VMLALDAVQ_P))
5123 ]
5124 "TARGET_HAVE_MVE"
5125 "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5126 [(set_attr "type" "mve_move")
5127 (set_attr "length""8")])
5128
5129;;
5130;; [vmlaldavxq_p_s])
5131;;
5132(define_insn "mve_vmlaldavxq_p_s<mode>"
5133 [
5134 (set (match_operand:DI 0 "s_register_operand" "=r")
5135 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5136 (match_operand:MVE_5 2 "s_register_operand" "w")
5137 (match_operand:HI 3 "vpr_register_operand" "Up")]
5138 VMLALDAVXQ_P_S))
5139 ]
5140 "TARGET_HAVE_MVE"
5141 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
5142 [(set_attr "type" "mve_move")
5143 (set_attr "length""8")])
5144;;
5145;; [vmlsldavaq_s])
5146;;
5147(define_insn "mve_vmlsldavaq_s<mode>"
5148 [
5149 (set (match_operand:DI 0 "s_register_operand" "=r")
5150 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5151 (match_operand:MVE_5 2 "s_register_operand" "w")
5152 (match_operand:MVE_5 3 "s_register_operand" "w")]
5153 VMLSLDAVAQ_S))
5154 ]
5155 "TARGET_HAVE_MVE"
5156 "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5157 [(set_attr "type" "mve_move")
5158])
5159
5160;;
5161;; [vmlsldavaxq_s])
5162;;
5163(define_insn "mve_vmlsldavaxq_s<mode>"
5164 [
5165 (set (match_operand:DI 0 "s_register_operand" "=r")
5166 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5167 (match_operand:MVE_5 2 "s_register_operand" "w")
5168 (match_operand:MVE_5 3 "s_register_operand" "w")]
5169 VMLSLDAVAXQ_S))
5170 ]
5171 "TARGET_HAVE_MVE"
5172 "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5173 [(set_attr "type" "mve_move")
5174])
5175
5176;;
5177;; [vmlsldavq_p_s])
5178;;
5179(define_insn "mve_vmlsldavq_p_s<mode>"
5180 [
5181 (set (match_operand:DI 0 "s_register_operand" "=r")
5182 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5183 (match_operand:MVE_5 2 "s_register_operand" "w")
5184 (match_operand:HI 3 "vpr_register_operand" "Up")]
5185 VMLSLDAVQ_P_S))
5186 ]
5187 "TARGET_HAVE_MVE"
5188 "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5189 [(set_attr "type" "mve_move")
5190 (set_attr "length""8")])
5191
5192;;
5193;; [vmlsldavxq_p_s])
5194;;
5195(define_insn "mve_vmlsldavxq_p_s<mode>"
5196 [
5197 (set (match_operand:DI 0 "s_register_operand" "=r")
5198 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5199 (match_operand:MVE_5 2 "s_register_operand" "w")
5200 (match_operand:HI 3 "vpr_register_operand" "Up")]
5201 VMLSLDAVXQ_P_S))
5202 ]
5203 "TARGET_HAVE_MVE"
5204 "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5205 [(set_attr "type" "mve_move")
5206 (set_attr "length""8")])
5207;;
5208;; [vmovlbq_m_u, vmovlbq_m_s])
5209;;
5210(define_insn "mve_vmovlbq_m_<supf><mode>"
5211 [
5212 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5213 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5214 (match_operand:MVE_3 2 "s_register_operand" "w")
5215 (match_operand:HI 3 "vpr_register_operand" "Up")]
5216 VMOVLBQ_M))
5217 ]
5218 "TARGET_HAVE_MVE"
5219 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2"
5220 [(set_attr "type" "mve_move")
5221 (set_attr "length""8")])
5222;;
5223;; [vmovltq_m_u, vmovltq_m_s])
5224;;
5225(define_insn "mve_vmovltq_m_<supf><mode>"
5226 [
5227 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5228 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5229 (match_operand:MVE_3 2 "s_register_operand" "w")
5230 (match_operand:HI 3 "vpr_register_operand" "Up")]
5231 VMOVLTQ_M))
5232 ]
5233 "TARGET_HAVE_MVE"
5234 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2"
5235 [(set_attr "type" "mve_move")
5236 (set_attr "length""8")])
5237;;
5238;; [vmovnbq_m_u, vmovnbq_m_s])
5239;;
5240(define_insn "mve_vmovnbq_m_<supf><mode>"
5241 [
5242 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5243 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5244 (match_operand:MVE_5 2 "s_register_operand" "w")
5245 (match_operand:HI 3 "vpr_register_operand" "Up")]
5246 VMOVNBQ_M))
5247 ]
5248 "TARGET_HAVE_MVE"
5249 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
5250 [(set_attr "type" "mve_move")
5251 (set_attr "length""8")])
5252
5253;;
5254;; [vmovntq_m_u, vmovntq_m_s])
5255;;
5256(define_insn "mve_vmovntq_m_<supf><mode>"
5257 [
5258 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5259 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5260 (match_operand:MVE_5 2 "s_register_operand" "w")
5261 (match_operand:HI 3 "vpr_register_operand" "Up")]
5262 VMOVNTQ_M))
5263 ]
5264 "TARGET_HAVE_MVE"
5265 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
5266 [(set_attr "type" "mve_move")
5267 (set_attr "length""8")])
5268
5269;;
5270;; [vmvnq_m_n_u, vmvnq_m_n_s])
5271;;
5272(define_insn "mve_vmvnq_m_n_<supf><mode>"
5273 [
5274 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5275 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5276 (match_operand:SI 2 "immediate_operand" "i")
5277 (match_operand:HI 3 "vpr_register_operand" "Up")]
5278 VMVNQ_M_N))
5279 ]
5280 "TARGET_HAVE_MVE"
5281 "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
5282 [(set_attr "type" "mve_move")
5283 (set_attr "length""8")])
5284;;
5285;; [vnegq_m_f])
5286;;
5287(define_insn "mve_vnegq_m_f<mode>"
5288 [
5289 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5290 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5291 (match_operand:MVE_0 2 "s_register_operand" "w")
5292 (match_operand:HI 3 "vpr_register_operand" "Up")]
5293 VNEGQ_M_F))
5294 ]
5295 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5296 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
5297 [(set_attr "type" "mve_move")
5298 (set_attr "length""8")])
5299
5300;;
5301;; [vorrq_m_n_s, vorrq_m_n_u])
5302;;
5303(define_insn "mve_vorrq_m_n_<supf><mode>"
5304 [
5305 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5306 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5307 (match_operand:SI 2 "immediate_operand" "i")
5308 (match_operand:HI 3 "vpr_register_operand" "Up")]
5309 VORRQ_M_N))
5310 ]
5311 "TARGET_HAVE_MVE"
5312 "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
5313 [(set_attr "type" "mve_move")
5314 (set_attr "length""8")])
5315;;
5316;; [vpselq_f])
5317;;
5318(define_insn "mve_vpselq_f<mode>"
5319 [
5320 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5321 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
5322 (match_operand:MVE_0 2 "s_register_operand" "w")
5323 (match_operand:HI 3 "vpr_register_operand" "Up")]
5324 VPSELQ_F))
5325 ]
5326 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5327 "vpsel %q0, %q1, %q2"
5328 [(set_attr "type" "mve_move")
5329])
5330
5331;;
5332;; [vqmovnbq_m_s, vqmovnbq_m_u])
5333;;
5334(define_insn "mve_vqmovnbq_m_<supf><mode>"
5335 [
5336 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5337 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5338 (match_operand:MVE_5 2 "s_register_operand" "w")
5339 (match_operand:HI 3 "vpr_register_operand" "Up")]
5340 VQMOVNBQ_M))
5341 ]
5342 "TARGET_HAVE_MVE"
5343 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2"
5344 [(set_attr "type" "mve_move")
5345 (set_attr "length""8")])
5346
5347;;
5348;; [vqmovntq_m_u, vqmovntq_m_s])
5349;;
5350(define_insn "mve_vqmovntq_m_<supf><mode>"
5351 [
5352 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5353 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5354 (match_operand:MVE_5 2 "s_register_operand" "w")
5355 (match_operand:HI 3 "vpr_register_operand" "Up")]
5356 VQMOVNTQ_M))
5357 ]
5358 "TARGET_HAVE_MVE"
5359 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2"
5360 [(set_attr "type" "mve_move")
5361 (set_attr "length""8")])
5362
5363;;
5364;; [vqmovunbq_m_s])
5365;;
5366(define_insn "mve_vqmovunbq_m_s<mode>"
5367 [
5368 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5369 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5370 (match_operand:MVE_5 2 "s_register_operand" "w")
5371 (match_operand:HI 3 "vpr_register_operand" "Up")]
5372 VQMOVUNBQ_M_S))
5373 ]
5374 "TARGET_HAVE_MVE"
5375 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2"
5376 [(set_attr "type" "mve_move")
5377 (set_attr "length""8")])
5378
5379;;
5380;; [vqmovuntq_m_s])
5381;;
5382(define_insn "mve_vqmovuntq_m_s<mode>"
5383 [
5384 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5385 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5386 (match_operand:MVE_5 2 "s_register_operand" "w")
5387 (match_operand:HI 3 "vpr_register_operand" "Up")]
5388 VQMOVUNTQ_M_S))
5389 ]
5390 "TARGET_HAVE_MVE"
5391 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2"
5392 [(set_attr "type" "mve_move")
5393 (set_attr "length""8")])
5394
5395;;
5396;; [vqrshrntq_n_u, vqrshrntq_n_s])
5397;;
5398(define_insn "mve_vqrshrntq_n_<supf><mode>"
5399 [
5400 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5401 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5402 (match_operand:MVE_5 2 "s_register_operand" "w")
5403 (match_operand:SI 3 "mve_imm_8" "Rb")]
5404 VQRSHRNTQ_N))
5405 ]
5406 "TARGET_HAVE_MVE"
5407 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5408 [(set_attr "type" "mve_move")
5409])
5410
5411;;
5412;; [vqrshruntq_n_s])
5413;;
5414(define_insn "mve_vqrshruntq_n_s<mode>"
5415 [
5416 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5417 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5418 (match_operand:MVE_5 2 "s_register_operand" "w")
5419 (match_operand:SI 3 "mve_imm_8" "Rb")]
5420 VQRSHRUNTQ_N_S))
5421 ]
5422 "TARGET_HAVE_MVE"
5423 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5424 [(set_attr "type" "mve_move")
5425])
5426
5427;;
5428;; [vqshrnbq_n_u, vqshrnbq_n_s])
5429;;
5430(define_insn "mve_vqshrnbq_n_<supf><mode>"
5431 [
5432 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5433 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5434 (match_operand:MVE_5 2 "s_register_operand" "w")
5435 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
5436 VQSHRNBQ_N))
5437 ]
5438 "TARGET_HAVE_MVE"
5439 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5440 [(set_attr "type" "mve_move")
5441])
5442
5443;;
5444;; [vqshrntq_n_u, vqshrntq_n_s])
5445;;
5446(define_insn "mve_vqshrntq_n_<supf><mode>"
5447 [
5448 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5449 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5450 (match_operand:MVE_5 2 "s_register_operand" "w")
5451 (match_operand:SI 3 "mve_imm_8" "Rb")]
5452 VQSHRNTQ_N))
5453 ]
5454 "TARGET_HAVE_MVE"
5455 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5456 [(set_attr "type" "mve_move")
5457])
5458
5459;;
5460;; [vqshrunbq_n_s])
5461;;
5462(define_insn "mve_vqshrunbq_n_s<mode>"
5463 [
5464 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5465 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5466 (match_operand:MVE_5 2 "s_register_operand" "w")
5467 (match_operand:SI 3 "immediate_operand" "i")]
5468 VQSHRUNBQ_N_S))
5469 ]
5470 "TARGET_HAVE_MVE"
5471 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3"
5472 [(set_attr "type" "mve_move")
5473])
5474
5475;;
5476;; [vqshruntq_n_s])
5477;;
5478(define_insn "mve_vqshruntq_n_s<mode>"
5479 [
5480 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5481 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5482 (match_operand:MVE_5 2 "s_register_operand" "w")
5483 (match_operand:SI 3 "mve_imm_8" "Rb")]
5484 VQSHRUNTQ_N_S))
5485 ]
5486 "TARGET_HAVE_MVE"
5487 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5488 [(set_attr "type" "mve_move")
5489])
5490
5491;;
5492;; [vrev32q_m_f])
5493;;
5494(define_insn "mve_vrev32q_m_fv8hf"
5495 [
5496 (set (match_operand:V8HF 0 "s_register_operand" "=w")
5497 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5498 (match_operand:V8HF 2 "s_register_operand" "w")
5499 (match_operand:HI 3 "vpr_register_operand" "Up")]
5500 VREV32Q_M_F))
5501 ]
5502 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5503 "vpst\;vrev32t.16 %q0, %q2"
5504 [(set_attr "type" "mve_move")
5505 (set_attr "length""8")])
5506
5507;;
5508;; [vrev32q_m_s, vrev32q_m_u])
5509;;
5510(define_insn "mve_vrev32q_m_<supf><mode>"
5511 [
5512 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5513 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5514 (match_operand:MVE_3 2 "s_register_operand" "w")
5515 (match_operand:HI 3 "vpr_register_operand" "Up")]
5516 VREV32Q_M))
5517 ]
5518 "TARGET_HAVE_MVE"
5519 "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
5520 [(set_attr "type" "mve_move")
5521 (set_attr "length""8")])
5522
5523;;
5524;; [vrev64q_m_f])
5525;;
5526(define_insn "mve_vrev64q_m_f<mode>"
5527 [
5528 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5529 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5530 (match_operand:MVE_0 2 "s_register_operand" "w")
5531 (match_operand:HI 3 "vpr_register_operand" "Up")]
5532 VREV64Q_M_F))
5533 ]
5534 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5535 "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
5536 [(set_attr "type" "mve_move")
5537 (set_attr "length""8")])
5538
5539;;
5540;; [vrmlaldavhaxq_s])
5541;;
5542(define_insn "mve_vrmlaldavhaxq_sv4si"
5543 [
5544 (set (match_operand:DI 0 "s_register_operand" "=r")
5545 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5546 (match_operand:V4SI 2 "s_register_operand" "w")
5547 (match_operand:V4SI 3 "s_register_operand" "w")]
5548 VRMLALDAVHAXQ_S))
5549 ]
5550 "TARGET_HAVE_MVE"
5551 "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5552 [(set_attr "type" "mve_move")
5553])
5554
5555;;
5556;; [vrmlaldavhxq_p_s])
5557;;
5558(define_insn "mve_vrmlaldavhxq_p_sv4si"
5559 [
5560 (set (match_operand:DI 0 "s_register_operand" "=r")
5561 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5562 (match_operand:V4SI 2 "s_register_operand" "w")
5563 (match_operand:HI 3 "vpr_register_operand" "Up")]
5564 VRMLALDAVHXQ_P_S))
5565 ]
5566 "TARGET_HAVE_MVE"
5567 "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5568 [(set_attr "type" "mve_move")
5569 (set_attr "length""8")])
5570
5571;;
5572;; [vrmlsldavhaxq_s])
5573;;
5574(define_insn "mve_vrmlsldavhaxq_sv4si"
5575 [
5576 (set (match_operand:DI 0 "s_register_operand" "=r")
5577 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5578 (match_operand:V4SI 2 "s_register_operand" "w")
5579 (match_operand:V4SI 3 "s_register_operand" "w")]
5580 VRMLSLDAVHAXQ_S))
5581 ]
5582 "TARGET_HAVE_MVE"
5583 "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5584 [(set_attr "type" "mve_move")
5585])
5586
5587;;
5588;; [vrmlsldavhq_p_s])
5589;;
5590(define_insn "mve_vrmlsldavhq_p_sv4si"
5591 [
5592 (set (match_operand:DI 0 "s_register_operand" "=r")
5593 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5594 (match_operand:V4SI 2 "s_register_operand" "w")
5595 (match_operand:HI 3 "vpr_register_operand" "Up")]
5596 VRMLSLDAVHQ_P_S))
5597 ]
5598 "TARGET_HAVE_MVE"
5599 "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5600 [(set_attr "type" "mve_move")
5601 (set_attr "length""8")])
5602
5603;;
5604;; [vrmlsldavhxq_p_s])
5605;;
5606(define_insn "mve_vrmlsldavhxq_p_sv4si"
5607 [
5608 (set (match_operand:DI 0 "s_register_operand" "=r")
5609 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5610 (match_operand:V4SI 2 "s_register_operand" "w")
5611 (match_operand:HI 3 "vpr_register_operand" "Up")]
5612 VRMLSLDAVHXQ_P_S))
5613 ]
5614 "TARGET_HAVE_MVE"
5615 "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5616 [(set_attr "type" "mve_move")
5617 (set_attr "length""8")])
5618
5619;;
5620;; [vrndaq_m_f])
5621;;
5622(define_insn "mve_vrndaq_m_f<mode>"
5623 [
5624 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5625 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5626 (match_operand:MVE_0 2 "s_register_operand" "w")
5627 (match_operand:HI 3 "vpr_register_operand" "Up")]
5628 VRNDAQ_M_F))
5629 ]
5630 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5631 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5632 [(set_attr "type" "mve_move")
5633 (set_attr "length""8")])
5634
5635;;
5636;; [vrndmq_m_f])
5637;;
5638(define_insn "mve_vrndmq_m_f<mode>"
5639 [
5640 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5641 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5642 (match_operand:MVE_0 2 "s_register_operand" "w")
5643 (match_operand:HI 3 "vpr_register_operand" "Up")]
5644 VRNDMQ_M_F))
5645 ]
5646 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5647 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5648 [(set_attr "type" "mve_move")
5649 (set_attr "length""8")])
5650
5651;;
5652;; [vrndnq_m_f])
5653;;
5654(define_insn "mve_vrndnq_m_f<mode>"
5655 [
5656 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5657 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5658 (match_operand:MVE_0 2 "s_register_operand" "w")
5659 (match_operand:HI 3 "vpr_register_operand" "Up")]
5660 VRNDNQ_M_F))
5661 ]
5662 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5663 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5664 [(set_attr "type" "mve_move")
5665 (set_attr "length""8")])
5666
5667;;
5668;; [vrndpq_m_f])
5669;;
5670(define_insn "mve_vrndpq_m_f<mode>"
5671 [
5672 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5673 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5674 (match_operand:MVE_0 2 "s_register_operand" "w")
5675 (match_operand:HI 3 "vpr_register_operand" "Up")]
5676 VRNDPQ_M_F))
5677 ]
5678 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5679 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5680 [(set_attr "type" "mve_move")
5681 (set_attr "length""8")])
5682
5683;;
5684;; [vrndxq_m_f])
5685;;
5686(define_insn "mve_vrndxq_m_f<mode>"
5687 [
5688 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5689 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5690 (match_operand:MVE_0 2 "s_register_operand" "w")
5691 (match_operand:HI 3 "vpr_register_operand" "Up")]
5692 VRNDXQ_M_F))
5693 ]
5694 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5695 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5696 [(set_attr "type" "mve_move")
5697 (set_attr "length""8")])
5698
5699;;
5700;; [vrshrnbq_n_s, vrshrnbq_n_u])
5701;;
5702(define_insn "mve_vrshrnbq_n_<supf><mode>"
5703 [
5704 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5705 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5706 (match_operand:MVE_5 2 "s_register_operand" "w")
5707 (match_operand:SI 3 "mve_imm_8" "Rb")]
5708 VRSHRNBQ_N))
5709 ]
5710 "TARGET_HAVE_MVE"
5711 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5712 [(set_attr "type" "mve_move")
5713])
5714
5715;;
5716;; [vrshrntq_n_u, vrshrntq_n_s])
5717;;
5718(define_insn "mve_vrshrntq_n_<supf><mode>"
5719 [
5720 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5721 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5722 (match_operand:MVE_5 2 "s_register_operand" "w")
5723 (match_operand:SI 3 "mve_imm_8" "Rb")]
5724 VRSHRNTQ_N))
5725 ]
5726 "TARGET_HAVE_MVE"
5727 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
5728 [(set_attr "type" "mve_move")
5729])
5730
5731;;
5732;; [vshrnbq_n_u, vshrnbq_n_s])
5733;;
5734(define_insn "mve_vshrnbq_n_<supf><mode>"
5735 [
5736 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5737 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5738 (match_operand:MVE_5 2 "s_register_operand" "w")
5739 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5740 VSHRNBQ_N))
5741 ]
5742 "TARGET_HAVE_MVE"
5743 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5744 [(set_attr "type" "mve_move")
5745])
5746
5747;;
5748;; [vshrntq_n_s, vshrntq_n_u])
5749;;
5750(define_insn "mve_vshrntq_n_<supf><mode>"
5751 [
5752 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5753 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5754 (match_operand:MVE_5 2 "s_register_operand" "w")
5755 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5756 VSHRNTQ_N))
5757 ]
5758 "TARGET_HAVE_MVE"
db5db9d2 5759 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5760 [(set_attr "type" "mve_move")
5761])
5762
5763;;
5764;; [vcvtmq_m_s, vcvtmq_m_u])
5765;;
5766(define_insn "mve_vcvtmq_m_<supf><mode>"
5767 [
5768 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5769 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5770 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5771 (match_operand:HI 3 "vpr_register_operand" "Up")]
5772 VCVTMQ_M))
5773 ]
5774 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5775 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5776 [(set_attr "type" "mve_move")
5777 (set_attr "length""8")])
5778
5779;;
5780;; [vcvtpq_m_u, vcvtpq_m_s])
5781;;
5782(define_insn "mve_vcvtpq_m_<supf><mode>"
5783 [
5784 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5785 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5786 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5787 (match_operand:HI 3 "vpr_register_operand" "Up")]
5788 VCVTPQ_M))
5789 ]
5790 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5791 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5792 [(set_attr "type" "mve_move")
5793 (set_attr "length""8")])
5794
5795;;
5796;; [vcvtnq_m_s, vcvtnq_m_u])
5797;;
5798(define_insn "mve_vcvtnq_m_<supf><mode>"
5799 [
5800 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5801 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5802 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5803 (match_operand:HI 3 "vpr_register_operand" "Up")]
5804 VCVTNQ_M))
5805 ]
5806 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5807 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5808 [(set_attr "type" "mve_move")
5809 (set_attr "length""8")])
5810
5811;;
5812;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5813;;
5814(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5815 [
5816 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5817 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5818 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5819 (match_operand:SI 3 "mve_imm_16" "Rd")
5820 (match_operand:HI 4 "vpr_register_operand" "Up")]
5821 VCVTQ_M_N_FROM_F))
5822 ]
5823 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5824 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5825 [(set_attr "type" "mve_move")
5826 (set_attr "length""8")])
5827
5828;;
5829;; [vrev16q_m_u, vrev16q_m_s])
5830;;
5831(define_insn "mve_vrev16q_m_<supf>v16qi"
5832 [
5833 (set (match_operand:V16QI 0 "s_register_operand" "=w")
5834 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5835 (match_operand:V16QI 2 "s_register_operand" "w")
5836 (match_operand:HI 3 "vpr_register_operand" "Up")]
5837 VREV16Q_M))
5838 ]
5839 "TARGET_HAVE_MVE"
5840 "vpst\;vrev16t.8 %q0, %q2"
5841 [(set_attr "type" "mve_move")
5842 (set_attr "length""8")])
5843
5844;;
5845;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5846;;
5847(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5848 [
5849 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5850 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5851 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5852 (match_operand:HI 3 "vpr_register_operand" "Up")]
5853 VCVTQ_M_FROM_F))
5854 ]
5855 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5856 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5857 [(set_attr "type" "mve_move")
5858 (set_attr "length""8")])
5859
5860;;
5861;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5862;;
5863(define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5864 [
5865 (set (match_operand:DI 0 "s_register_operand" "=r")
5866 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5867 (match_operand:V4SI 2 "s_register_operand" "w")
5868 (match_operand:HI 3 "vpr_register_operand" "Up")]
5869 VRMLALDAVHQ_P))
5870 ]
5871 "TARGET_HAVE_MVE"
5872 "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5873 [(set_attr "type" "mve_move")
5874 (set_attr "length""8")])
5875
5876;;
5877;; [vrmlsldavhaq_s])
5878;;
5879(define_insn "mve_vrmlsldavhaq_sv4si"
5880 [
5881 (set (match_operand:DI 0 "s_register_operand" "=r")
5882 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5883 (match_operand:V4SI 2 "s_register_operand" "w")
5884 (match_operand:V4SI 3 "s_register_operand" "w")]
5885 VRMLSLDAVHAQ_S))
5886 ]
5887 "TARGET_HAVE_MVE"
5888 "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5889 [(set_attr "type" "mve_move")
5890])
db5db9d2
SP		 5891
5892;;
5893;; [vabavq_p_s, vabavq_p_u])
5894;;
5895(define_insn "mve_vabavq_p_<supf><mode>"
5896 [
5897 (set (match_operand:SI 0 "s_register_operand" "=r")
5898 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5899 (match_operand:MVE_2 2 "s_register_operand" "w")
5900 (match_operand:MVE_2 3 "s_register_operand" "w")
5901 (match_operand:HI 4 "vpr_register_operand" "Up")]
5902 VABAVQ_P))
5903 ]
5904 "TARGET_HAVE_MVE"
5905 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5906 [(set_attr "type" "mve_move")
5907])
5908
5909;;
5910;; [vqshluq_m_n_s])
5911;;
5912(define_insn "mve_vqshluq_m_n_s<mode>"
5913 [
5914 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5915 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5916 (match_operand:MVE_2 2 "s_register_operand" "w")
5917 (match_operand:SI 3 "mve_imm_7" "Ra")
5918 (match_operand:HI 4 "vpr_register_operand" "Up")]
5919 VQSHLUQ_M_N_S))
5920 ]
5921 "TARGET_HAVE_MVE"
5922 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5923 [(set_attr "type" "mve_move")])
5924
5925;;
5926;; [vshlq_m_s, vshlq_m_u])
5927;;
5928(define_insn "mve_vshlq_m_<supf><mode>"
5929 [
5930 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5931 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5932 (match_operand:MVE_2 2 "s_register_operand" "w")
5933 (match_operand:MVE_2 3 "s_register_operand" "w")
5934 (match_operand:HI 4 "vpr_register_operand" "Up")]
5935 VSHLQ_M))
5936 ]
5937 "TARGET_HAVE_MVE"
5938 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5939 [(set_attr "type" "mve_move")])
5940
5941;;
5942;; [vsriq_m_n_s, vsriq_m_n_u])
5943;;
5944(define_insn "mve_vsriq_m_n_<supf><mode>"
5945 [
5946 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5947 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5948 (match_operand:MVE_2 2 "s_register_operand" "w")
5949 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
5950 (match_operand:HI 4 "vpr_register_operand" "Up")]
5951 VSRIQ_M_N))
5952 ]
5953 "TARGET_HAVE_MVE"
5954 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
5955 [(set_attr "type" "mve_move")])
5956
5957;;
5958;; [vsubq_m_u, vsubq_m_s])
5959;;
5960(define_insn "mve_vsubq_m_<supf><mode>"
5961 [
5962 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5963 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5964 (match_operand:MVE_2 2 "s_register_operand" "w")
5965 (match_operand:MVE_2 3 "s_register_operand" "w")
5966 (match_operand:HI 4 "vpr_register_operand" "Up")]
5967 VSUBQ_M))
5968 ]
5969 "TARGET_HAVE_MVE"
5970 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
5971 [(set_attr "type" "mve_move")])
5972
5973;;
5974;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
5975;;
5976(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
5977 [
5978 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5979 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5980 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5981 (match_operand:SI 3 "mve_imm_16" "Rd")
5982 (match_operand:HI 4 "vpr_register_operand" "Up")]
5983 VCVTQ_M_N_TO_F))
5984 ]
5985 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5986 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5987 [(set_attr "type" "mve_move")
5988 (set_attr "length""8")])
8eb3b6b9
SP		 5989;;
5990;; [vabdq_m_s, vabdq_m_u])
5991;;
5992(define_insn "mve_vabdq_m_<supf><mode>"
5993 [
5994 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5995 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5996 (match_operand:MVE_2 2 "s_register_operand" "w")
5997 (match_operand:MVE_2 3 "s_register_operand" "w")
5998 (match_operand:HI 4 "vpr_register_operand" "Up")]
5999 VABDQ_M))
6000 ]
6001 "TARGET_HAVE_MVE"
6002 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6003 [(set_attr "type" "mve_move")
6004 (set_attr "length""8")])
6005
6006;;
6007;; [vaddq_m_n_s, vaddq_m_n_u])
6008;;
6009(define_insn "mve_vaddq_m_n_<supf><mode>"
6010 [
6011 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6012 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6013 (match_operand:MVE_2 2 "s_register_operand" "w")
6014 (match_operand:<V_elem> 3 "s_register_operand" "r")
6015 (match_operand:HI 4 "vpr_register_operand" "Up")]
6016 VADDQ_M_N))
6017 ]
6018 "TARGET_HAVE_MVE"
6019 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
6020 [(set_attr "type" "mve_move")
6021 (set_attr "length""8")])
6022
6023;;
6024;; [vaddq_m_u, vaddq_m_s])
6025;;
6026(define_insn "mve_vaddq_m_<supf><mode>"
6027 [
6028 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6029 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6030 (match_operand:MVE_2 2 "s_register_operand" "w")
6031 (match_operand:MVE_2 3 "s_register_operand" "w")
6032 (match_operand:HI 4 "vpr_register_operand" "Up")]
6033 VADDQ_M))
6034 ]
6035 "TARGET_HAVE_MVE"
6036 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
6037 [(set_attr "type" "mve_move")
6038 (set_attr "length""8")])
6039
6040;;
6041;; [vandq_m_u, vandq_m_s])
6042;;
6043(define_insn "mve_vandq_m_<supf><mode>"
6044 [
6045 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6046 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6047 (match_operand:MVE_2 2 "s_register_operand" "w")
6048 (match_operand:MVE_2 3 "s_register_operand" "w")
6049 (match_operand:HI 4 "vpr_register_operand" "Up")]
6050 VANDQ_M))
6051 ]
6052 "TARGET_HAVE_MVE"
6053 "vpst\;vandt %q0, %q2, %q3"
6054 [(set_attr "type" "mve_move")
6055 (set_attr "length""8")])
6056
6057;;
6058;; [vbicq_m_u, vbicq_m_s])
6059;;
6060(define_insn "mve_vbicq_m_<supf><mode>"
6061 [
6062 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6063 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6064 (match_operand:MVE_2 2 "s_register_operand" "w")
6065 (match_operand:MVE_2 3 "s_register_operand" "w")
6066 (match_operand:HI 4 "vpr_register_operand" "Up")]
6067 VBICQ_M))
6068 ]
6069 "TARGET_HAVE_MVE"
6070 "vpst\;vbict %q0, %q2, %q3"
6071 [(set_attr "type" "mve_move")
6072 (set_attr "length""8")])
6073
6074;;
6075;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
6076;;
6077(define_insn "mve_vbrsrq_m_n_<supf><mode>"
6078 [
6079 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6080 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6081 (match_operand:MVE_2 2 "s_register_operand" "w")
6082 (match_operand:SI 3 "s_register_operand" "r")
6083 (match_operand:HI 4 "vpr_register_operand" "Up")]
6084 VBRSRQ_M_N))
6085 ]
6086 "TARGET_HAVE_MVE"
6087 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
6088 [(set_attr "type" "mve_move")
6089 (set_attr "length""8")])
6090
6091;;
6092;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
6093;;
6094(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
6095 [
6096 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6097 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6098 (match_operand:MVE_2 2 "s_register_operand" "w")
6099 (match_operand:MVE_2 3 "s_register_operand" "w")
6100 (match_operand:HI 4 "vpr_register_operand" "Up")]
6101 VCADDQ_ROT270_M))
6102 ]
6103 "TARGET_HAVE_MVE"
6104 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
6105 [(set_attr "type" "mve_move")
6106 (set_attr "length""8")])
6107
6108;;
6109;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
6110;;
6111(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
6112 [
6113 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6114 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6115 (match_operand:MVE_2 2 "s_register_operand" "w")
6116 (match_operand:MVE_2 3 "s_register_operand" "w")
6117 (match_operand:HI 4 "vpr_register_operand" "Up")]
6118 VCADDQ_ROT90_M))
6119 ]
6120 "TARGET_HAVE_MVE"
6121 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
6122 [(set_attr "type" "mve_move")
6123 (set_attr "length""8")])
6124
6125;;
6126;; [veorq_m_s, veorq_m_u])
6127;;
6128(define_insn "mve_veorq_m_<supf><mode>"
6129 [
6130 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6131 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6132 (match_operand:MVE_2 2 "s_register_operand" "w")
6133 (match_operand:MVE_2 3 "s_register_operand" "w")
6134 (match_operand:HI 4 "vpr_register_operand" "Up")]
6135 VEORQ_M))
6136 ]
6137 "TARGET_HAVE_MVE"
6138 "vpst\;veort %q0, %q2, %q3"
6139 [(set_attr "type" "mve_move")
6140 (set_attr "length""8")])
6141
6142;;
6143;; [vhaddq_m_n_s, vhaddq_m_n_u])
6144;;
6145(define_insn "mve_vhaddq_m_n_<supf><mode>"
6146 [
6147 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6148 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6149 (match_operand:MVE_2 2 "s_register_operand" "w")
6150 (match_operand:<V_elem> 3 "s_register_operand" "r")
6151 (match_operand:HI 4 "vpr_register_operand" "Up")]
6152 VHADDQ_M_N))
6153 ]
6154 "TARGET_HAVE_MVE"
6155 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6156 [(set_attr "type" "mve_move")
6157 (set_attr "length""8")])
6158
6159;;
6160;; [vhaddq_m_s, vhaddq_m_u])
6161;;
6162(define_insn "mve_vhaddq_m_<supf><mode>"
6163 [
6164 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6165 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6166 (match_operand:MVE_2 2 "s_register_operand" "w")
6167 (match_operand:MVE_2 3 "s_register_operand" "w")
6168 (match_operand:HI 4 "vpr_register_operand" "Up")]
6169 VHADDQ_M))
6170 ]
6171 "TARGET_HAVE_MVE"
6172 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6173 [(set_attr "type" "mve_move")
6174 (set_attr "length""8")])
6175
6176;;
6177;; [vhsubq_m_n_s, vhsubq_m_n_u])
6178;;
6179(define_insn "mve_vhsubq_m_n_<supf><mode>"
6180 [
6181 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6182 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6183 (match_operand:MVE_2 2 "s_register_operand" "w")
6184 (match_operand:<V_elem> 3 "s_register_operand" "r")
6185 (match_operand:HI 4 "vpr_register_operand" "Up")]
6186 VHSUBQ_M_N))
6187 ]
6188 "TARGET_HAVE_MVE"
6189 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6190 [(set_attr "type" "mve_move")
6191 (set_attr "length""8")])
6192
6193;;
6194;; [vhsubq_m_s, vhsubq_m_u])
6195;;
6196(define_insn "mve_vhsubq_m_<supf><mode>"
6197 [
6198 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6199 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6200 (match_operand:MVE_2 2 "s_register_operand" "w")
6201 (match_operand:MVE_2 3 "s_register_operand" "w")
6202 (match_operand:HI 4 "vpr_register_operand" "Up")]
6203 VHSUBQ_M))
6204 ]
6205 "TARGET_HAVE_MVE"
6206 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6207 [(set_attr "type" "mve_move")
6208 (set_attr "length""8")])
6209
6210;;
6211;; [vmaxq_m_s, vmaxq_m_u])
6212;;
6213(define_insn "mve_vmaxq_m_<supf><mode>"
6214 [
6215 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6216 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6217 (match_operand:MVE_2 2 "s_register_operand" "w")
6218 (match_operand:MVE_2 3 "s_register_operand" "w")
6219 (match_operand:HI 4 "vpr_register_operand" "Up")]
6220 VMAXQ_M))
6221 ]
6222 "TARGET_HAVE_MVE"
6223 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6224 [(set_attr "type" "mve_move")
6225 (set_attr "length""8")])
6226
6227;;
6228;; [vminq_m_s, vminq_m_u])
6229;;
6230(define_insn "mve_vminq_m_<supf><mode>"
6231 [
6232 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6233 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6234 (match_operand:MVE_2 2 "s_register_operand" "w")
6235 (match_operand:MVE_2 3 "s_register_operand" "w")
6236 (match_operand:HI 4 "vpr_register_operand" "Up")]
6237 VMINQ_M))
6238 ]
6239 "TARGET_HAVE_MVE"
6240 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6241 [(set_attr "type" "mve_move")
6242 (set_attr "length""8")])
6243
6244;;
6245;; [vmladavaq_p_u, vmladavaq_p_s])
6246;;
6247(define_insn "mve_vmladavaq_p_<supf><mode>"
6248 [
6249 (set (match_operand:SI 0 "s_register_operand" "=e")
6250 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6251 (match_operand:MVE_2 2 "s_register_operand" "w")
6252 (match_operand:MVE_2 3 "s_register_operand" "w")
6253 (match_operand:HI 4 "vpr_register_operand" "Up")]
6254 VMLADAVAQ_P))
6255 ]
6256 "TARGET_HAVE_MVE"
6257 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
6258 [(set_attr "type" "mve_move")
6259 (set_attr "length""8")])
6260
6261;;
6262;; [vmlaq_m_n_s, vmlaq_m_n_u])
6263;;
6264(define_insn "mve_vmlaq_m_n_<supf><mode>"
6265 [
6266 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6267 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6268 (match_operand:MVE_2 2 "s_register_operand" "w")
6269 (match_operand:<V_elem> 3 "s_register_operand" "r")
6270 (match_operand:HI 4 "vpr_register_operand" "Up")]
6271 VMLAQ_M_N))
6272 ]
6273 "TARGET_HAVE_MVE"
6274 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
6275 [(set_attr "type" "mve_move")
6276 (set_attr "length""8")])
6277
6278;;
6279;; [vmlasq_m_n_u, vmlasq_m_n_s])
6280;;
6281(define_insn "mve_vmlasq_m_n_<supf><mode>"
6282 [
6283 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6284 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6285 (match_operand:MVE_2 2 "s_register_operand" "w")
6286 (match_operand:<V_elem> 3 "s_register_operand" "r")
6287 (match_operand:HI 4 "vpr_register_operand" "Up")]
6288 VMLASQ_M_N))
6289 ]
6290 "TARGET_HAVE_MVE"
6291 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
6292 [(set_attr "type" "mve_move")
6293 (set_attr "length""8")])
6294
6295;;
6296;; [vmulhq_m_s, vmulhq_m_u])
6297;;
6298(define_insn "mve_vmulhq_m_<supf><mode>"
6299 [
6300 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6301 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6302 (match_operand:MVE_2 2 "s_register_operand" "w")
6303 (match_operand:MVE_2 3 "s_register_operand" "w")
6304 (match_operand:HI 4 "vpr_register_operand" "Up")]
6305 VMULHQ_M))
6306 ]
6307 "TARGET_HAVE_MVE"
6308 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6309 [(set_attr "type" "mve_move")
6310 (set_attr "length""8")])
6311
6312;;
6313;; [vmullbq_int_m_u, vmullbq_int_m_s])
6314;;
6315(define_insn "mve_vmullbq_int_m_<supf><mode>"
6316 [
6317 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6318 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6319 (match_operand:MVE_2 2 "s_register_operand" "w")
6320 (match_operand:MVE_2 3 "s_register_operand" "w")
6321 (match_operand:HI 4 "vpr_register_operand" "Up")]
6322 VMULLBQ_INT_M))
6323 ]
6324 "TARGET_HAVE_MVE"
6325 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6326 [(set_attr "type" "mve_move")
6327 (set_attr "length""8")])
6328
6329;;
6330;; [vmulltq_int_m_s, vmulltq_int_m_u])
6331;;
6332(define_insn "mve_vmulltq_int_m_<supf><mode>"
6333 [
6334 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6335 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6336 (match_operand:MVE_2 2 "s_register_operand" "w")
6337 (match_operand:MVE_2 3 "s_register_operand" "w")
6338 (match_operand:HI 4 "vpr_register_operand" "Up")]
6339 VMULLTQ_INT_M))
6340 ]
6341 "TARGET_HAVE_MVE"
6342 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6343 [(set_attr "type" "mve_move")
6344 (set_attr "length""8")])
6345
6346;;
6347;; [vmulq_m_n_u, vmulq_m_n_s])
6348;;
6349(define_insn "mve_vmulq_m_n_<supf><mode>"
6350 [
6351 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6352 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6353 (match_operand:MVE_2 2 "s_register_operand" "w")
6354 (match_operand:<V_elem> 3 "s_register_operand" "r")
6355 (match_operand:HI 4 "vpr_register_operand" "Up")]
6356 VMULQ_M_N))
6357 ]
6358 "TARGET_HAVE_MVE"
6359 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
6360 [(set_attr "type" "mve_move")
6361 (set_attr "length""8")])
6362
6363;;
6364;; [vmulq_m_s, vmulq_m_u])
6365;;
6366(define_insn "mve_vmulq_m_<supf><mode>"
6367 [
6368 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6369 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6370 (match_operand:MVE_2 2 "s_register_operand" "w")
6371 (match_operand:MVE_2 3 "s_register_operand" "w")
6372 (match_operand:HI 4 "vpr_register_operand" "Up")]
6373 VMULQ_M))
6374 ]
6375 "TARGET_HAVE_MVE"
6376 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
6377 [(set_attr "type" "mve_move")
6378 (set_attr "length""8")])
6379
6380;;
6381;; [vornq_m_u, vornq_m_s])
6382;;
6383(define_insn "mve_vornq_m_<supf><mode>"
6384 [
6385 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6386 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6387 (match_operand:MVE_2 2 "s_register_operand" "w")
6388 (match_operand:MVE_2 3 "s_register_operand" "w")
6389 (match_operand:HI 4 "vpr_register_operand" "Up")]
6390 VORNQ_M))
6391 ]
6392 "TARGET_HAVE_MVE"
6393 "vpst\;vornt %q0, %q2, %q3"
6394 [(set_attr "type" "mve_move")
6395 (set_attr "length""8")])
6396
6397;;
6398;; [vorrq_m_s, vorrq_m_u])
6399;;
6400(define_insn "mve_vorrq_m_<supf><mode>"
6401 [
6402 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6403 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6404 (match_operand:MVE_2 2 "s_register_operand" "w")
6405 (match_operand:MVE_2 3 "s_register_operand" "w")
6406 (match_operand:HI 4 "vpr_register_operand" "Up")]
6407 VORRQ_M))
6408 ]
6409 "TARGET_HAVE_MVE"
6410 "vpst\;vorrt %q0, %q2, %q3"
6411 [(set_attr "type" "mve_move")
6412 (set_attr "length""8")])
6413
6414;;
6415;; [vqaddq_m_n_u, vqaddq_m_n_s])
6416;;
6417(define_insn "mve_vqaddq_m_n_<supf><mode>"
6418 [
6419 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6420 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6421 (match_operand:MVE_2 2 "s_register_operand" "w")
6422 (match_operand:<V_elem> 3 "s_register_operand" "r")
6423 (match_operand:HI 4 "vpr_register_operand" "Up")]
6424 VQADDQ_M_N))
6425 ]
6426 "TARGET_HAVE_MVE"
6427 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6428 [(set_attr "type" "mve_move")
6429 (set_attr "length""8")])
6430
6431;;
6432;; [vqaddq_m_u, vqaddq_m_s])
6433;;
6434(define_insn "mve_vqaddq_m_<supf><mode>"
6435 [
6436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6437 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6438 (match_operand:MVE_2 2 "s_register_operand" "w")
6439 (match_operand:MVE_2 3 "s_register_operand" "w")
6440 (match_operand:HI 4 "vpr_register_operand" "Up")]
6441 VQADDQ_M))
6442 ]
6443 "TARGET_HAVE_MVE"
6444 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6445 [(set_attr "type" "mve_move")
6446 (set_attr "length""8")])
6447
6448;;
6449;; [vqdmlahq_m_n_s])
6450;;
6451(define_insn "mve_vqdmlahq_m_n_s<mode>"
6452 [
6453 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6454 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6455 (match_operand:MVE_2 2 "s_register_operand" "w")
6456 (match_operand:<V_elem> 3 "s_register_operand" "r")
6457 (match_operand:HI 4 "vpr_register_operand" "Up")]
6458 VQDMLAHQ_M_N_S))
6459 ]
6460 "TARGET_HAVE_MVE"
6461 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6462 [(set_attr "type" "mve_move")
6463 (set_attr "length""8")])
6464
6465;;
6466;; [vqrdmlahq_m_n_s])
6467;;
6468(define_insn "mve_vqrdmlahq_m_n_s<mode>"
6469 [
6470 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6471 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6472 (match_operand:MVE_2 2 "s_register_operand" "w")
6473 (match_operand:<V_elem> 3 "s_register_operand" "r")
6474 (match_operand:HI 4 "vpr_register_operand" "Up")]
6475 VQRDMLAHQ_M_N_S))
6476 ]
6477 "TARGET_HAVE_MVE"
6478 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6479 [(set_attr "type" "mve_move")
6480 (set_attr "length""8")])
6481
6482;;
6483;; [vqrdmlashq_m_n_s])
6484;;
6485(define_insn "mve_vqrdmlashq_m_n_s<mode>"
6486 [
6487 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6488 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6489 (match_operand:MVE_2 2 "s_register_operand" "w")
6490 (match_operand:<V_elem> 3 "s_register_operand" "r")
6491 (match_operand:HI 4 "vpr_register_operand" "Up")]
6492 VQRDMLASHQ_M_N_S))
6493 ]
6494 "TARGET_HAVE_MVE"
6495 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6496 [(set_attr "type" "mve_move")
6497 (set_attr "length""8")])
6498
6499;;
6500;; [vqrshlq_m_u, vqrshlq_m_s])
6501;;
6502(define_insn "mve_vqrshlq_m_<supf><mode>"
6503 [
6504 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6505 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6506 (match_operand:MVE_2 2 "s_register_operand" "w")
6507 (match_operand:MVE_2 3 "s_register_operand" "w")
6508 (match_operand:HI 4 "vpr_register_operand" "Up")]
6509 VQRSHLQ_M))
6510 ]
6511 "TARGET_HAVE_MVE"
6512 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6513 [(set_attr "type" "mve_move")
6514 (set_attr "length""8")])
6515
6516;;
6517;; [vqshlq_m_n_s, vqshlq_m_n_u])
6518;;
6519(define_insn "mve_vqshlq_m_n_<supf><mode>"
6520 [
6521 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6522 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6523 (match_operand:MVE_2 2 "s_register_operand" "w")
6524 (match_operand:SI 3 "immediate_operand" "i")
6525 (match_operand:HI 4 "vpr_register_operand" "Up")]
6526 VQSHLQ_M_N))
6527 ]
6528 "TARGET_HAVE_MVE"
6529 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6530 [(set_attr "type" "mve_move")
6531 (set_attr "length""8")])
6532
6533;;
6534;; [vqshlq_m_u, vqshlq_m_s])
6535;;
6536(define_insn "mve_vqshlq_m_<supf><mode>"
6537 [
6538 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6539 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6540 (match_operand:MVE_2 2 "s_register_operand" "w")
6541 (match_operand:MVE_2 3 "s_register_operand" "w")
6542 (match_operand:HI 4 "vpr_register_operand" "Up")]
6543 VQSHLQ_M))
6544 ]
6545 "TARGET_HAVE_MVE"
6546 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6547 [(set_attr "type" "mve_move")
6548 (set_attr "length""8")])
6549
6550;;
6551;; [vqsubq_m_n_u, vqsubq_m_n_s])
6552;;
6553(define_insn "mve_vqsubq_m_n_<supf><mode>"
6554 [
6555 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6556 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6557 (match_operand:MVE_2 2 "s_register_operand" "w")
6558 (match_operand:<V_elem> 3 "s_register_operand" "r")
6559 (match_operand:HI 4 "vpr_register_operand" "Up")]
6560 VQSUBQ_M_N))
6561 ]
6562 "TARGET_HAVE_MVE"
6563 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6564 [(set_attr "type" "mve_move")
6565 (set_attr "length""8")])
6566
6567;;
6568;; [vqsubq_m_u, vqsubq_m_s])
6569;;
6570(define_insn "mve_vqsubq_m_<supf><mode>"
6571 [
6572 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6573 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6574 (match_operand:MVE_2 2 "s_register_operand" "w")
6575 (match_operand:MVE_2 3 "s_register_operand" "w")
6576 (match_operand:HI 4 "vpr_register_operand" "Up")]
6577 VQSUBQ_M))
6578 ]
6579 "TARGET_HAVE_MVE"
6580 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6581 [(set_attr "type" "mve_move")
6582 (set_attr "length""8")])
6583
6584;;
6585;; [vrhaddq_m_u, vrhaddq_m_s])
6586;;
6587(define_insn "mve_vrhaddq_m_<supf><mode>"
6588 [
6589 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6590 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6591 (match_operand:MVE_2 2 "s_register_operand" "w")
6592 (match_operand:MVE_2 3 "s_register_operand" "w")
6593 (match_operand:HI 4 "vpr_register_operand" "Up")]
6594 VRHADDQ_M))
6595 ]
6596 "TARGET_HAVE_MVE"
6597 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6598 [(set_attr "type" "mve_move")
6599 (set_attr "length""8")])
6600
6601;;
6602;; [vrmulhq_m_u, vrmulhq_m_s])
6603;;
6604(define_insn "mve_vrmulhq_m_<supf><mode>"
6605 [
6606 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6607 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6608 (match_operand:MVE_2 2 "s_register_operand" "w")
6609 (match_operand:MVE_2 3 "s_register_operand" "w")
6610 (match_operand:HI 4 "vpr_register_operand" "Up")]
6611 VRMULHQ_M))
6612 ]
6613 "TARGET_HAVE_MVE"
6614 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6615 [(set_attr "type" "mve_move")
6616 (set_attr "length""8")])
6617
6618;;
6619;; [vrshlq_m_s, vrshlq_m_u])
6620;;
6621(define_insn "mve_vrshlq_m_<supf><mode>"
6622 [
6623 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6624 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6625 (match_operand:MVE_2 2 "s_register_operand" "w")
6626 (match_operand:MVE_2 3 "s_register_operand" "w")
6627 (match_operand:HI 4 "vpr_register_operand" "Up")]
6628 VRSHLQ_M))
6629 ]
6630 "TARGET_HAVE_MVE"
6631 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6632 [(set_attr "type" "mve_move")
6633 (set_attr "length""8")])
6634
6635;;
6636;; [vrshrq_m_n_s, vrshrq_m_n_u])
6637;;
6638(define_insn "mve_vrshrq_m_n_<supf><mode>"
6639 [
6640 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6641 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6642 (match_operand:MVE_2 2 "s_register_operand" "w")
6643 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6644 (match_operand:HI 4 "vpr_register_operand" "Up")]
6645 VRSHRQ_M_N))
6646 ]
6647 "TARGET_HAVE_MVE"
6648 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6649 [(set_attr "type" "mve_move")
6650 (set_attr "length""8")])
6651
6652;;
6653;; [vshlq_m_n_s, vshlq_m_n_u])
6654;;
6655(define_insn "mve_vshlq_m_n_<supf><mode>"
6656 [
6657 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6658 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6659 (match_operand:MVE_2 2 "s_register_operand" "w")
6660 (match_operand:SI 3 "immediate_operand" "i")
6661 (match_operand:HI 4 "vpr_register_operand" "Up")]
6662 VSHLQ_M_N))
6663 ]
6664 "TARGET_HAVE_MVE"
6665 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6666 [(set_attr "type" "mve_move")
6667 (set_attr "length""8")])
6668
6669;;
6670;; [vshrq_m_n_s, vshrq_m_n_u])
6671;;
6672(define_insn "mve_vshrq_m_n_<supf><mode>"
6673 [
6674 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6675 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6676 (match_operand:MVE_2 2 "s_register_operand" "w")
6677 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6678 (match_operand:HI 4 "vpr_register_operand" "Up")]
6679 VSHRQ_M_N))
6680 ]
6681 "TARGET_HAVE_MVE"
6682 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6683 [(set_attr "type" "mve_move")
6684 (set_attr "length""8")])
6685
6686;;
6687;; [vsliq_m_n_u, vsliq_m_n_s])
6688;;
6689(define_insn "mve_vsliq_m_n_<supf><mode>"
6690 [
6691 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6692 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6693 (match_operand:MVE_2 2 "s_register_operand" "w")
6694 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
6695 (match_operand:HI 4 "vpr_register_operand" "Up")]
6696 VSLIQ_M_N))
6697 ]
6698 "TARGET_HAVE_MVE"
6699 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
6700 [(set_attr "type" "mve_move")
6701 (set_attr "length""8")])
6702
6703;;
6704;; [vsubq_m_n_s, vsubq_m_n_u])
6705;;
6706(define_insn "mve_vsubq_m_n_<supf><mode>"
6707 [
6708 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6709 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6710 (match_operand:MVE_2 2 "s_register_operand" "w")
6711 (match_operand:<V_elem> 3 "s_register_operand" "r")
6712 (match_operand:HI 4 "vpr_register_operand" "Up")]
6713 VSUBQ_M_N))
6714 ]
6715 "TARGET_HAVE_MVE"
6716 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
6717 [(set_attr "type" "mve_move")
6718 (set_attr "length""8")])
6719
6720;;
6721;; [vhcaddq_rot270_m_s])
6722;;
6723(define_insn "mve_vhcaddq_rot270_m_s<mode>"
6724 [
6725 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6726 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6727 (match_operand:MVE_2 2 "s_register_operand" "w")
6728 (match_operand:MVE_2 3 "s_register_operand" "w")
6729 (match_operand:HI 4 "vpr_register_operand" "Up")]
6730 VHCADDQ_ROT270_M_S))
6731 ]
6732 "TARGET_HAVE_MVE"
6733 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
6734 [(set_attr "type" "mve_move")
6735 (set_attr "length""8")])
6736
6737;;
6738;; [vhcaddq_rot90_m_s])
6739;;
6740(define_insn "mve_vhcaddq_rot90_m_s<mode>"
6741 [
6742 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6743 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6744 (match_operand:MVE_2 2 "s_register_operand" "w")
6745 (match_operand:MVE_2 3 "s_register_operand" "w")
6746 (match_operand:HI 4 "vpr_register_operand" "Up")]
6747 VHCADDQ_ROT90_M_S))
6748 ]
6749 "TARGET_HAVE_MVE"
6750 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
6751 [(set_attr "type" "mve_move")
6752 (set_attr "length""8")])
6753
6754;;
6755;; [vmladavaxq_p_s])
6756;;
6757(define_insn "mve_vmladavaxq_p_s<mode>"
6758 [
6759 (set (match_operand:SI 0 "s_register_operand" "=e")
6760 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6761 (match_operand:MVE_2 2 "s_register_operand" "w")
6762 (match_operand:MVE_2 3 "s_register_operand" "w")
6763 (match_operand:HI 4 "vpr_register_operand" "Up")]
6764 VMLADAVAXQ_P_S))
6765 ]
6766 "TARGET_HAVE_MVE"
6767 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6768 [(set_attr "type" "mve_move")
6769 (set_attr "length""8")])
6770
6771;;
6772;; [vmlsdavaq_p_s])
6773;;
6774(define_insn "mve_vmlsdavaq_p_s<mode>"
6775 [
6776 (set (match_operand:SI 0 "s_register_operand" "=e")
6777 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6778 (match_operand:MVE_2 2 "s_register_operand" "w")
6779 (match_operand:MVE_2 3 "s_register_operand" "w")
6780 (match_operand:HI 4 "vpr_register_operand" "Up")]
6781 VMLSDAVAQ_P_S))
6782 ]
6783 "TARGET_HAVE_MVE"
6784 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
6785 [(set_attr "type" "mve_move")
6786 (set_attr "length""8")])
6787
6788;;
6789;; [vmlsdavaxq_p_s])
6790;;
6791(define_insn "mve_vmlsdavaxq_p_s<mode>"
6792 [
6793 (set (match_operand:SI 0 "s_register_operand" "=e")
6794 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6795 (match_operand:MVE_2 2 "s_register_operand" "w")
6796 (match_operand:MVE_2 3 "s_register_operand" "w")
6797 (match_operand:HI 4 "vpr_register_operand" "Up")]
6798 VMLSDAVAXQ_P_S))
6799 ]
6800 "TARGET_HAVE_MVE"
6801 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6802 [(set_attr "type" "mve_move")
6803 (set_attr "length""8")])
6804
6805;;
6806;; [vqdmladhq_m_s])
6807;;
6808(define_insn "mve_vqdmladhq_m_s<mode>"
6809 [
6810 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6811 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6812 (match_operand:MVE_2 2 "s_register_operand" "w")
6813 (match_operand:MVE_2 3 "s_register_operand" "w")
6814 (match_operand:HI 4 "vpr_register_operand" "Up")]
6815 VQDMLADHQ_M_S))
6816 ]
6817 "TARGET_HAVE_MVE"
6818 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6819 [(set_attr "type" "mve_move")
6820 (set_attr "length""8")])
6821
6822;;
6823;; [vqdmladhxq_m_s])
6824;;
6825(define_insn "mve_vqdmladhxq_m_s<mode>"
6826 [
6827 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6828 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6829 (match_operand:MVE_2 2 "s_register_operand" "w")
6830 (match_operand:MVE_2 3 "s_register_operand" "w")
6831 (match_operand:HI 4 "vpr_register_operand" "Up")]
6832 VQDMLADHXQ_M_S))
6833 ]
6834 "TARGET_HAVE_MVE"
6835 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6836 [(set_attr "type" "mve_move")
6837 (set_attr "length""8")])
6838
6839;;
6840;; [vqdmlsdhq_m_s])
6841;;
6842(define_insn "mve_vqdmlsdhq_m_s<mode>"
6843 [
6844 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6845 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6846 (match_operand:MVE_2 2 "s_register_operand" "w")
6847 (match_operand:MVE_2 3 "s_register_operand" "w")
6848 (match_operand:HI 4 "vpr_register_operand" "Up")]
6849 VQDMLSDHQ_M_S))
6850 ]
6851 "TARGET_HAVE_MVE"
6852 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6853 [(set_attr "type" "mve_move")
6854 (set_attr "length""8")])
6855
6856;;
6857;; [vqdmlsdhxq_m_s])
6858;;
6859(define_insn "mve_vqdmlsdhxq_m_s<mode>"
6860 [
6861 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6862 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6863 (match_operand:MVE_2 2 "s_register_operand" "w")
6864 (match_operand:MVE_2 3 "s_register_operand" "w")
6865 (match_operand:HI 4 "vpr_register_operand" "Up")]
6866 VQDMLSDHXQ_M_S))
6867 ]
6868 "TARGET_HAVE_MVE"
6869 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6870 [(set_attr "type" "mve_move")
6871 (set_attr "length""8")])
6872
6873;;
6874;; [vqdmulhq_m_n_s])
6875;;
6876(define_insn "mve_vqdmulhq_m_n_s<mode>"
6877 [
6878 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6879 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6880 (match_operand:MVE_2 2 "s_register_operand" "w")
6881 (match_operand:<V_elem> 3 "s_register_operand" "r")
6882 (match_operand:HI 4 "vpr_register_operand" "Up")]
6883 VQDMULHQ_M_N_S))
6884 ]
6885 "TARGET_HAVE_MVE"
6886 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6887 [(set_attr "type" "mve_move")
6888 (set_attr "length""8")])
6889
6890;;
6891;; [vqdmulhq_m_s])
6892;;
6893(define_insn "mve_vqdmulhq_m_s<mode>"
6894 [
6895 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6896 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6897 (match_operand:MVE_2 2 "s_register_operand" "w")
6898 (match_operand:MVE_2 3 "s_register_operand" "w")
6899 (match_operand:HI 4 "vpr_register_operand" "Up")]
6900 VQDMULHQ_M_S))
6901 ]
6902 "TARGET_HAVE_MVE"
6903 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6904 [(set_attr "type" "mve_move")
6905 (set_attr "length""8")])
6906
6907;;
6908;; [vqrdmladhq_m_s])
6909;;
6910(define_insn "mve_vqrdmladhq_m_s<mode>"
6911 [
6912 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6913 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6914 (match_operand:MVE_2 2 "s_register_operand" "w")
6915 (match_operand:MVE_2 3 "s_register_operand" "w")
6916 (match_operand:HI 4 "vpr_register_operand" "Up")]
6917 VQRDMLADHQ_M_S))
6918 ]
6919 "TARGET_HAVE_MVE"
6920 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6921 [(set_attr "type" "mve_move")
6922 (set_attr "length""8")])
6923
6924;;
6925;; [vqrdmladhxq_m_s])
6926;;
6927(define_insn "mve_vqrdmladhxq_m_s<mode>"
6928 [
6929 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6930 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6931 (match_operand:MVE_2 2 "s_register_operand" "w")
6932 (match_operand:MVE_2 3 "s_register_operand" "w")
6933 (match_operand:HI 4 "vpr_register_operand" "Up")]
6934 VQRDMLADHXQ_M_S))
6935 ]
6936 "TARGET_HAVE_MVE"
6937 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6938 [(set_attr "type" "mve_move")
6939 (set_attr "length""8")])
6940
6941;;
6942;; [vqrdmlsdhq_m_s])
6943;;
6944(define_insn "mve_vqrdmlsdhq_m_s<mode>"
6945 [
6946 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6947 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6948 (match_operand:MVE_2 2 "s_register_operand" "w")
6949 (match_operand:MVE_2 3 "s_register_operand" "w")
6950 (match_operand:HI 4 "vpr_register_operand" "Up")]
6951 VQRDMLSDHQ_M_S))
6952 ]
6953 "TARGET_HAVE_MVE"
6954 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6955 [(set_attr "type" "mve_move")
6956 (set_attr "length""8")])
6957
6958;;
6959;; [vqrdmlsdhxq_m_s])
6960;;
6961(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
6962 [
6963 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6964 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6965 (match_operand:MVE_2 2 "s_register_operand" "w")
6966 (match_operand:MVE_2 3 "s_register_operand" "w")
6967 (match_operand:HI 4 "vpr_register_operand" "Up")]
6968 VQRDMLSDHXQ_M_S))
6969 ]
6970 "TARGET_HAVE_MVE"
6971 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6972 [(set_attr "type" "mve_move")
6973 (set_attr "length""8")])
6974
6975;;
6976;; [vqrdmulhq_m_n_s])
6977;;
6978(define_insn "mve_vqrdmulhq_m_n_s<mode>"
6979 [
6980 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6981 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6982 (match_operand:MVE_2 2 "s_register_operand" "w")
6983 (match_operand:<V_elem> 3 "s_register_operand" "r")
6984 (match_operand:HI 4 "vpr_register_operand" "Up")]
6985 VQRDMULHQ_M_N_S))
6986 ]
6987 "TARGET_HAVE_MVE"
6988 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6989 [(set_attr "type" "mve_move")
6990 (set_attr "length""8")])
6991
6992;;
6993;; [vqrdmulhq_m_s])
6994;;
6995(define_insn "mve_vqrdmulhq_m_s<mode>"
6996 [
6997 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6998 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6999 (match_operand:MVE_2 2 "s_register_operand" "w")
7000 (match_operand:MVE_2 3 "s_register_operand" "w")
7001 (match_operand:HI 4 "vpr_register_operand" "Up")]
7002 VQRDMULHQ_M_S))
7003 ]
7004 "TARGET_HAVE_MVE"
7005 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
7006 [(set_attr "type" "mve_move")
7007 (set_attr "length""8")])
7008
f2170a37
SP		 7009;;
7010;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
7011;;
7012(define_insn "mve_vmlaldavaq_p_<supf><mode>"
7013 [
7014 (set (match_operand:DI 0 "s_register_operand" "=r")
7015 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7016 (match_operand:MVE_5 2 "s_register_operand" "w")
7017 (match_operand:MVE_5 3 "s_register_operand" "w")
7018 (match_operand:HI 4 "vpr_register_operand" "Up")]
7019 VMLALDAVAQ_P))
7020 ]
7021 "TARGET_HAVE_MVE"
7022 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7023 [(set_attr "type" "mve_move")
7024 (set_attr "length""8")])
7025
7026;;
7027;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s])
7028;;
7029(define_insn "mve_vmlaldavaxq_p_<supf><mode>"
7030 [
7031 (set (match_operand:DI 0 "s_register_operand" "=r")
7032 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7033 (match_operand:MVE_5 2 "s_register_operand" "w")
7034 (match_operand:MVE_5 3 "s_register_operand" "w")
7035 (match_operand:HI 4 "vpr_register_operand" "Up")]
7036 VMLALDAVAXQ_P))
7037 ]
7038 "TARGET_HAVE_MVE"
7039 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7040 [(set_attr "type" "mve_move")
7041 (set_attr "length""8")])
7042
7043;;
7044;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
7045;;
7046(define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
7047 [
7048 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7049 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7050 (match_operand:MVE_5 2 "s_register_operand" "w")
7051 (match_operand:SI 3 "mve_imm_8" "Rb")
7052 (match_operand:HI 4 "vpr_register_operand" "Up")]
7053 VQRSHRNBQ_M_N))
7054 ]
7055 "TARGET_HAVE_MVE"
7056 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7057 [(set_attr "type" "mve_move")
7058 (set_attr "length""8")])
7059
7060;;
7061;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
7062;;
7063(define_insn "mve_vqrshrntq_m_n_<supf><mode>"
7064 [
7065 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7066 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7067 (match_operand:MVE_5 2 "s_register_operand" "w")
7068 (match_operand:SI 3 "mve_imm_8" "Rb")
7069 (match_operand:HI 4 "vpr_register_operand" "Up")]
7070 VQRSHRNTQ_M_N))
7071 ]
7072 "TARGET_HAVE_MVE"
7073 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7074 [(set_attr "type" "mve_move")
7075 (set_attr "length""8")])
7076
7077;;
7078;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
7079;;
7080(define_insn "mve_vqshrnbq_m_n_<supf><mode>"
7081 [
7082 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7083 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7084 (match_operand:MVE_5 2 "s_register_operand" "w")
7085 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")
7086 (match_operand:HI 4 "vpr_register_operand" "Up")]
7087 VQSHRNBQ_M_N))
7088 ]
7089 "TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], <MODE>mode, 0)"
7090 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7091 [(set_attr "type" "mve_move")
7092 (set_attr "length""8")])
7093
7094;;
7095;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
7096;;
7097(define_insn "mve_vqshrntq_m_n_<supf><mode>"
7098 [
7099 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7100 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7101 (match_operand:MVE_5 2 "s_register_operand" "w")
7102 (match_operand:SI 3 "mve_imm_8" "Rb")
7103 (match_operand:HI 4 "vpr_register_operand" "Up")]
7104 VQSHRNTQ_M_N))
7105 ]
7106 "TARGET_HAVE_MVE"
7107 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7108 [(set_attr "type" "mve_move")
7109 (set_attr "length""8")])
7110
7111;;
7112;; [vrmlaldavhaq_p_s])
7113;;
7114(define_insn "mve_vrmlaldavhaq_p_sv4si"
7115 [
7116 (set (match_operand:DI 0 "s_register_operand" "=r")
7117 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7118 (match_operand:V4SI 2 "s_register_operand" "w")
7119 (match_operand:V4SI 3 "s_register_operand" "w")
7120 (match_operand:HI 4 "vpr_register_operand" "Up")]
7121 VRMLALDAVHAQ_P_S))
7122 ]
7123 "TARGET_HAVE_MVE"
7124 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
7125 [(set_attr "type" "mve_move")
7126 (set_attr "length""8")])
7127
7128;;
7129;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
7130;;
7131(define_insn "mve_vrshrnbq_m_n_<supf><mode>"
7132 [
7133 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7134 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7135 (match_operand:MVE_5 2 "s_register_operand" "w")
7136 (match_operand:SI 3 "mve_imm_8" "Rb")
7137 (match_operand:HI 4 "vpr_register_operand" "Up")]
7138 VRSHRNBQ_M_N))
7139 ]
7140 "TARGET_HAVE_MVE"
7141 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7142 [(set_attr "type" "mve_move")
7143 (set_attr "length""8")])
7144
7145;;
7146;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
7147;;
7148(define_insn "mve_vrshrntq_m_n_<supf><mode>"
7149 [
7150 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7151 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7152 (match_operand:MVE_5 2 "s_register_operand" "w")
7153 (match_operand:SI 3 "mve_imm_8" "Rb")
7154 (match_operand:HI 4 "vpr_register_operand" "Up")]
7155 VRSHRNTQ_M_N))
7156 ]
7157 "TARGET_HAVE_MVE"
7158 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7159 [(set_attr "type" "mve_move")
7160 (set_attr "length""8")])
7161
7162;;
7163;; [vshllbq_m_n_u, vshllbq_m_n_s])
7164;;
7165(define_insn "mve_vshllbq_m_n_<supf><mode>"
7166 [
7167 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7168 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7169 (match_operand:MVE_3 2 "s_register_operand" "w")
7170 (match_operand:SI 3 "immediate_operand" "i")
7171 (match_operand:HI 4 "vpr_register_operand" "Up")]
7172 VSHLLBQ_M_N))
7173 ]
7174 "TARGET_HAVE_MVE"
7175 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7176 [(set_attr "type" "mve_move")
7177 (set_attr "length""8")])
7178
7179;;
7180;; [vshlltq_m_n_u, vshlltq_m_n_s])
7181;;
7182(define_insn "mve_vshlltq_m_n_<supf><mode>"
7183 [
7184 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7185 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7186 (match_operand:MVE_3 2 "s_register_operand" "w")
7187 (match_operand:SI 3 "immediate_operand" "i")
7188 (match_operand:HI 4 "vpr_register_operand" "Up")]
7189 VSHLLTQ_M_N))
7190 ]
7191 "TARGET_HAVE_MVE"
7192 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7193 [(set_attr "type" "mve_move")
7194 (set_attr "length""8")])
7195
7196;;
7197;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
7198;;
7199(define_insn "mve_vshrnbq_m_n_<supf><mode>"
7200 [
7201 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7202 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7203 (match_operand:MVE_5 2 "s_register_operand" "w")
7204 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7205 (match_operand:HI 4 "vpr_register_operand" "Up")]
7206 VSHRNBQ_M_N))
7207 ]
7208 "TARGET_HAVE_MVE"
7209 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7210 [(set_attr "type" "mve_move")
7211 (set_attr "length""8")])
7212
7213;;
7214;; [vshrntq_m_n_s, vshrntq_m_n_u])
7215;;
7216(define_insn "mve_vshrntq_m_n_<supf><mode>"
7217 [
7218 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7219 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7220 (match_operand:MVE_5 2 "s_register_operand" "w")
7221 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7222 (match_operand:HI 4 "vpr_register_operand" "Up")]
7223 VSHRNTQ_M_N))
7224 ]
7225 "TARGET_HAVE_MVE"
7226 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7227 [(set_attr "type" "mve_move")
7228 (set_attr "length""8")])
7229
7230;;
7231;; [vmlsldavaq_p_s])
7232;;
7233(define_insn "mve_vmlsldavaq_p_s<mode>"
7234 [
7235 (set (match_operand:DI 0 "s_register_operand" "=r")
7236 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7237 (match_operand:MVE_5 2 "s_register_operand" "w")
7238 (match_operand:MVE_5 3 "s_register_operand" "w")
7239 (match_operand:HI 4 "vpr_register_operand" "Up")]
7240 VMLSLDAVAQ_P_S))
7241 ]
7242 "TARGET_HAVE_MVE"
7243 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7244 [(set_attr "type" "mve_move")
7245 (set_attr "length""8")])
7246
7247;;
7248;; [vmlsldavaxq_p_s])
7249;;
7250(define_insn "mve_vmlsldavaxq_p_s<mode>"
7251 [
7252 (set (match_operand:DI 0 "s_register_operand" "=r")
7253 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7254 (match_operand:MVE_5 2 "s_register_operand" "w")
7255 (match_operand:MVE_5 3 "s_register_operand" "w")
7256 (match_operand:HI 4 "vpr_register_operand" "Up")]
7257 VMLSLDAVAXQ_P_S))
7258 ]
7259 "TARGET_HAVE_MVE"
7260 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7261 [(set_attr "type" "mve_move")
7262 (set_attr "length""8")])
7263
7264;;
7265;; [vmullbq_poly_m_p])
7266;;
7267(define_insn "mve_vmullbq_poly_m_p<mode>"
7268 [
7269 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7270 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7271 (match_operand:MVE_3 2 "s_register_operand" "w")
7272 (match_operand:MVE_3 3 "s_register_operand" "w")
7273 (match_operand:HI 4 "vpr_register_operand" "Up")]
7274 VMULLBQ_POLY_M_P))
7275 ]
7276 "TARGET_HAVE_MVE"
7277 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7278 [(set_attr "type" "mve_move")
7279 (set_attr "length""8")])
7280
7281;;
7282;; [vmulltq_poly_m_p])
7283;;
7284(define_insn "mve_vmulltq_poly_m_p<mode>"
7285 [
7286 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7287 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7288 (match_operand:MVE_3 2 "s_register_operand" "w")
7289 (match_operand:MVE_3 3 "s_register_operand" "w")
7290 (match_operand:HI 4 "vpr_register_operand" "Up")]
7291 VMULLTQ_POLY_M_P))
7292 ]
7293 "TARGET_HAVE_MVE"
7294 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7295 [(set_attr "type" "mve_move")
7296 (set_attr "length""8")])
7297
7298;;
7299;; [vqdmullbq_m_n_s])
7300;;
7301(define_insn "mve_vqdmullbq_m_n_s<mode>"
7302 [
7303 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7304 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7305 (match_operand:MVE_5 2 "s_register_operand" "w")
7306 (match_operand:<V_elem> 3 "s_register_operand" "r")
7307 (match_operand:HI 4 "vpr_register_operand" "Up")]
7308 VQDMULLBQ_M_N_S))
7309 ]
7310 "TARGET_HAVE_MVE"
7311 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7312 [(set_attr "type" "mve_move")
7313 (set_attr "length""8")])
7314
7315;;
7316;; [vqdmullbq_m_s])
7317;;
7318(define_insn "mve_vqdmullbq_m_s<mode>"
7319 [
7320 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7321 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7322 (match_operand:MVE_5 2 "s_register_operand" "w")
7323 (match_operand:MVE_5 3 "s_register_operand" "w")
7324 (match_operand:HI 4 "vpr_register_operand" "Up")]
7325 VQDMULLBQ_M_S))
7326 ]
7327 "TARGET_HAVE_MVE"
7328 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7329 [(set_attr "type" "mve_move")
7330 (set_attr "length""8")])
7331
7332;;
7333;; [vqdmulltq_m_n_s])
7334;;
7335(define_insn "mve_vqdmulltq_m_n_s<mode>"
7336 [
7337 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7338 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7339 (match_operand:MVE_5 2 "s_register_operand" "w")
7340 (match_operand:<V_elem> 3 "s_register_operand" "r")
7341 (match_operand:HI 4 "vpr_register_operand" "Up")]
7342 VQDMULLTQ_M_N_S))
7343 ]
7344 "TARGET_HAVE_MVE"
7345 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
7346 [(set_attr "type" "mve_move")
7347 (set_attr "length""8")])
7348
7349;;
7350;; [vqdmulltq_m_s])
7351;;
7352(define_insn "mve_vqdmulltq_m_s<mode>"
7353 [
7354 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7355 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7356 (match_operand:MVE_5 2 "s_register_operand" "w")
7357 (match_operand:MVE_5 3 "s_register_operand" "w")
7358 (match_operand:HI 4 "vpr_register_operand" "Up")]
7359 VQDMULLTQ_M_S))
7360 ]
7361 "TARGET_HAVE_MVE"
7362 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7363 [(set_attr "type" "mve_move")
7364 (set_attr "length""8")])
7365
7366;;
7367;; [vqrshrunbq_m_n_s])
7368;;
7369(define_insn "mve_vqrshrunbq_m_n_s<mode>"
7370 [
7371 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7372 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7373 (match_operand:MVE_5 2 "s_register_operand" "w")
7374 (match_operand:SI 3 "mve_imm_8" "Rb")
7375 (match_operand:HI 4 "vpr_register_operand" "Up")]
7376 VQRSHRUNBQ_M_N_S))
7377 ]
7378 "TARGET_HAVE_MVE"
7379 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7380 [(set_attr "type" "mve_move")
7381 (set_attr "length""8")])
7382
7383;;
7384;; [vqrshruntq_m_n_s])
7385;;
7386(define_insn "mve_vqrshruntq_m_n_s<mode>"
7387 [
7388 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7389 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7390 (match_operand:MVE_5 2 "s_register_operand" "w")
7391 (match_operand:SI 3 "mve_imm_8" "Rb")
7392 (match_operand:HI 4 "vpr_register_operand" "Up")]
7393 VQRSHRUNTQ_M_N_S))
7394 ]
7395 "TARGET_HAVE_MVE"
7396 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7397 [(set_attr "type" "mve_move")
7398 (set_attr "length""8")])
7399
7400;;
7401;; [vqshrunbq_m_n_s])
7402;;
7403(define_insn "mve_vqshrunbq_m_n_s<mode>"
7404 [
7405 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7406 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7407 (match_operand:MVE_5 2 "s_register_operand" "w")
7408 (match_operand:SI 3 "mve_imm_8" "Rb")
7409 (match_operand:HI 4 "vpr_register_operand" "Up")]
7410 VQSHRUNBQ_M_N_S))
7411 ]
7412 "TARGET_HAVE_MVE"
7413 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7414 [(set_attr "type" "mve_move")
7415 (set_attr "length""8")])
7416
7417;;
7418;; [vqshruntq_m_n_s])
7419;;
7420(define_insn "mve_vqshruntq_m_n_s<mode>"
7421 [
7422 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7423 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7424 (match_operand:MVE_5 2 "s_register_operand" "w")
7425 (match_operand:SI 3 "mve_imm_8" "Rb")
7426 (match_operand:HI 4 "vpr_register_operand" "Up")]
7427 VQSHRUNTQ_M_N_S))
7428 ]
7429 "TARGET_HAVE_MVE"
7430 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7431 [(set_attr "type" "mve_move")
7432 (set_attr "length""8")])
7433
7434;;
7435;; [vrmlaldavhaq_p_u])
7436;;
7437(define_insn "mve_vrmlaldavhaq_p_uv4si"
7438 [
7439 (set (match_operand:DI 0 "s_register_operand" "=r")
7440 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7441 (match_operand:V4SI 2 "s_register_operand" "w")
7442 (match_operand:V4SI 3 "s_register_operand" "w")
7443 (match_operand:HI 4 "vpr_register_operand" "Up")]
7444 VRMLALDAVHAQ_P_U))
7445 ]
7446 "TARGET_HAVE_MVE"
7447 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
7448 [(set_attr "type" "mve_move")
7449 (set_attr "length""8")])
7450
7451;;
7452;; [vrmlaldavhaxq_p_s])
7453;;
7454(define_insn "mve_vrmlaldavhaxq_p_sv4si"
7455 [
7456 (set (match_operand:DI 0 "s_register_operand" "=r")
7457 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7458 (match_operand:V4SI 2 "s_register_operand" "w")
7459 (match_operand:V4SI 3 "s_register_operand" "w")
7460 (match_operand:HI 4 "vpr_register_operand" "Up")]
7461 VRMLALDAVHAXQ_P_S))
7462 ]
7463 "TARGET_HAVE_MVE"
7464 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7465 [(set_attr "type" "mve_move")
7466 (set_attr "length""8")])
7467
7468;;
7469;; [vrmlsldavhaq_p_s])
7470;;
7471(define_insn "mve_vrmlsldavhaq_p_sv4si"
7472 [
7473 (set (match_operand:DI 0 "s_register_operand" "=r")
7474 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7475 (match_operand:V4SI 2 "s_register_operand" "w")
7476 (match_operand:V4SI 3 "s_register_operand" "w")
7477 (match_operand:HI 4 "vpr_register_operand" "Up")]
7478 VRMLSLDAVHAQ_P_S))
7479 ]
7480 "TARGET_HAVE_MVE"
7481 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
7482 [(set_attr "type" "mve_move")
7483 (set_attr "length""8")])
7484
7485;;
7486;; [vrmlsldavhaxq_p_s])
7487;;
7488(define_insn "mve_vrmlsldavhaxq_p_sv4si"
7489 [
7490 (set (match_operand:DI 0 "s_register_operand" "=r")
7491 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7492 (match_operand:V4SI 2 "s_register_operand" "w")
7493 (match_operand:V4SI 3 "s_register_operand" "w")
7494 (match_operand:HI 4 "vpr_register_operand" "Up")]
7495 VRMLSLDAVHAXQ_P_S))
7496 ]
7497 "TARGET_HAVE_MVE"
7498 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7499 [(set_attr "type" "mve_move")
7500 (set_attr "length""8")])
532e9e24
SP		 7501;;
7502;; [vabdq_m_f])
7503;;
7504(define_insn "mve_vabdq_m_f<mode>"
7505 [
7506 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7507 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7508 (match_operand:MVE_0 2 "s_register_operand" "w")
7509 (match_operand:MVE_0 3 "s_register_operand" "w")
7510 (match_operand:HI 4 "vpr_register_operand" "Up")]
7511 VABDQ_M_F))
7512 ]
7513 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7514 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3"
7515 [(set_attr "type" "mve_move")
7516 (set_attr "length""8")])
7517
7518;;
7519;; [vaddq_m_f])
7520;;
7521(define_insn "mve_vaddq_m_f<mode>"
7522 [
7523 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7524 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7525 (match_operand:MVE_0 2 "s_register_operand" "w")
7526 (match_operand:MVE_0 3 "s_register_operand" "w")
7527 (match_operand:HI 4 "vpr_register_operand" "Up")]
7528 VADDQ_M_F))
7529 ]
7530 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7531 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3"
7532 [(set_attr "type" "mve_move")
7533 (set_attr "length""8")])
7534
7535;;
7536;; [vaddq_m_n_f])
7537;;
7538(define_insn "mve_vaddq_m_n_f<mode>"
7539 [
7540 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7541 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7542 (match_operand:MVE_0 2 "s_register_operand" "w")
7543 (match_operand:<V_elem> 3 "s_register_operand" "r")
7544 (match_operand:HI 4 "vpr_register_operand" "Up")]
7545 VADDQ_M_N_F))
7546 ]
7547 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7548 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3"
7549 [(set_attr "type" "mve_move")
7550 (set_attr "length""8")])
7551
7552;;
7553;; [vandq_m_f])
7554;;
7555(define_insn "mve_vandq_m_f<mode>"
7556 [
7557 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7558 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7559 (match_operand:MVE_0 2 "s_register_operand" "w")
7560 (match_operand:MVE_0 3 "s_register_operand" "w")
7561 (match_operand:HI 4 "vpr_register_operand" "Up")]
7562 VANDQ_M_F))
7563 ]
7564 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7565 "vpst\;vandt %q0, %q2, %q3"
7566 [(set_attr "type" "mve_move")
7567 (set_attr "length""8")])
7568
7569;;
7570;; [vbicq_m_f])
7571;;
7572(define_insn "mve_vbicq_m_f<mode>"
7573 [
7574 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7575 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7576 (match_operand:MVE_0 2 "s_register_operand" "w")
7577 (match_operand:MVE_0 3 "s_register_operand" "w")
7578 (match_operand:HI 4 "vpr_register_operand" "Up")]
7579 VBICQ_M_F))
7580 ]
7581 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7582 "vpst\;vbict %q0, %q2, %q3"
7583 [(set_attr "type" "mve_move")
7584 (set_attr "length""8")])
7585
7586;;
7587;; [vbrsrq_m_n_f])
7588;;
7589(define_insn "mve_vbrsrq_m_n_f<mode>"
7590 [
7591 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7592 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7593 (match_operand:MVE_0 2 "s_register_operand" "w")
7594 (match_operand:SI 3 "s_register_operand" "r")
7595 (match_operand:HI 4 "vpr_register_operand" "Up")]
7596 VBRSRQ_M_N_F))
7597 ]
7598 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7599 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
7600 [(set_attr "type" "mve_move")
7601 (set_attr "length""8")])
7602
7603;;
7604;; [vcaddq_rot270_m_f])
7605;;
7606(define_insn "mve_vcaddq_rot270_m_f<mode>"
7607 [
7608 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7609 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7610 (match_operand:MVE_0 2 "s_register_operand" "w")
7611 (match_operand:MVE_0 3 "s_register_operand" "w")
7612 (match_operand:HI 4 "vpr_register_operand" "Up")]
7613 VCADDQ_ROT270_M_F))
7614 ]
7615 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7616 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7617 [(set_attr "type" "mve_move")
7618 (set_attr "length""8")])
7619
7620;;
7621;; [vcaddq_rot90_m_f])
7622;;
7623(define_insn "mve_vcaddq_rot90_m_f<mode>"
7624 [
7625 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7626 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7627 (match_operand:MVE_0 2 "s_register_operand" "w")
7628 (match_operand:MVE_0 3 "s_register_operand" "w")
7629 (match_operand:HI 4 "vpr_register_operand" "Up")]
7630 VCADDQ_ROT90_M_F))
7631 ]
7632 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7633 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7634 [(set_attr "type" "mve_move")
7635 (set_attr "length""8")])
7636
7637;;
7638;; [vcmlaq_m_f])
7639;;
7640(define_insn "mve_vcmlaq_m_f<mode>"
7641 [
7642 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7643 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7644 (match_operand:MVE_0 2 "s_register_operand" "w")
7645 (match_operand:MVE_0 3 "s_register_operand" "w")
7646 (match_operand:HI 4 "vpr_register_operand" "Up")]
7647 VCMLAQ_M_F))
7648 ]
7649 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7650 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7651 [(set_attr "type" "mve_move")
7652 (set_attr "length""8")])
7653
7654;;
7655;; [vcmlaq_rot180_m_f])
7656;;
7657(define_insn "mve_vcmlaq_rot180_m_f<mode>"
7658 [
7659 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7660 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7661 (match_operand:MVE_0 2 "s_register_operand" "w")
7662 (match_operand:MVE_0 3 "s_register_operand" "w")
7663 (match_operand:HI 4 "vpr_register_operand" "Up")]
7664 VCMLAQ_ROT180_M_F))
7665 ]
7666 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7667 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7668 [(set_attr "type" "mve_move")
7669 (set_attr "length""8")])
7670
7671;;
7672;; [vcmlaq_rot270_m_f])
7673;;
7674(define_insn "mve_vcmlaq_rot270_m_f<mode>"
7675 [
7676 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7677 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7678 (match_operand:MVE_0 2 "s_register_operand" "w")
7679 (match_operand:MVE_0 3 "s_register_operand" "w")
7680 (match_operand:HI 4 "vpr_register_operand" "Up")]
7681 VCMLAQ_ROT270_M_F))
7682 ]
7683 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7684 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7685 [(set_attr "type" "mve_move")
7686 (set_attr "length""8")])
7687
7688;;
7689;; [vcmlaq_rot90_m_f])
7690;;
7691(define_insn "mve_vcmlaq_rot90_m_f<mode>"
7692 [
7693 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7694 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7695 (match_operand:MVE_0 2 "s_register_operand" "w")
7696 (match_operand:MVE_0 3 "s_register_operand" "w")
7697 (match_operand:HI 4 "vpr_register_operand" "Up")]
7698 VCMLAQ_ROT90_M_F))
7699 ]
7700 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7701 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7702 [(set_attr "type" "mve_move")
7703 (set_attr "length""8")])
7704
7705;;
7706;; [vcmulq_m_f])
7707;;
7708(define_insn "mve_vcmulq_m_f<mode>"
7709 [
7710 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7711 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7712 (match_operand:MVE_0 2 "s_register_operand" "w")
7713 (match_operand:MVE_0 3 "s_register_operand" "w")
7714 (match_operand:HI 4 "vpr_register_operand" "Up")]
7715 VCMULQ_M_F))
7716 ]
7717 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7718 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7719 [(set_attr "type" "mve_move")
7720 (set_attr "length""8")])
7721
7722;;
7723;; [vcmulq_rot180_m_f])
7724;;
7725(define_insn "mve_vcmulq_rot180_m_f<mode>"
7726 [
7727 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7728 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7729 (match_operand:MVE_0 2 "s_register_operand" "w")
7730 (match_operand:MVE_0 3 "s_register_operand" "w")
7731 (match_operand:HI 4 "vpr_register_operand" "Up")]
7732 VCMULQ_ROT180_M_F))
7733 ]
7734 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7735 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7736 [(set_attr "type" "mve_move")
7737 (set_attr "length""8")])
7738
7739;;
7740;; [vcmulq_rot270_m_f])
7741;;
7742(define_insn "mve_vcmulq_rot270_m_f<mode>"
7743 [
7744 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7745 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7746 (match_operand:MVE_0 2 "s_register_operand" "w")
7747 (match_operand:MVE_0 3 "s_register_operand" "w")
7748 (match_operand:HI 4 "vpr_register_operand" "Up")]
7749 VCMULQ_ROT270_M_F))
7750 ]
7751 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7752 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7753 [(set_attr "type" "mve_move")
7754 (set_attr "length""8")])
7755
7756;;
7757;; [vcmulq_rot90_m_f])
7758;;
7759(define_insn "mve_vcmulq_rot90_m_f<mode>"
7760 [
7761 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7762 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7763 (match_operand:MVE_0 2 "s_register_operand" "w")
7764 (match_operand:MVE_0 3 "s_register_operand" "w")
7765 (match_operand:HI 4 "vpr_register_operand" "Up")]
7766 VCMULQ_ROT90_M_F))
7767 ]
7768 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7769 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7770 [(set_attr "type" "mve_move")
7771 (set_attr "length""8")])
7772
7773;;
7774;; [veorq_m_f])
7775;;
7776(define_insn "mve_veorq_m_f<mode>"
7777 [
7778 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7779 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7780 (match_operand:MVE_0 2 "s_register_operand" "w")
7781 (match_operand:MVE_0 3 "s_register_operand" "w")
7782 (match_operand:HI 4 "vpr_register_operand" "Up")]
7783 VEORQ_M_F))
7784 ]
7785 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7786 "vpst\;veort %q0, %q2, %q3"
7787 [(set_attr "type" "mve_move")
7788 (set_attr "length""8")])
7789
7790;;
7791;; [vfmaq_m_f])
7792;;
7793(define_insn "mve_vfmaq_m_f<mode>"
7794 [
7795 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7796 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7797 (match_operand:MVE_0 2 "s_register_operand" "w")
7798 (match_operand:MVE_0 3 "s_register_operand" "w")
7799 (match_operand:HI 4 "vpr_register_operand" "Up")]
7800 VFMAQ_M_F))
7801 ]
7802 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7803 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3"
7804 [(set_attr "type" "mve_move")
7805 (set_attr "length""8")])
7806
7807;;
7808;; [vfmaq_m_n_f])
7809;;
7810(define_insn "mve_vfmaq_m_n_f<mode>"
7811 [
7812 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7813 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7814 (match_operand:MVE_0 2 "s_register_operand" "w")
7815 (match_operand:<V_elem> 3 "s_register_operand" "r")
7816 (match_operand:HI 4 "vpr_register_operand" "Up")]
7817 VFMAQ_M_N_F))
7818 ]
7819 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7820 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3"
7821 [(set_attr "type" "mve_move")
7822 (set_attr "length""8")])
7823
7824;;
7825;; [vfmasq_m_n_f])
7826;;
7827(define_insn "mve_vfmasq_m_n_f<mode>"
7828 [
7829 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7830 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7831 (match_operand:MVE_0 2 "s_register_operand" "w")
7832 (match_operand:<V_elem> 3 "s_register_operand" "r")
7833 (match_operand:HI 4 "vpr_register_operand" "Up")]
7834 VFMASQ_M_N_F))
7835 ]
7836 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7837 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3"
7838 [(set_attr "type" "mve_move")
7839 (set_attr "length""8")])
7840
7841;;
7842;; [vfmsq_m_f])
7843;;
7844(define_insn "mve_vfmsq_m_f<mode>"
7845 [
7846 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7847 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7848 (match_operand:MVE_0 2 "s_register_operand" "w")
7849 (match_operand:MVE_0 3 "s_register_operand" "w")
7850 (match_operand:HI 4 "vpr_register_operand" "Up")]
7851 VFMSQ_M_F))
7852 ]
7853 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7854 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3"
7855 [(set_attr "type" "mve_move")
7856 (set_attr "length""8")])
7857
7858;;
7859;; [vmaxnmq_m_f])
7860;;
7861(define_insn "mve_vmaxnmq_m_f<mode>"
7862 [
7863 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7864 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7865 (match_operand:MVE_0 2 "s_register_operand" "w")
7866 (match_operand:MVE_0 3 "s_register_operand" "w")
7867 (match_operand:HI 4 "vpr_register_operand" "Up")]
7868 VMAXNMQ_M_F))
7869 ]
7870 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7871 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7872 [(set_attr "type" "mve_move")
7873 (set_attr "length""8")])
7874
7875;;
7876;; [vminnmq_m_f])
7877;;
7878(define_insn "mve_vminnmq_m_f<mode>"
7879 [
7880 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7881 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7882 (match_operand:MVE_0 2 "s_register_operand" "w")
7883 (match_operand:MVE_0 3 "s_register_operand" "w")
7884 (match_operand:HI 4 "vpr_register_operand" "Up")]
7885 VMINNMQ_M_F))
7886 ]
7887 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7888 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7889 [(set_attr "type" "mve_move")
7890 (set_attr "length""8")])
7891
7892;;
7893;; [vmulq_m_f])
7894;;
7895(define_insn "mve_vmulq_m_f<mode>"
7896 [
7897 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7898 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7899 (match_operand:MVE_0 2 "s_register_operand" "w")
7900 (match_operand:MVE_0 3 "s_register_operand" "w")
7901 (match_operand:HI 4 "vpr_register_operand" "Up")]
7902 VMULQ_M_F))
7903 ]
7904 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7905 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3"
7906 [(set_attr "type" "mve_move")
7907 (set_attr "length""8")])
7908
7909;;
7910;; [vmulq_m_n_f])
7911;;
7912(define_insn "mve_vmulq_m_n_f<mode>"
7913 [
7914 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7915 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7916 (match_operand:MVE_0 2 "s_register_operand" "w")
7917 (match_operand:<V_elem> 3 "s_register_operand" "r")
7918 (match_operand:HI 4 "vpr_register_operand" "Up")]
7919 VMULQ_M_N_F))
7920 ]
7921 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7922 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3"
7923 [(set_attr "type" "mve_move")
7924 (set_attr "length""8")])
7925
7926;;
7927;; [vornq_m_f])
7928;;
7929(define_insn "mve_vornq_m_f<mode>"
7930 [
7931 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7932 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7933 (match_operand:MVE_0 2 "s_register_operand" "w")
7934 (match_operand:MVE_0 3 "s_register_operand" "w")
7935 (match_operand:HI 4 "vpr_register_operand" "Up")]
7936 VORNQ_M_F))
7937 ]
7938 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7939 "vpst\;vornt %q0, %q2, %q3"
7940 [(set_attr "type" "mve_move")
7941 (set_attr "length""8")])
7942
7943;;
7944;; [vorrq_m_f])
7945;;
7946(define_insn "mve_vorrq_m_f<mode>"
7947 [
7948 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7949 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7950 (match_operand:MVE_0 2 "s_register_operand" "w")
7951 (match_operand:MVE_0 3 "s_register_operand" "w")
7952 (match_operand:HI 4 "vpr_register_operand" "Up")]
7953 VORRQ_M_F))
7954 ]
7955 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7956 "vpst\;vorrt %q0, %q2, %q3"
7957 [(set_attr "type" "mve_move")
7958 (set_attr "length""8")])
7959
7960;;
7961;; [vsubq_m_f])
7962;;
7963(define_insn "mve_vsubq_m_f<mode>"
7964 [
7965 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7966 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7967 (match_operand:MVE_0 2 "s_register_operand" "w")
7968 (match_operand:MVE_0 3 "s_register_operand" "w")
7969 (match_operand:HI 4 "vpr_register_operand" "Up")]
7970 VSUBQ_M_F))
7971 ]
7972 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7973 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3"
7974 [(set_attr "type" "mve_move")
7975 (set_attr "length""8")])
7976
7977;;
7978;; [vsubq_m_n_f])
7979;;
7980(define_insn "mve_vsubq_m_n_f<mode>"
7981 [
7982 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7983 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7984 (match_operand:MVE_0 2 "s_register_operand" "w")
7985 (match_operand:<V_elem> 3 "s_register_operand" "r")
7986 (match_operand:HI 4 "vpr_register_operand" "Up")]
7987 VSUBQ_M_N_F))
7988 ]
7989 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7990 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
7991 [(set_attr "type" "mve_move")
7992 (set_attr "length""8")])
4ff68575
SP		 7993
7994;;
7995;; [vstrbq_s vstrbq_u]
7996;;
7997(define_insn "mve_vstrbq_<supf><mode>"
7998 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
7999 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
8000 VSTRBQ))
8001 ]
8002 "TARGET_HAVE_MVE"
8003{
8004 rtx ops[2];
8005 int regno = REGNO (operands[1]);
8006 ops[1] = gen_rtx_REG (TImode, regno);
8007 ops[0] = operands[0];
8008 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
8009 return "";
8010}
8011 [(set_attr "length" "4")])
8012
8013;;
8014;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
8015;;
8016(define_insn "mve_vstrbq_scatter_offset_<supf><mode>"
8017 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8018 (unspec:<MVE_B_ELEM>
8019 [(match_operand:MVE_2 1 "s_register_operand" "w")
8020 (match_operand:MVE_2 2 "s_register_operand" "w")]
8021 VSTRBSOQ))
8022 ]
8023 "TARGET_HAVE_MVE"
8024{
8025 rtx ops[3];
8026 ops[0] = operands[0];
8027 ops[1] = operands[1];
8028 ops[2] = operands[2];
8029 output_asm_insn("vstrb.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8030 return "";
8031}
8032 [(set_attr "length" "4")])
8033
8034;;
8035;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
8036;;
8037(define_insn "mve_vstrwq_scatter_base_<supf>v4si"
8038 [(set (mem:BLK (scratch))
8039 (unspec:BLK
8040 [(match_operand:V4SI 0 "s_register_operand" "w")
8041 (match_operand:SI 1 "immediate_operand" "i")
8042 (match_operand:V4SI 2 "s_register_operand" "w")]
8043 VSTRWSBQ))
8044 ]
8045 "TARGET_HAVE_MVE"
8046{
8047 rtx ops[3];
8048 ops[0] = operands[0];
8049 ops[1] = operands[1];
8050 ops[2] = operands[2];
8051 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
8052 return "";
8053}
8054 [(set_attr "length" "4")])
535a8645
SP		 8055
8056;;
8057;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
8058;;
8059(define_insn "mve_vldrbq_gather_offset_<supf><mode>"
8060 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8061 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8062 (match_operand:MVE_2 2 "s_register_operand" "w")]
8063 VLDRBGOQ))
8064 ]
8065 "TARGET_HAVE_MVE"
8066{
8067 rtx ops[3];
8068 ops[0] = operands[0];
8069 ops[1] = operands[1];
8070 ops[2] = operands[2];
8071 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8072 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
8073 else
8074 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8075 return "";
8076}
8077 [(set_attr "length" "4")])
8078
8079;;
8080;; [vldrbq_s vldrbq_u]
8081;;
8082(define_insn "mve_vldrbq_<supf><mode>"
8083 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8084 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")]
8085 VLDRBQ))
8086 ]
8087 "TARGET_HAVE_MVE"
8088{
8089 rtx ops[2];
8090 int regno = REGNO (operands[0]);
8091 ops[0] = gen_rtx_REG (TImode, regno);
8092 ops[1] = operands[1];
8093 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
8094 return "";
8095}
8096 [(set_attr "length" "4")])
8097
8098;;
8099;; [vldrwq_gather_base_s vldrwq_gather_base_u]
8100;;
8101(define_insn "mve_vldrwq_gather_base_<supf>v4si"
8102 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8103 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8104 (match_operand:SI 2 "immediate_operand" "i")]
8105 VLDRWGBQ))
8106 ]
8107 "TARGET_HAVE_MVE"
8108{
8109 rtx ops[3];
8110 ops[0] = operands[0];
8111 ops[1] = operands[1];
8112 ops[2] = operands[2];
8113 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8114 return "";
8115}
8116 [(set_attr "length" "4")])
405e918c
SP		 8117
8118;;
8119;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
8120;;
8121(define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>"
8122 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8123 (unspec:<MVE_B_ELEM>
8124 [(match_operand:MVE_2 1 "s_register_operand" "w")
8125 (match_operand:MVE_2 2 "s_register_operand" "w")
8126 (match_operand:HI 3 "vpr_register_operand" "Up")]
8127 VSTRBSOQ))
8128 ]
8129 "TARGET_HAVE_MVE"
8130{
8131 rtx ops[3];
8132 ops[0] = operands[0];
8133 ops[1] = operands[1];
8134 ops[2] = operands[2];
8135 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8136 return "";
8137}
8138 [(set_attr "length" "8")])
8139
8140;;
8141;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
8142;;
8143(define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
8144 [(set (mem:BLK (scratch))
8145 (unspec:BLK
8146 [(match_operand:V4SI 0 "s_register_operand" "w")
8147 (match_operand:SI 1 "immediate_operand" "i")
8148 (match_operand:V4SI 2 "s_register_operand" "w")
8149 (match_operand:HI 3 "vpr_register_operand" "Up")]
8150 VSTRWSBQ))
8151 ]
8152 "TARGET_HAVE_MVE"
8153{
8154 rtx ops[3];
8155 ops[0] = operands[0];
8156 ops[1] = operands[1];
8157 ops[2] = operands[2];
8158 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
8159 return "";
8160}
8161 [(set_attr "length" "8")])
8162
8163;;
8164;; [vstrbq_p_s vstrbq_p_u]
8165;;
8166(define_insn "mve_vstrbq_p_<supf><mode>"
8167 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8168 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
8169 (match_operand:HI 2 "vpr_register_operand" "Up")]
8170 VSTRBQ))
8171 ]
8172 "TARGET_HAVE_MVE"
8173{
8174 rtx ops[2];
8175 int regno = REGNO (operands[1]);
8176 ops[1] = gen_rtx_REG (TImode, regno);
8177 ops[0] = operands[0];
8178 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q1, %E0",ops);
8179 return "";
8180}
8181 [(set_attr "length" "8")])
429d607b
SP		 8182
8183;;
8184;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
8185;;
8186(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
8187 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8188 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8189 (match_operand:MVE_2 2 "s_register_operand" "w")
8190 (match_operand:HI 3 "vpr_register_operand" "Up")]
8191 VLDRBGOQ))
8192 ]
8193 "TARGET_HAVE_MVE"
8194{
8195 rtx ops[4];
8196 ops[0] = operands[0];
8197 ops[1] = operands[1];
8198 ops[2] = operands[2];
8199 ops[3] = operands[3];
8200 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8201 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
8202 else
8203 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8204 return "";
8205}
8206 [(set_attr "length" "8")])
8207
8208;;
8209;; [vldrbq_z_s vldrbq_z_u]
8210;;
8211(define_insn "mve_vldrbq_z_<supf><mode>"
8212 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8213 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8214 (match_operand:HI 2 "vpr_register_operand" "Up")]
8215 VLDRBQ))
8216 ]
8217 "TARGET_HAVE_MVE"
8218{
8219 rtx ops[2];
8220 int regno = REGNO (operands[0]);
8221 ops[0] = gen_rtx_REG (TImode, regno);
8222 ops[1] = operands[1];
8223 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
8224 return "";
8225}
8226 [(set_attr "length" "8")])
8227
8228;;
8229;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
8230;;
8231(define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
8232 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8233 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8234 (match_operand:SI 2 "immediate_operand" "i")
8235 (match_operand:HI 3 "vpr_register_operand" "Up")]
8236 VLDRWGBQ))
8237 ]
8238 "TARGET_HAVE_MVE"
8239{
8240 rtx ops[3];
8241 ops[0] = operands[0];
8242 ops[1] = operands[1];
8243 ops[2] = operands[2];
8244 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8245 return "";
8246}
8247 [(set_attr "length" "8")])
bf1e3d5a
SP		 8248
8249;;
8250;; [vldrhq_f]
8251;;
8252(define_insn "mve_vldrhq_fv8hf"
8253 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8254 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]
8255 VLDRHQ_F))
8256 ]
8257 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8258{
8259 rtx ops[2];
8260 int regno = REGNO (operands[0]);
8261 ops[0] = gen_rtx_REG (TImode, regno);
8262 ops[1] = operands[1];
8263 output_asm_insn ("vldrh.f16\t%q0, %E1",ops);
8264 return "";
8265}
8266 [(set_attr "length" "4")])
8267
8268;;
8269;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
8270;;
8271(define_insn "mve_vldrhq_gather_offset_<supf><mode>"
8272 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8273 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8274 (match_operand:MVE_6 2 "s_register_operand" "w")]
8275 VLDRHGOQ))
8276 ]
8277 "TARGET_HAVE_MVE"
8278{
8279 rtx ops[3];
8280 ops[0] = operands[0];
8281 ops[1] = operands[1];
8282 ops[2] = operands[2];
8283 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8284 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
8285 else
8286 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8287 return "";
8288}
8289 [(set_attr "length" "4")])
8290
8291;;
8292;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
8293;;
8294(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
8295 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8296 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8297 (match_operand:MVE_6 2 "s_register_operand" "w")
8298 (match_operand:HI 3 "vpr_register_operand" "Up")
8299 ]VLDRHGOQ))
8300 ]
8301 "TARGET_HAVE_MVE"
8302{
8303 rtx ops[4];
8304 ops[0] = operands[0];
8305 ops[1] = operands[1];
8306 ops[2] = operands[2];
8307 ops[3] = operands[3];
8308 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8309 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
8310 else
8311 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8312 return "";
8313}
8314 [(set_attr "length" "8")])
8315
8316;;
8317;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
8318;;
8319(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
8320 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8321 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8322 (match_operand:MVE_6 2 "s_register_operand" "w")]
8323 VLDRHGSOQ))
8324 ]
8325 "TARGET_HAVE_MVE"
8326{
8327 rtx ops[3];
8328 ops[0] = operands[0];
8329 ops[1] = operands[1];
8330 ops[2] = operands[2];
8331 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8332 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8333 else
8334 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8335 return "";
8336}
8337 [(set_attr "length" "4")])
8338
8339;;
8340;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
8341;;
8342(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
8343 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8344 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8345 (match_operand:MVE_6 2 "s_register_operand" "w")
8346 (match_operand:HI 3 "vpr_register_operand" "Up")
8347 ]VLDRHGSOQ))
8348 ]
8349 "TARGET_HAVE_MVE"
8350{
8351 rtx ops[4];
8352 ops[0] = operands[0];
8353 ops[1] = operands[1];
8354 ops[2] = operands[2];
8355 ops[3] = operands[3];
8356 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8357 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8358 else
8359 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8360 return "";
8361}
8362 [(set_attr "length" "8")])
8363
8364;;
8365;;
8366;; [vldrhq_s, vldrhq_u]
8367;;
8368(define_insn "mve_vldrhq_<supf><mode>"
8369 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8370 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")]
8371 VLDRHQ))
8372 ]
8373 "TARGET_HAVE_MVE"
8374{
8375 rtx ops[2];
8376 int regno = REGNO (operands[0]);
8377 ops[0] = gen_rtx_REG (TImode, regno);
8378 ops[1] = operands[1];
8379 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
8380 return "";
8381}
8382 [(set_attr "length" "4")])
8383
8384;;
8385;; [vldrhq_z_f]
8386;;
8387(define_insn "mve_vldrhq_z_fv8hf"
8388 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8389 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8390 (match_operand:HI 2 "vpr_register_operand" "Up")]
8391 VLDRHQ_F))
8392 ]
8393 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8394{
8395 rtx ops[2];
8396 int regno = REGNO (operands[0]);
8397 ops[0] = gen_rtx_REG (TImode, regno);
8398 ops[1] = operands[1];
8399 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);
8400 return "";
8401}
8402 [(set_attr "length" "8")])
8403
8404;;
8405;; [vldrhq_z_s vldrhq_z_u]
8406;;
8407(define_insn "mve_vldrhq_z_<supf><mode>"
8408 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8409 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8410 (match_operand:HI 2 "vpr_register_operand" "Up")]
8411 VLDRHQ))
8412 ]
8413 "TARGET_HAVE_MVE"
8414{
8415 rtx ops[2];
8416 int regno = REGNO (operands[0]);
8417 ops[0] = gen_rtx_REG (TImode, regno);
8418 ops[1] = operands[1];
8419 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
8420 return "";
8421}
8422 [(set_attr "length" "8")])
8423
8424;;
8425;; [vldrwq_f]
8426;;
8427(define_insn "mve_vldrwq_fv4sf"
8428 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8429 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]
8430 VLDRWQ_F))
8431 ]
8432 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8433{
8434 rtx ops[2];
8435 int regno = REGNO (operands[0]);
8436 ops[0] = gen_rtx_REG (TImode, regno);
8437 ops[1] = operands[1];
8438 output_asm_insn ("vldrw.f32\t%q0, %E1",ops);
8439 return "";
8440}
8441 [(set_attr "length" "4")])
8442
8443;;
8444;; [vldrwq_s vldrwq_u]
8445;;
8446(define_insn "mve_vldrwq_<supf>v4si"
8447 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8448 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]
8449 VLDRWQ))
8450 ]
8451 "TARGET_HAVE_MVE"
8452{
8453 rtx ops[2];
8454 int regno = REGNO (operands[0]);
8455 ops[0] = gen_rtx_REG (TImode, regno);
8456 ops[1] = operands[1];
8457 output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);
8458 return "";
8459}
8460 [(set_attr "length" "4")])
8461
8462;;
8463;; [vldrwq_z_f]
8464;;
8465(define_insn "mve_vldrwq_z_fv4sf"
8466 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8467 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8468 (match_operand:HI 2 "vpr_register_operand" "Up")]
8469 VLDRWQ_F))
8470 ]
8471 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8472{
8473 rtx ops[2];
8474 int regno = REGNO (operands[0]);
8475 ops[0] = gen_rtx_REG (TImode, regno);
8476 ops[1] = operands[1];
8477 output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);
8478 return "";
8479}
8480 [(set_attr "length" "8")])
8481
8482;;
8483;; [vldrwq_z_s vldrwq_z_u]
8484;;
8485(define_insn "mve_vldrwq_z_<supf>v4si"
8486 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8487 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8488 (match_operand:HI 2 "vpr_register_operand" "Up")]
8489 VLDRWQ))
8490 ]
8491 "TARGET_HAVE_MVE"
8492{
8493 rtx ops[2];
8494 int regno = REGNO (operands[0]);
8495 ops[0] = gen_rtx_REG (TImode, regno);
8496 ops[1] = operands[1];
8497 output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);
8498 return "";
8499}
8500 [(set_attr "length" "8")])
8501
8502(define_expand "mve_vld1q_f<mode>"
8503 [(match_operand:MVE_0 0 "s_register_operand")
8504 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")] VLD1Q_F)
8505 ]
8506 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
8507{
8508 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
8509 DONE;
8510})
8511
8512(define_expand "mve_vld1q_<supf><mode>"
8513 [(match_operand:MVE_2 0 "s_register_operand")
8514 (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)
8515 ]
8516 "TARGET_HAVE_MVE"
8517{
8518 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
8519 DONE;
8520})
4cc23303
SP		 8521
8522;;
8523;; [vldrdq_gather_base_s vldrdq_gather_base_u]
8524;;
8525(define_insn "mve_vldrdq_gather_base_<supf>v2di"
8526 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8527 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8528 (match_operand:SI 2 "immediate_operand" "i")]
8529 VLDRDGBQ))
8530 ]
8531 "TARGET_HAVE_MVE"
8532{
8533 rtx ops[3];
8534 ops[0] = operands[0];
8535 ops[1] = operands[1];
8536 ops[2] = operands[2];
8537 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops);
8538 return "";
8539}
8540 [(set_attr "length" "4")])
8541
8542;;
8543;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u]
8544;;
8545(define_insn "mve_vldrdq_gather_base_z_<supf>v2di"
8546 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8547 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
8548 (match_operand:SI 2 "immediate_operand" "i")
8549 (match_operand:HI 3 "vpr_register_operand" "Up")]
8550 VLDRDGBQ))
8551 ]
8552 "TARGET_HAVE_MVE"
8553{
8554 rtx ops[3];
8555 ops[0] = operands[0];
8556 ops[1] = operands[1];
8557 ops[2] = operands[2];
8558 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops);
8559 return "";
8560}
8561 [(set_attr "length" "8")])
8562
8563;;
8564;; [vldrdq_gather_offset_s vldrdq_gather_offset_u]
8565;;
8566(define_insn "mve_vldrdq_gather_offset_<supf>v2di"
8567 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8568 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8569 (match_operand:V2DI 2 "s_register_operand" "w")]
8570 VLDRDGOQ))
8571 ]
8572 "TARGET_HAVE_MVE"
8573{
8574 rtx ops[3];
8575 ops[0] = operands[0];
8576 ops[1] = operands[1];
8577 ops[2] = operands[2];
8578 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops);
8579 return "";
8580}
8581 [(set_attr "length" "4")])
8582
8583;;
8584;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u]
8585;;
8586(define_insn "mve_vldrdq_gather_offset_z_<supf>v2di"
8587 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8588 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8589 (match_operand:V2DI 2 "s_register_operand" "w")
8590 (match_operand:HI 3 "vpr_register_operand" "Up")]
8591 VLDRDGOQ))
8592 ]
8593 "TARGET_HAVE_MVE"
8594{
8595 rtx ops[3];
8596 ops[0] = operands[0];
8597 ops[1] = operands[1];
8598 ops[2] = operands[2];
8599 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops);
8600 return "";
8601}
8602 [(set_attr "length" "8")])
8603
8604;;
8605;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u]
8606;;
8607(define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di"
8608 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8609 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8610 (match_operand:V2DI 2 "s_register_operand" "w")]
8611 VLDRDGSOQ))
8612 ]
8613 "TARGET_HAVE_MVE"
8614{
8615 rtx ops[3];
8616 ops[0] = operands[0];
8617 ops[1] = operands[1];
8618 ops[2] = operands[2];
8619 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8620 return "";
8621}
8622 [(set_attr "length" "4")])
8623
8624;;
8625;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u]
8626;;
8627(define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di"
8628 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
8629 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
8630 (match_operand:V2DI 2 "s_register_operand" "w")
8631 (match_operand:HI 3 "vpr_register_operand" "Up")]
8632 VLDRDGSOQ))
8633 ]
8634 "TARGET_HAVE_MVE"
8635{
8636 rtx ops[3];
8637 ops[0] = operands[0];
8638 ops[1] = operands[1];
8639 ops[2] = operands[2];
8640 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
8641 return "";
8642}
8643 [(set_attr "length" "8")])
8644
8645;;
8646;; [vldrhq_gather_offset_f]
8647;;
8648(define_insn "mve_vldrhq_gather_offset_fv8hf"
8649 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8650 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8651 (match_operand:V8HI 2 "s_register_operand" "w")]
8652 VLDRHQGO_F))
8653 ]
8654 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8655{
8656 rtx ops[3];
8657 ops[0] = operands[0];
8658 ops[1] = operands[1];
8659 ops[2] = operands[2];
8660 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops);
8661 return "";
8662}
8663 [(set_attr "length" "4")])
8664
8665;;
8666;; [vldrhq_gather_offset_z_f]
8667;;
8668(define_insn "mve_vldrhq_gather_offset_z_fv8hf"
8669 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8670 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8671 (match_operand:V8HI 2 "s_register_operand" "w")
8672 (match_operand:HI 3 "vpr_register_operand" "Up")]
8673 VLDRHQGO_F))
8674 ]
8675 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8676{
8677 rtx ops[4];
8678 ops[0] = operands[0];
8679 ops[1] = operands[1];
8680 ops[2] = operands[2];
8681 ops[3] = operands[3];
8682 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops);
8683 return "";
8684}
8685 [(set_attr "length" "8")])
8686
8687;;
8688;; [vldrhq_gather_shifted_offset_f]
8689;;
8690(define_insn "mve_vldrhq_gather_shifted_offset_fv8hf"
8691 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8692 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8693 (match_operand:V8HI 2 "s_register_operand" "w")]
8694 VLDRHQGSO_F))
8695 ]
8696 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8697{
8698 rtx ops[3];
8699 ops[0] = operands[0];
8700 ops[1] = operands[1];
8701 ops[2] = operands[2];
8702 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8703 return "";
8704}
8705 [(set_attr "length" "4")])
8706
8707;;
8708;; [vldrhq_gather_shifted_offset_z_f]
8709;;
8710(define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf"
8711 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
8712 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8713 (match_operand:V8HI 2 "s_register_operand" "w")
8714 (match_operand:HI 3 "vpr_register_operand" "Up")]
8715 VLDRHQGSO_F))
8716 ]
8717 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8718{
8719 rtx ops[4];
8720 ops[0] = operands[0];
8721 ops[1] = operands[1];
8722 ops[2] = operands[2];
8723 ops[3] = operands[3];
8724 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
8725 return "";
8726}
8727 [(set_attr "length" "8")])
8728
8729;;
8730;; [vldrwq_gather_base_f]
8731;;
8732(define_insn "mve_vldrwq_gather_base_fv4sf"
8733 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8734 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8735 (match_operand:SI 2 "immediate_operand" "i")]
8736 VLDRWQGB_F))
8737 ]
8738 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8739{
8740 rtx ops[3];
8741 ops[0] = operands[0];
8742 ops[1] = operands[1];
8743 ops[2] = operands[2];
8744 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8745 return "";
8746}
8747 [(set_attr "length" "4")])
8748
8749;;
8750;; [vldrwq_gather_base_z_f]
8751;;
8752(define_insn "mve_vldrwq_gather_base_z_fv4sf"
8753 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8754 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
8755 (match_operand:SI 2 "immediate_operand" "i")
8756 (match_operand:HI 3 "vpr_register_operand" "Up")]
8757 VLDRWQGB_F))
8758 ]
8759 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8760{
8761 rtx ops[3];
8762 ops[0] = operands[0];
8763 ops[1] = operands[1];
8764 ops[2] = operands[2];
8765 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8766 return "";
8767}
8768 [(set_attr "length" "8")])
8769
8770;;
8771;; [vldrwq_gather_offset_f]
8772;;
8773(define_insn "mve_vldrwq_gather_offset_fv4sf"
8774 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8775 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8776 (match_operand:V4SI 2 "s_register_operand" "w")]
8777 VLDRWQGO_F))
8778 ]
8779 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8780{
8781 rtx ops[3];
8782 ops[0] = operands[0];
8783 ops[1] = operands[1];
8784 ops[2] = operands[2];
8785 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8786 return "";
8787}
8788 [(set_attr "length" "4")])
8789
8790;;
8791;; [vldrwq_gather_offset_s vldrwq_gather_offset_u]
8792;;
8793(define_insn "mve_vldrwq_gather_offset_<supf>v4si"
8794 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8795 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8796 (match_operand:V4SI 2 "s_register_operand" "w")]
8797 VLDRWGOQ))
8798 ]
8799 "TARGET_HAVE_MVE"
8800{
8801 rtx ops[3];
8802 ops[0] = operands[0];
8803 ops[1] = operands[1];
8804 ops[2] = operands[2];
8805 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
8806 return "";
8807}
8808 [(set_attr "length" "4")])
8809
8810;;
8811;; [vldrwq_gather_offset_z_f]
8812;;
8813(define_insn "mve_vldrwq_gather_offset_z_fv4sf"
8814 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8815 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8816 (match_operand:V4SI 2 "s_register_operand" "w")
8817 (match_operand:HI 3 "vpr_register_operand" "Up")]
8818 VLDRWQGO_F))
8819 ]
8820 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8821{
8822 rtx ops[4];
8823 ops[0] = operands[0];
8824 ops[1] = operands[1];
8825 ops[2] = operands[2];
8826 ops[3] = operands[3];
8827 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8828 return "";
8829}
8830 [(set_attr "length" "8")])
8831
8832;;
8833;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u]
8834;;
8835(define_insn "mve_vldrwq_gather_offset_z_<supf>v4si"
8836 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8837 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8838 (match_operand:V4SI 2 "s_register_operand" "w")
8839 (match_operand:HI 3 "vpr_register_operand" "Up")]
8840 VLDRWGOQ))
8841 ]
8842 "TARGET_HAVE_MVE"
8843{
8844 rtx ops[4];
8845 ops[0] = operands[0];
8846 ops[1] = operands[1];
8847 ops[2] = operands[2];
8848 ops[3] = operands[3];
8849 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
8850 return "";
8851}
8852 [(set_attr "length" "8")])
8853
8854;;
8855;; [vldrwq_gather_shifted_offset_f]
8856;;
8857(define_insn "mve_vldrwq_gather_shifted_offset_fv4sf"
8858 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8859 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8860 (match_operand:V4SI 2 "s_register_operand" "w")]
8861 VLDRWQGSO_F))
8862 ]
8863 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8864{
8865 rtx ops[3];
8866 ops[0] = operands[0];
8867 ops[1] = operands[1];
8868 ops[2] = operands[2];
8869 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8870 return "";
8871}
8872 [(set_attr "length" "4")])
8873
8874;;
8875;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u]
8876;;
8877(define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si"
8878 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8879 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8880 (match_operand:V4SI 2 "s_register_operand" "w")]
8881 VLDRWGSOQ))
8882 ]
8883 "TARGET_HAVE_MVE"
8884{
8885 rtx ops[3];
8886 ops[0] = operands[0];
8887 ops[1] = operands[1];
8888 ops[2] = operands[2];
8889 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8890 return "";
8891}
8892 [(set_attr "length" "4")])
8893
8894;;
8895;; [vldrwq_gather_shifted_offset_z_f]
8896;;
8897(define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf"
8898 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
8899 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8900 (match_operand:V4SI 2 "s_register_operand" "w")
8901 (match_operand:HI 3 "vpr_register_operand" "Up")]
8902 VLDRWQGSO_F))
8903 ]
8904 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8905{
8906 rtx ops[4];
8907 ops[0] = operands[0];
8908 ops[1] = operands[1];
8909 ops[2] = operands[2];
8910 ops[3] = operands[3];
8911 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8912 return "";
8913}
8914 [(set_attr "length" "8")])
8915
8916;;
8917;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u]
8918;;
8919(define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
8920 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8921 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8922 (match_operand:V4SI 2 "s_register_operand" "w")
8923 (match_operand:HI 3 "vpr_register_operand" "Up")]
8924 VLDRWGSOQ))
8925 ]
8926 "TARGET_HAVE_MVE"
8927{
8928 rtx ops[4];
8929 ops[0] = operands[0];
8930 ops[1] = operands[1];
8931 ops[2] = operands[2];
8932 ops[3] = operands[3];
8933 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
8934 return "";
8935}
8936 [(set_attr "length" "8")])
5cad47e0
SP		 8937
8938;;
8939;; [vstrhq_f]
8940;;
8941(define_insn "mve_vstrhq_fv8hf"
8942 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
8943 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")]
8944 VSTRHQ_F))
8945 ]
8946 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8947{
8948 rtx ops[2];
8949 int regno = REGNO (operands[1]);
8950 ops[1] = gen_rtx_REG (TImode, regno);
8951 ops[0] = operands[0];
8952 output_asm_insn ("vstrh.16\t%q1, %E0",ops);
8953 return "";
8954}
8955 [(set_attr "length" "4")])
8956
8957;;
8958;; [vstrhq_p_f]
8959;;
8960(define_insn "mve_vstrhq_p_fv8hf"
8961 [(set (match_operand:V8HI 0 "memory_operand" "=Us")
8962 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
8963 (match_operand:HI 2 "vpr_register_operand" "Up")]
8964 VSTRHQ_F))
8965 ]
8966 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8967{
8968 rtx ops[2];
8969 int regno = REGNO (operands[1]);
8970 ops[1] = gen_rtx_REG (TImode, regno);
8971 ops[0] = operands[0];
8972 output_asm_insn ("vpst\n\tvstrht.16\t%q1, %E0",ops);
8973 return "";
8974}
8975 [(set_attr "length" "8")])
8976
8977;;
8978;; [vstrhq_p_s vstrhq_p_u]
8979;;
8980(define_insn "mve_vstrhq_p_<supf><mode>"
8981 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
8982 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
8983 (match_operand:HI 2 "vpr_register_operand" "Up")]
8984 VSTRHQ))
8985 ]
8986 "TARGET_HAVE_MVE"
8987{
8988 rtx ops[2];
8989 int regno = REGNO (operands[1]);
8990 ops[1] = gen_rtx_REG (TImode, regno);
8991 ops[0] = operands[0];
8992 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q1, %E0",ops);
8993 return "";
8994}
8995 [(set_attr "length" "8")])
8996
8997;;
8998;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u]
8999;;
9000(define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>"
9001 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9002 (unspec:<MVE_H_ELEM>
9003 [(match_operand:MVE_6 1 "s_register_operand" "w")
9004 (match_operand:MVE_6 2 "s_register_operand" "w")
9005 (match_operand:HI 3 "vpr_register_operand" "Up")]
9006 VSTRHSOQ))
9007 ]
9008 "TARGET_HAVE_MVE"
9009{
9010 rtx ops[3];
9011 ops[0] = operands[0];
9012 ops[1] = operands[1];
9013 ops[2] = operands[2];
9014 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
9015 return "";
9016}
9017 [(set_attr "length" "8")])
9018
9019;;
9020;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u]
9021;;
9022(define_insn "mve_vstrhq_scatter_offset_<supf><mode>"
9023 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9024 (unspec:<MVE_H_ELEM>
9025 [(match_operand:MVE_6 1 "s_register_operand" "w")
9026 (match_operand:MVE_6 2 "s_register_operand" "w")]
9027 VSTRHSOQ))
9028 ]
9029 "TARGET_HAVE_MVE"
9030{
9031 rtx ops[3];
9032 ops[0] = operands[0];
9033 ops[1] = operands[1];
9034 ops[2] = operands[2];
9035 output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
9036 return "";
9037}
9038 [(set_attr "length" "4")])
9039
9040;;
9041;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u]
9042;;
9043(define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
9044 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9045 (unspec:<MVE_H_ELEM>
9046 [(match_operand:MVE_6 1 "s_register_operand" "w")
9047 (match_operand:MVE_6 2 "s_register_operand" "w")
9048 (match_operand:HI 3 "vpr_register_operand" "Up")]
9049 VSTRHSSOQ))
9050 ]
9051 "TARGET_HAVE_MVE"
9052{
9053 rtx ops[3];
9054 ops[0] = operands[0];
9055 ops[1] = operands[1];
9056 ops[2] = operands[2];
9057 output_asm_insn ("vpst\n\tvstrht.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
9058 return "";
9059}
9060 [(set_attr "length" "8")])
9061
9062;;
9063;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u]
9064;;
9065(define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
9066 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9067 (unspec:<MVE_H_ELEM>
9068 [(match_operand:MVE_6 1 "s_register_operand" "w")
9069 (match_operand:MVE_6 2 "s_register_operand" "w")]
9070 VSTRHSSOQ))
9071 ]
9072 "TARGET_HAVE_MVE"
9073{
9074 rtx ops[3];
9075 ops[0] = operands[0];
9076 ops[1] = operands[1];
9077 ops[2] = operands[2];
9078 output_asm_insn ("vstrh.<V_sz_elem>\t%q2, [%m0, %q1, uxtw #1]",ops);
9079 return "";
9080}
9081 [(set_attr "length" "4")])
9082
9083;;
9084;; [vstrhq_s, vstrhq_u]
9085;;
9086(define_insn "mve_vstrhq_<supf><mode>"
9087 [(set (match_operand:<MVE_H_ELEM> 0 "memory_operand" "=Us")
9088 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")]
9089 VSTRHQ))
9090 ]
9091 "TARGET_HAVE_MVE"
9092{
9093 rtx ops[2];
9094 int regno = REGNO (operands[1]);
9095 ops[1] = gen_rtx_REG (TImode, regno);
9096 ops[0] = operands[0];
9097 output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops);
9098 return "";
9099}
9100 [(set_attr "length" "4")])
9101
9102;;
9103;; [vstrwq_f]
9104;;
9105(define_insn "mve_vstrwq_fv4sf"
9106 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9107 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
9108 VSTRWQ_F))
9109 ]
9110 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9111{
9112 rtx ops[2];
9113 int regno = REGNO (operands[1]);
9114 ops[1] = gen_rtx_REG (TImode, regno);
9115 ops[0] = operands[0];
9116 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
9117 return "";
9118}
9119 [(set_attr "length" "4")])
9120
9121;;
9122;; [vstrwq_p_f]
9123;;
9124(define_insn "mve_vstrwq_p_fv4sf"
9125 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9126 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
9127 (match_operand:HI 2 "vpr_register_operand" "Up")]
9128 VSTRWQ_F))
9129 ]
9130 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
9131{
9132 rtx ops[2];
9133 int regno = REGNO (operands[1]);
9134 ops[1] = gen_rtx_REG (TImode, regno);
9135 ops[0] = operands[0];
9136 output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
9137 return "";
9138}
9139 [(set_attr "length" "8")])
9140
9141;;
9142;; [vstrwq_p_s vstrwq_p_u]
9143;;
9144(define_insn "mve_vstrwq_p_<supf>v4si"
9145 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9146 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
9147 (match_operand:HI 2 "vpr_register_operand" "Up")]
9148 VSTRWQ))
9149 ]
9150 "TARGET_HAVE_MVE"
9151{
9152 rtx ops[2];
9153 int regno = REGNO (operands[1]);
9154 ops[1] = gen_rtx_REG (TImode, regno);
9155 ops[0] = operands[0];
9156 output_asm_insn ("vpst\n\tvstrwt.32\t%q1, %E0",ops);
9157 return "";
9158}
9159 [(set_attr "length" "8")])
9160
9161;;
9162;; [vstrwq_s vstrwq_u]
9163;;
9164(define_insn "mve_vstrwq_<supf>v4si"
9165 [(set (match_operand:V4SI 0 "memory_operand" "=Us")
9166 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
9167 VSTRWQ))
9168 ]
9169 "TARGET_HAVE_MVE"
9170{
9171 rtx ops[2];
9172 int regno = REGNO (operands[1]);
9173 ops[1] = gen_rtx_REG (TImode, regno);
9174 ops[0] = operands[0];
9175 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
9176 return "";
9177}
9178 [(set_attr "length" "4")])
9179
9180(define_expand "mve_vst1q_f<mode>"
9181 [(match_operand:<MVE_CNVT> 0 "memory_operand")
9182 (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
9183 ]
9184 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
9185{
9186 emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
9187 DONE;
9188})
9189
9190(define_expand "mve_vst1q_<supf><mode>"
9191 [(match_operand:MVE_2 0 "memory_operand")
9192 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
9193 ]
9194 "TARGET_HAVE_MVE"
9195{
9196 emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
9197 DONE;
9198})
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