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63c8f7d6 SP |
1 | ;; Arm M-profile Vector Extension Machine Description |
2 | ;; Copyright (C) 2019-2020 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but | |
12 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | ;; General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
63c8f7d6 | 20 | (define_insn "*mve_mov<mode>" |
d91524d5 SP |
21 | [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Ux,w") |
22 | (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Uxi,r,Dm,w,Ul"))] | |
63c8f7d6 SP |
23 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" |
24 | { | |
25 | if (which_alternative == 3 || which_alternative == 6) | |
26 | { | |
27 | int width, is_valid; | |
28 | static char templ[40]; | |
29 | ||
30 | is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode, | |
31 | &operands[1], &width); | |
32 | ||
33 | gcc_assert (is_valid != 0); | |
34 | ||
35 | if (width == 0) | |
36 | return "vmov.f32\t%q0, %1 @ <mode>"; | |
37 | else | |
38 | sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width); | |
39 | return templ; | |
40 | } | |
d91524d5 SP |
41 | |
42 | if (which_alternative == 4 || which_alternative == 7) | |
43 | { | |
44 | rtx ops[2]; | |
45 | int regno = (which_alternative == 7) | |
46 | ? REGNO (operands[1]) : REGNO (operands[0]); | |
47 | ||
48 | ops[0] = operands[0]; | |
49 | ops[1] = operands[1]; | |
50 | if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode) | |
51 | { | |
52 | if (which_alternative == 7) | |
53 | { | |
54 | ops[1] = gen_rtx_REG (DImode, regno); | |
55 | output_asm_insn ("vstr.64\t%P1, %E0",ops); | |
56 | } | |
57 | else | |
58 | { | |
59 | ops[0] = gen_rtx_REG (DImode, regno); | |
60 | output_asm_insn ("vldr.64\t%P0, %E1",ops); | |
61 | } | |
62 | } | |
63 | else if (<MODE>mode == TImode) | |
64 | { | |
65 | if (which_alternative == 7) | |
66 | output_asm_insn ("vstr.64\t%q1, %E0",ops); | |
67 | else | |
68 | output_asm_insn ("vldr.64\t%q0, %E1",ops); | |
69 | } | |
70 | else | |
71 | { | |
72 | if (which_alternative == 7) | |
73 | { | |
74 | ops[1] = gen_rtx_REG (TImode, regno); | |
75 | output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0",ops); | |
76 | } | |
77 | else | |
78 | { | |
79 | ops[0] = gen_rtx_REG (TImode, regno); | |
80 | output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1",ops); | |
81 | } | |
82 | } | |
83 | return ""; | |
84 | } | |
63c8f7d6 SP |
85 | switch (which_alternative) |
86 | { | |
87 | case 0: | |
88 | return "vmov\t%q0, %q1"; | |
89 | case 1: | |
90 | return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1"; | |
91 | case 2: | |
92 | return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1"; | |
63c8f7d6 | 93 | case 5: |
0efe7d87 | 94 | return output_move_quad (operands); |
d91524d5 SP |
95 | case 8: |
96 | return output_move_neon (operands); | |
63c8f7d6 SP |
97 | default: |
98 | gcc_unreachable (); | |
99 | return ""; | |
100 | } | |
101 | } | |
d91524d5 SP |
102 | [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store,mve_load") |
103 | (set_attr "length" "4,8,8,4,8,8,4,4,4") | |
104 | (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*") | |
105 | (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")]) | |
63c8f7d6 SP |
106 | |
107 | (define_insn "*mve_mov<mode>" | |
108 | [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w") | |
109 | (vec_duplicate:MVE_types | |
110 | (match_operand:SI 1 "nonmemory_operand" "r,i")))] | |
111 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
112 | { | |
113 | if (which_alternative == 0) | |
114 | return "vdup.<V_sz_elem>\t%q0, %1"; | |
115 | return "vmov.<V_sz_elem>\t%q0, %1"; | |
116 | } | |
117 | [(set_attr "length" "4,4") | |
118 | (set_attr "type" "mve_move,mve_move")]) | |
14782c81 SP |
119 | |
120 | ;; | |
121 | ;; [vst4q]) | |
122 | ;; | |
123 | (define_insn "mve_vst4q<mode>" | |
124 | [(set (match_operand:XI 0 "neon_struct_operand" "=Um") | |
125 | (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") | |
126 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
127 | VST4Q)) | |
128 | ] | |
129 | "TARGET_HAVE_MVE" | |
130 | { | |
131 | rtx ops[6]; | |
132 | int regno = REGNO (operands[1]); | |
133 | ops[0] = gen_rtx_REG (TImode, regno); | |
134 | ops[1] = gen_rtx_REG (TImode, regno+4); | |
135 | ops[2] = gen_rtx_REG (TImode, regno+8); | |
136 | ops[3] = gen_rtx_REG (TImode, regno+12); | |
137 | rtx reg = operands[0]; | |
138 | while (reg && !REG_P (reg)) | |
139 | reg = XEXP (reg, 0); | |
140 | gcc_assert (REG_P (reg)); | |
141 | ops[4] = reg; | |
142 | ops[5] = operands[0]; | |
143 | /* Here in first three instructions data is stored to ops[4]'s location but | |
144 | in the fourth instruction data is stored to operands[0], this is to | |
145 | support the writeback. */ | |
146 | output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
147 | "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
148 | "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
149 | "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); | |
150 | return ""; | |
151 | } | |
152 | [(set_attr "length" "16")]) | |
a50f6abf | 153 | |
e3678b44 SP |
154 | ;; |
155 | ;; [vrndq_m_f]) | |
156 | ;; | |
157 | (define_insn "mve_vrndq_m_f<mode>" | |
158 | [ | |
159 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
160 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
161 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
162 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
163 | VRNDQ_M_F)) | |
164 | ] | |
165 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
166 | "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2" | |
167 | [(set_attr "type" "mve_move") | |
168 | (set_attr "length""8")]) | |
169 | ||
a50f6abf SP |
170 | ;; |
171 | ;; [vrndxq_f]) | |
172 | ;; | |
173 | (define_insn "mve_vrndxq_f<mode>" | |
174 | [ | |
175 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
176 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
177 | VRNDXQ_F)) | |
178 | ] | |
179 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
180 | "vrintx.f%#<V_sz_elem> %q0, %q1" | |
181 | [(set_attr "type" "mve_move") | |
182 | ]) | |
183 | ||
184 | ;; | |
185 | ;; [vrndq_f]) | |
186 | ;; | |
187 | (define_insn "mve_vrndq_f<mode>" | |
188 | [ | |
189 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
190 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
191 | VRNDQ_F)) | |
192 | ] | |
193 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
194 | "vrintz.f%#<V_sz_elem> %q0, %q1" | |
195 | [(set_attr "type" "mve_move") | |
196 | ]) | |
197 | ||
198 | ;; | |
199 | ;; [vrndpq_f]) | |
200 | ;; | |
201 | (define_insn "mve_vrndpq_f<mode>" | |
202 | [ | |
203 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
204 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
205 | VRNDPQ_F)) | |
206 | ] | |
207 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
208 | "vrintp.f%#<V_sz_elem> %q0, %q1" | |
209 | [(set_attr "type" "mve_move") | |
210 | ]) | |
211 | ||
212 | ;; | |
213 | ;; [vrndnq_f]) | |
214 | ;; | |
215 | (define_insn "mve_vrndnq_f<mode>" | |
216 | [ | |
217 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
218 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
219 | VRNDNQ_F)) | |
220 | ] | |
221 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
222 | "vrintn.f%#<V_sz_elem> %q0, %q1" | |
223 | [(set_attr "type" "mve_move") | |
224 | ]) | |
225 | ||
226 | ;; | |
227 | ;; [vrndmq_f]) | |
228 | ;; | |
229 | (define_insn "mve_vrndmq_f<mode>" | |
230 | [ | |
231 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
232 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
233 | VRNDMQ_F)) | |
234 | ] | |
235 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
236 | "vrintm.f%#<V_sz_elem> %q0, %q1" | |
237 | [(set_attr "type" "mve_move") | |
238 | ]) | |
239 | ||
240 | ;; | |
241 | ;; [vrndaq_f]) | |
242 | ;; | |
243 | (define_insn "mve_vrndaq_f<mode>" | |
244 | [ | |
245 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
246 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
247 | VRNDAQ_F)) | |
248 | ] | |
249 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
250 | "vrinta.f%#<V_sz_elem> %q0, %q1" | |
251 | [(set_attr "type" "mve_move") | |
252 | ]) | |
253 | ||
254 | ;; | |
255 | ;; [vrev64q_f]) | |
256 | ;; | |
257 | (define_insn "mve_vrev64q_f<mode>" | |
258 | [ | |
6debbff6 | 259 | (set (match_operand:MVE_0 0 "s_register_operand" "=&w") |
a50f6abf SP |
260 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] |
261 | VREV64Q_F)) | |
262 | ] | |
263 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
264 | "vrev64.%#<V_sz_elem> %q0, %q1" | |
265 | [(set_attr "type" "mve_move") | |
266 | ]) | |
267 | ||
268 | ;; | |
269 | ;; [vnegq_f]) | |
270 | ;; | |
271 | (define_insn "mve_vnegq_f<mode>" | |
272 | [ | |
273 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
274 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
275 | VNEGQ_F)) | |
276 | ] | |
277 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
278 | "vneg.f%#<V_sz_elem> %q0, %q1" | |
279 | [(set_attr "type" "mve_move") | |
280 | ]) | |
281 | ||
282 | ;; | |
283 | ;; [vdupq_n_f]) | |
284 | ;; | |
285 | (define_insn "mve_vdupq_n_f<mode>" | |
286 | [ | |
287 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
288 | (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
289 | VDUPQ_N_F)) | |
290 | ] | |
291 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
292 | "vdup.%#<V_sz_elem> %q0, %1" | |
293 | [(set_attr "type" "mve_move") | |
294 | ]) | |
295 | ||
296 | ;; | |
297 | ;; [vabsq_f]) | |
298 | ;; | |
299 | (define_insn "mve_vabsq_f<mode>" | |
300 | [ | |
301 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
302 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
303 | VABSQ_F)) | |
304 | ] | |
305 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
306 | "vabs.f%#<V_sz_elem> %q0, %q1" | |
307 | [(set_attr "type" "mve_move") | |
308 | ]) | |
309 | ||
310 | ;; | |
311 | ;; [vrev32q_f]) | |
312 | ;; | |
313 | (define_insn "mve_vrev32q_fv8hf" | |
314 | [ | |
315 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
316 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
317 | VREV32Q_F)) | |
318 | ] | |
319 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
320 | "vrev32.16 %q0, %q1" | |
321 | [(set_attr "type" "mve_move") | |
322 | ]) | |
323 | ;; | |
324 | ;; [vcvttq_f32_f16]) | |
325 | ;; | |
326 | (define_insn "mve_vcvttq_f32_f16v4sf" | |
327 | [ | |
328 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
329 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
330 | VCVTTQ_F32_F16)) | |
331 | ] | |
332 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
333 | "vcvtt.f32.f16 %q0, %q1" | |
334 | [(set_attr "type" "mve_move") | |
335 | ]) | |
336 | ||
337 | ;; | |
338 | ;; [vcvtbq_f32_f16]) | |
339 | ;; | |
340 | (define_insn "mve_vcvtbq_f32_f16v4sf" | |
341 | [ | |
342 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
343 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
344 | VCVTBQ_F32_F16)) | |
345 | ] | |
346 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
347 | "vcvtb.f32.f16 %q0, %q1" | |
348 | [(set_attr "type" "mve_move") | |
349 | ]) | |
350 | ||
351 | ;; | |
352 | ;; [vcvtq_to_f_s, vcvtq_to_f_u]) | |
353 | ;; | |
354 | (define_insn "mve_vcvtq_to_f_<supf><mode>" | |
355 | [ | |
356 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
357 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
358 | VCVTQ_TO_F)) | |
359 | ] | |
360 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
361 | "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1" | |
362 | [(set_attr "type" "mve_move") | |
363 | ]) | |
5db0eb95 SP |
364 | |
365 | ;; | |
366 | ;; [vrev64q_u, vrev64q_s]) | |
367 | ;; | |
368 | (define_insn "mve_vrev64q_<supf><mode>" | |
369 | [ | |
6debbff6 | 370 | (set (match_operand:MVE_2 0 "s_register_operand" "=&w") |
5db0eb95 SP |
371 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] |
372 | VREV64Q)) | |
373 | ] | |
374 | "TARGET_HAVE_MVE" | |
375 | "vrev64.%#<V_sz_elem> %q0, %q1" | |
376 | [(set_attr "type" "mve_move") | |
377 | ]) | |
378 | ||
379 | ;; | |
380 | ;; [vcvtq_from_f_s, vcvtq_from_f_u]) | |
381 | ;; | |
382 | (define_insn "mve_vcvtq_from_f_<supf><mode>" | |
383 | [ | |
384 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
385 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
386 | VCVTQ_FROM_F)) | |
387 | ] | |
388 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
389 | "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
390 | [(set_attr "type" "mve_move") | |
391 | ]) | |
6df4618c SP |
392 | ;; [vqnegq_s]) |
393 | ;; | |
394 | (define_insn "mve_vqnegq_s<mode>" | |
395 | [ | |
396 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
397 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
398 | VQNEGQ_S)) | |
399 | ] | |
400 | "TARGET_HAVE_MVE" | |
401 | "vqneg.s%#<V_sz_elem> %q0, %q1" | |
402 | [(set_attr "type" "mve_move") | |
403 | ]) | |
404 | ||
405 | ;; | |
406 | ;; [vqabsq_s]) | |
407 | ;; | |
408 | (define_insn "mve_vqabsq_s<mode>" | |
409 | [ | |
410 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
411 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
412 | VQABSQ_S)) | |
413 | ] | |
414 | "TARGET_HAVE_MVE" | |
415 | "vqabs.s%#<V_sz_elem> %q0, %q1" | |
416 | [(set_attr "type" "mve_move") | |
417 | ]) | |
418 | ||
419 | ;; | |
420 | ;; [vnegq_s]) | |
421 | ;; | |
422 | (define_insn "mve_vnegq_s<mode>" | |
423 | [ | |
424 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
425 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
426 | VNEGQ_S)) | |
427 | ] | |
428 | "TARGET_HAVE_MVE" | |
429 | "vneg.s%#<V_sz_elem> %q0, %q1" | |
430 | [(set_attr "type" "mve_move") | |
431 | ]) | |
432 | ||
433 | ;; | |
434 | ;; [vmvnq_u, vmvnq_s]) | |
435 | ;; | |
436 | (define_insn "mve_vmvnq_<supf><mode>" | |
437 | [ | |
438 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
439 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
440 | VMVNQ)) | |
441 | ] | |
442 | "TARGET_HAVE_MVE" | |
443 | "vmvn %q0, %q1" | |
444 | [(set_attr "type" "mve_move") | |
445 | ]) | |
446 | ||
447 | ;; | |
448 | ;; [vdupq_n_u, vdupq_n_s]) | |
449 | ;; | |
450 | (define_insn "mve_vdupq_n_<supf><mode>" | |
451 | [ | |
452 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
453 | (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
454 | VDUPQ_N)) | |
455 | ] | |
456 | "TARGET_HAVE_MVE" | |
457 | "vdup.%#<V_sz_elem> %q0, %1" | |
458 | [(set_attr "type" "mve_move") | |
459 | ]) | |
460 | ||
461 | ;; | |
462 | ;; [vclzq_u, vclzq_s]) | |
463 | ;; | |
464 | (define_insn "mve_vclzq_<supf><mode>" | |
465 | [ | |
466 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
467 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
468 | VCLZQ)) | |
469 | ] | |
470 | "TARGET_HAVE_MVE" | |
471 | "vclz.i%#<V_sz_elem> %q0, %q1" | |
472 | [(set_attr "type" "mve_move") | |
473 | ]) | |
474 | ||
475 | ;; | |
476 | ;; [vclsq_s]) | |
477 | ;; | |
478 | (define_insn "mve_vclsq_s<mode>" | |
479 | [ | |
480 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
481 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
482 | VCLSQ_S)) | |
483 | ] | |
484 | "TARGET_HAVE_MVE" | |
485 | "vcls.s%#<V_sz_elem> %q0, %q1" | |
486 | [(set_attr "type" "mve_move") | |
487 | ]) | |
488 | ||
489 | ;; | |
490 | ;; [vaddvq_s, vaddvq_u]) | |
491 | ;; | |
492 | (define_insn "mve_vaddvq_<supf><mode>" | |
493 | [ | |
3d537943 | 494 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
6df4618c SP |
495 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] |
496 | VADDVQ)) | |
497 | ] | |
498 | "TARGET_HAVE_MVE" | |
499 | "vaddv.<supf>%#<V_sz_elem>\t%0, %q1" | |
500 | [(set_attr "type" "mve_move") | |
501 | ]) | |
502 | ||
503 | ;; | |
504 | ;; [vabsq_s]) | |
505 | ;; | |
506 | (define_insn "mve_vabsq_s<mode>" | |
507 | [ | |
508 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
509 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
510 | VABSQ_S)) | |
511 | ] | |
512 | "TARGET_HAVE_MVE" | |
513 | "vabs.s%#<V_sz_elem>\t%q0, %q1" | |
514 | [(set_attr "type" "mve_move") | |
515 | ]) | |
516 | ||
517 | ;; | |
518 | ;; [vrev32q_u, vrev32q_s]) | |
519 | ;; | |
520 | (define_insn "mve_vrev32q_<supf><mode>" | |
521 | [ | |
522 | (set (match_operand:MVE_3 0 "s_register_operand" "=w") | |
523 | (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
524 | VREV32Q)) | |
525 | ] | |
526 | "TARGET_HAVE_MVE" | |
527 | "vrev32.%#<V_sz_elem>\t%q0, %q1" | |
528 | [(set_attr "type" "mve_move") | |
529 | ]) | |
530 | ||
531 | ;; | |
532 | ;; [vmovltq_u, vmovltq_s]) | |
533 | ;; | |
534 | (define_insn "mve_vmovltq_<supf><mode>" | |
535 | [ | |
536 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
537 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
538 | VMOVLTQ)) | |
539 | ] | |
540 | "TARGET_HAVE_MVE" | |
541 | "vmovlt.<supf>%#<V_sz_elem> %q0, %q1" | |
542 | [(set_attr "type" "mve_move") | |
543 | ]) | |
544 | ||
545 | ;; | |
546 | ;; [vmovlbq_s, vmovlbq_u]) | |
547 | ;; | |
548 | (define_insn "mve_vmovlbq_<supf><mode>" | |
549 | [ | |
550 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
551 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
552 | VMOVLBQ)) | |
553 | ] | |
554 | "TARGET_HAVE_MVE" | |
555 | "vmovlb.<supf>%#<V_sz_elem> %q0, %q1" | |
556 | [(set_attr "type" "mve_move") | |
557 | ]) | |
558 | ||
559 | ;; | |
560 | ;; [vcvtpq_s, vcvtpq_u]) | |
561 | ;; | |
562 | (define_insn "mve_vcvtpq_<supf><mode>" | |
563 | [ | |
564 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
565 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
566 | VCVTPQ)) | |
567 | ] | |
568 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
569 | "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
570 | [(set_attr "type" "mve_move") | |
571 | ]) | |
572 | ||
573 | ;; | |
574 | ;; [vcvtnq_s, vcvtnq_u]) | |
575 | ;; | |
576 | (define_insn "mve_vcvtnq_<supf><mode>" | |
577 | [ | |
578 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
579 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
580 | VCVTNQ)) | |
581 | ] | |
582 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
583 | "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
584 | [(set_attr "type" "mve_move") | |
585 | ]) | |
586 | ||
587 | ;; | |
588 | ;; [vcvtmq_s, vcvtmq_u]) | |
589 | ;; | |
590 | (define_insn "mve_vcvtmq_<supf><mode>" | |
591 | [ | |
592 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
593 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
594 | VCVTMQ)) | |
595 | ] | |
596 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
597 | "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
598 | [(set_attr "type" "mve_move") | |
599 | ]) | |
600 | ||
601 | ;; | |
602 | ;; [vcvtaq_u, vcvtaq_s]) | |
603 | ;; | |
604 | (define_insn "mve_vcvtaq_<supf><mode>" | |
605 | [ | |
606 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
607 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
608 | VCVTAQ)) | |
609 | ] | |
610 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
611 | "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
612 | [(set_attr "type" "mve_move") | |
613 | ]) | |
5db0eb95 SP |
614 | |
615 | ;; | |
616 | ;; [vmvnq_n_u, vmvnq_n_s]) | |
617 | ;; | |
618 | (define_insn "mve_vmvnq_n_<supf><mode>" | |
619 | [ | |
620 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
621 | (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")] | |
622 | VMVNQ_N)) | |
623 | ] | |
624 | "TARGET_HAVE_MVE" | |
625 | "vmvn.i%#<V_sz_elem> %q0, %1" | |
626 | [(set_attr "type" "mve_move") | |
627 | ]) | |
6df4618c SP |
628 | |
629 | ;; | |
630 | ;; [vrev16q_u, vrev16q_s]) | |
631 | ;; | |
632 | (define_insn "mve_vrev16q_<supf>v16qi" | |
633 | [ | |
634 | (set (match_operand:V16QI 0 "s_register_operand" "=w") | |
635 | (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] | |
636 | VREV16Q)) | |
637 | ] | |
638 | "TARGET_HAVE_MVE" | |
639 | "vrev16.8 %q0, %q1" | |
640 | [(set_attr "type" "mve_move") | |
641 | ]) | |
642 | ||
643 | ;; | |
644 | ;; [vaddlvq_s vaddlvq_u]) | |
645 | ;; | |
646 | (define_insn "mve_vaddlvq_<supf>v4si" | |
647 | [ | |
648 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
649 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] | |
650 | VADDLVQ)) | |
651 | ] | |
652 | "TARGET_HAVE_MVE" | |
653 | "vaddlv.<supf>32 %Q0, %R0, %q1" | |
654 | [(set_attr "type" "mve_move") | |
655 | ]) | |
a475f153 SP |
656 | |
657 | ;; | |
658 | ;; [vctp8q vctp16q vctp32q vctp64q]) | |
659 | ;; | |
660 | (define_insn "mve_vctp<mode1>qhi" | |
661 | [ | |
662 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
663 | (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")] | |
664 | VCTPQ)) | |
665 | ] | |
666 | "TARGET_HAVE_MVE" | |
667 | "vctp.<mode1> %1" | |
668 | [(set_attr "type" "mve_move") | |
669 | ]) | |
670 | ||
671 | ;; | |
672 | ;; [vpnot]) | |
673 | ;; | |
674 | (define_insn "mve_vpnothi" | |
675 | [ | |
676 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
677 | (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")] | |
678 | VPNOT)) | |
679 | ] | |
680 | "TARGET_HAVE_MVE" | |
681 | "vpnot" | |
682 | [(set_attr "type" "mve_move") | |
683 | ]) | |
4be8cf77 SP |
684 | |
685 | ;; | |
686 | ;; [vsubq_n_f]) | |
687 | ;; | |
688 | (define_insn "mve_vsubq_n_f<mode>" | |
689 | [ | |
690 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
691 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
692 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
693 | VSUBQ_N_F)) | |
694 | ] | |
695 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
696 | "vsub.f<V_sz_elem> %q0, %q1, %2" | |
697 | [(set_attr "type" "mve_move") | |
698 | ]) | |
699 | ||
700 | ;; | |
701 | ;; [vbrsrq_n_f]) | |
702 | ;; | |
703 | (define_insn "mve_vbrsrq_n_f<mode>" | |
704 | [ | |
705 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
706 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
707 | (match_operand:SI 2 "s_register_operand" "r")] | |
708 | VBRSRQ_N_F)) | |
709 | ] | |
710 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
711 | "vbrsr.<V_sz_elem> %q0, %q1, %2" | |
712 | [(set_attr "type" "mve_move") | |
713 | ]) | |
714 | ||
715 | ;; | |
716 | ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) | |
717 | ;; | |
718 | (define_insn "mve_vcvtq_n_to_f_<supf><mode>" | |
719 | [ | |
720 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
721 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
d2ce75fe | 722 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] |
4be8cf77 SP |
723 | VCVTQ_N_TO_F)) |
724 | ] | |
725 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
726 | "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2" | |
727 | [(set_attr "type" "mve_move") | |
728 | ]) | |
729 | ||
730 | ;; [vcreateq_f]) | |
731 | ;; | |
732 | (define_insn "mve_vcreateq_f<mode>" | |
733 | [ | |
734 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
735 | (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") | |
736 | (match_operand:DI 2 "s_register_operand" "r")] | |
737 | VCREATEQ_F)) | |
738 | ] | |
739 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
740 | "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" | |
741 | [(set_attr "type" "mve_move") | |
742 | (set_attr "length""8")]) | |
f166a8cd SP |
743 | |
744 | ;; | |
745 | ;; [vcreateq_u, vcreateq_s]) | |
746 | ;; | |
747 | (define_insn "mve_vcreateq_<supf><mode>" | |
748 | [ | |
749 | (set (match_operand:MVE_1 0 "s_register_operand" "=w") | |
750 | (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") | |
751 | (match_operand:DI 2 "s_register_operand" "r")] | |
752 | VCREATEQ)) | |
753 | ] | |
754 | "TARGET_HAVE_MVE" | |
755 | "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" | |
756 | [(set_attr "type" "mve_move") | |
757 | (set_attr "length""8")]) | |
758 | ||
759 | ;; | |
760 | ;; [vshrq_n_s, vshrq_n_u]) | |
761 | ;; | |
762 | (define_insn "mve_vshrq_n_<supf><mode>" | |
763 | [ | |
764 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
765 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
766 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] | |
767 | VSHRQ_N)) | |
768 | ] | |
769 | "TARGET_HAVE_MVE" | |
770 | "vshr.<supf><V_sz_elem>\t%q0, %q1, %2" | |
771 | [(set_attr "type" "mve_move") | |
772 | ]) | |
773 | ||
774 | ;; | |
775 | ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) | |
776 | ;; | |
777 | (define_insn "mve_vcvtq_n_from_f_<supf><mode>" | |
778 | [ | |
779 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
780 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
d2ce75fe | 781 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] |
f166a8cd SP |
782 | VCVTQ_N_FROM_F)) |
783 | ] | |
784 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
785 | "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2" | |
786 | [(set_attr "type" "mve_move") | |
787 | ]) | |
d71dba7b SP |
788 | |
789 | ;; | |
790 | ;; [vaddlvq_p_s]) | |
791 | ;; | |
792 | (define_insn "mve_vaddlvq_p_<supf>v4si" | |
793 | [ | |
794 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
795 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
796 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
797 | VADDLVQ_P)) | |
798 | ] | |
799 | "TARGET_HAVE_MVE" | |
800 | "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1" | |
801 | [(set_attr "type" "mve_move") | |
802 | (set_attr "length""8")]) | |
803 | ||
804 | ;; | |
805 | ;; [vcmpneq_u, vcmpneq_s]) | |
806 | ;; | |
807 | (define_insn "mve_vcmpneq_<supf><mode>" | |
808 | [ | |
809 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
810 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
811 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
812 | VCMPNEQ)) | |
813 | ] | |
814 | "TARGET_HAVE_MVE" | |
815 | "vcmp.i%#<V_sz_elem> ne, %q1, %q2" | |
816 | [(set_attr "type" "mve_move") | |
817 | ]) | |
818 | ||
819 | ;; | |
820 | ;; [vshlq_s, vshlq_u]) | |
821 | ;; | |
822 | (define_insn "mve_vshlq_<supf><mode>" | |
823 | [ | |
824 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
825 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
826 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
827 | VSHLQ)) | |
828 | ] | |
829 | "TARGET_HAVE_MVE" | |
830 | "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
831 | [(set_attr "type" "mve_move") | |
832 | ]) | |
33203b4c SP |
833 | |
834 | ;; | |
835 | ;; [vabdq_s, vabdq_u]) | |
836 | ;; | |
837 | (define_insn "mve_vabdq_<supf><mode>" | |
838 | [ | |
839 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
840 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
841 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
842 | VABDQ)) | |
843 | ] | |
844 | "TARGET_HAVE_MVE" | |
845 | "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2" | |
846 | [(set_attr "type" "mve_move") | |
847 | ]) | |
848 | ||
849 | ;; | |
850 | ;; [vaddq_n_s, vaddq_n_u]) | |
851 | ;; | |
852 | (define_insn "mve_vaddq_n_<supf><mode>" | |
853 | [ | |
854 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
855 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
856 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
857 | VADDQ_N)) | |
858 | ] | |
859 | "TARGET_HAVE_MVE" | |
860 | "vadd.i%#<V_sz_elem> %q0, %q1, %2" | |
861 | [(set_attr "type" "mve_move") | |
862 | ]) | |
863 | ||
864 | ;; | |
865 | ;; [vaddvaq_s, vaddvaq_u]) | |
866 | ;; | |
867 | (define_insn "mve_vaddvaq_<supf><mode>" | |
868 | [ | |
3d537943 | 869 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
870 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
871 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
872 | VADDVAQ)) | |
873 | ] | |
874 | "TARGET_HAVE_MVE" | |
875 | "vaddva.<supf>%#<V_sz_elem> %0, %q2" | |
876 | [(set_attr "type" "mve_move") | |
877 | ]) | |
878 | ||
879 | ;; | |
880 | ;; [vaddvq_p_u, vaddvq_p_s]) | |
881 | ;; | |
882 | (define_insn "mve_vaddvq_p_<supf><mode>" | |
883 | [ | |
3d537943 | 884 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
885 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
886 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
887 | VADDVQ_P)) | |
888 | ] | |
889 | "TARGET_HAVE_MVE" | |
890 | "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1" | |
891 | [(set_attr "type" "mve_move") | |
892 | (set_attr "length""8")]) | |
893 | ||
894 | ;; | |
895 | ;; [vandq_u, vandq_s]) | |
896 | ;; | |
897 | (define_insn "mve_vandq_<supf><mode>" | |
898 | [ | |
899 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
900 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
901 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
902 | VANDQ)) | |
903 | ] | |
904 | "TARGET_HAVE_MVE" | |
905 | "vand %q0, %q1, %q2" | |
906 | [(set_attr "type" "mve_move") | |
907 | ]) | |
908 | ||
909 | ;; | |
910 | ;; [vbicq_s, vbicq_u]) | |
911 | ;; | |
912 | (define_insn "mve_vbicq_<supf><mode>" | |
913 | [ | |
914 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
915 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
916 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
917 | VBICQ)) | |
918 | ] | |
919 | "TARGET_HAVE_MVE" | |
920 | "vbic %q0, %q1, %q2" | |
921 | [(set_attr "type" "mve_move") | |
922 | ]) | |
923 | ||
924 | ;; | |
925 | ;; [vbrsrq_n_u, vbrsrq_n_s]) | |
926 | ;; | |
927 | (define_insn "mve_vbrsrq_n_<supf><mode>" | |
928 | [ | |
929 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
930 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
931 | (match_operand:SI 2 "s_register_operand" "r")] | |
932 | VBRSRQ_N)) | |
933 | ] | |
934 | "TARGET_HAVE_MVE" | |
935 | "vbrsr.%#<V_sz_elem> %q0, %q1, %2" | |
936 | [(set_attr "type" "mve_move") | |
937 | ]) | |
938 | ||
939 | ;; | |
940 | ;; [vcaddq_rot270_s, vcaddq_rot270_u]) | |
941 | ;; | |
942 | (define_insn "mve_vcaddq_rot270_<supf><mode>" | |
943 | [ | |
6debbff6 | 944 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
945 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
946 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
947 | VCADDQ_ROT270)) | |
948 | ] | |
949 | "TARGET_HAVE_MVE" | |
950 | "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270" | |
951 | [(set_attr "type" "mve_move") | |
952 | ]) | |
953 | ||
954 | ;; | |
955 | ;; [vcaddq_rot90_u, vcaddq_rot90_s]) | |
956 | ;; | |
957 | (define_insn "mve_vcaddq_rot90_<supf><mode>" | |
958 | [ | |
6debbff6 | 959 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
960 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
961 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
962 | VCADDQ_ROT90)) | |
963 | ] | |
964 | "TARGET_HAVE_MVE" | |
965 | "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90" | |
966 | [(set_attr "type" "mve_move") | |
967 | ]) | |
968 | ||
969 | ;; | |
970 | ;; [vcmpcsq_n_u]) | |
971 | ;; | |
972 | (define_insn "mve_vcmpcsq_n_u<mode>" | |
973 | [ | |
974 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
975 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
976 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
977 | VCMPCSQ_N_U)) | |
978 | ] | |
979 | "TARGET_HAVE_MVE" | |
980 | "vcmp.u%#<V_sz_elem> cs, %q1, %2" | |
981 | [(set_attr "type" "mve_move") | |
982 | ]) | |
983 | ||
984 | ;; | |
985 | ;; [vcmpcsq_u]) | |
986 | ;; | |
987 | (define_insn "mve_vcmpcsq_u<mode>" | |
988 | [ | |
989 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
990 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
991 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
992 | VCMPCSQ_U)) | |
993 | ] | |
994 | "TARGET_HAVE_MVE" | |
995 | "vcmp.u%#<V_sz_elem> cs, %q1, %q2" | |
996 | [(set_attr "type" "mve_move") | |
997 | ]) | |
998 | ||
999 | ;; | |
1000 | ;; [vcmpeqq_n_s, vcmpeqq_n_u]) | |
1001 | ;; | |
1002 | (define_insn "mve_vcmpeqq_n_<supf><mode>" | |
1003 | [ | |
1004 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1005 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1006 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1007 | VCMPEQQ_N)) | |
1008 | ] | |
1009 | "TARGET_HAVE_MVE" | |
1010 | "vcmp.i%#<V_sz_elem> eq, %q1, %2" | |
1011 | [(set_attr "type" "mve_move") | |
1012 | ]) | |
1013 | ||
1014 | ;; | |
1015 | ;; [vcmpeqq_u, vcmpeqq_s]) | |
1016 | ;; | |
1017 | (define_insn "mve_vcmpeqq_<supf><mode>" | |
1018 | [ | |
1019 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1020 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1021 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1022 | VCMPEQQ)) | |
1023 | ] | |
1024 | "TARGET_HAVE_MVE" | |
1025 | "vcmp.i%#<V_sz_elem> eq, %q1, %q2" | |
1026 | [(set_attr "type" "mve_move") | |
1027 | ]) | |
1028 | ||
1029 | ;; | |
1030 | ;; [vcmpgeq_n_s]) | |
1031 | ;; | |
1032 | (define_insn "mve_vcmpgeq_n_s<mode>" | |
1033 | [ | |
1034 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1035 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1036 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1037 | VCMPGEQ_N_S)) | |
1038 | ] | |
1039 | "TARGET_HAVE_MVE" | |
1040 | "vcmp.s%#<V_sz_elem> ge, %q1, %2" | |
1041 | [(set_attr "type" "mve_move") | |
1042 | ]) | |
1043 | ||
1044 | ;; | |
1045 | ;; [vcmpgeq_s]) | |
1046 | ;; | |
1047 | (define_insn "mve_vcmpgeq_s<mode>" | |
1048 | [ | |
1049 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1050 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1051 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1052 | VCMPGEQ_S)) | |
1053 | ] | |
1054 | "TARGET_HAVE_MVE" | |
1055 | "vcmp.s%#<V_sz_elem> ge, %q1, %q2" | |
1056 | [(set_attr "type" "mve_move") | |
1057 | ]) | |
1058 | ||
1059 | ;; | |
1060 | ;; [vcmpgtq_n_s]) | |
1061 | ;; | |
1062 | (define_insn "mve_vcmpgtq_n_s<mode>" | |
1063 | [ | |
1064 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1065 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1066 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1067 | VCMPGTQ_N_S)) | |
1068 | ] | |
1069 | "TARGET_HAVE_MVE" | |
1070 | "vcmp.s%#<V_sz_elem> gt, %q1, %2" | |
1071 | [(set_attr "type" "mve_move") | |
1072 | ]) | |
1073 | ||
1074 | ;; | |
1075 | ;; [vcmpgtq_s]) | |
1076 | ;; | |
1077 | (define_insn "mve_vcmpgtq_s<mode>" | |
1078 | [ | |
1079 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1080 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1081 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1082 | VCMPGTQ_S)) | |
1083 | ] | |
1084 | "TARGET_HAVE_MVE" | |
1085 | "vcmp.s%#<V_sz_elem> gt, %q1, %q2" | |
1086 | [(set_attr "type" "mve_move") | |
1087 | ]) | |
1088 | ||
1089 | ;; | |
1090 | ;; [vcmphiq_n_u]) | |
1091 | ;; | |
1092 | (define_insn "mve_vcmphiq_n_u<mode>" | |
1093 | [ | |
1094 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1095 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1096 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1097 | VCMPHIQ_N_U)) | |
1098 | ] | |
1099 | "TARGET_HAVE_MVE" | |
1100 | "vcmp.u%#<V_sz_elem> hi, %q1, %2" | |
1101 | [(set_attr "type" "mve_move") | |
1102 | ]) | |
1103 | ||
1104 | ;; | |
1105 | ;; [vcmphiq_u]) | |
1106 | ;; | |
1107 | (define_insn "mve_vcmphiq_u<mode>" | |
1108 | [ | |
1109 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1110 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1111 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1112 | VCMPHIQ_U)) | |
1113 | ] | |
1114 | "TARGET_HAVE_MVE" | |
1115 | "vcmp.u%#<V_sz_elem> hi, %q1, %q2" | |
1116 | [(set_attr "type" "mve_move") | |
1117 | ]) | |
1118 | ||
1119 | ;; | |
1120 | ;; [vcmpleq_n_s]) | |
1121 | ;; | |
1122 | (define_insn "mve_vcmpleq_n_s<mode>" | |
1123 | [ | |
1124 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1125 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1126 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1127 | VCMPLEQ_N_S)) | |
1128 | ] | |
1129 | "TARGET_HAVE_MVE" | |
1130 | "vcmp.s%#<V_sz_elem> le, %q1, %2" | |
1131 | [(set_attr "type" "mve_move") | |
1132 | ]) | |
1133 | ||
1134 | ;; | |
1135 | ;; [vcmpleq_s]) | |
1136 | ;; | |
1137 | (define_insn "mve_vcmpleq_s<mode>" | |
1138 | [ | |
1139 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1140 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1141 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1142 | VCMPLEQ_S)) | |
1143 | ] | |
1144 | "TARGET_HAVE_MVE" | |
1145 | "vcmp.s%#<V_sz_elem> le, %q1, %q2" | |
1146 | [(set_attr "type" "mve_move") | |
1147 | ]) | |
1148 | ||
1149 | ;; | |
1150 | ;; [vcmpltq_n_s]) | |
1151 | ;; | |
1152 | (define_insn "mve_vcmpltq_n_s<mode>" | |
1153 | [ | |
1154 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1155 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1156 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1157 | VCMPLTQ_N_S)) | |
1158 | ] | |
1159 | "TARGET_HAVE_MVE" | |
1160 | "vcmp.s%#<V_sz_elem> lt, %q1, %2" | |
1161 | [(set_attr "type" "mve_move") | |
1162 | ]) | |
1163 | ||
1164 | ;; | |
1165 | ;; [vcmpltq_s]) | |
1166 | ;; | |
1167 | (define_insn "mve_vcmpltq_s<mode>" | |
1168 | [ | |
1169 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1170 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1171 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1172 | VCMPLTQ_S)) | |
1173 | ] | |
1174 | "TARGET_HAVE_MVE" | |
1175 | "vcmp.s%#<V_sz_elem> lt, %q1, %q2" | |
1176 | [(set_attr "type" "mve_move") | |
1177 | ]) | |
1178 | ||
1179 | ;; | |
1180 | ;; [vcmpneq_n_u, vcmpneq_n_s]) | |
1181 | ;; | |
1182 | (define_insn "mve_vcmpneq_n_<supf><mode>" | |
1183 | [ | |
1184 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1185 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1186 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1187 | VCMPNEQ_N)) | |
1188 | ] | |
1189 | "TARGET_HAVE_MVE" | |
1190 | "vcmp.i%#<V_sz_elem> ne, %q1, %2" | |
1191 | [(set_attr "type" "mve_move") | |
1192 | ]) | |
1193 | ||
1194 | ;; | |
1195 | ;; [veorq_u, veorq_s]) | |
1196 | ;; | |
1197 | (define_insn "mve_veorq_<supf><mode>" | |
1198 | [ | |
1199 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1200 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1201 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1202 | VEORQ)) | |
1203 | ] | |
1204 | "TARGET_HAVE_MVE" | |
1205 | "veor %q0, %q1, %q2" | |
1206 | [(set_attr "type" "mve_move") | |
1207 | ]) | |
1208 | ||
1209 | ;; | |
1210 | ;; [vhaddq_n_u, vhaddq_n_s]) | |
1211 | ;; | |
1212 | (define_insn "mve_vhaddq_n_<supf><mode>" | |
1213 | [ | |
1214 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1215 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1216 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1217 | VHADDQ_N)) | |
1218 | ] | |
1219 | "TARGET_HAVE_MVE" | |
1220 | "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1221 | [(set_attr "type" "mve_move") | |
1222 | ]) | |
1223 | ||
1224 | ;; | |
1225 | ;; [vhaddq_s, vhaddq_u]) | |
1226 | ;; | |
1227 | (define_insn "mve_vhaddq_<supf><mode>" | |
1228 | [ | |
1229 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1230 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1231 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1232 | VHADDQ)) | |
1233 | ] | |
1234 | "TARGET_HAVE_MVE" | |
1235 | "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1236 | [(set_attr "type" "mve_move") | |
1237 | ]) | |
1238 | ||
1239 | ;; | |
1240 | ;; [vhcaddq_rot270_s]) | |
1241 | ;; | |
1242 | (define_insn "mve_vhcaddq_rot270_s<mode>" | |
1243 | [ | |
6debbff6 | 1244 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1245 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
1246 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1247 | VHCADDQ_ROT270_S)) | |
1248 | ] | |
1249 | "TARGET_HAVE_MVE" | |
1250 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270" | |
1251 | [(set_attr "type" "mve_move") | |
1252 | ]) | |
1253 | ||
1254 | ;; | |
1255 | ;; [vhcaddq_rot90_s]) | |
1256 | ;; | |
1257 | (define_insn "mve_vhcaddq_rot90_s<mode>" | |
1258 | [ | |
6debbff6 | 1259 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1260 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
1261 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1262 | VHCADDQ_ROT90_S)) | |
1263 | ] | |
1264 | "TARGET_HAVE_MVE" | |
1265 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90" | |
1266 | [(set_attr "type" "mve_move") | |
1267 | ]) | |
1268 | ||
1269 | ;; | |
1270 | ;; [vhsubq_n_u, vhsubq_n_s]) | |
1271 | ;; | |
1272 | (define_insn "mve_vhsubq_n_<supf><mode>" | |
1273 | [ | |
1274 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1275 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1276 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1277 | VHSUBQ_N)) | |
1278 | ] | |
1279 | "TARGET_HAVE_MVE" | |
1280 | "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1281 | [(set_attr "type" "mve_move") | |
1282 | ]) | |
1283 | ||
1284 | ;; | |
1285 | ;; [vhsubq_s, vhsubq_u]) | |
1286 | ;; | |
1287 | (define_insn "mve_vhsubq_<supf><mode>" | |
1288 | [ | |
1289 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1290 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1291 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1292 | VHSUBQ)) | |
1293 | ] | |
1294 | "TARGET_HAVE_MVE" | |
1295 | "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1296 | [(set_attr "type" "mve_move") | |
1297 | ]) | |
1298 | ||
1299 | ;; | |
1300 | ;; [vmaxaq_s]) | |
1301 | ;; | |
1302 | (define_insn "mve_vmaxaq_s<mode>" | |
1303 | [ | |
1304 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1305 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1306 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1307 | VMAXAQ_S)) | |
1308 | ] | |
1309 | "TARGET_HAVE_MVE" | |
1310 | "vmaxa.s%#<V_sz_elem> %q0, %q2" | |
1311 | [(set_attr "type" "mve_move") | |
1312 | ]) | |
1313 | ||
1314 | ;; | |
1315 | ;; [vmaxavq_s]) | |
1316 | ;; | |
1317 | (define_insn "mve_vmaxavq_s<mode>" | |
1318 | [ | |
1319 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1320 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1321 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1322 | VMAXAVQ_S)) | |
1323 | ] | |
1324 | "TARGET_HAVE_MVE" | |
1325 | "vmaxav.s%#<V_sz_elem>\t%0, %q2" | |
1326 | [(set_attr "type" "mve_move") | |
1327 | ]) | |
1328 | ||
1329 | ;; | |
1330 | ;; [vmaxq_u, vmaxq_s]) | |
1331 | ;; | |
1332 | (define_insn "mve_vmaxq_<supf><mode>" | |
1333 | [ | |
1334 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1335 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1336 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1337 | VMAXQ)) | |
1338 | ] | |
1339 | "TARGET_HAVE_MVE" | |
1340 | "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1341 | [(set_attr "type" "mve_move") | |
1342 | ]) | |
1343 | ||
1344 | ;; | |
1345 | ;; [vmaxvq_u, vmaxvq_s]) | |
1346 | ;; | |
1347 | (define_insn "mve_vmaxvq_<supf><mode>" | |
1348 | [ | |
1349 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1350 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1351 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1352 | VMAXVQ)) | |
1353 | ] | |
1354 | "TARGET_HAVE_MVE" | |
1355 | "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2" | |
1356 | [(set_attr "type" "mve_move") | |
1357 | ]) | |
1358 | ||
1359 | ;; | |
1360 | ;; [vminaq_s]) | |
1361 | ;; | |
1362 | (define_insn "mve_vminaq_s<mode>" | |
1363 | [ | |
1364 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1365 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1366 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1367 | VMINAQ_S)) | |
1368 | ] | |
1369 | "TARGET_HAVE_MVE" | |
1370 | "vmina.s%#<V_sz_elem>\t%q0, %q2" | |
1371 | [(set_attr "type" "mve_move") | |
1372 | ]) | |
1373 | ||
1374 | ;; | |
1375 | ;; [vminavq_s]) | |
1376 | ;; | |
1377 | (define_insn "mve_vminavq_s<mode>" | |
1378 | [ | |
1379 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1380 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1381 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1382 | VMINAVQ_S)) | |
1383 | ] | |
1384 | "TARGET_HAVE_MVE" | |
1385 | "vminav.s%#<V_sz_elem>\t%0, %q2" | |
1386 | [(set_attr "type" "mve_move") | |
1387 | ]) | |
1388 | ||
1389 | ;; | |
1390 | ;; [vminq_s, vminq_u]) | |
1391 | ;; | |
1392 | (define_insn "mve_vminq_<supf><mode>" | |
1393 | [ | |
1394 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1395 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1396 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1397 | VMINQ)) | |
1398 | ] | |
1399 | "TARGET_HAVE_MVE" | |
1400 | "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1401 | [(set_attr "type" "mve_move") | |
1402 | ]) | |
1403 | ||
1404 | ;; | |
1405 | ;; [vminvq_u, vminvq_s]) | |
1406 | ;; | |
1407 | (define_insn "mve_vminvq_<supf><mode>" | |
1408 | [ | |
1409 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1410 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1411 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1412 | VMINVQ)) | |
1413 | ] | |
1414 | "TARGET_HAVE_MVE" | |
1415 | "vminv.<supf>%#<V_sz_elem>\t%0, %q2" | |
1416 | [(set_attr "type" "mve_move") | |
1417 | ]) | |
1418 | ||
1419 | ;; | |
1420 | ;; [vmladavq_u, vmladavq_s]) | |
1421 | ;; | |
1422 | (define_insn "mve_vmladavq_<supf><mode>" | |
1423 | [ | |
3d537943 | 1424 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
1425 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
1426 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1427 | VMLADAVQ)) | |
1428 | ] | |
1429 | "TARGET_HAVE_MVE" | |
1430 | "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2" | |
1431 | [(set_attr "type" "mve_move") | |
1432 | ]) | |
1433 | ||
1434 | ;; | |
1435 | ;; [vmladavxq_s]) | |
1436 | ;; | |
1437 | (define_insn "mve_vmladavxq_s<mode>" | |
1438 | [ | |
3d537943 | 1439 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
1440 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
1441 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1442 | VMLADAVXQ_S)) | |
1443 | ] | |
1444 | "TARGET_HAVE_MVE" | |
1445 | "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1446 | [(set_attr "type" "mve_move") | |
1447 | ]) | |
1448 | ||
1449 | ;; | |
1450 | ;; [vmlsdavq_s]) | |
1451 | ;; | |
1452 | (define_insn "mve_vmlsdavq_s<mode>" | |
1453 | [ | |
3d537943 | 1454 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
1455 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
1456 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1457 | VMLSDAVQ_S)) | |
1458 | ] | |
1459 | "TARGET_HAVE_MVE" | |
1460 | "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1461 | [(set_attr "type" "mve_move") | |
1462 | ]) | |
1463 | ||
1464 | ;; | |
1465 | ;; [vmlsdavxq_s]) | |
1466 | ;; | |
1467 | (define_insn "mve_vmlsdavxq_s<mode>" | |
1468 | [ | |
3d537943 | 1469 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
1470 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
1471 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1472 | VMLSDAVXQ_S)) | |
1473 | ] | |
1474 | "TARGET_HAVE_MVE" | |
1475 | "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1476 | [(set_attr "type" "mve_move") | |
1477 | ]) | |
1478 | ||
1479 | ;; | |
1480 | ;; [vmulhq_s, vmulhq_u]) | |
1481 | ;; | |
1482 | (define_insn "mve_vmulhq_<supf><mode>" | |
1483 | [ | |
1484 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1485 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1486 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1487 | VMULHQ)) | |
1488 | ] | |
1489 | "TARGET_HAVE_MVE" | |
1490 | "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1491 | [(set_attr "type" "mve_move") | |
1492 | ]) | |
1493 | ||
1494 | ;; | |
1495 | ;; [vmullbq_int_u, vmullbq_int_s]) | |
1496 | ;; | |
1497 | (define_insn "mve_vmullbq_int_<supf><mode>" | |
1498 | [ | |
6debbff6 | 1499 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1500 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") |
1501 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1502 | VMULLBQ_INT)) | |
1503 | ] | |
1504 | "TARGET_HAVE_MVE" | |
1505 | "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1506 | [(set_attr "type" "mve_move") | |
1507 | ]) | |
1508 | ||
1509 | ;; | |
1510 | ;; [vmulltq_int_u, vmulltq_int_s]) | |
1511 | ;; | |
1512 | (define_insn "mve_vmulltq_int_<supf><mode>" | |
1513 | [ | |
6debbff6 | 1514 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1515 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") |
1516 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1517 | VMULLTQ_INT)) | |
1518 | ] | |
1519 | "TARGET_HAVE_MVE" | |
1520 | "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1521 | [(set_attr "type" "mve_move") | |
1522 | ]) | |
1523 | ||
1524 | ;; | |
1525 | ;; [vmulq_n_u, vmulq_n_s]) | |
1526 | ;; | |
1527 | (define_insn "mve_vmulq_n_<supf><mode>" | |
1528 | [ | |
1529 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1530 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1531 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1532 | VMULQ_N)) | |
1533 | ] | |
1534 | "TARGET_HAVE_MVE" | |
1535 | "vmul.i%#<V_sz_elem>\t%q0, %q1, %2" | |
1536 | [(set_attr "type" "mve_move") | |
1537 | ]) | |
1538 | ||
1539 | ;; | |
1540 | ;; [vmulq_u, vmulq_s]) | |
1541 | ;; | |
1542 | (define_insn "mve_vmulq_<supf><mode>" | |
1543 | [ | |
1544 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1545 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1546 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1547 | VMULQ)) | |
1548 | ] | |
1549 | "TARGET_HAVE_MVE" | |
1550 | "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2" | |
1551 | [(set_attr "type" "mve_move") | |
1552 | ]) | |
1553 | ||
0f41b5e0 DZ |
1554 | (define_insn "mve_vmulq<mode>" |
1555 | [ | |
1556 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1557 | (mult:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") | |
1558 | (match_operand:MVE_2 2 "s_register_operand" "w"))) | |
1559 | ] | |
1560 | "TARGET_HAVE_MVE" | |
1561 | "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2" | |
1562 | [(set_attr "type" "mve_move") | |
1563 | ]) | |
1564 | ||
33203b4c SP |
1565 | ;; |
1566 | ;; [vornq_u, vornq_s]) | |
1567 | ;; | |
1568 | (define_insn "mve_vornq_<supf><mode>" | |
1569 | [ | |
1570 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1571 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1572 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1573 | VORNQ)) | |
1574 | ] | |
1575 | "TARGET_HAVE_MVE" | |
1576 | "vorn %q0, %q1, %q2" | |
1577 | [(set_attr "type" "mve_move") | |
1578 | ]) | |
1579 | ||
1580 | ;; | |
1581 | ;; [vorrq_s, vorrq_u]) | |
1582 | ;; | |
1583 | (define_insn "mve_vorrq_<supf><mode>" | |
1584 | [ | |
1585 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1586 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1587 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1588 | VORRQ)) | |
1589 | ] | |
1590 | "TARGET_HAVE_MVE" | |
1591 | "vorr %q0, %q1, %q2" | |
1592 | [(set_attr "type" "mve_move") | |
1593 | ]) | |
1594 | ||
1595 | ;; | |
1596 | ;; [vqaddq_n_s, vqaddq_n_u]) | |
1597 | ;; | |
1598 | (define_insn "mve_vqaddq_n_<supf><mode>" | |
1599 | [ | |
1600 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1601 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1602 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1603 | VQADDQ_N)) | |
1604 | ] | |
1605 | "TARGET_HAVE_MVE" | |
1606 | "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1607 | [(set_attr "type" "mve_move") | |
1608 | ]) | |
1609 | ||
1610 | ;; | |
1611 | ;; [vqaddq_u, vqaddq_s]) | |
1612 | ;; | |
1613 | (define_insn "mve_vqaddq_<supf><mode>" | |
1614 | [ | |
1615 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1616 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1617 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1618 | VQADDQ)) | |
1619 | ] | |
1620 | "TARGET_HAVE_MVE" | |
1621 | "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1622 | [(set_attr "type" "mve_move") | |
1623 | ]) | |
1624 | ||
1625 | ;; | |
1626 | ;; [vqdmulhq_n_s]) | |
1627 | ;; | |
1628 | (define_insn "mve_vqdmulhq_n_s<mode>" | |
1629 | [ | |
1630 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1631 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1632 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1633 | VQDMULHQ_N_S)) | |
1634 | ] | |
1635 | "TARGET_HAVE_MVE" | |
1636 | "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1637 | [(set_attr "type" "mve_move") | |
1638 | ]) | |
1639 | ||
1640 | ;; | |
1641 | ;; [vqdmulhq_s]) | |
1642 | ;; | |
1643 | (define_insn "mve_vqdmulhq_s<mode>" | |
1644 | [ | |
1645 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1646 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1647 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1648 | VQDMULHQ_S)) | |
1649 | ] | |
1650 | "TARGET_HAVE_MVE" | |
1651 | "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" | |
1652 | [(set_attr "type" "mve_move") | |
1653 | ]) | |
1654 | ||
1655 | ;; | |
1656 | ;; [vqrdmulhq_n_s]) | |
1657 | ;; | |
1658 | (define_insn "mve_vqrdmulhq_n_s<mode>" | |
1659 | [ | |
1660 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1661 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1662 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1663 | VQRDMULHQ_N_S)) | |
1664 | ] | |
1665 | "TARGET_HAVE_MVE" | |
1666 | "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1667 | [(set_attr "type" "mve_move") | |
1668 | ]) | |
1669 | ||
1670 | ;; | |
1671 | ;; [vqrdmulhq_s]) | |
1672 | ;; | |
1673 | (define_insn "mve_vqrdmulhq_s<mode>" | |
1674 | [ | |
1675 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1676 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1677 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1678 | VQRDMULHQ_S)) | |
1679 | ] | |
1680 | "TARGET_HAVE_MVE" | |
1681 | "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" | |
1682 | [(set_attr "type" "mve_move") | |
1683 | ]) | |
1684 | ||
1685 | ;; | |
1686 | ;; [vqrshlq_n_s, vqrshlq_n_u]) | |
1687 | ;; | |
1688 | (define_insn "mve_vqrshlq_n_<supf><mode>" | |
1689 | [ | |
1690 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1691 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1692 | (match_operand:SI 2 "s_register_operand" "r")] | |
1693 | VQRSHLQ_N)) | |
1694 | ] | |
1695 | "TARGET_HAVE_MVE" | |
1696 | "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1697 | [(set_attr "type" "mve_move") | |
1698 | ]) | |
1699 | ||
1700 | ;; | |
1701 | ;; [vqrshlq_s, vqrshlq_u]) | |
1702 | ;; | |
1703 | (define_insn "mve_vqrshlq_<supf><mode>" | |
1704 | [ | |
1705 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1706 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1707 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1708 | VQRSHLQ)) | |
1709 | ] | |
1710 | "TARGET_HAVE_MVE" | |
1711 | "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1712 | [(set_attr "type" "mve_move") | |
1713 | ]) | |
1714 | ||
1715 | ;; | |
1716 | ;; [vqshlq_n_s, vqshlq_n_u]) | |
1717 | ;; | |
1718 | (define_insn "mve_vqshlq_n_<supf><mode>" | |
1719 | [ | |
1720 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1721 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1722 | (match_operand:SI 2 "immediate_operand" "i")] | |
1723 | VQSHLQ_N)) | |
1724 | ] | |
1725 | "TARGET_HAVE_MVE" | |
1726 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1727 | [(set_attr "type" "mve_move") | |
1728 | ]) | |
1729 | ||
1730 | ;; | |
1731 | ;; [vqshlq_r_u, vqshlq_r_s]) | |
1732 | ;; | |
1733 | (define_insn "mve_vqshlq_r_<supf><mode>" | |
1734 | [ | |
1735 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1736 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1737 | (match_operand:SI 2 "s_register_operand" "r")] | |
1738 | VQSHLQ_R)) | |
1739 | ] | |
1740 | "TARGET_HAVE_MVE" | |
1741 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1742 | [(set_attr "type" "mve_move") | |
1743 | ]) | |
1744 | ||
1745 | ;; | |
1746 | ;; [vqshlq_s, vqshlq_u]) | |
1747 | ;; | |
1748 | (define_insn "mve_vqshlq_<supf><mode>" | |
1749 | [ | |
1750 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1751 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1752 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1753 | VQSHLQ)) | |
1754 | ] | |
1755 | "TARGET_HAVE_MVE" | |
1756 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1757 | [(set_attr "type" "mve_move") | |
1758 | ]) | |
1759 | ||
1760 | ;; | |
1761 | ;; [vqshluq_n_s]) | |
1762 | ;; | |
1763 | (define_insn "mve_vqshluq_n_s<mode>" | |
1764 | [ | |
1765 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1766 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1767 | (match_operand:SI 2 "mve_imm_7" "Ra")] | |
1768 | VQSHLUQ_N_S)) | |
1769 | ] | |
1770 | "TARGET_HAVE_MVE" | |
1771 | "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1772 | [(set_attr "type" "mve_move") | |
1773 | ]) | |
1774 | ||
1775 | ;; | |
1776 | ;; [vqsubq_n_s, vqsubq_n_u]) | |
1777 | ;; | |
1778 | (define_insn "mve_vqsubq_n_<supf><mode>" | |
1779 | [ | |
1780 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1781 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1782 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1783 | VQSUBQ_N)) | |
1784 | ] | |
1785 | "TARGET_HAVE_MVE" | |
1786 | "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1787 | [(set_attr "type" "mve_move") | |
1788 | ]) | |
1789 | ||
1790 | ;; | |
1791 | ;; [vqsubq_u, vqsubq_s]) | |
1792 | ;; | |
1793 | (define_insn "mve_vqsubq_<supf><mode>" | |
1794 | [ | |
1795 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1796 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1797 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1798 | VQSUBQ)) | |
1799 | ] | |
1800 | "TARGET_HAVE_MVE" | |
1801 | "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1802 | [(set_attr "type" "mve_move") | |
1803 | ]) | |
1804 | ||
1805 | ;; | |
1806 | ;; [vrhaddq_s, vrhaddq_u]) | |
1807 | ;; | |
1808 | (define_insn "mve_vrhaddq_<supf><mode>" | |
1809 | [ | |
1810 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1811 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1812 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1813 | VRHADDQ)) | |
1814 | ] | |
1815 | "TARGET_HAVE_MVE" | |
1816 | "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1817 | [(set_attr "type" "mve_move") | |
1818 | ]) | |
1819 | ||
1820 | ;; | |
1821 | ;; [vrmulhq_s, vrmulhq_u]) | |
1822 | ;; | |
1823 | (define_insn "mve_vrmulhq_<supf><mode>" | |
1824 | [ | |
1825 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1826 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1827 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1828 | VRMULHQ)) | |
1829 | ] | |
1830 | "TARGET_HAVE_MVE" | |
1831 | "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1832 | [(set_attr "type" "mve_move") | |
1833 | ]) | |
1834 | ||
1835 | ;; | |
1836 | ;; [vrshlq_n_u, vrshlq_n_s]) | |
1837 | ;; | |
1838 | (define_insn "mve_vrshlq_n_<supf><mode>" | |
1839 | [ | |
1840 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1841 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1842 | (match_operand:SI 2 "s_register_operand" "r")] | |
1843 | VRSHLQ_N)) | |
1844 | ] | |
1845 | "TARGET_HAVE_MVE" | |
1846 | "vrshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1847 | [(set_attr "type" "mve_move") | |
1848 | ]) | |
1849 | ||
1850 | ;; | |
1851 | ;; [vrshlq_s, vrshlq_u]) | |
1852 | ;; | |
1853 | (define_insn "mve_vrshlq_<supf><mode>" | |
1854 | [ | |
1855 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1856 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1857 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1858 | VRSHLQ)) | |
1859 | ] | |
1860 | "TARGET_HAVE_MVE" | |
1861 | "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1862 | [(set_attr "type" "mve_move") | |
1863 | ]) | |
1864 | ||
1865 | ;; | |
1866 | ;; [vrshrq_n_s, vrshrq_n_u]) | |
1867 | ;; | |
1868 | (define_insn "mve_vrshrq_n_<supf><mode>" | |
1869 | [ | |
1870 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1871 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1872 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] | |
1873 | VRSHRQ_N)) | |
1874 | ] | |
1875 | "TARGET_HAVE_MVE" | |
1876 | "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1877 | [(set_attr "type" "mve_move") | |
1878 | ]) | |
1879 | ||
1880 | ;; | |
1881 | ;; [vshlq_n_u, vshlq_n_s]) | |
1882 | ;; | |
1883 | (define_insn "mve_vshlq_n_<supf><mode>" | |
1884 | [ | |
1885 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1886 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1887 | (match_operand:SI 2 "immediate_operand" "i")] | |
1888 | VSHLQ_N)) | |
1889 | ] | |
1890 | "TARGET_HAVE_MVE" | |
1891 | "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1892 | [(set_attr "type" "mve_move") | |
1893 | ]) | |
1894 | ||
1895 | ;; | |
1896 | ;; [vshlq_r_s, vshlq_r_u]) | |
1897 | ;; | |
1898 | (define_insn "mve_vshlq_r_<supf><mode>" | |
1899 | [ | |
1900 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1901 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1902 | (match_operand:SI 2 "s_register_operand" "r")] | |
1903 | VSHLQ_R)) | |
1904 | ] | |
1905 | "TARGET_HAVE_MVE" | |
1906 | "vshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1907 | [(set_attr "type" "mve_move") | |
1908 | ]) | |
1909 | ||
1910 | ;; | |
1911 | ;; [vsubq_n_s, vsubq_n_u]) | |
1912 | ;; | |
1913 | (define_insn "mve_vsubq_n_<supf><mode>" | |
1914 | [ | |
1915 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1916 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1917 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1918 | VSUBQ_N)) | |
1919 | ] | |
1920 | "TARGET_HAVE_MVE" | |
1921 | "vsub.i%#<V_sz_elem>\t%q0, %q1, %2" | |
1922 | [(set_attr "type" "mve_move") | |
1923 | ]) | |
1924 | ||
1925 | ;; | |
1926 | ;; [vsubq_s, vsubq_u]) | |
1927 | ;; | |
1928 | (define_insn "mve_vsubq_<supf><mode>" | |
1929 | [ | |
1930 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1931 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1932 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1933 | VSUBQ)) | |
1934 | ] | |
1935 | "TARGET_HAVE_MVE" | |
1936 | "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2" | |
1937 | [(set_attr "type" "mve_move") | |
1938 | ]) | |
f9355dee SP |
1939 | |
1940 | ;; | |
1941 | ;; [vabdq_f]) | |
1942 | ;; | |
1943 | (define_insn "mve_vabdq_f<mode>" | |
1944 | [ | |
1945 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1946 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1947 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
1948 | VABDQ_F)) | |
1949 | ] | |
1950 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1951 | "vabd.f%#<V_sz_elem> %q0, %q1, %q2" | |
1952 | [(set_attr "type" "mve_move") | |
1953 | ]) | |
1954 | ||
1955 | ;; | |
1956 | ;; [vaddlvaq_s vaddlvaq_u]) | |
1957 | ;; | |
1958 | (define_insn "mve_vaddlvaq_<supf>v4si" | |
1959 | [ | |
1960 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
1961 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
1962 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
1963 | VADDLVAQ)) | |
1964 | ] | |
1965 | "TARGET_HAVE_MVE" | |
1966 | "vaddlva.<supf>32 %Q0, %R0, %q2" | |
1967 | [(set_attr "type" "mve_move") | |
1968 | ]) | |
1969 | ||
1970 | ;; | |
1971 | ;; [vaddq_n_f]) | |
1972 | ;; | |
1973 | (define_insn "mve_vaddq_n_f<mode>" | |
1974 | [ | |
1975 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1976 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1977 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1978 | VADDQ_N_F)) | |
1979 | ] | |
1980 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1981 | "vadd.f%#<V_sz_elem> %q0, %q1, %2" | |
1982 | [(set_attr "type" "mve_move") | |
1983 | ]) | |
1984 | ||
1985 | ;; | |
1986 | ;; [vandq_f]) | |
1987 | ;; | |
1988 | (define_insn "mve_vandq_f<mode>" | |
1989 | [ | |
1990 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1991 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1992 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
1993 | VANDQ_F)) | |
1994 | ] | |
1995 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1996 | "vand %q0, %q1, %q2" | |
1997 | [(set_attr "type" "mve_move") | |
1998 | ]) | |
1999 | ||
2000 | ;; | |
2001 | ;; [vbicq_f]) | |
2002 | ;; | |
2003 | (define_insn "mve_vbicq_f<mode>" | |
2004 | [ | |
2005 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2006 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2007 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2008 | VBICQ_F)) | |
2009 | ] | |
2010 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2011 | "vbic %q0, %q1, %q2" | |
2012 | [(set_attr "type" "mve_move") | |
2013 | ]) | |
2014 | ||
2015 | ;; | |
2016 | ;; [vbicq_n_s, vbicq_n_u]) | |
2017 | ;; | |
2018 | (define_insn "mve_vbicq_n_<supf><mode>" | |
2019 | [ | |
2020 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2021 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2022 | (match_operand:SI 2 "immediate_operand" "i")] | |
2023 | VBICQ_N)) | |
2024 | ] | |
2025 | "TARGET_HAVE_MVE" | |
2026 | "vbic.i%#<V_sz_elem> %q0, %2" | |
2027 | [(set_attr "type" "mve_move") | |
2028 | ]) | |
2029 | ||
2030 | ;; | |
2031 | ;; [vcaddq_rot270_f]) | |
2032 | ;; | |
2033 | (define_insn "mve_vcaddq_rot270_f<mode>" | |
2034 | [ | |
6debbff6 | 2035 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2036 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2037 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2038 | VCADDQ_ROT270_F)) | |
2039 | ] | |
2040 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2041 | "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270" | |
2042 | [(set_attr "type" "mve_move") | |
2043 | ]) | |
2044 | ||
2045 | ;; | |
2046 | ;; [vcaddq_rot90_f]) | |
2047 | ;; | |
2048 | (define_insn "mve_vcaddq_rot90_f<mode>" | |
2049 | [ | |
6debbff6 | 2050 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2051 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2052 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2053 | VCADDQ_ROT90_F)) | |
2054 | ] | |
2055 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2056 | "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90" | |
2057 | [(set_attr "type" "mve_move") | |
2058 | ]) | |
2059 | ||
2060 | ;; | |
2061 | ;; [vcmpeqq_f]) | |
2062 | ;; | |
2063 | (define_insn "mve_vcmpeqq_f<mode>" | |
2064 | [ | |
2065 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2066 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2067 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2068 | VCMPEQQ_F)) | |
2069 | ] | |
2070 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2071 | "vcmp.f%#<V_sz_elem> eq, %q1, %q2" | |
2072 | [(set_attr "type" "mve_move") | |
2073 | ]) | |
2074 | ||
2075 | ;; | |
2076 | ;; [vcmpeqq_n_f]) | |
2077 | ;; | |
2078 | (define_insn "mve_vcmpeqq_n_f<mode>" | |
2079 | [ | |
2080 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2081 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2082 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2083 | VCMPEQQ_N_F)) | |
2084 | ] | |
2085 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2086 | "vcmp.f%#<V_sz_elem> eq, %q1, %2" | |
2087 | [(set_attr "type" "mve_move") | |
2088 | ]) | |
2089 | ||
2090 | ;; | |
2091 | ;; [vcmpgeq_f]) | |
2092 | ;; | |
2093 | (define_insn "mve_vcmpgeq_f<mode>" | |
2094 | [ | |
2095 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2096 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2097 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2098 | VCMPGEQ_F)) | |
2099 | ] | |
2100 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2101 | "vcmp.f%#<V_sz_elem> ge, %q1, %q2" | |
2102 | [(set_attr "type" "mve_move") | |
2103 | ]) | |
2104 | ||
2105 | ;; | |
2106 | ;; [vcmpgeq_n_f]) | |
2107 | ;; | |
2108 | (define_insn "mve_vcmpgeq_n_f<mode>" | |
2109 | [ | |
2110 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2111 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2112 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2113 | VCMPGEQ_N_F)) | |
2114 | ] | |
2115 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2116 | "vcmp.f%#<V_sz_elem> ge, %q1, %2" | |
2117 | [(set_attr "type" "mve_move") | |
2118 | ]) | |
2119 | ||
2120 | ;; | |
2121 | ;; [vcmpgtq_f]) | |
2122 | ;; | |
2123 | (define_insn "mve_vcmpgtq_f<mode>" | |
2124 | [ | |
2125 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2126 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2127 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2128 | VCMPGTQ_F)) | |
2129 | ] | |
2130 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2131 | "vcmp.f%#<V_sz_elem> gt, %q1, %q2" | |
2132 | [(set_attr "type" "mve_move") | |
2133 | ]) | |
2134 | ||
2135 | ;; | |
2136 | ;; [vcmpgtq_n_f]) | |
2137 | ;; | |
2138 | (define_insn "mve_vcmpgtq_n_f<mode>" | |
2139 | [ | |
2140 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2141 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2142 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2143 | VCMPGTQ_N_F)) | |
2144 | ] | |
2145 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2146 | "vcmp.f%#<V_sz_elem> gt, %q1, %2" | |
2147 | [(set_attr "type" "mve_move") | |
2148 | ]) | |
2149 | ||
2150 | ;; | |
2151 | ;; [vcmpleq_f]) | |
2152 | ;; | |
2153 | (define_insn "mve_vcmpleq_f<mode>" | |
2154 | [ | |
2155 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2156 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2157 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2158 | VCMPLEQ_F)) | |
2159 | ] | |
2160 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2161 | "vcmp.f%#<V_sz_elem> le, %q1, %q2" | |
2162 | [(set_attr "type" "mve_move") | |
2163 | ]) | |
2164 | ||
2165 | ;; | |
2166 | ;; [vcmpleq_n_f]) | |
2167 | ;; | |
2168 | (define_insn "mve_vcmpleq_n_f<mode>" | |
2169 | [ | |
2170 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2171 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2172 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2173 | VCMPLEQ_N_F)) | |
2174 | ] | |
2175 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2176 | "vcmp.f%#<V_sz_elem> le, %q1, %2" | |
2177 | [(set_attr "type" "mve_move") | |
2178 | ]) | |
2179 | ||
2180 | ;; | |
2181 | ;; [vcmpltq_f]) | |
2182 | ;; | |
2183 | (define_insn "mve_vcmpltq_f<mode>" | |
2184 | [ | |
2185 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2186 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2187 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2188 | VCMPLTQ_F)) | |
2189 | ] | |
2190 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2191 | "vcmp.f%#<V_sz_elem> lt, %q1, %q2" | |
2192 | [(set_attr "type" "mve_move") | |
2193 | ]) | |
2194 | ||
2195 | ;; | |
2196 | ;; [vcmpltq_n_f]) | |
2197 | ;; | |
2198 | (define_insn "mve_vcmpltq_n_f<mode>" | |
2199 | [ | |
2200 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2201 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2202 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2203 | VCMPLTQ_N_F)) | |
2204 | ] | |
2205 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2206 | "vcmp.f%#<V_sz_elem> lt, %q1, %2" | |
2207 | [(set_attr "type" "mve_move") | |
2208 | ]) | |
2209 | ||
2210 | ;; | |
2211 | ;; [vcmpneq_f]) | |
2212 | ;; | |
2213 | (define_insn "mve_vcmpneq_f<mode>" | |
2214 | [ | |
2215 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2216 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2217 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2218 | VCMPNEQ_F)) | |
2219 | ] | |
2220 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2221 | "vcmp.f%#<V_sz_elem> ne, %q1, %q2" | |
2222 | [(set_attr "type" "mve_move") | |
2223 | ]) | |
2224 | ||
2225 | ;; | |
2226 | ;; [vcmpneq_n_f]) | |
2227 | ;; | |
2228 | (define_insn "mve_vcmpneq_n_f<mode>" | |
2229 | [ | |
2230 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2231 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2232 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2233 | VCMPNEQ_N_F)) | |
2234 | ] | |
2235 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2236 | "vcmp.f%#<V_sz_elem> ne, %q1, %2" | |
2237 | [(set_attr "type" "mve_move") | |
2238 | ]) | |
2239 | ||
2240 | ;; | |
2241 | ;; [vcmulq_f]) | |
2242 | ;; | |
2243 | (define_insn "mve_vcmulq_f<mode>" | |
2244 | [ | |
6debbff6 | 2245 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2246 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2247 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2248 | VCMULQ_F)) | |
2249 | ] | |
2250 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2251 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0" | |
2252 | [(set_attr "type" "mve_move") | |
2253 | ]) | |
2254 | ||
2255 | ;; | |
2256 | ;; [vcmulq_rot180_f]) | |
2257 | ;; | |
2258 | (define_insn "mve_vcmulq_rot180_f<mode>" | |
2259 | [ | |
6debbff6 | 2260 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2261 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2262 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2263 | VCMULQ_ROT180_F)) | |
2264 | ] | |
2265 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2266 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180" | |
2267 | [(set_attr "type" "mve_move") | |
2268 | ]) | |
2269 | ||
2270 | ;; | |
2271 | ;; [vcmulq_rot270_f]) | |
2272 | ;; | |
2273 | (define_insn "mve_vcmulq_rot270_f<mode>" | |
2274 | [ | |
6debbff6 | 2275 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2276 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2277 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2278 | VCMULQ_ROT270_F)) | |
2279 | ] | |
2280 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2281 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270" | |
2282 | [(set_attr "type" "mve_move") | |
2283 | ]) | |
2284 | ||
2285 | ;; | |
2286 | ;; [vcmulq_rot90_f]) | |
2287 | ;; | |
2288 | (define_insn "mve_vcmulq_rot90_f<mode>" | |
2289 | [ | |
6debbff6 | 2290 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2291 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") |
2292 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2293 | VCMULQ_ROT90_F)) | |
2294 | ] | |
2295 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2296 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90" | |
2297 | [(set_attr "type" "mve_move") | |
2298 | ]) | |
2299 | ||
2300 | ;; | |
2301 | ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) | |
2302 | ;; | |
2303 | (define_insn "mve_vctp<mode1>q_mhi" | |
2304 | [ | |
2305 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2306 | (unspec:HI [(match_operand:SI 1 "s_register_operand" "r") | |
2307 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
2308 | VCTPQ_M)) | |
2309 | ] | |
2310 | "TARGET_HAVE_MVE" | |
2311 | "vpst\;vctpt.<mode1> %1" | |
2312 | [(set_attr "type" "mve_move") | |
2313 | (set_attr "length""8")]) | |
2314 | ||
2315 | ;; | |
2316 | ;; [vcvtbq_f16_f32]) | |
2317 | ;; | |
2318 | (define_insn "mve_vcvtbq_f16_f32v8hf" | |
2319 | [ | |
2320 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2321 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2322 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
2323 | VCVTBQ_F16_F32)) | |
2324 | ] | |
2325 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2326 | "vcvtb.f16.f32 %q0, %q2" | |
2327 | [(set_attr "type" "mve_move") | |
2328 | ]) | |
2329 | ||
2330 | ;; | |
2331 | ;; [vcvttq_f16_f32]) | |
2332 | ;; | |
2333 | (define_insn "mve_vcvttq_f16_f32v8hf" | |
2334 | [ | |
2335 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2336 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2337 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
2338 | VCVTTQ_F16_F32)) | |
2339 | ] | |
2340 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2341 | "vcvtt.f16.f32 %q0, %q2" | |
2342 | [(set_attr "type" "mve_move") | |
2343 | ]) | |
2344 | ||
2345 | ;; | |
2346 | ;; [veorq_f]) | |
2347 | ;; | |
2348 | (define_insn "mve_veorq_f<mode>" | |
2349 | [ | |
2350 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2351 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2352 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2353 | VEORQ_F)) | |
2354 | ] | |
2355 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2356 | "veor %q0, %q1, %q2" | |
2357 | [(set_attr "type" "mve_move") | |
2358 | ]) | |
2359 | ||
2360 | ;; | |
2361 | ;; [vmaxnmaq_f]) | |
2362 | ;; | |
2363 | (define_insn "mve_vmaxnmaq_f<mode>" | |
2364 | [ | |
2365 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2366 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2367 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2368 | VMAXNMAQ_F)) | |
2369 | ] | |
2370 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2371 | "vmaxnma.f%#<V_sz_elem> %q0, %q2" | |
2372 | [(set_attr "type" "mve_move") | |
2373 | ]) | |
2374 | ||
2375 | ;; | |
2376 | ;; [vmaxnmavq_f]) | |
2377 | ;; | |
2378 | (define_insn "mve_vmaxnmavq_f<mode>" | |
2379 | [ | |
2380 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2381 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2382 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2383 | VMAXNMAVQ_F)) | |
2384 | ] | |
2385 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2386 | "vmaxnmav.f%#<V_sz_elem> %0, %q2" | |
2387 | [(set_attr "type" "mve_move") | |
2388 | ]) | |
2389 | ||
2390 | ;; | |
2391 | ;; [vmaxnmq_f]) | |
2392 | ;; | |
2393 | (define_insn "mve_vmaxnmq_f<mode>" | |
2394 | [ | |
2395 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2396 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2397 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2398 | VMAXNMQ_F)) | |
2399 | ] | |
2400 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2401 | "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2" | |
2402 | [(set_attr "type" "mve_move") | |
2403 | ]) | |
2404 | ||
2405 | ;; | |
2406 | ;; [vmaxnmvq_f]) | |
2407 | ;; | |
2408 | (define_insn "mve_vmaxnmvq_f<mode>" | |
2409 | [ | |
2410 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2411 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2412 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2413 | VMAXNMVQ_F)) | |
2414 | ] | |
2415 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2416 | "vmaxnmv.f%#<V_sz_elem> %0, %q2" | |
2417 | [(set_attr "type" "mve_move") | |
2418 | ]) | |
2419 | ||
2420 | ;; | |
2421 | ;; [vminnmaq_f]) | |
2422 | ;; | |
2423 | (define_insn "mve_vminnmaq_f<mode>" | |
2424 | [ | |
2425 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2426 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2427 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2428 | VMINNMAQ_F)) | |
2429 | ] | |
2430 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2431 | "vminnma.f%#<V_sz_elem> %q0, %q2" | |
2432 | [(set_attr "type" "mve_move") | |
2433 | ]) | |
2434 | ||
2435 | ;; | |
2436 | ;; [vminnmavq_f]) | |
2437 | ;; | |
2438 | (define_insn "mve_vminnmavq_f<mode>" | |
2439 | [ | |
2440 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2441 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2442 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2443 | VMINNMAVQ_F)) | |
2444 | ] | |
2445 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2446 | "vminnmav.f%#<V_sz_elem> %0, %q2" | |
2447 | [(set_attr "type" "mve_move") | |
2448 | ]) | |
2449 | ||
2450 | ;; | |
2451 | ;; [vminnmq_f]) | |
2452 | ;; | |
2453 | (define_insn "mve_vminnmq_f<mode>" | |
2454 | [ | |
2455 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2456 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2457 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2458 | VMINNMQ_F)) | |
2459 | ] | |
2460 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2461 | "vminnm.f%#<V_sz_elem> %q0, %q1, %q2" | |
2462 | [(set_attr "type" "mve_move") | |
2463 | ]) | |
2464 | ||
2465 | ;; | |
2466 | ;; [vminnmvq_f]) | |
2467 | ;; | |
2468 | (define_insn "mve_vminnmvq_f<mode>" | |
2469 | [ | |
2470 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2471 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2472 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2473 | VMINNMVQ_F)) | |
2474 | ] | |
2475 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2476 | "vminnmv.f%#<V_sz_elem> %0, %q2" | |
2477 | [(set_attr "type" "mve_move") | |
2478 | ]) | |
2479 | ||
2480 | ;; | |
2481 | ;; [vmlaldavq_u, vmlaldavq_s]) | |
2482 | ;; | |
2483 | (define_insn "mve_vmlaldavq_<supf><mode>" | |
2484 | [ | |
2485 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2486 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2487 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2488 | VMLALDAVQ)) | |
2489 | ] | |
2490 | "TARGET_HAVE_MVE" | |
2491 | "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2492 | [(set_attr "type" "mve_move") | |
2493 | ]) | |
2494 | ||
2495 | ;; | |
2496 | ;; [vmlaldavxq_s]) | |
2497 | ;; | |
2498 | (define_insn "mve_vmlaldavxq_s<mode>" | |
2499 | [ | |
2500 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2501 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2502 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2503 | VMLALDAVXQ_S)) | |
2504 | ] | |
2505 | "TARGET_HAVE_MVE" | |
2506 | "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2507 | [(set_attr "type" "mve_move") | |
2508 | ]) | |
2509 | ||
2510 | ;; | |
2511 | ;; [vmlsldavq_s]) | |
2512 | ;; | |
2513 | (define_insn "mve_vmlsldavq_s<mode>" | |
2514 | [ | |
2515 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2516 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2517 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2518 | VMLSLDAVQ_S)) | |
2519 | ] | |
2520 | "TARGET_HAVE_MVE" | |
2521 | "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2522 | [(set_attr "type" "mve_move") | |
2523 | ]) | |
2524 | ||
2525 | ;; | |
2526 | ;; [vmlsldavxq_s]) | |
2527 | ;; | |
2528 | (define_insn "mve_vmlsldavxq_s<mode>" | |
2529 | [ | |
2530 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2531 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2532 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2533 | VMLSLDAVXQ_S)) | |
2534 | ] | |
2535 | "TARGET_HAVE_MVE" | |
2536 | "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2537 | [(set_attr "type" "mve_move") | |
2538 | ]) | |
2539 | ||
2540 | ;; | |
2541 | ;; [vmovnbq_u, vmovnbq_s]) | |
2542 | ;; | |
2543 | (define_insn "mve_vmovnbq_<supf><mode>" | |
2544 | [ | |
2545 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2546 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2547 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2548 | VMOVNBQ)) | |
2549 | ] | |
2550 | "TARGET_HAVE_MVE" | |
2551 | "vmovnb.i%#<V_sz_elem> %q0, %q2" | |
2552 | [(set_attr "type" "mve_move") | |
2553 | ]) | |
2554 | ||
2555 | ;; | |
2556 | ;; [vmovntq_s, vmovntq_u]) | |
2557 | ;; | |
2558 | (define_insn "mve_vmovntq_<supf><mode>" | |
2559 | [ | |
2560 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2561 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2562 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2563 | VMOVNTQ)) | |
2564 | ] | |
2565 | "TARGET_HAVE_MVE" | |
2566 | "vmovnt.i%#<V_sz_elem> %q0, %q2" | |
2567 | [(set_attr "type" "mve_move") | |
2568 | ]) | |
2569 | ||
2570 | ;; | |
2571 | ;; [vmulq_f]) | |
2572 | ;; | |
2573 | (define_insn "mve_vmulq_f<mode>" | |
2574 | [ | |
2575 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
0f41b5e0 DZ |
2576 | (mult:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
2577 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
2578 | ] |
2579 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2580 | "vmul.f%#<V_sz_elem> %q0, %q1, %q2" | |
2581 | [(set_attr "type" "mve_move") | |
2582 | ]) | |
2583 | ||
2584 | ;; | |
2585 | ;; [vmulq_n_f]) | |
2586 | ;; | |
2587 | (define_insn "mve_vmulq_n_f<mode>" | |
2588 | [ | |
2589 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2590 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2591 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2592 | VMULQ_N_F)) | |
2593 | ] | |
2594 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2595 | "vmul.f%#<V_sz_elem> %q0, %q1, %2" | |
2596 | [(set_attr "type" "mve_move") | |
2597 | ]) | |
2598 | ||
2599 | ;; | |
2600 | ;; [vornq_f]) | |
2601 | ;; | |
2602 | (define_insn "mve_vornq_f<mode>" | |
2603 | [ | |
2604 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2605 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2606 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2607 | VORNQ_F)) | |
2608 | ] | |
2609 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2610 | "vorn %q0, %q1, %q2" | |
2611 | [(set_attr "type" "mve_move") | |
2612 | ]) | |
2613 | ||
2614 | ;; | |
2615 | ;; [vorrq_f]) | |
2616 | ;; | |
2617 | (define_insn "mve_vorrq_f<mode>" | |
2618 | [ | |
2619 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2620 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2621 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2622 | VORRQ_F)) | |
2623 | ] | |
2624 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2625 | "vorr %q0, %q1, %q2" | |
2626 | [(set_attr "type" "mve_move") | |
2627 | ]) | |
2628 | ||
2629 | ;; | |
2630 | ;; [vorrq_n_u, vorrq_n_s]) | |
2631 | ;; | |
2632 | (define_insn "mve_vorrq_n_<supf><mode>" | |
2633 | [ | |
2634 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2635 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2636 | (match_operand:SI 2 "immediate_operand" "i")] | |
2637 | VORRQ_N)) | |
2638 | ] | |
2639 | "TARGET_HAVE_MVE" | |
2640 | "vorr.i%#<V_sz_elem> %q0, %2" | |
2641 | [(set_attr "type" "mve_move") | |
2642 | ]) | |
2643 | ||
2644 | ;; | |
2645 | ;; [vqdmullbq_n_s]) | |
2646 | ;; | |
2647 | (define_insn "mve_vqdmullbq_n_s<mode>" | |
2648 | [ | |
6debbff6 | 2649 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2650 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
2651 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2652 | VQDMULLBQ_N_S)) | |
2653 | ] | |
2654 | "TARGET_HAVE_MVE" | |
2655 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2" | |
2656 | [(set_attr "type" "mve_move") | |
2657 | ]) | |
2658 | ||
2659 | ;; | |
2660 | ;; [vqdmullbq_s]) | |
2661 | ;; | |
2662 | (define_insn "mve_vqdmullbq_s<mode>" | |
2663 | [ | |
6debbff6 | 2664 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2665 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
2666 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2667 | VQDMULLBQ_S)) | |
2668 | ] | |
2669 | "TARGET_HAVE_MVE" | |
2670 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2" | |
2671 | [(set_attr "type" "mve_move") | |
2672 | ]) | |
2673 | ||
2674 | ;; | |
2675 | ;; [vqdmulltq_n_s]) | |
2676 | ;; | |
2677 | (define_insn "mve_vqdmulltq_n_s<mode>" | |
2678 | [ | |
6debbff6 | 2679 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2680 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
2681 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2682 | VQDMULLTQ_N_S)) | |
2683 | ] | |
2684 | "TARGET_HAVE_MVE" | |
2685 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2" | |
2686 | [(set_attr "type" "mve_move") | |
2687 | ]) | |
2688 | ||
2689 | ;; | |
2690 | ;; [vqdmulltq_s]) | |
2691 | ;; | |
2692 | (define_insn "mve_vqdmulltq_s<mode>" | |
2693 | [ | |
6debbff6 | 2694 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
2695 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
2696 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2697 | VQDMULLTQ_S)) | |
2698 | ] | |
2699 | "TARGET_HAVE_MVE" | |
2700 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2" | |
2701 | [(set_attr "type" "mve_move") | |
2702 | ]) | |
2703 | ||
2704 | ;; | |
2705 | ;; [vqmovnbq_u, vqmovnbq_s]) | |
2706 | ;; | |
2707 | (define_insn "mve_vqmovnbq_<supf><mode>" | |
2708 | [ | |
2709 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2710 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2711 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2712 | VQMOVNBQ)) | |
2713 | ] | |
2714 | "TARGET_HAVE_MVE" | |
2715 | "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2" | |
2716 | [(set_attr "type" "mve_move") | |
2717 | ]) | |
2718 | ||
2719 | ;; | |
2720 | ;; [vqmovntq_u, vqmovntq_s]) | |
2721 | ;; | |
2722 | (define_insn "mve_vqmovntq_<supf><mode>" | |
2723 | [ | |
2724 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2725 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2726 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2727 | VQMOVNTQ)) | |
2728 | ] | |
2729 | "TARGET_HAVE_MVE" | |
2730 | "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2" | |
2731 | [(set_attr "type" "mve_move") | |
2732 | ]) | |
2733 | ||
2734 | ;; | |
2735 | ;; [vqmovunbq_s]) | |
2736 | ;; | |
2737 | (define_insn "mve_vqmovunbq_s<mode>" | |
2738 | [ | |
2739 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2740 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2741 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2742 | VQMOVUNBQ_S)) | |
2743 | ] | |
2744 | "TARGET_HAVE_MVE" | |
2745 | "vqmovunb.s%#<V_sz_elem> %q0, %q2" | |
2746 | [(set_attr "type" "mve_move") | |
2747 | ]) | |
2748 | ||
2749 | ;; | |
2750 | ;; [vqmovuntq_s]) | |
2751 | ;; | |
2752 | (define_insn "mve_vqmovuntq_s<mode>" | |
2753 | [ | |
2754 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2755 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2756 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2757 | VQMOVUNTQ_S)) | |
2758 | ] | |
2759 | "TARGET_HAVE_MVE" | |
2760 | "vqmovunt.s%#<V_sz_elem> %q0, %q2" | |
2761 | [(set_attr "type" "mve_move") | |
2762 | ]) | |
2763 | ||
2764 | ;; | |
2765 | ;; [vrmlaldavhxq_s]) | |
2766 | ;; | |
2767 | (define_insn "mve_vrmlaldavhxq_sv4si" | |
2768 | [ | |
2769 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2770 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2771 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2772 | VRMLALDAVHXQ_S)) | |
2773 | ] | |
2774 | "TARGET_HAVE_MVE" | |
2775 | "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2" | |
2776 | [(set_attr "type" "mve_move") | |
2777 | ]) | |
2778 | ||
2779 | ;; | |
2780 | ;; [vrmlsldavhq_s]) | |
2781 | ;; | |
2782 | (define_insn "mve_vrmlsldavhq_sv4si" | |
2783 | [ | |
2784 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2785 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2786 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2787 | VRMLSLDAVHQ_S)) | |
2788 | ] | |
2789 | "TARGET_HAVE_MVE" | |
2790 | "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2" | |
2791 | [(set_attr "type" "mve_move") | |
2792 | ]) | |
2793 | ||
2794 | ;; | |
2795 | ;; [vrmlsldavhxq_s]) | |
2796 | ;; | |
2797 | (define_insn "mve_vrmlsldavhxq_sv4si" | |
2798 | [ | |
2799 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2800 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2801 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2802 | VRMLSLDAVHXQ_S)) | |
2803 | ] | |
2804 | "TARGET_HAVE_MVE" | |
2805 | "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2" | |
2806 | [(set_attr "type" "mve_move") | |
2807 | ]) | |
2808 | ||
2809 | ;; | |
2810 | ;; [vshllbq_n_s, vshllbq_n_u]) | |
2811 | ;; | |
2812 | (define_insn "mve_vshllbq_n_<supf><mode>" | |
2813 | [ | |
2814 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2815 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
2816 | (match_operand:SI 2 "immediate_operand" "i")] | |
2817 | VSHLLBQ_N)) | |
2818 | ] | |
2819 | "TARGET_HAVE_MVE" | |
2820 | "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
2821 | [(set_attr "type" "mve_move") | |
2822 | ]) | |
2823 | ||
2824 | ;; | |
2825 | ;; [vshlltq_n_u, vshlltq_n_s]) | |
2826 | ;; | |
2827 | (define_insn "mve_vshlltq_n_<supf><mode>" | |
2828 | [ | |
2829 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2830 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
2831 | (match_operand:SI 2 "immediate_operand" "i")] | |
2832 | VSHLLTQ_N)) | |
2833 | ] | |
2834 | "TARGET_HAVE_MVE" | |
2835 | "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
2836 | [(set_attr "type" "mve_move") | |
2837 | ]) | |
2838 | ||
2839 | ;; | |
2840 | ;; [vsubq_f]) | |
2841 | ;; | |
2842 | (define_insn "mve_vsubq_f<mode>" | |
2843 | [ | |
2844 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2845 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2846 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2847 | VSUBQ_F)) | |
2848 | ] | |
2849 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2850 | "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2" | |
2851 | [(set_attr "type" "mve_move") | |
2852 | ]) | |
2853 | ||
2854 | ;; | |
2855 | ;; [vmulltq_poly_p]) | |
2856 | ;; | |
2857 | (define_insn "mve_vmulltq_poly_p<mode>" | |
2858 | [ | |
2859 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2860 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
2861 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
2862 | VMULLTQ_POLY_P)) | |
2863 | ] | |
2864 | "TARGET_HAVE_MVE" | |
2865 | "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
2866 | [(set_attr "type" "mve_move") | |
2867 | ]) | |
2868 | ||
2869 | ;; | |
2870 | ;; [vmullbq_poly_p]) | |
2871 | ;; | |
2872 | (define_insn "mve_vmullbq_poly_p<mode>" | |
2873 | [ | |
2874 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2875 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
2876 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
2877 | VMULLBQ_POLY_P)) | |
2878 | ] | |
2879 | "TARGET_HAVE_MVE" | |
2880 | "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
2881 | [(set_attr "type" "mve_move") | |
2882 | ]) | |
2883 | ||
2884 | ;; | |
2885 | ;; [vrmlaldavhq_u vrmlaldavhq_s]) | |
2886 | ;; | |
2887 | (define_insn "mve_vrmlaldavhq_<supf>v4si" | |
2888 | [ | |
2889 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2890 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2891 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2892 | VRMLALDAVHQ)) | |
2893 | ] | |
2894 | "TARGET_HAVE_MVE" | |
2895 | "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2" | |
2896 | [(set_attr "type" "mve_move") | |
2897 | ]) | |
0dad5b33 SP |
2898 | |
2899 | ;; | |
2900 | ;; [vbicq_m_n_s, vbicq_m_n_u]) | |
2901 | ;; | |
2902 | (define_insn "mve_vbicq_m_n_<supf><mode>" | |
2903 | [ | |
2904 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2905 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2906 | (match_operand:SI 2 "immediate_operand" "i") | |
2907 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
2908 | VBICQ_M_N)) | |
2909 | ] | |
2910 | "TARGET_HAVE_MVE" | |
2911 | "vpst\;vbict.i%#<V_sz_elem> %q0, %2" | |
2912 | [(set_attr "type" "mve_move") | |
2913 | (set_attr "length""8")]) | |
2914 | ;; | |
2915 | ;; [vcmpeqq_m_f]) | |
2916 | ;; | |
2917 | (define_insn "mve_vcmpeqq_m_f<mode>" | |
2918 | [ | |
2919 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2920 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2921 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
2922 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
2923 | VCMPEQQ_M_F)) | |
2924 | ] | |
2925 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2926 | "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2" | |
2927 | [(set_attr "type" "mve_move") | |
2928 | (set_attr "length""8")]) | |
2929 | ;; | |
2930 | ;; [vcvtaq_m_u, vcvtaq_m_s]) | |
2931 | ;; | |
2932 | (define_insn "mve_vcvtaq_m_<supf><mode>" | |
2933 | [ | |
2934 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2935 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2936 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
2937 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
2938 | VCVTAQ_M)) | |
2939 | ] | |
2940 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2941 | "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" | |
2942 | [(set_attr "type" "mve_move") | |
2943 | (set_attr "length""8")]) | |
2944 | ;; | |
2945 | ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) | |
2946 | ;; | |
2947 | (define_insn "mve_vcvtq_m_to_f_<supf><mode>" | |
2948 | [ | |
2949 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2950 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2951 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
2952 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
2953 | VCVTQ_M_TO_F)) | |
2954 | ] | |
2955 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2956 | "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2" | |
2957 | [(set_attr "type" "mve_move") | |
2958 | (set_attr "length""8")]) | |
2959 | ;; | |
2960 | ;; [vqrshrnbq_n_u, vqrshrnbq_n_s]) | |
2961 | ;; | |
2962 | (define_insn "mve_vqrshrnbq_n_<supf><mode>" | |
2963 | [ | |
2964 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2965 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2966 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
2967 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
2968 | VQRSHRNBQ_N)) | |
2969 | ] | |
2970 | "TARGET_HAVE_MVE" | |
2971 | "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
2972 | [(set_attr "type" "mve_move") | |
2973 | ]) | |
2974 | ;; | |
2975 | ;; [vqrshrunbq_n_s]) | |
2976 | ;; | |
2977 | (define_insn "mve_vqrshrunbq_n_s<mode>" | |
2978 | [ | |
2979 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2980 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2981 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
2982 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
2983 | VQRSHRUNBQ_N_S)) | |
2984 | ] | |
2985 | "TARGET_HAVE_MVE" | |
2986 | "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3" | |
2987 | [(set_attr "type" "mve_move") | |
2988 | ]) | |
2989 | ;; | |
2990 | ;; [vrmlaldavhaq_s vrmlaldavhaq_u]) | |
2991 | ;; | |
2992 | (define_insn "mve_vrmlaldavhaq_<supf>v4si" | |
2993 | [ | |
2994 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2995 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2996 | (match_operand:V4SI 2 "s_register_operand" "w") | |
2997 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
2998 | VRMLALDAVHAQ)) | |
2999 | ] | |
3000 | "TARGET_HAVE_MVE" | |
3001 | "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3" | |
3002 | [(set_attr "type" "mve_move") | |
3003 | ]) | |
3004 | ||
3005 | ;; | |
3006 | ;; [vabavq_s, vabavq_u]) | |
3007 | ;; | |
3008 | (define_insn "mve_vabavq_<supf><mode>" | |
3009 | [ | |
3010 | (set (match_operand:SI 0 "s_register_operand" "=r") | |
3011 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
3012 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3013 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3014 | VABAVQ)) | |
3015 | ] | |
3016 | "TARGET_HAVE_MVE" | |
3017 | "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3" | |
3018 | [(set_attr "type" "mve_move") | |
3019 | ]) | |
3020 | ||
3021 | ;; | |
3022 | ;; [vshlcq_u vshlcq_s] | |
3023 | ;; | |
3024 | (define_expand "mve_vshlcq_vec_<supf><mode>" | |
3025 | [(match_operand:MVE_2 0 "s_register_operand") | |
3026 | (match_operand:MVE_2 1 "s_register_operand") | |
3027 | (match_operand:SI 2 "s_register_operand") | |
3028 | (match_operand:SI 3 "mve_imm_32") | |
3029 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
3030 | "TARGET_HAVE_MVE" | |
3031 | { | |
3032 | rtx ignore_wb = gen_reg_rtx (SImode); | |
3033 | emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], | |
8165795c | 3034 | operands[2], operands[3])); |
0dad5b33 SP |
3035 | DONE; |
3036 | }) | |
3037 | ||
3038 | (define_expand "mve_vshlcq_carry_<supf><mode>" | |
3039 | [(match_operand:SI 0 "s_register_operand") | |
3040 | (match_operand:MVE_2 1 "s_register_operand") | |
3041 | (match_operand:SI 2 "s_register_operand") | |
3042 | (match_operand:SI 3 "mve_imm_32") | |
3043 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
3044 | "TARGET_HAVE_MVE" | |
3045 | { | |
3046 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
3047 | emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], | |
3048 | operands[2], operands[3])); | |
3049 | DONE; | |
3050 | }) | |
3051 | ||
3052 | (define_insn "mve_vshlcq_<supf><mode>" | |
3053 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3054 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") | |
3055 | (match_operand:SI 3 "s_register_operand" "1") | |
3056 | (match_operand:SI 4 "mve_imm_32" "Rf")] | |
3057 | VSHLCQ)) | |
3058 | (set (match_operand:SI 1 "s_register_operand" "=r") | |
3059 | (unspec:SI [(match_dup 2) | |
3060 | (match_dup 3) | |
3061 | (match_dup 4)] | |
3062 | VSHLCQ))] | |
3063 | "TARGET_HAVE_MVE" | |
3064 | "vshlc %q0, %1, %4") | |
8165795c SP |
3065 | |
3066 | ;; | |
3067 | ;; [vabsq_m_s]) | |
3068 | ;; | |
3069 | (define_insn "mve_vabsq_m_s<mode>" | |
3070 | [ | |
3071 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3072 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3073 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3074 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3075 | VABSQ_M_S)) | |
3076 | ] | |
3077 | "TARGET_HAVE_MVE" | |
3078 | "vpst\;vabst.s%#<V_sz_elem> %q0, %q2" | |
3079 | [(set_attr "type" "mve_move") | |
3080 | (set_attr "length""8")]) | |
3081 | ||
3082 | ;; | |
3083 | ;; [vaddvaq_p_u, vaddvaq_p_s]) | |
3084 | ;; | |
3085 | (define_insn "mve_vaddvaq_p_<supf><mode>" | |
3086 | [ | |
3d537943 | 3087 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3088 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
3089 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3090 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3091 | VADDVAQ_P)) | |
3092 | ] | |
3093 | "TARGET_HAVE_MVE" | |
3094 | "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2" | |
3095 | [(set_attr "type" "mve_move") | |
3096 | (set_attr "length""8")]) | |
3097 | ||
3098 | ;; | |
3099 | ;; [vclsq_m_s]) | |
3100 | ;; | |
3101 | (define_insn "mve_vclsq_m_s<mode>" | |
3102 | [ | |
3103 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3104 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3105 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3106 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3107 | VCLSQ_M_S)) | |
3108 | ] | |
3109 | "TARGET_HAVE_MVE" | |
3110 | "vpst\;vclst.s%#<V_sz_elem> %q0, %q2" | |
3111 | [(set_attr "type" "mve_move") | |
3112 | (set_attr "length""8")]) | |
3113 | ||
3114 | ;; | |
3115 | ;; [vclzq_m_s, vclzq_m_u]) | |
3116 | ;; | |
3117 | (define_insn "mve_vclzq_m_<supf><mode>" | |
3118 | [ | |
3119 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3120 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3121 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3122 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3123 | VCLZQ_M)) | |
3124 | ] | |
3125 | "TARGET_HAVE_MVE" | |
3126 | "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2" | |
3127 | [(set_attr "type" "mve_move") | |
3128 | (set_attr "length""8")]) | |
3129 | ||
3130 | ;; | |
3131 | ;; [vcmpcsq_m_n_u]) | |
3132 | ;; | |
3133 | (define_insn "mve_vcmpcsq_m_n_u<mode>" | |
3134 | [ | |
3135 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3136 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3137 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3138 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3139 | VCMPCSQ_M_N_U)) | |
3140 | ] | |
3141 | "TARGET_HAVE_MVE" | |
3142 | "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2" | |
3143 | [(set_attr "type" "mve_move") | |
3144 | (set_attr "length""8")]) | |
3145 | ||
3146 | ;; | |
3147 | ;; [vcmpcsq_m_u]) | |
3148 | ;; | |
3149 | (define_insn "mve_vcmpcsq_m_u<mode>" | |
3150 | [ | |
3151 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3152 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3153 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3154 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3155 | VCMPCSQ_M_U)) | |
3156 | ] | |
3157 | "TARGET_HAVE_MVE" | |
3158 | "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2" | |
3159 | [(set_attr "type" "mve_move") | |
3160 | (set_attr "length""8")]) | |
3161 | ||
3162 | ;; | |
3163 | ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s]) | |
3164 | ;; | |
3165 | (define_insn "mve_vcmpeqq_m_n_<supf><mode>" | |
3166 | [ | |
3167 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3168 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3169 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3170 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3171 | VCMPEQQ_M_N)) | |
3172 | ] | |
3173 | "TARGET_HAVE_MVE" | |
3174 | "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2" | |
3175 | [(set_attr "type" "mve_move") | |
3176 | (set_attr "length""8")]) | |
3177 | ||
3178 | ;; | |
3179 | ;; [vcmpeqq_m_u, vcmpeqq_m_s]) | |
3180 | ;; | |
3181 | (define_insn "mve_vcmpeqq_m_<supf><mode>" | |
3182 | [ | |
3183 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3184 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3185 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3186 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3187 | VCMPEQQ_M)) | |
3188 | ] | |
3189 | "TARGET_HAVE_MVE" | |
3190 | "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2" | |
3191 | [(set_attr "type" "mve_move") | |
3192 | (set_attr "length""8")]) | |
3193 | ||
3194 | ;; | |
3195 | ;; [vcmpgeq_m_n_s]) | |
3196 | ;; | |
3197 | (define_insn "mve_vcmpgeq_m_n_s<mode>" | |
3198 | [ | |
3199 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3200 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3201 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3202 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3203 | VCMPGEQ_M_N_S)) | |
3204 | ] | |
3205 | "TARGET_HAVE_MVE" | |
3206 | "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2" | |
3207 | [(set_attr "type" "mve_move") | |
3208 | (set_attr "length""8")]) | |
3209 | ||
3210 | ;; | |
3211 | ;; [vcmpgeq_m_s]) | |
3212 | ;; | |
3213 | (define_insn "mve_vcmpgeq_m_s<mode>" | |
3214 | [ | |
3215 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3216 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3217 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3218 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3219 | VCMPGEQ_M_S)) | |
3220 | ] | |
3221 | "TARGET_HAVE_MVE" | |
3222 | "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2" | |
3223 | [(set_attr "type" "mve_move") | |
3224 | (set_attr "length""8")]) | |
3225 | ||
3226 | ;; | |
3227 | ;; [vcmpgtq_m_n_s]) | |
3228 | ;; | |
3229 | (define_insn "mve_vcmpgtq_m_n_s<mode>" | |
3230 | [ | |
3231 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3232 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3233 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3234 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3235 | VCMPGTQ_M_N_S)) | |
3236 | ] | |
3237 | "TARGET_HAVE_MVE" | |
3238 | "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2" | |
3239 | [(set_attr "type" "mve_move") | |
3240 | (set_attr "length""8")]) | |
3241 | ||
3242 | ;; | |
3243 | ;; [vcmpgtq_m_s]) | |
3244 | ;; | |
3245 | (define_insn "mve_vcmpgtq_m_s<mode>" | |
3246 | [ | |
3247 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3248 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3249 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3250 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3251 | VCMPGTQ_M_S)) | |
3252 | ] | |
3253 | "TARGET_HAVE_MVE" | |
3254 | "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2" | |
3255 | [(set_attr "type" "mve_move") | |
3256 | (set_attr "length""8")]) | |
3257 | ||
3258 | ;; | |
3259 | ;; [vcmphiq_m_n_u]) | |
3260 | ;; | |
3261 | (define_insn "mve_vcmphiq_m_n_u<mode>" | |
3262 | [ | |
3263 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3264 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3265 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3266 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3267 | VCMPHIQ_M_N_U)) | |
3268 | ] | |
3269 | "TARGET_HAVE_MVE" | |
3270 | "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2" | |
3271 | [(set_attr "type" "mve_move") | |
3272 | (set_attr "length""8")]) | |
3273 | ||
3274 | ;; | |
3275 | ;; [vcmphiq_m_u]) | |
3276 | ;; | |
3277 | (define_insn "mve_vcmphiq_m_u<mode>" | |
3278 | [ | |
3279 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3280 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3281 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3282 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3283 | VCMPHIQ_M_U)) | |
3284 | ] | |
3285 | "TARGET_HAVE_MVE" | |
3286 | "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2" | |
3287 | [(set_attr "type" "mve_move") | |
3288 | (set_attr "length""8")]) | |
3289 | ||
3290 | ;; | |
3291 | ;; [vcmpleq_m_n_s]) | |
3292 | ;; | |
3293 | (define_insn "mve_vcmpleq_m_n_s<mode>" | |
3294 | [ | |
3295 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3296 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3297 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3298 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3299 | VCMPLEQ_M_N_S)) | |
3300 | ] | |
3301 | "TARGET_HAVE_MVE" | |
3302 | "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2" | |
3303 | [(set_attr "type" "mve_move") | |
3304 | (set_attr "length""8")]) | |
3305 | ||
3306 | ;; | |
3307 | ;; [vcmpleq_m_s]) | |
3308 | ;; | |
3309 | (define_insn "mve_vcmpleq_m_s<mode>" | |
3310 | [ | |
3311 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3312 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3313 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3314 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3315 | VCMPLEQ_M_S)) | |
3316 | ] | |
3317 | "TARGET_HAVE_MVE" | |
3318 | "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2" | |
3319 | [(set_attr "type" "mve_move") | |
3320 | (set_attr "length""8")]) | |
3321 | ||
3322 | ;; | |
3323 | ;; [vcmpltq_m_n_s]) | |
3324 | ;; | |
3325 | (define_insn "mve_vcmpltq_m_n_s<mode>" | |
3326 | [ | |
3327 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3328 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3329 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3330 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3331 | VCMPLTQ_M_N_S)) | |
3332 | ] | |
3333 | "TARGET_HAVE_MVE" | |
3334 | "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2" | |
3335 | [(set_attr "type" "mve_move") | |
3336 | (set_attr "length""8")]) | |
3337 | ||
3338 | ;; | |
3339 | ;; [vcmpltq_m_s]) | |
3340 | ;; | |
3341 | (define_insn "mve_vcmpltq_m_s<mode>" | |
3342 | [ | |
3343 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3344 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3345 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3346 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3347 | VCMPLTQ_M_S)) | |
3348 | ] | |
3349 | "TARGET_HAVE_MVE" | |
3350 | "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2" | |
3351 | [(set_attr "type" "mve_move") | |
3352 | (set_attr "length""8")]) | |
3353 | ||
3354 | ;; | |
3355 | ;; [vcmpneq_m_n_u, vcmpneq_m_n_s]) | |
3356 | ;; | |
3357 | (define_insn "mve_vcmpneq_m_n_<supf><mode>" | |
3358 | [ | |
3359 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3360 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3361 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3362 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3363 | VCMPNEQ_M_N)) | |
3364 | ] | |
3365 | "TARGET_HAVE_MVE" | |
3366 | "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2" | |
3367 | [(set_attr "type" "mve_move") | |
3368 | (set_attr "length""8")]) | |
3369 | ||
3370 | ;; | |
3371 | ;; [vcmpneq_m_s, vcmpneq_m_u]) | |
3372 | ;; | |
3373 | (define_insn "mve_vcmpneq_m_<supf><mode>" | |
3374 | [ | |
3375 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3376 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
3377 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3378 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3379 | VCMPNEQ_M)) | |
3380 | ] | |
3381 | "TARGET_HAVE_MVE" | |
3382 | "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2" | |
3383 | [(set_attr "type" "mve_move") | |
3384 | (set_attr "length""8")]) | |
3385 | ||
3386 | ;; | |
3387 | ;; [vdupq_m_n_s, vdupq_m_n_u]) | |
3388 | ;; | |
3389 | (define_insn "mve_vdupq_m_n_<supf><mode>" | |
3390 | [ | |
3391 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3392 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3393 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
3394 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3395 | VDUPQ_M_N)) | |
3396 | ] | |
3397 | "TARGET_HAVE_MVE" | |
3398 | "vpst\;vdupt.%#<V_sz_elem> %q0, %2" | |
3399 | [(set_attr "type" "mve_move") | |
3400 | (set_attr "length""8")]) | |
3401 | ||
3402 | ;; | |
3403 | ;; [vmaxaq_m_s]) | |
3404 | ;; | |
3405 | (define_insn "mve_vmaxaq_m_s<mode>" | |
3406 | [ | |
3407 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3408 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3409 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3410 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3411 | VMAXAQ_M_S)) | |
3412 | ] | |
3413 | "TARGET_HAVE_MVE" | |
3414 | "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2" | |
3415 | [(set_attr "type" "mve_move") | |
3416 | (set_attr "length""8")]) | |
3417 | ||
3418 | ;; | |
3419 | ;; [vmaxavq_p_s]) | |
3420 | ;; | |
3421 | (define_insn "mve_vmaxavq_p_s<mode>" | |
3422 | [ | |
3423 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
3424 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
3425 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3426 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3427 | VMAXAVQ_P_S)) | |
3428 | ] | |
3429 | "TARGET_HAVE_MVE" | |
3430 | "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2" | |
3431 | [(set_attr "type" "mve_move") | |
3432 | (set_attr "length""8")]) | |
3433 | ||
3434 | ;; | |
3435 | ;; [vmaxvq_p_u, vmaxvq_p_s]) | |
3436 | ;; | |
3437 | (define_insn "mve_vmaxvq_p_<supf><mode>" | |
3438 | [ | |
3439 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
3440 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
3441 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3442 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3443 | VMAXVQ_P)) | |
3444 | ] | |
3445 | "TARGET_HAVE_MVE" | |
3446 | "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2" | |
3447 | [(set_attr "type" "mve_move") | |
3448 | (set_attr "length""8")]) | |
3449 | ||
3450 | ;; | |
3451 | ;; [vminaq_m_s]) | |
3452 | ;; | |
3453 | (define_insn "mve_vminaq_m_s<mode>" | |
3454 | [ | |
3455 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3456 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3457 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3458 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3459 | VMINAQ_M_S)) | |
3460 | ] | |
3461 | "TARGET_HAVE_MVE" | |
3462 | "vpst\;vminat.s%#<V_sz_elem> %q0, %q2" | |
3463 | [(set_attr "type" "mve_move") | |
3464 | (set_attr "length""8")]) | |
3465 | ||
3466 | ;; | |
3467 | ;; [vminavq_p_s]) | |
3468 | ;; | |
3469 | (define_insn "mve_vminavq_p_s<mode>" | |
3470 | [ | |
3471 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
3472 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
3473 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3474 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3475 | VMINAVQ_P_S)) | |
3476 | ] | |
3477 | "TARGET_HAVE_MVE" | |
3478 | "vpst\;vminavt.s%#<V_sz_elem> %0, %q2" | |
3479 | [(set_attr "type" "mve_move") | |
3480 | (set_attr "length""8")]) | |
3481 | ||
3482 | ;; | |
3483 | ;; [vminvq_p_s, vminvq_p_u]) | |
3484 | ;; | |
3485 | (define_insn "mve_vminvq_p_<supf><mode>" | |
3486 | [ | |
3487 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
3488 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
3489 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3490 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3491 | VMINVQ_P)) | |
3492 | ] | |
3493 | "TARGET_HAVE_MVE" | |
3494 | "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2" | |
3495 | [(set_attr "type" "mve_move") | |
3496 | (set_attr "length""8")]) | |
3497 | ||
3498 | ;; | |
3499 | ;; [vmladavaq_u, vmladavaq_s]) | |
3500 | ;; | |
3501 | (define_insn "mve_vmladavaq_<supf><mode>" | |
3502 | [ | |
3d537943 | 3503 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3504 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
3505 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3506 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3507 | VMLADAVAQ)) | |
3508 | ] | |
3509 | "TARGET_HAVE_MVE" | |
3510 | "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3" | |
3511 | [(set_attr "type" "mve_move") | |
3512 | ]) | |
3513 | ||
3514 | ;; | |
3515 | ;; [vmladavq_p_u, vmladavq_p_s]) | |
3516 | ;; | |
3517 | (define_insn "mve_vmladavq_p_<supf><mode>" | |
3518 | [ | |
3d537943 | 3519 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3520 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
3521 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3522 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3523 | VMLADAVQ_P)) | |
3524 | ] | |
3525 | "TARGET_HAVE_MVE" | |
3526 | "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2" | |
3527 | [(set_attr "type" "mve_move") | |
3528 | (set_attr "length""8")]) | |
3529 | ||
3530 | ;; | |
3531 | ;; [vmladavxq_p_s]) | |
3532 | ;; | |
3533 | (define_insn "mve_vmladavxq_p_s<mode>" | |
3534 | [ | |
3d537943 | 3535 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3536 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
3537 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3538 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3539 | VMLADAVXQ_P_S)) | |
3540 | ] | |
3541 | "TARGET_HAVE_MVE" | |
3542 | "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2" | |
3543 | [(set_attr "type" "mve_move") | |
3544 | (set_attr "length""8")]) | |
3545 | ||
3546 | ;; | |
3547 | ;; [vmlaq_n_u, vmlaq_n_s]) | |
3548 | ;; | |
3549 | (define_insn "mve_vmlaq_n_<supf><mode>" | |
3550 | [ | |
3551 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3552 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3553 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3554 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3555 | VMLAQ_N)) | |
3556 | ] | |
3557 | "TARGET_HAVE_MVE" | |
3558 | "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
3559 | [(set_attr "type" "mve_move") | |
3560 | ]) | |
3561 | ||
3562 | ;; | |
3563 | ;; [vmlasq_n_u, vmlasq_n_s]) | |
3564 | ;; | |
3565 | (define_insn "mve_vmlasq_n_<supf><mode>" | |
3566 | [ | |
3567 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3568 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3569 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3570 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3571 | VMLASQ_N)) | |
3572 | ] | |
3573 | "TARGET_HAVE_MVE" | |
3574 | "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
3575 | [(set_attr "type" "mve_move") | |
3576 | ]) | |
3577 | ||
3578 | ;; | |
3579 | ;; [vmlsdavq_p_s]) | |
3580 | ;; | |
3581 | (define_insn "mve_vmlsdavq_p_s<mode>" | |
3582 | [ | |
3d537943 | 3583 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3584 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
3585 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3586 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3587 | VMLSDAVQ_P_S)) | |
3588 | ] | |
3589 | "TARGET_HAVE_MVE" | |
3590 | "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2" | |
3591 | [(set_attr "type" "mve_move") | |
3592 | (set_attr "length""8")]) | |
3593 | ||
3594 | ;; | |
3595 | ;; [vmlsdavxq_p_s]) | |
3596 | ;; | |
3597 | (define_insn "mve_vmlsdavxq_p_s<mode>" | |
3598 | [ | |
3d537943 | 3599 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
3600 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
3601 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3602 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3603 | VMLSDAVXQ_P_S)) | |
3604 | ] | |
3605 | "TARGET_HAVE_MVE" | |
3606 | "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2" | |
3607 | [(set_attr "type" "mve_move") | |
3608 | (set_attr "length""8")]) | |
3609 | ||
3610 | ;; | |
3611 | ;; [vmvnq_m_s, vmvnq_m_u]) | |
3612 | ;; | |
3613 | (define_insn "mve_vmvnq_m_<supf><mode>" | |
3614 | [ | |
3615 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3616 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3617 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3618 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3619 | VMVNQ_M)) | |
3620 | ] | |
3621 | "TARGET_HAVE_MVE" | |
3622 | "vpst\;vmvnt %q0, %q2" | |
3623 | [(set_attr "type" "mve_move") | |
3624 | (set_attr "length""8")]) | |
3625 | ||
3626 | ;; | |
3627 | ;; [vnegq_m_s]) | |
3628 | ;; | |
3629 | (define_insn "mve_vnegq_m_s<mode>" | |
3630 | [ | |
3631 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3632 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3633 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3634 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3635 | VNEGQ_M_S)) | |
3636 | ] | |
3637 | "TARGET_HAVE_MVE" | |
3638 | "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2" | |
3639 | [(set_attr "type" "mve_move") | |
3640 | (set_attr "length""8")]) | |
3641 | ||
3642 | ;; | |
3643 | ;; [vpselq_u, vpselq_s]) | |
3644 | ;; | |
3645 | (define_insn "mve_vpselq_<supf><mode>" | |
3646 | [ | |
3647 | (set (match_operand:MVE_1 0 "s_register_operand" "=w") | |
3648 | (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") | |
3649 | (match_operand:MVE_1 2 "s_register_operand" "w") | |
3650 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3651 | VPSELQ)) | |
3652 | ] | |
3653 | "TARGET_HAVE_MVE" | |
3654 | "vpsel %q0, %q1, %q2" | |
3655 | [(set_attr "type" "mve_move") | |
3656 | ]) | |
3657 | ||
3658 | ;; | |
3659 | ;; [vqabsq_m_s]) | |
3660 | ;; | |
3661 | (define_insn "mve_vqabsq_m_s<mode>" | |
3662 | [ | |
3663 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3664 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3665 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3666 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3667 | VQABSQ_M_S)) | |
3668 | ] | |
3669 | "TARGET_HAVE_MVE" | |
3670 | "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2" | |
3671 | [(set_attr "type" "mve_move") | |
3672 | (set_attr "length""8")]) | |
3673 | ||
3674 | ;; | |
237f12da | 3675 | ;; [vqdmlahq_n_s]) |
8165795c SP |
3676 | ;; |
3677 | (define_insn "mve_vqdmlahq_n_<supf><mode>" | |
3678 | [ | |
3679 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3680 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3681 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3682 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3683 | VQDMLAHQ_N)) | |
3684 | ] | |
3685 | "TARGET_HAVE_MVE" | |
3686 | "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3687 | [(set_attr "type" "mve_move") | |
3688 | ]) | |
3689 | ||
afb198ee CL |
3690 | ;; |
3691 | ;; [vqdmlashq_n_s]) | |
3692 | ;; | |
3693 | (define_insn "mve_vqdmlashq_n_<supf><mode>" | |
3694 | [ | |
3695 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3696 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3697 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3698 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3699 | VQDMLASHQ_N)) | |
3700 | ] | |
3701 | "TARGET_HAVE_MVE" | |
3702 | "vqdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3703 | [(set_attr "type" "mve_move") | |
3704 | ]) | |
3705 | ||
8165795c SP |
3706 | ;; |
3707 | ;; [vqnegq_m_s]) | |
3708 | ;; | |
3709 | (define_insn "mve_vqnegq_m_s<mode>" | |
3710 | [ | |
3711 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3712 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3713 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3714 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3715 | VQNEGQ_M_S)) | |
3716 | ] | |
3717 | "TARGET_HAVE_MVE" | |
3718 | "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2" | |
3719 | [(set_attr "type" "mve_move") | |
3720 | (set_attr "length""8")]) | |
3721 | ||
3722 | ;; | |
3723 | ;; [vqrdmladhq_s]) | |
3724 | ;; | |
3725 | (define_insn "mve_vqrdmladhq_s<mode>" | |
3726 | [ | |
3727 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3728 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3729 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3730 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3731 | VQRDMLADHQ_S)) | |
3732 | ] | |
3733 | "TARGET_HAVE_MVE" | |
3734 | "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3735 | [(set_attr "type" "mve_move") | |
3736 | ]) | |
3737 | ||
3738 | ;; | |
3739 | ;; [vqrdmladhxq_s]) | |
3740 | ;; | |
3741 | (define_insn "mve_vqrdmladhxq_s<mode>" | |
3742 | [ | |
3743 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3744 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3745 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3746 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3747 | VQRDMLADHXQ_S)) | |
3748 | ] | |
3749 | "TARGET_HAVE_MVE" | |
3750 | "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3751 | [(set_attr "type" "mve_move") | |
3752 | ]) | |
3753 | ||
3754 | ;; | |
237f12da | 3755 | ;; [vqrdmlahq_n_s]) |
8165795c SP |
3756 | ;; |
3757 | (define_insn "mve_vqrdmlahq_n_<supf><mode>" | |
3758 | [ | |
3759 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3760 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3761 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3762 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3763 | VQRDMLAHQ_N)) | |
3764 | ] | |
3765 | "TARGET_HAVE_MVE" | |
3766 | "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3767 | [(set_attr "type" "mve_move") | |
3768 | ]) | |
3769 | ||
3770 | ;; | |
237f12da | 3771 | ;; [vqrdmlashq_n_s]) |
8165795c SP |
3772 | ;; |
3773 | (define_insn "mve_vqrdmlashq_n_<supf><mode>" | |
3774 | [ | |
3775 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3776 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3777 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3778 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
3779 | VQRDMLASHQ_N)) | |
3780 | ] | |
3781 | "TARGET_HAVE_MVE" | |
3782 | "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3783 | [(set_attr "type" "mve_move") | |
3784 | ]) | |
3785 | ||
3786 | ;; | |
3787 | ;; [vqrdmlsdhq_s]) | |
3788 | ;; | |
3789 | (define_insn "mve_vqrdmlsdhq_s<mode>" | |
3790 | [ | |
3791 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3792 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3793 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3794 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3795 | VQRDMLSDHQ_S)) | |
3796 | ] | |
3797 | "TARGET_HAVE_MVE" | |
3798 | "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3799 | [(set_attr "type" "mve_move") | |
3800 | ]) | |
3801 | ||
3802 | ;; | |
3803 | ;; [vqrdmlsdhxq_s]) | |
3804 | ;; | |
3805 | (define_insn "mve_vqrdmlsdhxq_s<mode>" | |
3806 | [ | |
3807 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3808 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3809 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3810 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3811 | VQRDMLSDHXQ_S)) | |
3812 | ] | |
3813 | "TARGET_HAVE_MVE" | |
3814 | "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3815 | [(set_attr "type" "mve_move") | |
3816 | ]) | |
3817 | ||
3818 | ;; | |
3819 | ;; [vqrshlq_m_n_s, vqrshlq_m_n_u]) | |
3820 | ;; | |
3821 | (define_insn "mve_vqrshlq_m_n_<supf><mode>" | |
3822 | [ | |
3823 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3824 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3825 | (match_operand:SI 2 "s_register_operand" "r") | |
3826 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3827 | VQRSHLQ_M_N)) | |
3828 | ] | |
3829 | "TARGET_HAVE_MVE" | |
3830 | "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2" | |
3831 | [(set_attr "type" "mve_move") | |
3832 | (set_attr "length""8")]) | |
3833 | ||
3834 | ;; | |
3835 | ;; [vqshlq_m_r_u, vqshlq_m_r_s]) | |
3836 | ;; | |
3837 | (define_insn "mve_vqshlq_m_r_<supf><mode>" | |
3838 | [ | |
3839 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3840 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3841 | (match_operand:SI 2 "s_register_operand" "r") | |
3842 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3843 | VQSHLQ_M_R)) | |
3844 | ] | |
3845 | "TARGET_HAVE_MVE" | |
3846 | "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2" | |
3847 | [(set_attr "type" "mve_move") | |
3848 | (set_attr "length""8")]) | |
3849 | ||
3850 | ;; | |
3851 | ;; [vrev64q_m_u, vrev64q_m_s]) | |
3852 | ;; | |
3853 | (define_insn "mve_vrev64q_m_<supf><mode>" | |
3854 | [ | |
3855 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3856 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3857 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3858 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3859 | VREV64Q_M)) | |
3860 | ] | |
3861 | "TARGET_HAVE_MVE" | |
3862 | "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2" | |
3863 | [(set_attr "type" "mve_move") | |
3864 | (set_attr "length""8")]) | |
3865 | ||
3866 | ;; | |
3867 | ;; [vrshlq_m_n_s, vrshlq_m_n_u]) | |
3868 | ;; | |
3869 | (define_insn "mve_vrshlq_m_n_<supf><mode>" | |
3870 | [ | |
3871 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3872 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3873 | (match_operand:SI 2 "s_register_operand" "r") | |
3874 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3875 | VRSHLQ_M_N)) | |
3876 | ] | |
3877 | "TARGET_HAVE_MVE" | |
3878 | "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2" | |
3879 | [(set_attr "type" "mve_move") | |
3880 | (set_attr "length""8")]) | |
3881 | ||
3882 | ;; | |
3883 | ;; [vshlq_m_r_u, vshlq_m_r_s]) | |
3884 | ;; | |
3885 | (define_insn "mve_vshlq_m_r_<supf><mode>" | |
3886 | [ | |
3887 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3888 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3889 | (match_operand:SI 2 "s_register_operand" "r") | |
3890 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3891 | VSHLQ_M_R)) | |
3892 | ] | |
3893 | "TARGET_HAVE_MVE" | |
3894 | "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2" | |
3895 | [(set_attr "type" "mve_move") | |
3896 | (set_attr "length""8")]) | |
3897 | ||
3898 | ;; | |
3899 | ;; [vsliq_n_u, vsliq_n_s]) | |
3900 | ;; | |
3901 | (define_insn "mve_vsliq_n_<supf><mode>" | |
3902 | [ | |
3903 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3904 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3905 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3906 | (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")] | |
3907 | VSLIQ_N)) | |
3908 | ] | |
3909 | "TARGET_HAVE_MVE" | |
3910 | "vsli.%#<V_sz_elem>\t%q0, %q2, %3" | |
3911 | [(set_attr "type" "mve_move") | |
3912 | ]) | |
3913 | ||
3914 | ;; | |
3915 | ;; [vsriq_n_u, vsriq_n_s]) | |
3916 | ;; | |
3917 | (define_insn "mve_vsriq_n_<supf><mode>" | |
3918 | [ | |
3919 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3920 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3921 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3922 | (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] | |
3923 | VSRIQ_N)) | |
3924 | ] | |
3925 | "TARGET_HAVE_MVE" | |
3926 | "vsri.%#<V_sz_elem>\t%q0, %q2, %3" | |
3927 | [(set_attr "type" "mve_move") | |
3928 | ]) | |
3929 | ||
3930 | ;; | |
3931 | ;; [vqdmlsdhxq_s]) | |
3932 | ;; | |
3933 | (define_insn "mve_vqdmlsdhxq_s<mode>" | |
3934 | [ | |
3935 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3936 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3937 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3938 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3939 | VQDMLSDHXQ_S)) | |
3940 | ] | |
3941 | "TARGET_HAVE_MVE" | |
3942 | "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3943 | [(set_attr "type" "mve_move") | |
3944 | ]) | |
3945 | ||
3946 | ;; | |
3947 | ;; [vqdmlsdhq_s]) | |
3948 | ;; | |
3949 | (define_insn "mve_vqdmlsdhq_s<mode>" | |
3950 | [ | |
3951 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3952 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3953 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3954 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3955 | VQDMLSDHQ_S)) | |
3956 | ] | |
3957 | "TARGET_HAVE_MVE" | |
3958 | "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3959 | [(set_attr "type" "mve_move") | |
3960 | ]) | |
3961 | ||
3962 | ;; | |
3963 | ;; [vqdmladhxq_s]) | |
3964 | ;; | |
3965 | (define_insn "mve_vqdmladhxq_s<mode>" | |
3966 | [ | |
3967 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3968 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3969 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3970 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3971 | VQDMLADHXQ_S)) | |
3972 | ] | |
3973 | "TARGET_HAVE_MVE" | |
3974 | "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3975 | [(set_attr "type" "mve_move") | |
3976 | ]) | |
3977 | ||
3978 | ;; | |
3979 | ;; [vqdmladhq_s]) | |
3980 | ;; | |
3981 | (define_insn "mve_vqdmladhq_s<mode>" | |
3982 | [ | |
3983 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3984 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3985 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3986 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3987 | VQDMLADHQ_S)) | |
3988 | ] | |
3989 | "TARGET_HAVE_MVE" | |
3990 | "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3991 | [(set_attr "type" "mve_move") | |
3992 | ]) | |
3993 | ||
3994 | ;; | |
3995 | ;; [vmlsdavaxq_s]) | |
3996 | ;; | |
3997 | (define_insn "mve_vmlsdavaxq_s<mode>" | |
3998 | [ | |
3d537943 | 3999 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
4000 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
4001 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
4002 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
4003 | VMLSDAVAXQ_S)) | |
4004 | ] | |
4005 | "TARGET_HAVE_MVE" | |
4006 | "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3" | |
4007 | [(set_attr "type" "mve_move") | |
4008 | ]) | |
4009 | ||
4010 | ;; | |
4011 | ;; [vmlsdavaq_s]) | |
4012 | ;; | |
4013 | (define_insn "mve_vmlsdavaq_s<mode>" | |
4014 | [ | |
3d537943 | 4015 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
4016 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
4017 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
4018 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
4019 | VMLSDAVAQ_S)) | |
4020 | ] | |
4021 | "TARGET_HAVE_MVE" | |
4022 | "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3" | |
4023 | [(set_attr "type" "mve_move") | |
4024 | ]) | |
4025 | ||
4026 | ;; | |
4027 | ;; [vmladavaxq_s]) | |
4028 | ;; | |
4029 | (define_insn "mve_vmladavaxq_s<mode>" | |
4030 | [ | |
3d537943 | 4031 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
4032 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
4033 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
4034 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
4035 | VMLADAVAXQ_S)) | |
4036 | ] | |
4037 | "TARGET_HAVE_MVE" | |
4038 | "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3" | |
4039 | [(set_attr "type" "mve_move") | |
4040 | ]) | |
e3678b44 SP |
4041 | ;; |
4042 | ;; [vabsq_m_f]) | |
4043 | ;; | |
4044 | (define_insn "mve_vabsq_m_f<mode>" | |
4045 | [ | |
4046 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4047 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4048 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4049 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4050 | VABSQ_M_F)) | |
4051 | ] | |
4052 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4053 | "vpst\;vabst.f%#<V_sz_elem> %q0, %q2" | |
4054 | [(set_attr "type" "mve_move") | |
4055 | (set_attr "length""8")]) | |
4056 | ||
4057 | ;; | |
4058 | ;; [vaddlvaq_p_s vaddlvaq_p_u]) | |
4059 | ;; | |
4060 | (define_insn "mve_vaddlvaq_p_<supf>v4si" | |
4061 | [ | |
4062 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4063 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
4064 | (match_operand:V4SI 2 "s_register_operand" "w") | |
4065 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4066 | VADDLVAQ_P)) | |
4067 | ] | |
4068 | "TARGET_HAVE_MVE" | |
4069 | "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2" | |
4070 | [(set_attr "type" "mve_move") | |
4071 | (set_attr "length""8")]) | |
4072 | ;; | |
4073 | ;; [vcmlaq_f]) | |
4074 | ;; | |
4075 | (define_insn "mve_vcmlaq_f<mode>" | |
4076 | [ | |
4077 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4078 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4079 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4080 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4081 | VCMLAQ_F)) | |
4082 | ] | |
4083 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4084 | "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0" | |
4085 | [(set_attr "type" "mve_move") | |
4086 | ]) | |
4087 | ||
4088 | ;; | |
4089 | ;; [vcmlaq_rot180_f]) | |
4090 | ;; | |
4091 | (define_insn "mve_vcmlaq_rot180_f<mode>" | |
4092 | [ | |
4093 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4094 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4095 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4096 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4097 | VCMLAQ_ROT180_F)) | |
4098 | ] | |
4099 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4100 | "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180" | |
4101 | [(set_attr "type" "mve_move") | |
4102 | ]) | |
4103 | ||
4104 | ;; | |
4105 | ;; [vcmlaq_rot270_f]) | |
4106 | ;; | |
4107 | (define_insn "mve_vcmlaq_rot270_f<mode>" | |
4108 | [ | |
4109 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4110 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4111 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4112 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4113 | VCMLAQ_ROT270_F)) | |
4114 | ] | |
4115 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4116 | "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
4117 | [(set_attr "type" "mve_move") | |
4118 | ]) | |
4119 | ||
4120 | ;; | |
4121 | ;; [vcmlaq_rot90_f]) | |
4122 | ;; | |
4123 | (define_insn "mve_vcmlaq_rot90_f<mode>" | |
4124 | [ | |
4125 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4126 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4127 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4128 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4129 | VCMLAQ_ROT90_F)) | |
4130 | ] | |
4131 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4132 | "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
4133 | [(set_attr "type" "mve_move") | |
4134 | ]) | |
4135 | ||
4136 | ;; | |
4137 | ;; [vcmpeqq_m_n_f]) | |
4138 | ;; | |
4139 | (define_insn "mve_vcmpeqq_m_n_f<mode>" | |
4140 | [ | |
4141 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4142 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4143 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4144 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4145 | VCMPEQQ_M_N_F)) | |
4146 | ] | |
4147 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4148 | "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2" | |
4149 | [(set_attr "type" "mve_move") | |
4150 | (set_attr "length""8")]) | |
4151 | ||
4152 | ;; | |
4153 | ;; [vcmpgeq_m_f]) | |
4154 | ;; | |
4155 | (define_insn "mve_vcmpgeq_m_f<mode>" | |
4156 | [ | |
4157 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4158 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4159 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4160 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4161 | VCMPGEQ_M_F)) | |
4162 | ] | |
4163 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4164 | "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2" | |
4165 | [(set_attr "type" "mve_move") | |
4166 | (set_attr "length""8")]) | |
4167 | ||
4168 | ;; | |
4169 | ;; [vcmpgeq_m_n_f]) | |
4170 | ;; | |
4171 | (define_insn "mve_vcmpgeq_m_n_f<mode>" | |
4172 | [ | |
4173 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4174 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4175 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4176 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4177 | VCMPGEQ_M_N_F)) | |
4178 | ] | |
4179 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4180 | "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2" | |
4181 | [(set_attr "type" "mve_move") | |
4182 | (set_attr "length""8")]) | |
4183 | ||
4184 | ;; | |
4185 | ;; [vcmpgtq_m_f]) | |
4186 | ;; | |
4187 | (define_insn "mve_vcmpgtq_m_f<mode>" | |
4188 | [ | |
4189 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4190 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4191 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4192 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4193 | VCMPGTQ_M_F)) | |
4194 | ] | |
4195 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4196 | "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2" | |
4197 | [(set_attr "type" "mve_move") | |
4198 | (set_attr "length""8")]) | |
4199 | ||
4200 | ;; | |
4201 | ;; [vcmpgtq_m_n_f]) | |
4202 | ;; | |
4203 | (define_insn "mve_vcmpgtq_m_n_f<mode>" | |
4204 | [ | |
4205 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4206 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4207 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4208 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4209 | VCMPGTQ_M_N_F)) | |
4210 | ] | |
4211 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4212 | "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2" | |
4213 | [(set_attr "type" "mve_move") | |
4214 | (set_attr "length""8")]) | |
4215 | ||
4216 | ;; | |
4217 | ;; [vcmpleq_m_f]) | |
4218 | ;; | |
4219 | (define_insn "mve_vcmpleq_m_f<mode>" | |
4220 | [ | |
4221 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4222 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4223 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4224 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4225 | VCMPLEQ_M_F)) | |
4226 | ] | |
4227 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4228 | "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2" | |
4229 | [(set_attr "type" "mve_move") | |
4230 | (set_attr "length""8")]) | |
4231 | ||
4232 | ;; | |
4233 | ;; [vcmpleq_m_n_f]) | |
4234 | ;; | |
4235 | (define_insn "mve_vcmpleq_m_n_f<mode>" | |
4236 | [ | |
4237 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4238 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4239 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4240 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4241 | VCMPLEQ_M_N_F)) | |
4242 | ] | |
4243 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4244 | "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2" | |
4245 | [(set_attr "type" "mve_move") | |
4246 | (set_attr "length""8")]) | |
4247 | ||
4248 | ;; | |
4249 | ;; [vcmpltq_m_f]) | |
4250 | ;; | |
4251 | (define_insn "mve_vcmpltq_m_f<mode>" | |
4252 | [ | |
4253 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4254 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4255 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4256 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4257 | VCMPLTQ_M_F)) | |
4258 | ] | |
4259 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4260 | "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2" | |
4261 | [(set_attr "type" "mve_move") | |
4262 | (set_attr "length""8")]) | |
4263 | ||
4264 | ;; | |
4265 | ;; [vcmpltq_m_n_f]) | |
4266 | ;; | |
4267 | (define_insn "mve_vcmpltq_m_n_f<mode>" | |
4268 | [ | |
4269 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4270 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4271 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4272 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4273 | VCMPLTQ_M_N_F)) | |
4274 | ] | |
4275 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4276 | "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2" | |
4277 | [(set_attr "type" "mve_move") | |
4278 | (set_attr "length""8")]) | |
4279 | ||
4280 | ;; | |
4281 | ;; [vcmpneq_m_f]) | |
4282 | ;; | |
4283 | (define_insn "mve_vcmpneq_m_f<mode>" | |
4284 | [ | |
4285 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4286 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4287 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4288 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4289 | VCMPNEQ_M_F)) | |
4290 | ] | |
4291 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4292 | "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2" | |
4293 | [(set_attr "type" "mve_move") | |
4294 | (set_attr "length""8")]) | |
4295 | ||
4296 | ;; | |
4297 | ;; [vcmpneq_m_n_f]) | |
4298 | ;; | |
4299 | (define_insn "mve_vcmpneq_m_n_f<mode>" | |
4300 | [ | |
4301 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
4302 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4303 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4304 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4305 | VCMPNEQ_M_N_F)) | |
4306 | ] | |
4307 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4308 | "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2" | |
4309 | [(set_attr "type" "mve_move") | |
4310 | (set_attr "length""8")]) | |
4311 | ||
4312 | ;; | |
4313 | ;; [vcvtbq_m_f16_f32]) | |
4314 | ;; | |
4315 | (define_insn "mve_vcvtbq_m_f16_f32v8hf" | |
4316 | [ | |
4317 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
4318 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
4319 | (match_operand:V4SF 2 "s_register_operand" "w") | |
4320 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4321 | VCVTBQ_M_F16_F32)) | |
4322 | ] | |
4323 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4324 | "vpst\;vcvtbt.f16.f32 %q0, %q2" | |
4325 | [(set_attr "type" "mve_move") | |
4326 | (set_attr "length""8")]) | |
4327 | ||
4328 | ;; | |
4329 | ;; [vcvtbq_m_f32_f16]) | |
4330 | ;; | |
4331 | (define_insn "mve_vcvtbq_m_f32_f16v4sf" | |
4332 | [ | |
4333 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
4334 | (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") | |
4335 | (match_operand:V8HF 2 "s_register_operand" "w") | |
4336 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4337 | VCVTBQ_M_F32_F16)) | |
4338 | ] | |
4339 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4340 | "vpst\;vcvtbt.f32.f16 %q0, %q2" | |
4341 | [(set_attr "type" "mve_move") | |
4342 | (set_attr "length""8")]) | |
4343 | ||
4344 | ;; | |
4345 | ;; [vcvttq_m_f16_f32]) | |
4346 | ;; | |
4347 | (define_insn "mve_vcvttq_m_f16_f32v8hf" | |
4348 | [ | |
4349 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
4350 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
4351 | (match_operand:V4SF 2 "s_register_operand" "w") | |
4352 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4353 | VCVTTQ_M_F16_F32)) | |
4354 | ] | |
4355 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4356 | "vpst\;vcvttt.f16.f32 %q0, %q2" | |
4357 | [(set_attr "type" "mve_move") | |
4358 | (set_attr "length""8")]) | |
4359 | ||
4360 | ;; | |
4361 | ;; [vcvttq_m_f32_f16]) | |
4362 | ;; | |
4363 | (define_insn "mve_vcvttq_m_f32_f16v4sf" | |
4364 | [ | |
4365 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
4366 | (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") | |
4367 | (match_operand:V8HF 2 "s_register_operand" "w") | |
4368 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4369 | VCVTTQ_M_F32_F16)) | |
4370 | ] | |
4371 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4372 | "vpst\;vcvttt.f32.f16 %q0, %q2" | |
4373 | [(set_attr "type" "mve_move") | |
4374 | (set_attr "length""8")]) | |
4375 | ||
4376 | ;; | |
4377 | ;; [vdupq_m_n_f]) | |
4378 | ;; | |
4379 | (define_insn "mve_vdupq_m_n_f<mode>" | |
4380 | [ | |
4381 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4382 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4383 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
4384 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4385 | VDUPQ_M_N_F)) | |
4386 | ] | |
4387 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4388 | "vpst\;vdupt.%#<V_sz_elem> %q0, %2" | |
4389 | [(set_attr "type" "mve_move") | |
4390 | (set_attr "length""8")]) | |
4391 | ||
4392 | ;; | |
4393 | ;; [vfmaq_f]) | |
4394 | ;; | |
4395 | (define_insn "mve_vfmaq_f<mode>" | |
4396 | [ | |
4397 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4398 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4399 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4400 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4401 | VFMAQ_F)) | |
4402 | ] | |
4403 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4404 | "vfma.f%#<V_sz_elem> %q0, %q2, %q3" | |
4405 | [(set_attr "type" "mve_move") | |
4406 | ]) | |
4407 | ||
4408 | ;; | |
4409 | ;; [vfmaq_n_f]) | |
4410 | ;; | |
4411 | (define_insn "mve_vfmaq_n_f<mode>" | |
4412 | [ | |
4413 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4414 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4415 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4416 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
4417 | VFMAQ_N_F)) | |
4418 | ] | |
4419 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4420 | "vfma.f%#<V_sz_elem> %q0, %q2, %3" | |
4421 | [(set_attr "type" "mve_move") | |
4422 | ]) | |
4423 | ||
4424 | ;; | |
4425 | ;; [vfmasq_n_f]) | |
4426 | ;; | |
4427 | (define_insn "mve_vfmasq_n_f<mode>" | |
4428 | [ | |
4429 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4430 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4431 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4432 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
4433 | VFMASQ_N_F)) | |
4434 | ] | |
4435 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4436 | "vfmas.f%#<V_sz_elem> %q0, %q2, %3" | |
4437 | [(set_attr "type" "mve_move") | |
4438 | ]) | |
4439 | ;; | |
4440 | ;; [vfmsq_f]) | |
4441 | ;; | |
4442 | (define_insn "mve_vfmsq_f<mode>" | |
4443 | [ | |
4444 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4445 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4446 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4447 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
4448 | VFMSQ_F)) | |
4449 | ] | |
4450 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4451 | "vfms.f%#<V_sz_elem> %q0, %q2, %q3" | |
4452 | [(set_attr "type" "mve_move") | |
4453 | ]) | |
4454 | ||
4455 | ;; | |
4456 | ;; [vmaxnmaq_m_f]) | |
4457 | ;; | |
4458 | (define_insn "mve_vmaxnmaq_m_f<mode>" | |
4459 | [ | |
4460 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4461 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4462 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4463 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4464 | VMAXNMAQ_M_F)) | |
4465 | ] | |
4466 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4467 | "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2" | |
4468 | [(set_attr "type" "mve_move") | |
4469 | (set_attr "length""8")]) | |
4470 | ;; | |
4471 | ;; [vmaxnmavq_p_f]) | |
4472 | ;; | |
4473 | (define_insn "mve_vmaxnmavq_p_f<mode>" | |
4474 | [ | |
4475 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
4476 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
4477 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4478 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4479 | VMAXNMAVQ_P_F)) | |
4480 | ] | |
4481 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4482 | "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2" | |
4483 | [(set_attr "type" "mve_move") | |
4484 | (set_attr "length""8")]) | |
4485 | ||
4486 | ;; | |
4487 | ;; [vmaxnmvq_p_f]) | |
4488 | ;; | |
4489 | (define_insn "mve_vmaxnmvq_p_f<mode>" | |
4490 | [ | |
4491 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
4492 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
4493 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4494 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4495 | VMAXNMVQ_P_F)) | |
4496 | ] | |
4497 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4498 | "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2" | |
4499 | [(set_attr "type" "mve_move") | |
4500 | (set_attr "length""8")]) | |
4501 | ;; | |
4502 | ;; [vminnmaq_m_f]) | |
4503 | ;; | |
4504 | (define_insn "mve_vminnmaq_m_f<mode>" | |
4505 | [ | |
4506 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4507 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4508 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4509 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4510 | VMINNMAQ_M_F)) | |
4511 | ] | |
4512 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4513 | "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2" | |
4514 | [(set_attr "type" "mve_move") | |
4515 | (set_attr "length""8")]) | |
4516 | ||
4517 | ;; | |
4518 | ;; [vminnmavq_p_f]) | |
4519 | ;; | |
4520 | (define_insn "mve_vminnmavq_p_f<mode>" | |
4521 | [ | |
4522 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
4523 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
4524 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4525 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4526 | VMINNMAVQ_P_F)) | |
4527 | ] | |
4528 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4529 | "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2" | |
4530 | [(set_attr "type" "mve_move") | |
4531 | (set_attr "length""8")]) | |
4532 | ;; | |
4533 | ;; [vminnmvq_p_f]) | |
4534 | ;; | |
4535 | (define_insn "mve_vminnmvq_p_f<mode>" | |
4536 | [ | |
4537 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
4538 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
4539 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4540 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4541 | VMINNMVQ_P_F)) | |
4542 | ] | |
4543 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4544 | "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2" | |
4545 | [(set_attr "type" "mve_move") | |
4546 | (set_attr "length""8")]) | |
4547 | ||
4548 | ;; | |
4549 | ;; [vmlaldavaq_s, vmlaldavaq_u]) | |
4550 | ;; | |
4551 | (define_insn "mve_vmlaldavaq_<supf><mode>" | |
4552 | [ | |
4553 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4554 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
4555 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4556 | (match_operand:MVE_5 3 "s_register_operand" "w")] | |
4557 | VMLALDAVAQ)) | |
4558 | ] | |
4559 | "TARGET_HAVE_MVE" | |
4560 | "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
4561 | [(set_attr "type" "mve_move") | |
4562 | ]) | |
4563 | ||
4564 | ;; | |
4565 | ;; [vmlaldavaxq_s]) | |
4566 | ;; | |
4567 | (define_insn "mve_vmlaldavaxq_s<mode>" | |
4568 | [ | |
4569 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4570 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
4571 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4572 | (match_operand:MVE_5 3 "s_register_operand" "w")] | |
4573 | VMLALDAVAXQ_S)) | |
4574 | ] | |
4575 | "TARGET_HAVE_MVE" | |
4576 | "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
4577 | [(set_attr "type" "mve_move") | |
4578 | ]) | |
4579 | ||
4580 | ;; | |
4581 | ;; [vmlaldavq_p_u, vmlaldavq_p_s]) | |
4582 | ;; | |
4583 | (define_insn "mve_vmlaldavq_p_<supf><mode>" | |
4584 | [ | |
4585 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4586 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
4587 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4588 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4589 | VMLALDAVQ_P)) | |
4590 | ] | |
4591 | "TARGET_HAVE_MVE" | |
4592 | "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
4593 | [(set_attr "type" "mve_move") | |
4594 | (set_attr "length""8")]) | |
4595 | ||
4596 | ;; | |
4597 | ;; [vmlaldavxq_p_s]) | |
4598 | ;; | |
4599 | (define_insn "mve_vmlaldavxq_p_s<mode>" | |
4600 | [ | |
4601 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4602 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
4603 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4604 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4605 | VMLALDAVXQ_P_S)) | |
4606 | ] | |
4607 | "TARGET_HAVE_MVE" | |
4608 | "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" | |
4609 | [(set_attr "type" "mve_move") | |
4610 | (set_attr "length""8")]) | |
4611 | ;; | |
4612 | ;; [vmlsldavaq_s]) | |
4613 | ;; | |
4614 | (define_insn "mve_vmlsldavaq_s<mode>" | |
4615 | [ | |
4616 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4617 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
4618 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4619 | (match_operand:MVE_5 3 "s_register_operand" "w")] | |
4620 | VMLSLDAVAQ_S)) | |
4621 | ] | |
4622 | "TARGET_HAVE_MVE" | |
4623 | "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
4624 | [(set_attr "type" "mve_move") | |
4625 | ]) | |
4626 | ||
4627 | ;; | |
4628 | ;; [vmlsldavaxq_s]) | |
4629 | ;; | |
4630 | (define_insn "mve_vmlsldavaxq_s<mode>" | |
4631 | [ | |
4632 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4633 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
4634 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4635 | (match_operand:MVE_5 3 "s_register_operand" "w")] | |
4636 | VMLSLDAVAXQ_S)) | |
4637 | ] | |
4638 | "TARGET_HAVE_MVE" | |
4639 | "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
4640 | [(set_attr "type" "mve_move") | |
4641 | ]) | |
4642 | ||
4643 | ;; | |
4644 | ;; [vmlsldavq_p_s]) | |
4645 | ;; | |
4646 | (define_insn "mve_vmlsldavq_p_s<mode>" | |
4647 | [ | |
4648 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4649 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
4650 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4651 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4652 | VMLSLDAVQ_P_S)) | |
4653 | ] | |
4654 | "TARGET_HAVE_MVE" | |
4655 | "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
4656 | [(set_attr "type" "mve_move") | |
4657 | (set_attr "length""8")]) | |
4658 | ||
4659 | ;; | |
4660 | ;; [vmlsldavxq_p_s]) | |
4661 | ;; | |
4662 | (define_insn "mve_vmlsldavxq_p_s<mode>" | |
4663 | [ | |
4664 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
4665 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
4666 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4667 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4668 | VMLSLDAVXQ_P_S)) | |
4669 | ] | |
4670 | "TARGET_HAVE_MVE" | |
4671 | "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
4672 | [(set_attr "type" "mve_move") | |
4673 | (set_attr "length""8")]) | |
4674 | ;; | |
4675 | ;; [vmovlbq_m_u, vmovlbq_m_s]) | |
4676 | ;; | |
4677 | (define_insn "mve_vmovlbq_m_<supf><mode>" | |
4678 | [ | |
4679 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
4680 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
4681 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
4682 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4683 | VMOVLBQ_M)) | |
4684 | ] | |
4685 | "TARGET_HAVE_MVE" | |
4686 | "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2" | |
4687 | [(set_attr "type" "mve_move") | |
4688 | (set_attr "length""8")]) | |
4689 | ;; | |
4690 | ;; [vmovltq_m_u, vmovltq_m_s]) | |
4691 | ;; | |
4692 | (define_insn "mve_vmovltq_m_<supf><mode>" | |
4693 | [ | |
4694 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
4695 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
4696 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
4697 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4698 | VMOVLTQ_M)) | |
4699 | ] | |
4700 | "TARGET_HAVE_MVE" | |
4701 | "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2" | |
4702 | [(set_attr "type" "mve_move") | |
4703 | (set_attr "length""8")]) | |
4704 | ;; | |
4705 | ;; [vmovnbq_m_u, vmovnbq_m_s]) | |
4706 | ;; | |
4707 | (define_insn "mve_vmovnbq_m_<supf><mode>" | |
4708 | [ | |
4709 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4710 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4711 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4712 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4713 | VMOVNBQ_M)) | |
4714 | ] | |
4715 | "TARGET_HAVE_MVE" | |
4716 | "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2" | |
4717 | [(set_attr "type" "mve_move") | |
4718 | (set_attr "length""8")]) | |
4719 | ||
4720 | ;; | |
4721 | ;; [vmovntq_m_u, vmovntq_m_s]) | |
4722 | ;; | |
4723 | (define_insn "mve_vmovntq_m_<supf><mode>" | |
4724 | [ | |
4725 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4726 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4727 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4728 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4729 | VMOVNTQ_M)) | |
4730 | ] | |
4731 | "TARGET_HAVE_MVE" | |
4732 | "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2" | |
4733 | [(set_attr "type" "mve_move") | |
4734 | (set_attr "length""8")]) | |
4735 | ||
4736 | ;; | |
4737 | ;; [vmvnq_m_n_u, vmvnq_m_n_s]) | |
4738 | ;; | |
4739 | (define_insn "mve_vmvnq_m_n_<supf><mode>" | |
4740 | [ | |
4741 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
4742 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
4743 | (match_operand:SI 2 "immediate_operand" "i") | |
4744 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4745 | VMVNQ_M_N)) | |
4746 | ] | |
4747 | "TARGET_HAVE_MVE" | |
4748 | "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2" | |
4749 | [(set_attr "type" "mve_move") | |
4750 | (set_attr "length""8")]) | |
4751 | ;; | |
4752 | ;; [vnegq_m_f]) | |
4753 | ;; | |
4754 | (define_insn "mve_vnegq_m_f<mode>" | |
4755 | [ | |
4756 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4757 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4758 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4759 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4760 | VNEGQ_M_F)) | |
4761 | ] | |
4762 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4763 | "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2" | |
4764 | [(set_attr "type" "mve_move") | |
4765 | (set_attr "length""8")]) | |
4766 | ||
4767 | ;; | |
4768 | ;; [vorrq_m_n_s, vorrq_m_n_u]) | |
4769 | ;; | |
4770 | (define_insn "mve_vorrq_m_n_<supf><mode>" | |
4771 | [ | |
4772 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
4773 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
4774 | (match_operand:SI 2 "immediate_operand" "i") | |
4775 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4776 | VORRQ_M_N)) | |
4777 | ] | |
4778 | "TARGET_HAVE_MVE" | |
4779 | "vpst\;vorrt.i%#<V_sz_elem> %q0, %2" | |
4780 | [(set_attr "type" "mve_move") | |
4781 | (set_attr "length""8")]) | |
4782 | ;; | |
4783 | ;; [vpselq_f]) | |
4784 | ;; | |
4785 | (define_insn "mve_vpselq_f<mode>" | |
4786 | [ | |
4787 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4788 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
4789 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4790 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4791 | VPSELQ_F)) | |
4792 | ] | |
4793 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4794 | "vpsel %q0, %q1, %q2" | |
4795 | [(set_attr "type" "mve_move") | |
4796 | ]) | |
4797 | ||
4798 | ;; | |
4799 | ;; [vqmovnbq_m_s, vqmovnbq_m_u]) | |
4800 | ;; | |
4801 | (define_insn "mve_vqmovnbq_m_<supf><mode>" | |
4802 | [ | |
4803 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4804 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4805 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4806 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4807 | VQMOVNBQ_M)) | |
4808 | ] | |
4809 | "TARGET_HAVE_MVE" | |
4810 | "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2" | |
4811 | [(set_attr "type" "mve_move") | |
4812 | (set_attr "length""8")]) | |
4813 | ||
4814 | ;; | |
4815 | ;; [vqmovntq_m_u, vqmovntq_m_s]) | |
4816 | ;; | |
4817 | (define_insn "mve_vqmovntq_m_<supf><mode>" | |
4818 | [ | |
4819 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4820 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4821 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4822 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4823 | VQMOVNTQ_M)) | |
4824 | ] | |
4825 | "TARGET_HAVE_MVE" | |
4826 | "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2" | |
4827 | [(set_attr "type" "mve_move") | |
4828 | (set_attr "length""8")]) | |
4829 | ||
4830 | ;; | |
4831 | ;; [vqmovunbq_m_s]) | |
4832 | ;; | |
4833 | (define_insn "mve_vqmovunbq_m_s<mode>" | |
4834 | [ | |
4835 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4836 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4837 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4838 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4839 | VQMOVUNBQ_M_S)) | |
4840 | ] | |
4841 | "TARGET_HAVE_MVE" | |
4842 | "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2" | |
4843 | [(set_attr "type" "mve_move") | |
4844 | (set_attr "length""8")]) | |
4845 | ||
4846 | ;; | |
4847 | ;; [vqmovuntq_m_s]) | |
4848 | ;; | |
4849 | (define_insn "mve_vqmovuntq_m_s<mode>" | |
4850 | [ | |
4851 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4852 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4853 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4854 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4855 | VQMOVUNTQ_M_S)) | |
4856 | ] | |
4857 | "TARGET_HAVE_MVE" | |
4858 | "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2" | |
4859 | [(set_attr "type" "mve_move") | |
4860 | (set_attr "length""8")]) | |
4861 | ||
4862 | ;; | |
4863 | ;; [vqrshrntq_n_u, vqrshrntq_n_s]) | |
4864 | ;; | |
4865 | (define_insn "mve_vqrshrntq_n_<supf><mode>" | |
4866 | [ | |
4867 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4868 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4869 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4870 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
4871 | VQRSHRNTQ_N)) | |
4872 | ] | |
4873 | "TARGET_HAVE_MVE" | |
4874 | "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
4875 | [(set_attr "type" "mve_move") | |
4876 | ]) | |
4877 | ||
4878 | ;; | |
4879 | ;; [vqrshruntq_n_s]) | |
4880 | ;; | |
4881 | (define_insn "mve_vqrshruntq_n_s<mode>" | |
4882 | [ | |
4883 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4884 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4885 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
4886 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
4887 | VQRSHRUNTQ_N_S)) | |
4888 | ] | |
4889 | "TARGET_HAVE_MVE" | |
4890 | "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3" | |
4891 | [(set_attr "type" "mve_move") | |
4892 | ]) | |
4893 | ||
4894 | ;; | |
4895 | ;; [vqshrnbq_n_u, vqshrnbq_n_s]) | |
4896 | ;; | |
4897 | (define_insn "mve_vqshrnbq_n_<supf><mode>" | |
4898 | [ | |
4899 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4900 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4901 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 4902 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] |
e3678b44 SP |
4903 | VQSHRNBQ_N)) |
4904 | ] | |
4905 | "TARGET_HAVE_MVE" | |
4906 | "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
4907 | [(set_attr "type" "mve_move") | |
4908 | ]) | |
4909 | ||
4910 | ;; | |
4911 | ;; [vqshrntq_n_u, vqshrntq_n_s]) | |
4912 | ;; | |
4913 | (define_insn "mve_vqshrntq_n_<supf><mode>" | |
4914 | [ | |
4915 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4916 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4917 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 4918 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] |
e3678b44 SP |
4919 | VQSHRNTQ_N)) |
4920 | ] | |
4921 | "TARGET_HAVE_MVE" | |
4922 | "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
4923 | [(set_attr "type" "mve_move") | |
4924 | ]) | |
4925 | ||
4926 | ;; | |
4927 | ;; [vqshrunbq_n_s]) | |
4928 | ;; | |
4929 | (define_insn "mve_vqshrunbq_n_s<mode>" | |
4930 | [ | |
4931 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4932 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4933 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 4934 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] |
e3678b44 SP |
4935 | VQSHRUNBQ_N_S)) |
4936 | ] | |
4937 | "TARGET_HAVE_MVE" | |
4938 | "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3" | |
4939 | [(set_attr "type" "mve_move") | |
4940 | ]) | |
4941 | ||
4942 | ;; | |
4943 | ;; [vqshruntq_n_s]) | |
4944 | ;; | |
4945 | (define_insn "mve_vqshruntq_n_s<mode>" | |
4946 | [ | |
4947 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
4948 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
4949 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 4950 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] |
e3678b44 SP |
4951 | VQSHRUNTQ_N_S)) |
4952 | ] | |
4953 | "TARGET_HAVE_MVE" | |
4954 | "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3" | |
4955 | [(set_attr "type" "mve_move") | |
4956 | ]) | |
4957 | ||
4958 | ;; | |
4959 | ;; [vrev32q_m_f]) | |
4960 | ;; | |
4961 | (define_insn "mve_vrev32q_m_fv8hf" | |
4962 | [ | |
4963 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
4964 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
4965 | (match_operand:V8HF 2 "s_register_operand" "w") | |
4966 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4967 | VREV32Q_M_F)) | |
4968 | ] | |
4969 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4970 | "vpst\;vrev32t.16 %q0, %q2" | |
4971 | [(set_attr "type" "mve_move") | |
4972 | (set_attr "length""8")]) | |
4973 | ||
4974 | ;; | |
4975 | ;; [vrev32q_m_s, vrev32q_m_u]) | |
4976 | ;; | |
4977 | (define_insn "mve_vrev32q_m_<supf><mode>" | |
4978 | [ | |
4979 | (set (match_operand:MVE_3 0 "s_register_operand" "=w") | |
4980 | (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") | |
4981 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
4982 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4983 | VREV32Q_M)) | |
4984 | ] | |
4985 | "TARGET_HAVE_MVE" | |
4986 | "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2" | |
4987 | [(set_attr "type" "mve_move") | |
4988 | (set_attr "length""8")]) | |
4989 | ||
4990 | ;; | |
4991 | ;; [vrev64q_m_f]) | |
4992 | ;; | |
4993 | (define_insn "mve_vrev64q_m_f<mode>" | |
4994 | [ | |
4995 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
4996 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
4997 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
4998 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
4999 | VREV64Q_M_F)) | |
5000 | ] | |
5001 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5002 | "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2" | |
5003 | [(set_attr "type" "mve_move") | |
5004 | (set_attr "length""8")]) | |
5005 | ||
5006 | ;; | |
5007 | ;; [vrmlaldavhaxq_s]) | |
5008 | ;; | |
5009 | (define_insn "mve_vrmlaldavhaxq_sv4si" | |
5010 | [ | |
5011 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5012 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
5013 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5014 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
5015 | VRMLALDAVHAXQ_S)) | |
5016 | ] | |
5017 | "TARGET_HAVE_MVE" | |
5018 | "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3" | |
5019 | [(set_attr "type" "mve_move") | |
5020 | ]) | |
5021 | ||
5022 | ;; | |
5023 | ;; [vrmlaldavhxq_p_s]) | |
5024 | ;; | |
5025 | (define_insn "mve_vrmlaldavhxq_p_sv4si" | |
5026 | [ | |
5027 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5028 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
5029 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5030 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5031 | VRMLALDAVHXQ_P_S)) | |
5032 | ] | |
5033 | "TARGET_HAVE_MVE" | |
5034 | "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2" | |
5035 | [(set_attr "type" "mve_move") | |
5036 | (set_attr "length""8")]) | |
5037 | ||
5038 | ;; | |
5039 | ;; [vrmlsldavhaxq_s]) | |
5040 | ;; | |
5041 | (define_insn "mve_vrmlsldavhaxq_sv4si" | |
5042 | [ | |
5043 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5044 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
5045 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5046 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
5047 | VRMLSLDAVHAXQ_S)) | |
5048 | ] | |
5049 | "TARGET_HAVE_MVE" | |
5050 | "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3" | |
5051 | [(set_attr "type" "mve_move") | |
5052 | ]) | |
5053 | ||
5054 | ;; | |
5055 | ;; [vrmlsldavhq_p_s]) | |
5056 | ;; | |
5057 | (define_insn "mve_vrmlsldavhq_p_sv4si" | |
5058 | [ | |
5059 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5060 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
5061 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5062 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5063 | VRMLSLDAVHQ_P_S)) | |
5064 | ] | |
5065 | "TARGET_HAVE_MVE" | |
5066 | "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2" | |
5067 | [(set_attr "type" "mve_move") | |
5068 | (set_attr "length""8")]) | |
5069 | ||
5070 | ;; | |
5071 | ;; [vrmlsldavhxq_p_s]) | |
5072 | ;; | |
5073 | (define_insn "mve_vrmlsldavhxq_p_sv4si" | |
5074 | [ | |
5075 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5076 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
5077 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5078 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5079 | VRMLSLDAVHXQ_P_S)) | |
5080 | ] | |
5081 | "TARGET_HAVE_MVE" | |
5082 | "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2" | |
5083 | [(set_attr "type" "mve_move") | |
5084 | (set_attr "length""8")]) | |
5085 | ||
5086 | ;; | |
5087 | ;; [vrndaq_m_f]) | |
5088 | ;; | |
5089 | (define_insn "mve_vrndaq_m_f<mode>" | |
5090 | [ | |
5091 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5092 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5093 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
5094 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5095 | VRNDAQ_M_F)) | |
5096 | ] | |
5097 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5098 | "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2" | |
5099 | [(set_attr "type" "mve_move") | |
5100 | (set_attr "length""8")]) | |
5101 | ||
5102 | ;; | |
5103 | ;; [vrndmq_m_f]) | |
5104 | ;; | |
5105 | (define_insn "mve_vrndmq_m_f<mode>" | |
5106 | [ | |
5107 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5108 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5109 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
5110 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5111 | VRNDMQ_M_F)) | |
5112 | ] | |
5113 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5114 | "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2" | |
5115 | [(set_attr "type" "mve_move") | |
5116 | (set_attr "length""8")]) | |
5117 | ||
5118 | ;; | |
5119 | ;; [vrndnq_m_f]) | |
5120 | ;; | |
5121 | (define_insn "mve_vrndnq_m_f<mode>" | |
5122 | [ | |
5123 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5124 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5125 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
5126 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5127 | VRNDNQ_M_F)) | |
5128 | ] | |
5129 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5130 | "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2" | |
5131 | [(set_attr "type" "mve_move") | |
5132 | (set_attr "length""8")]) | |
5133 | ||
5134 | ;; | |
5135 | ;; [vrndpq_m_f]) | |
5136 | ;; | |
5137 | (define_insn "mve_vrndpq_m_f<mode>" | |
5138 | [ | |
5139 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5140 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5141 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
5142 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5143 | VRNDPQ_M_F)) | |
5144 | ] | |
5145 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5146 | "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2" | |
5147 | [(set_attr "type" "mve_move") | |
5148 | (set_attr "length""8")]) | |
5149 | ||
5150 | ;; | |
5151 | ;; [vrndxq_m_f]) | |
5152 | ;; | |
5153 | (define_insn "mve_vrndxq_m_f<mode>" | |
5154 | [ | |
5155 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5156 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5157 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
5158 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5159 | VRNDXQ_M_F)) | |
5160 | ] | |
5161 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5162 | "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2" | |
5163 | [(set_attr "type" "mve_move") | |
5164 | (set_attr "length""8")]) | |
5165 | ||
5166 | ;; | |
5167 | ;; [vrshrnbq_n_s, vrshrnbq_n_u]) | |
5168 | ;; | |
5169 | (define_insn "mve_vrshrnbq_n_<supf><mode>" | |
5170 | [ | |
5171 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
5172 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
5173 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
5174 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
5175 | VRSHRNBQ_N)) | |
5176 | ] | |
5177 | "TARGET_HAVE_MVE" | |
5178 | "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3" | |
5179 | [(set_attr "type" "mve_move") | |
5180 | ]) | |
5181 | ||
5182 | ;; | |
5183 | ;; [vrshrntq_n_u, vrshrntq_n_s]) | |
5184 | ;; | |
5185 | (define_insn "mve_vrshrntq_n_<supf><mode>" | |
5186 | [ | |
5187 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
5188 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
5189 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
5190 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
5191 | VRSHRNTQ_N)) | |
5192 | ] | |
5193 | "TARGET_HAVE_MVE" | |
5194 | "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3" | |
5195 | [(set_attr "type" "mve_move") | |
5196 | ]) | |
5197 | ||
5198 | ;; | |
5199 | ;; [vshrnbq_n_u, vshrnbq_n_s]) | |
5200 | ;; | |
5201 | (define_insn "mve_vshrnbq_n_<supf><mode>" | |
5202 | [ | |
5203 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
5204 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
5205 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
5206 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] | |
5207 | VSHRNBQ_N)) | |
5208 | ] | |
5209 | "TARGET_HAVE_MVE" | |
5210 | "vshrnb.i%#<V_sz_elem> %q0, %q2, %3" | |
5211 | [(set_attr "type" "mve_move") | |
5212 | ]) | |
5213 | ||
5214 | ;; | |
5215 | ;; [vshrntq_n_s, vshrntq_n_u]) | |
5216 | ;; | |
5217 | (define_insn "mve_vshrntq_n_<supf><mode>" | |
5218 | [ | |
5219 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
5220 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
5221 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
5222 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] | |
5223 | VSHRNTQ_N)) | |
5224 | ] | |
5225 | "TARGET_HAVE_MVE" | |
db5db9d2 | 5226 | "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3" |
e3678b44 SP |
5227 | [(set_attr "type" "mve_move") |
5228 | ]) | |
5229 | ||
5230 | ;; | |
5231 | ;; [vcvtmq_m_s, vcvtmq_m_u]) | |
5232 | ;; | |
5233 | (define_insn "mve_vcvtmq_m_<supf><mode>" | |
5234 | [ | |
5235 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
5236 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
5237 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
5238 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5239 | VCVTMQ_M)) | |
5240 | ] | |
5241 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 5242 | "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
5243 | [(set_attr "type" "mve_move") |
5244 | (set_attr "length""8")]) | |
5245 | ||
5246 | ;; | |
5247 | ;; [vcvtpq_m_u, vcvtpq_m_s]) | |
5248 | ;; | |
5249 | (define_insn "mve_vcvtpq_m_<supf><mode>" | |
5250 | [ | |
5251 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
5252 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
5253 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
5254 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5255 | VCVTPQ_M)) | |
5256 | ] | |
5257 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 5258 | "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
5259 | [(set_attr "type" "mve_move") |
5260 | (set_attr "length""8")]) | |
5261 | ||
5262 | ;; | |
5263 | ;; [vcvtnq_m_s, vcvtnq_m_u]) | |
5264 | ;; | |
5265 | (define_insn "mve_vcvtnq_m_<supf><mode>" | |
5266 | [ | |
5267 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
5268 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
5269 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
5270 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5271 | VCVTNQ_M)) | |
5272 | ] | |
5273 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 5274 | "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
5275 | [(set_attr "type" "mve_move") |
5276 | (set_attr "length""8")]) | |
5277 | ||
5278 | ;; | |
5279 | ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]) | |
5280 | ;; | |
5281 | (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>" | |
5282 | [ | |
5283 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
5284 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
5285 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
d2ce75fe | 5286 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") |
e3678b44 SP |
5287 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
5288 | VCVTQ_M_N_FROM_F)) | |
5289 | ] | |
5290 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 5291 | "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3" |
e3678b44 SP |
5292 | [(set_attr "type" "mve_move") |
5293 | (set_attr "length""8")]) | |
5294 | ||
5295 | ;; | |
5296 | ;; [vrev16q_m_u, vrev16q_m_s]) | |
5297 | ;; | |
5298 | (define_insn "mve_vrev16q_m_<supf>v16qi" | |
5299 | [ | |
5300 | (set (match_operand:V16QI 0 "s_register_operand" "=w") | |
5301 | (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") | |
5302 | (match_operand:V16QI 2 "s_register_operand" "w") | |
5303 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5304 | VREV16Q_M)) | |
5305 | ] | |
5306 | "TARGET_HAVE_MVE" | |
5307 | "vpst\;vrev16t.8 %q0, %q2" | |
5308 | [(set_attr "type" "mve_move") | |
5309 | (set_attr "length""8")]) | |
5310 | ||
5311 | ;; | |
5312 | ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]) | |
5313 | ;; | |
5314 | (define_insn "mve_vcvtq_m_from_f_<supf><mode>" | |
5315 | [ | |
5316 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
5317 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
5318 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
5319 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5320 | VCVTQ_M_FROM_F)) | |
5321 | ] | |
5322 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 5323 | "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
5324 | [(set_attr "type" "mve_move") |
5325 | (set_attr "length""8")]) | |
5326 | ||
5327 | ;; | |
5328 | ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]) | |
5329 | ;; | |
5330 | (define_insn "mve_vrmlaldavhq_p_<supf>v4si" | |
5331 | [ | |
5332 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5333 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
5334 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5335 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
5336 | VRMLALDAVHQ_P)) | |
5337 | ] | |
5338 | "TARGET_HAVE_MVE" | |
5339 | "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2" | |
5340 | [(set_attr "type" "mve_move") | |
5341 | (set_attr "length""8")]) | |
5342 | ||
5343 | ;; | |
5344 | ;; [vrmlsldavhaq_s]) | |
5345 | ;; | |
5346 | (define_insn "mve_vrmlsldavhaq_sv4si" | |
5347 | [ | |
5348 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
5349 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
5350 | (match_operand:V4SI 2 "s_register_operand" "w") | |
5351 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
5352 | VRMLSLDAVHAQ_S)) | |
5353 | ] | |
5354 | "TARGET_HAVE_MVE" | |
5355 | "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" | |
5356 | [(set_attr "type" "mve_move") | |
5357 | ]) | |
db5db9d2 SP |
5358 | |
5359 | ;; | |
5360 | ;; [vabavq_p_s, vabavq_p_u]) | |
5361 | ;; | |
5362 | (define_insn "mve_vabavq_p_<supf><mode>" | |
5363 | [ | |
5364 | (set (match_operand:SI 0 "s_register_operand" "=r") | |
5365 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
5366 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5367 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5368 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5369 | VABAVQ_P)) | |
5370 | ] | |
5371 | "TARGET_HAVE_MVE" | |
5372 | "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3" | |
5373 | [(set_attr "type" "mve_move") | |
5374 | ]) | |
5375 | ||
5376 | ;; | |
5377 | ;; [vqshluq_m_n_s]) | |
5378 | ;; | |
5379 | (define_insn "mve_vqshluq_m_n_s<mode>" | |
5380 | [ | |
5381 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5382 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5383 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5384 | (match_operand:SI 3 "mve_imm_7" "Ra") | |
5385 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5386 | VQSHLUQ_M_N_S)) | |
5387 | ] | |
5388 | "TARGET_HAVE_MVE" | |
5389 | "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3" | |
5390 | [(set_attr "type" "mve_move")]) | |
5391 | ||
5392 | ;; | |
5393 | ;; [vshlq_m_s, vshlq_m_u]) | |
5394 | ;; | |
5395 | (define_insn "mve_vshlq_m_<supf><mode>" | |
5396 | [ | |
5397 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5398 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5399 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5400 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5401 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5402 | VSHLQ_M)) | |
5403 | ] | |
5404 | "TARGET_HAVE_MVE" | |
5405 | "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
5406 | [(set_attr "type" "mve_move")]) | |
5407 | ||
5408 | ;; | |
5409 | ;; [vsriq_m_n_s, vsriq_m_n_u]) | |
5410 | ;; | |
5411 | (define_insn "mve_vsriq_m_n_<supf><mode>" | |
5412 | [ | |
5413 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5414 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5415 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5416 | (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") | |
5417 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5418 | VSRIQ_M_N)) | |
5419 | ] | |
5420 | "TARGET_HAVE_MVE" | |
5421 | "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3" | |
5422 | [(set_attr "type" "mve_move")]) | |
5423 | ||
5424 | ;; | |
5425 | ;; [vsubq_m_u, vsubq_m_s]) | |
5426 | ;; | |
5427 | (define_insn "mve_vsubq_m_<supf><mode>" | |
5428 | [ | |
5429 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5430 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5431 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5432 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5433 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5434 | VSUBQ_M)) | |
5435 | ] | |
5436 | "TARGET_HAVE_MVE" | |
5437 | "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3" | |
5438 | [(set_attr "type" "mve_move")]) | |
5439 | ||
5440 | ;; | |
5441 | ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) | |
5442 | ;; | |
5443 | (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>" | |
5444 | [ | |
5445 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5446 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
5447 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
d2ce75fe | 5448 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") |
db5db9d2 SP |
5449 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
5450 | VCVTQ_M_N_TO_F)) | |
5451 | ] | |
5452 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5453 | "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
5454 | [(set_attr "type" "mve_move") | |
5455 | (set_attr "length""8")]) | |
8eb3b6b9 SP |
5456 | ;; |
5457 | ;; [vabdq_m_s, vabdq_m_u]) | |
5458 | ;; | |
5459 | (define_insn "mve_vabdq_m_<supf><mode>" | |
5460 | [ | |
5461 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5462 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5463 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5464 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5465 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5466 | VABDQ_M)) | |
5467 | ] | |
5468 | "TARGET_HAVE_MVE" | |
5469 | "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5470 | [(set_attr "type" "mve_move") | |
5471 | (set_attr "length""8")]) | |
5472 | ||
5473 | ;; | |
5474 | ;; [vaddq_m_n_s, vaddq_m_n_u]) | |
5475 | ;; | |
5476 | (define_insn "mve_vaddq_m_n_<supf><mode>" | |
5477 | [ | |
5478 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5479 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5480 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5481 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5482 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5483 | VADDQ_M_N)) | |
5484 | ] | |
5485 | "TARGET_HAVE_MVE" | |
5486 | "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3" | |
5487 | [(set_attr "type" "mve_move") | |
5488 | (set_attr "length""8")]) | |
5489 | ||
5490 | ;; | |
5491 | ;; [vaddq_m_u, vaddq_m_s]) | |
5492 | ;; | |
5493 | (define_insn "mve_vaddq_m_<supf><mode>" | |
5494 | [ | |
5495 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5496 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5497 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5498 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5499 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5500 | VADDQ_M)) | |
5501 | ] | |
5502 | "TARGET_HAVE_MVE" | |
5503 | "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3" | |
5504 | [(set_attr "type" "mve_move") | |
5505 | (set_attr "length""8")]) | |
5506 | ||
5507 | ;; | |
5508 | ;; [vandq_m_u, vandq_m_s]) | |
5509 | ;; | |
5510 | (define_insn "mve_vandq_m_<supf><mode>" | |
5511 | [ | |
5512 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5513 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5514 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5515 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5516 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5517 | VANDQ_M)) | |
5518 | ] | |
5519 | "TARGET_HAVE_MVE" | |
5520 | "vpst\;vandt %q0, %q2, %q3" | |
5521 | [(set_attr "type" "mve_move") | |
5522 | (set_attr "length""8")]) | |
5523 | ||
5524 | ;; | |
5525 | ;; [vbicq_m_u, vbicq_m_s]) | |
5526 | ;; | |
5527 | (define_insn "mve_vbicq_m_<supf><mode>" | |
5528 | [ | |
5529 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5530 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5531 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5532 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5533 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5534 | VBICQ_M)) | |
5535 | ] | |
5536 | "TARGET_HAVE_MVE" | |
5537 | "vpst\;vbict %q0, %q2, %q3" | |
5538 | [(set_attr "type" "mve_move") | |
5539 | (set_attr "length""8")]) | |
5540 | ||
5541 | ;; | |
5542 | ;; [vbrsrq_m_n_u, vbrsrq_m_n_s]) | |
5543 | ;; | |
5544 | (define_insn "mve_vbrsrq_m_n_<supf><mode>" | |
5545 | [ | |
5546 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5547 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5548 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5549 | (match_operand:SI 3 "s_register_operand" "r") | |
5550 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5551 | VBRSRQ_M_N)) | |
5552 | ] | |
5553 | "TARGET_HAVE_MVE" | |
5554 | "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" | |
5555 | [(set_attr "type" "mve_move") | |
5556 | (set_attr "length""8")]) | |
5557 | ||
5558 | ;; | |
5559 | ;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]) | |
5560 | ;; | |
5561 | (define_insn "mve_vcaddq_rot270_m_<supf><mode>" | |
5562 | [ | |
6debbff6 | 5563 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
5564 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
5565 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5566 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5567 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5568 | VCADDQ_ROT270_M)) | |
5569 | ] | |
5570 | "TARGET_HAVE_MVE" | |
5571 | "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270" | |
5572 | [(set_attr "type" "mve_move") | |
5573 | (set_attr "length""8")]) | |
5574 | ||
5575 | ;; | |
5576 | ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]) | |
5577 | ;; | |
5578 | (define_insn "mve_vcaddq_rot90_m_<supf><mode>" | |
5579 | [ | |
6debbff6 | 5580 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
5581 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
5582 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5583 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5584 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5585 | VCADDQ_ROT90_M)) | |
5586 | ] | |
5587 | "TARGET_HAVE_MVE" | |
5588 | "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90" | |
5589 | [(set_attr "type" "mve_move") | |
5590 | (set_attr "length""8")]) | |
5591 | ||
5592 | ;; | |
5593 | ;; [veorq_m_s, veorq_m_u]) | |
5594 | ;; | |
5595 | (define_insn "mve_veorq_m_<supf><mode>" | |
5596 | [ | |
5597 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5598 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5599 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5600 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5601 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5602 | VEORQ_M)) | |
5603 | ] | |
5604 | "TARGET_HAVE_MVE" | |
5605 | "vpst\;veort %q0, %q2, %q3" | |
5606 | [(set_attr "type" "mve_move") | |
5607 | (set_attr "length""8")]) | |
5608 | ||
5609 | ;; | |
5610 | ;; [vhaddq_m_n_s, vhaddq_m_n_u]) | |
5611 | ;; | |
5612 | (define_insn "mve_vhaddq_m_n_<supf><mode>" | |
5613 | [ | |
5614 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5615 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5616 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5617 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5618 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5619 | VHADDQ_M_N)) | |
5620 | ] | |
5621 | "TARGET_HAVE_MVE" | |
5622 | "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
5623 | [(set_attr "type" "mve_move") | |
5624 | (set_attr "length""8")]) | |
5625 | ||
5626 | ;; | |
5627 | ;; [vhaddq_m_s, vhaddq_m_u]) | |
5628 | ;; | |
5629 | (define_insn "mve_vhaddq_m_<supf><mode>" | |
5630 | [ | |
5631 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5632 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5633 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5634 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5635 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5636 | VHADDQ_M)) | |
5637 | ] | |
5638 | "TARGET_HAVE_MVE" | |
5639 | "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5640 | [(set_attr "type" "mve_move") | |
5641 | (set_attr "length""8")]) | |
5642 | ||
5643 | ;; | |
5644 | ;; [vhsubq_m_n_s, vhsubq_m_n_u]) | |
5645 | ;; | |
5646 | (define_insn "mve_vhsubq_m_n_<supf><mode>" | |
5647 | [ | |
5648 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5649 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5650 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5651 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5652 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5653 | VHSUBQ_M_N)) | |
5654 | ] | |
5655 | "TARGET_HAVE_MVE" | |
5656 | "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
5657 | [(set_attr "type" "mve_move") | |
5658 | (set_attr "length""8")]) | |
5659 | ||
5660 | ;; | |
5661 | ;; [vhsubq_m_s, vhsubq_m_u]) | |
5662 | ;; | |
5663 | (define_insn "mve_vhsubq_m_<supf><mode>" | |
5664 | [ | |
5665 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5666 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5667 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5668 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5669 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5670 | VHSUBQ_M)) | |
5671 | ] | |
5672 | "TARGET_HAVE_MVE" | |
5673 | "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5674 | [(set_attr "type" "mve_move") | |
5675 | (set_attr "length""8")]) | |
5676 | ||
5677 | ;; | |
5678 | ;; [vmaxq_m_s, vmaxq_m_u]) | |
5679 | ;; | |
5680 | (define_insn "mve_vmaxq_m_<supf><mode>" | |
5681 | [ | |
5682 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5683 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5684 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5685 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5686 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5687 | VMAXQ_M)) | |
5688 | ] | |
5689 | "TARGET_HAVE_MVE" | |
5690 | "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5691 | [(set_attr "type" "mve_move") | |
5692 | (set_attr "length""8")]) | |
5693 | ||
5694 | ;; | |
5695 | ;; [vminq_m_s, vminq_m_u]) | |
5696 | ;; | |
5697 | (define_insn "mve_vminq_m_<supf><mode>" | |
5698 | [ | |
5699 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5700 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5701 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5702 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5703 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5704 | VMINQ_M)) | |
5705 | ] | |
5706 | "TARGET_HAVE_MVE" | |
5707 | "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5708 | [(set_attr "type" "mve_move") | |
5709 | (set_attr "length""8")]) | |
5710 | ||
5711 | ;; | |
5712 | ;; [vmladavaq_p_u, vmladavaq_p_s]) | |
5713 | ;; | |
5714 | (define_insn "mve_vmladavaq_p_<supf><mode>" | |
5715 | [ | |
3d537943 | 5716 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8eb3b6b9 SP |
5717 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
5718 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5719 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5720 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5721 | VMLADAVAQ_P)) | |
5722 | ] | |
5723 | "TARGET_HAVE_MVE" | |
5724 | "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3" | |
5725 | [(set_attr "type" "mve_move") | |
5726 | (set_attr "length""8")]) | |
5727 | ||
5728 | ;; | |
5729 | ;; [vmlaq_m_n_s, vmlaq_m_n_u]) | |
5730 | ;; | |
5731 | (define_insn "mve_vmlaq_m_n_<supf><mode>" | |
5732 | [ | |
5733 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5734 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5735 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5736 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5737 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5738 | VMLAQ_M_N)) | |
5739 | ] | |
5740 | "TARGET_HAVE_MVE" | |
5741 | "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
5742 | [(set_attr "type" "mve_move") | |
5743 | (set_attr "length""8")]) | |
5744 | ||
5745 | ;; | |
5746 | ;; [vmlasq_m_n_u, vmlasq_m_n_s]) | |
5747 | ;; | |
5748 | (define_insn "mve_vmlasq_m_n_<supf><mode>" | |
5749 | [ | |
5750 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5751 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5752 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5753 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5754 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5755 | VMLASQ_M_N)) | |
5756 | ] | |
5757 | "TARGET_HAVE_MVE" | |
5758 | "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
5759 | [(set_attr "type" "mve_move") | |
5760 | (set_attr "length""8")]) | |
5761 | ||
5762 | ;; | |
5763 | ;; [vmulhq_m_s, vmulhq_m_u]) | |
5764 | ;; | |
5765 | (define_insn "mve_vmulhq_m_<supf><mode>" | |
5766 | [ | |
5767 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5768 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5769 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5770 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5771 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5772 | VMULHQ_M)) | |
5773 | ] | |
5774 | "TARGET_HAVE_MVE" | |
5775 | "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5776 | [(set_attr "type" "mve_move") | |
5777 | (set_attr "length""8")]) | |
5778 | ||
5779 | ;; | |
5780 | ;; [vmullbq_int_m_u, vmullbq_int_m_s]) | |
5781 | ;; | |
5782 | (define_insn "mve_vmullbq_int_m_<supf><mode>" | |
5783 | [ | |
6debbff6 | 5784 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
5785 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
5786 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5787 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5788 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5789 | VMULLBQ_INT_M)) | |
5790 | ] | |
5791 | "TARGET_HAVE_MVE" | |
5792 | "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5793 | [(set_attr "type" "mve_move") | |
5794 | (set_attr "length""8")]) | |
5795 | ||
5796 | ;; | |
5797 | ;; [vmulltq_int_m_s, vmulltq_int_m_u]) | |
5798 | ;; | |
5799 | (define_insn "mve_vmulltq_int_m_<supf><mode>" | |
5800 | [ | |
6debbff6 | 5801 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
5802 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
5803 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5804 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5805 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5806 | VMULLTQ_INT_M)) | |
5807 | ] | |
5808 | "TARGET_HAVE_MVE" | |
5809 | "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
5810 | [(set_attr "type" "mve_move") | |
5811 | (set_attr "length""8")]) | |
5812 | ||
5813 | ;; | |
5814 | ;; [vmulq_m_n_u, vmulq_m_n_s]) | |
5815 | ;; | |
5816 | (define_insn "mve_vmulq_m_n_<supf><mode>" | |
5817 | [ | |
5818 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5819 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5820 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5821 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5822 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5823 | VMULQ_M_N)) | |
5824 | ] | |
5825 | "TARGET_HAVE_MVE" | |
5826 | "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3" | |
5827 | [(set_attr "type" "mve_move") | |
5828 | (set_attr "length""8")]) | |
5829 | ||
5830 | ;; | |
5831 | ;; [vmulq_m_s, vmulq_m_u]) | |
5832 | ;; | |
5833 | (define_insn "mve_vmulq_m_<supf><mode>" | |
5834 | [ | |
5835 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5836 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5837 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5838 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5839 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5840 | VMULQ_M)) | |
5841 | ] | |
5842 | "TARGET_HAVE_MVE" | |
5843 | "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3" | |
5844 | [(set_attr "type" "mve_move") | |
5845 | (set_attr "length""8")]) | |
5846 | ||
5847 | ;; | |
5848 | ;; [vornq_m_u, vornq_m_s]) | |
5849 | ;; | |
5850 | (define_insn "mve_vornq_m_<supf><mode>" | |
5851 | [ | |
5852 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5853 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5854 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5855 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5856 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5857 | VORNQ_M)) | |
5858 | ] | |
5859 | "TARGET_HAVE_MVE" | |
5860 | "vpst\;vornt %q0, %q2, %q3" | |
5861 | [(set_attr "type" "mve_move") | |
5862 | (set_attr "length""8")]) | |
5863 | ||
5864 | ;; | |
5865 | ;; [vorrq_m_s, vorrq_m_u]) | |
5866 | ;; | |
5867 | (define_insn "mve_vorrq_m_<supf><mode>" | |
5868 | [ | |
5869 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5870 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5871 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5872 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5873 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5874 | VORRQ_M)) | |
5875 | ] | |
5876 | "TARGET_HAVE_MVE" | |
5877 | "vpst\;vorrt %q0, %q2, %q3" | |
5878 | [(set_attr "type" "mve_move") | |
5879 | (set_attr "length""8")]) | |
5880 | ||
5881 | ;; | |
5882 | ;; [vqaddq_m_n_u, vqaddq_m_n_s]) | |
5883 | ;; | |
5884 | (define_insn "mve_vqaddq_m_n_<supf><mode>" | |
5885 | [ | |
5886 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5887 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5888 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5889 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5890 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5891 | VQADDQ_M_N)) | |
5892 | ] | |
5893 | "TARGET_HAVE_MVE" | |
5894 | "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
5895 | [(set_attr "type" "mve_move") | |
5896 | (set_attr "length""8")]) | |
5897 | ||
5898 | ;; | |
5899 | ;; [vqaddq_m_u, vqaddq_m_s]) | |
5900 | ;; | |
5901 | (define_insn "mve_vqaddq_m_<supf><mode>" | |
5902 | [ | |
5903 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5904 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5905 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5906 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5907 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5908 | VQADDQ_M)) | |
5909 | ] | |
5910 | "TARGET_HAVE_MVE" | |
5911 | "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
5912 | [(set_attr "type" "mve_move") | |
5913 | (set_attr "length""8")]) | |
5914 | ||
5915 | ;; | |
5916 | ;; [vqdmlahq_m_n_s]) | |
5917 | ;; | |
5918 | (define_insn "mve_vqdmlahq_m_n_s<mode>" | |
5919 | [ | |
5920 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5921 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5922 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5923 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5924 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5925 | VQDMLAHQ_M_N_S)) | |
5926 | ] | |
5927 | "TARGET_HAVE_MVE" | |
5928 | "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
5929 | [(set_attr "type" "mve_move") | |
5930 | (set_attr "length""8")]) | |
5931 | ||
afb198ee CL |
5932 | ;; |
5933 | ;; [vqdmlashq_m_n_s]) | |
5934 | ;; | |
5935 | (define_insn "mve_vqdmlashq_m_n_s<mode>" | |
5936 | [ | |
5937 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5938 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5939 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5940 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5941 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5942 | VQDMLASHQ_M_N_S)) | |
5943 | ] | |
5944 | "TARGET_HAVE_MVE" | |
5945 | "vpst\;vqdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
5946 | [(set_attr "type" "mve_move") | |
5947 | (set_attr "length""8")]) | |
5948 | ||
8eb3b6b9 SP |
5949 | ;; |
5950 | ;; [vqrdmlahq_m_n_s]) | |
5951 | ;; | |
5952 | (define_insn "mve_vqrdmlahq_m_n_s<mode>" | |
5953 | [ | |
5954 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5955 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5956 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5957 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5958 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5959 | VQRDMLAHQ_M_N_S)) | |
5960 | ] | |
5961 | "TARGET_HAVE_MVE" | |
5962 | "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
5963 | [(set_attr "type" "mve_move") | |
5964 | (set_attr "length""8")]) | |
5965 | ||
5966 | ;; | |
5967 | ;; [vqrdmlashq_m_n_s]) | |
5968 | ;; | |
5969 | (define_insn "mve_vqrdmlashq_m_n_s<mode>" | |
5970 | [ | |
5971 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5972 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5973 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5974 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
5975 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5976 | VQRDMLASHQ_M_N_S)) | |
5977 | ] | |
5978 | "TARGET_HAVE_MVE" | |
5979 | "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
5980 | [(set_attr "type" "mve_move") | |
5981 | (set_attr "length""8")]) | |
5982 | ||
5983 | ;; | |
5984 | ;; [vqrshlq_m_u, vqrshlq_m_s]) | |
5985 | ;; | |
5986 | (define_insn "mve_vqrshlq_m_<supf><mode>" | |
5987 | [ | |
5988 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5989 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5990 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
5991 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
5992 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
5993 | VQRSHLQ_M)) | |
5994 | ] | |
5995 | "TARGET_HAVE_MVE" | |
5996 | "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
5997 | [(set_attr "type" "mve_move") | |
5998 | (set_attr "length""8")]) | |
5999 | ||
6000 | ;; | |
6001 | ;; [vqshlq_m_n_s, vqshlq_m_n_u]) | |
6002 | ;; | |
6003 | (define_insn "mve_vqshlq_m_n_<supf><mode>" | |
6004 | [ | |
6005 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6006 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6007 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6008 | (match_operand:SI 3 "immediate_operand" "i") | |
6009 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6010 | VQSHLQ_M_N)) | |
6011 | ] | |
6012 | "TARGET_HAVE_MVE" | |
6013 | "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6014 | [(set_attr "type" "mve_move") | |
6015 | (set_attr "length""8")]) | |
6016 | ||
6017 | ;; | |
6018 | ;; [vqshlq_m_u, vqshlq_m_s]) | |
6019 | ;; | |
6020 | (define_insn "mve_vqshlq_m_<supf><mode>" | |
6021 | [ | |
6022 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6023 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6024 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6025 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6026 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6027 | VQSHLQ_M)) | |
6028 | ] | |
6029 | "TARGET_HAVE_MVE" | |
6030 | "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
6031 | [(set_attr "type" "mve_move") | |
6032 | (set_attr "length""8")]) | |
6033 | ||
6034 | ;; | |
6035 | ;; [vqsubq_m_n_u, vqsubq_m_n_s]) | |
6036 | ;; | |
6037 | (define_insn "mve_vqsubq_m_n_<supf><mode>" | |
6038 | [ | |
6039 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6040 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6041 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6042 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6043 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6044 | VQSUBQ_M_N)) | |
6045 | ] | |
6046 | "TARGET_HAVE_MVE" | |
6047 | "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6048 | [(set_attr "type" "mve_move") | |
6049 | (set_attr "length""8")]) | |
6050 | ||
6051 | ;; | |
6052 | ;; [vqsubq_m_u, vqsubq_m_s]) | |
6053 | ;; | |
6054 | (define_insn "mve_vqsubq_m_<supf><mode>" | |
6055 | [ | |
6056 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6057 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6058 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6059 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6060 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6061 | VQSUBQ_M)) | |
6062 | ] | |
6063 | "TARGET_HAVE_MVE" | |
6064 | "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
6065 | [(set_attr "type" "mve_move") | |
6066 | (set_attr "length""8")]) | |
6067 | ||
6068 | ;; | |
6069 | ;; [vrhaddq_m_u, vrhaddq_m_s]) | |
6070 | ;; | |
6071 | (define_insn "mve_vrhaddq_m_<supf><mode>" | |
6072 | [ | |
6073 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6074 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6075 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6076 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6077 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6078 | VRHADDQ_M)) | |
6079 | ] | |
6080 | "TARGET_HAVE_MVE" | |
6081 | "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
6082 | [(set_attr "type" "mve_move") | |
6083 | (set_attr "length""8")]) | |
6084 | ||
6085 | ;; | |
6086 | ;; [vrmulhq_m_u, vrmulhq_m_s]) | |
6087 | ;; | |
6088 | (define_insn "mve_vrmulhq_m_<supf><mode>" | |
6089 | [ | |
6090 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6091 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6092 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6093 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6094 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6095 | VRMULHQ_M)) | |
6096 | ] | |
6097 | "TARGET_HAVE_MVE" | |
6098 | "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
6099 | [(set_attr "type" "mve_move") | |
6100 | (set_attr "length""8")]) | |
6101 | ||
6102 | ;; | |
6103 | ;; [vrshlq_m_s, vrshlq_m_u]) | |
6104 | ;; | |
6105 | (define_insn "mve_vrshlq_m_<supf><mode>" | |
6106 | [ | |
6107 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6108 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6109 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6110 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6111 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6112 | VRSHLQ_M)) | |
6113 | ] | |
6114 | "TARGET_HAVE_MVE" | |
6115 | "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" | |
6116 | [(set_attr "type" "mve_move") | |
6117 | (set_attr "length""8")]) | |
6118 | ||
6119 | ;; | |
6120 | ;; [vrshrq_m_n_s, vrshrq_m_n_u]) | |
6121 | ;; | |
6122 | (define_insn "mve_vrshrq_m_n_<supf><mode>" | |
6123 | [ | |
6124 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6125 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6126 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6127 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") | |
6128 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6129 | VRSHRQ_M_N)) | |
6130 | ] | |
6131 | "TARGET_HAVE_MVE" | |
6132 | "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6133 | [(set_attr "type" "mve_move") | |
6134 | (set_attr "length""8")]) | |
6135 | ||
6136 | ;; | |
6137 | ;; [vshlq_m_n_s, vshlq_m_n_u]) | |
6138 | ;; | |
6139 | (define_insn "mve_vshlq_m_n_<supf><mode>" | |
6140 | [ | |
6141 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6142 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6143 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6144 | (match_operand:SI 3 "immediate_operand" "i") | |
6145 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6146 | VSHLQ_M_N)) | |
6147 | ] | |
6148 | "TARGET_HAVE_MVE" | |
6149 | "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6150 | [(set_attr "type" "mve_move") | |
6151 | (set_attr "length""8")]) | |
6152 | ||
6153 | ;; | |
6154 | ;; [vshrq_m_n_s, vshrq_m_n_u]) | |
6155 | ;; | |
6156 | (define_insn "mve_vshrq_m_n_<supf><mode>" | |
6157 | [ | |
6158 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6159 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6160 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6161 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") | |
6162 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6163 | VSHRQ_M_N)) | |
6164 | ] | |
6165 | "TARGET_HAVE_MVE" | |
6166 | "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6167 | [(set_attr "type" "mve_move") | |
6168 | (set_attr "length""8")]) | |
6169 | ||
6170 | ;; | |
6171 | ;; [vsliq_m_n_u, vsliq_m_n_s]) | |
6172 | ;; | |
6173 | (define_insn "mve_vsliq_m_n_<supf><mode>" | |
6174 | [ | |
6175 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6176 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6177 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6178 | (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") | |
6179 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6180 | VSLIQ_M_N)) | |
6181 | ] | |
6182 | "TARGET_HAVE_MVE" | |
6183 | "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3" | |
6184 | [(set_attr "type" "mve_move") | |
6185 | (set_attr "length""8")]) | |
6186 | ||
6187 | ;; | |
6188 | ;; [vsubq_m_n_s, vsubq_m_n_u]) | |
6189 | ;; | |
6190 | (define_insn "mve_vsubq_m_n_<supf><mode>" | |
6191 | [ | |
6192 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6193 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6194 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6195 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6196 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6197 | VSUBQ_M_N)) | |
6198 | ] | |
6199 | "TARGET_HAVE_MVE" | |
6200 | "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3" | |
6201 | [(set_attr "type" "mve_move") | |
6202 | (set_attr "length""8")]) | |
6203 | ||
6204 | ;; | |
6205 | ;; [vhcaddq_rot270_m_s]) | |
6206 | ;; | |
6207 | (define_insn "mve_vhcaddq_rot270_m_s<mode>" | |
6208 | [ | |
6debbff6 | 6209 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
6210 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
6211 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6212 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6213 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6214 | VHCADDQ_ROT270_M_S)) | |
6215 | ] | |
6216 | "TARGET_HAVE_MVE" | |
6217 | "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270" | |
6218 | [(set_attr "type" "mve_move") | |
6219 | (set_attr "length""8")]) | |
6220 | ||
6221 | ;; | |
6222 | ;; [vhcaddq_rot90_m_s]) | |
6223 | ;; | |
6224 | (define_insn "mve_vhcaddq_rot90_m_s<mode>" | |
6225 | [ | |
6debbff6 | 6226 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
6227 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
6228 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6229 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6230 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6231 | VHCADDQ_ROT90_M_S)) | |
6232 | ] | |
6233 | "TARGET_HAVE_MVE" | |
6234 | "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90" | |
6235 | [(set_attr "type" "mve_move") | |
6236 | (set_attr "length""8")]) | |
6237 | ||
6238 | ;; | |
6239 | ;; [vmladavaxq_p_s]) | |
6240 | ;; | |
6241 | (define_insn "mve_vmladavaxq_p_s<mode>" | |
6242 | [ | |
3d537943 | 6243 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8eb3b6b9 SP |
6244 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
6245 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6246 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6247 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6248 | VMLADAVAXQ_P_S)) | |
6249 | ] | |
6250 | "TARGET_HAVE_MVE" | |
6251 | "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3" | |
6252 | [(set_attr "type" "mve_move") | |
6253 | (set_attr "length""8")]) | |
6254 | ||
6255 | ;; | |
6256 | ;; [vmlsdavaq_p_s]) | |
6257 | ;; | |
6258 | (define_insn "mve_vmlsdavaq_p_s<mode>" | |
6259 | [ | |
3d537943 | 6260 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8eb3b6b9 SP |
6261 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
6262 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6263 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6264 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6265 | VMLSDAVAQ_P_S)) | |
6266 | ] | |
6267 | "TARGET_HAVE_MVE" | |
6268 | "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3" | |
6269 | [(set_attr "type" "mve_move") | |
6270 | (set_attr "length""8")]) | |
6271 | ||
6272 | ;; | |
6273 | ;; [vmlsdavaxq_p_s]) | |
6274 | ;; | |
6275 | (define_insn "mve_vmlsdavaxq_p_s<mode>" | |
6276 | [ | |
3d537943 | 6277 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8eb3b6b9 SP |
6278 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
6279 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6280 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6281 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6282 | VMLSDAVAXQ_P_S)) | |
6283 | ] | |
6284 | "TARGET_HAVE_MVE" | |
6285 | "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3" | |
6286 | [(set_attr "type" "mve_move") | |
6287 | (set_attr "length""8")]) | |
6288 | ||
6289 | ;; | |
6290 | ;; [vqdmladhq_m_s]) | |
6291 | ;; | |
6292 | (define_insn "mve_vqdmladhq_m_s<mode>" | |
6293 | [ | |
6294 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6295 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6296 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6297 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6298 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6299 | VQDMLADHQ_M_S)) | |
6300 | ] | |
6301 | "TARGET_HAVE_MVE" | |
6302 | "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6303 | [(set_attr "type" "mve_move") | |
6304 | (set_attr "length""8")]) | |
6305 | ||
6306 | ;; | |
6307 | ;; [vqdmladhxq_m_s]) | |
6308 | ;; | |
6309 | (define_insn "mve_vqdmladhxq_m_s<mode>" | |
6310 | [ | |
6311 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6312 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6313 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6314 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6315 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6316 | VQDMLADHXQ_M_S)) | |
6317 | ] | |
6318 | "TARGET_HAVE_MVE" | |
6319 | "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6320 | [(set_attr "type" "mve_move") | |
6321 | (set_attr "length""8")]) | |
6322 | ||
6323 | ;; | |
6324 | ;; [vqdmlsdhq_m_s]) | |
6325 | ;; | |
6326 | (define_insn "mve_vqdmlsdhq_m_s<mode>" | |
6327 | [ | |
6328 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6329 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6330 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6331 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6332 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6333 | VQDMLSDHQ_M_S)) | |
6334 | ] | |
6335 | "TARGET_HAVE_MVE" | |
6336 | "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6337 | [(set_attr "type" "mve_move") | |
6338 | (set_attr "length""8")]) | |
6339 | ||
6340 | ;; | |
6341 | ;; [vqdmlsdhxq_m_s]) | |
6342 | ;; | |
6343 | (define_insn "mve_vqdmlsdhxq_m_s<mode>" | |
6344 | [ | |
6345 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6346 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6347 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6348 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6349 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6350 | VQDMLSDHXQ_M_S)) | |
6351 | ] | |
6352 | "TARGET_HAVE_MVE" | |
6353 | "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6354 | [(set_attr "type" "mve_move") | |
6355 | (set_attr "length""8")]) | |
6356 | ||
6357 | ;; | |
6358 | ;; [vqdmulhq_m_n_s]) | |
6359 | ;; | |
6360 | (define_insn "mve_vqdmulhq_m_n_s<mode>" | |
6361 | [ | |
6362 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6363 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6364 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6365 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6366 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6367 | VQDMULHQ_M_N_S)) | |
6368 | ] | |
6369 | "TARGET_HAVE_MVE" | |
6370 | "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6371 | [(set_attr "type" "mve_move") | |
6372 | (set_attr "length""8")]) | |
6373 | ||
6374 | ;; | |
6375 | ;; [vqdmulhq_m_s]) | |
6376 | ;; | |
6377 | (define_insn "mve_vqdmulhq_m_s<mode>" | |
6378 | [ | |
6379 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6380 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6381 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6382 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6383 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6384 | VQDMULHQ_M_S)) | |
6385 | ] | |
6386 | "TARGET_HAVE_MVE" | |
6387 | "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6388 | [(set_attr "type" "mve_move") | |
6389 | (set_attr "length""8")]) | |
6390 | ||
6391 | ;; | |
6392 | ;; [vqrdmladhq_m_s]) | |
6393 | ;; | |
6394 | (define_insn "mve_vqrdmladhq_m_s<mode>" | |
6395 | [ | |
6396 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6397 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6398 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6399 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6400 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6401 | VQRDMLADHQ_M_S)) | |
6402 | ] | |
6403 | "TARGET_HAVE_MVE" | |
6404 | "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6405 | [(set_attr "type" "mve_move") | |
6406 | (set_attr "length""8")]) | |
6407 | ||
6408 | ;; | |
6409 | ;; [vqrdmladhxq_m_s]) | |
6410 | ;; | |
6411 | (define_insn "mve_vqrdmladhxq_m_s<mode>" | |
6412 | [ | |
6413 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6414 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6415 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6416 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6417 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6418 | VQRDMLADHXQ_M_S)) | |
6419 | ] | |
6420 | "TARGET_HAVE_MVE" | |
6421 | "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6422 | [(set_attr "type" "mve_move") | |
6423 | (set_attr "length""8")]) | |
6424 | ||
6425 | ;; | |
6426 | ;; [vqrdmlsdhq_m_s]) | |
6427 | ;; | |
6428 | (define_insn "mve_vqrdmlsdhq_m_s<mode>" | |
6429 | [ | |
6430 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6431 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6432 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6433 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6434 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6435 | VQRDMLSDHQ_M_S)) | |
6436 | ] | |
6437 | "TARGET_HAVE_MVE" | |
6438 | "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6439 | [(set_attr "type" "mve_move") | |
6440 | (set_attr "length""8")]) | |
6441 | ||
6442 | ;; | |
6443 | ;; [vqrdmlsdhxq_m_s]) | |
6444 | ;; | |
6445 | (define_insn "mve_vqrdmlsdhxq_m_s<mode>" | |
6446 | [ | |
6447 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6448 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6449 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6450 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6451 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6452 | VQRDMLSDHXQ_M_S)) | |
6453 | ] | |
6454 | "TARGET_HAVE_MVE" | |
6455 | "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6456 | [(set_attr "type" "mve_move") | |
6457 | (set_attr "length""8")]) | |
6458 | ||
6459 | ;; | |
6460 | ;; [vqrdmulhq_m_n_s]) | |
6461 | ;; | |
6462 | (define_insn "mve_vqrdmulhq_m_n_s<mode>" | |
6463 | [ | |
6464 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6465 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6466 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6467 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6468 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6469 | VQRDMULHQ_M_N_S)) | |
6470 | ] | |
6471 | "TARGET_HAVE_MVE" | |
6472 | "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6473 | [(set_attr "type" "mve_move") | |
6474 | (set_attr "length""8")]) | |
6475 | ||
6476 | ;; | |
6477 | ;; [vqrdmulhq_m_s]) | |
6478 | ;; | |
6479 | (define_insn "mve_vqrdmulhq_m_s<mode>" | |
6480 | [ | |
6481 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6482 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
6483 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
6484 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
6485 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6486 | VQRDMULHQ_M_S)) | |
6487 | ] | |
6488 | "TARGET_HAVE_MVE" | |
6489 | "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6490 | [(set_attr "type" "mve_move") | |
6491 | (set_attr "length""8")]) | |
6492 | ||
f2170a37 SP |
6493 | ;; |
6494 | ;; [vmlaldavaq_p_u, vmlaldavaq_p_s]) | |
6495 | ;; | |
6496 | (define_insn "mve_vmlaldavaq_p_<supf><mode>" | |
6497 | [ | |
6498 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6499 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6500 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6501 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6502 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6503 | VMLALDAVAQ_P)) | |
6504 | ] | |
6505 | "TARGET_HAVE_MVE" | |
6506 | "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
6507 | [(set_attr "type" "mve_move") | |
6508 | (set_attr "length""8")]) | |
6509 | ||
6510 | ;; | |
237f12da | 6511 | ;; [vmlaldavaxq_p_s]) |
f2170a37 SP |
6512 | ;; |
6513 | (define_insn "mve_vmlaldavaxq_p_<supf><mode>" | |
6514 | [ | |
6515 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6516 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6517 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6518 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6519 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6520 | VMLALDAVAXQ_P)) | |
6521 | ] | |
6522 | "TARGET_HAVE_MVE" | |
6523 | "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3" | |
6524 | [(set_attr "type" "mve_move") | |
6525 | (set_attr "length""8")]) | |
6526 | ||
6527 | ;; | |
6528 | ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]) | |
6529 | ;; | |
6530 | (define_insn "mve_vqrshrnbq_m_n_<supf><mode>" | |
6531 | [ | |
6532 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6533 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6534 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6535 | (match_operand:SI 3 "mve_imm_8" "Rb") | |
6536 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6537 | VQRSHRNBQ_M_N)) | |
6538 | ] | |
6539 | "TARGET_HAVE_MVE" | |
6540 | "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
6541 | [(set_attr "type" "mve_move") | |
6542 | (set_attr "length""8")]) | |
6543 | ||
6544 | ;; | |
6545 | ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]) | |
6546 | ;; | |
6547 | (define_insn "mve_vqrshrntq_m_n_<supf><mode>" | |
6548 | [ | |
6549 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6550 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6551 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6552 | (match_operand:SI 3 "mve_imm_8" "Rb") | |
6553 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6554 | VQRSHRNTQ_M_N)) | |
6555 | ] | |
6556 | "TARGET_HAVE_MVE" | |
6557 | "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
6558 | [(set_attr "type" "mve_move") | |
6559 | (set_attr "length""8")]) | |
6560 | ||
6561 | ;; | |
6562 | ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]) | |
6563 | ;; | |
6564 | (define_insn "mve_vqshrnbq_m_n_<supf><mode>" | |
6565 | [ | |
6566 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6567 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6568 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 6569 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") |
f2170a37 SP |
6570 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
6571 | VQSHRNBQ_M_N)) | |
6572 | ] | |
d2ce75fe | 6573 | "TARGET_HAVE_MVE" |
f2170a37 SP |
6574 | "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" |
6575 | [(set_attr "type" "mve_move") | |
6576 | (set_attr "length""8")]) | |
6577 | ||
6578 | ;; | |
6579 | ;; [vqshrntq_m_n_s, vqshrntq_m_n_u]) | |
6580 | ;; | |
6581 | (define_insn "mve_vqshrntq_m_n_<supf><mode>" | |
6582 | [ | |
6583 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6584 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6585 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 6586 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") |
f2170a37 SP |
6587 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
6588 | VQSHRNTQ_M_N)) | |
6589 | ] | |
6590 | "TARGET_HAVE_MVE" | |
6591 | "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6592 | [(set_attr "type" "mve_move") | |
6593 | (set_attr "length""8")]) | |
6594 | ||
6595 | ;; | |
6596 | ;; [vrmlaldavhaq_p_s]) | |
6597 | ;; | |
6598 | (define_insn "mve_vrmlaldavhaq_p_sv4si" | |
6599 | [ | |
6600 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6601 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6602 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6603 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6604 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6605 | VRMLALDAVHAQ_P_S)) | |
6606 | ] | |
6607 | "TARGET_HAVE_MVE" | |
6608 | "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3" | |
6609 | [(set_attr "type" "mve_move") | |
6610 | (set_attr "length""8")]) | |
6611 | ||
6612 | ;; | |
6613 | ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]) | |
6614 | ;; | |
6615 | (define_insn "mve_vrshrnbq_m_n_<supf><mode>" | |
6616 | [ | |
6617 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6618 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6619 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6620 | (match_operand:SI 3 "mve_imm_8" "Rb") | |
6621 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6622 | VRSHRNBQ_M_N)) | |
6623 | ] | |
6624 | "TARGET_HAVE_MVE" | |
6625 | "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3" | |
6626 | [(set_attr "type" "mve_move") | |
6627 | (set_attr "length""8")]) | |
6628 | ||
6629 | ;; | |
6630 | ;; [vrshrntq_m_n_u, vrshrntq_m_n_s]) | |
6631 | ;; | |
6632 | (define_insn "mve_vrshrntq_m_n_<supf><mode>" | |
6633 | [ | |
6634 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6635 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6636 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6637 | (match_operand:SI 3 "mve_imm_8" "Rb") | |
6638 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6639 | VRSHRNTQ_M_N)) | |
6640 | ] | |
6641 | "TARGET_HAVE_MVE" | |
6642 | "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3" | |
6643 | [(set_attr "type" "mve_move") | |
6644 | (set_attr "length""8")]) | |
6645 | ||
6646 | ;; | |
6647 | ;; [vshllbq_m_n_u, vshllbq_m_n_s]) | |
6648 | ;; | |
6649 | (define_insn "mve_vshllbq_m_n_<supf><mode>" | |
6650 | [ | |
6651 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
6652 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
6653 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
6654 | (match_operand:SI 3 "immediate_operand" "i") | |
6655 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6656 | VSHLLBQ_M_N)) | |
6657 | ] | |
6658 | "TARGET_HAVE_MVE" | |
6659 | "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6660 | [(set_attr "type" "mve_move") | |
6661 | (set_attr "length""8")]) | |
6662 | ||
6663 | ;; | |
6664 | ;; [vshlltq_m_n_u, vshlltq_m_n_s]) | |
6665 | ;; | |
6666 | (define_insn "mve_vshlltq_m_n_<supf><mode>" | |
6667 | [ | |
6668 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
6669 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
6670 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
6671 | (match_operand:SI 3 "immediate_operand" "i") | |
6672 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6673 | VSHLLTQ_M_N)) | |
6674 | ] | |
6675 | "TARGET_HAVE_MVE" | |
6676 | "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
6677 | [(set_attr "type" "mve_move") | |
6678 | (set_attr "length""8")]) | |
6679 | ||
6680 | ;; | |
6681 | ;; [vshrnbq_m_n_s, vshrnbq_m_n_u]) | |
6682 | ;; | |
6683 | (define_insn "mve_vshrnbq_m_n_<supf><mode>" | |
6684 | [ | |
6685 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6686 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6687 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6688 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") | |
6689 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6690 | VSHRNBQ_M_N)) | |
6691 | ] | |
6692 | "TARGET_HAVE_MVE" | |
6693 | "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3" | |
6694 | [(set_attr "type" "mve_move") | |
6695 | (set_attr "length""8")]) | |
6696 | ||
6697 | ;; | |
6698 | ;; [vshrntq_m_n_s, vshrntq_m_n_u]) | |
6699 | ;; | |
6700 | (define_insn "mve_vshrntq_m_n_<supf><mode>" | |
6701 | [ | |
6702 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6703 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6704 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6705 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") | |
6706 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6707 | VSHRNTQ_M_N)) | |
6708 | ] | |
6709 | "TARGET_HAVE_MVE" | |
6710 | "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3" | |
6711 | [(set_attr "type" "mve_move") | |
6712 | (set_attr "length""8")]) | |
6713 | ||
6714 | ;; | |
6715 | ;; [vmlsldavaq_p_s]) | |
6716 | ;; | |
6717 | (define_insn "mve_vmlsldavaq_p_s<mode>" | |
6718 | [ | |
6719 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6720 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6721 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6722 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6723 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6724 | VMLSLDAVAQ_P_S)) | |
6725 | ] | |
6726 | "TARGET_HAVE_MVE" | |
6727 | "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" | |
6728 | [(set_attr "type" "mve_move") | |
6729 | (set_attr "length""8")]) | |
6730 | ||
6731 | ;; | |
6732 | ;; [vmlsldavaxq_p_s]) | |
6733 | ;; | |
6734 | (define_insn "mve_vmlsldavaxq_p_s<mode>" | |
6735 | [ | |
6736 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6737 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6738 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6739 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6740 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6741 | VMLSLDAVAXQ_P_S)) | |
6742 | ] | |
6743 | "TARGET_HAVE_MVE" | |
6744 | "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" | |
6745 | [(set_attr "type" "mve_move") | |
6746 | (set_attr "length""8")]) | |
6747 | ||
6748 | ;; | |
6749 | ;; [vmullbq_poly_m_p]) | |
6750 | ;; | |
6751 | (define_insn "mve_vmullbq_poly_m_p<mode>" | |
6752 | [ | |
6753 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
6754 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
6755 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
6756 | (match_operand:MVE_3 3 "s_register_operand" "w") | |
6757 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6758 | VMULLBQ_POLY_M_P)) | |
6759 | ] | |
6760 | "TARGET_HAVE_MVE" | |
6761 | "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3" | |
6762 | [(set_attr "type" "mve_move") | |
6763 | (set_attr "length""8")]) | |
6764 | ||
6765 | ;; | |
6766 | ;; [vmulltq_poly_m_p]) | |
6767 | ;; | |
6768 | (define_insn "mve_vmulltq_poly_m_p<mode>" | |
6769 | [ | |
6770 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
6771 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
6772 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
6773 | (match_operand:MVE_3 3 "s_register_operand" "w") | |
6774 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6775 | VMULLTQ_POLY_M_P)) | |
6776 | ] | |
6777 | "TARGET_HAVE_MVE" | |
6778 | "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3" | |
6779 | [(set_attr "type" "mve_move") | |
6780 | (set_attr "length""8")]) | |
6781 | ||
6782 | ;; | |
6783 | ;; [vqdmullbq_m_n_s]) | |
6784 | ;; | |
6785 | (define_insn "mve_vqdmullbq_m_n_s<mode>" | |
6786 | [ | |
6debbff6 | 6787 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
6788 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
6789 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6790 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6791 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6792 | VQDMULLBQ_M_N_S)) | |
6793 | ] | |
6794 | "TARGET_HAVE_MVE" | |
6795 | "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6796 | [(set_attr "type" "mve_move") | |
6797 | (set_attr "length""8")]) | |
6798 | ||
6799 | ;; | |
6800 | ;; [vqdmullbq_m_s]) | |
6801 | ;; | |
6802 | (define_insn "mve_vqdmullbq_m_s<mode>" | |
6803 | [ | |
6debbff6 | 6804 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
6805 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
6806 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6807 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6808 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6809 | VQDMULLBQ_M_S)) | |
6810 | ] | |
6811 | "TARGET_HAVE_MVE" | |
6812 | "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6813 | [(set_attr "type" "mve_move") | |
6814 | (set_attr "length""8")]) | |
6815 | ||
6816 | ;; | |
6817 | ;; [vqdmulltq_m_n_s]) | |
6818 | ;; | |
6819 | (define_insn "mve_vqdmulltq_m_n_s<mode>" | |
6820 | [ | |
6debbff6 | 6821 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
6822 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
6823 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6824 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
6825 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6826 | VQDMULLTQ_M_N_S)) | |
6827 | ] | |
6828 | "TARGET_HAVE_MVE" | |
6829 | "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6830 | [(set_attr "type" "mve_move") | |
6831 | (set_attr "length""8")]) | |
6832 | ||
6833 | ;; | |
6834 | ;; [vqdmulltq_m_s]) | |
6835 | ;; | |
6836 | (define_insn "mve_vqdmulltq_m_s<mode>" | |
6837 | [ | |
6debbff6 | 6838 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
6839 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
6840 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6841 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
6842 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6843 | VQDMULLTQ_M_S)) | |
6844 | ] | |
6845 | "TARGET_HAVE_MVE" | |
6846 | "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
6847 | [(set_attr "type" "mve_move") | |
6848 | (set_attr "length""8")]) | |
6849 | ||
6850 | ;; | |
6851 | ;; [vqrshrunbq_m_n_s]) | |
6852 | ;; | |
6853 | (define_insn "mve_vqrshrunbq_m_n_s<mode>" | |
6854 | [ | |
6855 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6856 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6857 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
6858 | (match_operand:SI 3 "mve_imm_8" "Rb") | |
6859 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6860 | VQRSHRUNBQ_M_N_S)) | |
6861 | ] | |
6862 | "TARGET_HAVE_MVE" | |
6863 | "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6864 | [(set_attr "type" "mve_move") | |
6865 | (set_attr "length""8")]) | |
6866 | ||
6867 | ;; | |
6868 | ;; [vqrshruntq_m_n_s]) | |
6869 | ;; | |
6870 | (define_insn "mve_vqrshruntq_m_n_s<mode>" | |
6871 | [ | |
6872 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6873 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6874 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 6875 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") |
f2170a37 SP |
6876 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
6877 | VQRSHRUNTQ_M_N_S)) | |
6878 | ] | |
6879 | "TARGET_HAVE_MVE" | |
6880 | "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6881 | [(set_attr "type" "mve_move") | |
6882 | (set_attr "length""8")]) | |
6883 | ||
6884 | ;; | |
6885 | ;; [vqshrunbq_m_n_s]) | |
6886 | ;; | |
6887 | (define_insn "mve_vqshrunbq_m_n_s<mode>" | |
6888 | [ | |
6889 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6890 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6891 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 6892 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") |
f2170a37 SP |
6893 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
6894 | VQSHRUNBQ_M_N_S)) | |
6895 | ] | |
6896 | "TARGET_HAVE_MVE" | |
6897 | "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6898 | [(set_attr "type" "mve_move") | |
6899 | (set_attr "length""8")]) | |
6900 | ||
6901 | ;; | |
6902 | ;; [vqshruntq_m_n_s]) | |
6903 | ;; | |
6904 | (define_insn "mve_vqshruntq_m_n_s<mode>" | |
6905 | [ | |
6906 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
6907 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
6908 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
d2ce75fe | 6909 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") |
f2170a37 SP |
6910 | (match_operand:HI 4 "vpr_register_operand" "Up")] |
6911 | VQSHRUNTQ_M_N_S)) | |
6912 | ] | |
6913 | "TARGET_HAVE_MVE" | |
6914 | "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
6915 | [(set_attr "type" "mve_move") | |
6916 | (set_attr "length""8")]) | |
6917 | ||
6918 | ;; | |
6919 | ;; [vrmlaldavhaq_p_u]) | |
6920 | ;; | |
6921 | (define_insn "mve_vrmlaldavhaq_p_uv4si" | |
6922 | [ | |
6923 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6924 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6925 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6926 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6927 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6928 | VRMLALDAVHAQ_P_U)) | |
6929 | ] | |
6930 | "TARGET_HAVE_MVE" | |
6931 | "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3" | |
6932 | [(set_attr "type" "mve_move") | |
6933 | (set_attr "length""8")]) | |
6934 | ||
6935 | ;; | |
6936 | ;; [vrmlaldavhaxq_p_s]) | |
6937 | ;; | |
6938 | (define_insn "mve_vrmlaldavhaxq_p_sv4si" | |
6939 | [ | |
6940 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6941 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6942 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6943 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6944 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6945 | VRMLALDAVHAXQ_P_S)) | |
6946 | ] | |
6947 | "TARGET_HAVE_MVE" | |
6948 | "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3" | |
6949 | [(set_attr "type" "mve_move") | |
6950 | (set_attr "length""8")]) | |
6951 | ||
6952 | ;; | |
6953 | ;; [vrmlsldavhaq_p_s]) | |
6954 | ;; | |
6955 | (define_insn "mve_vrmlsldavhaq_p_sv4si" | |
6956 | [ | |
6957 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6958 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6959 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6960 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6961 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6962 | VRMLSLDAVHAQ_P_S)) | |
6963 | ] | |
6964 | "TARGET_HAVE_MVE" | |
6965 | "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3" | |
6966 | [(set_attr "type" "mve_move") | |
6967 | (set_attr "length""8")]) | |
6968 | ||
6969 | ;; | |
6970 | ;; [vrmlsldavhaxq_p_s]) | |
6971 | ;; | |
6972 | (define_insn "mve_vrmlsldavhaxq_p_sv4si" | |
6973 | [ | |
6974 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
6975 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
6976 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6977 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6978 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6979 | VRMLSLDAVHAXQ_P_S)) | |
6980 | ] | |
6981 | "TARGET_HAVE_MVE" | |
6982 | "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" | |
6983 | [(set_attr "type" "mve_move") | |
6984 | (set_attr "length""8")]) | |
532e9e24 SP |
6985 | ;; |
6986 | ;; [vabdq_m_f]) | |
6987 | ;; | |
6988 | (define_insn "mve_vabdq_m_f<mode>" | |
6989 | [ | |
6990 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
6991 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
6992 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
6993 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
6994 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
6995 | VABDQ_M_F)) | |
6996 | ] | |
6997 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6998 | "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3" | |
6999 | [(set_attr "type" "mve_move") | |
7000 | (set_attr "length""8")]) | |
7001 | ||
7002 | ;; | |
7003 | ;; [vaddq_m_f]) | |
7004 | ;; | |
7005 | (define_insn "mve_vaddq_m_f<mode>" | |
7006 | [ | |
7007 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7008 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7009 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7010 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7011 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7012 | VADDQ_M_F)) | |
7013 | ] | |
7014 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7015 | "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3" | |
7016 | [(set_attr "type" "mve_move") | |
7017 | (set_attr "length""8")]) | |
7018 | ||
7019 | ;; | |
7020 | ;; [vaddq_m_n_f]) | |
7021 | ;; | |
7022 | (define_insn "mve_vaddq_m_n_f<mode>" | |
7023 | [ | |
7024 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7025 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7026 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7027 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
7028 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7029 | VADDQ_M_N_F)) | |
7030 | ] | |
7031 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7032 | "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3" | |
7033 | [(set_attr "type" "mve_move") | |
7034 | (set_attr "length""8")]) | |
7035 | ||
7036 | ;; | |
7037 | ;; [vandq_m_f]) | |
7038 | ;; | |
7039 | (define_insn "mve_vandq_m_f<mode>" | |
7040 | [ | |
7041 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7042 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7043 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7044 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7045 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7046 | VANDQ_M_F)) | |
7047 | ] | |
7048 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7049 | "vpst\;vandt %q0, %q2, %q3" | |
7050 | [(set_attr "type" "mve_move") | |
7051 | (set_attr "length""8")]) | |
7052 | ||
7053 | ;; | |
7054 | ;; [vbicq_m_f]) | |
7055 | ;; | |
7056 | (define_insn "mve_vbicq_m_f<mode>" | |
7057 | [ | |
7058 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7059 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7060 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7061 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7062 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7063 | VBICQ_M_F)) | |
7064 | ] | |
7065 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7066 | "vpst\;vbict %q0, %q2, %q3" | |
7067 | [(set_attr "type" "mve_move") | |
7068 | (set_attr "length""8")]) | |
7069 | ||
7070 | ;; | |
7071 | ;; [vbrsrq_m_n_f]) | |
7072 | ;; | |
7073 | (define_insn "mve_vbrsrq_m_n_f<mode>" | |
7074 | [ | |
7075 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7076 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7077 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7078 | (match_operand:SI 3 "s_register_operand" "r") | |
7079 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7080 | VBRSRQ_M_N_F)) | |
7081 | ] | |
7082 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7083 | "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" | |
7084 | [(set_attr "type" "mve_move") | |
7085 | (set_attr "length""8")]) | |
7086 | ||
7087 | ;; | |
7088 | ;; [vcaddq_rot270_m_f]) | |
7089 | ;; | |
7090 | (define_insn "mve_vcaddq_rot270_m_f<mode>" | |
7091 | [ | |
6debbff6 | 7092 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7093 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7094 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7095 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7096 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7097 | VCADDQ_ROT270_M_F)) | |
7098 | ] | |
7099 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7100 | "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
7101 | [(set_attr "type" "mve_move") | |
7102 | (set_attr "length""8")]) | |
7103 | ||
7104 | ;; | |
7105 | ;; [vcaddq_rot90_m_f]) | |
7106 | ;; | |
7107 | (define_insn "mve_vcaddq_rot90_m_f<mode>" | |
7108 | [ | |
6debbff6 | 7109 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7110 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7111 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7112 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7113 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7114 | VCADDQ_ROT90_M_F)) | |
7115 | ] | |
7116 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7117 | "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
7118 | [(set_attr "type" "mve_move") | |
7119 | (set_attr "length""8")]) | |
7120 | ||
7121 | ;; | |
7122 | ;; [vcmlaq_m_f]) | |
7123 | ;; | |
7124 | (define_insn "mve_vcmlaq_m_f<mode>" | |
7125 | [ | |
7126 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7127 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7128 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7129 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7130 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7131 | VCMLAQ_M_F)) | |
7132 | ] | |
7133 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7134 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0" | |
7135 | [(set_attr "type" "mve_move") | |
7136 | (set_attr "length""8")]) | |
7137 | ||
7138 | ;; | |
7139 | ;; [vcmlaq_rot180_m_f]) | |
7140 | ;; | |
7141 | (define_insn "mve_vcmlaq_rot180_m_f<mode>" | |
7142 | [ | |
7143 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7144 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7145 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7146 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7147 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7148 | VCMLAQ_ROT180_M_F)) | |
7149 | ] | |
7150 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7151 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180" | |
7152 | [(set_attr "type" "mve_move") | |
7153 | (set_attr "length""8")]) | |
7154 | ||
7155 | ;; | |
7156 | ;; [vcmlaq_rot270_m_f]) | |
7157 | ;; | |
7158 | (define_insn "mve_vcmlaq_rot270_m_f<mode>" | |
7159 | [ | |
7160 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7161 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7162 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7163 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7164 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7165 | VCMLAQ_ROT270_M_F)) | |
7166 | ] | |
7167 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7168 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
7169 | [(set_attr "type" "mve_move") | |
7170 | (set_attr "length""8")]) | |
7171 | ||
7172 | ;; | |
7173 | ;; [vcmlaq_rot90_m_f]) | |
7174 | ;; | |
7175 | (define_insn "mve_vcmlaq_rot90_m_f<mode>" | |
7176 | [ | |
7177 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7178 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7179 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7180 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7181 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7182 | VCMLAQ_ROT90_M_F)) | |
7183 | ] | |
7184 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7185 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
7186 | [(set_attr "type" "mve_move") | |
7187 | (set_attr "length""8")]) | |
7188 | ||
7189 | ;; | |
7190 | ;; [vcmulq_m_f]) | |
7191 | ;; | |
7192 | (define_insn "mve_vcmulq_m_f<mode>" | |
7193 | [ | |
6debbff6 | 7194 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7195 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7196 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7197 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7198 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7199 | VCMULQ_M_F)) | |
7200 | ] | |
7201 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7202 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0" | |
7203 | [(set_attr "type" "mve_move") | |
7204 | (set_attr "length""8")]) | |
7205 | ||
7206 | ;; | |
7207 | ;; [vcmulq_rot180_m_f]) | |
7208 | ;; | |
7209 | (define_insn "mve_vcmulq_rot180_m_f<mode>" | |
7210 | [ | |
6debbff6 | 7211 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7212 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7213 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7214 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7215 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7216 | VCMULQ_ROT180_M_F)) | |
7217 | ] | |
7218 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7219 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180" | |
7220 | [(set_attr "type" "mve_move") | |
7221 | (set_attr "length""8")]) | |
7222 | ||
7223 | ;; | |
7224 | ;; [vcmulq_rot270_m_f]) | |
7225 | ;; | |
7226 | (define_insn "mve_vcmulq_rot270_m_f<mode>" | |
7227 | [ | |
6debbff6 | 7228 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7229 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7230 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7231 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7232 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7233 | VCMULQ_ROT270_M_F)) | |
7234 | ] | |
7235 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7236 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
7237 | [(set_attr "type" "mve_move") | |
7238 | (set_attr "length""8")]) | |
7239 | ||
7240 | ;; | |
7241 | ;; [vcmulq_rot90_m_f]) | |
7242 | ;; | |
7243 | (define_insn "mve_vcmulq_rot90_m_f<mode>" | |
7244 | [ | |
6debbff6 | 7245 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
7246 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
7247 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7248 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7249 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7250 | VCMULQ_ROT90_M_F)) | |
7251 | ] | |
7252 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7253 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
7254 | [(set_attr "type" "mve_move") | |
7255 | (set_attr "length""8")]) | |
7256 | ||
7257 | ;; | |
7258 | ;; [veorq_m_f]) | |
7259 | ;; | |
7260 | (define_insn "mve_veorq_m_f<mode>" | |
7261 | [ | |
7262 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7263 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7264 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7265 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7266 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7267 | VEORQ_M_F)) | |
7268 | ] | |
7269 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7270 | "vpst\;veort %q0, %q2, %q3" | |
7271 | [(set_attr "type" "mve_move") | |
7272 | (set_attr "length""8")]) | |
7273 | ||
7274 | ;; | |
7275 | ;; [vfmaq_m_f]) | |
7276 | ;; | |
7277 | (define_insn "mve_vfmaq_m_f<mode>" | |
7278 | [ | |
7279 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7280 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7281 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7282 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7283 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7284 | VFMAQ_M_F)) | |
7285 | ] | |
7286 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7287 | "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3" | |
7288 | [(set_attr "type" "mve_move") | |
7289 | (set_attr "length""8")]) | |
7290 | ||
7291 | ;; | |
7292 | ;; [vfmaq_m_n_f]) | |
7293 | ;; | |
7294 | (define_insn "mve_vfmaq_m_n_f<mode>" | |
7295 | [ | |
7296 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7297 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7298 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7299 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
7300 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7301 | VFMAQ_M_N_F)) | |
7302 | ] | |
7303 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7304 | "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3" | |
7305 | [(set_attr "type" "mve_move") | |
7306 | (set_attr "length""8")]) | |
7307 | ||
7308 | ;; | |
7309 | ;; [vfmasq_m_n_f]) | |
7310 | ;; | |
7311 | (define_insn "mve_vfmasq_m_n_f<mode>" | |
7312 | [ | |
7313 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7314 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7315 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7316 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
7317 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7318 | VFMASQ_M_N_F)) | |
7319 | ] | |
7320 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7321 | "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3" | |
7322 | [(set_attr "type" "mve_move") | |
7323 | (set_attr "length""8")]) | |
7324 | ||
7325 | ;; | |
7326 | ;; [vfmsq_m_f]) | |
7327 | ;; | |
7328 | (define_insn "mve_vfmsq_m_f<mode>" | |
7329 | [ | |
7330 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7331 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7332 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7333 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7334 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7335 | VFMSQ_M_F)) | |
7336 | ] | |
7337 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7338 | "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3" | |
7339 | [(set_attr "type" "mve_move") | |
7340 | (set_attr "length""8")]) | |
7341 | ||
7342 | ;; | |
7343 | ;; [vmaxnmq_m_f]) | |
7344 | ;; | |
7345 | (define_insn "mve_vmaxnmq_m_f<mode>" | |
7346 | [ | |
7347 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7348 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7349 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7350 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7351 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7352 | VMAXNMQ_M_F)) | |
7353 | ] | |
7354 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7355 | "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3" | |
7356 | [(set_attr "type" "mve_move") | |
7357 | (set_attr "length""8")]) | |
7358 | ||
7359 | ;; | |
7360 | ;; [vminnmq_m_f]) | |
7361 | ;; | |
7362 | (define_insn "mve_vminnmq_m_f<mode>" | |
7363 | [ | |
7364 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7365 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7366 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7367 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7368 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7369 | VMINNMQ_M_F)) | |
7370 | ] | |
7371 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7372 | "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3" | |
7373 | [(set_attr "type" "mve_move") | |
7374 | (set_attr "length""8")]) | |
7375 | ||
7376 | ;; | |
7377 | ;; [vmulq_m_f]) | |
7378 | ;; | |
7379 | (define_insn "mve_vmulq_m_f<mode>" | |
7380 | [ | |
7381 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7382 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7383 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7384 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7385 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7386 | VMULQ_M_F)) | |
7387 | ] | |
7388 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7389 | "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3" | |
7390 | [(set_attr "type" "mve_move") | |
7391 | (set_attr "length""8")]) | |
7392 | ||
7393 | ;; | |
7394 | ;; [vmulq_m_n_f]) | |
7395 | ;; | |
7396 | (define_insn "mve_vmulq_m_n_f<mode>" | |
7397 | [ | |
7398 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7399 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7400 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7401 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
7402 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7403 | VMULQ_M_N_F)) | |
7404 | ] | |
7405 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7406 | "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3" | |
7407 | [(set_attr "type" "mve_move") | |
7408 | (set_attr "length""8")]) | |
7409 | ||
7410 | ;; | |
7411 | ;; [vornq_m_f]) | |
7412 | ;; | |
7413 | (define_insn "mve_vornq_m_f<mode>" | |
7414 | [ | |
7415 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7416 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7417 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7418 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7419 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7420 | VORNQ_M_F)) | |
7421 | ] | |
7422 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7423 | "vpst\;vornt %q0, %q2, %q3" | |
7424 | [(set_attr "type" "mve_move") | |
7425 | (set_attr "length""8")]) | |
7426 | ||
7427 | ;; | |
7428 | ;; [vorrq_m_f]) | |
7429 | ;; | |
7430 | (define_insn "mve_vorrq_m_f<mode>" | |
7431 | [ | |
7432 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7433 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7434 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7435 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7436 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7437 | VORRQ_M_F)) | |
7438 | ] | |
7439 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7440 | "vpst\;vorrt %q0, %q2, %q3" | |
7441 | [(set_attr "type" "mve_move") | |
7442 | (set_attr "length""8")]) | |
7443 | ||
7444 | ;; | |
7445 | ;; [vsubq_m_f]) | |
7446 | ;; | |
7447 | (define_insn "mve_vsubq_m_f<mode>" | |
7448 | [ | |
7449 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7450 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7451 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7452 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
7453 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7454 | VSUBQ_M_F)) | |
7455 | ] | |
7456 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7457 | "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3" | |
7458 | [(set_attr "type" "mve_move") | |
7459 | (set_attr "length""8")]) | |
7460 | ||
7461 | ;; | |
7462 | ;; [vsubq_m_n_f]) | |
7463 | ;; | |
7464 | (define_insn "mve_vsubq_m_n_f<mode>" | |
7465 | [ | |
7466 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7467 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
7468 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
7469 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
7470 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
7471 | VSUBQ_M_N_F)) | |
7472 | ] | |
7473 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7474 | "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3" | |
7475 | [(set_attr "type" "mve_move") | |
7476 | (set_attr "length""8")]) | |
4ff68575 SP |
7477 | |
7478 | ;; | |
7479 | ;; [vstrbq_s vstrbq_u] | |
7480 | ;; | |
7481 | (define_insn "mve_vstrbq_<supf><mode>" | |
d91524d5 | 7482 | [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") |
4ff68575 SP |
7483 | (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")] |
7484 | VSTRBQ)) | |
7485 | ] | |
7486 | "TARGET_HAVE_MVE" | |
7487 | { | |
7488 | rtx ops[2]; | |
7489 | int regno = REGNO (operands[1]); | |
7490 | ops[1] = gen_rtx_REG (TImode, regno); | |
7491 | ops[0] = operands[0]; | |
7492 | output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops); | |
7493 | return ""; | |
7494 | } | |
7495 | [(set_attr "length" "4")]) | |
7496 | ||
7497 | ;; | |
7498 | ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] | |
7499 | ;; | |
9a810e57 SP |
7500 | (define_expand "mve_vstrbq_scatter_offset_<supf><mode>" |
7501 | [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") | |
7502 | (match_operand:MVE_2 1 "s_register_operand") | |
7503 | (match_operand:MVE_2 2 "s_register_operand") | |
7504 | (unspec:V4SI [(const_int 0)] VSTRBSOQ)] | |
4ff68575 SP |
7505 | "TARGET_HAVE_MVE" |
7506 | { | |
9a810e57 SP |
7507 | rtx ind = XEXP (operands[0], 0); |
7508 | gcc_assert (REG_P (ind)); | |
7509 | emit_insn (gen_mve_vstrbq_scatter_offset_<supf><mode>_insn (ind, operands[1], | |
7510 | operands[2])); | |
7511 | DONE; | |
7512 | }) | |
7513 | ||
7514 | (define_insn "mve_vstrbq_scatter_offset_<supf><mode>_insn" | |
7515 | [(set (mem:BLK (scratch)) | |
7516 | (unspec:BLK | |
7517 | [(match_operand:SI 0 "register_operand" "r") | |
7518 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
7519 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
7520 | VSTRBSOQ))] | |
7521 | "TARGET_HAVE_MVE" | |
7522 | "vstrb.<V_sz_elem>\t%q2, [%0, %q1]" | |
4ff68575 SP |
7523 | [(set_attr "length" "4")]) |
7524 | ||
7525 | ;; | |
7526 | ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] | |
7527 | ;; | |
7528 | (define_insn "mve_vstrwq_scatter_base_<supf>v4si" | |
7529 | [(set (mem:BLK (scratch)) | |
7530 | (unspec:BLK | |
7531 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
7532 | (match_operand:SI 1 "immediate_operand" "i") | |
7533 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
7534 | VSTRWSBQ)) | |
7535 | ] | |
7536 | "TARGET_HAVE_MVE" | |
7537 | { | |
7538 | rtx ops[3]; | |
7539 | ops[0] = operands[0]; | |
7540 | ops[1] = operands[1]; | |
7541 | ops[2] = operands[2]; | |
7542 | output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); | |
7543 | return ""; | |
7544 | } | |
7545 | [(set_attr "length" "4")]) | |
535a8645 SP |
7546 | |
7547 | ;; | |
7548 | ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] | |
7549 | ;; | |
7550 | (define_insn "mve_vldrbq_gather_offset_<supf><mode>" | |
7551 | [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") | |
7552 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") | |
7553 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
7554 | VLDRBGOQ)) | |
7555 | ] | |
7556 | "TARGET_HAVE_MVE" | |
7557 | { | |
7558 | rtx ops[3]; | |
7559 | ops[0] = operands[0]; | |
7560 | ops[1] = operands[1]; | |
7561 | ops[2] = operands[2]; | |
7562 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) | |
7563 | output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops); | |
7564 | else | |
7565 | output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
7566 | return ""; | |
7567 | } | |
7568 | [(set_attr "length" "4")]) | |
7569 | ||
7570 | ;; | |
7571 | ;; [vldrbq_s vldrbq_u] | |
7572 | ;; | |
7573 | (define_insn "mve_vldrbq_<supf><mode>" | |
7574 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
d91524d5 | 7575 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")] |
535a8645 SP |
7576 | VLDRBQ)) |
7577 | ] | |
7578 | "TARGET_HAVE_MVE" | |
7579 | { | |
7580 | rtx ops[2]; | |
7581 | int regno = REGNO (operands[0]); | |
7582 | ops[0] = gen_rtx_REG (TImode, regno); | |
7583 | ops[1] = operands[1]; | |
d91524d5 SP |
7584 | if (<V_sz_elem> == 8) |
7585 | output_asm_insn ("vldrb.<V_sz_elem>\t%q0, %E1",ops); | |
7586 | else | |
7587 | output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops); | |
535a8645 SP |
7588 | return ""; |
7589 | } | |
7590 | [(set_attr "length" "4")]) | |
7591 | ||
7592 | ;; | |
7593 | ;; [vldrwq_gather_base_s vldrwq_gather_base_u] | |
7594 | ;; | |
7595 | (define_insn "mve_vldrwq_gather_base_<supf>v4si" | |
7596 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
7597 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
7598 | (match_operand:SI 2 "immediate_operand" "i")] | |
7599 | VLDRWGBQ)) | |
7600 | ] | |
7601 | "TARGET_HAVE_MVE" | |
7602 | { | |
7603 | rtx ops[3]; | |
7604 | ops[0] = operands[0]; | |
7605 | ops[1] = operands[1]; | |
7606 | ops[2] = operands[2]; | |
7607 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); | |
7608 | return ""; | |
7609 | } | |
7610 | [(set_attr "length" "4")]) | |
405e918c SP |
7611 | |
7612 | ;; | |
7613 | ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u] | |
7614 | ;; | |
9a810e57 SP |
7615 | (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>" |
7616 | [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") | |
7617 | (match_operand:MVE_2 1 "s_register_operand") | |
7618 | (match_operand:MVE_2 2 "s_register_operand") | |
7619 | (match_operand:HI 3 "vpr_register_operand" "Up") | |
7620 | (unspec:V4SI [(const_int 0)] VSTRBSOQ)] | |
405e918c SP |
7621 | "TARGET_HAVE_MVE" |
7622 | { | |
9a810e57 SP |
7623 | rtx ind = XEXP (operands[0], 0); |
7624 | gcc_assert (REG_P (ind)); | |
7625 | emit_insn ( | |
7626 | gen_mve_vstrbq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], | |
7627 | operands[2], | |
7628 | operands[3])); | |
7629 | DONE; | |
7630 | }) | |
7631 | ||
7632 | (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn" | |
7633 | [(set (mem:BLK (scratch)) | |
7634 | (unspec:BLK | |
7635 | [(match_operand:SI 0 "register_operand" "r") | |
7636 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
7637 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
7638 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
7639 | VSTRBSOQ))] | |
7640 | "TARGET_HAVE_MVE" | |
7641 | "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]" | |
405e918c SP |
7642 | [(set_attr "length" "8")]) |
7643 | ||
7644 | ;; | |
7645 | ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u] | |
7646 | ;; | |
7647 | (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" | |
7648 | [(set (mem:BLK (scratch)) | |
7649 | (unspec:BLK | |
7650 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
7651 | (match_operand:SI 1 "immediate_operand" "i") | |
7652 | (match_operand:V4SI 2 "s_register_operand" "w") | |
7653 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
7654 | VSTRWSBQ)) | |
7655 | ] | |
7656 | "TARGET_HAVE_MVE" | |
7657 | { | |
7658 | rtx ops[3]; | |
7659 | ops[0] = operands[0]; | |
7660 | ops[1] = operands[1]; | |
7661 | ops[2] = operands[2]; | |
7662 | output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); | |
7663 | return ""; | |
7664 | } | |
7665 | [(set_attr "length" "8")]) | |
7666 | ||
7667 | ;; | |
7668 | ;; [vstrbq_p_s vstrbq_p_u] | |
7669 | ;; | |
7670 | (define_insn "mve_vstrbq_p_<supf><mode>" | |
d91524d5 | 7671 | [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") |
405e918c SP |
7672 | (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w") |
7673 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
7674 | VSTRBQ)) | |
7675 | ] | |
7676 | "TARGET_HAVE_MVE" | |
7677 | { | |
7678 | rtx ops[2]; | |
7679 | int regno = REGNO (operands[1]); | |
7680 | ops[1] = gen_rtx_REG (TImode, regno); | |
7681 | ops[0] = operands[0]; | |
d91524d5 | 7682 | output_asm_insn ("vpst\;vstrbt.<V_sz_elem>\t%q1, %E0",ops); |
405e918c SP |
7683 | return ""; |
7684 | } | |
7685 | [(set_attr "length" "8")]) | |
429d607b SP |
7686 | |
7687 | ;; | |
7688 | ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] | |
7689 | ;; | |
7690 | (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" | |
7691 | [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") | |
7692 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") | |
7693 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
7694 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
7695 | VLDRBGOQ)) | |
7696 | ] | |
7697 | "TARGET_HAVE_MVE" | |
7698 | { | |
7699 | rtx ops[4]; | |
7700 | ops[0] = operands[0]; | |
7701 | ops[1] = operands[1]; | |
7702 | ops[2] = operands[2]; | |
7703 | ops[3] = operands[3]; | |
7704 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) | |
7705 | output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops); | |
7706 | else | |
7707 | output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
7708 | return ""; | |
7709 | } | |
7710 | [(set_attr "length" "8")]) | |
7711 | ||
7712 | ;; | |
7713 | ;; [vldrbq_z_s vldrbq_z_u] | |
7714 | ;; | |
7715 | (define_insn "mve_vldrbq_z_<supf><mode>" | |
7716 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
d91524d5 | 7717 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux") |
429d607b SP |
7718 | (match_operand:HI 2 "vpr_register_operand" "Up")] |
7719 | VLDRBQ)) | |
7720 | ] | |
7721 | "TARGET_HAVE_MVE" | |
7722 | { | |
7723 | rtx ops[2]; | |
7724 | int regno = REGNO (operands[0]); | |
7725 | ops[0] = gen_rtx_REG (TImode, regno); | |
7726 | ops[1] = operands[1]; | |
d91524d5 SP |
7727 | if (<V_sz_elem> == 8) |
7728 | output_asm_insn ("vpst\;vldrbt.<V_sz_elem>\t%q0, %E1",ops); | |
7729 | else | |
7730 | output_asm_insn ("vpst\;vldrbt.<supf><V_sz_elem>\t%q0, %E1",ops); | |
429d607b SP |
7731 | return ""; |
7732 | } | |
7733 | [(set_attr "length" "8")]) | |
7734 | ||
7735 | ;; | |
7736 | ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] | |
7737 | ;; | |
7738 | (define_insn "mve_vldrwq_gather_base_z_<supf>v4si" | |
7739 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
7740 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
7741 | (match_operand:SI 2 "immediate_operand" "i") | |
7742 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
7743 | VLDRWGBQ)) | |
7744 | ] | |
7745 | "TARGET_HAVE_MVE" | |
7746 | { | |
7747 | rtx ops[3]; | |
7748 | ops[0] = operands[0]; | |
7749 | ops[1] = operands[1]; | |
7750 | ops[2] = operands[2]; | |
7751 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); | |
7752 | return ""; | |
7753 | } | |
7754 | [(set_attr "length" "8")]) | |
bf1e3d5a SP |
7755 | |
7756 | ;; | |
7757 | ;; [vldrhq_f] | |
7758 | ;; | |
7759 | (define_insn "mve_vldrhq_fv8hf" | |
7760 | [(set (match_operand:V8HF 0 "s_register_operand" "=w") | |
d91524d5 | 7761 | (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
7762 | VLDRHQ_F)) |
7763 | ] | |
7764 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7765 | { | |
7766 | rtx ops[2]; | |
7767 | int regno = REGNO (operands[0]); | |
7768 | ops[0] = gen_rtx_REG (TImode, regno); | |
7769 | ops[1] = operands[1]; | |
d91524d5 | 7770 | output_asm_insn ("vldrh.16\t%q0, %E1",ops); |
bf1e3d5a SP |
7771 | return ""; |
7772 | } | |
7773 | [(set_attr "length" "4")]) | |
7774 | ||
7775 | ;; | |
7776 | ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] | |
7777 | ;; | |
7778 | (define_insn "mve_vldrhq_gather_offset_<supf><mode>" | |
7779 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
7780 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
7781 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
7782 | VLDRHGOQ)) | |
7783 | ] | |
7784 | "TARGET_HAVE_MVE" | |
7785 | { | |
7786 | rtx ops[3]; | |
7787 | ops[0] = operands[0]; | |
7788 | ops[1] = operands[1]; | |
7789 | ops[2] = operands[2]; | |
7790 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
7791 | output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops); | |
7792 | else | |
7793 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
7794 | return ""; | |
7795 | } | |
7796 | [(set_attr "length" "4")]) | |
7797 | ||
7798 | ;; | |
7799 | ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] | |
7800 | ;; | |
7801 | (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>" | |
7802 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
7803 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
7804 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
7805 | (match_operand:HI 3 "vpr_register_operand" "Up") | |
7806 | ]VLDRHGOQ)) | |
7807 | ] | |
7808 | "TARGET_HAVE_MVE" | |
7809 | { | |
7810 | rtx ops[4]; | |
7811 | ops[0] = operands[0]; | |
7812 | ops[1] = operands[1]; | |
7813 | ops[2] = operands[2]; | |
7814 | ops[3] = operands[3]; | |
7815 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
7816 | output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops); | |
7817 | else | |
7818 | output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
7819 | return ""; | |
7820 | } | |
7821 | [(set_attr "length" "8")]) | |
7822 | ||
7823 | ;; | |
7824 | ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] | |
7825 | ;; | |
7826 | (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>" | |
7827 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
7828 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
7829 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
7830 | VLDRHGSOQ)) | |
7831 | ] | |
7832 | "TARGET_HAVE_MVE" | |
7833 | { | |
7834 | rtx ops[3]; | |
7835 | ops[0] = operands[0]; | |
7836 | ops[1] = operands[1]; | |
7837 | ops[2] = operands[2]; | |
7838 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
7839 | output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
7840 | else | |
7841 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); | |
7842 | return ""; | |
7843 | } | |
7844 | [(set_attr "length" "4")]) | |
7845 | ||
7846 | ;; | |
7847 | ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] | |
7848 | ;; | |
7849 | (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>" | |
7850 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
7851 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
7852 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
7853 | (match_operand:HI 3 "vpr_register_operand" "Up") | |
7854 | ]VLDRHGSOQ)) | |
7855 | ] | |
7856 | "TARGET_HAVE_MVE" | |
7857 | { | |
7858 | rtx ops[4]; | |
7859 | ops[0] = operands[0]; | |
7860 | ops[1] = operands[1]; | |
7861 | ops[2] = operands[2]; | |
7862 | ops[3] = operands[3]; | |
7863 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
7864 | output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
7865 | else | |
7866 | output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); | |
7867 | return ""; | |
7868 | } | |
7869 | [(set_attr "length" "8")]) | |
7870 | ||
bf1e3d5a SP |
7871 | ;; |
7872 | ;; [vldrhq_s, vldrhq_u] | |
7873 | ;; | |
7874 | (define_insn "mve_vldrhq_<supf><mode>" | |
7875 | [(set (match_operand:MVE_6 0 "s_register_operand" "=w") | |
d91524d5 | 7876 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
7877 | VLDRHQ)) |
7878 | ] | |
7879 | "TARGET_HAVE_MVE" | |
7880 | { | |
7881 | rtx ops[2]; | |
7882 | int regno = REGNO (operands[0]); | |
7883 | ops[0] = gen_rtx_REG (TImode, regno); | |
7884 | ops[1] = operands[1]; | |
d91524d5 SP |
7885 | if (<V_sz_elem> == 16) |
7886 | output_asm_insn ("vldrh.16\t%q0, %E1",ops); | |
7887 | else | |
7888 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops); | |
bf1e3d5a SP |
7889 | return ""; |
7890 | } | |
7891 | [(set_attr "length" "4")]) | |
7892 | ||
7893 | ;; | |
7894 | ;; [vldrhq_z_f] | |
7895 | ;; | |
7896 | (define_insn "mve_vldrhq_z_fv8hf" | |
7897 | [(set (match_operand:V8HF 0 "s_register_operand" "=w") | |
d91524d5 | 7898 | (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux") |
bf1e3d5a SP |
7899 | (match_operand:HI 2 "vpr_register_operand" "Up")] |
7900 | VLDRHQ_F)) | |
7901 | ] | |
7902 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7903 | { | |
7904 | rtx ops[2]; | |
7905 | int regno = REGNO (operands[0]); | |
7906 | ops[0] = gen_rtx_REG (TImode, regno); | |
7907 | ops[1] = operands[1]; | |
d91524d5 | 7908 | output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); |
bf1e3d5a SP |
7909 | return ""; |
7910 | } | |
7911 | [(set_attr "length" "8")]) | |
7912 | ||
7913 | ;; | |
7914 | ;; [vldrhq_z_s vldrhq_z_u] | |
7915 | ;; | |
7916 | (define_insn "mve_vldrhq_z_<supf><mode>" | |
7917 | [(set (match_operand:MVE_6 0 "s_register_operand" "=w") | |
d91524d5 | 7918 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux") |
bf1e3d5a SP |
7919 | (match_operand:HI 2 "vpr_register_operand" "Up")] |
7920 | VLDRHQ)) | |
7921 | ] | |
7922 | "TARGET_HAVE_MVE" | |
7923 | { | |
7924 | rtx ops[2]; | |
7925 | int regno = REGNO (operands[0]); | |
7926 | ops[0] = gen_rtx_REG (TImode, regno); | |
7927 | ops[1] = operands[1]; | |
d91524d5 SP |
7928 | if (<V_sz_elem> == 16) |
7929 | output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); | |
7930 | else | |
7931 | output_asm_insn ("vpst\;vldrht.<supf><V_sz_elem>\t%q0, %E1",ops); | |
bf1e3d5a SP |
7932 | return ""; |
7933 | } | |
7934 | [(set_attr "length" "8")]) | |
7935 | ||
7936 | ;; | |
7937 | ;; [vldrwq_f] | |
7938 | ;; | |
7939 | (define_insn "mve_vldrwq_fv4sf" | |
7940 | [(set (match_operand:V4SF 0 "s_register_operand" "=w") | |
d91524d5 | 7941 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")] |
bf1e3d5a SP |
7942 | VLDRWQ_F)) |
7943 | ] | |
7944 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7945 | { | |
7946 | rtx ops[2]; | |
7947 | int regno = REGNO (operands[0]); | |
7948 | ops[0] = gen_rtx_REG (TImode, regno); | |
7949 | ops[1] = operands[1]; | |
d91524d5 | 7950 | output_asm_insn ("vldrw.32\t%q0, %E1",ops); |
bf1e3d5a SP |
7951 | return ""; |
7952 | } | |
7953 | [(set_attr "length" "4")]) | |
7954 | ||
7955 | ;; | |
7956 | ;; [vldrwq_s vldrwq_u] | |
7957 | ;; | |
7958 | (define_insn "mve_vldrwq_<supf>v4si" | |
7959 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
d91524d5 | 7960 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")] |
bf1e3d5a SP |
7961 | VLDRWQ)) |
7962 | ] | |
7963 | "TARGET_HAVE_MVE" | |
7964 | { | |
7965 | rtx ops[2]; | |
7966 | int regno = REGNO (operands[0]); | |
7967 | ops[0] = gen_rtx_REG (TImode, regno); | |
7968 | ops[1] = operands[1]; | |
d91524d5 | 7969 | output_asm_insn ("vldrw.32\t%q0, %E1",ops); |
bf1e3d5a SP |
7970 | return ""; |
7971 | } | |
7972 | [(set_attr "length" "4")]) | |
7973 | ||
7974 | ;; | |
7975 | ;; [vldrwq_z_f] | |
7976 | ;; | |
7977 | (define_insn "mve_vldrwq_z_fv4sf" | |
7978 | [(set (match_operand:V4SF 0 "s_register_operand" "=w") | |
d91524d5 | 7979 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux") |
bf1e3d5a SP |
7980 | (match_operand:HI 2 "vpr_register_operand" "Up")] |
7981 | VLDRWQ_F)) | |
7982 | ] | |
7983 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7984 | { | |
7985 | rtx ops[2]; | |
7986 | int regno = REGNO (operands[0]); | |
7987 | ops[0] = gen_rtx_REG (TImode, regno); | |
7988 | ops[1] = operands[1]; | |
d91524d5 | 7989 | output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); |
bf1e3d5a SP |
7990 | return ""; |
7991 | } | |
7992 | [(set_attr "length" "8")]) | |
7993 | ||
7994 | ;; | |
7995 | ;; [vldrwq_z_s vldrwq_z_u] | |
7996 | ;; | |
7997 | (define_insn "mve_vldrwq_z_<supf>v4si" | |
7998 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
d91524d5 | 7999 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux") |
bf1e3d5a SP |
8000 | (match_operand:HI 2 "vpr_register_operand" "Up")] |
8001 | VLDRWQ)) | |
8002 | ] | |
8003 | "TARGET_HAVE_MVE" | |
8004 | { | |
8005 | rtx ops[2]; | |
8006 | int regno = REGNO (operands[0]); | |
8007 | ops[0] = gen_rtx_REG (TImode, regno); | |
8008 | ops[1] = operands[1]; | |
d91524d5 | 8009 | output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); |
bf1e3d5a SP |
8010 | return ""; |
8011 | } | |
8012 | [(set_attr "length" "8")]) | |
8013 | ||
8014 | (define_expand "mve_vld1q_f<mode>" | |
8015 | [(match_operand:MVE_0 0 "s_register_operand") | |
d91524d5 | 8016 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "mve_memory_operand")] VLD1Q_F) |
bf1e3d5a SP |
8017 | ] |
8018 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
8019 | { | |
8020 | emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); | |
8021 | DONE; | |
8022 | }) | |
8023 | ||
8024 | (define_expand "mve_vld1q_<supf><mode>" | |
8025 | [(match_operand:MVE_2 0 "s_register_operand") | |
d91524d5 | 8026 | (unspec:MVE_2 [(match_operand:MVE_2 1 "mve_memory_operand")] VLD1Q) |
bf1e3d5a SP |
8027 | ] |
8028 | "TARGET_HAVE_MVE" | |
8029 | { | |
8030 | emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); | |
8031 | DONE; | |
8032 | }) | |
4cc23303 SP |
8033 | |
8034 | ;; | |
8035 | ;; [vldrdq_gather_base_s vldrdq_gather_base_u] | |
8036 | ;; | |
8037 | (define_insn "mve_vldrdq_gather_base_<supf>v2di" | |
8038 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8039 | (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") | |
8040 | (match_operand:SI 2 "immediate_operand" "i")] | |
8041 | VLDRDGBQ)) | |
8042 | ] | |
8043 | "TARGET_HAVE_MVE" | |
8044 | { | |
8045 | rtx ops[3]; | |
8046 | ops[0] = operands[0]; | |
8047 | ops[1] = operands[1]; | |
8048 | ops[2] = operands[2]; | |
8049 | output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops); | |
8050 | return ""; | |
8051 | } | |
8052 | [(set_attr "length" "4")]) | |
8053 | ||
8054 | ;; | |
8055 | ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u] | |
8056 | ;; | |
8057 | (define_insn "mve_vldrdq_gather_base_z_<supf>v2di" | |
8058 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8059 | (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") | |
8060 | (match_operand:SI 2 "immediate_operand" "i") | |
8061 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8062 | VLDRDGBQ)) | |
8063 | ] | |
8064 | "TARGET_HAVE_MVE" | |
8065 | { | |
8066 | rtx ops[3]; | |
8067 | ops[0] = operands[0]; | |
8068 | ops[1] = operands[1]; | |
8069 | ops[2] = operands[2]; | |
8070 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops); | |
8071 | return ""; | |
8072 | } | |
8073 | [(set_attr "length" "8")]) | |
8074 | ||
8075 | ;; | |
8076 | ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u] | |
8077 | ;; | |
8078 | (define_insn "mve_vldrdq_gather_offset_<supf>v2di" | |
8079 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8080 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
8081 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
8082 | VLDRDGOQ)) | |
8083 | ] | |
8084 | "TARGET_HAVE_MVE" | |
8085 | { | |
8086 | rtx ops[3]; | |
8087 | ops[0] = operands[0]; | |
8088 | ops[1] = operands[1]; | |
8089 | ops[2] = operands[2]; | |
8090 | output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops); | |
8091 | return ""; | |
8092 | } | |
8093 | [(set_attr "length" "4")]) | |
8094 | ||
8095 | ;; | |
8096 | ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u] | |
8097 | ;; | |
8098 | (define_insn "mve_vldrdq_gather_offset_z_<supf>v2di" | |
8099 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8100 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
8101 | (match_operand:V2DI 2 "s_register_operand" "w") | |
8102 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8103 | VLDRDGOQ)) | |
8104 | ] | |
8105 | "TARGET_HAVE_MVE" | |
8106 | { | |
8107 | rtx ops[3]; | |
8108 | ops[0] = operands[0]; | |
8109 | ops[1] = operands[1]; | |
8110 | ops[2] = operands[2]; | |
8111 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops); | |
8112 | return ""; | |
8113 | } | |
8114 | [(set_attr "length" "8")]) | |
8115 | ||
8116 | ;; | |
8117 | ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u] | |
8118 | ;; | |
8119 | (define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di" | |
8120 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8121 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
8122 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
8123 | VLDRDGSOQ)) | |
8124 | ] | |
8125 | "TARGET_HAVE_MVE" | |
8126 | { | |
8127 | rtx ops[3]; | |
8128 | ops[0] = operands[0]; | |
8129 | ops[1] = operands[1]; | |
8130 | ops[2] = operands[2]; | |
8131 | output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops); | |
8132 | return ""; | |
8133 | } | |
8134 | [(set_attr "length" "4")]) | |
8135 | ||
8136 | ;; | |
8137 | ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u] | |
8138 | ;; | |
8139 | (define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di" | |
8140 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
8141 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
8142 | (match_operand:V2DI 2 "s_register_operand" "w") | |
8143 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8144 | VLDRDGSOQ)) | |
8145 | ] | |
8146 | "TARGET_HAVE_MVE" | |
8147 | { | |
8148 | rtx ops[3]; | |
8149 | ops[0] = operands[0]; | |
8150 | ops[1] = operands[1]; | |
8151 | ops[2] = operands[2]; | |
8152 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops); | |
8153 | return ""; | |
8154 | } | |
8155 | [(set_attr "length" "8")]) | |
8156 | ||
8157 | ;; | |
8158 | ;; [vldrhq_gather_offset_f] | |
8159 | ;; | |
8160 | (define_insn "mve_vldrhq_gather_offset_fv8hf" | |
8161 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
8162 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
8163 | (match_operand:V8HI 2 "s_register_operand" "w")] | |
8164 | VLDRHQGO_F)) | |
8165 | ] | |
8166 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8167 | { | |
8168 | rtx ops[3]; | |
8169 | ops[0] = operands[0]; | |
8170 | ops[1] = operands[1]; | |
8171 | ops[2] = operands[2]; | |
8172 | output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops); | |
8173 | return ""; | |
8174 | } | |
8175 | [(set_attr "length" "4")]) | |
8176 | ||
8177 | ;; | |
8178 | ;; [vldrhq_gather_offset_z_f] | |
8179 | ;; | |
8180 | (define_insn "mve_vldrhq_gather_offset_z_fv8hf" | |
8181 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
8182 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
8183 | (match_operand:V8HI 2 "s_register_operand" "w") | |
8184 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8185 | VLDRHQGO_F)) | |
8186 | ] | |
8187 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8188 | { | |
8189 | rtx ops[4]; | |
8190 | ops[0] = operands[0]; | |
8191 | ops[1] = operands[1]; | |
8192 | ops[2] = operands[2]; | |
8193 | ops[3] = operands[3]; | |
8194 | output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops); | |
8195 | return ""; | |
8196 | } | |
8197 | [(set_attr "length" "8")]) | |
8198 | ||
8199 | ;; | |
8200 | ;; [vldrhq_gather_shifted_offset_f] | |
8201 | ;; | |
8202 | (define_insn "mve_vldrhq_gather_shifted_offset_fv8hf" | |
8203 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
8204 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
8205 | (match_operand:V8HI 2 "s_register_operand" "w")] | |
8206 | VLDRHQGSO_F)) | |
8207 | ] | |
8208 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8209 | { | |
8210 | rtx ops[3]; | |
8211 | ops[0] = operands[0]; | |
8212 | ops[1] = operands[1]; | |
8213 | ops[2] = operands[2]; | |
8214 | output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
8215 | return ""; | |
8216 | } | |
8217 | [(set_attr "length" "4")]) | |
8218 | ||
8219 | ;; | |
8220 | ;; [vldrhq_gather_shifted_offset_z_f] | |
8221 | ;; | |
8222 | (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" | |
8223 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
8224 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
8225 | (match_operand:V8HI 2 "s_register_operand" "w") | |
8226 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8227 | VLDRHQGSO_F)) | |
8228 | ] | |
8229 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8230 | { | |
8231 | rtx ops[4]; | |
8232 | ops[0] = operands[0]; | |
8233 | ops[1] = operands[1]; | |
8234 | ops[2] = operands[2]; | |
8235 | ops[3] = operands[3]; | |
8236 | output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
8237 | return ""; | |
8238 | } | |
8239 | [(set_attr "length" "8")]) | |
8240 | ||
8241 | ;; | |
8242 | ;; [vldrwq_gather_base_f] | |
8243 | ;; | |
8244 | (define_insn "mve_vldrwq_gather_base_fv4sf" | |
8245 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8246 | (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") | |
8247 | (match_operand:SI 2 "immediate_operand" "i")] | |
8248 | VLDRWQGB_F)) | |
8249 | ] | |
8250 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8251 | { | |
8252 | rtx ops[3]; | |
8253 | ops[0] = operands[0]; | |
8254 | ops[1] = operands[1]; | |
8255 | ops[2] = operands[2]; | |
8256 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); | |
8257 | return ""; | |
8258 | } | |
8259 | [(set_attr "length" "4")]) | |
8260 | ||
8261 | ;; | |
8262 | ;; [vldrwq_gather_base_z_f] | |
8263 | ;; | |
8264 | (define_insn "mve_vldrwq_gather_base_z_fv4sf" | |
8265 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8266 | (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") | |
8267 | (match_operand:SI 2 "immediate_operand" "i") | |
8268 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8269 | VLDRWQGB_F)) | |
8270 | ] | |
8271 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8272 | { | |
8273 | rtx ops[3]; | |
8274 | ops[0] = operands[0]; | |
8275 | ops[1] = operands[1]; | |
8276 | ops[2] = operands[2]; | |
8277 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); | |
8278 | return ""; | |
8279 | } | |
8280 | [(set_attr "length" "8")]) | |
8281 | ||
8282 | ;; | |
8283 | ;; [vldrwq_gather_offset_f] | |
8284 | ;; | |
8285 | (define_insn "mve_vldrwq_gather_offset_fv4sf" | |
8286 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8287 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
8288 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
8289 | VLDRWQGO_F)) | |
8290 | ] | |
8291 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8292 | { | |
8293 | rtx ops[3]; | |
8294 | ops[0] = operands[0]; | |
8295 | ops[1] = operands[1]; | |
8296 | ops[2] = operands[2]; | |
8297 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); | |
8298 | return ""; | |
8299 | } | |
8300 | [(set_attr "length" "4")]) | |
8301 | ||
8302 | ;; | |
8303 | ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u] | |
8304 | ;; | |
8305 | (define_insn "mve_vldrwq_gather_offset_<supf>v4si" | |
8306 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
8307 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
8308 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
8309 | VLDRWGOQ)) | |
8310 | ] | |
8311 | "TARGET_HAVE_MVE" | |
8312 | { | |
8313 | rtx ops[3]; | |
8314 | ops[0] = operands[0]; | |
8315 | ops[1] = operands[1]; | |
8316 | ops[2] = operands[2]; | |
8317 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); | |
8318 | return ""; | |
8319 | } | |
8320 | [(set_attr "length" "4")]) | |
8321 | ||
8322 | ;; | |
8323 | ;; [vldrwq_gather_offset_z_f] | |
8324 | ;; | |
8325 | (define_insn "mve_vldrwq_gather_offset_z_fv4sf" | |
8326 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8327 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
8328 | (match_operand:V4SI 2 "s_register_operand" "w") | |
8329 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8330 | VLDRWQGO_F)) | |
8331 | ] | |
8332 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8333 | { | |
8334 | rtx ops[4]; | |
8335 | ops[0] = operands[0]; | |
8336 | ops[1] = operands[1]; | |
8337 | ops[2] = operands[2]; | |
8338 | ops[3] = operands[3]; | |
8339 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); | |
8340 | return ""; | |
8341 | } | |
8342 | [(set_attr "length" "8")]) | |
8343 | ||
8344 | ;; | |
8345 | ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u] | |
8346 | ;; | |
8347 | (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" | |
8348 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
8349 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
8350 | (match_operand:V4SI 2 "s_register_operand" "w") | |
8351 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8352 | VLDRWGOQ)) | |
8353 | ] | |
8354 | "TARGET_HAVE_MVE" | |
8355 | { | |
8356 | rtx ops[4]; | |
8357 | ops[0] = operands[0]; | |
8358 | ops[1] = operands[1]; | |
8359 | ops[2] = operands[2]; | |
8360 | ops[3] = operands[3]; | |
8361 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); | |
8362 | return ""; | |
8363 | } | |
8364 | [(set_attr "length" "8")]) | |
8365 | ||
8366 | ;; | |
8367 | ;; [vldrwq_gather_shifted_offset_f] | |
8368 | ;; | |
8369 | (define_insn "mve_vldrwq_gather_shifted_offset_fv4sf" | |
8370 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8371 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
8372 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
8373 | VLDRWQGSO_F)) | |
8374 | ] | |
8375 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8376 | { | |
8377 | rtx ops[3]; | |
8378 | ops[0] = operands[0]; | |
8379 | ops[1] = operands[1]; | |
8380 | ops[2] = operands[2]; | |
8381 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
8382 | return ""; | |
8383 | } | |
8384 | [(set_attr "length" "4")]) | |
8385 | ||
8386 | ;; | |
8387 | ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u] | |
8388 | ;; | |
8389 | (define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si" | |
8390 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
8391 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
8392 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
8393 | VLDRWGSOQ)) | |
8394 | ] | |
8395 | "TARGET_HAVE_MVE" | |
8396 | { | |
8397 | rtx ops[3]; | |
8398 | ops[0] = operands[0]; | |
8399 | ops[1] = operands[1]; | |
8400 | ops[2] = operands[2]; | |
8401 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
8402 | return ""; | |
8403 | } | |
8404 | [(set_attr "length" "4")]) | |
8405 | ||
8406 | ;; | |
8407 | ;; [vldrwq_gather_shifted_offset_z_f] | |
8408 | ;; | |
8409 | (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" | |
8410 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
8411 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
8412 | (match_operand:V4SI 2 "s_register_operand" "w") | |
8413 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8414 | VLDRWQGSO_F)) | |
8415 | ] | |
8416 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8417 | { | |
8418 | rtx ops[4]; | |
8419 | ops[0] = operands[0]; | |
8420 | ops[1] = operands[1]; | |
8421 | ops[2] = operands[2]; | |
8422 | ops[3] = operands[3]; | |
8423 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
8424 | return ""; | |
8425 | } | |
8426 | [(set_attr "length" "8")]) | |
8427 | ||
8428 | ;; | |
8429 | ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u] | |
8430 | ;; | |
8431 | (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" | |
8432 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
8433 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
8434 | (match_operand:V4SI 2 "s_register_operand" "w") | |
8435 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8436 | VLDRWGSOQ)) | |
8437 | ] | |
8438 | "TARGET_HAVE_MVE" | |
8439 | { | |
8440 | rtx ops[4]; | |
8441 | ops[0] = operands[0]; | |
8442 | ops[1] = operands[1]; | |
8443 | ops[2] = operands[2]; | |
8444 | ops[3] = operands[3]; | |
8445 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
8446 | return ""; | |
8447 | } | |
8448 | [(set_attr "length" "8")]) | |
5cad47e0 SP |
8449 | |
8450 | ;; | |
8451 | ;; [vstrhq_f] | |
8452 | ;; | |
8453 | (define_insn "mve_vstrhq_fv8hf" | |
d91524d5 | 8454 | [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
8455 | (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")] |
8456 | VSTRHQ_F)) | |
8457 | ] | |
8458 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8459 | { | |
8460 | rtx ops[2]; | |
8461 | int regno = REGNO (operands[1]); | |
8462 | ops[1] = gen_rtx_REG (TImode, regno); | |
8463 | ops[0] = operands[0]; | |
8464 | output_asm_insn ("vstrh.16\t%q1, %E0",ops); | |
8465 | return ""; | |
8466 | } | |
8467 | [(set_attr "length" "4")]) | |
8468 | ||
8469 | ;; | |
8470 | ;; [vstrhq_p_f] | |
8471 | ;; | |
8472 | (define_insn "mve_vstrhq_p_fv8hf" | |
d91524d5 | 8473 | [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
8474 | (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") |
8475 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
8476 | VSTRHQ_F)) | |
8477 | ] | |
8478 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8479 | { | |
8480 | rtx ops[2]; | |
8481 | int regno = REGNO (operands[1]); | |
8482 | ops[1] = gen_rtx_REG (TImode, regno); | |
8483 | ops[0] = operands[0]; | |
d91524d5 | 8484 | output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops); |
5cad47e0 SP |
8485 | return ""; |
8486 | } | |
8487 | [(set_attr "length" "8")]) | |
8488 | ||
8489 | ;; | |
8490 | ;; [vstrhq_p_s vstrhq_p_u] | |
8491 | ;; | |
8492 | (define_insn "mve_vstrhq_p_<supf><mode>" | |
d91524d5 | 8493 | [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
8494 | (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w") |
8495 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
8496 | VSTRHQ)) | |
8497 | ] | |
8498 | "TARGET_HAVE_MVE" | |
8499 | { | |
8500 | rtx ops[2]; | |
8501 | int regno = REGNO (operands[1]); | |
8502 | ops[1] = gen_rtx_REG (TImode, regno); | |
8503 | ops[0] = operands[0]; | |
d91524d5 | 8504 | output_asm_insn ("vpst\;vstrht.<V_sz_elem>\t%q1, %E0",ops); |
5cad47e0 SP |
8505 | return ""; |
8506 | } | |
8507 | [(set_attr "length" "8")]) | |
8508 | ||
8509 | ;; | |
8510 | ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u] | |
8511 | ;; | |
9a810e57 SP |
8512 | (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>" |
8513 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
8514 | (match_operand:MVE_6 1 "s_register_operand") | |
8515 | (match_operand:MVE_6 2 "s_register_operand") | |
8516 | (match_operand:HI 3 "vpr_register_operand") | |
8517 | (unspec:V4SI [(const_int 0)] VSTRHSOQ)] | |
5cad47e0 SP |
8518 | "TARGET_HAVE_MVE" |
8519 | { | |
9a810e57 SP |
8520 | rtx ind = XEXP (operands[0], 0); |
8521 | gcc_assert (REG_P (ind)); | |
8522 | emit_insn ( | |
8523 | gen_mve_vstrhq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], | |
8524 | operands[2], | |
8525 | operands[3])); | |
8526 | DONE; | |
8527 | }) | |
8528 | ||
8529 | (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn" | |
8530 | [(set (mem:BLK (scratch)) | |
8531 | (unspec:BLK | |
8532 | [(match_operand:SI 0 "register_operand" "r") | |
8533 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
8534 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
8535 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8536 | VSTRHSOQ))] | |
8537 | "TARGET_HAVE_MVE" | |
8538 | "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]" | |
5cad47e0 SP |
8539 | [(set_attr "length" "8")]) |
8540 | ||
8541 | ;; | |
8542 | ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u] | |
8543 | ;; | |
9a810e57 SP |
8544 | (define_expand "mve_vstrhq_scatter_offset_<supf><mode>" |
8545 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
8546 | (match_operand:MVE_6 1 "s_register_operand") | |
8547 | (match_operand:MVE_6 2 "s_register_operand") | |
8548 | (unspec:V4SI [(const_int 0)] VSTRHSOQ)] | |
5cad47e0 SP |
8549 | "TARGET_HAVE_MVE" |
8550 | { | |
9a810e57 SP |
8551 | rtx ind = XEXP (operands[0], 0); |
8552 | gcc_assert (REG_P (ind)); | |
8553 | emit_insn (gen_mve_vstrhq_scatter_offset_<supf><mode>_insn (ind, operands[1], | |
8554 | operands[2])); | |
8555 | DONE; | |
8556 | }) | |
8557 | ||
8558 | (define_insn "mve_vstrhq_scatter_offset_<supf><mode>_insn" | |
8559 | [(set (mem:BLK (scratch)) | |
8560 | (unspec:BLK | |
8561 | [(match_operand:SI 0 "register_operand" "r") | |
8562 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
8563 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
8564 | VSTRHSOQ))] | |
8565 | "TARGET_HAVE_MVE" | |
8566 | "vstrh.<V_sz_elem>\t%q2, [%0, %q1]" | |
5cad47e0 SP |
8567 | [(set_attr "length" "4")]) |
8568 | ||
8569 | ;; | |
8570 | ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u] | |
8571 | ;; | |
9a810e57 SP |
8572 | (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>" |
8573 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
8574 | (match_operand:MVE_6 1 "s_register_operand") | |
8575 | (match_operand:MVE_6 2 "s_register_operand") | |
8576 | (match_operand:HI 3 "vpr_register_operand") | |
8577 | (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] | |
5cad47e0 SP |
8578 | "TARGET_HAVE_MVE" |
8579 | { | |
9a810e57 SP |
8580 | rtx ind = XEXP (operands[0], 0); |
8581 | gcc_assert (REG_P (ind)); | |
8582 | emit_insn ( | |
8583 | gen_mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn (ind, operands[1], | |
8584 | operands[2], | |
8585 | operands[3])); | |
8586 | DONE; | |
8587 | }) | |
8588 | ||
8589 | (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn" | |
8590 | [(set (mem:BLK (scratch)) | |
8591 | (unspec:BLK | |
8592 | [(match_operand:SI 0 "register_operand" "r") | |
8593 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
8594 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
8595 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8596 | VSTRHSSOQ))] | |
8597 | "TARGET_HAVE_MVE" | |
8598 | "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" | |
5cad47e0 SP |
8599 | [(set_attr "length" "8")]) |
8600 | ||
8601 | ;; | |
8602 | ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u] | |
8603 | ;; | |
9a810e57 SP |
8604 | (define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>" |
8605 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
8606 | (match_operand:MVE_6 1 "s_register_operand") | |
8607 | (match_operand:MVE_6 2 "s_register_operand") | |
8608 | (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] | |
5cad47e0 SP |
8609 | "TARGET_HAVE_MVE" |
8610 | { | |
9a810e57 SP |
8611 | rtx ind = XEXP (operands[0], 0); |
8612 | gcc_assert (REG_P (ind)); | |
8613 | emit_insn ( | |
8614 | gen_mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn (ind, operands[1], | |
8615 | operands[2])); | |
8616 | DONE; | |
8617 | }) | |
8618 | ||
8619 | (define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn" | |
8620 | [(set (mem:BLK (scratch)) | |
8621 | (unspec:BLK | |
8622 | [(match_operand:SI 0 "register_operand" "r") | |
8623 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
8624 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
8625 | VSTRHSSOQ))] | |
8626 | "TARGET_HAVE_MVE" | |
8627 | "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" | |
5cad47e0 SP |
8628 | [(set_attr "length" "4")]) |
8629 | ||
8630 | ;; | |
8631 | ;; [vstrhq_s, vstrhq_u] | |
8632 | ;; | |
8633 | (define_insn "mve_vstrhq_<supf><mode>" | |
d91524d5 | 8634 | [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
8635 | (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")] |
8636 | VSTRHQ)) | |
8637 | ] | |
8638 | "TARGET_HAVE_MVE" | |
8639 | { | |
8640 | rtx ops[2]; | |
8641 | int regno = REGNO (operands[1]); | |
8642 | ops[1] = gen_rtx_REG (TImode, regno); | |
8643 | ops[0] = operands[0]; | |
8644 | output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops); | |
8645 | return ""; | |
8646 | } | |
8647 | [(set_attr "length" "4")]) | |
8648 | ||
8649 | ;; | |
8650 | ;; [vstrwq_f] | |
8651 | ;; | |
8652 | (define_insn "mve_vstrwq_fv4sf" | |
d91524d5 | 8653 | [(set (match_operand:V4SI 0 "memory_operand" "=Ux") |
5cad47e0 SP |
8654 | (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")] |
8655 | VSTRWQ_F)) | |
8656 | ] | |
8657 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8658 | { | |
8659 | rtx ops[2]; | |
8660 | int regno = REGNO (operands[1]); | |
8661 | ops[1] = gen_rtx_REG (TImode, regno); | |
8662 | ops[0] = operands[0]; | |
8663 | output_asm_insn ("vstrw.32\t%q1, %E0",ops); | |
8664 | return ""; | |
8665 | } | |
8666 | [(set_attr "length" "4")]) | |
8667 | ||
8668 | ;; | |
8669 | ;; [vstrwq_p_f] | |
8670 | ;; | |
8671 | (define_insn "mve_vstrwq_p_fv4sf" | |
d91524d5 | 8672 | [(set (match_operand:V4SI 0 "memory_operand" "=Ux") |
5cad47e0 SP |
8673 | (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") |
8674 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
8675 | VSTRWQ_F)) | |
8676 | ] | |
8677 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8678 | { | |
8679 | rtx ops[2]; | |
8680 | int regno = REGNO (operands[1]); | |
8681 | ops[1] = gen_rtx_REG (TImode, regno); | |
8682 | ops[0] = operands[0]; | |
d91524d5 | 8683 | output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); |
5cad47e0 SP |
8684 | return ""; |
8685 | } | |
8686 | [(set_attr "length" "8")]) | |
8687 | ||
8688 | ;; | |
8689 | ;; [vstrwq_p_s vstrwq_p_u] | |
8690 | ;; | |
8691 | (define_insn "mve_vstrwq_p_<supf>v4si" | |
d91524d5 | 8692 | [(set (match_operand:V4SI 0 "memory_operand" "=Ux") |
5cad47e0 SP |
8693 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") |
8694 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
8695 | VSTRWQ)) | |
8696 | ] | |
8697 | "TARGET_HAVE_MVE" | |
8698 | { | |
8699 | rtx ops[2]; | |
8700 | int regno = REGNO (operands[1]); | |
8701 | ops[1] = gen_rtx_REG (TImode, regno); | |
8702 | ops[0] = operands[0]; | |
d91524d5 | 8703 | output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); |
5cad47e0 SP |
8704 | return ""; |
8705 | } | |
8706 | [(set_attr "length" "8")]) | |
8707 | ||
8708 | ;; | |
8709 | ;; [vstrwq_s vstrwq_u] | |
8710 | ;; | |
8711 | (define_insn "mve_vstrwq_<supf>v4si" | |
d91524d5 | 8712 | [(set (match_operand:V4SI 0 "memory_operand" "=Ux") |
5cad47e0 SP |
8713 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")] |
8714 | VSTRWQ)) | |
8715 | ] | |
8716 | "TARGET_HAVE_MVE" | |
8717 | { | |
8718 | rtx ops[2]; | |
8719 | int regno = REGNO (operands[1]); | |
8720 | ops[1] = gen_rtx_REG (TImode, regno); | |
8721 | ops[0] = operands[0]; | |
8722 | output_asm_insn ("vstrw.32\t%q1, %E0",ops); | |
8723 | return ""; | |
8724 | } | |
8725 | [(set_attr "length" "4")]) | |
8726 | ||
8727 | (define_expand "mve_vst1q_f<mode>" | |
91d206ad | 8728 | [(match_operand:<MVE_CNVT> 0 "mve_memory_operand") |
5cad47e0 SP |
8729 | (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F) |
8730 | ] | |
8731 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
8732 | { | |
8733 | emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); | |
8734 | DONE; | |
8735 | }) | |
8736 | ||
8737 | (define_expand "mve_vst1q_<supf><mode>" | |
91d206ad | 8738 | [(match_operand:MVE_2 0 "mve_memory_operand") |
5cad47e0 SP |
8739 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q) |
8740 | ] | |
8741 | "TARGET_HAVE_MVE" | |
8742 | { | |
8743 | emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); | |
8744 | DONE; | |
8745 | }) | |
7a5fffa5 SP |
8746 | |
8747 | ;; | |
8748 | ;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u] | |
8749 | ;; | |
8750 | (define_insn "mve_vstrdq_scatter_base_p_<supf>v2di" | |
8751 | [(set (mem:BLK (scratch)) | |
8752 | (unspec:BLK | |
8753 | [(match_operand:V2DI 0 "s_register_operand" "w") | |
8754 | (match_operand:SI 1 "mve_vldrd_immediate" "Ri") | |
8755 | (match_operand:V2DI 2 "s_register_operand" "w") | |
8756 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8757 | VSTRDSBQ)) | |
8758 | ] | |
8759 | "TARGET_HAVE_MVE" | |
8760 | { | |
8761 | rtx ops[3]; | |
8762 | ops[0] = operands[0]; | |
8763 | ops[1] = operands[1]; | |
8764 | ops[2] = operands[2]; | |
8765 | output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops); | |
8766 | return ""; | |
8767 | } | |
8768 | [(set_attr "length" "8")]) | |
8769 | ||
8770 | ;; | |
8771 | ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u] | |
8772 | ;; | |
8773 | (define_insn "mve_vstrdq_scatter_base_<supf>v2di" | |
8774 | [(set (mem:BLK (scratch)) | |
8775 | (unspec:BLK | |
8776 | [(match_operand:V2DI 0 "s_register_operand" "=w") | |
8777 | (match_operand:SI 1 "mve_vldrd_immediate" "Ri") | |
8778 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
8779 | VSTRDSBQ)) | |
8780 | ] | |
8781 | "TARGET_HAVE_MVE" | |
8782 | { | |
8783 | rtx ops[3]; | |
8784 | ops[0] = operands[0]; | |
8785 | ops[1] = operands[1]; | |
8786 | ops[2] = operands[2]; | |
8787 | output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops); | |
8788 | return ""; | |
8789 | } | |
8790 | [(set_attr "length" "4")]) | |
8791 | ||
8792 | ;; | |
8793 | ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u] | |
8794 | ;; | |
9a810e57 SP |
8795 | (define_expand "mve_vstrdq_scatter_offset_p_<supf>v2di" |
8796 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
8797 | (match_operand:V2DI 1 "s_register_operand") | |
8798 | (match_operand:V2DI 2 "s_register_operand") | |
8799 | (match_operand:HI 3 "vpr_register_operand") | |
8800 | (unspec:V4SI [(const_int 0)] VSTRDSOQ)] | |
7a5fffa5 SP |
8801 | "TARGET_HAVE_MVE" |
8802 | { | |
9a810e57 SP |
8803 | rtx ind = XEXP (operands[0], 0); |
8804 | gcc_assert (REG_P (ind)); | |
8805 | emit_insn (gen_mve_vstrdq_scatter_offset_p_<supf>v2di_insn (ind, operands[1], | |
8806 | operands[2], | |
8807 | operands[3])); | |
8808 | DONE; | |
8809 | }) | |
8810 | ||
8811 | (define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di_insn" | |
8812 | [(set (mem:BLK (scratch)) | |
8813 | (unspec:BLK | |
8814 | [(match_operand:SI 0 "register_operand" "r") | |
8815 | (match_operand:V2DI 1 "s_register_operand" "w") | |
8816 | (match_operand:V2DI 2 "s_register_operand" "w") | |
8817 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8818 | VSTRDSOQ))] | |
8819 | "TARGET_HAVE_MVE" | |
8820 | "vpst\;vstrdt.64\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
8821 | [(set_attr "length" "8")]) |
8822 | ||
8823 | ;; | |
8824 | ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u] | |
8825 | ;; | |
9a810e57 SP |
8826 | (define_expand "mve_vstrdq_scatter_offset_<supf>v2di" |
8827 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
8828 | (match_operand:V2DI 1 "s_register_operand") | |
8829 | (match_operand:V2DI 2 "s_register_operand") | |
8830 | (unspec:V4SI [(const_int 0)] VSTRDSOQ)] | |
7a5fffa5 SP |
8831 | "TARGET_HAVE_MVE" |
8832 | { | |
9a810e57 SP |
8833 | rtx ind = XEXP (operands[0], 0); |
8834 | gcc_assert (REG_P (ind)); | |
8835 | emit_insn (gen_mve_vstrdq_scatter_offset_<supf>v2di_insn (ind, operands[1], | |
8836 | operands[2])); | |
8837 | DONE; | |
8838 | }) | |
8839 | ||
8840 | (define_insn "mve_vstrdq_scatter_offset_<supf>v2di_insn" | |
8841 | [(set (mem:BLK (scratch)) | |
8842 | (unspec:BLK | |
8843 | [(match_operand:SI 0 "register_operand" "r") | |
8844 | (match_operand:V2DI 1 "s_register_operand" "w") | |
8845 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
8846 | VSTRDSOQ))] | |
8847 | "TARGET_HAVE_MVE" | |
8848 | "vstrd.64\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
8849 | [(set_attr "length" "4")]) |
8850 | ||
8851 | ;; | |
8852 | ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u] | |
8853 | ;; | |
9a810e57 SP |
8854 | (define_expand "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di" |
8855 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
8856 | (match_operand:V2DI 1 "s_register_operand") | |
8857 | (match_operand:V2DI 2 "s_register_operand") | |
8858 | (match_operand:HI 3 "vpr_register_operand") | |
8859 | (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] | |
7a5fffa5 SP |
8860 | "TARGET_HAVE_MVE" |
8861 | { | |
9a810e57 SP |
8862 | rtx ind = XEXP (operands[0], 0); |
8863 | gcc_assert (REG_P (ind)); | |
8864 | emit_insn ( | |
8865 | gen_mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn (ind, operands[1], | |
8866 | operands[2], | |
8867 | operands[3])); | |
8868 | DONE; | |
8869 | }) | |
8870 | ||
8871 | (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn" | |
8872 | [(set (mem:BLK (scratch)) | |
8873 | (unspec:BLK | |
8874 | [(match_operand:SI 0 "register_operand" "r") | |
8875 | (match_operand:V2DI 1 "s_register_operand" "w") | |
8876 | (match_operand:V2DI 2 "s_register_operand" "w") | |
8877 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8878 | VSTRDSSOQ))] | |
8879 | "TARGET_HAVE_MVE" | |
8880 | "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]" | |
7a5fffa5 SP |
8881 | [(set_attr "length" "8")]) |
8882 | ||
8883 | ;; | |
8884 | ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u] | |
8885 | ;; | |
9a810e57 SP |
8886 | (define_expand "mve_vstrdq_scatter_shifted_offset_<supf>v2di" |
8887 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
8888 | (match_operand:V2DI 1 "s_register_operand") | |
8889 | (match_operand:V2DI 2 "s_register_operand") | |
8890 | (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] | |
7a5fffa5 SP |
8891 | "TARGET_HAVE_MVE" |
8892 | { | |
9a810e57 SP |
8893 | rtx ind = XEXP (operands[0], 0); |
8894 | gcc_assert (REG_P (ind)); | |
8895 | emit_insn ( | |
8896 | gen_mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn (ind, operands[1], | |
8897 | operands[2])); | |
8898 | DONE; | |
8899 | }) | |
8900 | ||
8901 | (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn" | |
8902 | [(set (mem:BLK (scratch)) | |
8903 | (unspec:BLK | |
8904 | [(match_operand:SI 0 "register_operand" "r") | |
8905 | (match_operand:V2DI 1 "s_register_operand" "w") | |
8906 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
8907 | VSTRDSSOQ))] | |
8908 | "TARGET_HAVE_MVE" | |
8909 | "vstrd.64\t%q2, [%0, %q1, UXTW #3]" | |
7a5fffa5 SP |
8910 | [(set_attr "length" "4")]) |
8911 | ||
8912 | ;; | |
8913 | ;; [vstrhq_scatter_offset_f] | |
8914 | ;; | |
9a810e57 SP |
8915 | (define_expand "mve_vstrhq_scatter_offset_fv8hf" |
8916 | [(match_operand:V8HI 0 "mve_scatter_memory") | |
8917 | (match_operand:V8HI 1 "s_register_operand") | |
8918 | (match_operand:V8HF 2 "s_register_operand") | |
8919 | (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] | |
7a5fffa5 SP |
8920 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
8921 | { | |
9a810e57 SP |
8922 | rtx ind = XEXP (operands[0], 0); |
8923 | gcc_assert (REG_P (ind)); | |
8924 | emit_insn (gen_mve_vstrhq_scatter_offset_fv8hf_insn (ind, operands[1], | |
8925 | operands[2])); | |
8926 | DONE; | |
8927 | }) | |
8928 | ||
8929 | (define_insn "mve_vstrhq_scatter_offset_fv8hf_insn" | |
8930 | [(set (mem:BLK (scratch)) | |
8931 | (unspec:BLK | |
8932 | [(match_operand:SI 0 "register_operand" "r") | |
8933 | (match_operand:V8HI 1 "s_register_operand" "w") | |
8934 | (match_operand:V8HF 2 "s_register_operand" "w")] | |
8935 | VSTRHQSO_F))] | |
8936 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8937 | "vstrh.16\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
8938 | [(set_attr "length" "4")]) |
8939 | ||
8940 | ;; | |
8941 | ;; [vstrhq_scatter_offset_p_f] | |
8942 | ;; | |
9a810e57 SP |
8943 | (define_expand "mve_vstrhq_scatter_offset_p_fv8hf" |
8944 | [(match_operand:V8HI 0 "mve_scatter_memory") | |
8945 | (match_operand:V8HI 1 "s_register_operand") | |
8946 | (match_operand:V8HF 2 "s_register_operand") | |
8947 | (match_operand:HI 3 "vpr_register_operand") | |
8948 | (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] | |
7a5fffa5 SP |
8949 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
8950 | { | |
9a810e57 SP |
8951 | rtx ind = XEXP (operands[0], 0); |
8952 | gcc_assert (REG_P (ind)); | |
8953 | emit_insn (gen_mve_vstrhq_scatter_offset_p_fv8hf_insn (ind, operands[1], | |
8954 | operands[2], | |
8955 | operands[3])); | |
8956 | DONE; | |
8957 | }) | |
8958 | ||
8959 | (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" | |
8960 | [(set (mem:BLK (scratch)) | |
8961 | (unspec:BLK | |
8962 | [(match_operand:SI 0 "register_operand" "r") | |
8963 | (match_operand:V8HI 1 "s_register_operand" "w") | |
8964 | (match_operand:V8HF 2 "s_register_operand" "w") | |
8965 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
8966 | VSTRHQSO_F))] | |
8967 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8968 | "vpst\;vstrht.16\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
8969 | [(set_attr "length" "8")]) |
8970 | ||
8971 | ;; | |
8972 | ;; [vstrhq_scatter_shifted_offset_f] | |
8973 | ;; | |
9a810e57 SP |
8974 | (define_expand "mve_vstrhq_scatter_shifted_offset_fv8hf" |
8975 | [(match_operand:V8HI 0 "memory_operand" "=Us") | |
8976 | (match_operand:V8HI 1 "s_register_operand" "w") | |
8977 | (match_operand:V8HF 2 "s_register_operand" "w") | |
8978 | (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] | |
7a5fffa5 SP |
8979 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
8980 | { | |
9a810e57 SP |
8981 | rtx ind = XEXP (operands[0], 0); |
8982 | gcc_assert (REG_P (ind)); | |
8983 | emit_insn (gen_mve_vstrhq_scatter_shifted_offset_fv8hf_insn (ind, operands[1], | |
8984 | operands[2])); | |
8985 | DONE; | |
8986 | }) | |
8987 | ||
8988 | (define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf_insn" | |
8989 | [(set (mem:BLK (scratch)) | |
8990 | (unspec:BLK | |
8991 | [(match_operand:SI 0 "register_operand" "r") | |
8992 | (match_operand:V8HI 1 "s_register_operand" "w") | |
8993 | (match_operand:V8HF 2 "s_register_operand" "w")] | |
8994 | VSTRHQSSO_F))] | |
8995 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
8996 | "vstrh.16\t%q2, [%0, %q1, uxtw #1]" | |
7a5fffa5 SP |
8997 | [(set_attr "length" "4")]) |
8998 | ||
8999 | ;; | |
9000 | ;; [vstrhq_scatter_shifted_offset_p_f] | |
9001 | ;; | |
9a810e57 SP |
9002 | (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" |
9003 | [(match_operand:V8HI 0 "memory_operand" "=Us") | |
9004 | (match_operand:V8HI 1 "s_register_operand" "w") | |
9005 | (match_operand:V8HF 2 "s_register_operand" "w") | |
9006 | (match_operand:HI 3 "vpr_register_operand" "Up") | |
9007 | (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] | |
7a5fffa5 SP |
9008 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
9009 | { | |
9a810e57 SP |
9010 | rtx ind = XEXP (operands[0], 0); |
9011 | gcc_assert (REG_P (ind)); | |
9012 | emit_insn ( | |
9013 | gen_mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn (ind, operands[1], | |
9014 | operands[2], | |
9015 | operands[3])); | |
9016 | DONE; | |
9017 | }) | |
9018 | ||
9019 | (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" | |
9020 | [(set (mem:BLK (scratch)) | |
9021 | (unspec:BLK | |
9022 | [(match_operand:SI 0 "register_operand" "r") | |
9023 | (match_operand:V8HI 1 "s_register_operand" "w") | |
9024 | (match_operand:V8HF 2 "s_register_operand" "w") | |
9025 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9026 | VSTRHQSSO_F))] | |
9027 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9028 | "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" | |
7a5fffa5 SP |
9029 | [(set_attr "length" "8")]) |
9030 | ||
9031 | ;; | |
9032 | ;; [vstrwq_scatter_base_f] | |
9033 | ;; | |
9034 | (define_insn "mve_vstrwq_scatter_base_fv4sf" | |
9035 | [(set (mem:BLK (scratch)) | |
9036 | (unspec:BLK | |
9037 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
9038 | (match_operand:SI 1 "immediate_operand" "i") | |
9039 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
9040 | VSTRWQSB_F)) | |
9041 | ] | |
9042 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9043 | { | |
9044 | rtx ops[3]; | |
9045 | ops[0] = operands[0]; | |
9046 | ops[1] = operands[1]; | |
9047 | ops[2] = operands[2]; | |
9048 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops); | |
9049 | return ""; | |
9050 | } | |
9051 | [(set_attr "length" "4")]) | |
9052 | ||
9053 | ;; | |
9054 | ;; [vstrwq_scatter_base_p_f] | |
9055 | ;; | |
9056 | (define_insn "mve_vstrwq_scatter_base_p_fv4sf" | |
9057 | [(set (mem:BLK (scratch)) | |
9058 | (unspec:BLK | |
9059 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
9060 | (match_operand:SI 1 "immediate_operand" "i") | |
9061 | (match_operand:V4SF 2 "s_register_operand" "w") | |
9062 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9063 | VSTRWQSB_F)) | |
9064 | ] | |
9065 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9066 | { | |
9067 | rtx ops[3]; | |
9068 | ops[0] = operands[0]; | |
9069 | ops[1] = operands[1]; | |
9070 | ops[2] = operands[2]; | |
9071 | output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); | |
9072 | return ""; | |
9073 | } | |
9074 | [(set_attr "length" "8")]) | |
9075 | ||
9076 | ;; | |
9077 | ;; [vstrwq_scatter_offset_f] | |
9078 | ;; | |
9a810e57 SP |
9079 | (define_expand "mve_vstrwq_scatter_offset_fv4sf" |
9080 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9081 | (match_operand:V4SI 1 "s_register_operand") | |
9082 | (match_operand:V4SF 2 "s_register_operand") | |
9083 | (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] | |
7a5fffa5 SP |
9084 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
9085 | { | |
9a810e57 SP |
9086 | rtx ind = XEXP (operands[0], 0); |
9087 | gcc_assert (REG_P (ind)); | |
9088 | emit_insn (gen_mve_vstrwq_scatter_offset_fv4sf_insn (ind, operands[1], | |
9089 | operands[2])); | |
9090 | DONE; | |
9091 | }) | |
9092 | ||
9093 | (define_insn "mve_vstrwq_scatter_offset_fv4sf_insn" | |
9094 | [(set (mem:BLK (scratch)) | |
9095 | (unspec:BLK | |
9096 | [(match_operand:SI 0 "register_operand" "r") | |
9097 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9098 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
9099 | VSTRWQSO_F))] | |
9100 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9101 | "vstrw.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
9102 | [(set_attr "length" "4")]) |
9103 | ||
9104 | ;; | |
9105 | ;; [vstrwq_scatter_offset_p_f] | |
9106 | ;; | |
9a810e57 SP |
9107 | (define_expand "mve_vstrwq_scatter_offset_p_fv4sf" |
9108 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9109 | (match_operand:V4SI 1 "s_register_operand") | |
9110 | (match_operand:V4SF 2 "s_register_operand") | |
9111 | (match_operand:HI 3 "vpr_register_operand") | |
9112 | (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] | |
7a5fffa5 SP |
9113 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
9114 | { | |
9a810e57 SP |
9115 | rtx ind = XEXP (operands[0], 0); |
9116 | gcc_assert (REG_P (ind)); | |
9117 | emit_insn (gen_mve_vstrwq_scatter_offset_p_fv4sf_insn (ind, operands[1], | |
9118 | operands[2], | |
9119 | operands[3])); | |
9120 | DONE; | |
9121 | }) | |
9122 | ||
9123 | (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" | |
9124 | [(set (mem:BLK (scratch)) | |
9125 | (unspec:BLK | |
9126 | [(match_operand:SI 0 "register_operand" "r") | |
9127 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9128 | (match_operand:V4SF 2 "s_register_operand" "w") | |
9129 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9130 | VSTRWQSO_F))] | |
9131 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9132 | "vpst\;vstrwt.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
9133 | [(set_attr "length" "8")]) |
9134 | ||
9135 | ;; | |
9a810e57 | 9136 | ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] |
7a5fffa5 | 9137 | ;; |
9a810e57 SP |
9138 | (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" |
9139 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9140 | (match_operand:V4SI 1 "s_register_operand") | |
9141 | (match_operand:V4SI 2 "s_register_operand") | |
9142 | (match_operand:HI 3 "vpr_register_operand") | |
9143 | (unspec:V4SI [(const_int 0)] VSTRWSOQ)] | |
7a5fffa5 SP |
9144 | "TARGET_HAVE_MVE" |
9145 | { | |
9a810e57 SP |
9146 | rtx ind = XEXP (operands[0], 0); |
9147 | gcc_assert (REG_P (ind)); | |
9148 | emit_insn (gen_mve_vstrwq_scatter_offset_p_<supf>v4si_insn (ind, operands[1], | |
9149 | operands[2], | |
9150 | operands[3])); | |
9151 | DONE; | |
9152 | }) | |
9153 | ||
9154 | (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" | |
9155 | [(set (mem:BLK (scratch)) | |
9156 | (unspec:BLK | |
9157 | [(match_operand:SI 0 "register_operand" "r") | |
9158 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9159 | (match_operand:V4SI 2 "s_register_operand" "w") | |
9160 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9161 | VSTRWSOQ))] | |
9162 | "TARGET_HAVE_MVE" | |
9163 | "vpst\;vstrwt.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
9164 | [(set_attr "length" "8")]) |
9165 | ||
9166 | ;; | |
9167 | ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] | |
9168 | ;; | |
9a810e57 SP |
9169 | (define_expand "mve_vstrwq_scatter_offset_<supf>v4si" |
9170 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9171 | (match_operand:V4SI 1 "s_register_operand") | |
9172 | (match_operand:V4SI 2 "s_register_operand") | |
9173 | (unspec:V4SI [(const_int 0)] VSTRWSOQ)] | |
7a5fffa5 SP |
9174 | "TARGET_HAVE_MVE" |
9175 | { | |
9a810e57 SP |
9176 | rtx ind = XEXP (operands[0], 0); |
9177 | gcc_assert (REG_P (ind)); | |
9178 | emit_insn (gen_mve_vstrwq_scatter_offset_<supf>v4si_insn (ind, operands[1], | |
9179 | operands[2])); | |
9180 | DONE; | |
9181 | }) | |
9182 | ||
9183 | (define_insn "mve_vstrwq_scatter_offset_<supf>v4si_insn" | |
9184 | [(set (mem:BLK (scratch)) | |
9185 | (unspec:BLK | |
9186 | [(match_operand:SI 0 "register_operand" "r") | |
9187 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9188 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
9189 | VSTRWSOQ))] | |
9190 | "TARGET_HAVE_MVE" | |
9191 | "vstrw.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
9192 | [(set_attr "length" "4")]) |
9193 | ||
9194 | ;; | |
9195 | ;; [vstrwq_scatter_shifted_offset_f] | |
9196 | ;; | |
9a810e57 SP |
9197 | (define_expand "mve_vstrwq_scatter_shifted_offset_fv4sf" |
9198 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9199 | (match_operand:V4SI 1 "s_register_operand") | |
9200 | (match_operand:V4SF 2 "s_register_operand") | |
9201 | (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] | |
7a5fffa5 SP |
9202 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
9203 | { | |
9a810e57 SP |
9204 | rtx ind = XEXP (operands[0], 0); |
9205 | gcc_assert (REG_P (ind)); | |
9206 | emit_insn (gen_mve_vstrwq_scatter_shifted_offset_fv4sf_insn (ind, operands[1], | |
9207 | operands[2])); | |
9208 | DONE; | |
9209 | }) | |
9210 | ||
9211 | (define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf_insn" | |
9212 | [(set (mem:BLK (scratch)) | |
9213 | (unspec:BLK | |
9214 | [(match_operand:SI 0 "register_operand" "r") | |
9215 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9216 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
9217 | VSTRWQSSO_F))] | |
9218 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9219 | "vstrw.32\t%q2, [%0, %q1, uxtw #2]" | |
9220 | [(set_attr "length" "8")]) | |
7a5fffa5 SP |
9221 | |
9222 | ;; | |
9223 | ;; [vstrwq_scatter_shifted_offset_p_f] | |
9224 | ;; | |
9a810e57 SP |
9225 | (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" |
9226 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9227 | (match_operand:V4SI 1 "s_register_operand") | |
9228 | (match_operand:V4SF 2 "s_register_operand") | |
9229 | (match_operand:HI 3 "vpr_register_operand") | |
9230 | (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] | |
7a5fffa5 SP |
9231 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
9232 | { | |
9a810e57 SP |
9233 | rtx ind = XEXP (operands[0], 0); |
9234 | gcc_assert (REG_P (ind)); | |
9235 | emit_insn ( | |
9236 | gen_mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn (ind, operands[1], | |
9237 | operands[2], | |
9238 | operands[3])); | |
9239 | DONE; | |
9240 | }) | |
9241 | ||
9242 | (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" | |
9243 | [(set (mem:BLK (scratch)) | |
9244 | (unspec:BLK | |
9245 | [(match_operand:SI 0 "register_operand" "r") | |
9246 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9247 | (match_operand:V4SF 2 "s_register_operand" "w") | |
9248 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9249 | VSTRWQSSO_F))] | |
9250 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9251 | "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 SP |
9252 | [(set_attr "length" "8")]) |
9253 | ||
9254 | ;; | |
9255 | ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u] | |
9256 | ;; | |
9a810e57 SP |
9257 | (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" |
9258 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9259 | (match_operand:V4SI 1 "s_register_operand") | |
9260 | (match_operand:V4SI 2 "s_register_operand") | |
9261 | (match_operand:HI 3 "vpr_register_operand") | |
9262 | (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] | |
7a5fffa5 SP |
9263 | "TARGET_HAVE_MVE" |
9264 | { | |
9a810e57 SP |
9265 | rtx ind = XEXP (operands[0], 0); |
9266 | gcc_assert (REG_P (ind)); | |
9267 | emit_insn ( | |
9268 | gen_mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn (ind, operands[1], | |
9269 | operands[2], | |
9270 | operands[3])); | |
9271 | DONE; | |
9272 | }) | |
9273 | ||
9274 | (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" | |
9275 | [(set (mem:BLK (scratch)) | |
9276 | (unspec:BLK | |
9277 | [(match_operand:SI 0 "register_operand" "r") | |
9278 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9279 | (match_operand:V4SI 2 "s_register_operand" "w") | |
9280 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
9281 | VSTRWSSOQ))] | |
9282 | "TARGET_HAVE_MVE" | |
9283 | "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 SP |
9284 | [(set_attr "length" "8")]) |
9285 | ||
9286 | ;; | |
9287 | ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u] | |
9288 | ;; | |
9a810e57 SP |
9289 | (define_expand "mve_vstrwq_scatter_shifted_offset_<supf>v4si" |
9290 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
9291 | (match_operand:V4SI 1 "s_register_operand") | |
9292 | (match_operand:V4SI 2 "s_register_operand") | |
9293 | (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] | |
7a5fffa5 SP |
9294 | "TARGET_HAVE_MVE" |
9295 | { | |
9a810e57 SP |
9296 | rtx ind = XEXP (operands[0], 0); |
9297 | gcc_assert (REG_P (ind)); | |
9298 | emit_insn ( | |
9299 | gen_mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn (ind, operands[1], | |
9300 | operands[2])); | |
9301 | DONE; | |
9302 | }) | |
9303 | ||
9304 | (define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn" | |
9305 | [(set (mem:BLK (scratch)) | |
9306 | (unspec:BLK | |
9307 | [(match_operand:SI 0 "register_operand" "r") | |
9308 | (match_operand:V4SI 1 "s_register_operand" "w") | |
9309 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
9310 | VSTRWSSOQ))] | |
9311 | "TARGET_HAVE_MVE" | |
9312 | "vstrw.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 | 9313 | [(set_attr "length" "4")]) |
3eff57aa SP |
9314 | |
9315 | ;; | |
9316 | ;; [vaddq_s, vaddq_u]) | |
9317 | ;; | |
9318 | (define_insn "mve_vaddq<mode>" | |
9319 | [ | |
9320 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9321 | (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") | |
9322 | (match_operand:MVE_2 2 "s_register_operand" "w"))) | |
9323 | ] | |
9324 | "TARGET_HAVE_MVE" | |
9325 | "vadd.i%#<V_sz_elem> %q0, %q1, %q2" | |
9326 | [(set_attr "type" "mve_move") | |
9327 | ]) | |
9328 | ||
9329 | ;; | |
9330 | ;; [vaddq_f]) | |
9331 | ;; | |
9332 | (define_insn "mve_vaddq_f<mode>" | |
9333 | [ | |
9334 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
9335 | (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") | |
9336 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
9337 | ] | |
9338 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9339 | "vadd.f%#<V_sz_elem> %q0, %q1, %q2" | |
9340 | [(set_attr "type" "mve_move") | |
9341 | ]) | |
92f80065 SP |
9342 | |
9343 | ;; | |
9344 | ;; [vidupq_n_u]) | |
9345 | ;; | |
9346 | (define_expand "mve_vidupq_n_u<mode>" | |
9347 | [(match_operand:MVE_2 0 "s_register_operand") | |
9348 | (match_operand:SI 1 "s_register_operand") | |
9349 | (match_operand:SI 2 "mve_imm_selective_upto_8")] | |
9350 | "TARGET_HAVE_MVE" | |
9351 | { | |
9352 | rtx temp = gen_reg_rtx (SImode); | |
9353 | emit_move_insn (temp, operands[1]); | |
9354 | rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); | |
9355 | emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1], | |
9356 | operands[2], inc)); | |
9357 | DONE; | |
9358 | }) | |
9359 | ||
9360 | ;; | |
9361 | ;; [vidupq_u_insn]) | |
9362 | ;; | |
9363 | (define_insn "mve_vidupq_u<mode>_insn" | |
9364 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9365 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9366 | (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] | |
9367 | VIDUPQ)) | |
3d537943 | 9368 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
9369 | (plus:SI (match_dup 2) |
9370 | (match_operand:SI 4 "immediate_operand" "i")))] | |
9371 | "TARGET_HAVE_MVE" | |
9372 | "vidup.u%#<V_sz_elem>\t%q0, %1, %3") | |
9373 | ||
9374 | ;; | |
9375 | ;; [vidupq_m_n_u]) | |
9376 | ;; | |
9377 | (define_expand "mve_vidupq_m_n_u<mode>" | |
9378 | [(match_operand:MVE_2 0 "s_register_operand") | |
9379 | (match_operand:MVE_2 1 "s_register_operand") | |
9380 | (match_operand:SI 2 "s_register_operand") | |
9381 | (match_operand:SI 3 "mve_imm_selective_upto_8") | |
9382 | (match_operand:HI 4 "vpr_register_operand")] | |
9383 | "TARGET_HAVE_MVE" | |
9384 | { | |
9385 | rtx temp = gen_reg_rtx (SImode); | |
9386 | emit_move_insn (temp, operands[2]); | |
9387 | rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); | |
9388 | emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, | |
9389 | operands[2], operands[3], | |
9390 | operands[4], inc)); | |
9391 | DONE; | |
9392 | }) | |
9393 | ||
9394 | ;; | |
9395 | ;; [vidupq_m_wb_u_insn]) | |
9396 | ;; | |
9397 | (define_insn "mve_vidupq_m_wb_u<mode>_insn" | |
9398 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9399 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
9400 | (match_operand:SI 3 "s_register_operand" "2") | |
9401 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") | |
9402 | (match_operand:HI 5 "vpr_register_operand" "Up")] | |
9403 | VIDUPQ_M)) | |
3d537943 | 9404 | (set (match_operand:SI 2 "s_register_operand" "=Te") |
92f80065 SP |
9405 | (plus:SI (match_dup 3) |
9406 | (match_operand:SI 6 "immediate_operand" "i")))] | |
9407 | "TARGET_HAVE_MVE" | |
9408 | "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4" | |
9409 | [(set_attr "length""8")]) | |
9410 | ||
9411 | ;; | |
9412 | ;; [vddupq_n_u]) | |
9413 | ;; | |
9414 | (define_expand "mve_vddupq_n_u<mode>" | |
9415 | [(match_operand:MVE_2 0 "s_register_operand") | |
9416 | (match_operand:SI 1 "s_register_operand") | |
9417 | (match_operand:SI 2 "mve_imm_selective_upto_8")] | |
9418 | "TARGET_HAVE_MVE" | |
9419 | { | |
9420 | rtx temp = gen_reg_rtx (SImode); | |
9421 | emit_move_insn (temp, operands[1]); | |
9422 | rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); | |
9423 | emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1], | |
9424 | operands[2], inc)); | |
9425 | DONE; | |
9426 | }) | |
9427 | ||
9428 | ;; | |
9429 | ;; [vddupq_u_insn]) | |
9430 | ;; | |
9431 | (define_insn "mve_vddupq_u<mode>_insn" | |
9432 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9433 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9434 | (match_operand:SI 3 "immediate_operand" "i")] | |
9435 | VDDUPQ)) | |
3d537943 | 9436 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
9437 | (minus:SI (match_dup 2) |
9438 | (match_operand:SI 4 "immediate_operand" "i")))] | |
9439 | "TARGET_HAVE_MVE" | |
9440 | "vddup.u%#<V_sz_elem> %q0, %1, %3") | |
9441 | ||
9442 | ;; | |
9443 | ;; [vddupq_m_n_u]) | |
9444 | ;; | |
9445 | (define_expand "mve_vddupq_m_n_u<mode>" | |
9446 | [(match_operand:MVE_2 0 "s_register_operand") | |
9447 | (match_operand:MVE_2 1 "s_register_operand") | |
9448 | (match_operand:SI 2 "s_register_operand") | |
9449 | (match_operand:SI 3 "mve_imm_selective_upto_8") | |
9450 | (match_operand:HI 4 "vpr_register_operand")] | |
9451 | "TARGET_HAVE_MVE" | |
9452 | { | |
9453 | rtx temp = gen_reg_rtx (SImode); | |
9454 | emit_move_insn (temp, operands[2]); | |
9455 | rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); | |
9456 | emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, | |
9457 | operands[2], operands[3], | |
9458 | operands[4], inc)); | |
9459 | DONE; | |
9460 | }) | |
9461 | ||
9462 | ;; | |
9463 | ;; [vddupq_m_wb_u_insn]) | |
9464 | ;; | |
9465 | (define_insn "mve_vddupq_m_wb_u<mode>_insn" | |
9466 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9467 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
9468 | (match_operand:SI 3 "s_register_operand" "2") | |
9469 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") | |
9470 | (match_operand:HI 5 "vpr_register_operand" "Up")] | |
9471 | VDDUPQ_M)) | |
3d537943 | 9472 | (set (match_operand:SI 2 "s_register_operand" "=Te") |
92f80065 SP |
9473 | (minus:SI (match_dup 3) |
9474 | (match_operand:SI 6 "immediate_operand" "i")))] | |
9475 | "TARGET_HAVE_MVE" | |
9476 | "vpst\;\tvddupt.u%#<V_sz_elem>\t%q0, %2, %4" | |
9477 | [(set_attr "length""8")]) | |
9478 | ||
9479 | ;; | |
9480 | ;; [vdwdupq_n_u]) | |
9481 | ;; | |
9482 | (define_expand "mve_vdwdupq_n_u<mode>" | |
9483 | [(match_operand:MVE_2 0 "s_register_operand") | |
9484 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 9485 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
9486 | (match_operand:SI 3 "mve_imm_selective_upto_8")] |
9487 | "TARGET_HAVE_MVE" | |
9488 | { | |
9489 | rtx ignore_wb = gen_reg_rtx (SImode); | |
9490 | emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb, | |
9491 | operands[1], operands[2], | |
9492 | operands[3])); | |
9493 | DONE; | |
9494 | }) | |
9495 | ||
9496 | ;; | |
9497 | ;; [vdwdupq_wb_u]) | |
9498 | ;; | |
9499 | (define_expand "mve_vdwdupq_wb_u<mode>" | |
9500 | [(match_operand:SI 0 "s_register_operand") | |
9501 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 9502 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
9503 | (match_operand:SI 3 "mve_imm_selective_upto_8") |
9504 | (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
9505 | "TARGET_HAVE_MVE" | |
9506 | { | |
9507 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
9508 | emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0], | |
9509 | operands[1], operands[2], | |
9510 | operands[3])); | |
9511 | DONE; | |
9512 | }) | |
9513 | ||
9514 | ;; | |
9515 | ;; [vdwdupq_wb_u_insn]) | |
9516 | ;; | |
9517 | (define_insn "mve_vdwdupq_wb_u<mode>_insn" | |
9518 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9519 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9ce780ef | 9520 | (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) |
92f80065 SP |
9521 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] |
9522 | VDWDUPQ)) | |
3d537943 | 9523 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 | 9524 | (unspec:SI [(match_dup 2) |
9ce780ef | 9525 | (subreg:SI (match_dup 3) 4) |
92f80065 SP |
9526 | (match_dup 4)] |
9527 | VDWDUPQ))] | |
9528 | "TARGET_HAVE_MVE" | |
9ce780ef | 9529 | "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" |
92f80065 SP |
9530 | ) |
9531 | ||
9532 | ;; | |
9533 | ;; [vdwdupq_m_n_u]) | |
9534 | ;; | |
9535 | (define_expand "mve_vdwdupq_m_n_u<mode>" | |
9536 | [(match_operand:MVE_2 0 "s_register_operand") | |
9537 | (match_operand:MVE_2 1 "s_register_operand") | |
9538 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 9539 | (match_operand:DI 3 "s_register_operand") |
92f80065 SP |
9540 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
9541 | (match_operand:HI 5 "vpr_register_operand")] | |
9542 | "TARGET_HAVE_MVE" | |
9543 | { | |
9544 | rtx ignore_wb = gen_reg_rtx (SImode); | |
9545 | emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, | |
9546 | operands[1], operands[2], | |
9547 | operands[3], operands[4], | |
9548 | operands[5])); | |
9549 | DONE; | |
9550 | }) | |
9551 | ||
9552 | ;; | |
9553 | ;; [vdwdupq_m_wb_u]) | |
9554 | ;; | |
9555 | (define_expand "mve_vdwdupq_m_wb_u<mode>" | |
9556 | [(match_operand:SI 0 "s_register_operand") | |
9557 | (match_operand:MVE_2 1 "s_register_operand") | |
9558 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 9559 | (match_operand:DI 3 "s_register_operand") |
92f80065 SP |
9560 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
9561 | (match_operand:HI 5 "vpr_register_operand")] | |
9562 | "TARGET_HAVE_MVE" | |
9563 | { | |
9564 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
9565 | emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], | |
9566 | operands[1], operands[2], | |
9567 | operands[3], operands[4], | |
9568 | operands[5])); | |
9569 | DONE; | |
9570 | }) | |
9571 | ||
9572 | ;; | |
9573 | ;; [vdwdupq_m_wb_u_insn]) | |
9574 | ;; | |
9575 | (define_insn "mve_vdwdupq_m_wb_u<mode>_insn" | |
9576 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9ce780ef | 9577 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") |
92f80065 | 9578 | (match_operand:SI 3 "s_register_operand" "1") |
9ce780ef | 9579 | (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) |
92f80065 SP |
9580 | (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") |
9581 | (match_operand:HI 6 "vpr_register_operand" "Up")] | |
9582 | VDWDUPQ_M)) | |
3d537943 | 9583 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
9584 | (unspec:SI [(match_dup 2) |
9585 | (match_dup 3) | |
9ce780ef | 9586 | (subreg:SI (match_dup 4) 4) |
92f80065 SP |
9587 | (match_dup 5) |
9588 | (match_dup 6)] | |
9589 | VDWDUPQ_M)) | |
9590 | ] | |
9591 | "TARGET_HAVE_MVE" | |
9ce780ef | 9592 | "vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" |
92f80065 SP |
9593 | [(set_attr "type" "mve_move") |
9594 | (set_attr "length""8")]) | |
9595 | ||
9596 | ;; | |
9597 | ;; [viwdupq_n_u]) | |
9598 | ;; | |
9599 | (define_expand "mve_viwdupq_n_u<mode>" | |
9600 | [(match_operand:MVE_2 0 "s_register_operand") | |
9601 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 9602 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
9603 | (match_operand:SI 3 "mve_imm_selective_upto_8")] |
9604 | "TARGET_HAVE_MVE" | |
9605 | { | |
9606 | rtx ignore_wb = gen_reg_rtx (SImode); | |
9607 | emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb, | |
9608 | operands[1], operands[2], | |
9609 | operands[3])); | |
9610 | DONE; | |
9611 | }) | |
9612 | ||
9613 | ;; | |
9614 | ;; [viwdupq_wb_u]) | |
9615 | ;; | |
9616 | (define_expand "mve_viwdupq_wb_u<mode>" | |
9617 | [(match_operand:SI 0 "s_register_operand") | |
9618 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 9619 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
9620 | (match_operand:SI 3 "mve_imm_selective_upto_8") |
9621 | (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
9622 | "TARGET_HAVE_MVE" | |
9623 | { | |
9624 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
9625 | emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0], | |
9626 | operands[1], operands[2], | |
9627 | operands[3])); | |
9628 | DONE; | |
9629 | }) | |
9630 | ||
9631 | ;; | |
9632 | ;; [viwdupq_wb_u_insn]) | |
9633 | ;; | |
9634 | (define_insn "mve_viwdupq_wb_u<mode>_insn" | |
9635 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9636 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9ce780ef | 9637 | (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) |
92f80065 SP |
9638 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] |
9639 | VIWDUPQ)) | |
3d537943 | 9640 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 | 9641 | (unspec:SI [(match_dup 2) |
9ce780ef | 9642 | (subreg:SI (match_dup 3) 4) |
92f80065 SP |
9643 | (match_dup 4)] |
9644 | VIWDUPQ))] | |
9645 | "TARGET_HAVE_MVE" | |
9ce780ef | 9646 | "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" |
92f80065 SP |
9647 | ) |
9648 | ||
9649 | ;; | |
9650 | ;; [viwdupq_m_n_u]) | |
9651 | ;; | |
9652 | (define_expand "mve_viwdupq_m_n_u<mode>" | |
9653 | [(match_operand:MVE_2 0 "s_register_operand") | |
9654 | (match_operand:MVE_2 1 "s_register_operand") | |
9655 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 9656 | (match_operand:DI 3 "s_register_operand") |
92f80065 SP |
9657 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
9658 | (match_operand:HI 5 "vpr_register_operand")] | |
9659 | "TARGET_HAVE_MVE" | |
9660 | { | |
9661 | rtx ignore_wb = gen_reg_rtx (SImode); | |
9662 | emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, | |
9663 | operands[1], operands[2], | |
9664 | operands[3], operands[4], | |
9665 | operands[5])); | |
9666 | DONE; | |
9667 | }) | |
9668 | ||
9669 | ;; | |
9670 | ;; [viwdupq_m_wb_u]) | |
9671 | ;; | |
9672 | (define_expand "mve_viwdupq_m_wb_u<mode>" | |
9673 | [(match_operand:SI 0 "s_register_operand") | |
9674 | (match_operand:MVE_2 1 "s_register_operand") | |
9675 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 9676 | (match_operand:DI 3 "s_register_operand") |
92f80065 SP |
9677 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
9678 | (match_operand:HI 5 "vpr_register_operand")] | |
9679 | "TARGET_HAVE_MVE" | |
9680 | { | |
9681 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
9682 | emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], | |
9683 | operands[1], operands[2], | |
9684 | operands[3], operands[4], | |
9685 | operands[5])); | |
9686 | DONE; | |
9687 | }) | |
9688 | ||
9689 | ;; | |
9690 | ;; [viwdupq_m_wb_u_insn]) | |
9691 | ;; | |
9692 | (define_insn "mve_viwdupq_m_wb_u<mode>_insn" | |
9693 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9ce780ef | 9694 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") |
92f80065 | 9695 | (match_operand:SI 3 "s_register_operand" "1") |
9ce780ef | 9696 | (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) |
92f80065 SP |
9697 | (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") |
9698 | (match_operand:HI 6 "vpr_register_operand" "Up")] | |
9699 | VIWDUPQ_M)) | |
3d537943 | 9700 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
9701 | (unspec:SI [(match_dup 2) |
9702 | (match_dup 3) | |
9ce780ef | 9703 | (subreg:SI (match_dup 4) 4) |
92f80065 SP |
9704 | (match_dup 5) |
9705 | (match_dup 6)] | |
9706 | VIWDUPQ_M)) | |
9707 | ] | |
9708 | "TARGET_HAVE_MVE" | |
9ce780ef | 9709 | "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" |
92f80065 SP |
9710 | [(set_attr "type" "mve_move") |
9711 | (set_attr "length""8")]) | |
9ce780ef | 9712 | |
41e1a7ff | 9713 | ;; |
37753588 | 9714 | ;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u] |
41e1a7ff | 9715 | ;; |
37753588 | 9716 | (define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si" |
41e1a7ff SP |
9717 | [(set (mem:BLK (scratch)) |
9718 | (unspec:BLK | |
9719 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
9720 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9721 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
9722 | VSTRWSBWBQ)) | |
9723 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
9724 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
9725 | VSTRWSBWBQ)) | |
9726 | ] | |
9727 | "TARGET_HAVE_MVE" | |
9728 | { | |
9729 | rtx ops[3]; | |
9730 | ops[0] = operands[1]; | |
9731 | ops[1] = operands[2]; | |
9732 | ops[2] = operands[3]; | |
9733 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); | |
9734 | return ""; | |
9735 | } | |
9736 | [(set_attr "length" "4")]) | |
9737 | ||
41e1a7ff SP |
9738 | ;; |
9739 | ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] | |
9740 | ;; | |
37753588 | 9741 | (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" |
41e1a7ff SP |
9742 | [(set (mem:BLK (scratch)) |
9743 | (unspec:BLK | |
9744 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
9745 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9746 | (match_operand:V4SI 3 "s_register_operand" "w") | |
9747 | (match_operand:HI 4 "vpr_register_operand")] | |
9748 | VSTRWSBWBQ)) | |
9749 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
9750 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
9751 | VSTRWSBWBQ)) | |
9752 | ] | |
9753 | "TARGET_HAVE_MVE" | |
9754 | { | |
9755 | rtx ops[3]; | |
9756 | ops[0] = operands[1]; | |
9757 | ops[1] = operands[2]; | |
9758 | ops[2] = operands[3]; | |
9759 | output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); | |
9760 | return ""; | |
9761 | } | |
9762 | [(set_attr "length" "8")]) | |
9763 | ||
41e1a7ff SP |
9764 | ;; |
9765 | ;; [vstrwq_scatter_base_wb_f] | |
9766 | ;; | |
37753588 | 9767 | (define_insn "mve_vstrwq_scatter_base_wb_fv4sf" |
41e1a7ff SP |
9768 | [(set (mem:BLK (scratch)) |
9769 | (unspec:BLK | |
9770 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
9771 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9772 | (match_operand:V4SF 3 "s_register_operand" "w")] | |
9773 | VSTRWQSBWB_F)) | |
9774 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
9775 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
9776 | VSTRWQSBWB_F)) | |
9777 | ] | |
9778 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9779 | { | |
9780 | rtx ops[3]; | |
9781 | ops[0] = operands[1]; | |
9782 | ops[1] = operands[2]; | |
9783 | ops[2] = operands[3]; | |
9784 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); | |
9785 | return ""; | |
9786 | } | |
9787 | [(set_attr "length" "4")]) | |
9788 | ||
41e1a7ff SP |
9789 | ;; |
9790 | ;; [vstrwq_scatter_base_wb_p_f] | |
9791 | ;; | |
37753588 | 9792 | (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" |
41e1a7ff SP |
9793 | [(set (mem:BLK (scratch)) |
9794 | (unspec:BLK | |
9795 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
9796 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9797 | (match_operand:V4SF 3 "s_register_operand" "w") | |
9798 | (match_operand:HI 4 "vpr_register_operand")] | |
9799 | VSTRWQSBWB_F)) | |
9800 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
9801 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
9802 | VSTRWQSBWB_F)) | |
9803 | ] | |
9804 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9805 | { | |
9806 | rtx ops[3]; | |
9807 | ops[0] = operands[1]; | |
9808 | ops[1] = operands[2]; | |
9809 | ops[2] = operands[3]; | |
9810 | output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); | |
9811 | return ""; | |
9812 | } | |
9813 | [(set_attr "length" "8")]) | |
9814 | ||
41e1a7ff SP |
9815 | ;; |
9816 | ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] | |
9817 | ;; | |
37753588 | 9818 | (define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di" |
41e1a7ff SP |
9819 | [(set (mem:BLK (scratch)) |
9820 | (unspec:BLK | |
9821 | [(match_operand:V2DI 1 "s_register_operand" "0") | |
9822 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9823 | (match_operand:V2DI 3 "s_register_operand" "w")] | |
9824 | VSTRDSBWBQ)) | |
9825 | (set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
9826 | (unspec:V2DI [(match_dup 1) (match_dup 2)] | |
9827 | VSTRDSBWBQ)) | |
9828 | ] | |
9829 | "TARGET_HAVE_MVE" | |
9830 | { | |
9831 | rtx ops[3]; | |
9832 | ops[0] = operands[1]; | |
9833 | ops[1] = operands[2]; | |
9834 | ops[2] = operands[3]; | |
9835 | output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops); | |
9836 | return ""; | |
9837 | } | |
9838 | [(set_attr "length" "4")]) | |
9839 | ||
41e1a7ff SP |
9840 | ;; |
9841 | ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] | |
9842 | ;; | |
37753588 | 9843 | (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di" |
41e1a7ff SP |
9844 | [(set (mem:BLK (scratch)) |
9845 | (unspec:BLK | |
9846 | [(match_operand:V2DI 1 "s_register_operand" "0") | |
9847 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
9848 | (match_operand:V2DI 3 "s_register_operand" "w") | |
9849 | (match_operand:HI 4 "vpr_register_operand")] | |
9850 | VSTRDSBWBQ)) | |
9851 | (set (match_operand:V2DI 0 "s_register_operand" "=w") | |
9852 | (unspec:V2DI [(match_dup 1) (match_dup 2)] | |
9853 | VSTRDSBWBQ)) | |
9854 | ] | |
9855 | "TARGET_HAVE_MVE" | |
9856 | { | |
9857 | rtx ops[3]; | |
9858 | ops[0] = operands[1]; | |
9859 | ops[1] = operands[2]; | |
9860 | ops[2] = operands[3]; | |
37753588 | 9861 | output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops); |
41e1a7ff SP |
9862 | return ""; |
9863 | } | |
9864 | [(set_attr "length" "8")]) | |
9865 | ||
9866 | (define_expand "mve_vldrwq_gather_base_wb_<supf>v4si" | |
9867 | [(match_operand:V4SI 0 "s_register_operand") | |
9868 | (match_operand:V4SI 1 "s_register_operand") | |
9869 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9870 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
9871 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
9872 | { |
9873 | rtx ignore_result = gen_reg_rtx (V4SImode); | |
9874 | emit_insn ( | |
9875 | gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0], | |
9876 | operands[1], operands[2])); | |
9877 | DONE; | |
9878 | }) | |
9879 | ||
9880 | (define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si" | |
9881 | [(match_operand:V4SI 0 "s_register_operand") | |
9882 | (match_operand:V4SI 1 "s_register_operand") | |
9883 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9884 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
9885 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
9886 | { |
9887 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
9888 | emit_insn ( | |
9889 | gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb, | |
9890 | operands[1], operands[2])); | |
9891 | DONE; | |
9892 | }) | |
9893 | ||
9894 | ;; | |
9895 | ;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u] | |
9896 | ;; | |
9897 | (define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn" | |
9898 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
9899 | (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") | |
9900 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
9901 | (mem:BLK (scratch))] | |
9902 | VLDRWGBWBQ)) | |
9903 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
9904 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
9905 | VLDRWGBWBQ)) | |
9906 | ] | |
9907 | "TARGET_HAVE_MVE" | |
9908 | { | |
9909 | rtx ops[3]; | |
9910 | ops[0] = operands[0]; | |
9911 | ops[1] = operands[2]; | |
9912 | ops[2] = operands[3]; | |
9913 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); | |
9914 | return ""; | |
9915 | } | |
9916 | [(set_attr "length" "4")]) | |
9917 | ||
9918 | (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" | |
9919 | [(match_operand:V4SI 0 "s_register_operand") | |
9920 | (match_operand:V4SI 1 "s_register_operand") | |
9921 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9922 | (match_operand:HI 3 "vpr_register_operand") | |
9923 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
9924 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
9925 | { |
9926 | rtx ignore_result = gen_reg_rtx (V4SImode); | |
9927 | emit_insn ( | |
9928 | gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0], | |
9929 | operands[1], operands[2], | |
9930 | operands[3])); | |
9931 | DONE; | |
9932 | }) | |
9933 | (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" | |
9934 | [(match_operand:V4SI 0 "s_register_operand") | |
9935 | (match_operand:V4SI 1 "s_register_operand") | |
9936 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9937 | (match_operand:HI 3 "vpr_register_operand") | |
9938 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
9939 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
9940 | { |
9941 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
9942 | emit_insn ( | |
9943 | gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb, | |
9944 | operands[1], operands[2], | |
9945 | operands[3])); | |
9946 | DONE; | |
9947 | }) | |
9948 | ||
9949 | ;; | |
9950 | ;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u] | |
9951 | ;; | |
9952 | (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" | |
9953 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
9954 | (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") | |
9955 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
9956 | (match_operand:HI 4 "vpr_register_operand" "Up") | |
9957 | (mem:BLK (scratch))] | |
9958 | VLDRWGBWBQ)) | |
9959 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
9960 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
9961 | VLDRWGBWBQ)) | |
9962 | ] | |
9963 | "TARGET_HAVE_MVE" | |
9964 | { | |
9965 | rtx ops[3]; | |
9966 | ops[0] = operands[0]; | |
9967 | ops[1] = operands[2]; | |
9968 | ops[2] = operands[3]; | |
ff825b81 | 9969 | output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
9970 | return ""; |
9971 | } | |
9972 | [(set_attr "length" "8")]) | |
9973 | ||
9974 | (define_expand "mve_vldrwq_gather_base_wb_fv4sf" | |
ff825b81 SP |
9975 | [(match_operand:V4SI 0 "s_register_operand") |
9976 | (match_operand:V4SI 1 "s_register_operand") | |
9977 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9978 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
9979 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9980 | { | |
9981 | rtx ignore_result = gen_reg_rtx (V4SFmode); | |
9982 | emit_insn ( | |
9983 | gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0], | |
9984 | operands[1], operands[2])); | |
9985 | DONE; | |
9986 | }) | |
9987 | ||
9988 | (define_expand "mve_vldrwq_gather_base_nowb_fv4sf" | |
41e1a7ff SP |
9989 | [(match_operand:V4SF 0 "s_register_operand") |
9990 | (match_operand:V4SI 1 "s_register_operand") | |
9991 | (match_operand:SI 2 "mve_vldrd_immediate") | |
9992 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
9993 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9994 | { | |
9995 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
9996 | emit_insn ( | |
9997 | gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb, | |
9998 | operands[1], operands[2])); | |
9999 | DONE; | |
10000 | }) | |
10001 | ||
10002 | ;; | |
10003 | ;; [vldrwq_gather_base_wb_f] | |
10004 | ;; | |
10005 | (define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn" | |
10006 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
10007 | (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") | |
10008 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
10009 | (mem:BLK (scratch))] | |
10010 | VLDRWQGBWB_F)) | |
10011 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
10012 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
10013 | VLDRWQGBWB_F)) | |
10014 | ] | |
10015 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
10016 | { | |
10017 | rtx ops[3]; | |
10018 | ops[0] = operands[0]; | |
10019 | ops[1] = operands[2]; | |
10020 | ops[2] = operands[3]; | |
10021 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); | |
10022 | return ""; | |
10023 | } | |
10024 | [(set_attr "length" "4")]) | |
10025 | ||
10026 | (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" | |
ff825b81 SP |
10027 | [(match_operand:V4SI 0 "s_register_operand") |
10028 | (match_operand:V4SI 1 "s_register_operand") | |
10029 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10030 | (match_operand:HI 3 "vpr_register_operand") | |
10031 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
10032 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
10033 | { | |
10034 | rtx ignore_result = gen_reg_rtx (V4SFmode); | |
10035 | emit_insn ( | |
10036 | gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0], | |
10037 | operands[1], operands[2], | |
10038 | operands[3])); | |
10039 | DONE; | |
10040 | }) | |
10041 | ||
10042 | (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" | |
41e1a7ff SP |
10043 | [(match_operand:V4SF 0 "s_register_operand") |
10044 | (match_operand:V4SI 1 "s_register_operand") | |
10045 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10046 | (match_operand:HI 3 "vpr_register_operand") | |
10047 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
10048 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
10049 | { | |
10050 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
10051 | emit_insn ( | |
10052 | gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb, | |
10053 | operands[1], operands[2], | |
10054 | operands[3])); | |
10055 | DONE; | |
10056 | }) | |
10057 | ||
10058 | ;; | |
10059 | ;; [vldrwq_gather_base_wb_z_f] | |
10060 | ;; | |
10061 | (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" | |
10062 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
10063 | (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") | |
10064 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
10065 | (match_operand:HI 4 "vpr_register_operand" "Up") | |
10066 | (mem:BLK (scratch))] | |
10067 | VLDRWQGBWB_F)) | |
10068 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
10069 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
10070 | VLDRWQGBWB_F)) | |
10071 | ] | |
10072 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
10073 | { | |
10074 | rtx ops[3]; | |
10075 | ops[0] = operands[0]; | |
10076 | ops[1] = operands[2]; | |
10077 | ops[2] = operands[3]; | |
ff825b81 | 10078 | output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
10079 | return ""; |
10080 | } | |
10081 | [(set_attr "length" "8")]) | |
10082 | ||
10083 | (define_expand "mve_vldrdq_gather_base_wb_<supf>v2di" | |
10084 | [(match_operand:V2DI 0 "s_register_operand") | |
10085 | (match_operand:V2DI 1 "s_register_operand") | |
10086 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10087 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
10088 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
10089 | { |
10090 | rtx ignore_result = gen_reg_rtx (V2DImode); | |
10091 | emit_insn ( | |
10092 | gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0], | |
10093 | operands[1], operands[2])); | |
10094 | DONE; | |
10095 | }) | |
10096 | ||
10097 | (define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di" | |
10098 | [(match_operand:V2DI 0 "s_register_operand") | |
10099 | (match_operand:V2DI 1 "s_register_operand") | |
10100 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10101 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
10102 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
10103 | { |
10104 | rtx ignore_wb = gen_reg_rtx (V2DImode); | |
10105 | emit_insn ( | |
10106 | gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb, | |
10107 | operands[1], operands[2])); | |
10108 | DONE; | |
10109 | }) | |
10110 | ||
ff825b81 | 10111 | |
41e1a7ff SP |
10112 | ;; |
10113 | ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u] | |
10114 | ;; | |
10115 | (define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn" | |
10116 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
10117 | (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") | |
10118 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
10119 | (mem:BLK (scratch))] | |
10120 | VLDRDGBWBQ)) | |
10121 | (set (match_operand:V2DI 1 "s_register_operand" "=&w") | |
10122 | (unspec:V2DI [(match_dup 2) (match_dup 3)] | |
10123 | VLDRDGBWBQ)) | |
10124 | ] | |
10125 | "TARGET_HAVE_MVE" | |
10126 | { | |
10127 | rtx ops[3]; | |
10128 | ops[0] = operands[0]; | |
10129 | ops[1] = operands[2]; | |
10130 | ops[2] = operands[3]; | |
10131 | output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops); | |
10132 | return ""; | |
10133 | } | |
10134 | [(set_attr "length" "4")]) | |
10135 | ||
10136 | (define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di" | |
10137 | [(match_operand:V2DI 0 "s_register_operand") | |
10138 | (match_operand:V2DI 1 "s_register_operand") | |
10139 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10140 | (match_operand:HI 3 "vpr_register_operand") | |
10141 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
10142 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
10143 | { |
10144 | rtx ignore_result = gen_reg_rtx (V2DImode); | |
10145 | emit_insn ( | |
10146 | gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0], | |
10147 | operands[1], operands[2], | |
10148 | operands[3])); | |
10149 | DONE; | |
10150 | }) | |
10151 | ||
10152 | (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di" | |
10153 | [(match_operand:V2DI 0 "s_register_operand") | |
10154 | (match_operand:V2DI 1 "s_register_operand") | |
10155 | (match_operand:SI 2 "mve_vldrd_immediate") | |
10156 | (match_operand:HI 3 "vpr_register_operand") | |
10157 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
10158 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
10159 | { |
10160 | rtx ignore_wb = gen_reg_rtx (V2DImode); | |
10161 | emit_insn ( | |
10162 | gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb, | |
10163 | operands[1], operands[2], | |
10164 | operands[3])); | |
10165 | DONE; | |
10166 | }) | |
10167 | ||
c3562f81 SP |
10168 | (define_insn "get_fpscr_nzcvqc" |
10169 | [(set (match_operand:SI 0 "register_operand" "=r") | |
10170 | (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] | |
10171 | "TARGET_HAVE_MVE" | |
10172 | "vmrs\\t%0, FPSCR_nzcvqc" | |
10173 | [(set_attr "type" "mve_move")]) | |
10174 | ||
10175 | (define_insn "set_fpscr_nzcvqc" | |
10176 | [(set (reg:SI VFPCC_REGNUM) | |
10177 | (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
10178 | VUNSPEC_SET_FPSCR_NZCVQC))] | |
10179 | "TARGET_HAVE_MVE" | |
10180 | "vmsr\\tFPSCR_nzcvqc, %0" | |
10181 | [(set_attr "type" "mve_move")]) | |
10182 | ||
41e1a7ff SP |
10183 | ;; |
10184 | ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] | |
10185 | ;; | |
10186 | (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn" | |
10187 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
10188 | (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") | |
10189 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
10190 | (match_operand:HI 4 "vpr_register_operand" "Up") | |
10191 | (mem:BLK (scratch))] | |
10192 | VLDRDGBWBQ)) | |
10193 | (set (match_operand:V2DI 1 "s_register_operand" "=&w") | |
10194 | (unspec:V2DI [(match_dup 2) (match_dup 3)] | |
10195 | VLDRDGBWBQ)) | |
10196 | ] | |
10197 | "TARGET_HAVE_MVE" | |
10198 | { | |
10199 | rtx ops[3]; | |
10200 | ops[0] = operands[0]; | |
10201 | ops[1] = operands[2]; | |
10202 | ops[2] = operands[3]; | |
ff825b81 | 10203 | output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
10204 | return ""; |
10205 | } | |
10206 | [(set_attr "length" "8")]) | |
c3562f81 SP |
10207 | ;; |
10208 | ;; [vadciq_m_s, vadciq_m_u]) | |
10209 | ;; | |
10210 | (define_insn "mve_vadciq_m_<supf>v4si" | |
10211 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10212 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") | |
10213 | (match_operand:V4SI 2 "s_register_operand" "w") | |
10214 | (match_operand:V4SI 3 "s_register_operand" "w") | |
10215 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
10216 | VADCIQ_M)) | |
10217 | (set (reg:SI VFPCC_REGNUM) | |
10218 | (unspec:SI [(const_int 0)] | |
10219 | VADCIQ_M)) | |
10220 | ] | |
10221 | "TARGET_HAVE_MVE" | |
10222 | "vpst\;vadcit.i32\t%q0, %q2, %q3" | |
10223 | [(set_attr "type" "mve_move") | |
10224 | (set_attr "length" "8")]) | |
10225 | ||
10226 | ;; | |
10227 | ;; [vadciq_u, vadciq_s]) | |
10228 | ;; | |
10229 | (define_insn "mve_vadciq_<supf>v4si" | |
10230 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10231 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10232 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
10233 | VADCIQ)) | |
10234 | (set (reg:SI VFPCC_REGNUM) | |
10235 | (unspec:SI [(const_int 0)] | |
10236 | VADCIQ)) | |
10237 | ] | |
10238 | "TARGET_HAVE_MVE" | |
10239 | "vadci.i32\t%q0, %q1, %q2" | |
10240 | [(set_attr "type" "mve_move") | |
10241 | (set_attr "length" "4")]) | |
10242 | ||
10243 | ;; | |
10244 | ;; [vadcq_m_s, vadcq_m_u]) | |
10245 | ;; | |
10246 | (define_insn "mve_vadcq_m_<supf>v4si" | |
10247 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10248 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") | |
10249 | (match_operand:V4SI 2 "s_register_operand" "w") | |
10250 | (match_operand:V4SI 3 "s_register_operand" "w") | |
10251 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
10252 | VADCQ_M)) | |
10253 | (set (reg:SI VFPCC_REGNUM) | |
10254 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
10255 | VADCQ_M)) | |
10256 | ] | |
10257 | "TARGET_HAVE_MVE" | |
10258 | "vpst\;vadct.i32\t%q0, %q2, %q3" | |
10259 | [(set_attr "type" "mve_move") | |
10260 | (set_attr "length" "8")]) | |
10261 | ||
10262 | ;; | |
10263 | ;; [vadcq_u, vadcq_s]) | |
10264 | ;; | |
10265 | (define_insn "mve_vadcq_<supf>v4si" | |
10266 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10267 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10268 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
10269 | VADCQ)) | |
10270 | (set (reg:SI VFPCC_REGNUM) | |
10271 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
10272 | VADCQ)) | |
10273 | ] | |
10274 | "TARGET_HAVE_MVE" | |
10275 | "vadc.i32\t%q0, %q1, %q2" | |
10276 | [(set_attr "type" "mve_move") | |
10277 | (set_attr "length" "4") | |
10278 | (set_attr "conds" "set")]) | |
10279 | ||
10280 | ;; | |
10281 | ;; [vsbciq_m_u, vsbciq_m_s]) | |
10282 | ;; | |
10283 | (define_insn "mve_vsbciq_m_<supf>v4si" | |
10284 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10285 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10286 | (match_operand:V4SI 2 "s_register_operand" "w") | |
10287 | (match_operand:V4SI 3 "s_register_operand" "w") | |
10288 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
10289 | VSBCIQ_M)) | |
10290 | (set (reg:SI VFPCC_REGNUM) | |
10291 | (unspec:SI [(const_int 0)] | |
10292 | VSBCIQ_M)) | |
10293 | ] | |
10294 | "TARGET_HAVE_MVE" | |
10295 | "vpst\;vsbcit.i32\t%q0, %q2, %q3" | |
10296 | [(set_attr "type" "mve_move") | |
10297 | (set_attr "length" "8")]) | |
10298 | ||
10299 | ;; | |
10300 | ;; [vsbciq_s, vsbciq_u]) | |
10301 | ;; | |
10302 | (define_insn "mve_vsbciq_<supf>v4si" | |
10303 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10304 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10305 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
10306 | VSBCIQ)) | |
10307 | (set (reg:SI VFPCC_REGNUM) | |
10308 | (unspec:SI [(const_int 0)] | |
10309 | VSBCIQ)) | |
10310 | ] | |
10311 | "TARGET_HAVE_MVE" | |
10312 | "vsbci.i32\t%q0, %q1, %q2" | |
10313 | [(set_attr "type" "mve_move") | |
10314 | (set_attr "length" "4")]) | |
10315 | ||
10316 | ;; | |
10317 | ;; [vsbcq_m_u, vsbcq_m_s]) | |
10318 | ;; | |
10319 | (define_insn "mve_vsbcq_m_<supf>v4si" | |
10320 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10321 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10322 | (match_operand:V4SI 2 "s_register_operand" "w") | |
10323 | (match_operand:V4SI 3 "s_register_operand" "w") | |
10324 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
10325 | VSBCQ_M)) | |
10326 | (set (reg:SI VFPCC_REGNUM) | |
10327 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
10328 | VSBCQ_M)) | |
10329 | ] | |
10330 | "TARGET_HAVE_MVE" | |
10331 | "vpst\;vsbct.i32\t%q0, %q2, %q3" | |
10332 | [(set_attr "type" "mve_move") | |
10333 | (set_attr "length" "8")]) | |
10334 | ||
10335 | ;; | |
10336 | ;; [vsbcq_s, vsbcq_u]) | |
10337 | ;; | |
10338 | (define_insn "mve_vsbcq_<supf>v4si" | |
10339 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
10340 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
10341 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
10342 | VSBCQ)) | |
10343 | (set (reg:SI VFPCC_REGNUM) | |
10344 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
10345 | VSBCQ)) | |
10346 | ] | |
10347 | "TARGET_HAVE_MVE" | |
10348 | "vsbc.i32\t%q0, %q1, %q2" | |
10349 | [(set_attr "type" "mve_move") | |
10350 | (set_attr "length" "4")]) | |
1dfcc3b5 SP |
10351 | |
10352 | ;; | |
10353 | ;; [vst2q]) | |
10354 | ;; | |
10355 | (define_insn "mve_vst2q<mode>" | |
10356 | [(set (match_operand:OI 0 "neon_struct_operand" "=Um") | |
10357 | (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") | |
10358 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
10359 | VST2Q)) | |
10360 | ] | |
10361 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10362 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10363 | { | |
10364 | rtx ops[4]; | |
10365 | int regno = REGNO (operands[1]); | |
10366 | ops[0] = gen_rtx_REG (TImode, regno); | |
10367 | ops[1] = gen_rtx_REG (TImode, regno + 4); | |
10368 | rtx reg = operands[0]; | |
10369 | while (reg && !REG_P (reg)) | |
10370 | reg = XEXP (reg, 0); | |
10371 | gcc_assert (REG_P (reg)); | |
10372 | ops[2] = reg; | |
10373 | ops[3] = operands[0]; | |
10374 | output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" | |
10375 | "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops); | |
10376 | return ""; | |
10377 | } | |
10378 | [(set_attr "length" "8")]) | |
10379 | ||
10380 | ;; | |
10381 | ;; [vld2q]) | |
10382 | ;; | |
10383 | (define_insn "mve_vld2q<mode>" | |
10384 | [(set (match_operand:OI 0 "s_register_operand" "=w") | |
10385 | (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") | |
10386 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
10387 | VLD2Q)) | |
10388 | ] | |
10389 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10390 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10391 | { | |
10392 | rtx ops[4]; | |
10393 | int regno = REGNO (operands[0]); | |
10394 | ops[0] = gen_rtx_REG (TImode, regno); | |
10395 | ops[1] = gen_rtx_REG (TImode, regno + 4); | |
10396 | rtx reg = operands[1]; | |
10397 | while (reg && !REG_P (reg)) | |
10398 | reg = XEXP (reg, 0); | |
10399 | gcc_assert (REG_P (reg)); | |
10400 | ops[2] = reg; | |
10401 | ops[3] = operands[1]; | |
10402 | output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" | |
10403 | "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops); | |
10404 | return ""; | |
10405 | } | |
10406 | [(set_attr "length" "8")]) | |
10407 | ||
10408 | ;; | |
10409 | ;; [vld4q]) | |
10410 | ;; | |
10411 | (define_insn "mve_vld4q<mode>" | |
10412 | [(set (match_operand:XI 0 "s_register_operand" "=w") | |
10413 | (unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um") | |
10414 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
10415 | VLD4Q)) | |
10416 | ] | |
10417 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10418 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10419 | { | |
10420 | rtx ops[6]; | |
10421 | int regno = REGNO (operands[0]); | |
10422 | ops[0] = gen_rtx_REG (TImode, regno); | |
10423 | ops[1] = gen_rtx_REG (TImode, regno+4); | |
10424 | ops[2] = gen_rtx_REG (TImode, regno+8); | |
10425 | ops[3] = gen_rtx_REG (TImode, regno + 12); | |
10426 | rtx reg = operands[1]; | |
10427 | while (reg && !REG_P (reg)) | |
10428 | reg = XEXP (reg, 0); | |
10429 | gcc_assert (REG_P (reg)); | |
10430 | ops[4] = reg; | |
10431 | ops[5] = operands[1]; | |
10432 | output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
10433 | "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
10434 | "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
10435 | "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); | |
10436 | return ""; | |
10437 | } | |
10438 | [(set_attr "length" "16")]) | |
1a5c27b1 SP |
10439 | ;; |
10440 | ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f]) | |
10441 | ;; | |
10442 | (define_insn "mve_vec_extract<mode><V_elem_l>" | |
302b6836 | 10443 | [(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=r") |
1a5c27b1 SP |
10444 | (vec_select:<V_elem> |
10445 | (match_operand:MVE_VLD_ST 1 "s_register_operand" "w") | |
10446 | (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | |
10447 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10448 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10449 | { | |
10450 | if (BYTES_BIG_ENDIAN) | |
10451 | { | |
10452 | int elt = INTVAL (operands[2]); | |
10453 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
10454 | operands[2] = GEN_INT (elt); | |
10455 | } | |
10456 | return "vmov.<V_extr_elem>\t%0, %q1[%c2]"; | |
10457 | } | |
10458 | [(set_attr "type" "mve_move")]) | |
10459 | ||
10460 | (define_insn "mve_vec_extractv2didi" | |
302b6836 | 10461 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r") |
1a5c27b1 SP |
10462 | (vec_select:DI |
10463 | (match_operand:V2DI 1 "s_register_operand" "w") | |
10464 | (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | |
10465 | "TARGET_HAVE_MVE" | |
10466 | { | |
10467 | int elt = INTVAL (operands[2]); | |
10468 | if (BYTES_BIG_ENDIAN) | |
10469 | elt = 1 - elt; | |
10470 | ||
10471 | if (elt == 0) | |
10472 | return "vmov\t%Q0, %R0, %e1"; | |
10473 | else | |
302b6836 | 10474 | return "vmov\t%Q0, %R0, %f1"; |
1a5c27b1 SP |
10475 | } |
10476 | [(set_attr "type" "mve_move")]) | |
10477 | ||
10478 | (define_insn "*mve_vec_extract_sext_internal<mode>" | |
10479 | [(set (match_operand:SI 0 "s_register_operand" "=r") | |
10480 | (sign_extend:SI | |
10481 | (vec_select:<V_elem> | |
10482 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
10483 | (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
10484 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10485 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10486 | { | |
10487 | if (BYTES_BIG_ENDIAN) | |
10488 | { | |
10489 | int elt = INTVAL (operands[2]); | |
10490 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
10491 | operands[2] = GEN_INT (elt); | |
10492 | } | |
10493 | return "vmov.s<V_sz_elem>\t%0, %q1[%c2]"; | |
10494 | } | |
10495 | [(set_attr "type" "mve_move")]) | |
10496 | ||
10497 | (define_insn "*mve_vec_extract_zext_internal<mode>" | |
10498 | [(set (match_operand:SI 0 "s_register_operand" "=r") | |
10499 | (zero_extend:SI | |
10500 | (vec_select:<V_elem> | |
10501 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
10502 | (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
10503 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10504 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10505 | { | |
10506 | if (BYTES_BIG_ENDIAN) | |
10507 | { | |
10508 | int elt = INTVAL (operands[2]); | |
10509 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
10510 | operands[2] = GEN_INT (elt); | |
10511 | } | |
10512 | return "vmov.u<V_sz_elem>\t%0, %q1[%c2]"; | |
10513 | } | |
10514 | [(set_attr "type" "mve_move")]) | |
10515 | ||
10516 | ;; | |
10517 | ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f]) | |
10518 | ;; | |
10519 | (define_insn "mve_vec_set<mode>_internal" | |
10520 | [(set (match_operand:VQ2 0 "s_register_operand" "=w") | |
10521 | (vec_merge:VQ2 | |
10522 | (vec_duplicate:VQ2 | |
10523 | (match_operand:<V_elem> 1 "nonimmediate_operand" "r")) | |
10524 | (match_operand:VQ2 3 "s_register_operand" "0") | |
10525 | (match_operand:SI 2 "immediate_operand" "i")))] | |
10526 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
10527 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
10528 | { | |
10529 | int elt = ffs ((int) INTVAL (operands[2])) - 1; | |
10530 | if (BYTES_BIG_ENDIAN) | |
10531 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
10532 | operands[2] = GEN_INT (elt); | |
10533 | ||
10534 | return "vmov.<V_sz_elem>\t%q0[%c2], %1"; | |
10535 | } | |
10536 | [(set_attr "type" "mve_move")]) | |
10537 | ||
10538 | (define_insn "mve_vec_setv2di_internal" | |
10539 | [(set (match_operand:V2DI 0 "s_register_operand" "=w") | |
10540 | (vec_merge:V2DI | |
10541 | (vec_duplicate:V2DI | |
10542 | (match_operand:DI 1 "nonimmediate_operand" "r")) | |
10543 | (match_operand:V2DI 3 "s_register_operand" "0") | |
10544 | (match_operand:SI 2 "immediate_operand" "i")))] | |
10545 | "TARGET_HAVE_MVE" | |
10546 | { | |
10547 | int elt = ffs ((int) INTVAL (operands[2])) - 1; | |
10548 | if (BYTES_BIG_ENDIAN) | |
10549 | elt = 1 - elt; | |
10550 | ||
10551 | if (elt == 0) | |
10552 | return "vmov\t%e0, %Q1, %R1"; | |
10553 | else | |
10554 | return "vmov\t%f0, %J1, %K1"; | |
10555 | } | |
10556 | [(set_attr "type" "mve_move")]) | |
85244449 SP |
10557 | |
10558 | ;; | |
10559 | ;; [uqrshll_di] | |
10560 | ;; | |
10561 | (define_insn "mve_uqrshll_sat<supf>_di" | |
6af59870 SP |
10562 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10563 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
10564 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
10565 | UQRSHLLQ))] |
10566 | "TARGET_HAVE_MVE" | |
10567 | "uqrshll%?\\t%Q1, %R1, #<supf>, %2" | |
10568 | [(set_attr "predicable" "yes")]) | |
10569 | ||
10570 | ;; | |
10571 | ;; [sqrshrl_di] | |
10572 | ;; | |
10573 | (define_insn "mve_sqrshrl_sat<supf>_di" | |
6af59870 SP |
10574 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10575 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
10576 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
10577 | SQRSHRLQ))] |
10578 | "TARGET_HAVE_MVE" | |
10579 | "sqrshrl%?\\t%Q1, %R1, #<supf>, %2" | |
10580 | [(set_attr "predicable" "yes")]) | |
10581 | ||
10582 | ;; | |
10583 | ;; [uqrshl_si] | |
10584 | ;; | |
10585 | (define_insn "mve_uqrshl_si" | |
6af59870 SP |
10586 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10587 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
10588 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
10589 | UQRSHL))] |
10590 | "TARGET_HAVE_MVE" | |
10591 | "uqrshl%?\\t%1, %2" | |
10592 | [(set_attr "predicable" "yes")]) | |
10593 | ||
10594 | ;; | |
10595 | ;; [sqrshr_si] | |
10596 | ;; | |
10597 | (define_insn "mve_sqrshr_si" | |
6af59870 SP |
10598 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10599 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
10600 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
10601 | SQRSHR))] |
10602 | "TARGET_HAVE_MVE" | |
10603 | "sqrshr%?\\t%1, %2" | |
10604 | [(set_attr "predicable" "yes")]) | |
10605 | ||
10606 | ;; | |
10607 | ;; [uqshll_di] | |
10608 | ;; | |
10609 | (define_insn "mve_uqshll_di" | |
6af59870 SP |
10610 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10611 | (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") | |
10612 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
10613 | "TARGET_HAVE_MVE" |
10614 | "uqshll%?\\t%Q1, %R1, %2" | |
10615 | [(set_attr "predicable" "yes")]) | |
10616 | ||
10617 | ;; | |
10618 | ;; [urshrl_di] | |
10619 | ;; | |
10620 | (define_insn "mve_urshrl_di" | |
6af59870 SP |
10621 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10622 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
10623 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
10624 | URSHRL))] |
10625 | "TARGET_HAVE_MVE" | |
10626 | "urshrl%?\\t%Q1, %R1, %2" | |
10627 | [(set_attr "predicable" "yes")]) | |
10628 | ||
10629 | ;; | |
10630 | ;; [uqshl_si] | |
10631 | ;; | |
10632 | (define_insn "mve_uqshl_si" | |
6af59870 SP |
10633 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10634 | (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0") | |
10635 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
10636 | "TARGET_HAVE_MVE" |
10637 | "uqshl%?\\t%1, %2" | |
10638 | [(set_attr "predicable" "yes")]) | |
10639 | ||
10640 | ;; | |
10641 | ;; [urshr_si] | |
10642 | ;; | |
10643 | (define_insn "mve_urshr_si" | |
6af59870 SP |
10644 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10645 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
10646 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
10647 | URSHR))] |
10648 | "TARGET_HAVE_MVE" | |
10649 | "urshr%?\\t%1, %2" | |
10650 | [(set_attr "predicable" "yes")]) | |
10651 | ||
10652 | ;; | |
10653 | ;; [sqshl_si] | |
10654 | ;; | |
10655 | (define_insn "mve_sqshl_si" | |
6af59870 SP |
10656 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10657 | (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0") | |
10658 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
10659 | "TARGET_HAVE_MVE" |
10660 | "sqshl%?\\t%1, %2" | |
10661 | [(set_attr "predicable" "yes")]) | |
10662 | ||
10663 | ;; | |
10664 | ;; [srshr_si] | |
10665 | ;; | |
10666 | (define_insn "mve_srshr_si" | |
6af59870 SP |
10667 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
10668 | (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0") | |
10669 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
10670 | SRSHR))] |
10671 | "TARGET_HAVE_MVE" | |
10672 | "srshr%?\\t%1, %2" | |
10673 | [(set_attr "predicable" "yes")]) | |
10674 | ||
10675 | ;; | |
10676 | ;; [srshrl_di] | |
10677 | ;; | |
10678 | (define_insn "mve_srshrl_di" | |
6af59870 SP |
10679 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10680 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
10681 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
10682 | SRSHRL))] |
10683 | "TARGET_HAVE_MVE" | |
10684 | "srshrl%?\\t%Q1, %R1, %2" | |
10685 | [(set_attr "predicable" "yes")]) | |
10686 | ||
10687 | ;; | |
10688 | ;; [sqshll_di] | |
10689 | ;; | |
10690 | (define_insn "mve_sqshll_di" | |
6af59870 SP |
10691 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
10692 | (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") | |
10693 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
10694 | "TARGET_HAVE_MVE" |
10695 | "sqshll%?\\t%Q1, %R1, %2" | |
10696 | [(set_attr "predicable" "yes")]) | |
88c9a831 SP |
10697 | |
10698 | ;; | |
10699 | ;; [vshlcq_m_u vshlcq_m_s] | |
10700 | ;; | |
10701 | (define_expand "mve_vshlcq_m_vec_<supf><mode>" | |
10702 | [(match_operand:MVE_2 0 "s_register_operand") | |
10703 | (match_operand:MVE_2 1 "s_register_operand") | |
10704 | (match_operand:SI 2 "s_register_operand") | |
10705 | (match_operand:SI 3 "mve_imm_32") | |
10706 | (match_operand:HI 4 "vpr_register_operand") | |
10707 | (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] | |
10708 | "TARGET_HAVE_MVE" | |
10709 | { | |
10710 | rtx ignore_wb = gen_reg_rtx (SImode); | |
10711 | emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1], | |
10712 | operands[2], operands[3], | |
10713 | operands[4])); | |
10714 | DONE; | |
10715 | }) | |
10716 | ||
10717 | (define_expand "mve_vshlcq_m_carry_<supf><mode>" | |
10718 | [(match_operand:SI 0 "s_register_operand") | |
10719 | (match_operand:MVE_2 1 "s_register_operand") | |
10720 | (match_operand:SI 2 "s_register_operand") | |
10721 | (match_operand:SI 3 "mve_imm_32") | |
10722 | (match_operand:HI 4 "vpr_register_operand") | |
10723 | (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] | |
10724 | "TARGET_HAVE_MVE" | |
10725 | { | |
10726 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
10727 | emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0], | |
10728 | operands[1], operands[2], | |
10729 | operands[3], operands[4])); | |
10730 | DONE; | |
10731 | }) | |
10732 | ||
10733 | (define_insn "mve_vshlcq_m_<supf><mode>" | |
10734 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
10735 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") | |
10736 | (match_operand:SI 3 "s_register_operand" "1") | |
10737 | (match_operand:SI 4 "mve_imm_32" "Rf") | |
10738 | (match_operand:HI 5 "vpr_register_operand" "Up")] | |
10739 | VSHLCQ_M)) | |
10740 | (set (match_operand:SI 1 "s_register_operand" "=r") | |
10741 | (unspec:SI [(match_dup 2) | |
10742 | (match_dup 3) | |
10743 | (match_dup 4) | |
10744 | (match_dup 5)] | |
10745 | VSHLCQ_M)) | |
10746 | ] | |
10747 | "TARGET_HAVE_MVE" | |
10748 | "vpst\;vshlct\t%q0, %1, %4" | |
10749 | [(set_attr "type" "mve_move") | |
10750 | (set_attr "length" "8")]) | |
479ccabc AV |
10751 | |
10752 | (define_insn "*mve_vec_duplicate<mode>" | |
10753 | [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") | |
10754 | (vec_duplicate:MVE_VLD_ST (match_operand:<V_elem> 1 "general_operand" "r")))] | |
10755 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
10756 | "vdup.<V_sz_elem>\t%q0, %1" | |
10757 | [(set_attr "type" "mve_move")]) | |
78bf9163 MM |
10758 | |
10759 | ;; CDE instructions on MVE registers. | |
10760 | ||
10761 | (define_insn "arm_vcx1qv16qi" | |
10762 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10763 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10764 | (match_operand:SI 2 "const_int_mve_cde1_operand" "i")] | |
10765 | UNSPEC_VCDE))] | |
10766 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10767 | "vcx1\\tp%c1, %q0, #%c2" | |
10768 | [(set_attr "type" "coproc")] | |
10769 | ) | |
10770 | ||
10771 | (define_insn "arm_vcx1qav16qi" | |
10772 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10773 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10774 | (match_operand:V16QI 2 "register_operand" "0") | |
10775 | (match_operand:SI 3 "const_int_mve_cde1_operand" "i")] | |
10776 | UNSPEC_VCDEA))] | |
10777 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10778 | "vcx1a\\tp%c1, %q0, #%c3" | |
10779 | [(set_attr "type" "coproc")] | |
10780 | ) | |
10781 | ||
10782 | (define_insn "arm_vcx2qv16qi" | |
10783 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10784 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10785 | (match_operand:V16QI 2 "register_operand" "t") | |
10786 | (match_operand:SI 3 "const_int_mve_cde2_operand" "i")] | |
10787 | UNSPEC_VCDE))] | |
10788 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10789 | "vcx2\\tp%c1, %q0, %q2, #%c3" | |
10790 | [(set_attr "type" "coproc")] | |
10791 | ) | |
10792 | ||
10793 | (define_insn "arm_vcx2qav16qi" | |
10794 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10795 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10796 | (match_operand:V16QI 2 "register_operand" "0") | |
10797 | (match_operand:V16QI 3 "register_operand" "t") | |
10798 | (match_operand:SI 4 "const_int_mve_cde2_operand" "i")] | |
10799 | UNSPEC_VCDEA))] | |
10800 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10801 | "vcx2a\\tp%c1, %q0, %q3, #%c4" | |
10802 | [(set_attr "type" "coproc")] | |
10803 | ) | |
10804 | ||
10805 | (define_insn "arm_vcx3qv16qi" | |
10806 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10807 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10808 | (match_operand:V16QI 2 "register_operand" "t") | |
10809 | (match_operand:V16QI 3 "register_operand" "t") | |
10810 | (match_operand:SI 4 "const_int_mve_cde3_operand" "i")] | |
10811 | UNSPEC_VCDE))] | |
10812 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10813 | "vcx3\\tp%c1, %q0, %q2, %q3, #%c4" | |
10814 | [(set_attr "type" "coproc")] | |
10815 | ) | |
10816 | ||
10817 | (define_insn "arm_vcx3qav16qi" | |
10818 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10819 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10820 | (match_operand:V16QI 2 "register_operand" "0") | |
10821 | (match_operand:V16QI 3 "register_operand" "t") | |
10822 | (match_operand:V16QI 4 "register_operand" "t") | |
10823 | (match_operand:SI 5 "const_int_mve_cde3_operand" "i")] | |
10824 | UNSPEC_VCDEA))] | |
10825 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10826 | "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5" | |
10827 | [(set_attr "type" "coproc")] | |
10828 | ) | |
ef684c78 MM |
10829 | |
10830 | (define_insn "arm_vcx1q<a>_p_v16qi" | |
10831 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10832 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10833 | (match_operand:V16QI 2 "register_operand" "0") | |
10834 | (match_operand:SI 3 "const_int_mve_cde1_operand" "i") | |
10835 | (match_operand:HI 4 "vpr_register_operand" "Up")] | |
10836 | CDE_VCX))] | |
10837 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10838 | "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3" | |
10839 | [(set_attr "type" "coproc") | |
10840 | (set_attr "length" "8")] | |
10841 | ) | |
10842 | ||
10843 | (define_insn "arm_vcx2q<a>_p_v16qi" | |
10844 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10845 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10846 | (match_operand:V16QI 2 "register_operand" "0") | |
10847 | (match_operand:V16QI 3 "register_operand" "t") | |
10848 | (match_operand:SI 4 "const_int_mve_cde2_operand" "i") | |
10849 | (match_operand:HI 5 "vpr_register_operand" "Up")] | |
10850 | CDE_VCX))] | |
10851 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10852 | "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4" | |
10853 | [(set_attr "type" "coproc") | |
10854 | (set_attr "length" "8")] | |
10855 | ) | |
10856 | ||
10857 | (define_insn "arm_vcx3q<a>_p_v16qi" | |
10858 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
10859 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
10860 | (match_operand:V16QI 2 "register_operand" "0") | |
10861 | (match_operand:V16QI 3 "register_operand" "t") | |
10862 | (match_operand:V16QI 4 "register_operand" "t") | |
10863 | (match_operand:SI 5 "const_int_mve_cde3_operand" "i") | |
10864 | (match_operand:HI 6 "vpr_register_operand" "Up")] | |
10865 | CDE_VCX))] | |
10866 | "TARGET_CDE && TARGET_HAVE_MVE" | |
10867 | "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5" | |
10868 | [(set_attr "type" "coproc") | |
10869 | (set_attr "length" "8")] | |
10870 | ) |