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[ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from...
[thirdparty/gcc.git] / gcc / config / arm / mve.md
CommitLineData
63c8f7d6
SP		 1;; Arm M-profile Vector Extension Machine Description
2;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful, but
12;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14;; General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
19
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SP		 20(define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
21 (V2DI "u64")])
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SP		 22(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
23(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
a50f6abf 24(define_mode_iterator MVE_0 [V8HF V4SF])
f166a8cd 25(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
6df4618c 26(define_mode_iterator MVE_3 [V16QI V8HI])
5db0eb95
SP		 27(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
28(define_mode_iterator MVE_5 [V8HI V4SI])
bf1e3d5a 29(define_mode_iterator MVE_6 [V8HI V4SI])
14782c81 30
a50f6abf
SP		 31(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
32 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
6df4618c
SP		 33 VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
34 VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
35 VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
36 VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
37 VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
38 VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
39 VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
40 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
4be8cf77
SP		 41 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
42 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
f166a8cd 43 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
d71dba7b 44 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
33203b4c
SP		 45 VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
46 VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
47 VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
48 VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
49 VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
50 VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
51 VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
52 VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
53 VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
54 VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
55 VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
56 VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
57 VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
58 VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
59 VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
60 VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
61 VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
62 VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
63 VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
64 VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
65 VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
66 VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
67 VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
68 VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
69 VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
f9355dee
SP		 70 VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
71 VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
72 VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
73 VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
74 VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
75 VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
76 VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
77 VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
78 VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
79 VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
80 VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
81 VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
82 VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
83 VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
84 VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
85 VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
86 VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
87 VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
88 VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
0dad5b33
SP		 89 VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
90 VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
91 VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
92 VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
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SP		 93 VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
94 VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
95 VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
96 VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
97 VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
98 VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
99 VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
100 VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
101 VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
102 VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
103 VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
104 VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
105 VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
106 VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
107 VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
108 VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
109 VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
110 VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
111 VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
112 VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
113 VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
e3678b44
SP		 114 VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
115 VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
116 VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
117 VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
118 VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
119 VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
120 VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
121 VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
122 VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
123 VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
124 VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
125 VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
126 VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
127 VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
128 VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
129 VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
130 VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
131 VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
132 VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
133 VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
134 VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
135 VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
136 VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
137 VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
138 VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
139 VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
140 VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
141 VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
142 VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
143 VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
db5db9d2
SP		 144 VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
145 VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
146 VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
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SP		 147 VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
148 VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
149 VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
150 VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
151 VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
152 VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
153 VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
154 VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
155 VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
156 VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
157 VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
158 VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
159 VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
160 VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
161 VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
162 VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
163 VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
164 VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
165 VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
166 VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
167 VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
168 VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
169 VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
170 VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
171 VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
172 VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
173 VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
174 VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
175 VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
176 VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
f2170a37
SP		 177 VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
178 VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
179 VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
180 VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
181 VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
182 VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
183 VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
184 VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
185 VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
186 VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
187 VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
188 VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
189 VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
532e9e24
SP		 190 VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
191 VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
192 VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
193 VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
194 VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
4ff68575 195 VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
535a8645 196 VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
bf1e3d5a
SP		 197 VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
198 VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
199 VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
200 VLDRWQ_F VLDRWQ_S VLDRWQ_U])
a50f6abf 201
bf1e3d5a
SP		 202(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
203 (V4SF "V4SI")])
a50f6abf 204
6df4618c
SP		 205(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
206 (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
207 (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
208 (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
209 (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
210 (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
211 (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
212 (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
213 (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
214 (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
215 (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
4be8cf77 216 (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
f166a8cd
SP		 217 (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
218 (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
d71dba7b
SP		 219 (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
220 (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
33203b4c
SP		 221 (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
222 (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
223 (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
224 (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
225 (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
226 (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
227 (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
228 (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
229 (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
230 (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
231 (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
232 (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
233 (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
234 (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
235 (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
236 (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
237 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
238 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
239 (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
240 (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
241 (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
242 (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
243 (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
244 (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
245 (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
246 (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
247 (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
248 (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
249 (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
250 (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
251 (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
252 (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
f9355dee
SP		 253 (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
254 (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
255 (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
256 (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
257 (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
258 (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
259 (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
260 (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
0dad5b33
SP		 261 (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
262 (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
263 (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
264 (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
265 (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
8165795c
SP		 266 (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
267 (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
268 (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
269 (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
270 (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
271 (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
272 (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
273 (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
274 (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
275 (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
276 (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
277 (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
278 (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
279 (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
280 (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
281 (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
282 (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
e3678b44
SP		 283 (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
284 (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
285 (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
286 (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
287 (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
288 (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
289 (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
290 (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
291 (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
292 (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
293 (VREV16Q_M_S "s") (VREV16Q_M_U "u")
294 (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
295 (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
296 (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
297 (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
298 (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
299 (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
300 (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
301 (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
302 (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
303 (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
db5db9d2
SP		 304 (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
305 (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
306 (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
307 (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
8eb3b6b9
SP		 308 (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
309 (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
310 (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
311 (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
312 (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
313 (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
314 (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
315 (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
316 (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
317 (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
318 (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
319 (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
320 (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
321 (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
322 (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
323 (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
324 (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
325 (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
326 (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
327 (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
328 (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
329 (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
330 (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
331 (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
332 (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
333 (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
334 (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
335 (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
336 (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
337 (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
f2170a37
SP		 338 (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
339 (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
340 (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
341 (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
342 (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
343 (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
344 (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
345 (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
346 (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
347 (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
348 (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
349 (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
350 (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
4ff68575
SP		 351 (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
352 (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
535a8645
SP		 353 (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
354 (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
bf1e3d5a
SP		 355 (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
356 (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
357 (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
358 (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
359 (VLDRWQ_U "u")])
5db0eb95 360
a475f153 361(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
f9355dee
SP		 362 (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
363 (VCTP32Q_M "32") (VCTP64Q_M "64")])
f166a8cd
SP		 364(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
365 (V4SI "mve_imm_32")])
366(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
33203b4c 367(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
8165795c
SP		 368(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
369(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
370 (V4SI "mve_imm_31")])
e3678b44
SP		 371(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
372(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
e3678b44
SP		 373(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
374(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
4ff68575 375(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
bf1e3d5a
SP		 376(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
377(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h")
378 (V4SF "w")])
a475f153 379
a50f6abf 380(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
5db0eb95
SP		 381(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
382(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
383(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
6df4618c
SP		 384(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
385(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
386(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
387(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
388(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
389(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
390(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
391(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
392(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
393(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
394(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
395(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
396(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
a475f153 397(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
f9355dee 398(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
4be8cf77 399(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
f166a8cd
SP		 400(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
401(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
402(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
d71dba7b
SP		 403(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
404(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
405(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
33203b4c
SP		 406(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
407(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
408(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
409(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
410(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
411(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
412(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
413(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
414(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
415(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
416(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
417(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
418(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
419(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
420(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
421(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
422(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
423(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
424(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
425(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
426(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
427(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
428(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
429(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
430(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
431(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
432(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
433(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
434(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
435(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
436(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
437(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
438(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
439(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
440(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
441(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
442(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
443(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
444(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
445(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
446(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
447(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
448(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
449(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
450(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
451(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
452(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
f9355dee
SP		 453(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
454(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
455(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
456(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
457(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
458(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
459(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
460(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
461(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
462(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
463(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
464(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
0dad5b33
SP		 465(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
466(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
467(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
468(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
469(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
470(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
471(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
8165795c
SP		 472(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
473(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
474(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
475(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
476(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
477(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
478(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
479(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
480(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
481(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
482(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
483(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
484(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
485(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
486(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
487(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
488(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
489(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
490(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
491(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
492(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
493(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
494(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
495(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
496(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
e3678b44
SP		 497(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
498(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
499(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
500(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
501(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
502(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
503(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
504(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
505(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
506(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
507(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
508(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
509(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
510(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
511(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
512(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
513(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
514(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
515(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
516(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
517(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
518(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
519(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
520(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
521(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
522(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
523(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
524(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
db5db9d2
SP		 525(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
526(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
527(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
528(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
529(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
8eb3b6b9
SP		 530(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
531(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
532(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
533(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
534(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
535(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
536(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
537(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
538(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
539(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
540(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
541(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
542(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
543(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
544(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
545(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
546(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
547(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
548(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
549(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
550(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
551(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
552(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
553(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
554(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
555(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
556(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
557(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
558(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
559(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
560(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
561(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
562(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
563(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
564(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
565(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
566(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
567(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
568(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
569(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
f2170a37
SP		 570(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
571(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
572(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
573(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
574(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
575(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
576(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
577(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
578(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
579(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
580(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
581(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
4ff68575
SP		 582(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
583(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
584(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
535a8645
SP		 585(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
586(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
587(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
bf1e3d5a
SP		 588(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
589(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
590(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
591(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
592(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
63c8f7d6
SP		 593
594(define_insn "*mve_mov<mode>"
595 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
596 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
597 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
598{
599 if (which_alternative == 3 || which_alternative == 6)
600 {
601 int width, is_valid;
602 static char templ[40];
603
604 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
605 &operands[1], &width);
606
607 gcc_assert (is_valid != 0);
608
609 if (width == 0)
610 return "vmov.f32\t%q0, %1 @ <mode>";
611 else
612 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
613 return templ;
614 }
615 switch (which_alternative)
616 {
617 case 0:
618 return "vmov\t%q0, %q1";
619 case 1:
620 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
621 case 2:
622 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
623 case 4:
624 if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
625 || (MEM_P (operands[1])
626 && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
627 return output_move_neon (operands);
628 else
629 return "vldrb.8 %q0, %E1";
630 case 5:
631 return output_move_neon (operands);
632 case 7:
633 return "vstrb.8 %q1, %E0";
634 default:
635 gcc_unreachable ();
636 return "";
637 }
638}
639 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
640 (set_attr "length" "4,8,8,4,8,8,4,4")
641 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
642 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
643
644(define_insn "*mve_mov<mode>"
645 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
646 (vec_duplicate:MVE_types
647 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
648 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
649{
650 if (which_alternative == 0)
651 return "vdup.<V_sz_elem>\t%q0, %1";
652 return "vmov.<V_sz_elem>\t%q0, %1";
653}
654 [(set_attr "length" "4,4")
655 (set_attr "type" "mve_move,mve_move")])
14782c81
SP		 656
657;;
658;; [vst4q])
659;;
660(define_insn "mve_vst4q<mode>"
661 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
662 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
663 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
664 VST4Q))
665 ]
666 "TARGET_HAVE_MVE"
667{
668 rtx ops[6];
669 int regno = REGNO (operands[1]);
670 ops[0] = gen_rtx_REG (TImode, regno);
671 ops[1] = gen_rtx_REG (TImode, regno+4);
672 ops[2] = gen_rtx_REG (TImode, regno+8);
673 ops[3] = gen_rtx_REG (TImode, regno+12);
674 rtx reg = operands[0];
675 while (reg && !REG_P (reg))
676 reg = XEXP (reg, 0);
677 gcc_assert (REG_P (reg));
678 ops[4] = reg;
679 ops[5] = operands[0];
680 /* Here in first three instructions data is stored to ops[4]'s location but
681 in the fourth instruction data is stored to operands[0], this is to
682 support the writeback. */
683 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
684 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
685 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
686 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
687 return "";
688}
689 [(set_attr "length" "16")])
a50f6abf 690
e3678b44
SP		 691;;
692;; [vrndq_m_f])
693;;
694(define_insn "mve_vrndq_m_f<mode>"
695 [
696 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
697 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
698 (match_operand:MVE_0 2 "s_register_operand" "w")
699 (match_operand:HI 3 "vpr_register_operand" "Up")]
700 VRNDQ_M_F))
701 ]
702 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
703 "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
704 [(set_attr "type" "mve_move")
705 (set_attr "length""8")])
706
a50f6abf
SP		 707;;
708;; [vrndxq_f])
709;;
710(define_insn "mve_vrndxq_f<mode>"
711 [
712 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
713 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
714 VRNDXQ_F))
715 ]
716 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
717 "vrintx.f%#<V_sz_elem> %q0, %q1"
718 [(set_attr "type" "mve_move")
719])
720
721;;
722;; [vrndq_f])
723;;
724(define_insn "mve_vrndq_f<mode>"
725 [
726 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
727 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
728 VRNDQ_F))
729 ]
730 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
731 "vrintz.f%#<V_sz_elem> %q0, %q1"
732 [(set_attr "type" "mve_move")
733])
734
735;;
736;; [vrndpq_f])
737;;
738(define_insn "mve_vrndpq_f<mode>"
739 [
740 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
741 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
742 VRNDPQ_F))
743 ]
744 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
745 "vrintp.f%#<V_sz_elem> %q0, %q1"
746 [(set_attr "type" "mve_move")
747])
748
749;;
750;; [vrndnq_f])
751;;
752(define_insn "mve_vrndnq_f<mode>"
753 [
754 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
755 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
756 VRNDNQ_F))
757 ]
758 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
759 "vrintn.f%#<V_sz_elem> %q0, %q1"
760 [(set_attr "type" "mve_move")
761])
762
763;;
764;; [vrndmq_f])
765;;
766(define_insn "mve_vrndmq_f<mode>"
767 [
768 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
769 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
770 VRNDMQ_F))
771 ]
772 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
773 "vrintm.f%#<V_sz_elem> %q0, %q1"
774 [(set_attr "type" "mve_move")
775])
776
777;;
778;; [vrndaq_f])
779;;
780(define_insn "mve_vrndaq_f<mode>"
781 [
782 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
783 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
784 VRNDAQ_F))
785 ]
786 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
787 "vrinta.f%#<V_sz_elem> %q0, %q1"
788 [(set_attr "type" "mve_move")
789])
790
791;;
792;; [vrev64q_f])
793;;
794(define_insn "mve_vrev64q_f<mode>"
795 [
796 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
797 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
798 VREV64Q_F))
799 ]
800 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
801 "vrev64.%#<V_sz_elem> %q0, %q1"
802 [(set_attr "type" "mve_move")
803])
804
805;;
806;; [vnegq_f])
807;;
808(define_insn "mve_vnegq_f<mode>"
809 [
810 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
811 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
812 VNEGQ_F))
813 ]
814 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
815 "vneg.f%#<V_sz_elem> %q0, %q1"
816 [(set_attr "type" "mve_move")
817])
818
819;;
820;; [vdupq_n_f])
821;;
822(define_insn "mve_vdupq_n_f<mode>"
823 [
824 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
825 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
826 VDUPQ_N_F))
827 ]
828 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
829 "vdup.%#<V_sz_elem> %q0, %1"
830 [(set_attr "type" "mve_move")
831])
832
833;;
834;; [vabsq_f])
835;;
836(define_insn "mve_vabsq_f<mode>"
837 [
838 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
839 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
840 VABSQ_F))
841 ]
842 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
843 "vabs.f%#<V_sz_elem> %q0, %q1"
844 [(set_attr "type" "mve_move")
845])
846
847;;
848;; [vrev32q_f])
849;;
850(define_insn "mve_vrev32q_fv8hf"
851 [
852 (set (match_operand:V8HF 0 "s_register_operand" "=w")
853 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
854 VREV32Q_F))
855 ]
856 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
857 "vrev32.16 %q0, %q1"
858 [(set_attr "type" "mve_move")
859])
860;;
861;; [vcvttq_f32_f16])
862;;
863(define_insn "mve_vcvttq_f32_f16v4sf"
864 [
865 (set (match_operand:V4SF 0 "s_register_operand" "=w")
866 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
867 VCVTTQ_F32_F16))
868 ]
869 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
870 "vcvtt.f32.f16 %q0, %q1"
871 [(set_attr "type" "mve_move")
872])
873
874;;
875;; [vcvtbq_f32_f16])
876;;
877(define_insn "mve_vcvtbq_f32_f16v4sf"
878 [
879 (set (match_operand:V4SF 0 "s_register_operand" "=w")
880 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
881 VCVTBQ_F32_F16))
882 ]
883 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
884 "vcvtb.f32.f16 %q0, %q1"
885 [(set_attr "type" "mve_move")
886])
887
888;;
889;; [vcvtq_to_f_s, vcvtq_to_f_u])
890;;
891(define_insn "mve_vcvtq_to_f_<supf><mode>"
892 [
893 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
894 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
895 VCVTQ_TO_F))
896 ]
897 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
898 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
899 [(set_attr "type" "mve_move")
900])
5db0eb95
SP		 901
902;;
903;; [vrev64q_u, vrev64q_s])
904;;
905(define_insn "mve_vrev64q_<supf><mode>"
906 [
907 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
908 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
909 VREV64Q))
910 ]
911 "TARGET_HAVE_MVE"
912 "vrev64.%#<V_sz_elem> %q0, %q1"
913 [(set_attr "type" "mve_move")
914])
915
916;;
917;; [vcvtq_from_f_s, vcvtq_from_f_u])
918;;
919(define_insn "mve_vcvtq_from_f_<supf><mode>"
920 [
921 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
922 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
923 VCVTQ_FROM_F))
924 ]
925 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
926 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
927 [(set_attr "type" "mve_move")
928])
6df4618c
SP		 929;; [vqnegq_s])
930;;
931(define_insn "mve_vqnegq_s<mode>"
932 [
933 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
934 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
935 VQNEGQ_S))
936 ]
937 "TARGET_HAVE_MVE"
938 "vqneg.s%#<V_sz_elem> %q0, %q1"
939 [(set_attr "type" "mve_move")
940])
941
942;;
943;; [vqabsq_s])
944;;
945(define_insn "mve_vqabsq_s<mode>"
946 [
947 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
948 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
949 VQABSQ_S))
950 ]
951 "TARGET_HAVE_MVE"
952 "vqabs.s%#<V_sz_elem> %q0, %q1"
953 [(set_attr "type" "mve_move")
954])
955
956;;
957;; [vnegq_s])
958;;
959(define_insn "mve_vnegq_s<mode>"
960 [
961 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
962 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
963 VNEGQ_S))
964 ]
965 "TARGET_HAVE_MVE"
966 "vneg.s%#<V_sz_elem> %q0, %q1"
967 [(set_attr "type" "mve_move")
968])
969
970;;
971;; [vmvnq_u, vmvnq_s])
972;;
973(define_insn "mve_vmvnq_<supf><mode>"
974 [
975 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
976 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
977 VMVNQ))
978 ]
979 "TARGET_HAVE_MVE"
980 "vmvn %q0, %q1"
981 [(set_attr "type" "mve_move")
982])
983
984;;
985;; [vdupq_n_u, vdupq_n_s])
986;;
987(define_insn "mve_vdupq_n_<supf><mode>"
988 [
989 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
990 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
991 VDUPQ_N))
992 ]
993 "TARGET_HAVE_MVE"
994 "vdup.%#<V_sz_elem> %q0, %1"
995 [(set_attr "type" "mve_move")
996])
997
998;;
999;; [vclzq_u, vclzq_s])
1000;;
1001(define_insn "mve_vclzq_<supf><mode>"
1002 [
1003 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1004 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1005 VCLZQ))
1006 ]
1007 "TARGET_HAVE_MVE"
1008 "vclz.i%#<V_sz_elem> %q0, %q1"
1009 [(set_attr "type" "mve_move")
1010])
1011
1012;;
1013;; [vclsq_s])
1014;;
1015(define_insn "mve_vclsq_s<mode>"
1016 [
1017 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1018 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1019 VCLSQ_S))
1020 ]
1021 "TARGET_HAVE_MVE"
1022 "vcls.s%#<V_sz_elem> %q0, %q1"
1023 [(set_attr "type" "mve_move")
1024])
1025
1026;;
1027;; [vaddvq_s, vaddvq_u])
1028;;
1029(define_insn "mve_vaddvq_<supf><mode>"
1030 [
1031 (set (match_operand:SI 0 "s_register_operand" "=e")
1032 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
1033 VADDVQ))
1034 ]
1035 "TARGET_HAVE_MVE"
1036 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
1037 [(set_attr "type" "mve_move")
1038])
1039
1040;;
1041;; [vabsq_s])
1042;;
1043(define_insn "mve_vabsq_s<mode>"
1044 [
1045 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1046 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
1047 VABSQ_S))
1048 ]
1049 "TARGET_HAVE_MVE"
1050 "vabs.s%#<V_sz_elem>\t%q0, %q1"
1051 [(set_attr "type" "mve_move")
1052])
1053
1054;;
1055;; [vrev32q_u, vrev32q_s])
1056;;
1057(define_insn "mve_vrev32q_<supf><mode>"
1058 [
1059 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
1060 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
1061 VREV32Q))
1062 ]
1063 "TARGET_HAVE_MVE"
1064 "vrev32.%#<V_sz_elem>\t%q0, %q1"
1065 [(set_attr "type" "mve_move")
1066])
1067
1068;;
1069;; [vmovltq_u, vmovltq_s])
1070;;
1071(define_insn "mve_vmovltq_<supf><mode>"
1072 [
1073 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1074 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1075 VMOVLTQ))
1076 ]
1077 "TARGET_HAVE_MVE"
1078 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
1079 [(set_attr "type" "mve_move")
1080])
1081
1082;;
1083;; [vmovlbq_s, vmovlbq_u])
1084;;
1085(define_insn "mve_vmovlbq_<supf><mode>"
1086 [
1087 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1088 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
1089 VMOVLBQ))
1090 ]
1091 "TARGET_HAVE_MVE"
1092 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
1093 [(set_attr "type" "mve_move")
1094])
1095
1096;;
1097;; [vcvtpq_s, vcvtpq_u])
1098;;
1099(define_insn "mve_vcvtpq_<supf><mode>"
1100 [
1101 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1102 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1103 VCVTPQ))
1104 ]
1105 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1106 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1107 [(set_attr "type" "mve_move")
1108])
1109
1110;;
1111;; [vcvtnq_s, vcvtnq_u])
1112;;
1113(define_insn "mve_vcvtnq_<supf><mode>"
1114 [
1115 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1116 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1117 VCVTNQ))
1118 ]
1119 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1120 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1121 [(set_attr "type" "mve_move")
1122])
1123
1124;;
1125;; [vcvtmq_s, vcvtmq_u])
1126;;
1127(define_insn "mve_vcvtmq_<supf><mode>"
1128 [
1129 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1130 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1131 VCVTMQ))
1132 ]
1133 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1134 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1135 [(set_attr "type" "mve_move")
1136])
1137
1138;;
1139;; [vcvtaq_u, vcvtaq_s])
1140;;
1141(define_insn "mve_vcvtaq_<supf><mode>"
1142 [
1143 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1144 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
1145 VCVTAQ))
1146 ]
1147 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1148 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
1149 [(set_attr "type" "mve_move")
1150])
5db0eb95
SP		 1151
1152;;
1153;; [vmvnq_n_u, vmvnq_n_s])
1154;;
1155(define_insn "mve_vmvnq_n_<supf><mode>"
1156 [
1157 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1158 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
1159 VMVNQ_N))
1160 ]
1161 "TARGET_HAVE_MVE"
1162 "vmvn.i%#<V_sz_elem> %q0, %1"
1163 [(set_attr "type" "mve_move")
1164])
6df4618c
SP		 1165
1166;;
1167;; [vrev16q_u, vrev16q_s])
1168;;
1169(define_insn "mve_vrev16q_<supf>v16qi"
1170 [
1171 (set (match_operand:V16QI 0 "s_register_operand" "=w")
1172 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
1173 VREV16Q))
1174 ]
1175 "TARGET_HAVE_MVE"
1176 "vrev16.8 %q0, %q1"
1177 [(set_attr "type" "mve_move")
1178])
1179
1180;;
1181;; [vaddlvq_s vaddlvq_u])
1182;;
1183(define_insn "mve_vaddlvq_<supf>v4si"
1184 [
1185 (set (match_operand:DI 0 "s_register_operand" "=r")
1186 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
1187 VADDLVQ))
1188 ]
1189 "TARGET_HAVE_MVE"
1190 "vaddlv.<supf>32 %Q0, %R0, %q1"
1191 [(set_attr "type" "mve_move")
1192])
a475f153
SP		 1193
1194;;
1195;; [vctp8q vctp16q vctp32q vctp64q])
1196;;
1197(define_insn "mve_vctp<mode1>qhi"
1198 [
1199 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1200 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
1201 VCTPQ))
1202 ]
1203 "TARGET_HAVE_MVE"
1204 "vctp.<mode1> %1"
1205 [(set_attr "type" "mve_move")
1206])
1207
1208;;
1209;; [vpnot])
1210;;
1211(define_insn "mve_vpnothi"
1212 [
1213 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1214 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
1215 VPNOT))
1216 ]
1217 "TARGET_HAVE_MVE"
1218 "vpnot"
1219 [(set_attr "type" "mve_move")
1220])
4be8cf77
SP		 1221
1222;;
1223;; [vsubq_n_f])
1224;;
1225(define_insn "mve_vsubq_n_f<mode>"
1226 [
1227 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1228 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1229 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1230 VSUBQ_N_F))
1231 ]
1232 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1233 "vsub.f<V_sz_elem> %q0, %q1, %2"
1234 [(set_attr "type" "mve_move")
1235])
1236
1237;;
1238;; [vbrsrq_n_f])
1239;;
1240(define_insn "mve_vbrsrq_n_f<mode>"
1241 [
1242 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1243 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1244 (match_operand:SI 2 "s_register_operand" "r")]
1245 VBRSRQ_N_F))
1246 ]
1247 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1248 "vbrsr.<V_sz_elem> %q0, %q1, %2"
1249 [(set_attr "type" "mve_move")
1250])
1251
1252;;
1253;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
1254;;
1255(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
1256 [
1257 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1258 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1259 (match_operand:SI 2 "mve_imm_16" "Rd")]
1260 VCVTQ_N_TO_F))
1261 ]
1262 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1263 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
1264 [(set_attr "type" "mve_move")
1265])
1266
1267;; [vcreateq_f])
1268;;
1269(define_insn "mve_vcreateq_f<mode>"
1270 [
1271 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1272 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
1273 (match_operand:DI 2 "s_register_operand" "r")]
1274 VCREATEQ_F))
1275 ]
1276 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1277 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1278 [(set_attr "type" "mve_move")
1279 (set_attr "length""8")])
f166a8cd
SP		 1280
1281;;
1282;; [vcreateq_u, vcreateq_s])
1283;;
1284(define_insn "mve_vcreateq_<supf><mode>"
1285 [
1286 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1287 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
1288 (match_operand:DI 2 "s_register_operand" "r")]
1289 VCREATEQ))
1290 ]
1291 "TARGET_HAVE_MVE"
1292 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
1293 [(set_attr "type" "mve_move")
1294 (set_attr "length""8")])
1295
1296;;
1297;; [vshrq_n_s, vshrq_n_u])
1298;;
1299(define_insn "mve_vshrq_n_<supf><mode>"
1300 [
1301 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1302 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1303 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
1304 VSHRQ_N))
1305 ]
1306 "TARGET_HAVE_MVE"
1307 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
1308 [(set_attr "type" "mve_move")
1309])
1310
1311;;
1312;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
1313;;
1314(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
1315 [
1316 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1317 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
1318 (match_operand:SI 2 "mve_imm_16" "Rd")]
1319 VCVTQ_N_FROM_F))
1320 ]
1321 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1322 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
1323 [(set_attr "type" "mve_move")
1324])
d71dba7b
SP		 1325
1326;;
1327;; [vaddlvq_p_s])
1328;;
1329(define_insn "mve_vaddlvq_p_<supf>v4si"
1330 [
1331 (set (match_operand:DI 0 "s_register_operand" "=r")
1332 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1333 (match_operand:HI 2 "vpr_register_operand" "Up")]
1334 VADDLVQ_P))
1335 ]
1336 "TARGET_HAVE_MVE"
1337 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
1338 [(set_attr "type" "mve_move")
1339 (set_attr "length""8")])
1340
1341;;
1342;; [vcmpneq_u, vcmpneq_s])
1343;;
1344(define_insn "mve_vcmpneq_<supf><mode>"
1345 [
1346 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1347 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1348 (match_operand:MVE_2 2 "s_register_operand" "w")]
1349 VCMPNEQ))
1350 ]
1351 "TARGET_HAVE_MVE"
1352 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
1353 [(set_attr "type" "mve_move")
1354])
1355
1356;;
1357;; [vshlq_s, vshlq_u])
1358;;
1359(define_insn "mve_vshlq_<supf><mode>"
1360 [
1361 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1362 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1363 (match_operand:MVE_2 2 "s_register_operand" "w")]
1364 VSHLQ))
1365 ]
1366 "TARGET_HAVE_MVE"
1367 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1368 [(set_attr "type" "mve_move")
1369])
33203b4c
SP		 1370
1371;;
1372;; [vabdq_s, vabdq_u])
1373;;
1374(define_insn "mve_vabdq_<supf><mode>"
1375 [
1376 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1377 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1378 (match_operand:MVE_2 2 "s_register_operand" "w")]
1379 VABDQ))
1380 ]
1381 "TARGET_HAVE_MVE"
1382 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
1383 [(set_attr "type" "mve_move")
1384])
1385
1386;;
1387;; [vaddq_n_s, vaddq_n_u])
1388;;
1389(define_insn "mve_vaddq_n_<supf><mode>"
1390 [
1391 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1392 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1393 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1394 VADDQ_N))
1395 ]
1396 "TARGET_HAVE_MVE"
1397 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
1398 [(set_attr "type" "mve_move")
1399])
1400
1401;;
1402;; [vaddvaq_s, vaddvaq_u])
1403;;
1404(define_insn "mve_vaddvaq_<supf><mode>"
1405 [
1406 (set (match_operand:SI 0 "s_register_operand" "=e")
1407 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1408 (match_operand:MVE_2 2 "s_register_operand" "w")]
1409 VADDVAQ))
1410 ]
1411 "TARGET_HAVE_MVE"
1412 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
1413 [(set_attr "type" "mve_move")
1414])
1415
1416;;
1417;; [vaddvq_p_u, vaddvq_p_s])
1418;;
1419(define_insn "mve_vaddvq_p_<supf><mode>"
1420 [
1421 (set (match_operand:SI 0 "s_register_operand" "=e")
1422 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1423 (match_operand:HI 2 "vpr_register_operand" "Up")]
1424 VADDVQ_P))
1425 ]
1426 "TARGET_HAVE_MVE"
1427 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
1428 [(set_attr "type" "mve_move")
1429 (set_attr "length""8")])
1430
1431;;
1432;; [vandq_u, vandq_s])
1433;;
1434(define_insn "mve_vandq_<supf><mode>"
1435 [
1436 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1437 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1438 (match_operand:MVE_2 2 "s_register_operand" "w")]
1439 VANDQ))
1440 ]
1441 "TARGET_HAVE_MVE"
1442 "vand %q0, %q1, %q2"
1443 [(set_attr "type" "mve_move")
1444])
1445
1446;;
1447;; [vbicq_s, vbicq_u])
1448;;
1449(define_insn "mve_vbicq_<supf><mode>"
1450 [
1451 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1452 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1453 (match_operand:MVE_2 2 "s_register_operand" "w")]
1454 VBICQ))
1455 ]
1456 "TARGET_HAVE_MVE"
1457 "vbic %q0, %q1, %q2"
1458 [(set_attr "type" "mve_move")
1459])
1460
1461;;
1462;; [vbrsrq_n_u, vbrsrq_n_s])
1463;;
1464(define_insn "mve_vbrsrq_n_<supf><mode>"
1465 [
1466 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1467 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1468 (match_operand:SI 2 "s_register_operand" "r")]
1469 VBRSRQ_N))
1470 ]
1471 "TARGET_HAVE_MVE"
1472 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
1473 [(set_attr "type" "mve_move")
1474])
1475
1476;;
1477;; [vcaddq_rot270_s, vcaddq_rot270_u])
1478;;
1479(define_insn "mve_vcaddq_rot270_<supf><mode>"
1480 [
1481 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1482 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1483 (match_operand:MVE_2 2 "s_register_operand" "w")]
1484 VCADDQ_ROT270))
1485 ]
1486 "TARGET_HAVE_MVE"
1487 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1488 [(set_attr "type" "mve_move")
1489])
1490
1491;;
1492;; [vcaddq_rot90_u, vcaddq_rot90_s])
1493;;
1494(define_insn "mve_vcaddq_rot90_<supf><mode>"
1495 [
1496 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1497 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1498 (match_operand:MVE_2 2 "s_register_operand" "w")]
1499 VCADDQ_ROT90))
1500 ]
1501 "TARGET_HAVE_MVE"
1502 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1503 [(set_attr "type" "mve_move")
1504])
1505
1506;;
1507;; [vcmpcsq_n_u])
1508;;
1509(define_insn "mve_vcmpcsq_n_u<mode>"
1510 [
1511 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1512 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1513 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1514 VCMPCSQ_N_U))
1515 ]
1516 "TARGET_HAVE_MVE"
1517 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1518 [(set_attr "type" "mve_move")
1519])
1520
1521;;
1522;; [vcmpcsq_u])
1523;;
1524(define_insn "mve_vcmpcsq_u<mode>"
1525 [
1526 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1527 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1528 (match_operand:MVE_2 2 "s_register_operand" "w")]
1529 VCMPCSQ_U))
1530 ]
1531 "TARGET_HAVE_MVE"
1532 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1533 [(set_attr "type" "mve_move")
1534])
1535
1536;;
1537;; [vcmpeqq_n_s, vcmpeqq_n_u])
1538;;
1539(define_insn "mve_vcmpeqq_n_<supf><mode>"
1540 [
1541 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1542 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1543 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1544 VCMPEQQ_N))
1545 ]
1546 "TARGET_HAVE_MVE"
1547 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1548 [(set_attr "type" "mve_move")
1549])
1550
1551;;
1552;; [vcmpeqq_u, vcmpeqq_s])
1553;;
1554(define_insn "mve_vcmpeqq_<supf><mode>"
1555 [
1556 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1557 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1558 (match_operand:MVE_2 2 "s_register_operand" "w")]
1559 VCMPEQQ))
1560 ]
1561 "TARGET_HAVE_MVE"
1562 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1563 [(set_attr "type" "mve_move")
1564])
1565
1566;;
1567;; [vcmpgeq_n_s])
1568;;
1569(define_insn "mve_vcmpgeq_n_s<mode>"
1570 [
1571 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1572 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1573 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1574 VCMPGEQ_N_S))
1575 ]
1576 "TARGET_HAVE_MVE"
1577 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1578 [(set_attr "type" "mve_move")
1579])
1580
1581;;
1582;; [vcmpgeq_s])
1583;;
1584(define_insn "mve_vcmpgeq_s<mode>"
1585 [
1586 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1587 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1588 (match_operand:MVE_2 2 "s_register_operand" "w")]
1589 VCMPGEQ_S))
1590 ]
1591 "TARGET_HAVE_MVE"
1592 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1593 [(set_attr "type" "mve_move")
1594])
1595
1596;;
1597;; [vcmpgtq_n_s])
1598;;
1599(define_insn "mve_vcmpgtq_n_s<mode>"
1600 [
1601 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1602 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1603 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1604 VCMPGTQ_N_S))
1605 ]
1606 "TARGET_HAVE_MVE"
1607 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1608 [(set_attr "type" "mve_move")
1609])
1610
1611;;
1612;; [vcmpgtq_s])
1613;;
1614(define_insn "mve_vcmpgtq_s<mode>"
1615 [
1616 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1617 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1618 (match_operand:MVE_2 2 "s_register_operand" "w")]
1619 VCMPGTQ_S))
1620 ]
1621 "TARGET_HAVE_MVE"
1622 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1623 [(set_attr "type" "mve_move")
1624])
1625
1626;;
1627;; [vcmphiq_n_u])
1628;;
1629(define_insn "mve_vcmphiq_n_u<mode>"
1630 [
1631 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1632 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1633 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1634 VCMPHIQ_N_U))
1635 ]
1636 "TARGET_HAVE_MVE"
1637 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1638 [(set_attr "type" "mve_move")
1639])
1640
1641;;
1642;; [vcmphiq_u])
1643;;
1644(define_insn "mve_vcmphiq_u<mode>"
1645 [
1646 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1647 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1648 (match_operand:MVE_2 2 "s_register_operand" "w")]
1649 VCMPHIQ_U))
1650 ]
1651 "TARGET_HAVE_MVE"
1652 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1653 [(set_attr "type" "mve_move")
1654])
1655
1656;;
1657;; [vcmpleq_n_s])
1658;;
1659(define_insn "mve_vcmpleq_n_s<mode>"
1660 [
1661 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1662 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1663 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1664 VCMPLEQ_N_S))
1665 ]
1666 "TARGET_HAVE_MVE"
1667 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1668 [(set_attr "type" "mve_move")
1669])
1670
1671;;
1672;; [vcmpleq_s])
1673;;
1674(define_insn "mve_vcmpleq_s<mode>"
1675 [
1676 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1677 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1678 (match_operand:MVE_2 2 "s_register_operand" "w")]
1679 VCMPLEQ_S))
1680 ]
1681 "TARGET_HAVE_MVE"
1682 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1683 [(set_attr "type" "mve_move")
1684])
1685
1686;;
1687;; [vcmpltq_n_s])
1688;;
1689(define_insn "mve_vcmpltq_n_s<mode>"
1690 [
1691 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1692 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1693 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1694 VCMPLTQ_N_S))
1695 ]
1696 "TARGET_HAVE_MVE"
1697 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1698 [(set_attr "type" "mve_move")
1699])
1700
1701;;
1702;; [vcmpltq_s])
1703;;
1704(define_insn "mve_vcmpltq_s<mode>"
1705 [
1706 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1707 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1708 (match_operand:MVE_2 2 "s_register_operand" "w")]
1709 VCMPLTQ_S))
1710 ]
1711 "TARGET_HAVE_MVE"
1712 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1713 [(set_attr "type" "mve_move")
1714])
1715
1716;;
1717;; [vcmpneq_n_u, vcmpneq_n_s])
1718;;
1719(define_insn "mve_vcmpneq_n_<supf><mode>"
1720 [
1721 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1722 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1723 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1724 VCMPNEQ_N))
1725 ]
1726 "TARGET_HAVE_MVE"
1727 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1728 [(set_attr "type" "mve_move")
1729])
1730
1731;;
1732;; [veorq_u, veorq_s])
1733;;
1734(define_insn "mve_veorq_<supf><mode>"
1735 [
1736 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1737 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1738 (match_operand:MVE_2 2 "s_register_operand" "w")]
1739 VEORQ))
1740 ]
1741 "TARGET_HAVE_MVE"
1742 "veor %q0, %q1, %q2"
1743 [(set_attr "type" "mve_move")
1744])
1745
1746;;
1747;; [vhaddq_n_u, vhaddq_n_s])
1748;;
1749(define_insn "mve_vhaddq_n_<supf><mode>"
1750 [
1751 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1752 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1753 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1754 VHADDQ_N))
1755 ]
1756 "TARGET_HAVE_MVE"
1757 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1758 [(set_attr "type" "mve_move")
1759])
1760
1761;;
1762;; [vhaddq_s, vhaddq_u])
1763;;
1764(define_insn "mve_vhaddq_<supf><mode>"
1765 [
1766 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1767 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1768 (match_operand:MVE_2 2 "s_register_operand" "w")]
1769 VHADDQ))
1770 ]
1771 "TARGET_HAVE_MVE"
1772 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1773 [(set_attr "type" "mve_move")
1774])
1775
1776;;
1777;; [vhcaddq_rot270_s])
1778;;
1779(define_insn "mve_vhcaddq_rot270_s<mode>"
1780 [
1781 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1782 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1783 (match_operand:MVE_2 2 "s_register_operand" "w")]
1784 VHCADDQ_ROT270_S))
1785 ]
1786 "TARGET_HAVE_MVE"
1787 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1788 [(set_attr "type" "mve_move")
1789])
1790
1791;;
1792;; [vhcaddq_rot90_s])
1793;;
1794(define_insn "mve_vhcaddq_rot90_s<mode>"
1795 [
1796 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1797 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1798 (match_operand:MVE_2 2 "s_register_operand" "w")]
1799 VHCADDQ_ROT90_S))
1800 ]
1801 "TARGET_HAVE_MVE"
1802 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1803 [(set_attr "type" "mve_move")
1804])
1805
1806;;
1807;; [vhsubq_n_u, vhsubq_n_s])
1808;;
1809(define_insn "mve_vhsubq_n_<supf><mode>"
1810 [
1811 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1812 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1813 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1814 VHSUBQ_N))
1815 ]
1816 "TARGET_HAVE_MVE"
1817 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1818 [(set_attr "type" "mve_move")
1819])
1820
1821;;
1822;; [vhsubq_s, vhsubq_u])
1823;;
1824(define_insn "mve_vhsubq_<supf><mode>"
1825 [
1826 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1827 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1828 (match_operand:MVE_2 2 "s_register_operand" "w")]
1829 VHSUBQ))
1830 ]
1831 "TARGET_HAVE_MVE"
1832 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1833 [(set_attr "type" "mve_move")
1834])
1835
1836;;
1837;; [vmaxaq_s])
1838;;
1839(define_insn "mve_vmaxaq_s<mode>"
1840 [
1841 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1842 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1843 (match_operand:MVE_2 2 "s_register_operand" "w")]
1844 VMAXAQ_S))
1845 ]
1846 "TARGET_HAVE_MVE"
1847 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1848 [(set_attr "type" "mve_move")
1849])
1850
1851;;
1852;; [vmaxavq_s])
1853;;
1854(define_insn "mve_vmaxavq_s<mode>"
1855 [
1856 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1857 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1858 (match_operand:MVE_2 2 "s_register_operand" "w")]
1859 VMAXAVQ_S))
1860 ]
1861 "TARGET_HAVE_MVE"
1862 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1863 [(set_attr "type" "mve_move")
1864])
1865
1866;;
1867;; [vmaxq_u, vmaxq_s])
1868;;
1869(define_insn "mve_vmaxq_<supf><mode>"
1870 [
1871 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1872 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1873 (match_operand:MVE_2 2 "s_register_operand" "w")]
1874 VMAXQ))
1875 ]
1876 "TARGET_HAVE_MVE"
1877 "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1878 [(set_attr "type" "mve_move")
1879])
1880
1881;;
1882;; [vmaxvq_u, vmaxvq_s])
1883;;
1884(define_insn "mve_vmaxvq_<supf><mode>"
1885 [
1886 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1887 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1888 (match_operand:MVE_2 2 "s_register_operand" "w")]
1889 VMAXVQ))
1890 ]
1891 "TARGET_HAVE_MVE"
1892 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1893 [(set_attr "type" "mve_move")
1894])
1895
1896;;
1897;; [vminaq_s])
1898;;
1899(define_insn "mve_vminaq_s<mode>"
1900 [
1901 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1902 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1903 (match_operand:MVE_2 2 "s_register_operand" "w")]
1904 VMINAQ_S))
1905 ]
1906 "TARGET_HAVE_MVE"
1907 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1908 [(set_attr "type" "mve_move")
1909])
1910
1911;;
1912;; [vminavq_s])
1913;;
1914(define_insn "mve_vminavq_s<mode>"
1915 [
1916 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1917 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1918 (match_operand:MVE_2 2 "s_register_operand" "w")]
1919 VMINAVQ_S))
1920 ]
1921 "TARGET_HAVE_MVE"
1922 "vminav.s%#<V_sz_elem>\t%0, %q2"
1923 [(set_attr "type" "mve_move")
1924])
1925
1926;;
1927;; [vminq_s, vminq_u])
1928;;
1929(define_insn "mve_vminq_<supf><mode>"
1930 [
1931 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1932 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1933 (match_operand:MVE_2 2 "s_register_operand" "w")]
1934 VMINQ))
1935 ]
1936 "TARGET_HAVE_MVE"
1937 "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1938 [(set_attr "type" "mve_move")
1939])
1940
1941;;
1942;; [vminvq_u, vminvq_s])
1943;;
1944(define_insn "mve_vminvq_<supf><mode>"
1945 [
1946 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1947 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1948 (match_operand:MVE_2 2 "s_register_operand" "w")]
1949 VMINVQ))
1950 ]
1951 "TARGET_HAVE_MVE"
1952 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1953 [(set_attr "type" "mve_move")
1954])
1955
1956;;
1957;; [vmladavq_u, vmladavq_s])
1958;;
1959(define_insn "mve_vmladavq_<supf><mode>"
1960 [
1961 (set (match_operand:SI 0 "s_register_operand" "=e")
1962 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1963 (match_operand:MVE_2 2 "s_register_operand" "w")]
1964 VMLADAVQ))
1965 ]
1966 "TARGET_HAVE_MVE"
1967 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1968 [(set_attr "type" "mve_move")
1969])
1970
1971;;
1972;; [vmladavxq_s])
1973;;
1974(define_insn "mve_vmladavxq_s<mode>"
1975 [
1976 (set (match_operand:SI 0 "s_register_operand" "=e")
1977 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1978 (match_operand:MVE_2 2 "s_register_operand" "w")]
1979 VMLADAVXQ_S))
1980 ]
1981 "TARGET_HAVE_MVE"
1982 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1983 [(set_attr "type" "mve_move")
1984])
1985
1986;;
1987;; [vmlsdavq_s])
1988;;
1989(define_insn "mve_vmlsdavq_s<mode>"
1990 [
1991 (set (match_operand:SI 0 "s_register_operand" "=e")
1992 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1993 (match_operand:MVE_2 2 "s_register_operand" "w")]
1994 VMLSDAVQ_S))
1995 ]
1996 "TARGET_HAVE_MVE"
1997 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
1998 [(set_attr "type" "mve_move")
1999])
2000
2001;;
2002;; [vmlsdavxq_s])
2003;;
2004(define_insn "mve_vmlsdavxq_s<mode>"
2005 [
2006 (set (match_operand:SI 0 "s_register_operand" "=e")
2007 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
2008 (match_operand:MVE_2 2 "s_register_operand" "w")]
2009 VMLSDAVXQ_S))
2010 ]
2011 "TARGET_HAVE_MVE"
2012 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
2013 [(set_attr "type" "mve_move")
2014])
2015
2016;;
2017;; [vmulhq_s, vmulhq_u])
2018;;
2019(define_insn "mve_vmulhq_<supf><mode>"
2020 [
2021 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2022 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2023 (match_operand:MVE_2 2 "s_register_operand" "w")]
2024 VMULHQ))
2025 ]
2026 "TARGET_HAVE_MVE"
2027 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2028 [(set_attr "type" "mve_move")
2029])
2030
2031;;
2032;; [vmullbq_int_u, vmullbq_int_s])
2033;;
2034(define_insn "mve_vmullbq_int_<supf><mode>"
2035 [
2036 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2037 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2038 (match_operand:MVE_2 2 "s_register_operand" "w")]
2039 VMULLBQ_INT))
2040 ]
2041 "TARGET_HAVE_MVE"
2042 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2043 [(set_attr "type" "mve_move")
2044])
2045
2046;;
2047;; [vmulltq_int_u, vmulltq_int_s])
2048;;
2049(define_insn "mve_vmulltq_int_<supf><mode>"
2050 [
2051 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2052 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
2053 (match_operand:MVE_2 2 "s_register_operand" "w")]
2054 VMULLTQ_INT))
2055 ]
2056 "TARGET_HAVE_MVE"
2057 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2058 [(set_attr "type" "mve_move")
2059])
2060
2061;;
2062;; [vmulq_n_u, vmulq_n_s])
2063;;
2064(define_insn "mve_vmulq_n_<supf><mode>"
2065 [
2066 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2067 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2068 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2069 VMULQ_N))
2070 ]
2071 "TARGET_HAVE_MVE"
2072 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
2073 [(set_attr "type" "mve_move")
2074])
2075
2076;;
2077;; [vmulq_u, vmulq_s])
2078;;
2079(define_insn "mve_vmulq_<supf><mode>"
2080 [
2081 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2082 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2083 (match_operand:MVE_2 2 "s_register_operand" "w")]
2084 VMULQ))
2085 ]
2086 "TARGET_HAVE_MVE"
2087 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
2088 [(set_attr "type" "mve_move")
2089])
2090
2091;;
2092;; [vornq_u, vornq_s])
2093;;
2094(define_insn "mve_vornq_<supf><mode>"
2095 [
2096 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2097 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2098 (match_operand:MVE_2 2 "s_register_operand" "w")]
2099 VORNQ))
2100 ]
2101 "TARGET_HAVE_MVE"
2102 "vorn %q0, %q1, %q2"
2103 [(set_attr "type" "mve_move")
2104])
2105
2106;;
2107;; [vorrq_s, vorrq_u])
2108;;
2109(define_insn "mve_vorrq_<supf><mode>"
2110 [
2111 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2112 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2113 (match_operand:MVE_2 2 "s_register_operand" "w")]
2114 VORRQ))
2115 ]
2116 "TARGET_HAVE_MVE"
2117 "vorr %q0, %q1, %q2"
2118 [(set_attr "type" "mve_move")
2119])
2120
2121;;
2122;; [vqaddq_n_s, vqaddq_n_u])
2123;;
2124(define_insn "mve_vqaddq_n_<supf><mode>"
2125 [
2126 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2127 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2128 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2129 VQADDQ_N))
2130 ]
2131 "TARGET_HAVE_MVE"
2132 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2133 [(set_attr "type" "mve_move")
2134])
2135
2136;;
2137;; [vqaddq_u, vqaddq_s])
2138;;
2139(define_insn "mve_vqaddq_<supf><mode>"
2140 [
2141 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2142 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2143 (match_operand:MVE_2 2 "s_register_operand" "w")]
2144 VQADDQ))
2145 ]
2146 "TARGET_HAVE_MVE"
2147 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2148 [(set_attr "type" "mve_move")
2149])
2150
2151;;
2152;; [vqdmulhq_n_s])
2153;;
2154(define_insn "mve_vqdmulhq_n_s<mode>"
2155 [
2156 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2157 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2158 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2159 VQDMULHQ_N_S))
2160 ]
2161 "TARGET_HAVE_MVE"
2162 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2163 [(set_attr "type" "mve_move")
2164])
2165
2166;;
2167;; [vqdmulhq_s])
2168;;
2169(define_insn "mve_vqdmulhq_s<mode>"
2170 [
2171 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2172 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2173 (match_operand:MVE_2 2 "s_register_operand" "w")]
2174 VQDMULHQ_S))
2175 ]
2176 "TARGET_HAVE_MVE"
2177 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2178 [(set_attr "type" "mve_move")
2179])
2180
2181;;
2182;; [vqrdmulhq_n_s])
2183;;
2184(define_insn "mve_vqrdmulhq_n_s<mode>"
2185 [
2186 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2187 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2188 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2189 VQRDMULHQ_N_S))
2190 ]
2191 "TARGET_HAVE_MVE"
2192 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
2193 [(set_attr "type" "mve_move")
2194])
2195
2196;;
2197;; [vqrdmulhq_s])
2198;;
2199(define_insn "mve_vqrdmulhq_s<mode>"
2200 [
2201 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2202 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2203 (match_operand:MVE_2 2 "s_register_operand" "w")]
2204 VQRDMULHQ_S))
2205 ]
2206 "TARGET_HAVE_MVE"
2207 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
2208 [(set_attr "type" "mve_move")
2209])
2210
2211;;
2212;; [vqrshlq_n_s, vqrshlq_n_u])
2213;;
2214(define_insn "mve_vqrshlq_n_<supf><mode>"
2215 [
2216 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2217 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2218 (match_operand:SI 2 "s_register_operand" "r")]
2219 VQRSHLQ_N))
2220 ]
2221 "TARGET_HAVE_MVE"
2222 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2223 [(set_attr "type" "mve_move")
2224])
2225
2226;;
2227;; [vqrshlq_s, vqrshlq_u])
2228;;
2229(define_insn "mve_vqrshlq_<supf><mode>"
2230 [
2231 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2232 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2233 (match_operand:MVE_2 2 "s_register_operand" "w")]
2234 VQRSHLQ))
2235 ]
2236 "TARGET_HAVE_MVE"
2237 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2238 [(set_attr "type" "mve_move")
2239])
2240
2241;;
2242;; [vqshlq_n_s, vqshlq_n_u])
2243;;
2244(define_insn "mve_vqshlq_n_<supf><mode>"
2245 [
2246 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2247 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2248 (match_operand:SI 2 "immediate_operand" "i")]
2249 VQSHLQ_N))
2250 ]
2251 "TARGET_HAVE_MVE"
2252 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2253 [(set_attr "type" "mve_move")
2254])
2255
2256;;
2257;; [vqshlq_r_u, vqshlq_r_s])
2258;;
2259(define_insn "mve_vqshlq_r_<supf><mode>"
2260 [
2261 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2263 (match_operand:SI 2 "s_register_operand" "r")]
2264 VQSHLQ_R))
2265 ]
2266 "TARGET_HAVE_MVE"
2267 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
2268 [(set_attr "type" "mve_move")
2269])
2270
2271;;
2272;; [vqshlq_s, vqshlq_u])
2273;;
2274(define_insn "mve_vqshlq_<supf><mode>"
2275 [
2276 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2277 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2278 (match_operand:MVE_2 2 "s_register_operand" "w")]
2279 VQSHLQ))
2280 ]
2281 "TARGET_HAVE_MVE"
2282 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2283 [(set_attr "type" "mve_move")
2284])
2285
2286;;
2287;; [vqshluq_n_s])
2288;;
2289(define_insn "mve_vqshluq_n_s<mode>"
2290 [
2291 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2292 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2293 (match_operand:SI 2 "mve_imm_7" "Ra")]
2294 VQSHLUQ_N_S))
2295 ]
2296 "TARGET_HAVE_MVE"
2297 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
2298 [(set_attr "type" "mve_move")
2299])
2300
2301;;
2302;; [vqsubq_n_s, vqsubq_n_u])
2303;;
2304(define_insn "mve_vqsubq_n_<supf><mode>"
2305 [
2306 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2307 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2308 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2309 VQSUBQ_N))
2310 ]
2311 "TARGET_HAVE_MVE"
2312 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2313 [(set_attr "type" "mve_move")
2314])
2315
2316;;
2317;; [vqsubq_u, vqsubq_s])
2318;;
2319(define_insn "mve_vqsubq_<supf><mode>"
2320 [
2321 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2322 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2323 (match_operand:MVE_2 2 "s_register_operand" "w")]
2324 VQSUBQ))
2325 ]
2326 "TARGET_HAVE_MVE"
2327 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2328 [(set_attr "type" "mve_move")
2329])
2330
2331;;
2332;; [vrhaddq_s, vrhaddq_u])
2333;;
2334(define_insn "mve_vrhaddq_<supf><mode>"
2335 [
2336 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2337 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2338 (match_operand:MVE_2 2 "s_register_operand" "w")]
2339 VRHADDQ))
2340 ]
2341 "TARGET_HAVE_MVE"
2342 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2343 [(set_attr "type" "mve_move")
2344])
2345
2346;;
2347;; [vrmulhq_s, vrmulhq_u])
2348;;
2349(define_insn "mve_vrmulhq_<supf><mode>"
2350 [
2351 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2352 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2353 (match_operand:MVE_2 2 "s_register_operand" "w")]
2354 VRMULHQ))
2355 ]
2356 "TARGET_HAVE_MVE"
2357 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2358 [(set_attr "type" "mve_move")
2359])
2360
2361;;
2362;; [vrshlq_n_u, vrshlq_n_s])
2363;;
2364(define_insn "mve_vrshlq_n_<supf><mode>"
2365 [
2366 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2367 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2368 (match_operand:SI 2 "s_register_operand" "r")]
2369 VRSHLQ_N))
2370 ]
2371 "TARGET_HAVE_MVE"
2372 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2373 [(set_attr "type" "mve_move")
2374])
2375
2376;;
2377;; [vrshlq_s, vrshlq_u])
2378;;
2379(define_insn "mve_vrshlq_<supf><mode>"
2380 [
2381 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2382 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2383 (match_operand:MVE_2 2 "s_register_operand" "w")]
2384 VRSHLQ))
2385 ]
2386 "TARGET_HAVE_MVE"
2387 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2388 [(set_attr "type" "mve_move")
2389])
2390
2391;;
2392;; [vrshrq_n_s, vrshrq_n_u])
2393;;
2394(define_insn "mve_vrshrq_n_<supf><mode>"
2395 [
2396 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2397 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2398 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2399 VRSHRQ_N))
2400 ]
2401 "TARGET_HAVE_MVE"
2402 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2403 [(set_attr "type" "mve_move")
2404])
2405
2406;;
2407;; [vshlq_n_u, vshlq_n_s])
2408;;
2409(define_insn "mve_vshlq_n_<supf><mode>"
2410 [
2411 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2412 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2413 (match_operand:SI 2 "immediate_operand" "i")]
2414 VSHLQ_N))
2415 ]
2416 "TARGET_HAVE_MVE"
2417 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2418 [(set_attr "type" "mve_move")
2419])
2420
2421;;
2422;; [vshlq_r_s, vshlq_r_u])
2423;;
2424(define_insn "mve_vshlq_r_<supf><mode>"
2425 [
2426 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2427 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2428 (match_operand:SI 2 "s_register_operand" "r")]
2429 VSHLQ_R))
2430 ]
2431 "TARGET_HAVE_MVE"
2432 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2433 [(set_attr "type" "mve_move")
2434])
2435
2436;;
2437;; [vsubq_n_s, vsubq_n_u])
2438;;
2439(define_insn "mve_vsubq_n_<supf><mode>"
2440 [
2441 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2442 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2443 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2444 VSUBQ_N))
2445 ]
2446 "TARGET_HAVE_MVE"
2447 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2448 [(set_attr "type" "mve_move")
2449])
2450
2451;;
2452;; [vsubq_s, vsubq_u])
2453;;
2454(define_insn "mve_vsubq_<supf><mode>"
2455 [
2456 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2457 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2458 (match_operand:MVE_2 2 "s_register_operand" "w")]
2459 VSUBQ))
2460 ]
2461 "TARGET_HAVE_MVE"
2462 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2463 [(set_attr "type" "mve_move")
2464])
f9355dee
SP		 2465
2466;;
2467;; [vabdq_f])
2468;;
2469(define_insn "mve_vabdq_f<mode>"
2470 [
2471 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2472 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2473 (match_operand:MVE_0 2 "s_register_operand" "w")]
2474 VABDQ_F))
2475 ]
2476 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2477 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2478 [(set_attr "type" "mve_move")
2479])
2480
2481;;
2482;; [vaddlvaq_s vaddlvaq_u])
2483;;
2484(define_insn "mve_vaddlvaq_<supf>v4si"
2485 [
2486 (set (match_operand:DI 0 "s_register_operand" "=r")
2487 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2488 (match_operand:V4SI 2 "s_register_operand" "w")]
2489 VADDLVAQ))
2490 ]
2491 "TARGET_HAVE_MVE"
2492 "vaddlva.<supf>32 %Q0, %R0, %q2"
2493 [(set_attr "type" "mve_move")
2494])
2495
2496;;
2497;; [vaddq_n_f])
2498;;
2499(define_insn "mve_vaddq_n_f<mode>"
2500 [
2501 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2502 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2503 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2504 VADDQ_N_F))
2505 ]
2506 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2507 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2508 [(set_attr "type" "mve_move")
2509])
2510
2511;;
2512;; [vandq_f])
2513;;
2514(define_insn "mve_vandq_f<mode>"
2515 [
2516 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2517 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2518 (match_operand:MVE_0 2 "s_register_operand" "w")]
2519 VANDQ_F))
2520 ]
2521 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2522 "vand %q0, %q1, %q2"
2523 [(set_attr "type" "mve_move")
2524])
2525
2526;;
2527;; [vbicq_f])
2528;;
2529(define_insn "mve_vbicq_f<mode>"
2530 [
2531 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2532 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2533 (match_operand:MVE_0 2 "s_register_operand" "w")]
2534 VBICQ_F))
2535 ]
2536 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2537 "vbic %q0, %q1, %q2"
2538 [(set_attr "type" "mve_move")
2539])
2540
2541;;
2542;; [vbicq_n_s, vbicq_n_u])
2543;;
2544(define_insn "mve_vbicq_n_<supf><mode>"
2545 [
2546 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2547 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2548 (match_operand:SI 2 "immediate_operand" "i")]
2549 VBICQ_N))
2550 ]
2551 "TARGET_HAVE_MVE"
2552 "vbic.i%#<V_sz_elem> %q0, %2"
2553 [(set_attr "type" "mve_move")
2554])
2555
2556;;
2557;; [vcaddq_rot270_f])
2558;;
2559(define_insn "mve_vcaddq_rot270_f<mode>"
2560 [
2561 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2562 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2563 (match_operand:MVE_0 2 "s_register_operand" "w")]
2564 VCADDQ_ROT270_F))
2565 ]
2566 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2567 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2568 [(set_attr "type" "mve_move")
2569])
2570
2571;;
2572;; [vcaddq_rot90_f])
2573;;
2574(define_insn "mve_vcaddq_rot90_f<mode>"
2575 [
2576 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2577 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2578 (match_operand:MVE_0 2 "s_register_operand" "w")]
2579 VCADDQ_ROT90_F))
2580 ]
2581 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2582 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2583 [(set_attr "type" "mve_move")
2584])
2585
2586;;
2587;; [vcmpeqq_f])
2588;;
2589(define_insn "mve_vcmpeqq_f<mode>"
2590 [
2591 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2592 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2593 (match_operand:MVE_0 2 "s_register_operand" "w")]
2594 VCMPEQQ_F))
2595 ]
2596 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2597 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2598 [(set_attr "type" "mve_move")
2599])
2600
2601;;
2602;; [vcmpeqq_n_f])
2603;;
2604(define_insn "mve_vcmpeqq_n_f<mode>"
2605 [
2606 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2607 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2608 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2609 VCMPEQQ_N_F))
2610 ]
2611 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2612 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2613 [(set_attr "type" "mve_move")
2614])
2615
2616;;
2617;; [vcmpgeq_f])
2618;;
2619(define_insn "mve_vcmpgeq_f<mode>"
2620 [
2621 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2622 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2623 (match_operand:MVE_0 2 "s_register_operand" "w")]
2624 VCMPGEQ_F))
2625 ]
2626 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2627 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2628 [(set_attr "type" "mve_move")
2629])
2630
2631;;
2632;; [vcmpgeq_n_f])
2633;;
2634(define_insn "mve_vcmpgeq_n_f<mode>"
2635 [
2636 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2637 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2638 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2639 VCMPGEQ_N_F))
2640 ]
2641 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2642 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2643 [(set_attr "type" "mve_move")
2644])
2645
2646;;
2647;; [vcmpgtq_f])
2648;;
2649(define_insn "mve_vcmpgtq_f<mode>"
2650 [
2651 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2652 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2653 (match_operand:MVE_0 2 "s_register_operand" "w")]
2654 VCMPGTQ_F))
2655 ]
2656 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2657 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2658 [(set_attr "type" "mve_move")
2659])
2660
2661;;
2662;; [vcmpgtq_n_f])
2663;;
2664(define_insn "mve_vcmpgtq_n_f<mode>"
2665 [
2666 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2667 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2668 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2669 VCMPGTQ_N_F))
2670 ]
2671 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2672 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2673 [(set_attr "type" "mve_move")
2674])
2675
2676;;
2677;; [vcmpleq_f])
2678;;
2679(define_insn "mve_vcmpleq_f<mode>"
2680 [
2681 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2682 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2683 (match_operand:MVE_0 2 "s_register_operand" "w")]
2684 VCMPLEQ_F))
2685 ]
2686 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2687 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2688 [(set_attr "type" "mve_move")
2689])
2690
2691;;
2692;; [vcmpleq_n_f])
2693;;
2694(define_insn "mve_vcmpleq_n_f<mode>"
2695 [
2696 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2697 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2698 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2699 VCMPLEQ_N_F))
2700 ]
2701 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2702 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2703 [(set_attr "type" "mve_move")
2704])
2705
2706;;
2707;; [vcmpltq_f])
2708;;
2709(define_insn "mve_vcmpltq_f<mode>"
2710 [
2711 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2712 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2713 (match_operand:MVE_0 2 "s_register_operand" "w")]
2714 VCMPLTQ_F))
2715 ]
2716 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2717 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2718 [(set_attr "type" "mve_move")
2719])
2720
2721;;
2722;; [vcmpltq_n_f])
2723;;
2724(define_insn "mve_vcmpltq_n_f<mode>"
2725 [
2726 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2727 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2728 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2729 VCMPLTQ_N_F))
2730 ]
2731 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2732 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2733 [(set_attr "type" "mve_move")
2734])
2735
2736;;
2737;; [vcmpneq_f])
2738;;
2739(define_insn "mve_vcmpneq_f<mode>"
2740 [
2741 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2742 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2743 (match_operand:MVE_0 2 "s_register_operand" "w")]
2744 VCMPNEQ_F))
2745 ]
2746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2747 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2748 [(set_attr "type" "mve_move")
2749])
2750
2751;;
2752;; [vcmpneq_n_f])
2753;;
2754(define_insn "mve_vcmpneq_n_f<mode>"
2755 [
2756 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2757 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2758 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2759 VCMPNEQ_N_F))
2760 ]
2761 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2762 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2763 [(set_attr "type" "mve_move")
2764])
2765
2766;;
2767;; [vcmulq_f])
2768;;
2769(define_insn "mve_vcmulq_f<mode>"
2770 [
2771 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2772 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2773 (match_operand:MVE_0 2 "s_register_operand" "w")]
2774 VCMULQ_F))
2775 ]
2776 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2777 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2778 [(set_attr "type" "mve_move")
2779])
2780
2781;;
2782;; [vcmulq_rot180_f])
2783;;
2784(define_insn "mve_vcmulq_rot180_f<mode>"
2785 [
2786 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2787 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2788 (match_operand:MVE_0 2 "s_register_operand" "w")]
2789 VCMULQ_ROT180_F))
2790 ]
2791 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2792 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2793 [(set_attr "type" "mve_move")
2794])
2795
2796;;
2797;; [vcmulq_rot270_f])
2798;;
2799(define_insn "mve_vcmulq_rot270_f<mode>"
2800 [
2801 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2802 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2803 (match_operand:MVE_0 2 "s_register_operand" "w")]
2804 VCMULQ_ROT270_F))
2805 ]
2806 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2807 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2808 [(set_attr "type" "mve_move")
2809])
2810
2811;;
2812;; [vcmulq_rot90_f])
2813;;
2814(define_insn "mve_vcmulq_rot90_f<mode>"
2815 [
2816 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2817 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2818 (match_operand:MVE_0 2 "s_register_operand" "w")]
2819 VCMULQ_ROT90_F))
2820 ]
2821 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2822 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2823 [(set_attr "type" "mve_move")
2824])
2825
2826;;
2827;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2828;;
2829(define_insn "mve_vctp<mode1>q_mhi"
2830 [
2831 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2832 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2833 (match_operand:HI 2 "vpr_register_operand" "Up")]
2834 VCTPQ_M))
2835 ]
2836 "TARGET_HAVE_MVE"
2837 "vpst\;vctpt.<mode1> %1"
2838 [(set_attr "type" "mve_move")
2839 (set_attr "length""8")])
2840
2841;;
2842;; [vcvtbq_f16_f32])
2843;;
2844(define_insn "mve_vcvtbq_f16_f32v8hf"
2845 [
2846 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2847 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2848 (match_operand:V4SF 2 "s_register_operand" "w")]
2849 VCVTBQ_F16_F32))
2850 ]
2851 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2852 "vcvtb.f16.f32 %q0, %q2"
2853 [(set_attr "type" "mve_move")
2854])
2855
2856;;
2857;; [vcvttq_f16_f32])
2858;;
2859(define_insn "mve_vcvttq_f16_f32v8hf"
2860 [
2861 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2862 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2863 (match_operand:V4SF 2 "s_register_operand" "w")]
2864 VCVTTQ_F16_F32))
2865 ]
2866 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2867 "vcvtt.f16.f32 %q0, %q2"
2868 [(set_attr "type" "mve_move")
2869])
2870
2871;;
2872;; [veorq_f])
2873;;
2874(define_insn "mve_veorq_f<mode>"
2875 [
2876 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2877 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2878 (match_operand:MVE_0 2 "s_register_operand" "w")]
2879 VEORQ_F))
2880 ]
2881 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2882 "veor %q0, %q1, %q2"
2883 [(set_attr "type" "mve_move")
2884])
2885
2886;;
2887;; [vmaxnmaq_f])
2888;;
2889(define_insn "mve_vmaxnmaq_f<mode>"
2890 [
2891 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2892 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2893 (match_operand:MVE_0 2 "s_register_operand" "w")]
2894 VMAXNMAQ_F))
2895 ]
2896 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2897 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2898 [(set_attr "type" "mve_move")
2899])
2900
2901;;
2902;; [vmaxnmavq_f])
2903;;
2904(define_insn "mve_vmaxnmavq_f<mode>"
2905 [
2906 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2907 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2908 (match_operand:MVE_0 2 "s_register_operand" "w")]
2909 VMAXNMAVQ_F))
2910 ]
2911 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2912 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2913 [(set_attr "type" "mve_move")
2914])
2915
2916;;
2917;; [vmaxnmq_f])
2918;;
2919(define_insn "mve_vmaxnmq_f<mode>"
2920 [
2921 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2922 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2923 (match_operand:MVE_0 2 "s_register_operand" "w")]
2924 VMAXNMQ_F))
2925 ]
2926 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2927 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
2928 [(set_attr "type" "mve_move")
2929])
2930
2931;;
2932;; [vmaxnmvq_f])
2933;;
2934(define_insn "mve_vmaxnmvq_f<mode>"
2935 [
2936 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2937 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2938 (match_operand:MVE_0 2 "s_register_operand" "w")]
2939 VMAXNMVQ_F))
2940 ]
2941 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2942 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
2943 [(set_attr "type" "mve_move")
2944])
2945
2946;;
2947;; [vminnmaq_f])
2948;;
2949(define_insn "mve_vminnmaq_f<mode>"
2950 [
2951 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2952 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2953 (match_operand:MVE_0 2 "s_register_operand" "w")]
2954 VMINNMAQ_F))
2955 ]
2956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2957 "vminnma.f%#<V_sz_elem> %q0, %q2"
2958 [(set_attr "type" "mve_move")
2959])
2960
2961;;
2962;; [vminnmavq_f])
2963;;
2964(define_insn "mve_vminnmavq_f<mode>"
2965 [
2966 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2967 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2968 (match_operand:MVE_0 2 "s_register_operand" "w")]
2969 VMINNMAVQ_F))
2970 ]
2971 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2972 "vminnmav.f%#<V_sz_elem> %0, %q2"
2973 [(set_attr "type" "mve_move")
2974])
2975
2976;;
2977;; [vminnmq_f])
2978;;
2979(define_insn "mve_vminnmq_f<mode>"
2980 [
2981 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2982 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2983 (match_operand:MVE_0 2 "s_register_operand" "w")]
2984 VMINNMQ_F))
2985 ]
2986 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2987 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
2988 [(set_attr "type" "mve_move")
2989])
2990
2991;;
2992;; [vminnmvq_f])
2993;;
2994(define_insn "mve_vminnmvq_f<mode>"
2995 [
2996 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2997 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2998 (match_operand:MVE_0 2 "s_register_operand" "w")]
2999 VMINNMVQ_F))
3000 ]
3001 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3002 "vminnmv.f%#<V_sz_elem> %0, %q2"
3003 [(set_attr "type" "mve_move")
3004])
3005
3006;;
3007;; [vmlaldavq_u, vmlaldavq_s])
3008;;
3009(define_insn "mve_vmlaldavq_<supf><mode>"
3010 [
3011 (set (match_operand:DI 0 "s_register_operand" "=r")
3012 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3013 (match_operand:MVE_5 2 "s_register_operand" "w")]
3014 VMLALDAVQ))
3015 ]
3016 "TARGET_HAVE_MVE"
3017 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3018 [(set_attr "type" "mve_move")
3019])
3020
3021;;
3022;; [vmlaldavxq_s])
3023;;
3024(define_insn "mve_vmlaldavxq_s<mode>"
3025 [
3026 (set (match_operand:DI 0 "s_register_operand" "=r")
3027 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3028 (match_operand:MVE_5 2 "s_register_operand" "w")]
3029 VMLALDAVXQ_S))
3030 ]
3031 "TARGET_HAVE_MVE"
3032 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3033 [(set_attr "type" "mve_move")
3034])
3035
3036;;
3037;; [vmlsldavq_s])
3038;;
3039(define_insn "mve_vmlsldavq_s<mode>"
3040 [
3041 (set (match_operand:DI 0 "s_register_operand" "=r")
3042 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3043 (match_operand:MVE_5 2 "s_register_operand" "w")]
3044 VMLSLDAVQ_S))
3045 ]
3046 "TARGET_HAVE_MVE"
3047 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3048 [(set_attr "type" "mve_move")
3049])
3050
3051;;
3052;; [vmlsldavxq_s])
3053;;
3054(define_insn "mve_vmlsldavxq_s<mode>"
3055 [
3056 (set (match_operand:DI 0 "s_register_operand" "=r")
3057 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
3058 (match_operand:MVE_5 2 "s_register_operand" "w")]
3059 VMLSLDAVXQ_S))
3060 ]
3061 "TARGET_HAVE_MVE"
3062 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
3063 [(set_attr "type" "mve_move")
3064])
3065
3066;;
3067;; [vmovnbq_u, vmovnbq_s])
3068;;
3069(define_insn "mve_vmovnbq_<supf><mode>"
3070 [
3071 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3072 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3073 (match_operand:MVE_5 2 "s_register_operand" "w")]
3074 VMOVNBQ))
3075 ]
3076 "TARGET_HAVE_MVE"
3077 "vmovnb.i%#<V_sz_elem> %q0, %q2"
3078 [(set_attr "type" "mve_move")
3079])
3080
3081;;
3082;; [vmovntq_s, vmovntq_u])
3083;;
3084(define_insn "mve_vmovntq_<supf><mode>"
3085 [
3086 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3087 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3088 (match_operand:MVE_5 2 "s_register_operand" "w")]
3089 VMOVNTQ))
3090 ]
3091 "TARGET_HAVE_MVE"
3092 "vmovnt.i%#<V_sz_elem> %q0, %q2"
3093 [(set_attr "type" "mve_move")
3094])
3095
3096;;
3097;; [vmulq_f])
3098;;
3099(define_insn "mve_vmulq_f<mode>"
3100 [
3101 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3102 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3103 (match_operand:MVE_0 2 "s_register_operand" "w")]
3104 VMULQ_F))
3105 ]
3106 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3107 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
3108 [(set_attr "type" "mve_move")
3109])
3110
3111;;
3112;; [vmulq_n_f])
3113;;
3114(define_insn "mve_vmulq_n_f<mode>"
3115 [
3116 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3117 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3118 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3119 VMULQ_N_F))
3120 ]
3121 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3122 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
3123 [(set_attr "type" "mve_move")
3124])
3125
3126;;
3127;; [vornq_f])
3128;;
3129(define_insn "mve_vornq_f<mode>"
3130 [
3131 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3132 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3133 (match_operand:MVE_0 2 "s_register_operand" "w")]
3134 VORNQ_F))
3135 ]
3136 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3137 "vorn %q0, %q1, %q2"
3138 [(set_attr "type" "mve_move")
3139])
3140
3141;;
3142;; [vorrq_f])
3143;;
3144(define_insn "mve_vorrq_f<mode>"
3145 [
3146 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3147 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3148 (match_operand:MVE_0 2 "s_register_operand" "w")]
3149 VORRQ_F))
3150 ]
3151 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3152 "vorr %q0, %q1, %q2"
3153 [(set_attr "type" "mve_move")
3154])
3155
3156;;
3157;; [vorrq_n_u, vorrq_n_s])
3158;;
3159(define_insn "mve_vorrq_n_<supf><mode>"
3160 [
3161 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3162 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3163 (match_operand:SI 2 "immediate_operand" "i")]
3164 VORRQ_N))
3165 ]
3166 "TARGET_HAVE_MVE"
3167 "vorr.i%#<V_sz_elem> %q0, %2"
3168 [(set_attr "type" "mve_move")
3169])
3170
3171;;
3172;; [vqdmullbq_n_s])
3173;;
3174(define_insn "mve_vqdmullbq_n_s<mode>"
3175 [
3176 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3177 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3178 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3179 VQDMULLBQ_N_S))
3180 ]
3181 "TARGET_HAVE_MVE"
3182 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
3183 [(set_attr "type" "mve_move")
3184])
3185
3186;;
3187;; [vqdmullbq_s])
3188;;
3189(define_insn "mve_vqdmullbq_s<mode>"
3190 [
3191 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3192 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3193 (match_operand:MVE_5 2 "s_register_operand" "w")]
3194 VQDMULLBQ_S))
3195 ]
3196 "TARGET_HAVE_MVE"
3197 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
3198 [(set_attr "type" "mve_move")
3199])
3200
3201;;
3202;; [vqdmulltq_n_s])
3203;;
3204(define_insn "mve_vqdmulltq_n_s<mode>"
3205 [
3206 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3207 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3208 (match_operand:<V_elem> 2 "s_register_operand" "r")]
3209 VQDMULLTQ_N_S))
3210 ]
3211 "TARGET_HAVE_MVE"
3212 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
3213 [(set_attr "type" "mve_move")
3214])
3215
3216;;
3217;; [vqdmulltq_s])
3218;;
3219(define_insn "mve_vqdmulltq_s<mode>"
3220 [
3221 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3222 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
3223 (match_operand:MVE_5 2 "s_register_operand" "w")]
3224 VQDMULLTQ_S))
3225 ]
3226 "TARGET_HAVE_MVE"
3227 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
3228 [(set_attr "type" "mve_move")
3229])
3230
3231;;
3232;; [vqmovnbq_u, vqmovnbq_s])
3233;;
3234(define_insn "mve_vqmovnbq_<supf><mode>"
3235 [
3236 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3237 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3238 (match_operand:MVE_5 2 "s_register_operand" "w")]
3239 VQMOVNBQ))
3240 ]
3241 "TARGET_HAVE_MVE"
3242 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
3243 [(set_attr "type" "mve_move")
3244])
3245
3246;;
3247;; [vqmovntq_u, vqmovntq_s])
3248;;
3249(define_insn "mve_vqmovntq_<supf><mode>"
3250 [
3251 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3252 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3253 (match_operand:MVE_5 2 "s_register_operand" "w")]
3254 VQMOVNTQ))
3255 ]
3256 "TARGET_HAVE_MVE"
3257 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
3258 [(set_attr "type" "mve_move")
3259])
3260
3261;;
3262;; [vqmovunbq_s])
3263;;
3264(define_insn "mve_vqmovunbq_s<mode>"
3265 [
3266 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3267 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3268 (match_operand:MVE_5 2 "s_register_operand" "w")]
3269 VQMOVUNBQ_S))
3270 ]
3271 "TARGET_HAVE_MVE"
3272 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
3273 [(set_attr "type" "mve_move")
3274])
3275
3276;;
3277;; [vqmovuntq_s])
3278;;
3279(define_insn "mve_vqmovuntq_s<mode>"
3280 [
3281 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3282 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3283 (match_operand:MVE_5 2 "s_register_operand" "w")]
3284 VQMOVUNTQ_S))
3285 ]
3286 "TARGET_HAVE_MVE"
3287 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
3288 [(set_attr "type" "mve_move")
3289])
3290
3291;;
3292;; [vrmlaldavhxq_s])
3293;;
3294(define_insn "mve_vrmlaldavhxq_sv4si"
3295 [
3296 (set (match_operand:DI 0 "s_register_operand" "=r")
3297 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3298 (match_operand:V4SI 2 "s_register_operand" "w")]
3299 VRMLALDAVHXQ_S))
3300 ]
3301 "TARGET_HAVE_MVE"
3302 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
3303 [(set_attr "type" "mve_move")
3304])
3305
3306;;
3307;; [vrmlsldavhq_s])
3308;;
3309(define_insn "mve_vrmlsldavhq_sv4si"
3310 [
3311 (set (match_operand:DI 0 "s_register_operand" "=r")
3312 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3313 (match_operand:V4SI 2 "s_register_operand" "w")]
3314 VRMLSLDAVHQ_S))
3315 ]
3316 "TARGET_HAVE_MVE"
3317 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
3318 [(set_attr "type" "mve_move")
3319])
3320
3321;;
3322;; [vrmlsldavhxq_s])
3323;;
3324(define_insn "mve_vrmlsldavhxq_sv4si"
3325 [
3326 (set (match_operand:DI 0 "s_register_operand" "=r")
3327 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3328 (match_operand:V4SI 2 "s_register_operand" "w")]
3329 VRMLSLDAVHXQ_S))
3330 ]
3331 "TARGET_HAVE_MVE"
3332 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
3333 [(set_attr "type" "mve_move")
3334])
3335
3336;;
3337;; [vshllbq_n_s, vshllbq_n_u])
3338;;
3339(define_insn "mve_vshllbq_n_<supf><mode>"
3340 [
3341 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3342 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3343 (match_operand:SI 2 "immediate_operand" "i")]
3344 VSHLLBQ_N))
3345 ]
3346 "TARGET_HAVE_MVE"
3347 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3348 [(set_attr "type" "mve_move")
3349])
3350
3351;;
3352;; [vshlltq_n_u, vshlltq_n_s])
3353;;
3354(define_insn "mve_vshlltq_n_<supf><mode>"
3355 [
3356 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3357 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3358 (match_operand:SI 2 "immediate_operand" "i")]
3359 VSHLLTQ_N))
3360 ]
3361 "TARGET_HAVE_MVE"
3362 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
3363 [(set_attr "type" "mve_move")
3364])
3365
3366;;
3367;; [vsubq_f])
3368;;
3369(define_insn "mve_vsubq_f<mode>"
3370 [
3371 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3372 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3373 (match_operand:MVE_0 2 "s_register_operand" "w")]
3374 VSUBQ_F))
3375 ]
3376 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3377 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3378 [(set_attr "type" "mve_move")
3379])
3380
3381;;
3382;; [vmulltq_poly_p])
3383;;
3384(define_insn "mve_vmulltq_poly_p<mode>"
3385 [
3386 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3387 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3388 (match_operand:MVE_3 2 "s_register_operand" "w")]
3389 VMULLTQ_POLY_P))
3390 ]
3391 "TARGET_HAVE_MVE"
3392 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3393 [(set_attr "type" "mve_move")
3394])
3395
3396;;
3397;; [vmullbq_poly_p])
3398;;
3399(define_insn "mve_vmullbq_poly_p<mode>"
3400 [
3401 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3402 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3403 (match_operand:MVE_3 2 "s_register_operand" "w")]
3404 VMULLBQ_POLY_P))
3405 ]
3406 "TARGET_HAVE_MVE"
3407 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3408 [(set_attr "type" "mve_move")
3409])
3410
3411;;
3412;; [vrmlaldavhq_u vrmlaldavhq_s])
3413;;
3414(define_insn "mve_vrmlaldavhq_<supf>v4si"
3415 [
3416 (set (match_operand:DI 0 "s_register_operand" "=r")
3417 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3418 (match_operand:V4SI 2 "s_register_operand" "w")]
3419 VRMLALDAVHQ))
3420 ]
3421 "TARGET_HAVE_MVE"
3422 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3423 [(set_attr "type" "mve_move")
3424])
0dad5b33
SP		 3425
3426;;
3427;; [vbicq_m_n_s, vbicq_m_n_u])
3428;;
3429(define_insn "mve_vbicq_m_n_<supf><mode>"
3430 [
3431 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3432 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3433 (match_operand:SI 2 "immediate_operand" "i")
3434 (match_operand:HI 3 "vpr_register_operand" "Up")]
3435 VBICQ_M_N))
3436 ]
3437 "TARGET_HAVE_MVE"
3438 "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
3439 [(set_attr "type" "mve_move")
3440 (set_attr "length""8")])
3441;;
3442;; [vcmpeqq_m_f])
3443;;
3444(define_insn "mve_vcmpeqq_m_f<mode>"
3445 [
3446 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3447 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
3448 (match_operand:MVE_0 2 "s_register_operand" "w")
3449 (match_operand:HI 3 "vpr_register_operand" "Up")]
3450 VCMPEQQ_M_F))
3451 ]
3452 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3453 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
3454 [(set_attr "type" "mve_move")
3455 (set_attr "length""8")])
3456;;
3457;; [vcvtaq_m_u, vcvtaq_m_s])
3458;;
3459(define_insn "mve_vcvtaq_m_<supf><mode>"
3460 [
3461 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
3462 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
3463 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3464 (match_operand:HI 3 "vpr_register_operand" "Up")]
3465 VCVTAQ_M))
3466 ]
3467 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3468 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
3469 [(set_attr "type" "mve_move")
3470 (set_attr "length""8")])
3471;;
3472;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
3473;;
3474(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
3475 [
3476 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3477 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3478 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
3479 (match_operand:HI 3 "vpr_register_operand" "Up")]
3480 VCVTQ_M_TO_F))
3481 ]
3482 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3483 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
3484 [(set_attr "type" "mve_move")
3485 (set_attr "length""8")])
3486;;
3487;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
3488;;
3489(define_insn "mve_vqrshrnbq_n_<supf><mode>"
3490 [
3491 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3492 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3493 (match_operand:MVE_5 2 "s_register_operand" "w")
3494 (match_operand:SI 3 "mve_imm_8" "Rb")]
3495 VQRSHRNBQ_N))
3496 ]
3497 "TARGET_HAVE_MVE"
3498 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
3499 [(set_attr "type" "mve_move")
3500])
3501;;
3502;; [vqrshrunbq_n_s])
3503;;
3504(define_insn "mve_vqrshrunbq_n_s<mode>"
3505 [
3506 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
3507 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
3508 (match_operand:MVE_5 2 "s_register_operand" "w")
3509 (match_operand:SI 3 "mve_imm_8" "Rb")]
3510 VQRSHRUNBQ_N_S))
3511 ]
3512 "TARGET_HAVE_MVE"
3513 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
3514 [(set_attr "type" "mve_move")
3515])
3516;;
3517;; [vrmlaldavhaq_s vrmlaldavhaq_u])
3518;;
3519(define_insn "mve_vrmlaldavhaq_<supf>v4si"
3520 [
3521 (set (match_operand:DI 0 "s_register_operand" "=r")
3522 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
3523 (match_operand:V4SI 2 "s_register_operand" "w")
3524 (match_operand:V4SI 3 "s_register_operand" "w")]
3525 VRMLALDAVHAQ))
3526 ]
3527 "TARGET_HAVE_MVE"
3528 "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
3529 [(set_attr "type" "mve_move")
3530])
3531
3532;;
3533;; [vabavq_s, vabavq_u])
3534;;
3535(define_insn "mve_vabavq_<supf><mode>"
3536 [
3537 (set (match_operand:SI 0 "s_register_operand" "=r")
3538 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3539 (match_operand:MVE_2 2 "s_register_operand" "w")
3540 (match_operand:MVE_2 3 "s_register_operand" "w")]
3541 VABAVQ))
3542 ]
3543 "TARGET_HAVE_MVE"
3544 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
3545 [(set_attr "type" "mve_move")
3546])
3547
3548;;
3549;; [vshlcq_u vshlcq_s]
3550;;
3551(define_expand "mve_vshlcq_vec_<supf><mode>"
3552 [(match_operand:MVE_2 0 "s_register_operand")
3553 (match_operand:MVE_2 1 "s_register_operand")
3554 (match_operand:SI 2 "s_register_operand")
3555 (match_operand:SI 3 "mve_imm_32")
3556 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3557 "TARGET_HAVE_MVE"
3558{
3559 rtx ignore_wb = gen_reg_rtx (SImode);
3560 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
8165795c 3561 operands[2], operands[3]));
0dad5b33
SP		 3562 DONE;
3563})
3564
3565(define_expand "mve_vshlcq_carry_<supf><mode>"
3566 [(match_operand:SI 0 "s_register_operand")
3567 (match_operand:MVE_2 1 "s_register_operand")
3568 (match_operand:SI 2 "s_register_operand")
3569 (match_operand:SI 3 "mve_imm_32")
3570 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
3571 "TARGET_HAVE_MVE"
3572{
3573 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
3574 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
3575 operands[2], operands[3]));
3576 DONE;
3577})
3578
3579(define_insn "mve_vshlcq_<supf><mode>"
3580 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3581 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
3582 (match_operand:SI 3 "s_register_operand" "1")
3583 (match_operand:SI 4 "mve_imm_32" "Rf")]
3584 VSHLCQ))
3585 (set (match_operand:SI 1 "s_register_operand" "=r")
3586 (unspec:SI [(match_dup 2)
3587 (match_dup 3)
3588 (match_dup 4)]
3589 VSHLCQ))]
3590 "TARGET_HAVE_MVE"
3591 "vshlc %q0, %1, %4")
8165795c
SP		 3592
3593;;
3594;; [vabsq_m_s])
3595;;
3596(define_insn "mve_vabsq_m_s<mode>"
3597 [
3598 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3599 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3600 (match_operand:MVE_2 2 "s_register_operand" "w")
3601 (match_operand:HI 3 "vpr_register_operand" "Up")]
3602 VABSQ_M_S))
3603 ]
3604 "TARGET_HAVE_MVE"
3605 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2"
3606 [(set_attr "type" "mve_move")
3607 (set_attr "length""8")])
3608
3609;;
3610;; [vaddvaq_p_u, vaddvaq_p_s])
3611;;
3612(define_insn "mve_vaddvaq_p_<supf><mode>"
3613 [
3614 (set (match_operand:SI 0 "s_register_operand" "=e")
3615 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
3616 (match_operand:MVE_2 2 "s_register_operand" "w")
3617 (match_operand:HI 3 "vpr_register_operand" "Up")]
3618 VADDVAQ_P))
3619 ]
3620 "TARGET_HAVE_MVE"
3621 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2"
3622 [(set_attr "type" "mve_move")
3623 (set_attr "length""8")])
3624
3625;;
3626;; [vclsq_m_s])
3627;;
3628(define_insn "mve_vclsq_m_s<mode>"
3629 [
3630 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3631 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3632 (match_operand:MVE_2 2 "s_register_operand" "w")
3633 (match_operand:HI 3 "vpr_register_operand" "Up")]
3634 VCLSQ_M_S))
3635 ]
3636 "TARGET_HAVE_MVE"
3637 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2"
3638 [(set_attr "type" "mve_move")
3639 (set_attr "length""8")])
3640
3641;;
3642;; [vclzq_m_s, vclzq_m_u])
3643;;
3644(define_insn "mve_vclzq_m_<supf><mode>"
3645 [
3646 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3647 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3648 (match_operand:MVE_2 2 "s_register_operand" "w")
3649 (match_operand:HI 3 "vpr_register_operand" "Up")]
3650 VCLZQ_M))
3651 ]
3652 "TARGET_HAVE_MVE"
3653 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2"
3654 [(set_attr "type" "mve_move")
3655 (set_attr "length""8")])
3656
3657;;
3658;; [vcmpcsq_m_n_u])
3659;;
3660(define_insn "mve_vcmpcsq_m_n_u<mode>"
3661 [
3662 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3663 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3664 (match_operand:<V_elem> 2 "s_register_operand" "r")
3665 (match_operand:HI 3 "vpr_register_operand" "Up")]
3666 VCMPCSQ_M_N_U))
3667 ]
3668 "TARGET_HAVE_MVE"
3669 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2"
3670 [(set_attr "type" "mve_move")
3671 (set_attr "length""8")])
3672
3673;;
3674;; [vcmpcsq_m_u])
3675;;
3676(define_insn "mve_vcmpcsq_m_u<mode>"
3677 [
3678 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3679 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3680 (match_operand:MVE_2 2 "s_register_operand" "w")
3681 (match_operand:HI 3 "vpr_register_operand" "Up")]
3682 VCMPCSQ_M_U))
3683 ]
3684 "TARGET_HAVE_MVE"
3685 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2"
3686 [(set_attr "type" "mve_move")
3687 (set_attr "length""8")])
3688
3689;;
3690;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
3691;;
3692(define_insn "mve_vcmpeqq_m_n_<supf><mode>"
3693 [
3694 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3695 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3696 (match_operand:<V_elem> 2 "s_register_operand" "r")
3697 (match_operand:HI 3 "vpr_register_operand" "Up")]
3698 VCMPEQQ_M_N))
3699 ]
3700 "TARGET_HAVE_MVE"
3701 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2"
3702 [(set_attr "type" "mve_move")
3703 (set_attr "length""8")])
3704
3705;;
3706;; [vcmpeqq_m_u, vcmpeqq_m_s])
3707;;
3708(define_insn "mve_vcmpeqq_m_<supf><mode>"
3709 [
3710 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3711 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3712 (match_operand:MVE_2 2 "s_register_operand" "w")
3713 (match_operand:HI 3 "vpr_register_operand" "Up")]
3714 VCMPEQQ_M))
3715 ]
3716 "TARGET_HAVE_MVE"
3717 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2"
3718 [(set_attr "type" "mve_move")
3719 (set_attr "length""8")])
3720
3721;;
3722;; [vcmpgeq_m_n_s])
3723;;
3724(define_insn "mve_vcmpgeq_m_n_s<mode>"
3725 [
3726 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3727 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3728 (match_operand:<V_elem> 2 "s_register_operand" "r")
3729 (match_operand:HI 3 "vpr_register_operand" "Up")]
3730 VCMPGEQ_M_N_S))
3731 ]
3732 "TARGET_HAVE_MVE"
3733 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2"
3734 [(set_attr "type" "mve_move")
3735 (set_attr "length""8")])
3736
3737;;
3738;; [vcmpgeq_m_s])
3739;;
3740(define_insn "mve_vcmpgeq_m_s<mode>"
3741 [
3742 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3743 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3744 (match_operand:MVE_2 2 "s_register_operand" "w")
3745 (match_operand:HI 3 "vpr_register_operand" "Up")]
3746 VCMPGEQ_M_S))
3747 ]
3748 "TARGET_HAVE_MVE"
3749 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2"
3750 [(set_attr "type" "mve_move")
3751 (set_attr "length""8")])
3752
3753;;
3754;; [vcmpgtq_m_n_s])
3755;;
3756(define_insn "mve_vcmpgtq_m_n_s<mode>"
3757 [
3758 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3759 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3760 (match_operand:<V_elem> 2 "s_register_operand" "r")
3761 (match_operand:HI 3 "vpr_register_operand" "Up")]
3762 VCMPGTQ_M_N_S))
3763 ]
3764 "TARGET_HAVE_MVE"
3765 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2"
3766 [(set_attr "type" "mve_move")
3767 (set_attr "length""8")])
3768
3769;;
3770;; [vcmpgtq_m_s])
3771;;
3772(define_insn "mve_vcmpgtq_m_s<mode>"
3773 [
3774 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3775 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3776 (match_operand:MVE_2 2 "s_register_operand" "w")
3777 (match_operand:HI 3 "vpr_register_operand" "Up")]
3778 VCMPGTQ_M_S))
3779 ]
3780 "TARGET_HAVE_MVE"
3781 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2"
3782 [(set_attr "type" "mve_move")
3783 (set_attr "length""8")])
3784
3785;;
3786;; [vcmphiq_m_n_u])
3787;;
3788(define_insn "mve_vcmphiq_m_n_u<mode>"
3789 [
3790 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3791 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3792 (match_operand:<V_elem> 2 "s_register_operand" "r")
3793 (match_operand:HI 3 "vpr_register_operand" "Up")]
3794 VCMPHIQ_M_N_U))
3795 ]
3796 "TARGET_HAVE_MVE"
3797 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2"
3798 [(set_attr "type" "mve_move")
3799 (set_attr "length""8")])
3800
3801;;
3802;; [vcmphiq_m_u])
3803;;
3804(define_insn "mve_vcmphiq_m_u<mode>"
3805 [
3806 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3807 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3808 (match_operand:MVE_2 2 "s_register_operand" "w")
3809 (match_operand:HI 3 "vpr_register_operand" "Up")]
3810 VCMPHIQ_M_U))
3811 ]
3812 "TARGET_HAVE_MVE"
3813 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2"
3814 [(set_attr "type" "mve_move")
3815 (set_attr "length""8")])
3816
3817;;
3818;; [vcmpleq_m_n_s])
3819;;
3820(define_insn "mve_vcmpleq_m_n_s<mode>"
3821 [
3822 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3823 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3824 (match_operand:<V_elem> 2 "s_register_operand" "r")
3825 (match_operand:HI 3 "vpr_register_operand" "Up")]
3826 VCMPLEQ_M_N_S))
3827 ]
3828 "TARGET_HAVE_MVE"
3829 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2"
3830 [(set_attr "type" "mve_move")
3831 (set_attr "length""8")])
3832
3833;;
3834;; [vcmpleq_m_s])
3835;;
3836(define_insn "mve_vcmpleq_m_s<mode>"
3837 [
3838 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3839 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3840 (match_operand:MVE_2 2 "s_register_operand" "w")
3841 (match_operand:HI 3 "vpr_register_operand" "Up")]
3842 VCMPLEQ_M_S))
3843 ]
3844 "TARGET_HAVE_MVE"
3845 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2"
3846 [(set_attr "type" "mve_move")
3847 (set_attr "length""8")])
3848
3849;;
3850;; [vcmpltq_m_n_s])
3851;;
3852(define_insn "mve_vcmpltq_m_n_s<mode>"
3853 [
3854 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3855 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3856 (match_operand:<V_elem> 2 "s_register_operand" "r")
3857 (match_operand:HI 3 "vpr_register_operand" "Up")]
3858 VCMPLTQ_M_N_S))
3859 ]
3860 "TARGET_HAVE_MVE"
3861 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2"
3862 [(set_attr "type" "mve_move")
3863 (set_attr "length""8")])
3864
3865;;
3866;; [vcmpltq_m_s])
3867;;
3868(define_insn "mve_vcmpltq_m_s<mode>"
3869 [
3870 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3871 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3872 (match_operand:MVE_2 2 "s_register_operand" "w")
3873 (match_operand:HI 3 "vpr_register_operand" "Up")]
3874 VCMPLTQ_M_S))
3875 ]
3876 "TARGET_HAVE_MVE"
3877 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2"
3878 [(set_attr "type" "mve_move")
3879 (set_attr "length""8")])
3880
3881;;
3882;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
3883;;
3884(define_insn "mve_vcmpneq_m_n_<supf><mode>"
3885 [
3886 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3887 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3888 (match_operand:<V_elem> 2 "s_register_operand" "r")
3889 (match_operand:HI 3 "vpr_register_operand" "Up")]
3890 VCMPNEQ_M_N))
3891 ]
3892 "TARGET_HAVE_MVE"
3893 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2"
3894 [(set_attr "type" "mve_move")
3895 (set_attr "length""8")])
3896
3897;;
3898;; [vcmpneq_m_s, vcmpneq_m_u])
3899;;
3900(define_insn "mve_vcmpneq_m_<supf><mode>"
3901 [
3902 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
3903 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
3904 (match_operand:MVE_2 2 "s_register_operand" "w")
3905 (match_operand:HI 3 "vpr_register_operand" "Up")]
3906 VCMPNEQ_M))
3907 ]
3908 "TARGET_HAVE_MVE"
3909 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2"
3910 [(set_attr "type" "mve_move")
3911 (set_attr "length""8")])
3912
3913;;
3914;; [vdupq_m_n_s, vdupq_m_n_u])
3915;;
3916(define_insn "mve_vdupq_m_n_<supf><mode>"
3917 [
3918 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3919 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3920 (match_operand:<V_elem> 2 "s_register_operand" "r")
3921 (match_operand:HI 3 "vpr_register_operand" "Up")]
3922 VDUPQ_M_N))
3923 ]
3924 "TARGET_HAVE_MVE"
3925 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
3926 [(set_attr "type" "mve_move")
3927 (set_attr "length""8")])
3928
3929;;
3930;; [vmaxaq_m_s])
3931;;
3932(define_insn "mve_vmaxaq_m_s<mode>"
3933 [
3934 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3935 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3936 (match_operand:MVE_2 2 "s_register_operand" "w")
3937 (match_operand:HI 3 "vpr_register_operand" "Up")]
3938 VMAXAQ_M_S))
3939 ]
3940 "TARGET_HAVE_MVE"
3941 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2"
3942 [(set_attr "type" "mve_move")
3943 (set_attr "length""8")])
3944
3945;;
3946;; [vmaxavq_p_s])
3947;;
3948(define_insn "mve_vmaxavq_p_s<mode>"
3949 [
3950 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3951 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3952 (match_operand:MVE_2 2 "s_register_operand" "w")
3953 (match_operand:HI 3 "vpr_register_operand" "Up")]
3954 VMAXAVQ_P_S))
3955 ]
3956 "TARGET_HAVE_MVE"
3957 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
3958 [(set_attr "type" "mve_move")
3959 (set_attr "length""8")])
3960
3961;;
3962;; [vmaxvq_p_u, vmaxvq_p_s])
3963;;
3964(define_insn "mve_vmaxvq_p_<supf><mode>"
3965 [
3966 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3967 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
3968 (match_operand:MVE_2 2 "s_register_operand" "w")
3969 (match_operand:HI 3 "vpr_register_operand" "Up")]
3970 VMAXVQ_P))
3971 ]
3972 "TARGET_HAVE_MVE"
3973 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
3974 [(set_attr "type" "mve_move")
3975 (set_attr "length""8")])
3976
3977;;
3978;; [vminaq_m_s])
3979;;
3980(define_insn "mve_vminaq_m_s<mode>"
3981 [
3982 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
3983 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
3984 (match_operand:MVE_2 2 "s_register_operand" "w")
3985 (match_operand:HI 3 "vpr_register_operand" "Up")]
3986 VMINAQ_M_S))
3987 ]
3988 "TARGET_HAVE_MVE"
3989 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2"
3990 [(set_attr "type" "mve_move")
3991 (set_attr "length""8")])
3992
3993;;
3994;; [vminavq_p_s])
3995;;
3996(define_insn "mve_vminavq_p_s<mode>"
3997 [
3998 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
3999 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4000 (match_operand:MVE_2 2 "s_register_operand" "w")
4001 (match_operand:HI 3 "vpr_register_operand" "Up")]
4002 VMINAVQ_P_S))
4003 ]
4004 "TARGET_HAVE_MVE"
4005 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
4006 [(set_attr "type" "mve_move")
4007 (set_attr "length""8")])
4008
4009;;
4010;; [vminvq_p_s, vminvq_p_u])
4011;;
4012(define_insn "mve_vminvq_p_<supf><mode>"
4013 [
4014 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4015 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4016 (match_operand:MVE_2 2 "s_register_operand" "w")
4017 (match_operand:HI 3 "vpr_register_operand" "Up")]
4018 VMINVQ_P))
4019 ]
4020 "TARGET_HAVE_MVE"
4021 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
4022 [(set_attr "type" "mve_move")
4023 (set_attr "length""8")])
4024
4025;;
4026;; [vmladavaq_u, vmladavaq_s])
4027;;
4028(define_insn "mve_vmladavaq_<supf><mode>"
4029 [
4030 (set (match_operand:SI 0 "s_register_operand" "=e")
4031 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4032 (match_operand:MVE_2 2 "s_register_operand" "w")
4033 (match_operand:MVE_2 3 "s_register_operand" "w")]
4034 VMLADAVAQ))
4035 ]
4036 "TARGET_HAVE_MVE"
4037 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
4038 [(set_attr "type" "mve_move")
4039])
4040
4041;;
4042;; [vmladavq_p_u, vmladavq_p_s])
4043;;
4044(define_insn "mve_vmladavq_p_<supf><mode>"
4045 [
4046 (set (match_operand:SI 0 "s_register_operand" "=e")
4047 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4048 (match_operand:MVE_2 2 "s_register_operand" "w")
4049 (match_operand:HI 3 "vpr_register_operand" "Up")]
4050 VMLADAVQ_P))
4051 ]
4052 "TARGET_HAVE_MVE"
4053 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
4054 [(set_attr "type" "mve_move")
4055 (set_attr "length""8")])
4056
4057;;
4058;; [vmladavxq_p_s])
4059;;
4060(define_insn "mve_vmladavxq_p_s<mode>"
4061 [
4062 (set (match_operand:SI 0 "s_register_operand" "=e")
4063 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4064 (match_operand:MVE_2 2 "s_register_operand" "w")
4065 (match_operand:HI 3 "vpr_register_operand" "Up")]
4066 VMLADAVXQ_P_S))
4067 ]
4068 "TARGET_HAVE_MVE"
4069 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
4070 [(set_attr "type" "mve_move")
4071 (set_attr "length""8")])
4072
4073;;
4074;; [vmlaq_n_u, vmlaq_n_s])
4075;;
4076(define_insn "mve_vmlaq_n_<supf><mode>"
4077 [
4078 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4079 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4080 (match_operand:MVE_2 2 "s_register_operand" "w")
4081 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4082 VMLAQ_N))
4083 ]
4084 "TARGET_HAVE_MVE"
4085 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
4086 [(set_attr "type" "mve_move")
4087])
4088
4089;;
4090;; [vmlasq_n_u, vmlasq_n_s])
4091;;
4092(define_insn "mve_vmlasq_n_<supf><mode>"
4093 [
4094 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4095 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4096 (match_operand:MVE_2 2 "s_register_operand" "w")
4097 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4098 VMLASQ_N))
4099 ]
4100 "TARGET_HAVE_MVE"
4101 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3"
4102 [(set_attr "type" "mve_move")
4103])
4104
4105;;
4106;; [vmlsdavq_p_s])
4107;;
4108(define_insn "mve_vmlsdavq_p_s<mode>"
4109 [
4110 (set (match_operand:SI 0 "s_register_operand" "=e")
4111 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4112 (match_operand:MVE_2 2 "s_register_operand" "w")
4113 (match_operand:HI 3 "vpr_register_operand" "Up")]
4114 VMLSDAVQ_P_S))
4115 ]
4116 "TARGET_HAVE_MVE"
4117 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
4118 [(set_attr "type" "mve_move")
4119 (set_attr "length""8")])
4120
4121;;
4122;; [vmlsdavxq_p_s])
4123;;
4124(define_insn "mve_vmlsdavxq_p_s<mode>"
4125 [
4126 (set (match_operand:SI 0 "s_register_operand" "=e")
4127 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
4128 (match_operand:MVE_2 2 "s_register_operand" "w")
4129 (match_operand:HI 3 "vpr_register_operand" "Up")]
4130 VMLSDAVXQ_P_S))
4131 ]
4132 "TARGET_HAVE_MVE"
4133 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
4134 [(set_attr "type" "mve_move")
4135 (set_attr "length""8")])
4136
4137;;
4138;; [vmvnq_m_s, vmvnq_m_u])
4139;;
4140(define_insn "mve_vmvnq_m_<supf><mode>"
4141 [
4142 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4143 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4144 (match_operand:MVE_2 2 "s_register_operand" "w")
4145 (match_operand:HI 3 "vpr_register_operand" "Up")]
4146 VMVNQ_M))
4147 ]
4148 "TARGET_HAVE_MVE"
4149 "vpst\;vmvnt %q0, %q2"
4150 [(set_attr "type" "mve_move")
4151 (set_attr "length""8")])
4152
4153;;
4154;; [vnegq_m_s])
4155;;
4156(define_insn "mve_vnegq_m_s<mode>"
4157 [
4158 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4159 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4160 (match_operand:MVE_2 2 "s_register_operand" "w")
4161 (match_operand:HI 3 "vpr_register_operand" "Up")]
4162 VNEGQ_M_S))
4163 ]
4164 "TARGET_HAVE_MVE"
4165 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2"
4166 [(set_attr "type" "mve_move")
4167 (set_attr "length""8")])
4168
4169;;
4170;; [vpselq_u, vpselq_s])
4171;;
4172(define_insn "mve_vpselq_<supf><mode>"
4173 [
4174 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
4175 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
4176 (match_operand:MVE_1 2 "s_register_operand" "w")
4177 (match_operand:HI 3 "vpr_register_operand" "Up")]
4178 VPSELQ))
4179 ]
4180 "TARGET_HAVE_MVE"
4181 "vpsel %q0, %q1, %q2"
4182 [(set_attr "type" "mve_move")
4183])
4184
4185;;
4186;; [vqabsq_m_s])
4187;;
4188(define_insn "mve_vqabsq_m_s<mode>"
4189 [
4190 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4191 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4192 (match_operand:MVE_2 2 "s_register_operand" "w")
4193 (match_operand:HI 3 "vpr_register_operand" "Up")]
4194 VQABSQ_M_S))
4195 ]
4196 "TARGET_HAVE_MVE"
4197 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2"
4198 [(set_attr "type" "mve_move")
4199 (set_attr "length""8")])
4200
4201;;
4202;; [vqdmlahq_n_s, vqdmlahq_n_u])
4203;;
4204(define_insn "mve_vqdmlahq_n_<supf><mode>"
4205 [
4206 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4207 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4208 (match_operand:MVE_2 2 "s_register_operand" "w")
4209 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4210 VQDMLAHQ_N))
4211 ]
4212 "TARGET_HAVE_MVE"
4213 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4214 [(set_attr "type" "mve_move")
4215])
4216
4217;;
4218;; [vqnegq_m_s])
4219;;
4220(define_insn "mve_vqnegq_m_s<mode>"
4221 [
4222 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4223 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4224 (match_operand:MVE_2 2 "s_register_operand" "w")
4225 (match_operand:HI 3 "vpr_register_operand" "Up")]
4226 VQNEGQ_M_S))
4227 ]
4228 "TARGET_HAVE_MVE"
4229 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2"
4230 [(set_attr "type" "mve_move")
4231 (set_attr "length""8")])
4232
4233;;
4234;; [vqrdmladhq_s])
4235;;
4236(define_insn "mve_vqrdmladhq_s<mode>"
4237 [
4238 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4239 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4240 (match_operand:MVE_2 2 "s_register_operand" "w")
4241 (match_operand:MVE_2 3 "s_register_operand" "w")]
4242 VQRDMLADHQ_S))
4243 ]
4244 "TARGET_HAVE_MVE"
4245 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4246 [(set_attr "type" "mve_move")
4247])
4248
4249;;
4250;; [vqrdmladhxq_s])
4251;;
4252(define_insn "mve_vqrdmladhxq_s<mode>"
4253 [
4254 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4255 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4256 (match_operand:MVE_2 2 "s_register_operand" "w")
4257 (match_operand:MVE_2 3 "s_register_operand" "w")]
4258 VQRDMLADHXQ_S))
4259 ]
4260 "TARGET_HAVE_MVE"
4261 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4262 [(set_attr "type" "mve_move")
4263])
4264
4265;;
4266;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
4267;;
4268(define_insn "mve_vqrdmlahq_n_<supf><mode>"
4269 [
4270 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4271 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4272 (match_operand:MVE_2 2 "s_register_operand" "w")
4273 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4274 VQRDMLAHQ_N))
4275 ]
4276 "TARGET_HAVE_MVE"
4277 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3"
4278 [(set_attr "type" "mve_move")
4279])
4280
4281;;
4282;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
4283;;
4284(define_insn "mve_vqrdmlashq_n_<supf><mode>"
4285 [
4286 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4287 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4288 (match_operand:MVE_2 2 "s_register_operand" "w")
4289 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4290 VQRDMLASHQ_N))
4291 ]
4292 "TARGET_HAVE_MVE"
4293 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
4294 [(set_attr "type" "mve_move")
4295])
4296
4297;;
4298;; [vqrdmlsdhq_s])
4299;;
4300(define_insn "mve_vqrdmlsdhq_s<mode>"
4301 [
4302 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4303 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4304 (match_operand:MVE_2 2 "s_register_operand" "w")
4305 (match_operand:MVE_2 3 "s_register_operand" "w")]
4306 VQRDMLSDHQ_S))
4307 ]
4308 "TARGET_HAVE_MVE"
4309 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4310 [(set_attr "type" "mve_move")
4311])
4312
4313;;
4314;; [vqrdmlsdhxq_s])
4315;;
4316(define_insn "mve_vqrdmlsdhxq_s<mode>"
4317 [
4318 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4319 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4320 (match_operand:MVE_2 2 "s_register_operand" "w")
4321 (match_operand:MVE_2 3 "s_register_operand" "w")]
4322 VQRDMLSDHXQ_S))
4323 ]
4324 "TARGET_HAVE_MVE"
4325 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4326 [(set_attr "type" "mve_move")
4327])
4328
4329;;
4330;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
4331;;
4332(define_insn "mve_vqrshlq_m_n_<supf><mode>"
4333 [
4334 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4335 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4336 (match_operand:SI 2 "s_register_operand" "r")
4337 (match_operand:HI 3 "vpr_register_operand" "Up")]
4338 VQRSHLQ_M_N))
4339 ]
4340 "TARGET_HAVE_MVE"
4341 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2"
4342 [(set_attr "type" "mve_move")
4343 (set_attr "length""8")])
4344
4345;;
4346;; [vqshlq_m_r_u, vqshlq_m_r_s])
4347;;
4348(define_insn "mve_vqshlq_m_r_<supf><mode>"
4349 [
4350 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4351 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4352 (match_operand:SI 2 "s_register_operand" "r")
4353 (match_operand:HI 3 "vpr_register_operand" "Up")]
4354 VQSHLQ_M_R))
4355 ]
4356 "TARGET_HAVE_MVE"
4357 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4358 [(set_attr "type" "mve_move")
4359 (set_attr "length""8")])
4360
4361;;
4362;; [vrev64q_m_u, vrev64q_m_s])
4363;;
4364(define_insn "mve_vrev64q_m_<supf><mode>"
4365 [
4366 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4367 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4368 (match_operand:MVE_2 2 "s_register_operand" "w")
4369 (match_operand:HI 3 "vpr_register_operand" "Up")]
4370 VREV64Q_M))
4371 ]
4372 "TARGET_HAVE_MVE"
4373 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
4374 [(set_attr "type" "mve_move")
4375 (set_attr "length""8")])
4376
4377;;
4378;; [vrshlq_m_n_s, vrshlq_m_n_u])
4379;;
4380(define_insn "mve_vrshlq_m_n_<supf><mode>"
4381 [
4382 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4383 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4384 (match_operand:SI 2 "s_register_operand" "r")
4385 (match_operand:HI 3 "vpr_register_operand" "Up")]
4386 VRSHLQ_M_N))
4387 ]
4388 "TARGET_HAVE_MVE"
4389 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4390 [(set_attr "type" "mve_move")
4391 (set_attr "length""8")])
4392
4393;;
4394;; [vshlq_m_r_u, vshlq_m_r_s])
4395;;
4396(define_insn "mve_vshlq_m_r_<supf><mode>"
4397 [
4398 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4399 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4400 (match_operand:SI 2 "s_register_operand" "r")
4401 (match_operand:HI 3 "vpr_register_operand" "Up")]
4402 VSHLQ_M_R))
4403 ]
4404 "TARGET_HAVE_MVE"
4405 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
4406 [(set_attr "type" "mve_move")
4407 (set_attr "length""8")])
4408
4409;;
4410;; [vsliq_n_u, vsliq_n_s])
4411;;
4412(define_insn "mve_vsliq_n_<supf><mode>"
4413 [
4414 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4415 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4416 (match_operand:MVE_2 2 "s_register_operand" "w")
4417 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
4418 VSLIQ_N))
4419 ]
4420 "TARGET_HAVE_MVE"
4421 "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
4422 [(set_attr "type" "mve_move")
4423])
4424
4425;;
4426;; [vsriq_n_u, vsriq_n_s])
4427;;
4428(define_insn "mve_vsriq_n_<supf><mode>"
4429 [
4430 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4431 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4432 (match_operand:MVE_2 2 "s_register_operand" "w")
4433 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
4434 VSRIQ_N))
4435 ]
4436 "TARGET_HAVE_MVE"
4437 "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
4438 [(set_attr "type" "mve_move")
4439])
4440
4441;;
4442;; [vqdmlsdhxq_s])
4443;;
4444(define_insn "mve_vqdmlsdhxq_s<mode>"
4445 [
4446 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4447 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4448 (match_operand:MVE_2 2 "s_register_operand" "w")
4449 (match_operand:MVE_2 3 "s_register_operand" "w")]
4450 VQDMLSDHXQ_S))
4451 ]
4452 "TARGET_HAVE_MVE"
4453 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4454 [(set_attr "type" "mve_move")
4455])
4456
4457;;
4458;; [vqdmlsdhq_s])
4459;;
4460(define_insn "mve_vqdmlsdhq_s<mode>"
4461 [
4462 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4463 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4464 (match_operand:MVE_2 2 "s_register_operand" "w")
4465 (match_operand:MVE_2 3 "s_register_operand" "w")]
4466 VQDMLSDHQ_S))
4467 ]
4468 "TARGET_HAVE_MVE"
4469 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4470 [(set_attr "type" "mve_move")
4471])
4472
4473;;
4474;; [vqdmladhxq_s])
4475;;
4476(define_insn "mve_vqdmladhxq_s<mode>"
4477 [
4478 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4479 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4480 (match_operand:MVE_2 2 "s_register_operand" "w")
4481 (match_operand:MVE_2 3 "s_register_operand" "w")]
4482 VQDMLADHXQ_S))
4483 ]
4484 "TARGET_HAVE_MVE"
4485 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
4486 [(set_attr "type" "mve_move")
4487])
4488
4489;;
4490;; [vqdmladhq_s])
4491;;
4492(define_insn "mve_vqdmladhq_s<mode>"
4493 [
4494 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
4495 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
4496 (match_operand:MVE_2 2 "s_register_operand" "w")
4497 (match_operand:MVE_2 3 "s_register_operand" "w")]
4498 VQDMLADHQ_S))
4499 ]
4500 "TARGET_HAVE_MVE"
4501 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
4502 [(set_attr "type" "mve_move")
4503])
4504
4505;;
4506;; [vmlsdavaxq_s])
4507;;
4508(define_insn "mve_vmlsdavaxq_s<mode>"
4509 [
4510 (set (match_operand:SI 0 "s_register_operand" "=e")
4511 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4512 (match_operand:MVE_2 2 "s_register_operand" "w")
4513 (match_operand:MVE_2 3 "s_register_operand" "w")]
4514 VMLSDAVAXQ_S))
4515 ]
4516 "TARGET_HAVE_MVE"
4517 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4518 [(set_attr "type" "mve_move")
4519])
4520
4521;;
4522;; [vmlsdavaq_s])
4523;;
4524(define_insn "mve_vmlsdavaq_s<mode>"
4525 [
4526 (set (match_operand:SI 0 "s_register_operand" "=e")
4527 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4528 (match_operand:MVE_2 2 "s_register_operand" "w")
4529 (match_operand:MVE_2 3 "s_register_operand" "w")]
4530 VMLSDAVAQ_S))
4531 ]
4532 "TARGET_HAVE_MVE"
4533 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
4534 [(set_attr "type" "mve_move")
4535])
4536
4537;;
4538;; [vmladavaxq_s])
4539;;
4540(define_insn "mve_vmladavaxq_s<mode>"
4541 [
4542 (set (match_operand:SI 0 "s_register_operand" "=e")
4543 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
4544 (match_operand:MVE_2 2 "s_register_operand" "w")
4545 (match_operand:MVE_2 3 "s_register_operand" "w")]
4546 VMLADAVAXQ_S))
4547 ]
4548 "TARGET_HAVE_MVE"
4549 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
4550 [(set_attr "type" "mve_move")
4551])
e3678b44
SP		 4552;;
4553;; [vabsq_m_f])
4554;;
4555(define_insn "mve_vabsq_m_f<mode>"
4556 [
4557 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4558 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4559 (match_operand:MVE_0 2 "s_register_operand" "w")
4560 (match_operand:HI 3 "vpr_register_operand" "Up")]
4561 VABSQ_M_F))
4562 ]
4563 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4564 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2"
4565 [(set_attr "type" "mve_move")
4566 (set_attr "length""8")])
4567
4568;;
4569;; [vaddlvaq_p_s vaddlvaq_p_u])
4570;;
4571(define_insn "mve_vaddlvaq_p_<supf>v4si"
4572 [
4573 (set (match_operand:DI 0 "s_register_operand" "=r")
4574 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
4575 (match_operand:V4SI 2 "s_register_operand" "w")
4576 (match_operand:HI 3 "vpr_register_operand" "Up")]
4577 VADDLVAQ_P))
4578 ]
4579 "TARGET_HAVE_MVE"
4580 "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
4581 [(set_attr "type" "mve_move")
4582 (set_attr "length""8")])
4583;;
4584;; [vcmlaq_f])
4585;;
4586(define_insn "mve_vcmlaq_f<mode>"
4587 [
4588 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4589 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4590 (match_operand:MVE_0 2 "s_register_operand" "w")
4591 (match_operand:MVE_0 3 "s_register_operand" "w")]
4592 VCMLAQ_F))
4593 ]
4594 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4595 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
4596 [(set_attr "type" "mve_move")
4597])
4598
4599;;
4600;; [vcmlaq_rot180_f])
4601;;
4602(define_insn "mve_vcmlaq_rot180_f<mode>"
4603 [
4604 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4605 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4606 (match_operand:MVE_0 2 "s_register_operand" "w")
4607 (match_operand:MVE_0 3 "s_register_operand" "w")]
4608 VCMLAQ_ROT180_F))
4609 ]
4610 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4611 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
4612 [(set_attr "type" "mve_move")
4613])
4614
4615;;
4616;; [vcmlaq_rot270_f])
4617;;
4618(define_insn "mve_vcmlaq_rot270_f<mode>"
4619 [
4620 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4621 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4622 (match_operand:MVE_0 2 "s_register_operand" "w")
4623 (match_operand:MVE_0 3 "s_register_operand" "w")]
4624 VCMLAQ_ROT270_F))
4625 ]
4626 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4627 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
4628 [(set_attr "type" "mve_move")
4629])
4630
4631;;
4632;; [vcmlaq_rot90_f])
4633;;
4634(define_insn "mve_vcmlaq_rot90_f<mode>"
4635 [
4636 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4637 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4638 (match_operand:MVE_0 2 "s_register_operand" "w")
4639 (match_operand:MVE_0 3 "s_register_operand" "w")]
4640 VCMLAQ_ROT90_F))
4641 ]
4642 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4643 "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
4644 [(set_attr "type" "mve_move")
4645])
4646
4647;;
4648;; [vcmpeqq_m_n_f])
4649;;
4650(define_insn "mve_vcmpeqq_m_n_f<mode>"
4651 [
4652 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4653 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4654 (match_operand:<V_elem> 2 "s_register_operand" "r")
4655 (match_operand:HI 3 "vpr_register_operand" "Up")]
4656 VCMPEQQ_M_N_F))
4657 ]
4658 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4659 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2"
4660 [(set_attr "type" "mve_move")
4661 (set_attr "length""8")])
4662
4663;;
4664;; [vcmpgeq_m_f])
4665;;
4666(define_insn "mve_vcmpgeq_m_f<mode>"
4667 [
4668 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4669 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4670 (match_operand:MVE_0 2 "s_register_operand" "w")
4671 (match_operand:HI 3 "vpr_register_operand" "Up")]
4672 VCMPGEQ_M_F))
4673 ]
4674 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4675 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2"
4676 [(set_attr "type" "mve_move")
4677 (set_attr "length""8")])
4678
4679;;
4680;; [vcmpgeq_m_n_f])
4681;;
4682(define_insn "mve_vcmpgeq_m_n_f<mode>"
4683 [
4684 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4685 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4686 (match_operand:<V_elem> 2 "s_register_operand" "r")
4687 (match_operand:HI 3 "vpr_register_operand" "Up")]
4688 VCMPGEQ_M_N_F))
4689 ]
4690 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4691 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2"
4692 [(set_attr "type" "mve_move")
4693 (set_attr "length""8")])
4694
4695;;
4696;; [vcmpgtq_m_f])
4697;;
4698(define_insn "mve_vcmpgtq_m_f<mode>"
4699 [
4700 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4701 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4702 (match_operand:MVE_0 2 "s_register_operand" "w")
4703 (match_operand:HI 3 "vpr_register_operand" "Up")]
4704 VCMPGTQ_M_F))
4705 ]
4706 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4707 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2"
4708 [(set_attr "type" "mve_move")
4709 (set_attr "length""8")])
4710
4711;;
4712;; [vcmpgtq_m_n_f])
4713;;
4714(define_insn "mve_vcmpgtq_m_n_f<mode>"
4715 [
4716 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4717 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4718 (match_operand:<V_elem> 2 "s_register_operand" "r")
4719 (match_operand:HI 3 "vpr_register_operand" "Up")]
4720 VCMPGTQ_M_N_F))
4721 ]
4722 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4723 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2"
4724 [(set_attr "type" "mve_move")
4725 (set_attr "length""8")])
4726
4727;;
4728;; [vcmpleq_m_f])
4729;;
4730(define_insn "mve_vcmpleq_m_f<mode>"
4731 [
4732 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4733 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4734 (match_operand:MVE_0 2 "s_register_operand" "w")
4735 (match_operand:HI 3 "vpr_register_operand" "Up")]
4736 VCMPLEQ_M_F))
4737 ]
4738 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4739 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2"
4740 [(set_attr "type" "mve_move")
4741 (set_attr "length""8")])
4742
4743;;
4744;; [vcmpleq_m_n_f])
4745;;
4746(define_insn "mve_vcmpleq_m_n_f<mode>"
4747 [
4748 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4749 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4750 (match_operand:<V_elem> 2 "s_register_operand" "r")
4751 (match_operand:HI 3 "vpr_register_operand" "Up")]
4752 VCMPLEQ_M_N_F))
4753 ]
4754 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4755 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2"
4756 [(set_attr "type" "mve_move")
4757 (set_attr "length""8")])
4758
4759;;
4760;; [vcmpltq_m_f])
4761;;
4762(define_insn "mve_vcmpltq_m_f<mode>"
4763 [
4764 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4765 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4766 (match_operand:MVE_0 2 "s_register_operand" "w")
4767 (match_operand:HI 3 "vpr_register_operand" "Up")]
4768 VCMPLTQ_M_F))
4769 ]
4770 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4771 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2"
4772 [(set_attr "type" "mve_move")
4773 (set_attr "length""8")])
4774
4775;;
4776;; [vcmpltq_m_n_f])
4777;;
4778(define_insn "mve_vcmpltq_m_n_f<mode>"
4779 [
4780 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4781 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4782 (match_operand:<V_elem> 2 "s_register_operand" "r")
4783 (match_operand:HI 3 "vpr_register_operand" "Up")]
4784 VCMPLTQ_M_N_F))
4785 ]
4786 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4787 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2"
4788 [(set_attr "type" "mve_move")
4789 (set_attr "length""8")])
4790
4791;;
4792;; [vcmpneq_m_f])
4793;;
4794(define_insn "mve_vcmpneq_m_f<mode>"
4795 [
4796 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4797 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4798 (match_operand:MVE_0 2 "s_register_operand" "w")
4799 (match_operand:HI 3 "vpr_register_operand" "Up")]
4800 VCMPNEQ_M_F))
4801 ]
4802 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4803 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2"
4804 [(set_attr "type" "mve_move")
4805 (set_attr "length""8")])
4806
4807;;
4808;; [vcmpneq_m_n_f])
4809;;
4810(define_insn "mve_vcmpneq_m_n_f<mode>"
4811 [
4812 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
4813 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
4814 (match_operand:<V_elem> 2 "s_register_operand" "r")
4815 (match_operand:HI 3 "vpr_register_operand" "Up")]
4816 VCMPNEQ_M_N_F))
4817 ]
4818 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4819 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2"
4820 [(set_attr "type" "mve_move")
4821 (set_attr "length""8")])
4822
4823;;
4824;; [vcvtbq_m_f16_f32])
4825;;
4826(define_insn "mve_vcvtbq_m_f16_f32v8hf"
4827 [
4828 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4829 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4830 (match_operand:V4SF 2 "s_register_operand" "w")
4831 (match_operand:HI 3 "vpr_register_operand" "Up")]
4832 VCVTBQ_M_F16_F32))
4833 ]
4834 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4835 "vpst\;vcvtbt.f16.f32 %q0, %q2"
4836 [(set_attr "type" "mve_move")
4837 (set_attr "length""8")])
4838
4839;;
4840;; [vcvtbq_m_f32_f16])
4841;;
4842(define_insn "mve_vcvtbq_m_f32_f16v4sf"
4843 [
4844 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4845 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4846 (match_operand:V8HF 2 "s_register_operand" "w")
4847 (match_operand:HI 3 "vpr_register_operand" "Up")]
4848 VCVTBQ_M_F32_F16))
4849 ]
4850 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4851 "vpst\;vcvtbt.f32.f16 %q0, %q2"
4852 [(set_attr "type" "mve_move")
4853 (set_attr "length""8")])
4854
4855;;
4856;; [vcvttq_m_f16_f32])
4857;;
4858(define_insn "mve_vcvttq_m_f16_f32v8hf"
4859 [
4860 (set (match_operand:V8HF 0 "s_register_operand" "=w")
4861 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
4862 (match_operand:V4SF 2 "s_register_operand" "w")
4863 (match_operand:HI 3 "vpr_register_operand" "Up")]
4864 VCVTTQ_M_F16_F32))
4865 ]
4866 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4867 "vpst\;vcvttt.f16.f32 %q0, %q2"
4868 [(set_attr "type" "mve_move")
4869 (set_attr "length""8")])
4870
4871;;
4872;; [vcvttq_m_f32_f16])
4873;;
4874(define_insn "mve_vcvttq_m_f32_f16v4sf"
4875 [
4876 (set (match_operand:V4SF 0 "s_register_operand" "=w")
4877 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
4878 (match_operand:V8HF 2 "s_register_operand" "w")
4879 (match_operand:HI 3 "vpr_register_operand" "Up")]
4880 VCVTTQ_M_F32_F16))
4881 ]
4882 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4883 "vpst\;vcvttt.f32.f16 %q0, %q2"
4884 [(set_attr "type" "mve_move")
4885 (set_attr "length""8")])
4886
4887;;
4888;; [vdupq_m_n_f])
4889;;
4890(define_insn "mve_vdupq_m_n_f<mode>"
4891 [
4892 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4893 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4894 (match_operand:<V_elem> 2 "s_register_operand" "r")
4895 (match_operand:HI 3 "vpr_register_operand" "Up")]
4896 VDUPQ_M_N_F))
4897 ]
4898 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4899 "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
4900 [(set_attr "type" "mve_move")
4901 (set_attr "length""8")])
4902
4903;;
4904;; [vfmaq_f])
4905;;
4906(define_insn "mve_vfmaq_f<mode>"
4907 [
4908 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4909 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4910 (match_operand:MVE_0 2 "s_register_operand" "w")
4911 (match_operand:MVE_0 3 "s_register_operand" "w")]
4912 VFMAQ_F))
4913 ]
4914 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4915 "vfma.f%#<V_sz_elem> %q0, %q2, %q3"
4916 [(set_attr "type" "mve_move")
4917])
4918
4919;;
4920;; [vfmaq_n_f])
4921;;
4922(define_insn "mve_vfmaq_n_f<mode>"
4923 [
4924 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4925 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4926 (match_operand:MVE_0 2 "s_register_operand" "w")
4927 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4928 VFMAQ_N_F))
4929 ]
4930 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4931 "vfma.f%#<V_sz_elem> %q0, %q2, %3"
4932 [(set_attr "type" "mve_move")
4933])
4934
4935;;
4936;; [vfmasq_n_f])
4937;;
4938(define_insn "mve_vfmasq_n_f<mode>"
4939 [
4940 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4941 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4942 (match_operand:MVE_0 2 "s_register_operand" "w")
4943 (match_operand:<V_elem> 3 "s_register_operand" "r")]
4944 VFMASQ_N_F))
4945 ]
4946 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4947 "vfmas.f%#<V_sz_elem> %q0, %q2, %3"
4948 [(set_attr "type" "mve_move")
4949])
4950;;
4951;; [vfmsq_f])
4952;;
4953(define_insn "mve_vfmsq_f<mode>"
4954 [
4955 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4956 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4957 (match_operand:MVE_0 2 "s_register_operand" "w")
4958 (match_operand:MVE_0 3 "s_register_operand" "w")]
4959 VFMSQ_F))
4960 ]
4961 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4962 "vfms.f%#<V_sz_elem> %q0, %q2, %q3"
4963 [(set_attr "type" "mve_move")
4964])
4965
4966;;
4967;; [vmaxnmaq_m_f])
4968;;
4969(define_insn "mve_vmaxnmaq_m_f<mode>"
4970 [
4971 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
4972 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
4973 (match_operand:MVE_0 2 "s_register_operand" "w")
4974 (match_operand:HI 3 "vpr_register_operand" "Up")]
4975 VMAXNMAQ_M_F))
4976 ]
4977 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4978 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2"
4979 [(set_attr "type" "mve_move")
4980 (set_attr "length""8")])
4981;;
4982;; [vmaxnmavq_p_f])
4983;;
4984(define_insn "mve_vmaxnmavq_p_f<mode>"
4985 [
4986 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
4987 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
4988 (match_operand:MVE_0 2 "s_register_operand" "w")
4989 (match_operand:HI 3 "vpr_register_operand" "Up")]
4990 VMAXNMAVQ_P_F))
4991 ]
4992 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4993 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2"
4994 [(set_attr "type" "mve_move")
4995 (set_attr "length""8")])
4996
4997;;
4998;; [vmaxnmvq_p_f])
4999;;
5000(define_insn "mve_vmaxnmvq_p_f<mode>"
5001 [
5002 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5003 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5004 (match_operand:MVE_0 2 "s_register_operand" "w")
5005 (match_operand:HI 3 "vpr_register_operand" "Up")]
5006 VMAXNMVQ_P_F))
5007 ]
5008 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5009 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2"
5010 [(set_attr "type" "mve_move")
5011 (set_attr "length""8")])
5012;;
5013;; [vminnmaq_m_f])
5014;;
5015(define_insn "mve_vminnmaq_m_f<mode>"
5016 [
5017 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5018 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5019 (match_operand:MVE_0 2 "s_register_operand" "w")
5020 (match_operand:HI 3 "vpr_register_operand" "Up")]
5021 VMINNMAQ_M_F))
5022 ]
5023 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5024 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2"
5025 [(set_attr "type" "mve_move")
5026 (set_attr "length""8")])
5027
5028;;
5029;; [vminnmavq_p_f])
5030;;
5031(define_insn "mve_vminnmavq_p_f<mode>"
5032 [
5033 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5034 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5035 (match_operand:MVE_0 2 "s_register_operand" "w")
5036 (match_operand:HI 3 "vpr_register_operand" "Up")]
5037 VMINNMAVQ_P_F))
5038 ]
5039 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5040 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2"
5041 [(set_attr "type" "mve_move")
5042 (set_attr "length""8")])
5043;;
5044;; [vminnmvq_p_f])
5045;;
5046(define_insn "mve_vminnmvq_p_f<mode>"
5047 [
5048 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
5049 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
5050 (match_operand:MVE_0 2 "s_register_operand" "w")
5051 (match_operand:HI 3 "vpr_register_operand" "Up")]
5052 VMINNMVQ_P_F))
5053 ]
5054 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5055 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2"
5056 [(set_attr "type" "mve_move")
5057 (set_attr "length""8")])
5058
5059;;
5060;; [vmlaldavaq_s, vmlaldavaq_u])
5061;;
5062(define_insn "mve_vmlaldavaq_<supf><mode>"
5063 [
5064 (set (match_operand:DI 0 "s_register_operand" "=r")
5065 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5066 (match_operand:MVE_5 2 "s_register_operand" "w")
5067 (match_operand:MVE_5 3 "s_register_operand" "w")]
5068 VMLALDAVAQ))
5069 ]
5070 "TARGET_HAVE_MVE"
5071 "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5072 [(set_attr "type" "mve_move")
5073])
5074
5075;;
5076;; [vmlaldavaxq_s])
5077;;
5078(define_insn "mve_vmlaldavaxq_s<mode>"
5079 [
5080 (set (match_operand:DI 0 "s_register_operand" "=r")
5081 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5082 (match_operand:MVE_5 2 "s_register_operand" "w")
5083 (match_operand:MVE_5 3 "s_register_operand" "w")]
5084 VMLALDAVAXQ_S))
5085 ]
5086 "TARGET_HAVE_MVE"
5087 "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5088 [(set_attr "type" "mve_move")
5089])
5090
5091;;
5092;; [vmlaldavq_p_u, vmlaldavq_p_s])
5093;;
5094(define_insn "mve_vmlaldavq_p_<supf><mode>"
5095 [
5096 (set (match_operand:DI 0 "s_register_operand" "=r")
5097 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5098 (match_operand:MVE_5 2 "s_register_operand" "w")
5099 (match_operand:HI 3 "vpr_register_operand" "Up")]
5100 VMLALDAVQ_P))
5101 ]
5102 "TARGET_HAVE_MVE"
5103 "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5104 [(set_attr "type" "mve_move")
5105 (set_attr "length""8")])
5106
5107;;
5108;; [vmlaldavxq_p_s])
5109;;
5110(define_insn "mve_vmlaldavxq_p_s<mode>"
5111 [
5112 (set (match_operand:DI 0 "s_register_operand" "=r")
5113 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5114 (match_operand:MVE_5 2 "s_register_operand" "w")
5115 (match_operand:HI 3 "vpr_register_operand" "Up")]
5116 VMLALDAVXQ_P_S))
5117 ]
5118 "TARGET_HAVE_MVE"
5119 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
5120 [(set_attr "type" "mve_move")
5121 (set_attr "length""8")])
5122;;
5123;; [vmlsldavaq_s])
5124;;
5125(define_insn "mve_vmlsldavaq_s<mode>"
5126 [
5127 (set (match_operand:DI 0 "s_register_operand" "=r")
5128 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5129 (match_operand:MVE_5 2 "s_register_operand" "w")
5130 (match_operand:MVE_5 3 "s_register_operand" "w")]
5131 VMLSLDAVAQ_S))
5132 ]
5133 "TARGET_HAVE_MVE"
5134 "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5135 [(set_attr "type" "mve_move")
5136])
5137
5138;;
5139;; [vmlsldavaxq_s])
5140;;
5141(define_insn "mve_vmlsldavaxq_s<mode>"
5142 [
5143 (set (match_operand:DI 0 "s_register_operand" "=r")
5144 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5145 (match_operand:MVE_5 2 "s_register_operand" "w")
5146 (match_operand:MVE_5 3 "s_register_operand" "w")]
5147 VMLSLDAVAXQ_S))
5148 ]
5149 "TARGET_HAVE_MVE"
5150 "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
5151 [(set_attr "type" "mve_move")
5152])
5153
5154;;
5155;; [vmlsldavq_p_s])
5156;;
5157(define_insn "mve_vmlsldavq_p_s<mode>"
5158 [
5159 (set (match_operand:DI 0 "s_register_operand" "=r")
5160 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5161 (match_operand:MVE_5 2 "s_register_operand" "w")
5162 (match_operand:HI 3 "vpr_register_operand" "Up")]
5163 VMLSLDAVQ_P_S))
5164 ]
5165 "TARGET_HAVE_MVE"
5166 "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5167 [(set_attr "type" "mve_move")
5168 (set_attr "length""8")])
5169
5170;;
5171;; [vmlsldavxq_p_s])
5172;;
5173(define_insn "mve_vmlsldavxq_p_s<mode>"
5174 [
5175 (set (match_operand:DI 0 "s_register_operand" "=r")
5176 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
5177 (match_operand:MVE_5 2 "s_register_operand" "w")
5178 (match_operand:HI 3 "vpr_register_operand" "Up")]
5179 VMLSLDAVXQ_P_S))
5180 ]
5181 "TARGET_HAVE_MVE"
5182 "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
5183 [(set_attr "type" "mve_move")
5184 (set_attr "length""8")])
5185;;
5186;; [vmovlbq_m_u, vmovlbq_m_s])
5187;;
5188(define_insn "mve_vmovlbq_m_<supf><mode>"
5189 [
5190 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5191 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5192 (match_operand:MVE_3 2 "s_register_operand" "w")
5193 (match_operand:HI 3 "vpr_register_operand" "Up")]
5194 VMOVLBQ_M))
5195 ]
5196 "TARGET_HAVE_MVE"
5197 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2"
5198 [(set_attr "type" "mve_move")
5199 (set_attr "length""8")])
5200;;
5201;; [vmovltq_m_u, vmovltq_m_s])
5202;;
5203(define_insn "mve_vmovltq_m_<supf><mode>"
5204 [
5205 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
5206 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
5207 (match_operand:MVE_3 2 "s_register_operand" "w")
5208 (match_operand:HI 3 "vpr_register_operand" "Up")]
5209 VMOVLTQ_M))
5210 ]
5211 "TARGET_HAVE_MVE"
5212 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2"
5213 [(set_attr "type" "mve_move")
5214 (set_attr "length""8")])
5215;;
5216;; [vmovnbq_m_u, vmovnbq_m_s])
5217;;
5218(define_insn "mve_vmovnbq_m_<supf><mode>"
5219 [
5220 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5221 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5222 (match_operand:MVE_5 2 "s_register_operand" "w")
5223 (match_operand:HI 3 "vpr_register_operand" "Up")]
5224 VMOVNBQ_M))
5225 ]
5226 "TARGET_HAVE_MVE"
5227 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2"
5228 [(set_attr "type" "mve_move")
5229 (set_attr "length""8")])
5230
5231;;
5232;; [vmovntq_m_u, vmovntq_m_s])
5233;;
5234(define_insn "mve_vmovntq_m_<supf><mode>"
5235 [
5236 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5237 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5238 (match_operand:MVE_5 2 "s_register_operand" "w")
5239 (match_operand:HI 3 "vpr_register_operand" "Up")]
5240 VMOVNTQ_M))
5241 ]
5242 "TARGET_HAVE_MVE"
5243 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2"
5244 [(set_attr "type" "mve_move")
5245 (set_attr "length""8")])
5246
5247;;
5248;; [vmvnq_m_n_u, vmvnq_m_n_s])
5249;;
5250(define_insn "mve_vmvnq_m_n_<supf><mode>"
5251 [
5252 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5253 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5254 (match_operand:SI 2 "immediate_operand" "i")
5255 (match_operand:HI 3 "vpr_register_operand" "Up")]
5256 VMVNQ_M_N))
5257 ]
5258 "TARGET_HAVE_MVE"
5259 "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
5260 [(set_attr "type" "mve_move")
5261 (set_attr "length""8")])
5262;;
5263;; [vnegq_m_f])
5264;;
5265(define_insn "mve_vnegq_m_f<mode>"
5266 [
5267 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5268 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5269 (match_operand:MVE_0 2 "s_register_operand" "w")
5270 (match_operand:HI 3 "vpr_register_operand" "Up")]
5271 VNEGQ_M_F))
5272 ]
5273 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5274 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2"
5275 [(set_attr "type" "mve_move")
5276 (set_attr "length""8")])
5277
5278;;
5279;; [vorrq_m_n_s, vorrq_m_n_u])
5280;;
5281(define_insn "mve_vorrq_m_n_<supf><mode>"
5282 [
5283 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5284 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5285 (match_operand:SI 2 "immediate_operand" "i")
5286 (match_operand:HI 3 "vpr_register_operand" "Up")]
5287 VORRQ_M_N))
5288 ]
5289 "TARGET_HAVE_MVE"
5290 "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
5291 [(set_attr "type" "mve_move")
5292 (set_attr "length""8")])
5293;;
5294;; [vpselq_f])
5295;;
5296(define_insn "mve_vpselq_f<mode>"
5297 [
5298 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5299 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
5300 (match_operand:MVE_0 2 "s_register_operand" "w")
5301 (match_operand:HI 3 "vpr_register_operand" "Up")]
5302 VPSELQ_F))
5303 ]
5304 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5305 "vpsel %q0, %q1, %q2"
5306 [(set_attr "type" "mve_move")
5307])
5308
5309;;
5310;; [vqmovnbq_m_s, vqmovnbq_m_u])
5311;;
5312(define_insn "mve_vqmovnbq_m_<supf><mode>"
5313 [
5314 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5315 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5316 (match_operand:MVE_5 2 "s_register_operand" "w")
5317 (match_operand:HI 3 "vpr_register_operand" "Up")]
5318 VQMOVNBQ_M))
5319 ]
5320 "TARGET_HAVE_MVE"
5321 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2"
5322 [(set_attr "type" "mve_move")
5323 (set_attr "length""8")])
5324
5325;;
5326;; [vqmovntq_m_u, vqmovntq_m_s])
5327;;
5328(define_insn "mve_vqmovntq_m_<supf><mode>"
5329 [
5330 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5331 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5332 (match_operand:MVE_5 2 "s_register_operand" "w")
5333 (match_operand:HI 3 "vpr_register_operand" "Up")]
5334 VQMOVNTQ_M))
5335 ]
5336 "TARGET_HAVE_MVE"
5337 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2"
5338 [(set_attr "type" "mve_move")
5339 (set_attr "length""8")])
5340
5341;;
5342;; [vqmovunbq_m_s])
5343;;
5344(define_insn "mve_vqmovunbq_m_s<mode>"
5345 [
5346 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5347 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5348 (match_operand:MVE_5 2 "s_register_operand" "w")
5349 (match_operand:HI 3 "vpr_register_operand" "Up")]
5350 VQMOVUNBQ_M_S))
5351 ]
5352 "TARGET_HAVE_MVE"
5353 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2"
5354 [(set_attr "type" "mve_move")
5355 (set_attr "length""8")])
5356
5357;;
5358;; [vqmovuntq_m_s])
5359;;
5360(define_insn "mve_vqmovuntq_m_s<mode>"
5361 [
5362 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5363 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5364 (match_operand:MVE_5 2 "s_register_operand" "w")
5365 (match_operand:HI 3 "vpr_register_operand" "Up")]
5366 VQMOVUNTQ_M_S))
5367 ]
5368 "TARGET_HAVE_MVE"
5369 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2"
5370 [(set_attr "type" "mve_move")
5371 (set_attr "length""8")])
5372
5373;;
5374;; [vqrshrntq_n_u, vqrshrntq_n_s])
5375;;
5376(define_insn "mve_vqrshrntq_n_<supf><mode>"
5377 [
5378 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5379 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5380 (match_operand:MVE_5 2 "s_register_operand" "w")
5381 (match_operand:SI 3 "mve_imm_8" "Rb")]
5382 VQRSHRNTQ_N))
5383 ]
5384 "TARGET_HAVE_MVE"
5385 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5386 [(set_attr "type" "mve_move")
5387])
5388
5389;;
5390;; [vqrshruntq_n_s])
5391;;
5392(define_insn "mve_vqrshruntq_n_s<mode>"
5393 [
5394 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5395 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5396 (match_operand:MVE_5 2 "s_register_operand" "w")
5397 (match_operand:SI 3 "mve_imm_8" "Rb")]
5398 VQRSHRUNTQ_N_S))
5399 ]
5400 "TARGET_HAVE_MVE"
5401 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5402 [(set_attr "type" "mve_move")
5403])
5404
5405;;
5406;; [vqshrnbq_n_u, vqshrnbq_n_s])
5407;;
5408(define_insn "mve_vqshrnbq_n_<supf><mode>"
5409 [
5410 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5411 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5412 (match_operand:MVE_5 2 "s_register_operand" "w")
5413 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")]
5414 VQSHRNBQ_N))
5415 ]
5416 "TARGET_HAVE_MVE"
5417 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5418 [(set_attr "type" "mve_move")
5419])
5420
5421;;
5422;; [vqshrntq_n_u, vqshrntq_n_s])
5423;;
5424(define_insn "mve_vqshrntq_n_<supf><mode>"
5425 [
5426 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5427 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5428 (match_operand:MVE_5 2 "s_register_operand" "w")
5429 (match_operand:SI 3 "mve_imm_8" "Rb")]
5430 VQSHRNTQ_N))
5431 ]
5432 "TARGET_HAVE_MVE"
5433 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3"
5434 [(set_attr "type" "mve_move")
5435])
5436
5437;;
5438;; [vqshrunbq_n_s])
5439;;
5440(define_insn "mve_vqshrunbq_n_s<mode>"
5441 [
5442 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5443 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5444 (match_operand:MVE_5 2 "s_register_operand" "w")
5445 (match_operand:SI 3 "immediate_operand" "i")]
5446 VQSHRUNBQ_N_S))
5447 ]
5448 "TARGET_HAVE_MVE"
5449 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3"
5450 [(set_attr "type" "mve_move")
5451])
5452
5453;;
5454;; [vqshruntq_n_s])
5455;;
5456(define_insn "mve_vqshruntq_n_s<mode>"
5457 [
5458 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5459 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5460 (match_operand:MVE_5 2 "s_register_operand" "w")
5461 (match_operand:SI 3 "mve_imm_8" "Rb")]
5462 VQSHRUNTQ_N_S))
5463 ]
5464 "TARGET_HAVE_MVE"
5465 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3"
5466 [(set_attr "type" "mve_move")
5467])
5468
5469;;
5470;; [vrev32q_m_f])
5471;;
5472(define_insn "mve_vrev32q_m_fv8hf"
5473 [
5474 (set (match_operand:V8HF 0 "s_register_operand" "=w")
5475 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
5476 (match_operand:V8HF 2 "s_register_operand" "w")
5477 (match_operand:HI 3 "vpr_register_operand" "Up")]
5478 VREV32Q_M_F))
5479 ]
5480 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5481 "vpst\;vrev32t.16 %q0, %q2"
5482 [(set_attr "type" "mve_move")
5483 (set_attr "length""8")])
5484
5485;;
5486;; [vrev32q_m_s, vrev32q_m_u])
5487;;
5488(define_insn "mve_vrev32q_m_<supf><mode>"
5489 [
5490 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
5491 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
5492 (match_operand:MVE_3 2 "s_register_operand" "w")
5493 (match_operand:HI 3 "vpr_register_operand" "Up")]
5494 VREV32Q_M))
5495 ]
5496 "TARGET_HAVE_MVE"
5497 "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
5498 [(set_attr "type" "mve_move")
5499 (set_attr "length""8")])
5500
5501;;
5502;; [vrev64q_m_f])
5503;;
5504(define_insn "mve_vrev64q_m_f<mode>"
5505 [
5506 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5507 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5508 (match_operand:MVE_0 2 "s_register_operand" "w")
5509 (match_operand:HI 3 "vpr_register_operand" "Up")]
5510 VREV64Q_M_F))
5511 ]
5512 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5513 "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
5514 [(set_attr "type" "mve_move")
5515 (set_attr "length""8")])
5516
5517;;
5518;; [vrmlaldavhaxq_s])
5519;;
5520(define_insn "mve_vrmlaldavhaxq_sv4si"
5521 [
5522 (set (match_operand:DI 0 "s_register_operand" "=r")
5523 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5524 (match_operand:V4SI 2 "s_register_operand" "w")
5525 (match_operand:V4SI 3 "s_register_operand" "w")]
5526 VRMLALDAVHAXQ_S))
5527 ]
5528 "TARGET_HAVE_MVE"
5529 "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
5530 [(set_attr "type" "mve_move")
5531])
5532
5533;;
5534;; [vrmlaldavhxq_p_s])
5535;;
5536(define_insn "mve_vrmlaldavhxq_p_sv4si"
5537 [
5538 (set (match_operand:DI 0 "s_register_operand" "=r")
5539 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5540 (match_operand:V4SI 2 "s_register_operand" "w")
5541 (match_operand:HI 3 "vpr_register_operand" "Up")]
5542 VRMLALDAVHXQ_P_S))
5543 ]
5544 "TARGET_HAVE_MVE"
5545 "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
5546 [(set_attr "type" "mve_move")
5547 (set_attr "length""8")])
5548
5549;;
5550;; [vrmlsldavhaxq_s])
5551;;
5552(define_insn "mve_vrmlsldavhaxq_sv4si"
5553 [
5554 (set (match_operand:DI 0 "s_register_operand" "=r")
5555 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5556 (match_operand:V4SI 2 "s_register_operand" "w")
5557 (match_operand:V4SI 3 "s_register_operand" "w")]
5558 VRMLSLDAVHAXQ_S))
5559 ]
5560 "TARGET_HAVE_MVE"
5561 "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
5562 [(set_attr "type" "mve_move")
5563])
5564
5565;;
5566;; [vrmlsldavhq_p_s])
5567;;
5568(define_insn "mve_vrmlsldavhq_p_sv4si"
5569 [
5570 (set (match_operand:DI 0 "s_register_operand" "=r")
5571 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5572 (match_operand:V4SI 2 "s_register_operand" "w")
5573 (match_operand:HI 3 "vpr_register_operand" "Up")]
5574 VRMLSLDAVHQ_P_S))
5575 ]
5576 "TARGET_HAVE_MVE"
5577 "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
5578 [(set_attr "type" "mve_move")
5579 (set_attr "length""8")])
5580
5581;;
5582;; [vrmlsldavhxq_p_s])
5583;;
5584(define_insn "mve_vrmlsldavhxq_p_sv4si"
5585 [
5586 (set (match_operand:DI 0 "s_register_operand" "=r")
5587 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5588 (match_operand:V4SI 2 "s_register_operand" "w")
5589 (match_operand:HI 3 "vpr_register_operand" "Up")]
5590 VRMLSLDAVHXQ_P_S))
5591 ]
5592 "TARGET_HAVE_MVE"
5593 "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
5594 [(set_attr "type" "mve_move")
5595 (set_attr "length""8")])
5596
5597;;
5598;; [vrndaq_m_f])
5599;;
5600(define_insn "mve_vrndaq_m_f<mode>"
5601 [
5602 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5603 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5604 (match_operand:MVE_0 2 "s_register_operand" "w")
5605 (match_operand:HI 3 "vpr_register_operand" "Up")]
5606 VRNDAQ_M_F))
5607 ]
5608 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5609 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2"
5610 [(set_attr "type" "mve_move")
5611 (set_attr "length""8")])
5612
5613;;
5614;; [vrndmq_m_f])
5615;;
5616(define_insn "mve_vrndmq_m_f<mode>"
5617 [
5618 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5619 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5620 (match_operand:MVE_0 2 "s_register_operand" "w")
5621 (match_operand:HI 3 "vpr_register_operand" "Up")]
5622 VRNDMQ_M_F))
5623 ]
5624 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5625 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2"
5626 [(set_attr "type" "mve_move")
5627 (set_attr "length""8")])
5628
5629;;
5630;; [vrndnq_m_f])
5631;;
5632(define_insn "mve_vrndnq_m_f<mode>"
5633 [
5634 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5635 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5636 (match_operand:MVE_0 2 "s_register_operand" "w")
5637 (match_operand:HI 3 "vpr_register_operand" "Up")]
5638 VRNDNQ_M_F))
5639 ]
5640 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5641 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2"
5642 [(set_attr "type" "mve_move")
5643 (set_attr "length""8")])
5644
5645;;
5646;; [vrndpq_m_f])
5647;;
5648(define_insn "mve_vrndpq_m_f<mode>"
5649 [
5650 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5651 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5652 (match_operand:MVE_0 2 "s_register_operand" "w")
5653 (match_operand:HI 3 "vpr_register_operand" "Up")]
5654 VRNDPQ_M_F))
5655 ]
5656 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5657 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2"
5658 [(set_attr "type" "mve_move")
5659 (set_attr "length""8")])
5660
5661;;
5662;; [vrndxq_m_f])
5663;;
5664(define_insn "mve_vrndxq_m_f<mode>"
5665 [
5666 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5667 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5668 (match_operand:MVE_0 2 "s_register_operand" "w")
5669 (match_operand:HI 3 "vpr_register_operand" "Up")]
5670 VRNDXQ_M_F))
5671 ]
5672 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5673 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2"
5674 [(set_attr "type" "mve_move")
5675 (set_attr "length""8")])
5676
5677;;
5678;; [vrshrnbq_n_s, vrshrnbq_n_u])
5679;;
5680(define_insn "mve_vrshrnbq_n_<supf><mode>"
5681 [
5682 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5683 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5684 (match_operand:MVE_5 2 "s_register_operand" "w")
5685 (match_operand:SI 3 "mve_imm_8" "Rb")]
5686 VRSHRNBQ_N))
5687 ]
5688 "TARGET_HAVE_MVE"
5689 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5690 [(set_attr "type" "mve_move")
5691])
5692
5693;;
5694;; [vrshrntq_n_u, vrshrntq_n_s])
5695;;
5696(define_insn "mve_vrshrntq_n_<supf><mode>"
5697 [
5698 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5699 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5700 (match_operand:MVE_5 2 "s_register_operand" "w")
5701 (match_operand:SI 3 "mve_imm_8" "Rb")]
5702 VRSHRNTQ_N))
5703 ]
5704 "TARGET_HAVE_MVE"
5705 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3"
5706 [(set_attr "type" "mve_move")
5707])
5708
5709;;
5710;; [vshrnbq_n_u, vshrnbq_n_s])
5711;;
5712(define_insn "mve_vshrnbq_n_<supf><mode>"
5713 [
5714 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5715 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5716 (match_operand:MVE_5 2 "s_register_operand" "w")
5717 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5718 VSHRNBQ_N))
5719 ]
5720 "TARGET_HAVE_MVE"
5721 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3"
5722 [(set_attr "type" "mve_move")
5723])
5724
5725;;
5726;; [vshrntq_n_s, vshrntq_n_u])
5727;;
5728(define_insn "mve_vshrntq_n_<supf><mode>"
5729 [
5730 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
5731 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
5732 (match_operand:MVE_5 2 "s_register_operand" "w")
5733 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
5734 VSHRNTQ_N))
5735 ]
5736 "TARGET_HAVE_MVE"
db5db9d2 5737 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5738 [(set_attr "type" "mve_move")
5739])
5740
5741;;
5742;; [vcvtmq_m_s, vcvtmq_m_u])
5743;;
5744(define_insn "mve_vcvtmq_m_<supf><mode>"
5745 [
5746 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5747 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5748 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5749 (match_operand:HI 3 "vpr_register_operand" "Up")]
5750 VCVTMQ_M))
5751 ]
5752 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5753 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5754 [(set_attr "type" "mve_move")
5755 (set_attr "length""8")])
5756
5757;;
5758;; [vcvtpq_m_u, vcvtpq_m_s])
5759;;
5760(define_insn "mve_vcvtpq_m_<supf><mode>"
5761 [
5762 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5763 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5764 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5765 (match_operand:HI 3 "vpr_register_operand" "Up")]
5766 VCVTPQ_M))
5767 ]
5768 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5769 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5770 [(set_attr "type" "mve_move")
5771 (set_attr "length""8")])
5772
5773;;
5774;; [vcvtnq_m_s, vcvtnq_m_u])
5775;;
5776(define_insn "mve_vcvtnq_m_<supf><mode>"
5777 [
5778 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5779 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5780 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5781 (match_operand:HI 3 "vpr_register_operand" "Up")]
5782 VCVTNQ_M))
5783 ]
5784 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5785 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5786 [(set_attr "type" "mve_move")
5787 (set_attr "length""8")])
5788
5789;;
5790;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
5791;;
5792(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
5793 [
5794 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5795 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5796 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5797 (match_operand:SI 3 "mve_imm_16" "Rd")
5798 (match_operand:HI 4 "vpr_register_operand" "Up")]
5799 VCVTQ_M_N_FROM_F))
5800 ]
5801 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5802 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
e3678b44
SP		 5803 [(set_attr "type" "mve_move")
5804 (set_attr "length""8")])
5805
5806;;
5807;; [vrev16q_m_u, vrev16q_m_s])
5808;;
5809(define_insn "mve_vrev16q_m_<supf>v16qi"
5810 [
5811 (set (match_operand:V16QI 0 "s_register_operand" "=w")
5812 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
5813 (match_operand:V16QI 2 "s_register_operand" "w")
5814 (match_operand:HI 3 "vpr_register_operand" "Up")]
5815 VREV16Q_M))
5816 ]
5817 "TARGET_HAVE_MVE"
5818 "vpst\;vrev16t.8 %q0, %q2"
5819 [(set_attr "type" "mve_move")
5820 (set_attr "length""8")])
5821
5822;;
5823;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
5824;;
5825(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
5826 [
5827 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
5828 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
5829 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5830 (match_operand:HI 3 "vpr_register_operand" "Up")]
5831 VCVTQ_M_FROM_F))
5832 ]
5833 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
db5db9d2 5834 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
e3678b44
SP		 5835 [(set_attr "type" "mve_move")
5836 (set_attr "length""8")])
5837
5838;;
5839;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
5840;;
5841(define_insn "mve_vrmlaldavhq_p_<supf>v4si"
5842 [
5843 (set (match_operand:DI 0 "s_register_operand" "=r")
5844 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
5845 (match_operand:V4SI 2 "s_register_operand" "w")
5846 (match_operand:HI 3 "vpr_register_operand" "Up")]
5847 VRMLALDAVHQ_P))
5848 ]
5849 "TARGET_HAVE_MVE"
5850 "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
5851 [(set_attr "type" "mve_move")
5852 (set_attr "length""8")])
5853
5854;;
5855;; [vrmlsldavhaq_s])
5856;;
5857(define_insn "mve_vrmlsldavhaq_sv4si"
5858 [
5859 (set (match_operand:DI 0 "s_register_operand" "=r")
5860 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
5861 (match_operand:V4SI 2 "s_register_operand" "w")
5862 (match_operand:V4SI 3 "s_register_operand" "w")]
5863 VRMLSLDAVHAQ_S))
5864 ]
5865 "TARGET_HAVE_MVE"
5866 "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
5867 [(set_attr "type" "mve_move")
5868])
db5db9d2
SP		 5869
5870;;
5871;; [vabavq_p_s, vabavq_p_u])
5872;;
5873(define_insn "mve_vabavq_p_<supf><mode>"
5874 [
5875 (set (match_operand:SI 0 "s_register_operand" "=r")
5876 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
5877 (match_operand:MVE_2 2 "s_register_operand" "w")
5878 (match_operand:MVE_2 3 "s_register_operand" "w")
5879 (match_operand:HI 4 "vpr_register_operand" "Up")]
5880 VABAVQ_P))
5881 ]
5882 "TARGET_HAVE_MVE"
5883 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
5884 [(set_attr "type" "mve_move")
5885])
5886
5887;;
5888;; [vqshluq_m_n_s])
5889;;
5890(define_insn "mve_vqshluq_m_n_s<mode>"
5891 [
5892 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5893 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5894 (match_operand:MVE_2 2 "s_register_operand" "w")
5895 (match_operand:SI 3 "mve_imm_7" "Ra")
5896 (match_operand:HI 4 "vpr_register_operand" "Up")]
5897 VQSHLUQ_M_N_S))
5898 ]
5899 "TARGET_HAVE_MVE"
5900 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
5901 [(set_attr "type" "mve_move")])
5902
5903;;
5904;; [vshlq_m_s, vshlq_m_u])
5905;;
5906(define_insn "mve_vshlq_m_<supf><mode>"
5907 [
5908 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5909 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5910 (match_operand:MVE_2 2 "s_register_operand" "w")
5911 (match_operand:MVE_2 3 "s_register_operand" "w")
5912 (match_operand:HI 4 "vpr_register_operand" "Up")]
5913 VSHLQ_M))
5914 ]
5915 "TARGET_HAVE_MVE"
5916 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
5917 [(set_attr "type" "mve_move")])
5918
5919;;
5920;; [vsriq_m_n_s, vsriq_m_n_u])
5921;;
5922(define_insn "mve_vsriq_m_n_<supf><mode>"
5923 [
5924 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5925 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5926 (match_operand:MVE_2 2 "s_register_operand" "w")
5927 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")
5928 (match_operand:HI 4 "vpr_register_operand" "Up")]
5929 VSRIQ_M_N))
5930 ]
5931 "TARGET_HAVE_MVE"
5932 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
5933 [(set_attr "type" "mve_move")])
5934
5935;;
5936;; [vsubq_m_u, vsubq_m_s])
5937;;
5938(define_insn "mve_vsubq_m_<supf><mode>"
5939 [
5940 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5941 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5942 (match_operand:MVE_2 2 "s_register_operand" "w")
5943 (match_operand:MVE_2 3 "s_register_operand" "w")
5944 (match_operand:HI 4 "vpr_register_operand" "Up")]
5945 VSUBQ_M))
5946 ]
5947 "TARGET_HAVE_MVE"
5948 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
5949 [(set_attr "type" "mve_move")])
5950
5951;;
5952;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
5953;;
5954(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
5955 [
5956 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
5957 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
5958 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
5959 (match_operand:SI 3 "mve_imm_16" "Rd")
5960 (match_operand:HI 4 "vpr_register_operand" "Up")]
5961 VCVTQ_M_N_TO_F))
5962 ]
5963 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5964 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
5965 [(set_attr "type" "mve_move")
5966 (set_attr "length""8")])
8eb3b6b9
SP		 5967;;
5968;; [vabdq_m_s, vabdq_m_u])
5969;;
5970(define_insn "mve_vabdq_m_<supf><mode>"
5971 [
5972 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5973 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5974 (match_operand:MVE_2 2 "s_register_operand" "w")
5975 (match_operand:MVE_2 3 "s_register_operand" "w")
5976 (match_operand:HI 4 "vpr_register_operand" "Up")]
5977 VABDQ_M))
5978 ]
5979 "TARGET_HAVE_MVE"
5980 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
5981 [(set_attr "type" "mve_move")
5982 (set_attr "length""8")])
5983
5984;;
5985;; [vaddq_m_n_s, vaddq_m_n_u])
5986;;
5987(define_insn "mve_vaddq_m_n_<supf><mode>"
5988 [
5989 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
5990 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5991 (match_operand:MVE_2 2 "s_register_operand" "w")
5992 (match_operand:<V_elem> 3 "s_register_operand" "r")
5993 (match_operand:HI 4 "vpr_register_operand" "Up")]
5994 VADDQ_M_N))
5995 ]
5996 "TARGET_HAVE_MVE"
5997 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
5998 [(set_attr "type" "mve_move")
5999 (set_attr "length""8")])
6000
6001;;
6002;; [vaddq_m_u, vaddq_m_s])
6003;;
6004(define_insn "mve_vaddq_m_<supf><mode>"
6005 [
6006 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6007 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6008 (match_operand:MVE_2 2 "s_register_operand" "w")
6009 (match_operand:MVE_2 3 "s_register_operand" "w")
6010 (match_operand:HI 4 "vpr_register_operand" "Up")]
6011 VADDQ_M))
6012 ]
6013 "TARGET_HAVE_MVE"
6014 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
6015 [(set_attr "type" "mve_move")
6016 (set_attr "length""8")])
6017
6018;;
6019;; [vandq_m_u, vandq_m_s])
6020;;
6021(define_insn "mve_vandq_m_<supf><mode>"
6022 [
6023 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6024 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6025 (match_operand:MVE_2 2 "s_register_operand" "w")
6026 (match_operand:MVE_2 3 "s_register_operand" "w")
6027 (match_operand:HI 4 "vpr_register_operand" "Up")]
6028 VANDQ_M))
6029 ]
6030 "TARGET_HAVE_MVE"
6031 "vpst\;vandt %q0, %q2, %q3"
6032 [(set_attr "type" "mve_move")
6033 (set_attr "length""8")])
6034
6035;;
6036;; [vbicq_m_u, vbicq_m_s])
6037;;
6038(define_insn "mve_vbicq_m_<supf><mode>"
6039 [
6040 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6041 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6042 (match_operand:MVE_2 2 "s_register_operand" "w")
6043 (match_operand:MVE_2 3 "s_register_operand" "w")
6044 (match_operand:HI 4 "vpr_register_operand" "Up")]
6045 VBICQ_M))
6046 ]
6047 "TARGET_HAVE_MVE"
6048 "vpst\;vbict %q0, %q2, %q3"
6049 [(set_attr "type" "mve_move")
6050 (set_attr "length""8")])
6051
6052;;
6053;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
6054;;
6055(define_insn "mve_vbrsrq_m_n_<supf><mode>"
6056 [
6057 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6058 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6059 (match_operand:MVE_2 2 "s_register_operand" "w")
6060 (match_operand:SI 3 "s_register_operand" "r")
6061 (match_operand:HI 4 "vpr_register_operand" "Up")]
6062 VBRSRQ_M_N))
6063 ]
6064 "TARGET_HAVE_MVE"
6065 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
6066 [(set_attr "type" "mve_move")
6067 (set_attr "length""8")])
6068
6069;;
6070;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
6071;;
6072(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
6073 [
6074 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6075 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6076 (match_operand:MVE_2 2 "s_register_operand" "w")
6077 (match_operand:MVE_2 3 "s_register_operand" "w")
6078 (match_operand:HI 4 "vpr_register_operand" "Up")]
6079 VCADDQ_ROT270_M))
6080 ]
6081 "TARGET_HAVE_MVE"
6082 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
6083 [(set_attr "type" "mve_move")
6084 (set_attr "length""8")])
6085
6086;;
6087;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
6088;;
6089(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
6090 [
6091 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6092 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6093 (match_operand:MVE_2 2 "s_register_operand" "w")
6094 (match_operand:MVE_2 3 "s_register_operand" "w")
6095 (match_operand:HI 4 "vpr_register_operand" "Up")]
6096 VCADDQ_ROT90_M))
6097 ]
6098 "TARGET_HAVE_MVE"
6099 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
6100 [(set_attr "type" "mve_move")
6101 (set_attr "length""8")])
6102
6103;;
6104;; [veorq_m_s, veorq_m_u])
6105;;
6106(define_insn "mve_veorq_m_<supf><mode>"
6107 [
6108 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6109 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6110 (match_operand:MVE_2 2 "s_register_operand" "w")
6111 (match_operand:MVE_2 3 "s_register_operand" "w")
6112 (match_operand:HI 4 "vpr_register_operand" "Up")]
6113 VEORQ_M))
6114 ]
6115 "TARGET_HAVE_MVE"
6116 "vpst\;veort %q0, %q2, %q3"
6117 [(set_attr "type" "mve_move")
6118 (set_attr "length""8")])
6119
6120;;
6121;; [vhaddq_m_n_s, vhaddq_m_n_u])
6122;;
6123(define_insn "mve_vhaddq_m_n_<supf><mode>"
6124 [
6125 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6126 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6127 (match_operand:MVE_2 2 "s_register_operand" "w")
6128 (match_operand:<V_elem> 3 "s_register_operand" "r")
6129 (match_operand:HI 4 "vpr_register_operand" "Up")]
6130 VHADDQ_M_N))
6131 ]
6132 "TARGET_HAVE_MVE"
6133 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6134 [(set_attr "type" "mve_move")
6135 (set_attr "length""8")])
6136
6137;;
6138;; [vhaddq_m_s, vhaddq_m_u])
6139;;
6140(define_insn "mve_vhaddq_m_<supf><mode>"
6141 [
6142 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6143 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6144 (match_operand:MVE_2 2 "s_register_operand" "w")
6145 (match_operand:MVE_2 3 "s_register_operand" "w")
6146 (match_operand:HI 4 "vpr_register_operand" "Up")]
6147 VHADDQ_M))
6148 ]
6149 "TARGET_HAVE_MVE"
6150 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6151 [(set_attr "type" "mve_move")
6152 (set_attr "length""8")])
6153
6154;;
6155;; [vhsubq_m_n_s, vhsubq_m_n_u])
6156;;
6157(define_insn "mve_vhsubq_m_n_<supf><mode>"
6158 [
6159 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6160 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6161 (match_operand:MVE_2 2 "s_register_operand" "w")
6162 (match_operand:<V_elem> 3 "s_register_operand" "r")
6163 (match_operand:HI 4 "vpr_register_operand" "Up")]
6164 VHSUBQ_M_N))
6165 ]
6166 "TARGET_HAVE_MVE"
6167 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
6168 [(set_attr "type" "mve_move")
6169 (set_attr "length""8")])
6170
6171;;
6172;; [vhsubq_m_s, vhsubq_m_u])
6173;;
6174(define_insn "mve_vhsubq_m_<supf><mode>"
6175 [
6176 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6177 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6178 (match_operand:MVE_2 2 "s_register_operand" "w")
6179 (match_operand:MVE_2 3 "s_register_operand" "w")
6180 (match_operand:HI 4 "vpr_register_operand" "Up")]
6181 VHSUBQ_M))
6182 ]
6183 "TARGET_HAVE_MVE"
6184 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6185 [(set_attr "type" "mve_move")
6186 (set_attr "length""8")])
6187
6188;;
6189;; [vmaxq_m_s, vmaxq_m_u])
6190;;
6191(define_insn "mve_vmaxq_m_<supf><mode>"
6192 [
6193 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6194 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6195 (match_operand:MVE_2 2 "s_register_operand" "w")
6196 (match_operand:MVE_2 3 "s_register_operand" "w")
6197 (match_operand:HI 4 "vpr_register_operand" "Up")]
6198 VMAXQ_M))
6199 ]
6200 "TARGET_HAVE_MVE"
6201 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6202 [(set_attr "type" "mve_move")
6203 (set_attr "length""8")])
6204
6205;;
6206;; [vminq_m_s, vminq_m_u])
6207;;
6208(define_insn "mve_vminq_m_<supf><mode>"
6209 [
6210 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6211 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6212 (match_operand:MVE_2 2 "s_register_operand" "w")
6213 (match_operand:MVE_2 3 "s_register_operand" "w")
6214 (match_operand:HI 4 "vpr_register_operand" "Up")]
6215 VMINQ_M))
6216 ]
6217 "TARGET_HAVE_MVE"
6218 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6219 [(set_attr "type" "mve_move")
6220 (set_attr "length""8")])
6221
6222;;
6223;; [vmladavaq_p_u, vmladavaq_p_s])
6224;;
6225(define_insn "mve_vmladavaq_p_<supf><mode>"
6226 [
6227 (set (match_operand:SI 0 "s_register_operand" "=e")
6228 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6229 (match_operand:MVE_2 2 "s_register_operand" "w")
6230 (match_operand:MVE_2 3 "s_register_operand" "w")
6231 (match_operand:HI 4 "vpr_register_operand" "Up")]
6232 VMLADAVAQ_P))
6233 ]
6234 "TARGET_HAVE_MVE"
6235 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
6236 [(set_attr "type" "mve_move")
6237 (set_attr "length""8")])
6238
6239;;
6240;; [vmlaq_m_n_s, vmlaq_m_n_u])
6241;;
6242(define_insn "mve_vmlaq_m_n_<supf><mode>"
6243 [
6244 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6245 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6246 (match_operand:MVE_2 2 "s_register_operand" "w")
6247 (match_operand:<V_elem> 3 "s_register_operand" "r")
6248 (match_operand:HI 4 "vpr_register_operand" "Up")]
6249 VMLAQ_M_N))
6250 ]
6251 "TARGET_HAVE_MVE"
6252 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
6253 [(set_attr "type" "mve_move")
6254 (set_attr "length""8")])
6255
6256;;
6257;; [vmlasq_m_n_u, vmlasq_m_n_s])
6258;;
6259(define_insn "mve_vmlasq_m_n_<supf><mode>"
6260 [
6261 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6263 (match_operand:MVE_2 2 "s_register_operand" "w")
6264 (match_operand:<V_elem> 3 "s_register_operand" "r")
6265 (match_operand:HI 4 "vpr_register_operand" "Up")]
6266 VMLASQ_M_N))
6267 ]
6268 "TARGET_HAVE_MVE"
6269 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
6270 [(set_attr "type" "mve_move")
6271 (set_attr "length""8")])
6272
6273;;
6274;; [vmulhq_m_s, vmulhq_m_u])
6275;;
6276(define_insn "mve_vmulhq_m_<supf><mode>"
6277 [
6278 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6279 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6280 (match_operand:MVE_2 2 "s_register_operand" "w")
6281 (match_operand:MVE_2 3 "s_register_operand" "w")
6282 (match_operand:HI 4 "vpr_register_operand" "Up")]
6283 VMULHQ_M))
6284 ]
6285 "TARGET_HAVE_MVE"
6286 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6287 [(set_attr "type" "mve_move")
6288 (set_attr "length""8")])
6289
6290;;
6291;; [vmullbq_int_m_u, vmullbq_int_m_s])
6292;;
6293(define_insn "mve_vmullbq_int_m_<supf><mode>"
6294 [
6295 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6296 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6297 (match_operand:MVE_2 2 "s_register_operand" "w")
6298 (match_operand:MVE_2 3 "s_register_operand" "w")
6299 (match_operand:HI 4 "vpr_register_operand" "Up")]
6300 VMULLBQ_INT_M))
6301 ]
6302 "TARGET_HAVE_MVE"
6303 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6304 [(set_attr "type" "mve_move")
6305 (set_attr "length""8")])
6306
6307;;
6308;; [vmulltq_int_m_s, vmulltq_int_m_u])
6309;;
6310(define_insn "mve_vmulltq_int_m_<supf><mode>"
6311 [
6312 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
6313 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
6314 (match_operand:MVE_2 2 "s_register_operand" "w")
6315 (match_operand:MVE_2 3 "s_register_operand" "w")
6316 (match_operand:HI 4 "vpr_register_operand" "Up")]
6317 VMULLTQ_INT_M))
6318 ]
6319 "TARGET_HAVE_MVE"
6320 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
6321 [(set_attr "type" "mve_move")
6322 (set_attr "length""8")])
6323
6324;;
6325;; [vmulq_m_n_u, vmulq_m_n_s])
6326;;
6327(define_insn "mve_vmulq_m_n_<supf><mode>"
6328 [
6329 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6330 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6331 (match_operand:MVE_2 2 "s_register_operand" "w")
6332 (match_operand:<V_elem> 3 "s_register_operand" "r")
6333 (match_operand:HI 4 "vpr_register_operand" "Up")]
6334 VMULQ_M_N))
6335 ]
6336 "TARGET_HAVE_MVE"
6337 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
6338 [(set_attr "type" "mve_move")
6339 (set_attr "length""8")])
6340
6341;;
6342;; [vmulq_m_s, vmulq_m_u])
6343;;
6344(define_insn "mve_vmulq_m_<supf><mode>"
6345 [
6346 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6347 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6348 (match_operand:MVE_2 2 "s_register_operand" "w")
6349 (match_operand:MVE_2 3 "s_register_operand" "w")
6350 (match_operand:HI 4 "vpr_register_operand" "Up")]
6351 VMULQ_M))
6352 ]
6353 "TARGET_HAVE_MVE"
6354 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
6355 [(set_attr "type" "mve_move")
6356 (set_attr "length""8")])
6357
6358;;
6359;; [vornq_m_u, vornq_m_s])
6360;;
6361(define_insn "mve_vornq_m_<supf><mode>"
6362 [
6363 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6364 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6365 (match_operand:MVE_2 2 "s_register_operand" "w")
6366 (match_operand:MVE_2 3 "s_register_operand" "w")
6367 (match_operand:HI 4 "vpr_register_operand" "Up")]
6368 VORNQ_M))
6369 ]
6370 "TARGET_HAVE_MVE"
6371 "vpst\;vornt %q0, %q2, %q3"
6372 [(set_attr "type" "mve_move")
6373 (set_attr "length""8")])
6374
6375;;
6376;; [vorrq_m_s, vorrq_m_u])
6377;;
6378(define_insn "mve_vorrq_m_<supf><mode>"
6379 [
6380 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6381 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6382 (match_operand:MVE_2 2 "s_register_operand" "w")
6383 (match_operand:MVE_2 3 "s_register_operand" "w")
6384 (match_operand:HI 4 "vpr_register_operand" "Up")]
6385 VORRQ_M))
6386 ]
6387 "TARGET_HAVE_MVE"
6388 "vpst\;vorrt %q0, %q2, %q3"
6389 [(set_attr "type" "mve_move")
6390 (set_attr "length""8")])
6391
6392;;
6393;; [vqaddq_m_n_u, vqaddq_m_n_s])
6394;;
6395(define_insn "mve_vqaddq_m_n_<supf><mode>"
6396 [
6397 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6398 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6399 (match_operand:MVE_2 2 "s_register_operand" "w")
6400 (match_operand:<V_elem> 3 "s_register_operand" "r")
6401 (match_operand:HI 4 "vpr_register_operand" "Up")]
6402 VQADDQ_M_N))
6403 ]
6404 "TARGET_HAVE_MVE"
6405 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6406 [(set_attr "type" "mve_move")
6407 (set_attr "length""8")])
6408
6409;;
6410;; [vqaddq_m_u, vqaddq_m_s])
6411;;
6412(define_insn "mve_vqaddq_m_<supf><mode>"
6413 [
6414 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6415 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6416 (match_operand:MVE_2 2 "s_register_operand" "w")
6417 (match_operand:MVE_2 3 "s_register_operand" "w")
6418 (match_operand:HI 4 "vpr_register_operand" "Up")]
6419 VQADDQ_M))
6420 ]
6421 "TARGET_HAVE_MVE"
6422 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6423 [(set_attr "type" "mve_move")
6424 (set_attr "length""8")])
6425
6426;;
6427;; [vqdmlahq_m_n_s])
6428;;
6429(define_insn "mve_vqdmlahq_m_n_s<mode>"
6430 [
6431 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6432 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6433 (match_operand:MVE_2 2 "s_register_operand" "w")
6434 (match_operand:<V_elem> 3 "s_register_operand" "r")
6435 (match_operand:HI 4 "vpr_register_operand" "Up")]
6436 VQDMLAHQ_M_N_S))
6437 ]
6438 "TARGET_HAVE_MVE"
6439 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6440 [(set_attr "type" "mve_move")
6441 (set_attr "length""8")])
6442
6443;;
6444;; [vqrdmlahq_m_n_s])
6445;;
6446(define_insn "mve_vqrdmlahq_m_n_s<mode>"
6447 [
6448 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6449 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6450 (match_operand:MVE_2 2 "s_register_operand" "w")
6451 (match_operand:<V_elem> 3 "s_register_operand" "r")
6452 (match_operand:HI 4 "vpr_register_operand" "Up")]
6453 VQRDMLAHQ_M_N_S))
6454 ]
6455 "TARGET_HAVE_MVE"
6456 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
6457 [(set_attr "type" "mve_move")
6458 (set_attr "length""8")])
6459
6460;;
6461;; [vqrdmlashq_m_n_s])
6462;;
6463(define_insn "mve_vqrdmlashq_m_n_s<mode>"
6464 [
6465 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6466 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6467 (match_operand:MVE_2 2 "s_register_operand" "w")
6468 (match_operand:<V_elem> 3 "s_register_operand" "r")
6469 (match_operand:HI 4 "vpr_register_operand" "Up")]
6470 VQRDMLASHQ_M_N_S))
6471 ]
6472 "TARGET_HAVE_MVE"
6473 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
6474 [(set_attr "type" "mve_move")
6475 (set_attr "length""8")])
6476
6477;;
6478;; [vqrshlq_m_u, vqrshlq_m_s])
6479;;
6480(define_insn "mve_vqrshlq_m_<supf><mode>"
6481 [
6482 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6483 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6484 (match_operand:MVE_2 2 "s_register_operand" "w")
6485 (match_operand:MVE_2 3 "s_register_operand" "w")
6486 (match_operand:HI 4 "vpr_register_operand" "Up")]
6487 VQRSHLQ_M))
6488 ]
6489 "TARGET_HAVE_MVE"
6490 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6491 [(set_attr "type" "mve_move")
6492 (set_attr "length""8")])
6493
6494;;
6495;; [vqshlq_m_n_s, vqshlq_m_n_u])
6496;;
6497(define_insn "mve_vqshlq_m_n_<supf><mode>"
6498 [
6499 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6500 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6501 (match_operand:MVE_2 2 "s_register_operand" "w")
6502 (match_operand:SI 3 "immediate_operand" "i")
6503 (match_operand:HI 4 "vpr_register_operand" "Up")]
6504 VQSHLQ_M_N))
6505 ]
6506 "TARGET_HAVE_MVE"
6507 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6508 [(set_attr "type" "mve_move")
6509 (set_attr "length""8")])
6510
6511;;
6512;; [vqshlq_m_u, vqshlq_m_s])
6513;;
6514(define_insn "mve_vqshlq_m_<supf><mode>"
6515 [
6516 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6517 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6518 (match_operand:MVE_2 2 "s_register_operand" "w")
6519 (match_operand:MVE_2 3 "s_register_operand" "w")
6520 (match_operand:HI 4 "vpr_register_operand" "Up")]
6521 VQSHLQ_M))
6522 ]
6523 "TARGET_HAVE_MVE"
6524 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6525 [(set_attr "type" "mve_move")
6526 (set_attr "length""8")])
6527
6528;;
6529;; [vqsubq_m_n_u, vqsubq_m_n_s])
6530;;
6531(define_insn "mve_vqsubq_m_n_<supf><mode>"
6532 [
6533 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6534 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6535 (match_operand:MVE_2 2 "s_register_operand" "w")
6536 (match_operand:<V_elem> 3 "s_register_operand" "r")
6537 (match_operand:HI 4 "vpr_register_operand" "Up")]
6538 VQSUBQ_M_N))
6539 ]
6540 "TARGET_HAVE_MVE"
6541 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6542 [(set_attr "type" "mve_move")
6543 (set_attr "length""8")])
6544
6545;;
6546;; [vqsubq_m_u, vqsubq_m_s])
6547;;
6548(define_insn "mve_vqsubq_m_<supf><mode>"
6549 [
6550 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6551 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6552 (match_operand:MVE_2 2 "s_register_operand" "w")
6553 (match_operand:MVE_2 3 "s_register_operand" "w")
6554 (match_operand:HI 4 "vpr_register_operand" "Up")]
6555 VQSUBQ_M))
6556 ]
6557 "TARGET_HAVE_MVE"
6558 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6559 [(set_attr "type" "mve_move")
6560 (set_attr "length""8")])
6561
6562;;
6563;; [vrhaddq_m_u, vrhaddq_m_s])
6564;;
6565(define_insn "mve_vrhaddq_m_<supf><mode>"
6566 [
6567 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6568 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6569 (match_operand:MVE_2 2 "s_register_operand" "w")
6570 (match_operand:MVE_2 3 "s_register_operand" "w")
6571 (match_operand:HI 4 "vpr_register_operand" "Up")]
6572 VRHADDQ_M))
6573 ]
6574 "TARGET_HAVE_MVE"
6575 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6576 [(set_attr "type" "mve_move")
6577 (set_attr "length""8")])
6578
6579;;
6580;; [vrmulhq_m_u, vrmulhq_m_s])
6581;;
6582(define_insn "mve_vrmulhq_m_<supf><mode>"
6583 [
6584 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6585 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6586 (match_operand:MVE_2 2 "s_register_operand" "w")
6587 (match_operand:MVE_2 3 "s_register_operand" "w")
6588 (match_operand:HI 4 "vpr_register_operand" "Up")]
6589 VRMULHQ_M))
6590 ]
6591 "TARGET_HAVE_MVE"
6592 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6593 [(set_attr "type" "mve_move")
6594 (set_attr "length""8")])
6595
6596;;
6597;; [vrshlq_m_s, vrshlq_m_u])
6598;;
6599(define_insn "mve_vrshlq_m_<supf><mode>"
6600 [
6601 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6602 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6603 (match_operand:MVE_2 2 "s_register_operand" "w")
6604 (match_operand:MVE_2 3 "s_register_operand" "w")
6605 (match_operand:HI 4 "vpr_register_operand" "Up")]
6606 VRSHLQ_M))
6607 ]
6608 "TARGET_HAVE_MVE"
6609 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
6610 [(set_attr "type" "mve_move")
6611 (set_attr "length""8")])
6612
6613;;
6614;; [vrshrq_m_n_s, vrshrq_m_n_u])
6615;;
6616(define_insn "mve_vrshrq_m_n_<supf><mode>"
6617 [
6618 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6619 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6620 (match_operand:MVE_2 2 "s_register_operand" "w")
6621 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6622 (match_operand:HI 4 "vpr_register_operand" "Up")]
6623 VRSHRQ_M_N))
6624 ]
6625 "TARGET_HAVE_MVE"
6626 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6627 [(set_attr "type" "mve_move")
6628 (set_attr "length""8")])
6629
6630;;
6631;; [vshlq_m_n_s, vshlq_m_n_u])
6632;;
6633(define_insn "mve_vshlq_m_n_<supf><mode>"
6634 [
6635 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6636 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6637 (match_operand:MVE_2 2 "s_register_operand" "w")
6638 (match_operand:SI 3 "immediate_operand" "i")
6639 (match_operand:HI 4 "vpr_register_operand" "Up")]
6640 VSHLQ_M_N))
6641 ]
6642 "TARGET_HAVE_MVE"
6643 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6644 [(set_attr "type" "mve_move")
6645 (set_attr "length""8")])
6646
6647;;
6648;; [vshrq_m_n_s, vshrq_m_n_u])
6649;;
6650(define_insn "mve_vshrq_m_n_<supf><mode>"
6651 [
6652 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6653 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6654 (match_operand:MVE_2 2 "s_register_operand" "w")
6655 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
6656 (match_operand:HI 4 "vpr_register_operand" "Up")]
6657 VSHRQ_M_N))
6658 ]
6659 "TARGET_HAVE_MVE"
6660 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
6661 [(set_attr "type" "mve_move")
6662 (set_attr "length""8")])
6663
6664;;
6665;; [vsliq_m_n_u, vsliq_m_n_s])
6666;;
6667(define_insn "mve_vsliq_m_n_<supf><mode>"
6668 [
6669 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6670 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6671 (match_operand:MVE_2 2 "s_register_operand" "w")
6672 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
6673 (match_operand:HI 4 "vpr_register_operand" "Up")]
6674 VSLIQ_M_N))
6675 ]
6676 "TARGET_HAVE_MVE"
6677 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
6678 [(set_attr "type" "mve_move")
6679 (set_attr "length""8")])
6680
6681;;
6682;; [vsubq_m_n_s, vsubq_m_n_u])
6683;;
6684(define_insn "mve_vsubq_m_n_<supf><mode>"
6685 [
6686 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6687 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6688 (match_operand:MVE_2 2 "s_register_operand" "w")
6689 (match_operand:<V_elem> 3 "s_register_operand" "r")
6690 (match_operand:HI 4 "vpr_register_operand" "Up")]
6691 VSUBQ_M_N))
6692 ]
6693 "TARGET_HAVE_MVE"
6694 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
6695 [(set_attr "type" "mve_move")
6696 (set_attr "length""8")])
6697
6698;;
6699;; [vhcaddq_rot270_m_s])
6700;;
6701(define_insn "mve_vhcaddq_rot270_m_s<mode>"
6702 [
6703 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6704 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6705 (match_operand:MVE_2 2 "s_register_operand" "w")
6706 (match_operand:MVE_2 3 "s_register_operand" "w")
6707 (match_operand:HI 4 "vpr_register_operand" "Up")]
6708 VHCADDQ_ROT270_M_S))
6709 ]
6710 "TARGET_HAVE_MVE"
6711 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
6712 [(set_attr "type" "mve_move")
6713 (set_attr "length""8")])
6714
6715;;
6716;; [vhcaddq_rot90_m_s])
6717;;
6718(define_insn "mve_vhcaddq_rot90_m_s<mode>"
6719 [
6720 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6721 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6722 (match_operand:MVE_2 2 "s_register_operand" "w")
6723 (match_operand:MVE_2 3 "s_register_operand" "w")
6724 (match_operand:HI 4 "vpr_register_operand" "Up")]
6725 VHCADDQ_ROT90_M_S))
6726 ]
6727 "TARGET_HAVE_MVE"
6728 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
6729 [(set_attr "type" "mve_move")
6730 (set_attr "length""8")])
6731
6732;;
6733;; [vmladavaxq_p_s])
6734;;
6735(define_insn "mve_vmladavaxq_p_s<mode>"
6736 [
6737 (set (match_operand:SI 0 "s_register_operand" "=e")
6738 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6739 (match_operand:MVE_2 2 "s_register_operand" "w")
6740 (match_operand:MVE_2 3 "s_register_operand" "w")
6741 (match_operand:HI 4 "vpr_register_operand" "Up")]
6742 VMLADAVAXQ_P_S))
6743 ]
6744 "TARGET_HAVE_MVE"
6745 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6746 [(set_attr "type" "mve_move")
6747 (set_attr "length""8")])
6748
6749;;
6750;; [vmlsdavaq_p_s])
6751;;
6752(define_insn "mve_vmlsdavaq_p_s<mode>"
6753 [
6754 (set (match_operand:SI 0 "s_register_operand" "=e")
6755 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6756 (match_operand:MVE_2 2 "s_register_operand" "w")
6757 (match_operand:MVE_2 3 "s_register_operand" "w")
6758 (match_operand:HI 4 "vpr_register_operand" "Up")]
6759 VMLSDAVAQ_P_S))
6760 ]
6761 "TARGET_HAVE_MVE"
6762 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
6763 [(set_attr "type" "mve_move")
6764 (set_attr "length""8")])
6765
6766;;
6767;; [vmlsdavaxq_p_s])
6768;;
6769(define_insn "mve_vmlsdavaxq_p_s<mode>"
6770 [
6771 (set (match_operand:SI 0 "s_register_operand" "=e")
6772 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
6773 (match_operand:MVE_2 2 "s_register_operand" "w")
6774 (match_operand:MVE_2 3 "s_register_operand" "w")
6775 (match_operand:HI 4 "vpr_register_operand" "Up")]
6776 VMLSDAVAXQ_P_S))
6777 ]
6778 "TARGET_HAVE_MVE"
6779 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
6780 [(set_attr "type" "mve_move")
6781 (set_attr "length""8")])
6782
6783;;
6784;; [vqdmladhq_m_s])
6785;;
6786(define_insn "mve_vqdmladhq_m_s<mode>"
6787 [
6788 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6789 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6790 (match_operand:MVE_2 2 "s_register_operand" "w")
6791 (match_operand:MVE_2 3 "s_register_operand" "w")
6792 (match_operand:HI 4 "vpr_register_operand" "Up")]
6793 VQDMLADHQ_M_S))
6794 ]
6795 "TARGET_HAVE_MVE"
6796 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6797 [(set_attr "type" "mve_move")
6798 (set_attr "length""8")])
6799
6800;;
6801;; [vqdmladhxq_m_s])
6802;;
6803(define_insn "mve_vqdmladhxq_m_s<mode>"
6804 [
6805 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6806 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6807 (match_operand:MVE_2 2 "s_register_operand" "w")
6808 (match_operand:MVE_2 3 "s_register_operand" "w")
6809 (match_operand:HI 4 "vpr_register_operand" "Up")]
6810 VQDMLADHXQ_M_S))
6811 ]
6812 "TARGET_HAVE_MVE"
6813 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6814 [(set_attr "type" "mve_move")
6815 (set_attr "length""8")])
6816
6817;;
6818;; [vqdmlsdhq_m_s])
6819;;
6820(define_insn "mve_vqdmlsdhq_m_s<mode>"
6821 [
6822 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6823 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6824 (match_operand:MVE_2 2 "s_register_operand" "w")
6825 (match_operand:MVE_2 3 "s_register_operand" "w")
6826 (match_operand:HI 4 "vpr_register_operand" "Up")]
6827 VQDMLSDHQ_M_S))
6828 ]
6829 "TARGET_HAVE_MVE"
6830 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6831 [(set_attr "type" "mve_move")
6832 (set_attr "length""8")])
6833
6834;;
6835;; [vqdmlsdhxq_m_s])
6836;;
6837(define_insn "mve_vqdmlsdhxq_m_s<mode>"
6838 [
6839 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6840 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6841 (match_operand:MVE_2 2 "s_register_operand" "w")
6842 (match_operand:MVE_2 3 "s_register_operand" "w")
6843 (match_operand:HI 4 "vpr_register_operand" "Up")]
6844 VQDMLSDHXQ_M_S))
6845 ]
6846 "TARGET_HAVE_MVE"
6847 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6848 [(set_attr "type" "mve_move")
6849 (set_attr "length""8")])
6850
6851;;
6852;; [vqdmulhq_m_n_s])
6853;;
6854(define_insn "mve_vqdmulhq_m_n_s<mode>"
6855 [
6856 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6857 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6858 (match_operand:MVE_2 2 "s_register_operand" "w")
6859 (match_operand:<V_elem> 3 "s_register_operand" "r")
6860 (match_operand:HI 4 "vpr_register_operand" "Up")]
6861 VQDMULHQ_M_N_S))
6862 ]
6863 "TARGET_HAVE_MVE"
6864 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6865 [(set_attr "type" "mve_move")
6866 (set_attr "length""8")])
6867
6868;;
6869;; [vqdmulhq_m_s])
6870;;
6871(define_insn "mve_vqdmulhq_m_s<mode>"
6872 [
6873 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6874 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6875 (match_operand:MVE_2 2 "s_register_operand" "w")
6876 (match_operand:MVE_2 3 "s_register_operand" "w")
6877 (match_operand:HI 4 "vpr_register_operand" "Up")]
6878 VQDMULHQ_M_S))
6879 ]
6880 "TARGET_HAVE_MVE"
6881 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6882 [(set_attr "type" "mve_move")
6883 (set_attr "length""8")])
6884
6885;;
6886;; [vqrdmladhq_m_s])
6887;;
6888(define_insn "mve_vqrdmladhq_m_s<mode>"
6889 [
6890 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6891 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6892 (match_operand:MVE_2 2 "s_register_operand" "w")
6893 (match_operand:MVE_2 3 "s_register_operand" "w")
6894 (match_operand:HI 4 "vpr_register_operand" "Up")]
6895 VQRDMLADHQ_M_S))
6896 ]
6897 "TARGET_HAVE_MVE"
6898 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6899 [(set_attr "type" "mve_move")
6900 (set_attr "length""8")])
6901
6902;;
6903;; [vqrdmladhxq_m_s])
6904;;
6905(define_insn "mve_vqrdmladhxq_m_s<mode>"
6906 [
6907 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6908 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6909 (match_operand:MVE_2 2 "s_register_operand" "w")
6910 (match_operand:MVE_2 3 "s_register_operand" "w")
6911 (match_operand:HI 4 "vpr_register_operand" "Up")]
6912 VQRDMLADHXQ_M_S))
6913 ]
6914 "TARGET_HAVE_MVE"
6915 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6916 [(set_attr "type" "mve_move")
6917 (set_attr "length""8")])
6918
6919;;
6920;; [vqrdmlsdhq_m_s])
6921;;
6922(define_insn "mve_vqrdmlsdhq_m_s<mode>"
6923 [
6924 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6925 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6926 (match_operand:MVE_2 2 "s_register_operand" "w")
6927 (match_operand:MVE_2 3 "s_register_operand" "w")
6928 (match_operand:HI 4 "vpr_register_operand" "Up")]
6929 VQRDMLSDHQ_M_S))
6930 ]
6931 "TARGET_HAVE_MVE"
6932 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6933 [(set_attr "type" "mve_move")
6934 (set_attr "length""8")])
6935
6936;;
6937;; [vqrdmlsdhxq_m_s])
6938;;
6939(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
6940 [
6941 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6942 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6943 (match_operand:MVE_2 2 "s_register_operand" "w")
6944 (match_operand:MVE_2 3 "s_register_operand" "w")
6945 (match_operand:HI 4 "vpr_register_operand" "Up")]
6946 VQRDMLSDHXQ_M_S))
6947 ]
6948 "TARGET_HAVE_MVE"
6949 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
6950 [(set_attr "type" "mve_move")
6951 (set_attr "length""8")])
6952
6953;;
6954;; [vqrdmulhq_m_n_s])
6955;;
6956(define_insn "mve_vqrdmulhq_m_n_s<mode>"
6957 [
6958 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6959 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6960 (match_operand:MVE_2 2 "s_register_operand" "w")
6961 (match_operand:<V_elem> 3 "s_register_operand" "r")
6962 (match_operand:HI 4 "vpr_register_operand" "Up")]
6963 VQRDMULHQ_M_N_S))
6964 ]
6965 "TARGET_HAVE_MVE"
6966 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
6967 [(set_attr "type" "mve_move")
6968 (set_attr "length""8")])
6969
6970;;
6971;; [vqrdmulhq_m_s])
6972;;
6973(define_insn "mve_vqrdmulhq_m_s<mode>"
6974 [
6975 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
6976 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
6977 (match_operand:MVE_2 2 "s_register_operand" "w")
6978 (match_operand:MVE_2 3 "s_register_operand" "w")
6979 (match_operand:HI 4 "vpr_register_operand" "Up")]
6980 VQRDMULHQ_M_S))
6981 ]
6982 "TARGET_HAVE_MVE"
6983 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
6984 [(set_attr "type" "mve_move")
6985 (set_attr "length""8")])
6986
f2170a37
SP		 6987;;
6988;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
6989;;
6990(define_insn "mve_vmlaldavaq_p_<supf><mode>"
6991 [
6992 (set (match_operand:DI 0 "s_register_operand" "=r")
6993 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
6994 (match_operand:MVE_5 2 "s_register_operand" "w")
6995 (match_operand:MVE_5 3 "s_register_operand" "w")
6996 (match_operand:HI 4 "vpr_register_operand" "Up")]
6997 VMLALDAVAQ_P))
6998 ]
6999 "TARGET_HAVE_MVE"
7000 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7001 [(set_attr "type" "mve_move")
7002 (set_attr "length""8")])
7003
7004;;
7005;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s])
7006;;
7007(define_insn "mve_vmlaldavaxq_p_<supf><mode>"
7008 [
7009 (set (match_operand:DI 0 "s_register_operand" "=r")
7010 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7011 (match_operand:MVE_5 2 "s_register_operand" "w")
7012 (match_operand:MVE_5 3 "s_register_operand" "w")
7013 (match_operand:HI 4 "vpr_register_operand" "Up")]
7014 VMLALDAVAXQ_P))
7015 ]
7016 "TARGET_HAVE_MVE"
7017 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
7018 [(set_attr "type" "mve_move")
7019 (set_attr "length""8")])
7020
7021;;
7022;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s])
7023;;
7024(define_insn "mve_vqrshrnbq_m_n_<supf><mode>"
7025 [
7026 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7027 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7028 (match_operand:MVE_5 2 "s_register_operand" "w")
7029 (match_operand:SI 3 "mve_imm_8" "Rb")
7030 (match_operand:HI 4 "vpr_register_operand" "Up")]
7031 VQRSHRNBQ_M_N))
7032 ]
7033 "TARGET_HAVE_MVE"
7034 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7035 [(set_attr "type" "mve_move")
7036 (set_attr "length""8")])
7037
7038;;
7039;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u])
7040;;
7041(define_insn "mve_vqrshrntq_m_n_<supf><mode>"
7042 [
7043 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7044 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7045 (match_operand:MVE_5 2 "s_register_operand" "w")
7046 (match_operand:SI 3 "mve_imm_8" "Rb")
7047 (match_operand:HI 4 "vpr_register_operand" "Up")]
7048 VQRSHRNTQ_M_N))
7049 ]
7050 "TARGET_HAVE_MVE"
7051 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3"
7052 [(set_attr "type" "mve_move")
7053 (set_attr "length""8")])
7054
7055;;
7056;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s])
7057;;
7058(define_insn "mve_vqshrnbq_m_n_<supf><mode>"
7059 [
7060 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7061 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7062 (match_operand:MVE_5 2 "s_register_operand" "w")
7063 (match_operand:SI 3 "<MVE_pred1>" "<MVE_constraint1>")
7064 (match_operand:HI 4 "vpr_register_operand" "Up")]
7065 VQSHRNBQ_M_N))
7066 ]
7067 "TARGET_HAVE_MVE && arm_mve_immediate_check (operands[3], <MODE>mode, 0)"
7068 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7069 [(set_attr "type" "mve_move")
7070 (set_attr "length""8")])
7071
7072;;
7073;; [vqshrntq_m_n_s, vqshrntq_m_n_u])
7074;;
7075(define_insn "mve_vqshrntq_m_n_<supf><mode>"
7076 [
7077 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7078 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7079 (match_operand:MVE_5 2 "s_register_operand" "w")
7080 (match_operand:SI 3 "mve_imm_8" "Rb")
7081 (match_operand:HI 4 "vpr_register_operand" "Up")]
7082 VQSHRNTQ_M_N))
7083 ]
7084 "TARGET_HAVE_MVE"
7085 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7086 [(set_attr "type" "mve_move")
7087 (set_attr "length""8")])
7088
7089;;
7090;; [vrmlaldavhaq_p_s])
7091;;
7092(define_insn "mve_vrmlaldavhaq_p_sv4si"
7093 [
7094 (set (match_operand:DI 0 "s_register_operand" "=r")
7095 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7096 (match_operand:V4SI 2 "s_register_operand" "w")
7097 (match_operand:V4SI 3 "s_register_operand" "w")
7098 (match_operand:HI 4 "vpr_register_operand" "Up")]
7099 VRMLALDAVHAQ_P_S))
7100 ]
7101 "TARGET_HAVE_MVE"
7102 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
7103 [(set_attr "type" "mve_move")
7104 (set_attr "length""8")])
7105
7106;;
7107;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s])
7108;;
7109(define_insn "mve_vrshrnbq_m_n_<supf><mode>"
7110 [
7111 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7112 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7113 (match_operand:MVE_5 2 "s_register_operand" "w")
7114 (match_operand:SI 3 "mve_imm_8" "Rb")
7115 (match_operand:HI 4 "vpr_register_operand" "Up")]
7116 VRSHRNBQ_M_N))
7117 ]
7118 "TARGET_HAVE_MVE"
7119 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7120 [(set_attr "type" "mve_move")
7121 (set_attr "length""8")])
7122
7123;;
7124;; [vrshrntq_m_n_u, vrshrntq_m_n_s])
7125;;
7126(define_insn "mve_vrshrntq_m_n_<supf><mode>"
7127 [
7128 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7129 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7130 (match_operand:MVE_5 2 "s_register_operand" "w")
7131 (match_operand:SI 3 "mve_imm_8" "Rb")
7132 (match_operand:HI 4 "vpr_register_operand" "Up")]
7133 VRSHRNTQ_M_N))
7134 ]
7135 "TARGET_HAVE_MVE"
7136 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7137 [(set_attr "type" "mve_move")
7138 (set_attr "length""8")])
7139
7140;;
7141;; [vshllbq_m_n_u, vshllbq_m_n_s])
7142;;
7143(define_insn "mve_vshllbq_m_n_<supf><mode>"
7144 [
7145 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7146 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7147 (match_operand:MVE_3 2 "s_register_operand" "w")
7148 (match_operand:SI 3 "immediate_operand" "i")
7149 (match_operand:HI 4 "vpr_register_operand" "Up")]
7150 VSHLLBQ_M_N))
7151 ]
7152 "TARGET_HAVE_MVE"
7153 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7154 [(set_attr "type" "mve_move")
7155 (set_attr "length""8")])
7156
7157;;
7158;; [vshlltq_m_n_u, vshlltq_m_n_s])
7159;;
7160(define_insn "mve_vshlltq_m_n_<supf><mode>"
7161 [
7162 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7163 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7164 (match_operand:MVE_3 2 "s_register_operand" "w")
7165 (match_operand:SI 3 "immediate_operand" "i")
7166 (match_operand:HI 4 "vpr_register_operand" "Up")]
7167 VSHLLTQ_M_N))
7168 ]
7169 "TARGET_HAVE_MVE"
7170 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
7171 [(set_attr "type" "mve_move")
7172 (set_attr "length""8")])
7173
7174;;
7175;; [vshrnbq_m_n_s, vshrnbq_m_n_u])
7176;;
7177(define_insn "mve_vshrnbq_m_n_<supf><mode>"
7178 [
7179 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7180 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7181 (match_operand:MVE_5 2 "s_register_operand" "w")
7182 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7183 (match_operand:HI 4 "vpr_register_operand" "Up")]
7184 VSHRNBQ_M_N))
7185 ]
7186 "TARGET_HAVE_MVE"
7187 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3"
7188 [(set_attr "type" "mve_move")
7189 (set_attr "length""8")])
7190
7191;;
7192;; [vshrntq_m_n_s, vshrntq_m_n_u])
7193;;
7194(define_insn "mve_vshrntq_m_n_<supf><mode>"
7195 [
7196 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7197 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7198 (match_operand:MVE_5 2 "s_register_operand" "w")
7199 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
7200 (match_operand:HI 4 "vpr_register_operand" "Up")]
7201 VSHRNTQ_M_N))
7202 ]
7203 "TARGET_HAVE_MVE"
7204 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3"
7205 [(set_attr "type" "mve_move")
7206 (set_attr "length""8")])
7207
7208;;
7209;; [vmlsldavaq_p_s])
7210;;
7211(define_insn "mve_vmlsldavaq_p_s<mode>"
7212 [
7213 (set (match_operand:DI 0 "s_register_operand" "=r")
7214 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7215 (match_operand:MVE_5 2 "s_register_operand" "w")
7216 (match_operand:MVE_5 3 "s_register_operand" "w")
7217 (match_operand:HI 4 "vpr_register_operand" "Up")]
7218 VMLSLDAVAQ_P_S))
7219 ]
7220 "TARGET_HAVE_MVE"
7221 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7222 [(set_attr "type" "mve_move")
7223 (set_attr "length""8")])
7224
7225;;
7226;; [vmlsldavaxq_p_s])
7227;;
7228(define_insn "mve_vmlsldavaxq_p_s<mode>"
7229 [
7230 (set (match_operand:DI 0 "s_register_operand" "=r")
7231 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7232 (match_operand:MVE_5 2 "s_register_operand" "w")
7233 (match_operand:MVE_5 3 "s_register_operand" "w")
7234 (match_operand:HI 4 "vpr_register_operand" "Up")]
7235 VMLSLDAVAXQ_P_S))
7236 ]
7237 "TARGET_HAVE_MVE"
7238 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
7239 [(set_attr "type" "mve_move")
7240 (set_attr "length""8")])
7241
7242;;
7243;; [vmullbq_poly_m_p])
7244;;
7245(define_insn "mve_vmullbq_poly_m_p<mode>"
7246 [
7247 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7248 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7249 (match_operand:MVE_3 2 "s_register_operand" "w")
7250 (match_operand:MVE_3 3 "s_register_operand" "w")
7251 (match_operand:HI 4 "vpr_register_operand" "Up")]
7252 VMULLBQ_POLY_M_P))
7253 ]
7254 "TARGET_HAVE_MVE"
7255 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7256 [(set_attr "type" "mve_move")
7257 (set_attr "length""8")])
7258
7259;;
7260;; [vmulltq_poly_m_p])
7261;;
7262(define_insn "mve_vmulltq_poly_m_p<mode>"
7263 [
7264 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7265 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7266 (match_operand:MVE_3 2 "s_register_operand" "w")
7267 (match_operand:MVE_3 3 "s_register_operand" "w")
7268 (match_operand:HI 4 "vpr_register_operand" "Up")]
7269 VMULLTQ_POLY_M_P))
7270 ]
7271 "TARGET_HAVE_MVE"
7272 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3"
7273 [(set_attr "type" "mve_move")
7274 (set_attr "length""8")])
7275
7276;;
7277;; [vqdmullbq_m_n_s])
7278;;
7279(define_insn "mve_vqdmullbq_m_n_s<mode>"
7280 [
7281 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7282 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7283 (match_operand:MVE_5 2 "s_register_operand" "w")
7284 (match_operand:<V_elem> 3 "s_register_operand" "r")
7285 (match_operand:HI 4 "vpr_register_operand" "Up")]
7286 VQDMULLBQ_M_N_S))
7287 ]
7288 "TARGET_HAVE_MVE"
7289 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7290 [(set_attr "type" "mve_move")
7291 (set_attr "length""8")])
7292
7293;;
7294;; [vqdmullbq_m_s])
7295;;
7296(define_insn "mve_vqdmullbq_m_s<mode>"
7297 [
7298 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7299 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7300 (match_operand:MVE_5 2 "s_register_operand" "w")
7301 (match_operand:MVE_5 3 "s_register_operand" "w")
7302 (match_operand:HI 4 "vpr_register_operand" "Up")]
7303 VQDMULLBQ_M_S))
7304 ]
7305 "TARGET_HAVE_MVE"
7306 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7307 [(set_attr "type" "mve_move")
7308 (set_attr "length""8")])
7309
7310;;
7311;; [vqdmulltq_m_n_s])
7312;;
7313(define_insn "mve_vqdmulltq_m_n_s<mode>"
7314 [
7315 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7316 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7317 (match_operand:MVE_5 2 "s_register_operand" "w")
7318 (match_operand:<V_elem> 3 "s_register_operand" "r")
7319 (match_operand:HI 4 "vpr_register_operand" "Up")]
7320 VQDMULLTQ_M_N_S))
7321 ]
7322 "TARGET_HAVE_MVE"
7323 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
7324 [(set_attr "type" "mve_move")
7325 (set_attr "length""8")])
7326
7327;;
7328;; [vqdmulltq_m_s])
7329;;
7330(define_insn "mve_vqdmulltq_m_s<mode>"
7331 [
7332 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
7333 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
7334 (match_operand:MVE_5 2 "s_register_operand" "w")
7335 (match_operand:MVE_5 3 "s_register_operand" "w")
7336 (match_operand:HI 4 "vpr_register_operand" "Up")]
7337 VQDMULLTQ_M_S))
7338 ]
7339 "TARGET_HAVE_MVE"
7340 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
7341 [(set_attr "type" "mve_move")
7342 (set_attr "length""8")])
7343
7344;;
7345;; [vqrshrunbq_m_n_s])
7346;;
7347(define_insn "mve_vqrshrunbq_m_n_s<mode>"
7348 [
7349 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7350 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7351 (match_operand:MVE_5 2 "s_register_operand" "w")
7352 (match_operand:SI 3 "mve_imm_8" "Rb")
7353 (match_operand:HI 4 "vpr_register_operand" "Up")]
7354 VQRSHRUNBQ_M_N_S))
7355 ]
7356 "TARGET_HAVE_MVE"
7357 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7358 [(set_attr "type" "mve_move")
7359 (set_attr "length""8")])
7360
7361;;
7362;; [vqrshruntq_m_n_s])
7363;;
7364(define_insn "mve_vqrshruntq_m_n_s<mode>"
7365 [
7366 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7367 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7368 (match_operand:MVE_5 2 "s_register_operand" "w")
7369 (match_operand:SI 3 "mve_imm_8" "Rb")
7370 (match_operand:HI 4 "vpr_register_operand" "Up")]
7371 VQRSHRUNTQ_M_N_S))
7372 ]
7373 "TARGET_HAVE_MVE"
7374 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7375 [(set_attr "type" "mve_move")
7376 (set_attr "length""8")])
7377
7378;;
7379;; [vqshrunbq_m_n_s])
7380;;
7381(define_insn "mve_vqshrunbq_m_n_s<mode>"
7382 [
7383 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7384 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7385 (match_operand:MVE_5 2 "s_register_operand" "w")
7386 (match_operand:SI 3 "mve_imm_8" "Rb")
7387 (match_operand:HI 4 "vpr_register_operand" "Up")]
7388 VQSHRUNBQ_M_N_S))
7389 ]
7390 "TARGET_HAVE_MVE"
7391 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3"
7392 [(set_attr "type" "mve_move")
7393 (set_attr "length""8")])
7394
7395;;
7396;; [vqshruntq_m_n_s])
7397;;
7398(define_insn "mve_vqshruntq_m_n_s<mode>"
7399 [
7400 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
7401 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
7402 (match_operand:MVE_5 2 "s_register_operand" "w")
7403 (match_operand:SI 3 "mve_imm_8" "Rb")
7404 (match_operand:HI 4 "vpr_register_operand" "Up")]
7405 VQSHRUNTQ_M_N_S))
7406 ]
7407 "TARGET_HAVE_MVE"
7408 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3"
7409 [(set_attr "type" "mve_move")
7410 (set_attr "length""8")])
7411
7412;;
7413;; [vrmlaldavhaq_p_u])
7414;;
7415(define_insn "mve_vrmlaldavhaq_p_uv4si"
7416 [
7417 (set (match_operand:DI 0 "s_register_operand" "=r")
7418 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7419 (match_operand:V4SI 2 "s_register_operand" "w")
7420 (match_operand:V4SI 3 "s_register_operand" "w")
7421 (match_operand:HI 4 "vpr_register_operand" "Up")]
7422 VRMLALDAVHAQ_P_U))
7423 ]
7424 "TARGET_HAVE_MVE"
7425 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
7426 [(set_attr "type" "mve_move")
7427 (set_attr "length""8")])
7428
7429;;
7430;; [vrmlaldavhaxq_p_s])
7431;;
7432(define_insn "mve_vrmlaldavhaxq_p_sv4si"
7433 [
7434 (set (match_operand:DI 0 "s_register_operand" "=r")
7435 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7436 (match_operand:V4SI 2 "s_register_operand" "w")
7437 (match_operand:V4SI 3 "s_register_operand" "w")
7438 (match_operand:HI 4 "vpr_register_operand" "Up")]
7439 VRMLALDAVHAXQ_P_S))
7440 ]
7441 "TARGET_HAVE_MVE"
7442 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7443 [(set_attr "type" "mve_move")
7444 (set_attr "length""8")])
7445
7446;;
7447;; [vrmlsldavhaq_p_s])
7448;;
7449(define_insn "mve_vrmlsldavhaq_p_sv4si"
7450 [
7451 (set (match_operand:DI 0 "s_register_operand" "=r")
7452 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7453 (match_operand:V4SI 2 "s_register_operand" "w")
7454 (match_operand:V4SI 3 "s_register_operand" "w")
7455 (match_operand:HI 4 "vpr_register_operand" "Up")]
7456 VRMLSLDAVHAQ_P_S))
7457 ]
7458 "TARGET_HAVE_MVE"
7459 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
7460 [(set_attr "type" "mve_move")
7461 (set_attr "length""8")])
7462
7463;;
7464;; [vrmlsldavhaxq_p_s])
7465;;
7466(define_insn "mve_vrmlsldavhaxq_p_sv4si"
7467 [
7468 (set (match_operand:DI 0 "s_register_operand" "=r")
7469 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
7470 (match_operand:V4SI 2 "s_register_operand" "w")
7471 (match_operand:V4SI 3 "s_register_operand" "w")
7472 (match_operand:HI 4 "vpr_register_operand" "Up")]
7473 VRMLSLDAVHAXQ_P_S))
7474 ]
7475 "TARGET_HAVE_MVE"
7476 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
7477 [(set_attr "type" "mve_move")
7478 (set_attr "length""8")])
532e9e24
SP		 7479;;
7480;; [vabdq_m_f])
7481;;
7482(define_insn "mve_vabdq_m_f<mode>"
7483 [
7484 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7485 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7486 (match_operand:MVE_0 2 "s_register_operand" "w")
7487 (match_operand:MVE_0 3 "s_register_operand" "w")
7488 (match_operand:HI 4 "vpr_register_operand" "Up")]
7489 VABDQ_M_F))
7490 ]
7491 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7492 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3"
7493 [(set_attr "type" "mve_move")
7494 (set_attr "length""8")])
7495
7496;;
7497;; [vaddq_m_f])
7498;;
7499(define_insn "mve_vaddq_m_f<mode>"
7500 [
7501 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7502 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7503 (match_operand:MVE_0 2 "s_register_operand" "w")
7504 (match_operand:MVE_0 3 "s_register_operand" "w")
7505 (match_operand:HI 4 "vpr_register_operand" "Up")]
7506 VADDQ_M_F))
7507 ]
7508 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7509 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3"
7510 [(set_attr "type" "mve_move")
7511 (set_attr "length""8")])
7512
7513;;
7514;; [vaddq_m_n_f])
7515;;
7516(define_insn "mve_vaddq_m_n_f<mode>"
7517 [
7518 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7519 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7520 (match_operand:MVE_0 2 "s_register_operand" "w")
7521 (match_operand:<V_elem> 3 "s_register_operand" "r")
7522 (match_operand:HI 4 "vpr_register_operand" "Up")]
7523 VADDQ_M_N_F))
7524 ]
7525 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7526 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3"
7527 [(set_attr "type" "mve_move")
7528 (set_attr "length""8")])
7529
7530;;
7531;; [vandq_m_f])
7532;;
7533(define_insn "mve_vandq_m_f<mode>"
7534 [
7535 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7536 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7537 (match_operand:MVE_0 2 "s_register_operand" "w")
7538 (match_operand:MVE_0 3 "s_register_operand" "w")
7539 (match_operand:HI 4 "vpr_register_operand" "Up")]
7540 VANDQ_M_F))
7541 ]
7542 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7543 "vpst\;vandt %q0, %q2, %q3"
7544 [(set_attr "type" "mve_move")
7545 (set_attr "length""8")])
7546
7547;;
7548;; [vbicq_m_f])
7549;;
7550(define_insn "mve_vbicq_m_f<mode>"
7551 [
7552 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7553 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7554 (match_operand:MVE_0 2 "s_register_operand" "w")
7555 (match_operand:MVE_0 3 "s_register_operand" "w")
7556 (match_operand:HI 4 "vpr_register_operand" "Up")]
7557 VBICQ_M_F))
7558 ]
7559 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7560 "vpst\;vbict %q0, %q2, %q3"
7561 [(set_attr "type" "mve_move")
7562 (set_attr "length""8")])
7563
7564;;
7565;; [vbrsrq_m_n_f])
7566;;
7567(define_insn "mve_vbrsrq_m_n_f<mode>"
7568 [
7569 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7570 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7571 (match_operand:MVE_0 2 "s_register_operand" "w")
7572 (match_operand:SI 3 "s_register_operand" "r")
7573 (match_operand:HI 4 "vpr_register_operand" "Up")]
7574 VBRSRQ_M_N_F))
7575 ]
7576 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7577 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
7578 [(set_attr "type" "mve_move")
7579 (set_attr "length""8")])
7580
7581;;
7582;; [vcaddq_rot270_m_f])
7583;;
7584(define_insn "mve_vcaddq_rot270_m_f<mode>"
7585 [
7586 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7587 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7588 (match_operand:MVE_0 2 "s_register_operand" "w")
7589 (match_operand:MVE_0 3 "s_register_operand" "w")
7590 (match_operand:HI 4 "vpr_register_operand" "Up")]
7591 VCADDQ_ROT270_M_F))
7592 ]
7593 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7594 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7595 [(set_attr "type" "mve_move")
7596 (set_attr "length""8")])
7597
7598;;
7599;; [vcaddq_rot90_m_f])
7600;;
7601(define_insn "mve_vcaddq_rot90_m_f<mode>"
7602 [
7603 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7604 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7605 (match_operand:MVE_0 2 "s_register_operand" "w")
7606 (match_operand:MVE_0 3 "s_register_operand" "w")
7607 (match_operand:HI 4 "vpr_register_operand" "Up")]
7608 VCADDQ_ROT90_M_F))
7609 ]
7610 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7611 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7612 [(set_attr "type" "mve_move")
7613 (set_attr "length""8")])
7614
7615;;
7616;; [vcmlaq_m_f])
7617;;
7618(define_insn "mve_vcmlaq_m_f<mode>"
7619 [
7620 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7621 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7622 (match_operand:MVE_0 2 "s_register_operand" "w")
7623 (match_operand:MVE_0 3 "s_register_operand" "w")
7624 (match_operand:HI 4 "vpr_register_operand" "Up")]
7625 VCMLAQ_M_F))
7626 ]
7627 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7628 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7629 [(set_attr "type" "mve_move")
7630 (set_attr "length""8")])
7631
7632;;
7633;; [vcmlaq_rot180_m_f])
7634;;
7635(define_insn "mve_vcmlaq_rot180_m_f<mode>"
7636 [
7637 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7638 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7639 (match_operand:MVE_0 2 "s_register_operand" "w")
7640 (match_operand:MVE_0 3 "s_register_operand" "w")
7641 (match_operand:HI 4 "vpr_register_operand" "Up")]
7642 VCMLAQ_ROT180_M_F))
7643 ]
7644 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7645 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7646 [(set_attr "type" "mve_move")
7647 (set_attr "length""8")])
7648
7649;;
7650;; [vcmlaq_rot270_m_f])
7651;;
7652(define_insn "mve_vcmlaq_rot270_m_f<mode>"
7653 [
7654 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7655 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7656 (match_operand:MVE_0 2 "s_register_operand" "w")
7657 (match_operand:MVE_0 3 "s_register_operand" "w")
7658 (match_operand:HI 4 "vpr_register_operand" "Up")]
7659 VCMLAQ_ROT270_M_F))
7660 ]
7661 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7662 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7663 [(set_attr "type" "mve_move")
7664 (set_attr "length""8")])
7665
7666;;
7667;; [vcmlaq_rot90_m_f])
7668;;
7669(define_insn "mve_vcmlaq_rot90_m_f<mode>"
7670 [
7671 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7672 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7673 (match_operand:MVE_0 2 "s_register_operand" "w")
7674 (match_operand:MVE_0 3 "s_register_operand" "w")
7675 (match_operand:HI 4 "vpr_register_operand" "Up")]
7676 VCMLAQ_ROT90_M_F))
7677 ]
7678 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7679 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7680 [(set_attr "type" "mve_move")
7681 (set_attr "length""8")])
7682
7683;;
7684;; [vcmulq_m_f])
7685;;
7686(define_insn "mve_vcmulq_m_f<mode>"
7687 [
7688 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7689 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7690 (match_operand:MVE_0 2 "s_register_operand" "w")
7691 (match_operand:MVE_0 3 "s_register_operand" "w")
7692 (match_operand:HI 4 "vpr_register_operand" "Up")]
7693 VCMULQ_M_F))
7694 ]
7695 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7696 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0"
7697 [(set_attr "type" "mve_move")
7698 (set_attr "length""8")])
7699
7700;;
7701;; [vcmulq_rot180_m_f])
7702;;
7703(define_insn "mve_vcmulq_rot180_m_f<mode>"
7704 [
7705 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7706 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7707 (match_operand:MVE_0 2 "s_register_operand" "w")
7708 (match_operand:MVE_0 3 "s_register_operand" "w")
7709 (match_operand:HI 4 "vpr_register_operand" "Up")]
7710 VCMULQ_ROT180_M_F))
7711 ]
7712 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7713 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180"
7714 [(set_attr "type" "mve_move")
7715 (set_attr "length""8")])
7716
7717;;
7718;; [vcmulq_rot270_m_f])
7719;;
7720(define_insn "mve_vcmulq_rot270_m_f<mode>"
7721 [
7722 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7723 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7724 (match_operand:MVE_0 2 "s_register_operand" "w")
7725 (match_operand:MVE_0 3 "s_register_operand" "w")
7726 (match_operand:HI 4 "vpr_register_operand" "Up")]
7727 VCMULQ_ROT270_M_F))
7728 ]
7729 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7730 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270"
7731 [(set_attr "type" "mve_move")
7732 (set_attr "length""8")])
7733
7734;;
7735;; [vcmulq_rot90_m_f])
7736;;
7737(define_insn "mve_vcmulq_rot90_m_f<mode>"
7738 [
7739 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7740 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7741 (match_operand:MVE_0 2 "s_register_operand" "w")
7742 (match_operand:MVE_0 3 "s_register_operand" "w")
7743 (match_operand:HI 4 "vpr_register_operand" "Up")]
7744 VCMULQ_ROT90_M_F))
7745 ]
7746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7747 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90"
7748 [(set_attr "type" "mve_move")
7749 (set_attr "length""8")])
7750
7751;;
7752;; [veorq_m_f])
7753;;
7754(define_insn "mve_veorq_m_f<mode>"
7755 [
7756 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7757 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7758 (match_operand:MVE_0 2 "s_register_operand" "w")
7759 (match_operand:MVE_0 3 "s_register_operand" "w")
7760 (match_operand:HI 4 "vpr_register_operand" "Up")]
7761 VEORQ_M_F))
7762 ]
7763 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7764 "vpst\;veort %q0, %q2, %q3"
7765 [(set_attr "type" "mve_move")
7766 (set_attr "length""8")])
7767
7768;;
7769;; [vfmaq_m_f])
7770;;
7771(define_insn "mve_vfmaq_m_f<mode>"
7772 [
7773 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7774 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7775 (match_operand:MVE_0 2 "s_register_operand" "w")
7776 (match_operand:MVE_0 3 "s_register_operand" "w")
7777 (match_operand:HI 4 "vpr_register_operand" "Up")]
7778 VFMAQ_M_F))
7779 ]
7780 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7781 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3"
7782 [(set_attr "type" "mve_move")
7783 (set_attr "length""8")])
7784
7785;;
7786;; [vfmaq_m_n_f])
7787;;
7788(define_insn "mve_vfmaq_m_n_f<mode>"
7789 [
7790 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7791 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7792 (match_operand:MVE_0 2 "s_register_operand" "w")
7793 (match_operand:<V_elem> 3 "s_register_operand" "r")
7794 (match_operand:HI 4 "vpr_register_operand" "Up")]
7795 VFMAQ_M_N_F))
7796 ]
7797 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7798 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3"
7799 [(set_attr "type" "mve_move")
7800 (set_attr "length""8")])
7801
7802;;
7803;; [vfmasq_m_n_f])
7804;;
7805(define_insn "mve_vfmasq_m_n_f<mode>"
7806 [
7807 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7808 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7809 (match_operand:MVE_0 2 "s_register_operand" "w")
7810 (match_operand:<V_elem> 3 "s_register_operand" "r")
7811 (match_operand:HI 4 "vpr_register_operand" "Up")]
7812 VFMASQ_M_N_F))
7813 ]
7814 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7815 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3"
7816 [(set_attr "type" "mve_move")
7817 (set_attr "length""8")])
7818
7819;;
7820;; [vfmsq_m_f])
7821;;
7822(define_insn "mve_vfmsq_m_f<mode>"
7823 [
7824 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7825 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7826 (match_operand:MVE_0 2 "s_register_operand" "w")
7827 (match_operand:MVE_0 3 "s_register_operand" "w")
7828 (match_operand:HI 4 "vpr_register_operand" "Up")]
7829 VFMSQ_M_F))
7830 ]
7831 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7832 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3"
7833 [(set_attr "type" "mve_move")
7834 (set_attr "length""8")])
7835
7836;;
7837;; [vmaxnmq_m_f])
7838;;
7839(define_insn "mve_vmaxnmq_m_f<mode>"
7840 [
7841 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7842 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7843 (match_operand:MVE_0 2 "s_register_operand" "w")
7844 (match_operand:MVE_0 3 "s_register_operand" "w")
7845 (match_operand:HI 4 "vpr_register_operand" "Up")]
7846 VMAXNMQ_M_F))
7847 ]
7848 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7849 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7850 [(set_attr "type" "mve_move")
7851 (set_attr "length""8")])
7852
7853;;
7854;; [vminnmq_m_f])
7855;;
7856(define_insn "mve_vminnmq_m_f<mode>"
7857 [
7858 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7859 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7860 (match_operand:MVE_0 2 "s_register_operand" "w")
7861 (match_operand:MVE_0 3 "s_register_operand" "w")
7862 (match_operand:HI 4 "vpr_register_operand" "Up")]
7863 VMINNMQ_M_F))
7864 ]
7865 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7866 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3"
7867 [(set_attr "type" "mve_move")
7868 (set_attr "length""8")])
7869
7870;;
7871;; [vmulq_m_f])
7872;;
7873(define_insn "mve_vmulq_m_f<mode>"
7874 [
7875 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7876 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7877 (match_operand:MVE_0 2 "s_register_operand" "w")
7878 (match_operand:MVE_0 3 "s_register_operand" "w")
7879 (match_operand:HI 4 "vpr_register_operand" "Up")]
7880 VMULQ_M_F))
7881 ]
7882 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7883 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3"
7884 [(set_attr "type" "mve_move")
7885 (set_attr "length""8")])
7886
7887;;
7888;; [vmulq_m_n_f])
7889;;
7890(define_insn "mve_vmulq_m_n_f<mode>"
7891 [
7892 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7893 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7894 (match_operand:MVE_0 2 "s_register_operand" "w")
7895 (match_operand:<V_elem> 3 "s_register_operand" "r")
7896 (match_operand:HI 4 "vpr_register_operand" "Up")]
7897 VMULQ_M_N_F))
7898 ]
7899 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7900 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3"
7901 [(set_attr "type" "mve_move")
7902 (set_attr "length""8")])
7903
7904;;
7905;; [vornq_m_f])
7906;;
7907(define_insn "mve_vornq_m_f<mode>"
7908 [
7909 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7910 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7911 (match_operand:MVE_0 2 "s_register_operand" "w")
7912 (match_operand:MVE_0 3 "s_register_operand" "w")
7913 (match_operand:HI 4 "vpr_register_operand" "Up")]
7914 VORNQ_M_F))
7915 ]
7916 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7917 "vpst\;vornt %q0, %q2, %q3"
7918 [(set_attr "type" "mve_move")
7919 (set_attr "length""8")])
7920
7921;;
7922;; [vorrq_m_f])
7923;;
7924(define_insn "mve_vorrq_m_f<mode>"
7925 [
7926 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7927 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7928 (match_operand:MVE_0 2 "s_register_operand" "w")
7929 (match_operand:MVE_0 3 "s_register_operand" "w")
7930 (match_operand:HI 4 "vpr_register_operand" "Up")]
7931 VORRQ_M_F))
7932 ]
7933 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7934 "vpst\;vorrt %q0, %q2, %q3"
7935 [(set_attr "type" "mve_move")
7936 (set_attr "length""8")])
7937
7938;;
7939;; [vsubq_m_f])
7940;;
7941(define_insn "mve_vsubq_m_f<mode>"
7942 [
7943 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7944 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7945 (match_operand:MVE_0 2 "s_register_operand" "w")
7946 (match_operand:MVE_0 3 "s_register_operand" "w")
7947 (match_operand:HI 4 "vpr_register_operand" "Up")]
7948 VSUBQ_M_F))
7949 ]
7950 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7951 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3"
7952 [(set_attr "type" "mve_move")
7953 (set_attr "length""8")])
7954
7955;;
7956;; [vsubq_m_n_f])
7957;;
7958(define_insn "mve_vsubq_m_n_f<mode>"
7959 [
7960 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
7961 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
7962 (match_operand:MVE_0 2 "s_register_operand" "w")
7963 (match_operand:<V_elem> 3 "s_register_operand" "r")
7964 (match_operand:HI 4 "vpr_register_operand" "Up")]
7965 VSUBQ_M_N_F))
7966 ]
7967 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
7968 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
7969 [(set_attr "type" "mve_move")
7970 (set_attr "length""8")])
4ff68575
SP		 7971
7972;;
7973;; [vstrbq_s vstrbq_u]
7974;;
7975(define_insn "mve_vstrbq_<supf><mode>"
7976 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
7977 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
7978 VSTRBQ))
7979 ]
7980 "TARGET_HAVE_MVE"
7981{
7982 rtx ops[2];
7983 int regno = REGNO (operands[1]);
7984 ops[1] = gen_rtx_REG (TImode, regno);
7985 ops[0] = operands[0];
7986 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
7987 return "";
7988}
7989 [(set_attr "length" "4")])
7990
7991;;
7992;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
7993;;
7994(define_insn "mve_vstrbq_scatter_offset_<supf><mode>"
7995 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
7996 (unspec:<MVE_B_ELEM>
7997 [(match_operand:MVE_2 1 "s_register_operand" "w")
7998 (match_operand:MVE_2 2 "s_register_operand" "w")]
7999 VSTRBSOQ))
8000 ]
8001 "TARGET_HAVE_MVE"
8002{
8003 rtx ops[3];
8004 ops[0] = operands[0];
8005 ops[1] = operands[1];
8006 ops[2] = operands[2];
8007 output_asm_insn("vstrb.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8008 return "";
8009}
8010 [(set_attr "length" "4")])
8011
8012;;
8013;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
8014;;
8015(define_insn "mve_vstrwq_scatter_base_<supf>v4si"
8016 [(set (mem:BLK (scratch))
8017 (unspec:BLK
8018 [(match_operand:V4SI 0 "s_register_operand" "w")
8019 (match_operand:SI 1 "immediate_operand" "i")
8020 (match_operand:V4SI 2 "s_register_operand" "w")]
8021 VSTRWSBQ))
8022 ]
8023 "TARGET_HAVE_MVE"
8024{
8025 rtx ops[3];
8026 ops[0] = operands[0];
8027 ops[1] = operands[1];
8028 ops[2] = operands[2];
8029 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
8030 return "";
8031}
8032 [(set_attr "length" "4")])
535a8645
SP		 8033
8034;;
8035;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
8036;;
8037(define_insn "mve_vldrbq_gather_offset_<supf><mode>"
8038 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8039 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8040 (match_operand:MVE_2 2 "s_register_operand" "w")]
8041 VLDRBGOQ))
8042 ]
8043 "TARGET_HAVE_MVE"
8044{
8045 rtx ops[3];
8046 ops[0] = operands[0];
8047 ops[1] = operands[1];
8048 ops[2] = operands[2];
8049 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8050 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
8051 else
8052 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8053 return "";
8054}
8055 [(set_attr "length" "4")])
8056
8057;;
8058;; [vldrbq_s vldrbq_u]
8059;;
8060(define_insn "mve_vldrbq_<supf><mode>"
8061 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8062 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")]
8063 VLDRBQ))
8064 ]
8065 "TARGET_HAVE_MVE"
8066{
8067 rtx ops[2];
8068 int regno = REGNO (operands[0]);
8069 ops[0] = gen_rtx_REG (TImode, regno);
8070 ops[1] = operands[1];
8071 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
8072 return "";
8073}
8074 [(set_attr "length" "4")])
8075
8076;;
8077;; [vldrwq_gather_base_s vldrwq_gather_base_u]
8078;;
8079(define_insn "mve_vldrwq_gather_base_<supf>v4si"
8080 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8081 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8082 (match_operand:SI 2 "immediate_operand" "i")]
8083 VLDRWGBQ))
8084 ]
8085 "TARGET_HAVE_MVE"
8086{
8087 rtx ops[3];
8088 ops[0] = operands[0];
8089 ops[1] = operands[1];
8090 ops[2] = operands[2];
8091 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
8092 return "";
8093}
8094 [(set_attr "length" "4")])
405e918c
SP		 8095
8096;;
8097;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
8098;;
8099(define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>"
8100 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8101 (unspec:<MVE_B_ELEM>
8102 [(match_operand:MVE_2 1 "s_register_operand" "w")
8103 (match_operand:MVE_2 2 "s_register_operand" "w")
8104 (match_operand:HI 3 "vpr_register_operand" "Up")]
8105 VSTRBSOQ))
8106 ]
8107 "TARGET_HAVE_MVE"
8108{
8109 rtx ops[3];
8110 ops[0] = operands[0];
8111 ops[1] = operands[1];
8112 ops[2] = operands[2];
8113 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
8114 return "";
8115}
8116 [(set_attr "length" "8")])
8117
8118;;
8119;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
8120;;
8121(define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
8122 [(set (mem:BLK (scratch))
8123 (unspec:BLK
8124 [(match_operand:V4SI 0 "s_register_operand" "w")
8125 (match_operand:SI 1 "immediate_operand" "i")
8126 (match_operand:V4SI 2 "s_register_operand" "w")
8127 (match_operand:HI 3 "vpr_register_operand" "Up")]
8128 VSTRWSBQ))
8129 ]
8130 "TARGET_HAVE_MVE"
8131{
8132 rtx ops[3];
8133 ops[0] = operands[0];
8134 ops[1] = operands[1];
8135 ops[2] = operands[2];
8136 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
8137 return "";
8138}
8139 [(set_attr "length" "8")])
8140
8141;;
8142;; [vstrbq_p_s vstrbq_p_u]
8143;;
8144(define_insn "mve_vstrbq_p_<supf><mode>"
8145 [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
8146 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
8147 (match_operand:HI 2 "vpr_register_operand" "Up")]
8148 VSTRBQ))
8149 ]
8150 "TARGET_HAVE_MVE"
8151{
8152 rtx ops[2];
8153 int regno = REGNO (operands[1]);
8154 ops[1] = gen_rtx_REG (TImode, regno);
8155 ops[0] = operands[0];
8156 output_asm_insn ("vpst\n\tvstrbt.<V_sz_elem>\t%q1, %E0",ops);
8157 return "";
8158}
8159 [(set_attr "length" "8")])
429d607b
SP		 8160
8161;;
8162;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
8163;;
8164(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
8165 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
8166 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8167 (match_operand:MVE_2 2 "s_register_operand" "w")
8168 (match_operand:HI 3 "vpr_register_operand" "Up")]
8169 VLDRBGOQ))
8170 ]
8171 "TARGET_HAVE_MVE"
8172{
8173 rtx ops[4];
8174 ops[0] = operands[0];
8175 ops[1] = operands[1];
8176 ops[2] = operands[2];
8177 ops[3] = operands[3];
8178 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
8179 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
8180 else
8181 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8182 return "";
8183}
8184 [(set_attr "length" "8")])
8185
8186;;
8187;; [vldrbq_z_s vldrbq_z_u]
8188;;
8189(define_insn "mve_vldrbq_z_<supf><mode>"
8190 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
8191 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
8192 (match_operand:HI 2 "vpr_register_operand" "Up")]
8193 VLDRBQ))
8194 ]
8195 "TARGET_HAVE_MVE"
8196{
8197 rtx ops[2];
8198 int regno = REGNO (operands[0]);
8199 ops[0] = gen_rtx_REG (TImode, regno);
8200 ops[1] = operands[1];
8201 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
8202 return "";
8203}
8204 [(set_attr "length" "8")])
8205
8206;;
8207;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
8208;;
8209(define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
8210 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
8211 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
8212 (match_operand:SI 2 "immediate_operand" "i")
8213 (match_operand:HI 3 "vpr_register_operand" "Up")]
8214 VLDRWGBQ))
8215 ]
8216 "TARGET_HAVE_MVE"
8217{
8218 rtx ops[3];
8219 ops[0] = operands[0];
8220 ops[1] = operands[1];
8221 ops[2] = operands[2];
8222 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
8223 return "";
8224}
8225 [(set_attr "length" "8")])
bf1e3d5a
SP		 8226
8227;;
8228;; [vldrhq_f]
8229;;
8230(define_insn "mve_vldrhq_fv8hf"
8231 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8232 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]
8233 VLDRHQ_F))
8234 ]
8235 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8236{
8237 rtx ops[2];
8238 int regno = REGNO (operands[0]);
8239 ops[0] = gen_rtx_REG (TImode, regno);
8240 ops[1] = operands[1];
8241 output_asm_insn ("vldrh.f16\t%q0, %E1",ops);
8242 return "";
8243}
8244 [(set_attr "length" "4")])
8245
8246;;
8247;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
8248;;
8249(define_insn "mve_vldrhq_gather_offset_<supf><mode>"
8250 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8251 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8252 (match_operand:MVE_6 2 "s_register_operand" "w")]
8253 VLDRHGOQ))
8254 ]
8255 "TARGET_HAVE_MVE"
8256{
8257 rtx ops[3];
8258 ops[0] = operands[0];
8259 ops[1] = operands[1];
8260 ops[2] = operands[2];
8261 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8262 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
8263 else
8264 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8265 return "";
8266}
8267 [(set_attr "length" "4")])
8268
8269;;
8270;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
8271;;
8272(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
8273 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8274 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8275 (match_operand:MVE_6 2 "s_register_operand" "w")
8276 (match_operand:HI 3 "vpr_register_operand" "Up")
8277 ]VLDRHGOQ))
8278 ]
8279 "TARGET_HAVE_MVE"
8280{
8281 rtx ops[4];
8282 ops[0] = operands[0];
8283 ops[1] = operands[1];
8284 ops[2] = operands[2];
8285 ops[3] = operands[3];
8286 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8287 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
8288 else
8289 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
8290 return "";
8291}
8292 [(set_attr "length" "8")])
8293
8294;;
8295;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
8296;;
8297(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
8298 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8299 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8300 (match_operand:MVE_6 2 "s_register_operand" "w")]
8301 VLDRHGSOQ))
8302 ]
8303 "TARGET_HAVE_MVE"
8304{
8305 rtx ops[3];
8306 ops[0] = operands[0];
8307 ops[1] = operands[1];
8308 ops[2] = operands[2];
8309 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8310 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8311 else
8312 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8313 return "";
8314}
8315 [(set_attr "length" "4")])
8316
8317;;
8318;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
8319;;
8320(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
8321 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
8322 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8323 (match_operand:MVE_6 2 "s_register_operand" "w")
8324 (match_operand:HI 3 "vpr_register_operand" "Up")
8325 ]VLDRHGSOQ))
8326 ]
8327 "TARGET_HAVE_MVE"
8328{
8329 rtx ops[4];
8330 ops[0] = operands[0];
8331 ops[1] = operands[1];
8332 ops[2] = operands[2];
8333 ops[3] = operands[3];
8334 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
8335 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
8336 else
8337 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
8338 return "";
8339}
8340 [(set_attr "length" "8")])
8341
8342;;
8343;;
8344;; [vldrhq_s, vldrhq_u]
8345;;
8346(define_insn "mve_vldrhq_<supf><mode>"
8347 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8348 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")]
8349 VLDRHQ))
8350 ]
8351 "TARGET_HAVE_MVE"
8352{
8353 rtx ops[2];
8354 int regno = REGNO (operands[0]);
8355 ops[0] = gen_rtx_REG (TImode, regno);
8356 ops[1] = operands[1];
8357 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
8358 return "";
8359}
8360 [(set_attr "length" "4")])
8361
8362;;
8363;; [vldrhq_z_f]
8364;;
8365(define_insn "mve_vldrhq_z_fv8hf"
8366 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
8367 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
8368 (match_operand:HI 2 "vpr_register_operand" "Up")]
8369 VLDRHQ_F))
8370 ]
8371 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8372{
8373 rtx ops[2];
8374 int regno = REGNO (operands[0]);
8375 ops[0] = gen_rtx_REG (TImode, regno);
8376 ops[1] = operands[1];
8377 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);
8378 return "";
8379}
8380 [(set_attr "length" "8")])
8381
8382;;
8383;; [vldrhq_z_s vldrhq_z_u]
8384;;
8385(define_insn "mve_vldrhq_z_<supf><mode>"
8386 [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
8387 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
8388 (match_operand:HI 2 "vpr_register_operand" "Up")]
8389 VLDRHQ))
8390 ]
8391 "TARGET_HAVE_MVE"
8392{
8393 rtx ops[2];
8394 int regno = REGNO (operands[0]);
8395 ops[0] = gen_rtx_REG (TImode, regno);
8396 ops[1] = operands[1];
8397 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
8398 return "";
8399}
8400 [(set_attr "length" "8")])
8401
8402;;
8403;; [vldrwq_f]
8404;;
8405(define_insn "mve_vldrwq_fv4sf"
8406 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8407 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]
8408 VLDRWQ_F))
8409 ]
8410 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8411{
8412 rtx ops[2];
8413 int regno = REGNO (operands[0]);
8414 ops[0] = gen_rtx_REG (TImode, regno);
8415 ops[1] = operands[1];
8416 output_asm_insn ("vldrw.f32\t%q0, %E1",ops);
8417 return "";
8418}
8419 [(set_attr "length" "4")])
8420
8421;;
8422;; [vldrwq_s vldrwq_u]
8423;;
8424(define_insn "mve_vldrwq_<supf>v4si"
8425 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8426 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]
8427 VLDRWQ))
8428 ]
8429 "TARGET_HAVE_MVE"
8430{
8431 rtx ops[2];
8432 int regno = REGNO (operands[0]);
8433 ops[0] = gen_rtx_REG (TImode, regno);
8434 ops[1] = operands[1];
8435 output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);
8436 return "";
8437}
8438 [(set_attr "length" "4")])
8439
8440;;
8441;; [vldrwq_z_f]
8442;;
8443(define_insn "mve_vldrwq_z_fv4sf"
8444 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
8445 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
8446 (match_operand:HI 2 "vpr_register_operand" "Up")]
8447 VLDRWQ_F))
8448 ]
8449 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
8450{
8451 rtx ops[2];
8452 int regno = REGNO (operands[0]);
8453 ops[0] = gen_rtx_REG (TImode, regno);
8454 ops[1] = operands[1];
8455 output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);
8456 return "";
8457}
8458 [(set_attr "length" "8")])
8459
8460;;
8461;; [vldrwq_z_s vldrwq_z_u]
8462;;
8463(define_insn "mve_vldrwq_z_<supf>v4si"
8464 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
8465 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
8466 (match_operand:HI 2 "vpr_register_operand" "Up")]
8467 VLDRWQ))
8468 ]
8469 "TARGET_HAVE_MVE"
8470{
8471 rtx ops[2];
8472 int regno = REGNO (operands[0]);
8473 ops[0] = gen_rtx_REG (TImode, regno);
8474 ops[1] = operands[1];
8475 output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);
8476 return "";
8477}
8478 [(set_attr "length" "8")])
8479
8480(define_expand "mve_vld1q_f<mode>"
8481 [(match_operand:MVE_0 0 "s_register_operand")
8482 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")] VLD1Q_F)
8483 ]
8484 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
8485{
8486 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
8487 DONE;
8488})
8489
8490(define_expand "mve_vld1q_<supf><mode>"
8491 [(match_operand:MVE_2 0 "s_register_operand")
8492 (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)
8493 ]
8494 "TARGET_HAVE_MVE"
8495{
8496 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
8497 DONE;
8498})
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