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63c8f7d6 | 1 | ;; Arm M-profile Vector Extension Machine Description |
aeee4812 | 2 | ;; Copyright (C) 2019-2023 Free Software Foundation, Inc. |
63c8f7d6 SP |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but | |
12 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | ;; General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
63c8f7d6 | 20 | (define_insn "*mve_mov<mode>" |
94018fd2 RE |
21 | [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w , w, r,Ux,w") |
22 | (match_operand:MVE_types 1 "general_operand" " w,r,w,DnDm,UxUi,r,w, Ul"))] | |
63c8f7d6 SP |
23 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" |
24 | { | |
94018fd2 | 25 | switch (which_alternative) |
63c8f7d6 | 26 | { |
94018fd2 RE |
27 | case 0: /* [w,w]. */ |
28 | return "vmov\t%q0, %q1"; | |
63c8f7d6 | 29 | |
94018fd2 RE |
30 | case 1: /* [w,r]. */ |
31 | return "vmov\t%e0, %Q1, %R1 %@ <mode>\;vmov\t%f0, %J1, %K1"; | |
63c8f7d6 | 32 | |
94018fd2 RE |
33 | case 2: /* [r,w]. */ |
34 | return "vmov\t%Q0, %R0, %e1 %@ <mode>\;vmov\t%J0, %K0, %f1"; | |
63c8f7d6 | 35 | |
94018fd2 RE |
36 | case 3: /* [w,DnDm]. */ |
37 | { | |
38 | int width, is_valid; | |
d91524d5 | 39 | |
94018fd2 RE |
40 | is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode, |
41 | &operands[1], &width); | |
42 | ||
43 | gcc_assert (is_valid); | |
44 | ||
45 | if (width == 0) | |
46 | return "vmov.f32\t%q0, %1 %@ <mode>"; | |
47 | else | |
48 | { | |
49 | const int templ_size = 40; | |
50 | static char templ[templ_size]; | |
51 | if (snprintf (templ, templ_size, | |
52 | "vmov.i%d\t%%q0, %%x1 %%@ <mode>", width) | |
53 | > templ_size) | |
54 | abort (); | |
55 | return templ; | |
56 | } | |
57 | } | |
58 | ||
59 | case 4: /* [w,UxUi]. */ | |
60 | if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode | |
61 | || <MODE>mode == TImode) | |
62 | return "vldrw.u32\t%q0, %E1"; | |
d91524d5 | 63 | else |
94018fd2 RE |
64 | return "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1"; |
65 | ||
66 | case 5: /* [r,r]. */ | |
0efe7d87 | 67 | return output_move_quad (operands); |
94018fd2 RE |
68 | |
69 | case 6: /* [Ux,w]. */ | |
70 | if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode | |
71 | || <MODE>mode == TImode) | |
72 | return "vstrw.32\t%q1, %E0"; | |
73 | else | |
74 | return "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0"; | |
75 | ||
76 | case 7: /* [w,Ul]. */ | |
d91524d5 | 77 | return output_move_neon (operands); |
94018fd2 | 78 | |
63c8f7d6 SP |
79 | default: |
80 | gcc_unreachable (); | |
81 | return ""; | |
82 | } | |
83 | } | |
94018fd2 RE |
84 | [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_store,mve_load") |
85 | (set_attr "length" "4,8,8,4,4,8,4,8") | |
86 | (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") | |
87 | (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) | |
63c8f7d6 | 88 | |
67d56b27 AC |
89 | (define_insn "*mve_vdup<mode>" |
90 | [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w") | |
91 | (vec_duplicate:MVE_vecs | |
92 | (match_operand:<V_elem> 1 "s_register_operand" "r")))] | |
63c8f7d6 | 93 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" |
67d56b27 AC |
94 | "vdup.<V_sz_elem>\t%q0, %1" |
95 | [(set_attr "length" "4") | |
96 | (set_attr "type" "mve_move")]) | |
14782c81 SP |
97 | |
98 | ;; | |
99 | ;; [vst4q]) | |
100 | ;; | |
101 | (define_insn "mve_vst4q<mode>" | |
4269a656 | 102 | [(set (match_operand:XI 0 "mve_struct_operand" "=Ug") |
14782c81 SP |
103 | (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") |
104 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
105 | VST4Q)) | |
106 | ] | |
107 | "TARGET_HAVE_MVE" | |
108 | { | |
109 | rtx ops[6]; | |
110 | int regno = REGNO (operands[1]); | |
111 | ops[0] = gen_rtx_REG (TImode, regno); | |
112 | ops[1] = gen_rtx_REG (TImode, regno+4); | |
113 | ops[2] = gen_rtx_REG (TImode, regno+8); | |
114 | ops[3] = gen_rtx_REG (TImode, regno+12); | |
115 | rtx reg = operands[0]; | |
116 | while (reg && !REG_P (reg)) | |
117 | reg = XEXP (reg, 0); | |
118 | gcc_assert (REG_P (reg)); | |
119 | ops[4] = reg; | |
120 | ops[5] = operands[0]; | |
121 | /* Here in first three instructions data is stored to ops[4]'s location but | |
122 | in the fourth instruction data is stored to operands[0], this is to | |
123 | support the writeback. */ | |
124 | output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
125 | "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
126 | "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
127 | "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); | |
128 | return ""; | |
129 | } | |
130 | [(set_attr "length" "16")]) | |
a50f6abf | 131 | |
e3678b44 | 132 | ;; |
7734b991 CL |
133 | ;; [vrndaq_f] |
134 | ;; [vrndmq_f] | |
135 | ;; [vrndnq_f] | |
136 | ;; [vrndpq_f] | |
137 | ;; [vrndq_f] | |
138 | ;; [vrndxq_f] | |
e3678b44 | 139 | ;; |
7734b991 | 140 | (define_insn "@mve_<mve_insn>q_f<mode>" |
a50f6abf SP |
141 | [ |
142 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
143 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
7734b991 | 144 | MVE_FP_UNARY)) |
a50f6abf SP |
145 | ] |
146 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7734b991 | 147 | "<mve_mnemo>.f%#<V_sz_elem>\t%q0, %q1" |
a50f6abf SP |
148 | [(set_attr "type" "mve_move") |
149 | ]) | |
150 | ||
151 | ;; | |
152 | ;; [vrev64q_f]) | |
153 | ;; | |
0c1eb901 | 154 | (define_insn "@mve_<mve_insn>q_f<mode>" |
a50f6abf | 155 | [ |
6debbff6 | 156 | (set (match_operand:MVE_0 0 "s_register_operand" "=&w") |
a50f6abf | 157 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] |
0c1eb901 | 158 | MVE_FP_VREV64Q_ONLY)) |
a50f6abf SP |
159 | ] |
160 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
0c1eb901 | 161 | "<mve_insn>.%#<V_sz_elem>\t%q0, %q1" |
a50f6abf SP |
162 | [(set_attr "type" "mve_move") |
163 | ]) | |
164 | ||
165 | ;; | |
7734b991 CL |
166 | ;; [vabsq_f] |
167 | ;; [vnegq_f] | |
a50f6abf | 168 | ;; |
7734b991 | 169 | (define_insn "mve_v<absneg_str>q_f<mode>" |
a50f6abf SP |
170 | [ |
171 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
7734b991 | 172 | (ABSNEG:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) |
a50f6abf SP |
173 | ] |
174 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7734b991 | 175 | "v<absneg_str>.f%#<V_sz_elem>\t%q0, %q1" |
a50f6abf SP |
176 | [(set_attr "type" "mve_move") |
177 | ]) | |
178 | ||
179 | ;; | |
180 | ;; [vdupq_n_f]) | |
181 | ;; | |
fc468102 | 182 | (define_insn "@mve_<mve_insn>q_n_f<mode>" |
a50f6abf SP |
183 | [ |
184 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
185 | (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
fc468102 | 186 | MVE_FP_N_VDUPQ_ONLY)) |
a50f6abf SP |
187 | ] |
188 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
fc468102 | 189 | "<mve_insn>.%#<V_sz_elem>\t%q0, %1" |
a50f6abf SP |
190 | [(set_attr "type" "mve_move") |
191 | ]) | |
192 | ||
a50f6abf SP |
193 | ;; |
194 | ;; [vrev32q_f]) | |
195 | ;; | |
0c1eb901 | 196 | (define_insn "@mve_<mve_insn>q_f<mode>" |
a50f6abf | 197 | [ |
0c1eb901 CL |
198 | (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w") |
199 | (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "w")] | |
200 | MVE_FP_VREV32Q_ONLY)) | |
a50f6abf SP |
201 | ] |
202 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
0c1eb901 | 203 | "<mve_insn>.<V_sz_elem>\t%q0, %q1" |
a50f6abf SP |
204 | [(set_attr "type" "mve_move") |
205 | ]) | |
206 | ;; | |
207 | ;; [vcvttq_f32_f16]) | |
208 | ;; | |
209 | (define_insn "mve_vcvttq_f32_f16v4sf" | |
210 | [ | |
211 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
212 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
213 | VCVTTQ_F32_F16)) | |
214 | ] | |
215 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
216 | "vcvtt.f32.f16 %q0, %q1" | |
217 | [(set_attr "type" "mve_move") | |
218 | ]) | |
219 | ||
220 | ;; | |
221 | ;; [vcvtbq_f32_f16]) | |
222 | ;; | |
223 | (define_insn "mve_vcvtbq_f32_f16v4sf" | |
224 | [ | |
225 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
226 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
227 | VCVTBQ_F32_F16)) | |
228 | ] | |
229 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
230 | "vcvtb.f32.f16 %q0, %q1" | |
231 | [(set_attr "type" "mve_move") | |
232 | ]) | |
233 | ||
234 | ;; | |
235 | ;; [vcvtq_to_f_s, vcvtq_to_f_u]) | |
236 | ;; | |
237 | (define_insn "mve_vcvtq_to_f_<supf><mode>" | |
238 | [ | |
239 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
240 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
241 | VCVTQ_TO_F)) | |
242 | ] | |
243 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
244 | "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1" | |
245 | [(set_attr "type" "mve_move") | |
246 | ]) | |
5db0eb95 SP |
247 | |
248 | ;; | |
249 | ;; [vrev64q_u, vrev64q_s]) | |
250 | ;; | |
0c1eb901 | 251 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
5db0eb95 | 252 | [ |
6debbff6 | 253 | (set (match_operand:MVE_2 0 "s_register_operand" "=&w") |
5db0eb95 SP |
254 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] |
255 | VREV64Q)) | |
256 | ] | |
257 | "TARGET_HAVE_MVE" | |
0c1eb901 | 258 | "<mve_insn>.%#<V_sz_elem>\t%q0, %q1" |
5db0eb95 SP |
259 | [(set_attr "type" "mve_move") |
260 | ]) | |
261 | ||
262 | ;; | |
263 | ;; [vcvtq_from_f_s, vcvtq_from_f_u]) | |
264 | ;; | |
265 | (define_insn "mve_vcvtq_from_f_<supf><mode>" | |
266 | [ | |
267 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
268 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
269 | VCVTQ_FROM_F)) | |
270 | ] | |
271 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
272 | "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
273 | [(set_attr "type" "mve_move") | |
274 | ]) | |
6df4618c SP |
275 | |
276 | ;; | |
7734b991 CL |
277 | ;; [vabsq_s] |
278 | ;; [vnegq_s] | |
6df4618c | 279 | ;; |
7734b991 | 280 | (define_insn "mve_v<absneg_str>q_s<mode>" |
6df4618c SP |
281 | [ |
282 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
7734b991 | 283 | (ABSNEG:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) |
6df4618c SP |
284 | ] |
285 | "TARGET_HAVE_MVE" | |
7734b991 | 286 | "v<absneg_str>.s%#<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
287 | [(set_attr "type" "mve_move") |
288 | ]) | |
289 | ||
290 | ;; | |
291 | ;; [vmvnq_u, vmvnq_s]) | |
292 | ;; | |
fd436034 | 293 | (define_insn "mve_vmvnq_u<mode>" |
6df4618c SP |
294 | [ |
295 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
fd436034 | 296 | (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) |
6df4618c SP |
297 | ] |
298 | "TARGET_HAVE_MVE" | |
fd436034 | 299 | "vmvn\t%q0, %q1" |
6df4618c SP |
300 | [(set_attr "type" "mve_move") |
301 | ]) | |
fd436034 CL |
302 | (define_expand "mve_vmvnq_s<mode>" |
303 | [ | |
304 | (set (match_operand:MVE_2 0 "s_register_operand") | |
305 | (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) | |
306 | ] | |
307 | "TARGET_HAVE_MVE" | |
308 | ) | |
6df4618c SP |
309 | |
310 | ;; | |
311 | ;; [vdupq_n_u, vdupq_n_s]) | |
312 | ;; | |
fc468102 | 313 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
6df4618c SP |
314 | [ |
315 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
316 | (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
317 | VDUPQ_N)) | |
318 | ] | |
319 | "TARGET_HAVE_MVE" | |
fc468102 | 320 | "<mve_insn>.%#<V_sz_elem>\t%q0, %1" |
6df4618c SP |
321 | [(set_attr "type" "mve_move") |
322 | ]) | |
323 | ||
324 | ;; | |
325 | ;; [vclzq_u, vclzq_s]) | |
326 | ;; | |
7969d9c8 | 327 | (define_insn "@mve_vclzq_s<mode>" |
6df4618c SP |
328 | [ |
329 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
7969d9c8 | 330 | (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) |
6df4618c SP |
331 | ] |
332 | "TARGET_HAVE_MVE" | |
16452c63 | 333 | "vclz.i%#<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
334 | [(set_attr "type" "mve_move") |
335 | ]) | |
7969d9c8 CL |
336 | (define_expand "mve_vclzq_u<mode>" |
337 | [ | |
338 | (set (match_operand:MVE_2 0 "s_register_operand") | |
339 | (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) | |
340 | ] | |
341 | "TARGET_HAVE_MVE" | |
342 | ) | |
6df4618c SP |
343 | |
344 | ;; | |
7734b991 CL |
345 | ;; [vclsq_s] |
346 | ;; [vqabsq_s] | |
347 | ;; [vqnegq_s] | |
6df4618c | 348 | ;; |
7734b991 | 349 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
6df4618c SP |
350 | [ |
351 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
352 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
7734b991 | 353 | MVE_INT_UNARY)) |
6df4618c SP |
354 | ] |
355 | "TARGET_HAVE_MVE" | |
7734b991 | 356 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
357 | [(set_attr "type" "mve_move") |
358 | ]) | |
359 | ||
360 | ;; | |
361 | ;; [vaddvq_s, vaddvq_u]) | |
362 | ;; | |
eb1ded46 | 363 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
6df4618c | 364 | [ |
3d537943 | 365 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
6df4618c SP |
366 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] |
367 | VADDVQ)) | |
368 | ] | |
369 | "TARGET_HAVE_MVE" | |
eb1ded46 | 370 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1" |
6df4618c SP |
371 | [(set_attr "type" "mve_move") |
372 | ]) | |
373 | ||
6df4618c SP |
374 | ;; |
375 | ;; [vrev32q_u, vrev32q_s]) | |
376 | ;; | |
0c1eb901 | 377 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
6df4618c SP |
378 | [ |
379 | (set (match_operand:MVE_3 0 "s_register_operand" "=w") | |
380 | (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
381 | VREV32Q)) | |
382 | ] | |
383 | "TARGET_HAVE_MVE" | |
0c1eb901 | 384 | "<mve_insn>.%#<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
385 | [(set_attr "type" "mve_move") |
386 | ]) | |
387 | ||
388 | ;; | |
51fca3e1 CL |
389 | ;; [vmovlbq_s, vmovlbq_u] |
390 | ;; [vmovltq_u, vmovltq_s] | |
6df4618c | 391 | ;; |
51fca3e1 | 392 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
6df4618c SP |
393 | [ |
394 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
395 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
51fca3e1 | 396 | VMOVLxQ)) |
6df4618c SP |
397 | ] |
398 | "TARGET_HAVE_MVE" | |
51fca3e1 | 399 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
400 | [(set_attr "type" "mve_move") |
401 | ]) | |
402 | ||
403 | ;; | |
404 | ;; [vcvtpq_s, vcvtpq_u]) | |
405 | ;; | |
406 | (define_insn "mve_vcvtpq_<supf><mode>" | |
407 | [ | |
408 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
409 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
410 | VCVTPQ)) | |
411 | ] | |
412 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
413 | "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
414 | [(set_attr "type" "mve_move") | |
415 | ]) | |
416 | ||
417 | ;; | |
418 | ;; [vcvtnq_s, vcvtnq_u]) | |
419 | ;; | |
420 | (define_insn "mve_vcvtnq_<supf><mode>" | |
421 | [ | |
422 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
423 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
424 | VCVTNQ)) | |
425 | ] | |
426 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
427 | "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
428 | [(set_attr "type" "mve_move") | |
429 | ]) | |
430 | ||
431 | ;; | |
432 | ;; [vcvtmq_s, vcvtmq_u]) | |
433 | ;; | |
434 | (define_insn "mve_vcvtmq_<supf><mode>" | |
435 | [ | |
436 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
437 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
438 | VCVTMQ)) | |
439 | ] | |
440 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
441 | "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
442 | [(set_attr "type" "mve_move") | |
443 | ]) | |
444 | ||
445 | ;; | |
446 | ;; [vcvtaq_u, vcvtaq_s]) | |
447 | ;; | |
448 | (define_insn "mve_vcvtaq_<supf><mode>" | |
449 | [ | |
450 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
451 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
452 | VCVTAQ)) | |
453 | ] | |
454 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
455 | "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
456 | [(set_attr "type" "mve_move") | |
457 | ]) | |
5db0eb95 SP |
458 | |
459 | ;; | |
460 | ;; [vmvnq_n_u, vmvnq_n_s]) | |
461 | ;; | |
462 | (define_insn "mve_vmvnq_n_<supf><mode>" | |
463 | [ | |
464 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
0d0aaea1 | 465 | (unspec:MVE_5 [(match_operand:<V_elem> 1 "immediate_operand" "i")] |
5db0eb95 SP |
466 | VMVNQ_N)) |
467 | ] | |
468 | "TARGET_HAVE_MVE" | |
469 | "vmvn.i%#<V_sz_elem> %q0, %1" | |
470 | [(set_attr "type" "mve_move") | |
471 | ]) | |
6df4618c SP |
472 | |
473 | ;; | |
474 | ;; [vrev16q_u, vrev16q_s]) | |
475 | ;; | |
0c1eb901 | 476 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
6df4618c | 477 | [ |
0c1eb901 CL |
478 | (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w") |
479 | (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "w")] | |
6df4618c SP |
480 | VREV16Q)) |
481 | ] | |
482 | "TARGET_HAVE_MVE" | |
0c1eb901 | 483 | "<mve_insn>.<V_sz_elem>\t%q0, %q1" |
6df4618c SP |
484 | [(set_attr "type" "mve_move") |
485 | ]) | |
486 | ||
487 | ;; | |
488 | ;; [vaddlvq_s vaddlvq_u]) | |
489 | ;; | |
fa2c9dbb | 490 | (define_insn "@mve_<mve_insn>q_<supf>v4si" |
6df4618c SP |
491 | [ |
492 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
493 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] | |
494 | VADDLVQ)) | |
495 | ] | |
496 | "TARGET_HAVE_MVE" | |
fa2c9dbb | 497 | "<mve_insn>.<supf>32\t%Q0, %R0, %q1" |
6df4618c SP |
498 | [(set_attr "type" "mve_move") |
499 | ]) | |
a475f153 SP |
500 | |
501 | ;; | |
502 | ;; [vctp8q vctp16q vctp32q vctp64q]) | |
503 | ;; | |
e0bc13d3 | 504 | (define_insn "mve_vctp<MVE_vctp>q<MVE_vpred>" |
a475f153 | 505 | [ |
e0bc13d3 AV |
506 | (set (match_operand:MVE_7 0 "vpr_register_operand" "=Up") |
507 | (unspec:MVE_7 [(match_operand:SI 1 "s_register_operand" "r")] | |
508 | VCTP)) | |
a475f153 SP |
509 | ] |
510 | "TARGET_HAVE_MVE" | |
e0bc13d3 | 511 | "vctp.<MVE_vctp> %1" |
a475f153 SP |
512 | [(set_attr "type" "mve_move") |
513 | ]) | |
514 | ||
515 | ;; | |
516 | ;; [vpnot]) | |
517 | ;; | |
e0bc13d3 | 518 | (define_insn "mve_vpnotv16bi" |
a475f153 | 519 | [ |
e0bc13d3 AV |
520 | (set (match_operand:V16BI 0 "vpr_register_operand" "=Up") |
521 | (unspec:V16BI [(match_operand:V16BI 1 "vpr_register_operand" "0")] | |
a475f153 SP |
522 | VPNOT)) |
523 | ] | |
524 | "TARGET_HAVE_MVE" | |
525 | "vpnot" | |
526 | [(set_attr "type" "mve_move") | |
527 | ]) | |
4be8cf77 | 528 | |
4be8cf77 SP |
529 | ;; |
530 | ;; [vbrsrq_n_f]) | |
531 | ;; | |
532 | (define_insn "mve_vbrsrq_n_f<mode>" | |
533 | [ | |
534 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
535 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
536 | (match_operand:SI 2 "s_register_operand" "r")] | |
537 | VBRSRQ_N_F)) | |
538 | ] | |
539 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
540 | "vbrsr.<V_sz_elem> %q0, %q1, %2" | |
541 | [(set_attr "type" "mve_move") | |
542 | ]) | |
543 | ||
544 | ;; | |
545 | ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) | |
546 | ;; | |
547 | (define_insn "mve_vcvtq_n_to_f_<supf><mode>" | |
548 | [ | |
549 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
550 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
d2ce75fe | 551 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] |
4be8cf77 SP |
552 | VCVTQ_N_TO_F)) |
553 | ] | |
554 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
555 | "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2" | |
556 | [(set_attr "type" "mve_move") | |
557 | ]) | |
558 | ||
559 | ;; [vcreateq_f]) | |
560 | ;; | |
dd04568f | 561 | (define_insn "@mve_<mve_insn>q_f<mode>" |
4be8cf77 SP |
562 | [ |
563 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
564 | (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") | |
565 | (match_operand:DI 2 "s_register_operand" "r")] | |
dd04568f | 566 | MVE_FP_CREATE_ONLY)) |
4be8cf77 SP |
567 | ] |
568 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3f0ca7a3 | 569 | "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" |
4be8cf77 SP |
570 | [(set_attr "type" "mve_move") |
571 | (set_attr "length""8")]) | |
f166a8cd SP |
572 | |
573 | ;; | |
574 | ;; [vcreateq_u, vcreateq_s]) | |
575 | ;; | |
dd04568f | 576 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
f166a8cd SP |
577 | [ |
578 | (set (match_operand:MVE_1 0 "s_register_operand" "=w") | |
579 | (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") | |
580 | (match_operand:DI 2 "s_register_operand" "r")] | |
581 | VCREATEQ)) | |
582 | ] | |
583 | "TARGET_HAVE_MVE" | |
3f0ca7a3 | 584 | "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" |
f166a8cd SP |
585 | [(set_attr "type" "mve_move") |
586 | (set_attr "length""8")]) | |
587 | ||
588 | ;; | |
6bb8a5bd CL |
589 | ;; [vrshrq_n_s, vrshrq_n_u] |
590 | ;; [vshrq_n_s, vshrq_n_u] | |
f166a8cd | 591 | ;; |
bfab3550 | 592 | ;; Version that takes an immediate as operand 2. |
6bb8a5bd | 593 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
f166a8cd SP |
594 | [ |
595 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
596 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
597 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] | |
6bb8a5bd | 598 | MVE_VSHRQ_N)) |
f166a8cd SP |
599 | ] |
600 | "TARGET_HAVE_MVE" | |
6bb8a5bd | 601 | "<mve_insn>.<supf><V_sz_elem>\t%q0, %q1, %2" |
f166a8cd SP |
602 | [(set_attr "type" "mve_move") |
603 | ]) | |
604 | ||
bfab3550 CL |
605 | ;; Versions that take constant vectors as operand 2 (with all elements |
606 | ;; equal). | |
607 | (define_insn "mve_vshrq_n_s<mode>_imm" | |
608 | [ | |
609 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
610 | (ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") | |
611 | (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) | |
612 | ] | |
613 | "TARGET_HAVE_MVE" | |
614 | { | |
615 | return neon_output_shift_immediate ("vshr", 's', &operands[2], | |
616 | <MODE>mode, | |
617 | VALID_NEON_QREG_MODE (<MODE>mode), | |
618 | true); | |
619 | } | |
620 | [(set_attr "type" "mve_move") | |
621 | ]) | |
622 | (define_insn "mve_vshrq_n_u<mode>_imm" | |
623 | [ | |
624 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
625 | (lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") | |
626 | (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) | |
627 | ] | |
628 | "TARGET_HAVE_MVE" | |
629 | { | |
630 | return neon_output_shift_immediate ("vshr", 'u', &operands[2], | |
631 | <MODE>mode, | |
632 | VALID_NEON_QREG_MODE (<MODE>mode), | |
633 | true); | |
634 | } | |
635 | [(set_attr "type" "mve_move") | |
636 | ]) | |
637 | ||
f166a8cd SP |
638 | ;; |
639 | ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) | |
640 | ;; | |
641 | (define_insn "mve_vcvtq_n_from_f_<supf><mode>" | |
642 | [ | |
643 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
644 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
d2ce75fe | 645 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] |
f166a8cd SP |
646 | VCVTQ_N_FROM_F)) |
647 | ] | |
648 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
649 | "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2" | |
650 | [(set_attr "type" "mve_move") | |
651 | ]) | |
d71dba7b SP |
652 | |
653 | ;; | |
654 | ;; [vaddlvq_p_s]) | |
655 | ;; | |
fa2c9dbb | 656 | (define_insn "@mve_<mve_insn>q_p_<supf>v4si" |
d71dba7b SP |
657 | [ |
658 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
659 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
c6b4ea7a | 660 | (match_operand:V4BI 2 "vpr_register_operand" "Up")] |
d71dba7b SP |
661 | VADDLVQ_P)) |
662 | ] | |
663 | "TARGET_HAVE_MVE" | |
fa2c9dbb | 664 | "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1" |
d71dba7b SP |
665 | [(set_attr "type" "mve_move") |
666 | (set_attr "length""8")]) | |
667 | ||
668 | ;; | |
d083fbf7 | 669 | ;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_]) |
d71dba7b | 670 | ;; |
a6eacbf1 | 671 | (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" |
d71dba7b | 672 | [ |
91224cf6 CL |
673 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
674 | (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") | |
d083fbf7 CL |
675 | (match_operand:MVE_2 2 "s_register_operand" "w"))) |
676 | ] | |
677 | "TARGET_HAVE_MVE" | |
1fa5a447 | 678 | "vcmp.<mve_cmp_type>%#<V_sz_elem>\t<mve_cmp_op>, %q1, %q2" |
d083fbf7 CL |
679 | [(set_attr "type" "mve_move") |
680 | ]) | |
681 | ||
682 | ;; | |
683 | ;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_]) | |
684 | ;; | |
6a08718a | 685 | (define_insn "@mve_vcmp<mve_cmp_op>q_n_<mode>" |
d083fbf7 | 686 | [ |
e6a4aefc | 687 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
ed34c3bc AV |
688 | (MVE_COMPARISONS:<MVE_VPRED> |
689 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
690 | (vec_duplicate:MVE_2 (match_operand:<V_elem> 2 "s_register_operand" "r")))) | |
d71dba7b SP |
691 | ] |
692 | "TARGET_HAVE_MVE" | |
d083fbf7 | 693 | "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2" |
d71dba7b SP |
694 | [(set_attr "type" "mve_move") |
695 | ]) | |
696 | ||
697 | ;; | |
698 | ;; [vshlq_s, vshlq_u]) | |
7432f255 | 699 | ;; See vec-common.md |
33203b4c SP |
700 | |
701 | ;; | |
3fe5a244 CL |
702 | ;; [vabdq_s, vabdq_u] |
703 | ;; [vhaddq_s, vhaddq_u] | |
704 | ;; [vhsubq_s, vhsubq_u] | |
705 | ;; [vmulhq_s, vmulhq_u] | |
706 | ;; [vqaddq_u, vqaddq_s] | |
707 | ;; [vqdmulhq_s] | |
708 | ;; [vqrdmulhq_s] | |
709 | ;; [vqrshlq_s, vqrshlq_u] | |
710 | ;; [vqshlq_s, vqshlq_u] | |
711 | ;; [vqsubq_u, vqsubq_s] | |
712 | ;; [vrhaddq_s, vrhaddq_u] | |
713 | ;; [vrmulhq_s, vrmulhq_u] | |
714 | ;; [vrshlq_s, vrshlq_u] | |
33203b4c | 715 | ;; |
3fe5a244 | 716 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
33203b4c SP |
717 | [ |
718 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
719 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
720 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
3fe5a244 | 721 | MVE_INT_SU_BINARY)) |
33203b4c SP |
722 | ] |
723 | "TARGET_HAVE_MVE" | |
3fe5a244 | 724 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" |
33203b4c SP |
725 | [(set_attr "type" "mve_move") |
726 | ]) | |
727 | ||
728 | ;; | |
b0b3a5e9 CL |
729 | ;; [vaddq_n_s, vaddq_n_u] |
730 | ;; [vsubq_n_s, vsubq_n_u] | |
731 | ;; [vmulq_n_s, vmulq_n_u] | |
33203b4c | 732 | ;; |
b0b3a5e9 | 733 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
33203b4c SP |
734 | [ |
735 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
736 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
737 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
b0b3a5e9 | 738 | MVE_INT_N_BINARY)) |
33203b4c SP |
739 | ] |
740 | "TARGET_HAVE_MVE" | |
b0b3a5e9 | 741 | "<mve_insn>.i%#<V_sz_elem>\t%q0, %q1, %2" |
33203b4c SP |
742 | [(set_attr "type" "mve_move") |
743 | ]) | |
744 | ||
745 | ;; | |
746 | ;; [vaddvaq_s, vaddvaq_u]) | |
747 | ;; | |
782eb6bb | 748 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
33203b4c | 749 | [ |
3d537943 | 750 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
751 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
752 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
753 | VADDVAQ)) | |
754 | ] | |
755 | "TARGET_HAVE_MVE" | |
782eb6bb | 756 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2" |
33203b4c SP |
757 | [(set_attr "type" "mve_move") |
758 | ]) | |
759 | ||
760 | ;; | |
761 | ;; [vaddvq_p_u, vaddvq_p_s]) | |
762 | ;; | |
eb1ded46 | 763 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
33203b4c | 764 | [ |
3d537943 | 765 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c | 766 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
724d6566 | 767 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] |
33203b4c SP |
768 | VADDVQ_P)) |
769 | ] | |
770 | "TARGET_HAVE_MVE" | |
eb1ded46 | 771 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1" |
33203b4c SP |
772 | [(set_attr "type" "mve_move") |
773 | (set_attr "length""8")]) | |
774 | ||
775 | ;; | |
776 | ;; [vandq_u, vandq_s]) | |
777 | ;; | |
11a0beff CL |
778 | ;; signed and unsigned versions are the same: define the unsigned |
779 | ;; insn, and use an expander for the signed one as we still reference | |
780 | ;; both names from arm_mve.h. | |
781 | ;; We use the same code as in neon.md (TODO: avoid this duplication). | |
782 | (define_insn "mve_vandq_u<mode>" | |
33203b4c | 783 | [ |
11a0beff CL |
784 | (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") |
785 | (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") | |
786 | (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL"))) | |
33203b4c SP |
787 | ] |
788 | "TARGET_HAVE_MVE" | |
11a0beff CL |
789 | "@ |
790 | vand\t%q0, %q1, %q2 | |
791 | * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));" | |
33203b4c SP |
792 | [(set_attr "type" "mve_move") |
793 | ]) | |
11a0beff CL |
794 | (define_expand "mve_vandq_s<mode>" |
795 | [ | |
796 | (set (match_operand:MVE_2 0 "s_register_operand") | |
797 | (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand") | |
798 | (match_operand:MVE_2 2 "neon_inv_logic_op2"))) | |
799 | ] | |
800 | "TARGET_HAVE_MVE" | |
801 | ) | |
33203b4c SP |
802 | |
803 | ;; | |
804 | ;; [vbicq_s, vbicq_u]) | |
805 | ;; | |
5391cf07 | 806 | (define_insn "mve_vbicq_u<mode>" |
33203b4c SP |
807 | [ |
808 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5391cf07 CL |
809 | (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) |
810 | (match_operand:MVE_2 1 "s_register_operand" "w"))) | |
33203b4c SP |
811 | ] |
812 | "TARGET_HAVE_MVE" | |
5391cf07 | 813 | "vbic\t%q0, %q1, %q2" |
33203b4c SP |
814 | [(set_attr "type" "mve_move") |
815 | ]) | |
816 | ||
5391cf07 CL |
817 | (define_expand "mve_vbicq_s<mode>" |
818 | [ | |
819 | (set (match_operand:MVE_2 0 "s_register_operand") | |
820 | (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) | |
821 | (match_operand:MVE_2 1 "s_register_operand"))) | |
822 | ] | |
823 | "TARGET_HAVE_MVE" | |
824 | ) | |
825 | ||
33203b4c SP |
826 | ;; |
827 | ;; [vbrsrq_n_u, vbrsrq_n_s]) | |
828 | ;; | |
829 | (define_insn "mve_vbrsrq_n_<supf><mode>" | |
830 | [ | |
831 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
832 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
833 | (match_operand:SI 2 "s_register_operand" "r")] | |
834 | VBRSRQ_N)) | |
835 | ] | |
836 | "TARGET_HAVE_MVE" | |
837 | "vbrsr.%#<V_sz_elem> %q0, %q1, %2" | |
838 | [(set_attr "type" "mve_move") | |
839 | ]) | |
840 | ||
841 | ;; | |
9732dc85 | 842 | ;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) |
33203b4c | 843 | ;; |
9732dc85 | 844 | (define_insn "mve_vcaddq<mve_rot><mode>" |
33203b4c | 845 | [ |
6debbff6 | 846 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
847 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
848 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
9732dc85 | 849 | VCADD)) |
33203b4c SP |
850 | ] |
851 | "TARGET_HAVE_MVE" | |
9732dc85 | 852 | "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>" |
33203b4c SP |
853 | [(set_attr "type" "mve_move") |
854 | ]) | |
855 | ||
9732dc85 TC |
856 | ;; Auto vectorizer pattern for int vcadd |
857 | (define_expand "cadd<rot><mode>3" | |
858 | [(set (match_operand:MVE_2 0 "register_operand") | |
859 | (unspec:MVE_2 [(match_operand:MVE_2 1 "register_operand") | |
860 | (match_operand:MVE_2 2 "register_operand")] | |
861 | VCADD))] | |
862 | "TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN" | |
863 | ) | |
33203b4c | 864 | |
33203b4c SP |
865 | ;; |
866 | ;; [veorq_u, veorq_s]) | |
867 | ;; | |
434fb3b6 | 868 | (define_insn "mve_veorq_u<mode>" |
33203b4c SP |
869 | [ |
870 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
434fb3b6 CL |
871 | (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") |
872 | (match_operand:MVE_2 2 "s_register_operand" "w"))) | |
33203b4c SP |
873 | ] |
874 | "TARGET_HAVE_MVE" | |
434fb3b6 | 875 | "veor\t%q0, %q1, %q2" |
33203b4c SP |
876 | [(set_attr "type" "mve_move") |
877 | ]) | |
434fb3b6 CL |
878 | (define_expand "mve_veorq_s<mode>" |
879 | [ | |
880 | (set (match_operand:MVE_2 0 "s_register_operand") | |
881 | (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") | |
882 | (match_operand:MVE_2 2 "s_register_operand"))) | |
883 | ] | |
884 | "TARGET_HAVE_MVE" | |
885 | ) | |
33203b4c SP |
886 | |
887 | ;; | |
111f474f CL |
888 | ;; [vhaddq_n_u, vhaddq_n_s] |
889 | ;; [vhsubq_n_u, vhsubq_n_s] | |
890 | ;; [vqaddq_n_s, vqaddq_n_u] | |
891 | ;; [vqdmulhq_n_s] | |
892 | ;; [vqrdmulhq_n_s] | |
893 | ;; [vqsubq_n_s, vqsubq_n_u] | |
33203b4c | 894 | ;; |
111f474f | 895 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
33203b4c SP |
896 | [ |
897 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
898 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
899 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
111f474f | 900 | MVE_INT_SU_N_BINARY)) |
33203b4c SP |
901 | ] |
902 | "TARGET_HAVE_MVE" | |
111f474f | 903 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2" |
33203b4c SP |
904 | [(set_attr "type" "mve_move") |
905 | ]) | |
906 | ||
33203b4c SP |
907 | ;; |
908 | ;; [vhcaddq_rot270_s]) | |
909 | ;; | |
910 | (define_insn "mve_vhcaddq_rot270_s<mode>" | |
911 | [ | |
6debbff6 | 912 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
913 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
914 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
915 | VHCADDQ_ROT270_S)) | |
916 | ] | |
917 | "TARGET_HAVE_MVE" | |
918 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270" | |
919 | [(set_attr "type" "mve_move") | |
920 | ]) | |
921 | ||
922 | ;; | |
923 | ;; [vhcaddq_rot90_s]) | |
924 | ;; | |
925 | (define_insn "mve_vhcaddq_rot90_s<mode>" | |
926 | [ | |
6debbff6 | 927 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
928 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") |
929 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
930 | VHCADDQ_ROT90_S)) | |
931 | ] | |
932 | "TARGET_HAVE_MVE" | |
933 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90" | |
934 | [(set_attr "type" "mve_move") | |
935 | ]) | |
936 | ||
33203b4c | 937 | ;; |
dcc05862 CL |
938 | ;; [vmaxaq_s] |
939 | ;; [vminaq_s] | |
33203b4c | 940 | ;; |
dcc05862 | 941 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
33203b4c SP |
942 | [ |
943 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
944 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
945 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
dcc05862 | 946 | MVE_VMAXAVMINAQ)) |
33203b4c SP |
947 | ] |
948 | "TARGET_HAVE_MVE" | |
dcc05862 | 949 | "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2" |
33203b4c SP |
950 | [(set_attr "type" "mve_move") |
951 | ]) | |
952 | ||
33203b4c | 953 | ;; |
bcf66a4d CL |
954 | ;; [vmaxq_u, vmaxq_s] |
955 | ;; [vminq_s, vminq_u] | |
33203b4c | 956 | ;; |
bcf66a4d | 957 | (define_insn "mve_<max_min_su_str>q_<max_min_supf><mode>" |
33203b4c SP |
958 | [ |
959 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
bcf66a4d | 960 | (MAX_MIN_SU:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") |
76835dca | 961 | (match_operand:MVE_2 2 "s_register_operand" "w"))) |
33203b4c SP |
962 | ] |
963 | "TARGET_HAVE_MVE" | |
bcf66a4d | 964 | "<max_min_su_str>.<max_min_supf>%#<V_sz_elem>\t%q0, %q1, %q2" |
76835dca DZ |
965 | [(set_attr "type" "mve_move") |
966 | ]) | |
967 | ||
33203b4c SP |
968 | |
969 | ;; | |
16c5aca6 CL |
970 | ;; [vmaxavq_s] |
971 | ;; [vmaxvq_u, vmaxvq_s] | |
972 | ;; [vminavq_s] | |
973 | ;; [vminvq_u, vminvq_s] | |
33203b4c | 974 | ;; |
16c5aca6 | 975 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
33203b4c SP |
976 | [ |
977 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
978 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
979 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
16c5aca6 | 980 | MVE_VMAXVQ_VMINVQ)) |
33203b4c SP |
981 | ] |
982 | "TARGET_HAVE_MVE" | |
16c5aca6 | 983 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2" |
33203b4c SP |
984 | [(set_attr "type" "mve_move") |
985 | ]) | |
986 | ||
33203b4c | 987 | ;; |
1817749d CL |
988 | ;; [vmladavq_u, vmladavq_s] |
989 | ;; [vmladavxq_s] | |
990 | ;; [vmlsdavq_s] | |
991 | ;; [vmlsdavxq_s] | |
33203b4c | 992 | ;; |
1817749d | 993 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
33203b4c | 994 | [ |
3d537943 | 995 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
33203b4c SP |
996 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
997 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1817749d | 998 | MVE_VMLxDAVQ)) |
33203b4c SP |
999 | ] |
1000 | "TARGET_HAVE_MVE" | |
1817749d | 1001 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1, %q2" |
33203b4c SP |
1002 | [(set_attr "type" "mve_move") |
1003 | ]) | |
1004 | ||
33203b4c SP |
1005 | ;; |
1006 | ;; [vmullbq_int_u, vmullbq_int_s]) | |
1007 | ;; | |
1008 | (define_insn "mve_vmullbq_int_<supf><mode>" | |
1009 | [ | |
6debbff6 | 1010 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1011 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") |
1012 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1013 | VMULLBQ_INT)) | |
1014 | ] | |
1015 | "TARGET_HAVE_MVE" | |
1016 | "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1017 | [(set_attr "type" "mve_move") | |
1018 | ]) | |
1019 | ||
1020 | ;; | |
1021 | ;; [vmulltq_int_u, vmulltq_int_s]) | |
1022 | ;; | |
1023 | (define_insn "mve_vmulltq_int_<supf><mode>" | |
1024 | [ | |
6debbff6 | 1025 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
33203b4c SP |
1026 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") |
1027 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1028 | VMULLTQ_INT)) | |
1029 | ] | |
1030 | "TARGET_HAVE_MVE" | |
1031 | "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1032 | [(set_attr "type" "mve_move") | |
1033 | ]) | |
1034 | ||
1035 | ;; | |
b0b3a5e9 CL |
1036 | ;; [vaddq_s, vaddq_u] |
1037 | ;; [vmulq_u, vmulq_s] | |
1038 | ;; [vsubq_s, vsubq_u] | |
33203b4c | 1039 | ;; |
b0b3a5e9 | 1040 | (define_insn "mve_<mve_addsubmul>q<mode>" |
0f41b5e0 DZ |
1041 | [ |
1042 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
b0b3a5e9 CL |
1043 | (MVE_INT_BINARY_RTX:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") |
1044 | (match_operand:MVE_2 2 "s_register_operand" "w"))) | |
0f41b5e0 DZ |
1045 | ] |
1046 | "TARGET_HAVE_MVE" | |
b0b3a5e9 | 1047 | "<mve_addsubmul>.i%#<V_sz_elem>\t%q0, %q1, %q2" |
0f41b5e0 DZ |
1048 | [(set_attr "type" "mve_move") |
1049 | ]) | |
1050 | ||
33203b4c SP |
1051 | ;; |
1052 | ;; [vornq_u, vornq_s]) | |
1053 | ;; | |
250fd9fb | 1054 | (define_insn "mve_vornq_s<mode>" |
33203b4c SP |
1055 | [ |
1056 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
250fd9fb CL |
1057 | (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) |
1058 | (match_operand:MVE_2 1 "s_register_operand" "w"))) | |
33203b4c SP |
1059 | ] |
1060 | "TARGET_HAVE_MVE" | |
250fd9fb | 1061 | "vorn\t%q0, %q1, %q2" |
33203b4c SP |
1062 | [(set_attr "type" "mve_move") |
1063 | ]) | |
1064 | ||
250fd9fb CL |
1065 | (define_expand "mve_vornq_u<mode>" |
1066 | [ | |
1067 | (set (match_operand:MVE_2 0 "s_register_operand") | |
1068 | (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) | |
1069 | (match_operand:MVE_2 1 "s_register_operand"))) | |
1070 | ] | |
1071 | "TARGET_HAVE_MVE" | |
1072 | ) | |
1073 | ||
33203b4c SP |
1074 | ;; |
1075 | ;; [vorrq_s, vorrq_u]) | |
1076 | ;; | |
75de6a28 CL |
1077 | ;; signed and unsigned versions are the same: define the unsigned |
1078 | ;; insn, and use an expander for the signed one as we still reference | |
1079 | ;; both names from arm_mve.h. | |
1080 | ;; We use the same code as in neon.md (TODO: avoid this duplication). | |
1081 | (define_insn "mve_vorrq_s<mode>" | |
33203b4c | 1082 | [ |
75de6a28 CL |
1083 | (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") |
1084 | (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") | |
1085 | (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl"))) | |
33203b4c SP |
1086 | ] |
1087 | "TARGET_HAVE_MVE" | |
75de6a28 CL |
1088 | "@ |
1089 | vorr\t%q0, %q1, %q2 | |
1090 | * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));" | |
33203b4c SP |
1091 | [(set_attr "type" "mve_move") |
1092 | ]) | |
75de6a28 CL |
1093 | (define_expand "mve_vorrq_u<mode>" |
1094 | [ | |
1095 | (set (match_operand:MVE_2 0 "s_register_operand") | |
1096 | (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand") | |
1097 | (match_operand:MVE_2 2 "neon_logic_op2"))) | |
1098 | ] | |
1099 | "TARGET_HAVE_MVE" | |
1100 | ) | |
33203b4c | 1101 | |
33203b4c | 1102 | ;; |
c4d4e62b CL |
1103 | ;; [vqrshlq_n_s, vqrshlq_n_u] |
1104 | ;; [vrshlq_n_u, vrshlq_n_s] | |
33203b4c | 1105 | ;; |
c4d4e62b | 1106 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
33203b4c SP |
1107 | [ |
1108 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1109 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1110 | (match_operand:SI 2 "s_register_operand" "r")] | |
c4d4e62b | 1111 | MVE_RSHIFT_N)) |
33203b4c SP |
1112 | ] |
1113 | "TARGET_HAVE_MVE" | |
c4d4e62b | 1114 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2" |
33203b4c SP |
1115 | [(set_attr "type" "mve_move") |
1116 | ]) | |
1117 | ||
33203b4c | 1118 | ;; |
7e6c39a3 CL |
1119 | ;; [vqshlq_n_s, vqshlq_n_u] |
1120 | ;; [vshlq_n_u, vshlq_n_s] | |
33203b4c | 1121 | ;; |
7e6c39a3 | 1122 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
33203b4c SP |
1123 | [ |
1124 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1125 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1126 | (match_operand:SI 2 "immediate_operand" "i")] | |
7e6c39a3 | 1127 | MVE_SHIFT_N)) |
33203b4c SP |
1128 | ] |
1129 | "TARGET_HAVE_MVE" | |
7e6c39a3 | 1130 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2" |
33203b4c SP |
1131 | [(set_attr "type" "mve_move") |
1132 | ]) | |
1133 | ||
1134 | ;; | |
7e6c39a3 CL |
1135 | ;; [vqshlq_r_u, vqshlq_r_s] |
1136 | ;; [vshlq_r_s, vshlq_r_u] | |
33203b4c | 1137 | ;; |
7e6c39a3 | 1138 | (define_insn "@mve_<mve_insn>q_r_<supf><mode>" |
33203b4c SP |
1139 | [ |
1140 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1141 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1142 | (match_operand:SI 2 "s_register_operand" "r")] | |
7e6c39a3 | 1143 | MVE_SHIFT_R)) |
33203b4c SP |
1144 | ] |
1145 | "TARGET_HAVE_MVE" | |
7e6c39a3 | 1146 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2" |
33203b4c SP |
1147 | [(set_attr "type" "mve_move") |
1148 | ]) | |
1149 | ||
33203b4c SP |
1150 | ;; |
1151 | ;; [vqshluq_n_s]) | |
1152 | ;; | |
1153 | (define_insn "mve_vqshluq_n_s<mode>" | |
1154 | [ | |
1155 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1156 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
c3fb6658 | 1157 | (match_operand:SI 2 "<MVE_pred>" "<MVE_constraint>")] |
33203b4c SP |
1158 | VQSHLUQ_N_S)) |
1159 | ] | |
1160 | "TARGET_HAVE_MVE" | |
1161 | "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1162 | [(set_attr "type" "mve_move") | |
1163 | ]) | |
1164 | ||
f9355dee | 1165 | ;; |
1736f4af | 1166 | ;; [vabdq_f] |
f9355dee | 1167 | ;; |
1736f4af | 1168 | (define_insn "@mve_<mve_insn>q_f<mode>" |
f9355dee SP |
1169 | [ |
1170 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1171 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1172 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
1736f4af | 1173 | MVE_FP_VABDQ_ONLY)) |
f9355dee SP |
1174 | ] |
1175 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1736f4af | 1176 | "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2" |
f9355dee SP |
1177 | [(set_attr "type" "mve_move") |
1178 | ]) | |
1179 | ||
1180 | ;; | |
1181 | ;; [vaddlvaq_s vaddlvaq_u]) | |
1182 | ;; | |
42c94cce | 1183 | (define_insn "@mve_<mve_insn>q_<supf>v4si" |
f9355dee SP |
1184 | [ |
1185 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
1186 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
1187 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
1188 | VADDLVAQ)) | |
1189 | ] | |
1190 | "TARGET_HAVE_MVE" | |
42c94cce | 1191 | "<mve_insn>.<supf>32\t%Q0, %R0, %q2" |
f9355dee SP |
1192 | [(set_attr "type" "mve_move") |
1193 | ]) | |
1194 | ||
1195 | ;; | |
b0b3a5e9 CL |
1196 | ;; [vaddq_n_f] |
1197 | ;; [vsubq_n_f] | |
1198 | ;; [vmulq_n_f] | |
f9355dee | 1199 | ;; |
b0b3a5e9 | 1200 | (define_insn "@mve_<mve_insn>q_n_f<mode>" |
f9355dee SP |
1201 | [ |
1202 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1203 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1204 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
b0b3a5e9 | 1205 | MVE_FP_N_BINARY)) |
f9355dee SP |
1206 | ] |
1207 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
b0b3a5e9 | 1208 | "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %2" |
f9355dee SP |
1209 | [(set_attr "type" "mve_move") |
1210 | ]) | |
1211 | ||
1212 | ;; | |
1213 | ;; [vandq_f]) | |
1214 | ;; | |
1215 | (define_insn "mve_vandq_f<mode>" | |
1216 | [ | |
1217 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
11a0beff CL |
1218 | (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
1219 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
1220 | ] |
1221 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1222 | "vand %q0, %q1, %q2" | |
1223 | [(set_attr "type" "mve_move") | |
1224 | ]) | |
1225 | ||
1226 | ;; | |
1227 | ;; [vbicq_f]) | |
1228 | ;; | |
1229 | (define_insn "mve_vbicq_f<mode>" | |
1230 | [ | |
1231 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5391cf07 CL |
1232 | (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")) |
1233 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
1234 | ] |
1235 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1236 | "vbic %q0, %q1, %q2" | |
1237 | [(set_attr "type" "mve_move") | |
1238 | ]) | |
1239 | ||
f9355dee | 1240 | ;; |
9732dc85 | 1241 | ;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) |
3cc4e183 | 1242 | ;; |
9732dc85 | 1243 | (define_insn "mve_vcaddq<mve_rot><mode>" |
3cc4e183 TC |
1244 | [ |
1245 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") | |
1246 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1247 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
9732dc85 | 1248 | VCADD)) |
3cc4e183 TC |
1249 | ] |
1250 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
9732dc85 | 1251 | "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" |
f9355dee SP |
1252 | [(set_attr "type" "mve_move") |
1253 | ]) | |
1254 | ||
1255 | ;; | |
902692c1 | 1256 | ;; [vcmpeqq_f, vcmpgeq_f, vcmpgtq_f, vcmpleq_f, vcmpltq_f, vcmpneq_f]) |
f9355dee | 1257 | ;; |
a6eacbf1 | 1258 | (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" |
f9355dee | 1259 | [ |
91224cf6 CL |
1260 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
1261 | (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") | |
902692c1 | 1262 | (match_operand:MVE_0 2 "s_register_operand" "w"))) |
f9355dee SP |
1263 | ] |
1264 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
902692c1 | 1265 | "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %q2" |
f9355dee SP |
1266 | [(set_attr "type" "mve_move") |
1267 | ]) | |
1268 | ||
1269 | ;; | |
902692c1 | 1270 | ;; [vcmpeqq_n_f, vcmpgeq_n_f, vcmpgtq_n_f, vcmpleq_n_f, vcmpltq_n_f, vcmpneq_n_f]) |
f9355dee | 1271 | ;; |
a6eacbf1 | 1272 | (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" |
f9355dee | 1273 | [ |
e6a4aefc | 1274 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
ed34c3bc AV |
1275 | (MVE_FP_COMPARISONS:<MVE_VPRED> |
1276 | (match_operand:MVE_0 1 "s_register_operand" "w") | |
1277 | (vec_duplicate:MVE_0 (match_operand:<V_elem> 2 "s_register_operand" "r")))) | |
f9355dee SP |
1278 | ] |
1279 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
902692c1 | 1280 | "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %2" |
f9355dee SP |
1281 | [(set_attr "type" "mve_move") |
1282 | ]) | |
1283 | ||
1284 | ;; | |
db253e8b | 1285 | ;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270]) |
3cc4e183 | 1286 | ;; |
db253e8b | 1287 | (define_insn "mve_vcmulq<mve_rot><mode>" |
3cc4e183 TC |
1288 | [ |
1289 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") | |
1290 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
1291 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
db253e8b | 1292 | VCMUL)) |
3cc4e183 TC |
1293 | ] |
1294 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db253e8b | 1295 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" |
f9355dee SP |
1296 | [(set_attr "type" "mve_move") |
1297 | ]) | |
1298 | ||
1299 | ;; | |
1300 | ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) | |
1301 | ;; | |
e0bc13d3 | 1302 | (define_insn "mve_vctp<MVE_vctp>q_m<MVE_vpred>" |
f9355dee | 1303 | [ |
e0bc13d3 AV |
1304 | (set (match_operand:MVE_7 0 "vpr_register_operand" "=Up") |
1305 | (unspec:MVE_7 [(match_operand:SI 1 "s_register_operand" "r") | |
1306 | (match_operand:MVE_7 2 "vpr_register_operand" "Up")] | |
1307 | VCTP_M)) | |
f9355dee SP |
1308 | ] |
1309 | "TARGET_HAVE_MVE" | |
e0bc13d3 | 1310 | "vpst\;vctpt.<MVE_vctp> %1" |
f9355dee SP |
1311 | [(set_attr "type" "mve_move") |
1312 | (set_attr "length""8")]) | |
1313 | ||
1314 | ;; | |
1315 | ;; [vcvtbq_f16_f32]) | |
1316 | ;; | |
1317 | (define_insn "mve_vcvtbq_f16_f32v8hf" | |
1318 | [ | |
1319 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
1320 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
1321 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
1322 | VCVTBQ_F16_F32)) | |
1323 | ] | |
1324 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1325 | "vcvtb.f16.f32 %q0, %q2" | |
1326 | [(set_attr "type" "mve_move") | |
1327 | ]) | |
1328 | ||
1329 | ;; | |
1330 | ;; [vcvttq_f16_f32]) | |
1331 | ;; | |
1332 | (define_insn "mve_vcvttq_f16_f32v8hf" | |
1333 | [ | |
1334 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
1335 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
1336 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
1337 | VCVTTQ_F16_F32)) | |
1338 | ] | |
1339 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1340 | "vcvtt.f16.f32 %q0, %q2" | |
1341 | [(set_attr "type" "mve_move") | |
1342 | ]) | |
1343 | ||
1344 | ;; | |
1345 | ;; [veorq_f]) | |
1346 | ;; | |
1347 | (define_insn "mve_veorq_f<mode>" | |
1348 | [ | |
1349 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
434fb3b6 CL |
1350 | (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
1351 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
1352 | ] |
1353 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1354 | "veor %q0, %q1, %q2" | |
1355 | [(set_attr "type" "mve_move") | |
1356 | ]) | |
1357 | ||
1358 | ;; | |
26d6e02c CL |
1359 | ;; [vmaxnmaq_f] |
1360 | ;; [vminnmaq_f] | |
f9355dee | 1361 | ;; |
26d6e02c | 1362 | (define_insn "@mve_<mve_insn>q_f<mode>" |
f9355dee SP |
1363 | [ |
1364 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1365 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
1366 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
26d6e02c | 1367 | MVE_VMAXNMA_VMINNMAQ)) |
f9355dee SP |
1368 | ] |
1369 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
26d6e02c | 1370 | "<mve_insn>.f%#<V_sz_elem>\t%q0, %q2" |
f9355dee SP |
1371 | [(set_attr "type" "mve_move") |
1372 | ]) | |
1373 | ||
1374 | ;; | |
d814dc9d CL |
1375 | ;; [vmaxnmavq_f] |
1376 | ;; [vmaxnmvq_f] | |
1377 | ;; [vminnmavq_f] | |
1378 | ;; [vminnmvq_f] | |
f9355dee | 1379 | ;; |
d814dc9d | 1380 | (define_insn "@mve_<mve_insn>q_f<mode>" |
f9355dee SP |
1381 | [ |
1382 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1383 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1384 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
d814dc9d | 1385 | MVE_VMAXNMxV_MINNMxVQ)) |
f9355dee SP |
1386 | ] |
1387 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
d814dc9d | 1388 | "<mve_insn>.f%#<V_sz_elem>\t%0, %q2" |
f9355dee SP |
1389 | [(set_attr "type" "mve_move") |
1390 | ]) | |
1391 | ||
1392 | ;; | |
5ea7a47c CL |
1393 | ;; [vmaxnmq_f] |
1394 | ;; [vminnmq_f] | |
f9355dee | 1395 | ;; |
5ea7a47c | 1396 | (define_insn "@mve_<max_min_f_str>q_f<mode>" |
f9355dee SP |
1397 | [ |
1398 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
5ea7a47c CL |
1399 | (MAX_MIN_F:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
1400 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
1401 | ] |
1402 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5ea7a47c | 1403 | "<max_min_f_str>.f%#<V_sz_elem> %q0, %q1, %q2" |
f9355dee SP |
1404 | [(set_attr "type" "mve_move") |
1405 | ]) | |
1406 | ||
f9355dee | 1407 | ;; |
c1e068e4 CL |
1408 | ;; [vmlaldavq_u, vmlaldavq_s] |
1409 | ;; [vmlaldavxq_s] | |
1410 | ;; [vmlsldavq_s] | |
1411 | ;; [vmlsldavxq_s] | |
f9355dee | 1412 | ;; |
c1e068e4 | 1413 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
f9355dee SP |
1414 | [ |
1415 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
1416 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
1417 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
c1e068e4 | 1418 | MVE_VMLxLDAVxQ)) |
f9355dee SP |
1419 | ] |
1420 | "TARGET_HAVE_MVE" | |
c1e068e4 | 1421 | "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" |
f9355dee SP |
1422 | [(set_attr "type" "mve_move") |
1423 | ]) | |
1424 | ||
1425 | ;; | |
7f49b4a0 CL |
1426 | ;; [vmovnbq_u, vmovnbq_s] |
1427 | ;; [vmovntq_s, vmovntq_u] | |
1428 | ;; [vqmovnbq_u, vqmovnbq_s] | |
1429 | ;; [vqmovntq_u, vqmovntq_s] | |
1430 | ;; [vqmovunbq_s] | |
1431 | ;; [vqmovuntq_s] | |
f9355dee | 1432 | ;; |
7f49b4a0 | 1433 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
f9355dee SP |
1434 | [ |
1435 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
1436 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
1437 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
7f49b4a0 | 1438 | MVE_MOVN)) |
f9355dee SP |
1439 | ] |
1440 | "TARGET_HAVE_MVE" | |
7f49b4a0 | 1441 | "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q2" |
f9355dee SP |
1442 | [(set_attr "type" "mve_move") |
1443 | ]) | |
1444 | ||
1445 | ;; | |
b0b3a5e9 CL |
1446 | ;; [vaddq_f] |
1447 | ;; [vmulq_f] | |
1448 | ;; [vsubq_f] | |
f9355dee | 1449 | ;; |
b0b3a5e9 | 1450 | (define_insn "mve_<mve_addsubmul>q_f<mode>" |
f9355dee SP |
1451 | [ |
1452 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
b0b3a5e9 | 1453 | (MVE_INT_BINARY_RTX:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
0f41b5e0 | 1454 | (match_operand:MVE_0 2 "s_register_operand" "w"))) |
f9355dee SP |
1455 | ] |
1456 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
b0b3a5e9 | 1457 | "<mve_addsubmul>.f%#<V_sz_elem>\t%q0, %q1, %q2" |
f9355dee SP |
1458 | [(set_attr "type" "mve_move") |
1459 | ]) | |
1460 | ||
1461 | ;; | |
1462 | ;; [vornq_f]) | |
1463 | ;; | |
1464 | (define_insn "mve_vornq_f<mode>" | |
1465 | [ | |
1466 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
250fd9fb CL |
1467 | (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2 "s_register_operand" "w")) |
1468 | (match_operand:MVE_0 1 "s_register_operand" "w"))) | |
f9355dee SP |
1469 | ] |
1470 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1471 | "vorn %q0, %q1, %q2" | |
1472 | [(set_attr "type" "mve_move") | |
1473 | ]) | |
1474 | ||
1475 | ;; | |
1476 | ;; [vorrq_f]) | |
1477 | ;; | |
1478 | (define_insn "mve_vorrq_f<mode>" | |
1479 | [ | |
1480 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
75de6a28 CL |
1481 | (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") |
1482 | (match_operand:MVE_0 2 "s_register_operand" "w"))) | |
f9355dee SP |
1483 | ] |
1484 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1485 | "vorr %q0, %q1, %q2" | |
1486 | [(set_attr "type" "mve_move") | |
1487 | ]) | |
1488 | ||
1489 | ;; | |
67e4e591 CL |
1490 | ;; [vbicq_n_s, vbicq_n_u] |
1491 | ;; [vorrq_n_u, vorrq_n_s] | |
f9355dee | 1492 | ;; |
67e4e591 | 1493 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
f9355dee SP |
1494 | [ |
1495 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
1496 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
1497 | (match_operand:SI 2 "immediate_operand" "i")] | |
67e4e591 | 1498 | MVE_INT_N_BINARY_LOGIC)) |
f9355dee SP |
1499 | ] |
1500 | "TARGET_HAVE_MVE" | |
67e4e591 | 1501 | "<mve_insn>.i%#<V_sz_elem> %q0, %2" |
f9355dee SP |
1502 | [(set_attr "type" "mve_move") |
1503 | ]) | |
1504 | ||
1505 | ;; | |
1506 | ;; [vqdmullbq_n_s]) | |
1507 | ;; | |
1508 | (define_insn "mve_vqdmullbq_n_s<mode>" | |
1509 | [ | |
6debbff6 | 1510 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
1511 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
1512 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1513 | VQDMULLBQ_N_S)) | |
1514 | ] | |
1515 | "TARGET_HAVE_MVE" | |
1516 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2" | |
1517 | [(set_attr "type" "mve_move") | |
1518 | ]) | |
1519 | ||
1520 | ;; | |
1521 | ;; [vqdmullbq_s]) | |
1522 | ;; | |
1523 | (define_insn "mve_vqdmullbq_s<mode>" | |
1524 | [ | |
6debbff6 | 1525 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
1526 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
1527 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
1528 | VQDMULLBQ_S)) | |
1529 | ] | |
1530 | "TARGET_HAVE_MVE" | |
1531 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2" | |
1532 | [(set_attr "type" "mve_move") | |
1533 | ]) | |
1534 | ||
1535 | ;; | |
1536 | ;; [vqdmulltq_n_s]) | |
1537 | ;; | |
1538 | (define_insn "mve_vqdmulltq_n_s<mode>" | |
1539 | [ | |
6debbff6 | 1540 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
1541 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
1542 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1543 | VQDMULLTQ_N_S)) | |
1544 | ] | |
1545 | "TARGET_HAVE_MVE" | |
1546 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2" | |
1547 | [(set_attr "type" "mve_move") | |
1548 | ]) | |
1549 | ||
1550 | ;; | |
1551 | ;; [vqdmulltq_s]) | |
1552 | ;; | |
1553 | (define_insn "mve_vqdmulltq_s<mode>" | |
1554 | [ | |
6debbff6 | 1555 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f9355dee SP |
1556 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") |
1557 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
1558 | VQDMULLTQ_S)) | |
1559 | ] | |
1560 | "TARGET_HAVE_MVE" | |
1561 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2" | |
1562 | [(set_attr "type" "mve_move") | |
1563 | ]) | |
1564 | ||
f9355dee | 1565 | ;; |
e044696f CL |
1566 | ;; [vrmlaldavhq_u vrmlaldavhq_s] |
1567 | ;; [vrmlaldavhxq_s] | |
1568 | ;; [vrmlsldavhq_s] | |
1569 | ;; [vrmlsldavhxq_s] | |
f9355dee | 1570 | ;; |
e044696f | 1571 | (define_insn "@mve_<mve_insn>q_<supf>v4si" |
f9355dee SP |
1572 | [ |
1573 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
1574 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
1575 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
e044696f | 1576 | MVE_VRMLxLDAVxQ)) |
f9355dee SP |
1577 | ] |
1578 | "TARGET_HAVE_MVE" | |
e044696f | 1579 | "<mve_insn>.<supf>32\t%Q0, %R0, %q1, %q2" |
f9355dee SP |
1580 | [(set_attr "type" "mve_move") |
1581 | ]) | |
1582 | ||
1583 | ;; | |
2cc50fd9 CL |
1584 | ;; [vshllbq_n_s, vshllbq_n_u] |
1585 | ;; [vshlltq_n_u, vshlltq_n_s] | |
f9355dee | 1586 | ;; |
2cc50fd9 | 1587 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
f9355dee SP |
1588 | [ |
1589 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
1590 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
1591 | (match_operand:SI 2 "immediate_operand" "i")] | |
2cc50fd9 | 1592 | VSHLLxQ_N)) |
f9355dee SP |
1593 | ] |
1594 | "TARGET_HAVE_MVE" | |
2cc50fd9 | 1595 | "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2" |
f9355dee SP |
1596 | [(set_attr "type" "mve_move") |
1597 | ]) | |
1598 | ||
f9355dee SP |
1599 | ;; |
1600 | ;; [vmulltq_poly_p]) | |
1601 | ;; | |
1602 | (define_insn "mve_vmulltq_poly_p<mode>" | |
1603 | [ | |
1604 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
1605 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
1606 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
1607 | VMULLTQ_POLY_P)) | |
1608 | ] | |
1609 | "TARGET_HAVE_MVE" | |
1610 | "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
1611 | [(set_attr "type" "mve_move") | |
1612 | ]) | |
1613 | ||
1614 | ;; | |
1615 | ;; [vmullbq_poly_p]) | |
1616 | ;; | |
1617 | (define_insn "mve_vmullbq_poly_p<mode>" | |
1618 | [ | |
1619 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
1620 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
1621 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
1622 | VMULLBQ_POLY_P)) | |
1623 | ] | |
1624 | "TARGET_HAVE_MVE" | |
1625 | "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
1626 | [(set_attr "type" "mve_move") | |
1627 | ]) | |
1628 | ||
0dad5b33 | 1629 | ;; |
6a08718a CL |
1630 | ;; [vcmpeqq_m_f] |
1631 | ;; [vcmpgeq_m_f] | |
1632 | ;; [vcmpgtq_m_f] | |
1633 | ;; [vcmpleq_m_f] | |
1634 | ;; [vcmpltq_m_f] | |
1635 | ;; [vcmpneq_m_f] | |
0dad5b33 | 1636 | ;; |
6a08718a | 1637 | (define_insn "@mve_vcmp<mve_cmp_op1>q_m_f<mode>" |
0dad5b33 | 1638 | [ |
e6a4aefc CL |
1639 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
1640 | (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") | |
0dad5b33 | 1641 | (match_operand:MVE_0 2 "s_register_operand" "w") |
e6a4aefc | 1642 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
6a08718a | 1643 | MVE_CMP_M_F)) |
0dad5b33 SP |
1644 | ] |
1645 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6a08718a | 1646 | "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2" |
0dad5b33 SP |
1647 | [(set_attr "type" "mve_move") |
1648 | (set_attr "length""8")]) | |
1649 | ;; | |
1650 | ;; [vcvtaq_m_u, vcvtaq_m_s]) | |
1651 | ;; | |
1652 | (define_insn "mve_vcvtaq_m_<supf><mode>" | |
1653 | [ | |
1654 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
1655 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
1656 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 1657 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
0dad5b33 SP |
1658 | VCVTAQ_M)) |
1659 | ] | |
1660 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1661 | "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" | |
1662 | [(set_attr "type" "mve_move") | |
1663 | (set_attr "length""8")]) | |
1664 | ;; | |
1665 | ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) | |
1666 | ;; | |
1667 | (define_insn "mve_vcvtq_m_to_f_<supf><mode>" | |
1668 | [ | |
1669 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
1670 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
1671 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 1672 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
0dad5b33 SP |
1673 | VCVTQ_M_TO_F)) |
1674 | ] | |
1675 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
1676 | "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2" | |
1677 | [(set_attr "type" "mve_move") | |
1678 | (set_attr "length""8")]) | |
e2f992f7 | 1679 | |
0dad5b33 | 1680 | ;; |
e2f992f7 CL |
1681 | ;; [vqrshrnbq_n_u, vqrshrnbq_n_s] |
1682 | ;; [vqrshrntq_n_u, vqrshrntq_n_s] | |
8f5b7d21 CL |
1683 | ;; [vqrshrunbq_n_s] |
1684 | ;; [vqrshruntq_n_s] | |
e2f992f7 CL |
1685 | ;; [vqshrnbq_n_u, vqshrnbq_n_s] |
1686 | ;; [vqshrntq_n_u, vqshrntq_n_s] | |
8f5b7d21 CL |
1687 | ;; [vqshrunbq_n_s] |
1688 | ;; [vqshruntq_n_s] | |
e2f992f7 CL |
1689 | ;; [vrshrnbq_n_s, vrshrnbq_n_u] |
1690 | ;; [vrshrntq_n_u, vrshrntq_n_s] | |
1691 | ;; [vshrnbq_n_u, vshrnbq_n_s] | |
1692 | ;; [vshrntq_n_s, vshrntq_n_u] | |
0dad5b33 | 1693 | ;; |
e2f992f7 | 1694 | (define_insn "@mve_<mve_insn>q_n_<supf><mode>" |
0dad5b33 SP |
1695 | [ |
1696 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
1697 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
1698 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
c3fb6658 | 1699 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] |
e2f992f7 | 1700 | MVE_SHRN_N)) |
0dad5b33 SP |
1701 | ] |
1702 | "TARGET_HAVE_MVE" | |
e2f992f7 | 1703 | "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q2, %3" |
0dad5b33 SP |
1704 | [(set_attr "type" "mve_move") |
1705 | ]) | |
e2f992f7 | 1706 | |
0dad5b33 SP |
1707 | ;; |
1708 | ;; [vrmlaldavhaq_s vrmlaldavhaq_u]) | |
1709 | ;; | |
1710 | (define_insn "mve_vrmlaldavhaq_<supf>v4si" | |
1711 | [ | |
1712 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
1713 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
1714 | (match_operand:V4SI 2 "s_register_operand" "w") | |
1715 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
1716 | VRMLALDAVHAQ)) | |
1717 | ] | |
1718 | "TARGET_HAVE_MVE" | |
a59b9af3 | 1719 | "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3" |
0dad5b33 SP |
1720 | [(set_attr "type" "mve_move") |
1721 | ]) | |
1722 | ||
1723 | ;; | |
1724 | ;; [vabavq_s, vabavq_u]) | |
1725 | ;; | |
1af6d1db | 1726 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
0dad5b33 SP |
1727 | [ |
1728 | (set (match_operand:SI 0 "s_register_operand" "=r") | |
1729 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
1730 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
1731 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
1732 | VABAVQ)) | |
1733 | ] | |
1734 | "TARGET_HAVE_MVE" | |
1af6d1db | 1735 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2, %q3" |
0dad5b33 SP |
1736 | [(set_attr "type" "mve_move") |
1737 | ]) | |
1738 | ||
1739 | ;; | |
1740 | ;; [vshlcq_u vshlcq_s] | |
1741 | ;; | |
1742 | (define_expand "mve_vshlcq_vec_<supf><mode>" | |
1743 | [(match_operand:MVE_2 0 "s_register_operand") | |
1744 | (match_operand:MVE_2 1 "s_register_operand") | |
1745 | (match_operand:SI 2 "s_register_operand") | |
1746 | (match_operand:SI 3 "mve_imm_32") | |
1747 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
1748 | "TARGET_HAVE_MVE" | |
1749 | { | |
1750 | rtx ignore_wb = gen_reg_rtx (SImode); | |
1751 | emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], | |
8165795c | 1752 | operands[2], operands[3])); |
0dad5b33 SP |
1753 | DONE; |
1754 | }) | |
1755 | ||
1756 | (define_expand "mve_vshlcq_carry_<supf><mode>" | |
1757 | [(match_operand:SI 0 "s_register_operand") | |
1758 | (match_operand:MVE_2 1 "s_register_operand") | |
1759 | (match_operand:SI 2 "s_register_operand") | |
1760 | (match_operand:SI 3 "mve_imm_32") | |
1761 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
1762 | "TARGET_HAVE_MVE" | |
1763 | { | |
1764 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
1765 | emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], | |
1766 | operands[2], operands[3])); | |
1767 | DONE; | |
1768 | }) | |
1769 | ||
1770 | (define_insn "mve_vshlcq_<supf><mode>" | |
1771 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1772 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") | |
1773 | (match_operand:SI 3 "s_register_operand" "1") | |
1774 | (match_operand:SI 4 "mve_imm_32" "Rf")] | |
1775 | VSHLCQ)) | |
1776 | (set (match_operand:SI 1 "s_register_operand" "=r") | |
1777 | (unspec:SI [(match_dup 2) | |
1778 | (match_dup 3) | |
1779 | (match_dup 4)] | |
1780 | VSHLCQ))] | |
1781 | "TARGET_HAVE_MVE" | |
1782 | "vshlc %q0, %1, %4") | |
8165795c SP |
1783 | |
1784 | ;; | |
7734b991 CL |
1785 | ;; [vabsq_m_s] |
1786 | ;; [vclsq_m_s] | |
1787 | ;; [vclzq_m_s, vclzq_m_u] | |
1788 | ;; [vnegq_m_s] | |
1789 | ;; [vqabsq_m_s] | |
1790 | ;; [vqnegq_m_s] | |
8165795c | 1791 | ;; |
7734b991 | 1792 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8165795c SP |
1793 | [ |
1794 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1795 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1796 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1797 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
7734b991 | 1798 | MVE_INT_M_UNARY)) |
8165795c SP |
1799 | ] |
1800 | "TARGET_HAVE_MVE" | |
7734b991 | 1801 | "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2" |
8165795c SP |
1802 | [(set_attr "type" "mve_move") |
1803 | (set_attr "length""8")]) | |
1804 | ||
1805 | ;; | |
1806 | ;; [vaddvaq_p_u, vaddvaq_p_s]) | |
1807 | ;; | |
782eb6bb | 1808 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
8165795c | 1809 | [ |
3d537943 | 1810 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
1811 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
1812 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1813 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
8165795c SP |
1814 | VADDVAQ_P)) |
1815 | ] | |
1816 | "TARGET_HAVE_MVE" | |
782eb6bb | 1817 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2" |
8165795c SP |
1818 | [(set_attr "type" "mve_move") |
1819 | (set_attr "length""8")]) | |
1820 | ||
8165795c SP |
1821 | ;; |
1822 | ;; [vcmpcsq_m_n_u]) | |
8165795c | 1823 | ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s]) |
8165795c | 1824 | ;; [vcmpgeq_m_n_s]) |
8165795c | 1825 | ;; [vcmpgtq_m_n_s]) |
8165795c | 1826 | ;; [vcmphiq_m_n_u]) |
8165795c | 1827 | ;; [vcmpleq_m_n_s]) |
8165795c | 1828 | ;; [vcmpltq_m_n_s]) |
8165795c SP |
1829 | ;; [vcmpneq_m_n_u, vcmpneq_m_n_s]) |
1830 | ;; | |
6a08718a | 1831 | (define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>" |
8165795c | 1832 | [ |
e6a4aefc CL |
1833 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
1834 | (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") | |
8165795c | 1835 | (match_operand:<V_elem> 2 "s_register_operand" "r") |
e6a4aefc | 1836 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
6a08718a | 1837 | MVE_CMP_M_N)) |
8165795c SP |
1838 | ] |
1839 | "TARGET_HAVE_MVE" | |
6a08718a | 1840 | "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2" |
8165795c SP |
1841 | [(set_attr "type" "mve_move") |
1842 | (set_attr "length""8")]) | |
1843 | ||
1844 | ;; | |
6a08718a CL |
1845 | ;; [vcmpcsq_m_u] |
1846 | ;; [vcmpeqq_m_u, vcmpeqq_m_s] | |
1847 | ;; [vcmpgeq_m_s] | |
1848 | ;; [vcmpgtq_m_s] | |
1849 | ;; [vcmphiq_m_u] | |
1850 | ;; [vcmpleq_m_s] | |
1851 | ;; [vcmpltq_m_s] | |
1852 | ;; [vcmpneq_m_s, vcmpneq_m_u] | |
8165795c | 1853 | ;; |
6a08718a | 1854 | (define_insn "@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>" |
8165795c | 1855 | [ |
e6a4aefc CL |
1856 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
1857 | (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") | |
8165795c | 1858 | (match_operand:MVE_2 2 "s_register_operand" "w") |
e6a4aefc | 1859 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
6a08718a | 1860 | MVE_CMP_M)) |
8165795c SP |
1861 | ] |
1862 | "TARGET_HAVE_MVE" | |
6a08718a | 1863 | "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2" |
8165795c SP |
1864 | [(set_attr "type" "mve_move") |
1865 | (set_attr "length""8")]) | |
1866 | ||
1867 | ;; | |
1868 | ;; [vdupq_m_n_s, vdupq_m_n_u]) | |
1869 | ;; | |
fc468102 | 1870 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8165795c SP |
1871 | [ |
1872 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1873 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1874 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
724d6566 | 1875 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
8165795c SP |
1876 | VDUPQ_M_N)) |
1877 | ] | |
1878 | "TARGET_HAVE_MVE" | |
fc468102 | 1879 | "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2" |
8165795c SP |
1880 | [(set_attr "type" "mve_move") |
1881 | (set_attr "length""8")]) | |
1882 | ||
1883 | ;; | |
dcc05862 CL |
1884 | ;; [vmaxaq_m_s] |
1885 | ;; [vminaq_m_s] | |
8165795c | 1886 | ;; |
dcc05862 | 1887 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8165795c SP |
1888 | [ |
1889 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1890 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1891 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1892 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
dcc05862 | 1893 | MVE_VMAXAVMINAQ_M)) |
8165795c SP |
1894 | ] |
1895 | "TARGET_HAVE_MVE" | |
dcc05862 | 1896 | "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2" |
8165795c SP |
1897 | [(set_attr "type" "mve_move") |
1898 | (set_attr "length""8")]) | |
1899 | ||
1900 | ;; | |
16c5aca6 CL |
1901 | ;; [vmaxavq_p_s] |
1902 | ;; [vmaxvq_p_u, vmaxvq_p_s] | |
1903 | ;; [vminavq_p_s] | |
1904 | ;; [vminvq_p_s, vminvq_p_u] | |
8165795c | 1905 | ;; |
16c5aca6 | 1906 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
8165795c SP |
1907 | [ |
1908 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1909 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1910 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1911 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
16c5aca6 | 1912 | MVE_VMAXVQ_VMINVQ_P)) |
8165795c SP |
1913 | ] |
1914 | "TARGET_HAVE_MVE" | |
16c5aca6 | 1915 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2" |
8165795c SP |
1916 | [(set_attr "type" "mve_move") |
1917 | (set_attr "length""8")]) | |
1918 | ||
8165795c | 1919 | ;; |
1817749d CL |
1920 | ;; [vmladavaq_u, vmladavaq_s] |
1921 | ;; [vmladavaxq_s] | |
1922 | ;; [vmlsdavaq_s] | |
1923 | ;; [vmlsdavaxq_s] | |
8165795c | 1924 | ;; |
1817749d | 1925 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
8165795c | 1926 | [ |
3d537943 | 1927 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
1928 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
1929 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
1930 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
1817749d | 1931 | MVE_VMLxDAVAQ)) |
8165795c SP |
1932 | ] |
1933 | "TARGET_HAVE_MVE" | |
1817749d | 1934 | "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2, %q3" |
8165795c SP |
1935 | [(set_attr "type" "mve_move") |
1936 | ]) | |
1937 | ||
1938 | ;; | |
1817749d CL |
1939 | ;; [vmladavq_p_u, vmladavq_p_s] |
1940 | ;; [vmladavxq_p_s] | |
1941 | ;; [vmlsdavq_p_s] | |
1942 | ;; [vmlsdavxq_p_s] | |
8165795c | 1943 | ;; |
1817749d | 1944 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
8165795c | 1945 | [ |
3d537943 | 1946 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8165795c SP |
1947 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") |
1948 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1949 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
1817749d | 1950 | MVE_VMLxDAVQ_P)) |
8165795c SP |
1951 | ] |
1952 | "TARGET_HAVE_MVE" | |
1817749d | 1953 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1, %q2" |
8165795c SP |
1954 | [(set_attr "type" "mve_move") |
1955 | (set_attr "length""8")]) | |
1956 | ||
1957 | ;; | |
1958 | ;; [vmlaq_n_u, vmlaq_n_s]) | |
1959 | ;; | |
1960 | (define_insn "mve_vmlaq_n_<supf><mode>" | |
1961 | [ | |
1962 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1963 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1964 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
1965 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
1966 | VMLAQ_N)) | |
1967 | ] | |
1968 | "TARGET_HAVE_MVE" | |
1969 | "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
1970 | [(set_attr "type" "mve_move") | |
1971 | ]) | |
1972 | ||
1973 | ;; | |
1974 | ;; [vmlasq_n_u, vmlasq_n_s]) | |
1975 | ;; | |
1976 | (define_insn "mve_vmlasq_n_<supf><mode>" | |
1977 | [ | |
1978 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1979 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1980 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
1981 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
1982 | VMLASQ_N)) | |
1983 | ] | |
1984 | "TARGET_HAVE_MVE" | |
1985 | "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
1986 | [(set_attr "type" "mve_move") | |
1987 | ]) | |
1988 | ||
8165795c SP |
1989 | ;; |
1990 | ;; [vmvnq_m_s, vmvnq_m_u]) | |
1991 | ;; | |
1992 | (define_insn "mve_vmvnq_m_<supf><mode>" | |
1993 | [ | |
1994 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1995 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1996 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 1997 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
8165795c SP |
1998 | VMVNQ_M)) |
1999 | ] | |
2000 | "TARGET_HAVE_MVE" | |
2001 | "vpst\;vmvnt %q0, %q2" | |
2002 | [(set_attr "type" "mve_move") | |
2003 | (set_attr "length""8")]) | |
2004 | ||
8165795c SP |
2005 | ;; |
2006 | ;; [vpselq_u, vpselq_s]) | |
2007 | ;; | |
a6eacbf1 | 2008 | (define_insn "@mve_vpselq_<supf><mode>" |
8165795c SP |
2009 | [ |
2010 | (set (match_operand:MVE_1 0 "s_register_operand" "=w") | |
2011 | (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") | |
2012 | (match_operand:MVE_1 2 "s_register_operand" "w") | |
91224cf6 | 2013 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
8165795c SP |
2014 | VPSELQ)) |
2015 | ] | |
2016 | "TARGET_HAVE_MVE" | |
2017 | "vpsel %q0, %q1, %q2" | |
2018 | [(set_attr "type" "mve_move") | |
2019 | ]) | |
2020 | ||
8165795c | 2021 | ;; |
237f12da | 2022 | ;; [vqdmlahq_n_s]) |
8165795c SP |
2023 | ;; |
2024 | (define_insn "mve_vqdmlahq_n_<supf><mode>" | |
2025 | [ | |
2026 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2027 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2028 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2029 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2030 | VQDMLAHQ_N)) | |
2031 | ] | |
2032 | "TARGET_HAVE_MVE" | |
2033 | "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" | |
2034 | [(set_attr "type" "mve_move") | |
2035 | ]) | |
2036 | ||
afb198ee CL |
2037 | ;; |
2038 | ;; [vqdmlashq_n_s]) | |
2039 | ;; | |
2040 | (define_insn "mve_vqdmlashq_n_<supf><mode>" | |
2041 | [ | |
2042 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2043 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2044 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2045 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2046 | VQDMLASHQ_N)) | |
2047 | ] | |
2048 | "TARGET_HAVE_MVE" | |
2049 | "vqdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" | |
2050 | [(set_attr "type" "mve_move") | |
2051 | ]) | |
2052 | ||
8165795c SP |
2053 | ;; |
2054 | ;; [vqrdmladhq_s]) | |
2055 | ;; | |
2056 | (define_insn "mve_vqrdmladhq_s<mode>" | |
2057 | [ | |
2058 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2059 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2060 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2061 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2062 | VQRDMLADHQ_S)) | |
2063 | ] | |
2064 | "TARGET_HAVE_MVE" | |
2065 | "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2066 | [(set_attr "type" "mve_move") | |
2067 | ]) | |
2068 | ||
2069 | ;; | |
2070 | ;; [vqrdmladhxq_s]) | |
2071 | ;; | |
2072 | (define_insn "mve_vqrdmladhxq_s<mode>" | |
2073 | [ | |
2074 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2075 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2076 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2077 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2078 | VQRDMLADHXQ_S)) | |
2079 | ] | |
2080 | "TARGET_HAVE_MVE" | |
2081 | "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2082 | [(set_attr "type" "mve_move") | |
2083 | ]) | |
2084 | ||
2085 | ;; | |
237f12da | 2086 | ;; [vqrdmlahq_n_s]) |
8165795c SP |
2087 | ;; |
2088 | (define_insn "mve_vqrdmlahq_n_<supf><mode>" | |
2089 | [ | |
2090 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2091 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2092 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2093 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2094 | VQRDMLAHQ_N)) | |
2095 | ] | |
2096 | "TARGET_HAVE_MVE" | |
2097 | "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" | |
2098 | [(set_attr "type" "mve_move") | |
2099 | ]) | |
2100 | ||
2101 | ;; | |
237f12da | 2102 | ;; [vqrdmlashq_n_s]) |
8165795c SP |
2103 | ;; |
2104 | (define_insn "mve_vqrdmlashq_n_<supf><mode>" | |
2105 | [ | |
2106 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2107 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2108 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2109 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2110 | VQRDMLASHQ_N)) | |
2111 | ] | |
2112 | "TARGET_HAVE_MVE" | |
2113 | "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" | |
2114 | [(set_attr "type" "mve_move") | |
2115 | ]) | |
2116 | ||
2117 | ;; | |
2118 | ;; [vqrdmlsdhq_s]) | |
2119 | ;; | |
2120 | (define_insn "mve_vqrdmlsdhq_s<mode>" | |
2121 | [ | |
2122 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2123 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2124 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2125 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2126 | VQRDMLSDHQ_S)) | |
2127 | ] | |
2128 | "TARGET_HAVE_MVE" | |
2129 | "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2130 | [(set_attr "type" "mve_move") | |
2131 | ]) | |
2132 | ||
2133 | ;; | |
2134 | ;; [vqrdmlsdhxq_s]) | |
2135 | ;; | |
2136 | (define_insn "mve_vqrdmlsdhxq_s<mode>" | |
2137 | [ | |
2138 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2139 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2140 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2141 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2142 | VQRDMLSDHXQ_S)) | |
2143 | ] | |
2144 | "TARGET_HAVE_MVE" | |
2145 | "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2146 | [(set_attr "type" "mve_move") | |
2147 | ]) | |
2148 | ||
2149 | ;; | |
c4d4e62b CL |
2150 | ;; [vqrshlq_m_n_s, vqrshlq_m_n_u] |
2151 | ;; [vrshlq_m_n_s, vrshlq_m_n_u] | |
8165795c | 2152 | ;; |
c4d4e62b | 2153 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8165795c SP |
2154 | [ |
2155 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2156 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2157 | (match_operand:SI 2 "s_register_operand" "r") | |
724d6566 | 2158 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
c4d4e62b | 2159 | MVE_RSHIFT_M_N)) |
8165795c SP |
2160 | ] |
2161 | "TARGET_HAVE_MVE" | |
c4d4e62b | 2162 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2" |
8165795c SP |
2163 | [(set_attr "type" "mve_move") |
2164 | (set_attr "length""8")]) | |
2165 | ||
2166 | ;; | |
7e6c39a3 CL |
2167 | ;; [vqshlq_m_r_u, vqshlq_m_r_s] |
2168 | ;; [vshlq_m_r_u, vshlq_m_r_s] | |
8165795c | 2169 | ;; |
7e6c39a3 | 2170 | (define_insn "@mve_<mve_insn>q_m_r_<supf><mode>" |
8165795c SP |
2171 | [ |
2172 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2173 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2174 | (match_operand:SI 2 "s_register_operand" "r") | |
724d6566 | 2175 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
7e6c39a3 | 2176 | MVE_SHIFT_M_R)) |
8165795c SP |
2177 | ] |
2178 | "TARGET_HAVE_MVE" | |
7e6c39a3 | 2179 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2" |
8165795c SP |
2180 | [(set_attr "type" "mve_move") |
2181 | (set_attr "length""8")]) | |
2182 | ||
2183 | ;; | |
2184 | ;; [vrev64q_m_u, vrev64q_m_s]) | |
2185 | ;; | |
0c1eb901 | 2186 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8165795c | 2187 | [ |
06aa66af | 2188 | (set (match_operand:MVE_2 0 "s_register_operand" "=&w") |
8165795c SP |
2189 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
2190 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 2191 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
8165795c SP |
2192 | VREV64Q_M)) |
2193 | ] | |
2194 | "TARGET_HAVE_MVE" | |
0c1eb901 | 2195 | "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2" |
8165795c SP |
2196 | [(set_attr "type" "mve_move") |
2197 | (set_attr "length""8")]) | |
2198 | ||
8165795c SP |
2199 | ;; |
2200 | ;; [vsliq_n_u, vsliq_n_s]) | |
2201 | ;; | |
2202 | (define_insn "mve_vsliq_n_<supf><mode>" | |
2203 | [ | |
2204 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2205 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2206 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2207 | (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")] | |
2208 | VSLIQ_N)) | |
2209 | ] | |
2210 | "TARGET_HAVE_MVE" | |
2211 | "vsli.%#<V_sz_elem>\t%q0, %q2, %3" | |
2212 | [(set_attr "type" "mve_move") | |
2213 | ]) | |
2214 | ||
2215 | ;; | |
2216 | ;; [vsriq_n_u, vsriq_n_s]) | |
2217 | ;; | |
2218 | (define_insn "mve_vsriq_n_<supf><mode>" | |
2219 | [ | |
2220 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2221 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2222 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
c3fb6658 | 2223 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")] |
8165795c SP |
2224 | VSRIQ_N)) |
2225 | ] | |
2226 | "TARGET_HAVE_MVE" | |
2227 | "vsri.%#<V_sz_elem>\t%q0, %q2, %3" | |
2228 | [(set_attr "type" "mve_move") | |
2229 | ]) | |
2230 | ||
2231 | ;; | |
2232 | ;; [vqdmlsdhxq_s]) | |
2233 | ;; | |
2234 | (define_insn "mve_vqdmlsdhxq_s<mode>" | |
2235 | [ | |
2236 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2237 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2238 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2239 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2240 | VQDMLSDHXQ_S)) | |
2241 | ] | |
2242 | "TARGET_HAVE_MVE" | |
2243 | "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2244 | [(set_attr "type" "mve_move") | |
2245 | ]) | |
2246 | ||
2247 | ;; | |
2248 | ;; [vqdmlsdhq_s]) | |
2249 | ;; | |
2250 | (define_insn "mve_vqdmlsdhq_s<mode>" | |
2251 | [ | |
2252 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2253 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2254 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2255 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2256 | VQDMLSDHQ_S)) | |
2257 | ] | |
2258 | "TARGET_HAVE_MVE" | |
2259 | "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2260 | [(set_attr "type" "mve_move") | |
2261 | ]) | |
2262 | ||
2263 | ;; | |
2264 | ;; [vqdmladhxq_s]) | |
2265 | ;; | |
2266 | (define_insn "mve_vqdmladhxq_s<mode>" | |
2267 | [ | |
2268 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2269 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2270 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2271 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2272 | VQDMLADHXQ_S)) | |
2273 | ] | |
2274 | "TARGET_HAVE_MVE" | |
2275 | "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2276 | [(set_attr "type" "mve_move") | |
2277 | ]) | |
2278 | ||
2279 | ;; | |
2280 | ;; [vqdmladhq_s]) | |
2281 | ;; | |
2282 | (define_insn "mve_vqdmladhq_s<mode>" | |
2283 | [ | |
2284 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2285 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2286 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2287 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
2288 | VQDMLADHQ_S)) | |
2289 | ] | |
2290 | "TARGET_HAVE_MVE" | |
2291 | "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
2292 | [(set_attr "type" "mve_move") | |
2293 | ]) | |
2294 | ||
e3678b44 | 2295 | ;; |
7734b991 CL |
2296 | ;; [vabsq_m_f] |
2297 | ;; [vnegq_m_f] | |
2298 | ;; [vrndaq_m_f] | |
2299 | ;; [vrndmq_m_f] | |
2300 | ;; [vrndnq_m_f] | |
2301 | ;; [vrndpq_m_f] | |
2302 | ;; [vrndq_m_f] | |
2303 | ;; [vrndxq_m_f] | |
e3678b44 | 2304 | ;; |
7734b991 | 2305 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
e3678b44 SP |
2306 | [ |
2307 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2308 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2309 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
724d6566 | 2310 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
7734b991 | 2311 | MVE_FP_M_UNARY)) |
e3678b44 SP |
2312 | ] |
2313 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
7734b991 | 2314 | "vpst\;<mve_mnemo>t.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2315 | [(set_attr "type" "mve_move") |
2316 | (set_attr "length""8")]) | |
2317 | ||
2318 | ;; | |
2319 | ;; [vaddlvaq_p_s vaddlvaq_p_u]) | |
2320 | ;; | |
42c94cce | 2321 | (define_insn "@mve_<mve_insn>q_p_<supf>v4si" |
e3678b44 SP |
2322 | [ |
2323 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2324 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2325 | (match_operand:V4SI 2 "s_register_operand" "w") | |
c6b4ea7a | 2326 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2327 | VADDLVAQ_P)) |
2328 | ] | |
2329 | "TARGET_HAVE_MVE" | |
42c94cce | 2330 | "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q2" |
e3678b44 SP |
2331 | [(set_attr "type" "mve_move") |
2332 | (set_attr "length""8")]) | |
2333 | ;; | |
db253e8b | 2334 | ;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270]) |
3cc4e183 | 2335 | ;; |
db253e8b | 2336 | (define_insn "mve_vcmlaq<mve_rot><mode>" |
3cc4e183 | 2337 | [ |
db253e8b | 2338 | (set (match_operand:MVE_0 0 "s_register_operand" "=w,w") |
389b67fe TC |
2339 | (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0") |
2340 | (unspec:MVE_0 | |
2341 | [(match_operand:MVE_0 2 "s_register_operand" "w,w") | |
2342 | (match_operand:MVE_0 3 "s_register_operand" "w,w")] | |
2343 | VCMLA))) | |
3cc4e183 TC |
2344 | ] |
2345 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db253e8b | 2346 | "@ |
389b67fe TC |
2347 | vcmul.f%#<V_sz_elem> %q0, %q2, %q3, #<rot> |
2348 | vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>" | |
e3678b44 SP |
2349 | [(set_attr "type" "mve_move") |
2350 | ]) | |
2351 | ||
2352 | ;; | |
2353 | ;; [vcmpeqq_m_n_f]) | |
e3678b44 | 2354 | ;; [vcmpgeq_m_n_f]) |
e3678b44 | 2355 | ;; [vcmpgtq_m_n_f]) |
e3678b44 | 2356 | ;; [vcmpleq_m_n_f]) |
e3678b44 | 2357 | ;; [vcmpltq_m_n_f]) |
e3678b44 SP |
2358 | ;; [vcmpneq_m_n_f]) |
2359 | ;; | |
6a08718a | 2360 | (define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>" |
e3678b44 | 2361 | [ |
e6a4aefc CL |
2362 | (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") |
2363 | (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") | |
e3678b44 | 2364 | (match_operand:<V_elem> 2 "s_register_operand" "r") |
e6a4aefc | 2365 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
6a08718a | 2366 | MVE_CMP_M_N_F)) |
e3678b44 SP |
2367 | ] |
2368 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6a08718a | 2369 | "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2" |
e3678b44 SP |
2370 | [(set_attr "type" "mve_move") |
2371 | (set_attr "length""8")]) | |
2372 | ||
2373 | ;; | |
2374 | ;; [vcvtbq_m_f16_f32]) | |
2375 | ;; | |
2376 | (define_insn "mve_vcvtbq_m_f16_f32v8hf" | |
2377 | [ | |
2378 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2379 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2380 | (match_operand:V4SF 2 "s_register_operand" "w") | |
c6b4ea7a | 2381 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2382 | VCVTBQ_M_F16_F32)) |
2383 | ] | |
2384 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2385 | "vpst\;vcvtbt.f16.f32 %q0, %q2" | |
2386 | [(set_attr "type" "mve_move") | |
2387 | (set_attr "length""8")]) | |
2388 | ||
2389 | ;; | |
2390 | ;; [vcvtbq_m_f32_f16]) | |
2391 | ;; | |
2392 | (define_insn "mve_vcvtbq_m_f32_f16v4sf" | |
2393 | [ | |
2394 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
2395 | (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") | |
2396 | (match_operand:V8HF 2 "s_register_operand" "w") | |
c6b4ea7a | 2397 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2398 | VCVTBQ_M_F32_F16)) |
2399 | ] | |
2400 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2401 | "vpst\;vcvtbt.f32.f16 %q0, %q2" | |
2402 | [(set_attr "type" "mve_move") | |
2403 | (set_attr "length""8")]) | |
2404 | ||
2405 | ;; | |
2406 | ;; [vcvttq_m_f16_f32]) | |
2407 | ;; | |
2408 | (define_insn "mve_vcvttq_m_f16_f32v8hf" | |
2409 | [ | |
2410 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2411 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2412 | (match_operand:V4SF 2 "s_register_operand" "w") | |
c6b4ea7a | 2413 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2414 | VCVTTQ_M_F16_F32)) |
2415 | ] | |
2416 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2417 | "vpst\;vcvttt.f16.f32 %q0, %q2" | |
2418 | [(set_attr "type" "mve_move") | |
2419 | (set_attr "length""8")]) | |
2420 | ||
2421 | ;; | |
2422 | ;; [vcvttq_m_f32_f16]) | |
2423 | ;; | |
2424 | (define_insn "mve_vcvttq_m_f32_f16v4sf" | |
2425 | [ | |
2426 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
2427 | (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") | |
2428 | (match_operand:V8HF 2 "s_register_operand" "w") | |
c6b4ea7a | 2429 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2430 | VCVTTQ_M_F32_F16)) |
2431 | ] | |
2432 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2433 | "vpst\;vcvttt.f32.f16 %q0, %q2" | |
2434 | [(set_attr "type" "mve_move") | |
2435 | (set_attr "length""8")]) | |
2436 | ||
2437 | ;; | |
2438 | ;; [vdupq_m_n_f]) | |
2439 | ;; | |
fc468102 | 2440 | (define_insn "@mve_<mve_insn>q_m_n_f<mode>" |
e3678b44 SP |
2441 | [ |
2442 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2443 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2444 | (match_operand:<V_elem> 2 "s_register_operand" "r") | |
724d6566 | 2445 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
fc468102 | 2446 | MVE_FP_M_N_VDUPQ_ONLY)) |
e3678b44 SP |
2447 | ] |
2448 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
fc468102 | 2449 | "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2" |
e3678b44 SP |
2450 | [(set_attr "type" "mve_move") |
2451 | (set_attr "length""8")]) | |
2452 | ||
2453 | ;; | |
2454 | ;; [vfmaq_f]) | |
2455 | ;; | |
2456 | (define_insn "mve_vfmaq_f<mode>" | |
2457 | [ | |
2458 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2459 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2460 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
2461 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
2462 | VFMAQ_F)) | |
2463 | ] | |
2464 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2465 | "vfma.f%#<V_sz_elem> %q0, %q2, %q3" | |
2466 | [(set_attr "type" "mve_move") | |
2467 | ]) | |
2468 | ||
2469 | ;; | |
2470 | ;; [vfmaq_n_f]) | |
2471 | ;; | |
2472 | (define_insn "mve_vfmaq_n_f<mode>" | |
2473 | [ | |
2474 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2475 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2476 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
2477 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2478 | VFMAQ_N_F)) | |
2479 | ] | |
2480 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2481 | "vfma.f%#<V_sz_elem> %q0, %q2, %3" | |
2482 | [(set_attr "type" "mve_move") | |
2483 | ]) | |
2484 | ||
2485 | ;; | |
2486 | ;; [vfmasq_n_f]) | |
2487 | ;; | |
2488 | (define_insn "mve_vfmasq_n_f<mode>" | |
2489 | [ | |
2490 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2491 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2492 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
2493 | (match_operand:<V_elem> 3 "s_register_operand" "r")] | |
2494 | VFMASQ_N_F)) | |
2495 | ] | |
2496 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2497 | "vfmas.f%#<V_sz_elem> %q0, %q2, %3" | |
2498 | [(set_attr "type" "mve_move") | |
2499 | ]) | |
2500 | ;; | |
2501 | ;; [vfmsq_f]) | |
2502 | ;; | |
2503 | (define_insn "mve_vfmsq_f<mode>" | |
2504 | [ | |
2505 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2506 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2507 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
2508 | (match_operand:MVE_0 3 "s_register_operand" "w")] | |
2509 | VFMSQ_F)) | |
2510 | ] | |
2511 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2512 | "vfms.f%#<V_sz_elem> %q0, %q2, %q3" | |
2513 | [(set_attr "type" "mve_move") | |
2514 | ]) | |
2515 | ||
2516 | ;; | |
26d6e02c CL |
2517 | ;; [vmaxnmaq_m_f] |
2518 | ;; [vminnmaq_m_f] | |
e3678b44 | 2519 | ;; |
26d6e02c | 2520 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
e3678b44 SP |
2521 | [ |
2522 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2523 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2524 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
724d6566 | 2525 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
26d6e02c | 2526 | MVE_VMAXNMA_VMINNMAQ_M)) |
e3678b44 SP |
2527 | ] |
2528 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
26d6e02c | 2529 | "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2530 | [(set_attr "type" "mve_move") |
2531 | (set_attr "length""8")]) | |
e3678b44 SP |
2532 | |
2533 | ;; | |
d814dc9d CL |
2534 | ;; [vmaxnmavq_p_f] |
2535 | ;; [vmaxnmvq_p_f] | |
2536 | ;; [vminnmavq_p_f] | |
2537 | ;; [vminnmvq_p_f] | |
e3678b44 | 2538 | ;; |
d814dc9d | 2539 | (define_insn "@mve_<mve_insn>q_p_f<mode>" |
e3678b44 SP |
2540 | [ |
2541 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2542 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2543 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
724d6566 | 2544 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
d814dc9d | 2545 | MVE_VMAXNMxV_MINNMxVQ_P)) |
e3678b44 SP |
2546 | ] |
2547 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
d814dc9d | 2548 | "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%0, %q2" |
e3678b44 SP |
2549 | [(set_attr "type" "mve_move") |
2550 | (set_attr "length""8")]) | |
d814dc9d | 2551 | |
e3678b44 | 2552 | ;; |
c68ccdf2 CL |
2553 | ;; [vmlaldavaq_s, vmlaldavaq_u] |
2554 | ;; [vmlaldavaxq_s] | |
2555 | ;; [vmlsldavaq_s] | |
2556 | ;; [vmlsldavaxq_s] | |
e3678b44 | 2557 | ;; |
c68ccdf2 | 2558 | (define_insn "@mve_<mve_insn>q_<supf><mode>" |
e3678b44 SP |
2559 | [ |
2560 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2561 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2562 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
2563 | (match_operand:MVE_5 3 "s_register_operand" "w")] | |
c68ccdf2 | 2564 | MVE_VMLxLDAVAxQ)) |
e3678b44 SP |
2565 | ] |
2566 | "TARGET_HAVE_MVE" | |
c68ccdf2 | 2567 | "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" |
e3678b44 SP |
2568 | [(set_attr "type" "mve_move") |
2569 | ]) | |
2570 | ||
2571 | ;; | |
c1e068e4 CL |
2572 | ;; [vmlaldavq_p_u, vmlaldavq_p_s] |
2573 | ;; [vmlaldavxq_p_s] | |
2574 | ;; [vmlsldavq_p_s] | |
2575 | ;; [vmlsldavxq_p_s] | |
e3678b44 | 2576 | ;; |
c1e068e4 | 2577 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
e3678b44 SP |
2578 | [ |
2579 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2580 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2581 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
724d6566 | 2582 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
c1e068e4 | 2583 | MVE_VMLxLDAVxQ_P)) |
e3678b44 SP |
2584 | ] |
2585 | "TARGET_HAVE_MVE" | |
c1e068e4 | 2586 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" |
e3678b44 SP |
2587 | [(set_attr "type" "mve_move") |
2588 | (set_attr "length""8")]) | |
2589 | ||
e3678b44 SP |
2590 | ;; |
2591 | ;; [vmovlbq_m_u, vmovlbq_m_s]) | |
e3678b44 SP |
2592 | ;; [vmovltq_m_u, vmovltq_m_s]) |
2593 | ;; | |
51fca3e1 | 2594 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
e3678b44 SP |
2595 | [ |
2596 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2597 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
2598 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
724d6566 | 2599 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
51fca3e1 | 2600 | VMOVLxQ_M)) |
e3678b44 SP |
2601 | ] |
2602 | "TARGET_HAVE_MVE" | |
51fca3e1 | 2603 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2604 | [(set_attr "type" "mve_move") |
2605 | (set_attr "length""8")]) | |
e3678b44 SP |
2606 | |
2607 | ;; | |
7f49b4a0 CL |
2608 | ;; [vmovnbq_m_u, vmovnbq_m_s] |
2609 | ;; [vmovntq_m_u, vmovntq_m_s] | |
2610 | ;; [vqmovnbq_m_s, vqmovnbq_m_u] | |
2611 | ;; [vqmovntq_m_u, vqmovntq_m_s] | |
2612 | ;; [vqmovunbq_m_s] | |
2613 | ;; [vqmovuntq_m_s] | |
e3678b44 | 2614 | ;; |
7f49b4a0 | 2615 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
e3678b44 SP |
2616 | [ |
2617 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2618 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2619 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
724d6566 | 2620 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
7f49b4a0 | 2621 | MVE_MOVN_M)) |
e3678b44 SP |
2622 | ] |
2623 | "TARGET_HAVE_MVE" | |
7f49b4a0 | 2624 | "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2625 | [(set_attr "type" "mve_move") |
2626 | (set_attr "length""8")]) | |
2627 | ||
2628 | ;; | |
2629 | ;; [vmvnq_m_n_u, vmvnq_m_n_s]) | |
2630 | ;; | |
2631 | (define_insn "mve_vmvnq_m_n_<supf><mode>" | |
2632 | [ | |
2633 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2634 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2635 | (match_operand:SI 2 "immediate_operand" "i") | |
724d6566 | 2636 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2637 | VMVNQ_M_N)) |
2638 | ] | |
2639 | "TARGET_HAVE_MVE" | |
2640 | "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2" | |
2641 | [(set_attr "type" "mve_move") | |
2642 | (set_attr "length""8")]) | |
e3678b44 SP |
2643 | |
2644 | ;; | |
67e4e591 CL |
2645 | ;; [vbicq_m_n_s, vbicq_m_n_u] |
2646 | ;; [vorrq_m_n_s, vorrq_m_n_u] | |
e3678b44 | 2647 | ;; |
67e4e591 | 2648 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
e3678b44 SP |
2649 | [ |
2650 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2651 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2652 | (match_operand:SI 2 "immediate_operand" "i") | |
724d6566 | 2653 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
67e4e591 | 2654 | MVE_INT_M_N_BINARY_LOGIC)) |
e3678b44 SP |
2655 | ] |
2656 | "TARGET_HAVE_MVE" | |
67e4e591 | 2657 | "vpst\;<mve_insn>t.i%#<V_sz_elem> %q0, %2" |
e3678b44 SP |
2658 | [(set_attr "type" "mve_move") |
2659 | (set_attr "length""8")]) | |
67e4e591 | 2660 | |
e3678b44 SP |
2661 | ;; |
2662 | ;; [vpselq_f]) | |
2663 | ;; | |
a6eacbf1 | 2664 | (define_insn "@mve_vpselq_f<mode>" |
e3678b44 SP |
2665 | [ |
2666 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2667 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2668 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
91224cf6 | 2669 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2670 | VPSELQ_F)) |
2671 | ] | |
2672 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2673 | "vpsel %q0, %q1, %q2" | |
2674 | [(set_attr "type" "mve_move") | |
2675 | ]) | |
2676 | ||
e3678b44 SP |
2677 | ;; |
2678 | ;; [vrev32q_m_f]) | |
2679 | ;; | |
0c1eb901 | 2680 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
e3678b44 | 2681 | [ |
0c1eb901 CL |
2682 | (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w") |
2683 | (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "0") | |
2684 | (match_operand:MVE_V8HF 2 "s_register_operand" "w") | |
2685 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] | |
2686 | MVE_FP_M_VREV32Q_ONLY)) | |
e3678b44 SP |
2687 | ] |
2688 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
0c1eb901 | 2689 | "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2690 | [(set_attr "type" "mve_move") |
2691 | (set_attr "length""8")]) | |
2692 | ||
2693 | ;; | |
2694 | ;; [vrev32q_m_s, vrev32q_m_u]) | |
2695 | ;; | |
0c1eb901 | 2696 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
e3678b44 SP |
2697 | [ |
2698 | (set (match_operand:MVE_3 0 "s_register_operand" "=w") | |
2699 | (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") | |
2700 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
724d6566 | 2701 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2702 | VREV32Q_M)) |
2703 | ] | |
2704 | "TARGET_HAVE_MVE" | |
0c1eb901 | 2705 | "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2706 | [(set_attr "type" "mve_move") |
2707 | (set_attr "length""8")]) | |
2708 | ||
2709 | ;; | |
2710 | ;; [vrev64q_m_f]) | |
2711 | ;; | |
0c1eb901 | 2712 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
e3678b44 | 2713 | [ |
06aa66af | 2714 | (set (match_operand:MVE_0 0 "s_register_operand" "=&w") |
e3678b44 SP |
2715 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
2716 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
724d6566 | 2717 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
0c1eb901 | 2718 | MVE_FP_M_VREV64Q_ONLY)) |
e3678b44 SP |
2719 | ] |
2720 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
0c1eb901 | 2721 | "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2722 | [(set_attr "type" "mve_move") |
2723 | (set_attr "length""8")]) | |
2724 | ||
2725 | ;; | |
2726 | ;; [vrmlaldavhaxq_s]) | |
2727 | ;; | |
2728 | (define_insn "mve_vrmlaldavhaxq_sv4si" | |
2729 | [ | |
2730 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2731 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2732 | (match_operand:V4SI 2 "s_register_operand" "w") | |
2733 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
2734 | VRMLALDAVHAXQ_S)) | |
2735 | ] | |
2736 | "TARGET_HAVE_MVE" | |
2737 | "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3" | |
2738 | [(set_attr "type" "mve_move") | |
2739 | ]) | |
2740 | ||
2741 | ;; | |
e044696f CL |
2742 | ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s] |
2743 | ;; [vrmlaldavhxq_p_s] | |
2744 | ;; [vrmlsldavhq_p_s] | |
2745 | ;; [vrmlsldavhxq_p_s] | |
e3678b44 | 2746 | ;; |
e044696f | 2747 | (define_insn "@mve_<mve_insn>q_p_<supf>v4si" |
e3678b44 SP |
2748 | [ |
2749 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2750 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2751 | (match_operand:V4SI 2 "s_register_operand" "w") | |
e044696f CL |
2752 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
2753 | MVE_VRMLxLDAVHxQ_P)) | |
e3678b44 SP |
2754 | ] |
2755 | "TARGET_HAVE_MVE" | |
e044696f | 2756 | "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1, %q2" |
e3678b44 SP |
2757 | [(set_attr "type" "mve_move") |
2758 | (set_attr "length""8")]) | |
2759 | ||
2760 | ;; | |
2761 | ;; [vrmlsldavhaxq_s]) | |
2762 | ;; | |
2763 | (define_insn "mve_vrmlsldavhaxq_sv4si" | |
2764 | [ | |
2765 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2766 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2767 | (match_operand:V4SI 2 "s_register_operand" "w") | |
2768 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
2769 | VRMLSLDAVHAXQ_S)) | |
2770 | ] | |
2771 | "TARGET_HAVE_MVE" | |
2772 | "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3" | |
2773 | [(set_attr "type" "mve_move") | |
2774 | ]) | |
2775 | ||
e3678b44 SP |
2776 | ;; |
2777 | ;; [vcvtmq_m_s, vcvtmq_m_u]) | |
2778 | ;; | |
2779 | (define_insn "mve_vcvtmq_m_<supf><mode>" | |
2780 | [ | |
2781 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2782 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2783 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 2784 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2785 | VCVTMQ_M)) |
2786 | ] | |
2787 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 2788 | "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2789 | [(set_attr "type" "mve_move") |
2790 | (set_attr "length""8")]) | |
2791 | ||
2792 | ;; | |
2793 | ;; [vcvtpq_m_u, vcvtpq_m_s]) | |
2794 | ;; | |
2795 | (define_insn "mve_vcvtpq_m_<supf><mode>" | |
2796 | [ | |
2797 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2798 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2799 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 2800 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2801 | VCVTPQ_M)) |
2802 | ] | |
2803 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 2804 | "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2805 | [(set_attr "type" "mve_move") |
2806 | (set_attr "length""8")]) | |
2807 | ||
2808 | ;; | |
2809 | ;; [vcvtnq_m_s, vcvtnq_m_u]) | |
2810 | ;; | |
2811 | (define_insn "mve_vcvtnq_m_<supf><mode>" | |
2812 | [ | |
2813 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2814 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2815 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 2816 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2817 | VCVTNQ_M)) |
2818 | ] | |
2819 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 2820 | "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2821 | [(set_attr "type" "mve_move") |
2822 | (set_attr "length""8")]) | |
2823 | ||
2824 | ;; | |
2825 | ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]) | |
2826 | ;; | |
2827 | (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>" | |
2828 | [ | |
2829 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2830 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2831 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
d2ce75fe | 2832 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") |
724d6566 | 2833 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
e3678b44 SP |
2834 | VCVTQ_M_N_FROM_F)) |
2835 | ] | |
2836 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 2837 | "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3" |
e3678b44 SP |
2838 | [(set_attr "type" "mve_move") |
2839 | (set_attr "length""8")]) | |
2840 | ||
2841 | ;; | |
2842 | ;; [vrev16q_m_u, vrev16q_m_s]) | |
2843 | ;; | |
0c1eb901 | 2844 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
e3678b44 | 2845 | [ |
0c1eb901 CL |
2846 | (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w") |
2847 | (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "0") | |
2848 | (match_operand:MVE_V16QI 2 "s_register_operand" "w") | |
2849 | (match_operand:V16BI 3 "vpr_register_operand" "Up")] | |
e3678b44 SP |
2850 | VREV16Q_M)) |
2851 | ] | |
2852 | "TARGET_HAVE_MVE" | |
0c1eb901 | 2853 | "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2854 | [(set_attr "type" "mve_move") |
2855 | (set_attr "length""8")]) | |
2856 | ||
2857 | ;; | |
2858 | ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]) | |
2859 | ;; | |
2860 | (define_insn "mve_vcvtq_m_from_f_<supf><mode>" | |
2861 | [ | |
2862 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2863 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2864 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
724d6566 | 2865 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
e3678b44 SP |
2866 | VCVTQ_M_FROM_F)) |
2867 | ] | |
2868 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
db5db9d2 | 2869 | "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" |
e3678b44 SP |
2870 | [(set_attr "type" "mve_move") |
2871 | (set_attr "length""8")]) | |
2872 | ||
e3678b44 SP |
2873 | ;; |
2874 | ;; [vrmlsldavhaq_s]) | |
2875 | ;; | |
2876 | (define_insn "mve_vrmlsldavhaq_sv4si" | |
2877 | [ | |
2878 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2879 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2880 | (match_operand:V4SI 2 "s_register_operand" "w") | |
2881 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
2882 | VRMLSLDAVHAQ_S)) | |
2883 | ] | |
2884 | "TARGET_HAVE_MVE" | |
2885 | "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" | |
2886 | [(set_attr "type" "mve_move") | |
2887 | ]) | |
db5db9d2 SP |
2888 | |
2889 | ;; | |
2890 | ;; [vabavq_p_s, vabavq_p_u]) | |
2891 | ;; | |
1af6d1db | 2892 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
db5db9d2 SP |
2893 | [ |
2894 | (set (match_operand:SI 0 "s_register_operand" "=r") | |
2895 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
2896 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2897 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 2898 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
db5db9d2 SP |
2899 | VABAVQ_P)) |
2900 | ] | |
2901 | "TARGET_HAVE_MVE" | |
1af6d1db | 2902 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2, %q3" |
db5db9d2 | 2903 | [(set_attr "type" "mve_move") |
330d665c | 2904 | (set_attr "length" "8")]) |
db5db9d2 SP |
2905 | |
2906 | ;; | |
2907 | ;; [vqshluq_m_n_s]) | |
2908 | ;; | |
2909 | (define_insn "mve_vqshluq_m_n_s<mode>" | |
2910 | [ | |
2911 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2912 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2913 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
c3fb6658 | 2914 | (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") |
724d6566 | 2915 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
db5db9d2 SP |
2916 | VQSHLUQ_M_N_S)) |
2917 | ] | |
2918 | "TARGET_HAVE_MVE" | |
2919 | "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3" | |
330d665c CL |
2920 | [(set_attr "type" "mve_move") |
2921 | (set_attr "length" "8")]) | |
db5db9d2 | 2922 | |
db5db9d2 SP |
2923 | ;; |
2924 | ;; [vsriq_m_n_s, vsriq_m_n_u]) | |
2925 | ;; | |
2926 | (define_insn "mve_vsriq_m_n_<supf><mode>" | |
2927 | [ | |
2928 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2929 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2930 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
c3fb6658 | 2931 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") |
724d6566 | 2932 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
db5db9d2 SP |
2933 | VSRIQ_M_N)) |
2934 | ] | |
2935 | "TARGET_HAVE_MVE" | |
2936 | "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3" | |
330d665c CL |
2937 | [(set_attr "type" "mve_move") |
2938 | (set_attr "length" "8")]) | |
db5db9d2 | 2939 | |
db5db9d2 SP |
2940 | ;; |
2941 | ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) | |
2942 | ;; | |
2943 | (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>" | |
2944 | [ | |
2945 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2946 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2947 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
d2ce75fe | 2948 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") |
724d6566 | 2949 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
db5db9d2 SP |
2950 | VCVTQ_M_N_TO_F)) |
2951 | ] | |
2952 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2953 | "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3" | |
2954 | [(set_attr "type" "mve_move") | |
2955 | (set_attr "length""8")]) | |
5cbe0c09 | 2956 | |
8eb3b6b9 | 2957 | ;; |
5cbe0c09 CL |
2958 | ;; [vabdq_m_s, vabdq_m_u] |
2959 | ;; [vhaddq_m_s, vhaddq_m_u] | |
2960 | ;; [vhsubq_m_s, vhsubq_m_u] | |
2961 | ;; [vmaxq_m_s, vmaxq_m_u] | |
2962 | ;; [vminq_m_s, vminq_m_u] | |
2963 | ;; [vmulhq_m_s, vmulhq_m_u] | |
2964 | ;; [vqaddq_m_u, vqaddq_m_s] | |
2965 | ;; [vqdmladhq_m_s] | |
2966 | ;; [vqdmladhxq_m_s] | |
2967 | ;; [vqdmlsdhq_m_s] | |
2968 | ;; [vqdmlsdhxq_m_s] | |
2969 | ;; [vqdmulhq_m_s] | |
2970 | ;; [vqrdmladhq_m_s] | |
2971 | ;; [vqrdmladhxq_m_s] | |
2972 | ;; [vqrdmlsdhq_m_s] | |
2973 | ;; [vqrdmlsdhxq_m_s] | |
2974 | ;; [vqrdmulhq_m_s] | |
2975 | ;; [vqrshlq_m_u, vqrshlq_m_s] | |
2976 | ;; [vqshlq_m_u, vqshlq_m_s] | |
2977 | ;; [vqsubq_m_u, vqsubq_m_s] | |
2978 | ;; [vrhaddq_m_u, vrhaddq_m_s] | |
2979 | ;; [vrmulhq_m_u, vrmulhq_m_s] | |
2980 | ;; [vrshlq_m_s, vrshlq_m_u] | |
2981 | ;; [vshlq_m_s, vshlq_m_u] | |
8eb3b6b9 | 2982 | ;; |
5cbe0c09 | 2983 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8eb3b6b9 SP |
2984 | [ |
2985 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2986 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2987 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
2988 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 2989 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
5cbe0c09 | 2990 | MVE_INT_SU_M_BINARY)) |
8eb3b6b9 SP |
2991 | ] |
2992 | "TARGET_HAVE_MVE" | |
5cbe0c09 | 2993 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" |
8eb3b6b9 SP |
2994 | [(set_attr "type" "mve_move") |
2995 | (set_attr "length""8")]) | |
2996 | ||
2997 | ;; | |
b0b3a5e9 CL |
2998 | ;; [vaddq_m_n_s, vaddq_m_n_u] |
2999 | ;; [vsubq_m_n_s, vsubq_m_n_u] | |
3000 | ;; [vmulq_m_n_s, vmulq_m_n_u] | |
8eb3b6b9 | 3001 | ;; |
b0b3a5e9 | 3002 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8eb3b6b9 SP |
3003 | [ |
3004 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3005 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3006 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3007 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3008 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
b0b3a5e9 | 3009 | MVE_INT_M_N_BINARY)) |
8eb3b6b9 SP |
3010 | ] |
3011 | "TARGET_HAVE_MVE" | |
b0b3a5e9 | 3012 | "vpst\;<mve_insn>t.i%#<V_sz_elem> %q0, %q2, %3" |
8eb3b6b9 SP |
3013 | [(set_attr "type" "mve_move") |
3014 | (set_attr "length""8")]) | |
3015 | ||
3016 | ;; | |
b0b3a5e9 CL |
3017 | ;; [vaddq_m_u, vaddq_m_s] |
3018 | ;; [vsubq_m_u, vsubq_m_s] | |
3019 | ;; [vmulq_m_u, vmulq_m_s] | |
8eb3b6b9 | 3020 | ;; |
b0b3a5e9 | 3021 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8eb3b6b9 SP |
3022 | [ |
3023 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3024 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3025 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3026 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3027 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
b0b3a5e9 | 3028 | MVE_INT_M_BINARY)) |
8eb3b6b9 SP |
3029 | ] |
3030 | "TARGET_HAVE_MVE" | |
b0b3a5e9 | 3031 | "vpst\;<mve_insn>t.i%#<V_sz_elem> %q0, %q2, %q3" |
8eb3b6b9 SP |
3032 | [(set_attr "type" "mve_move") |
3033 | (set_attr "length""8")]) | |
3034 | ||
3035 | ;; | |
67e4e591 CL |
3036 | ;; [vandq_m_u, vandq_m_s] |
3037 | ;; [vbicq_m_u, vbicq_m_s] | |
3038 | ;; [veorq_m_u, veorq_m_s] | |
3039 | ;; [vorrq_m_u, vorrq_m_s] | |
8eb3b6b9 | 3040 | ;; |
67e4e591 | 3041 | (define_insn "@mve_<mve_insn>q_m_<supf><mode>" |
8eb3b6b9 SP |
3042 | [ |
3043 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3044 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3045 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3046 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3047 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
67e4e591 | 3048 | MVE_INT_M_BINARY_LOGIC)) |
8eb3b6b9 SP |
3049 | ] |
3050 | "TARGET_HAVE_MVE" | |
67e4e591 | 3051 | "vpst\;<mve_insn>t %q0, %q2, %q3" |
8eb3b6b9 SP |
3052 | [(set_attr "type" "mve_move") |
3053 | (set_attr "length""8")]) | |
3054 | ||
3055 | ;; | |
3056 | ;; [vbrsrq_m_n_u, vbrsrq_m_n_s]) | |
3057 | ;; | |
3058 | (define_insn "mve_vbrsrq_m_n_<supf><mode>" | |
3059 | [ | |
3060 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3061 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3062 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3063 | (match_operand:SI 3 "s_register_operand" "r") | |
724d6566 | 3064 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3065 | VBRSRQ_M_N)) |
3066 | ] | |
3067 | "TARGET_HAVE_MVE" | |
3068 | "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" | |
3069 | [(set_attr "type" "mve_move") | |
3070 | (set_attr "length""8")]) | |
3071 | ||
3072 | ;; | |
3073 | ;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]) | |
3074 | ;; | |
3075 | (define_insn "mve_vcaddq_rot270_m_<supf><mode>" | |
3076 | [ | |
6debbff6 | 3077 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3078 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
3079 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3080 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3081 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3082 | VCADDQ_ROT270_M)) |
3083 | ] | |
3084 | "TARGET_HAVE_MVE" | |
3085 | "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270" | |
3086 | [(set_attr "type" "mve_move") | |
3087 | (set_attr "length""8")]) | |
3088 | ||
3089 | ;; | |
3090 | ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]) | |
3091 | ;; | |
3092 | (define_insn "mve_vcaddq_rot90_m_<supf><mode>" | |
3093 | [ | |
6debbff6 | 3094 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3095 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
3096 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3097 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3098 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3099 | VCADDQ_ROT90_M)) |
3100 | ] | |
3101 | "TARGET_HAVE_MVE" | |
3102 | "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90" | |
3103 | [(set_attr "type" "mve_move") | |
3104 | (set_attr "length""8")]) | |
3105 | ||
8eb3b6b9 | 3106 | ;; |
a7cbd5f9 CL |
3107 | ;; [vhaddq_m_n_s, vhaddq_m_n_u] |
3108 | ;; [vhsubq_m_n_s, vhsubq_m_n_u] | |
3109 | ;; [vmlaq_m_n_s, vmlaq_m_n_u] | |
3110 | ;; [vmlasq_m_n_u, vmlasq_m_n_s] | |
3111 | ;; [vqaddq_m_n_u, vqaddq_m_n_s] | |
3112 | ;; [vqdmlahq_m_n_s] | |
3113 | ;; [vqdmlashq_m_n_s] | |
3114 | ;; [vqdmulhq_m_n_s] | |
3115 | ;; [vqrdmlahq_m_n_s] | |
3116 | ;; [vqrdmlashq_m_n_s] | |
3117 | ;; [vqrdmulhq_m_n_s] | |
3118 | ;; [vqsubq_m_n_u, vqsubq_m_n_s] | |
8eb3b6b9 | 3119 | ;; |
a7cbd5f9 | 3120 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8eb3b6b9 SP |
3121 | [ |
3122 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3123 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3124 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3125 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3126 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
a7cbd5f9 | 3127 | MVE_INT_SU_M_N_BINARY)) |
8eb3b6b9 SP |
3128 | ] |
3129 | "TARGET_HAVE_MVE" | |
a7cbd5f9 | 3130 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3" |
8eb3b6b9 SP |
3131 | [(set_attr "type" "mve_move") |
3132 | (set_attr "length""8")]) | |
3133 | ||
3134 | ;; | |
8eb3b6b9 | 3135 | ;; |
1817749d CL |
3136 | ;; [vmladavaq_p_u, vmladavaq_p_s] |
3137 | ;; [vmladavaxq_p_s] | |
3138 | ;; [vmlsdavaq_p_s] | |
3139 | ;; [vmlsdavaxq_p_s] | |
8eb3b6b9 | 3140 | ;; |
1817749d | 3141 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
8eb3b6b9 | 3142 | [ |
3d537943 | 3143 | (set (match_operand:SI 0 "s_register_operand" "=Te") |
8eb3b6b9 SP |
3144 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") |
3145 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3146 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3147 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
1817749d | 3148 | MVE_VMLxDAVAQ_P)) |
8eb3b6b9 SP |
3149 | ] |
3150 | "TARGET_HAVE_MVE" | |
1817749d | 3151 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2, %q3" |
8eb3b6b9 SP |
3152 | [(set_attr "type" "mve_move") |
3153 | (set_attr "length""8")]) | |
3154 | ||
8eb3b6b9 SP |
3155 | ;; |
3156 | ;; [vmullbq_int_m_u, vmullbq_int_m_s]) | |
3157 | ;; | |
3158 | (define_insn "mve_vmullbq_int_m_<supf><mode>" | |
3159 | [ | |
6debbff6 | 3160 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3161 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3162 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3163 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3164 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3165 | VMULLBQ_INT_M)) |
3166 | ] | |
3167 | "TARGET_HAVE_MVE" | |
3168 | "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
3169 | [(set_attr "type" "mve_move") | |
3170 | (set_attr "length""8")]) | |
3171 | ||
3172 | ;; | |
3173 | ;; [vmulltq_int_m_s, vmulltq_int_m_u]) | |
3174 | ;; | |
3175 | (define_insn "mve_vmulltq_int_m_<supf><mode>" | |
3176 | [ | |
6debbff6 | 3177 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3178 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3179 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3180 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3181 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3182 | VMULLTQ_INT_M)) |
3183 | ] | |
3184 | "TARGET_HAVE_MVE" | |
3185 | "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3" | |
3186 | [(set_attr "type" "mve_move") | |
3187 | (set_attr "length""8")]) | |
3188 | ||
8eb3b6b9 SP |
3189 | ;; |
3190 | ;; [vornq_m_u, vornq_m_s]) | |
3191 | ;; | |
3192 | (define_insn "mve_vornq_m_<supf><mode>" | |
3193 | [ | |
3194 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3195 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3196 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3197 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3198 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3199 | VORNQ_M)) |
3200 | ] | |
3201 | "TARGET_HAVE_MVE" | |
3202 | "vpst\;vornt %q0, %q2, %q3" | |
3203 | [(set_attr "type" "mve_move") | |
3204 | (set_attr "length""8")]) | |
3205 | ||
8eb3b6b9 | 3206 | ;; |
7e6c39a3 CL |
3207 | ;; [vqshlq_m_n_s, vqshlq_m_n_u] |
3208 | ;; [vshlq_m_n_s, vshlq_m_n_u] | |
8eb3b6b9 | 3209 | ;; |
7e6c39a3 | 3210 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8eb3b6b9 SP |
3211 | [ |
3212 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3213 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3214 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3215 | (match_operand:SI 3 "immediate_operand" "i") | |
724d6566 | 3216 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
7e6c39a3 | 3217 | MVE_SHIFT_M_N)) |
8eb3b6b9 SP |
3218 | ] |
3219 | "TARGET_HAVE_MVE" | |
7e6c39a3 | 3220 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3" |
8eb3b6b9 SP |
3221 | [(set_attr "type" "mve_move") |
3222 | (set_attr "length""8")]) | |
3223 | ||
8eb3b6b9 SP |
3224 | ;; |
3225 | ;; [vrshrq_m_n_s, vrshrq_m_n_u]) | |
8eb3b6b9 SP |
3226 | ;; [vshrq_m_n_s, vshrq_m_n_u]) |
3227 | ;; | |
6bb8a5bd | 3228 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
8eb3b6b9 SP |
3229 | [ |
3230 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3231 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3232 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3233 | (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") | |
724d6566 | 3234 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
6bb8a5bd | 3235 | MVE_VSHRQ_M_N)) |
8eb3b6b9 SP |
3236 | ] |
3237 | "TARGET_HAVE_MVE" | |
6bb8a5bd | 3238 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3" |
8eb3b6b9 SP |
3239 | [(set_attr "type" "mve_move") |
3240 | (set_attr "length""8")]) | |
3241 | ||
3242 | ;; | |
3243 | ;; [vsliq_m_n_u, vsliq_m_n_s]) | |
3244 | ;; | |
3245 | (define_insn "mve_vsliq_m_n_<supf><mode>" | |
3246 | [ | |
3247 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3248 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
3249 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3250 | (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") | |
724d6566 | 3251 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3252 | VSLIQ_M_N)) |
3253 | ] | |
3254 | "TARGET_HAVE_MVE" | |
3255 | "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3" | |
3256 | [(set_attr "type" "mve_move") | |
3257 | (set_attr "length""8")]) | |
3258 | ||
8eb3b6b9 SP |
3259 | ;; |
3260 | ;; [vhcaddq_rot270_m_s]) | |
3261 | ;; | |
3262 | (define_insn "mve_vhcaddq_rot270_m_s<mode>" | |
3263 | [ | |
6debbff6 | 3264 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3265 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
3266 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3267 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3268 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3269 | VHCADDQ_ROT270_M_S)) |
3270 | ] | |
3271 | "TARGET_HAVE_MVE" | |
3272 | "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270" | |
3273 | [(set_attr "type" "mve_move") | |
3274 | (set_attr "length""8")]) | |
3275 | ||
3276 | ;; | |
3277 | ;; [vhcaddq_rot90_m_s]) | |
3278 | ;; | |
3279 | (define_insn "mve_vhcaddq_rot90_m_s<mode>" | |
3280 | [ | |
6debbff6 | 3281 | (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") |
8eb3b6b9 SP |
3282 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") |
3283 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3284 | (match_operand:MVE_2 3 "s_register_operand" "w") | |
724d6566 | 3285 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
8eb3b6b9 SP |
3286 | VHCADDQ_ROT90_M_S)) |
3287 | ] | |
3288 | "TARGET_HAVE_MVE" | |
3289 | "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90" | |
3290 | [(set_attr "type" "mve_move") | |
3291 | (set_attr "length""8")]) | |
3292 | ||
f2170a37 | 3293 | ;; |
c68ccdf2 CL |
3294 | ;; [vmlaldavaq_p_u, vmlaldavaq_p_s] |
3295 | ;; [vmlaldavaxq_p_s] | |
3296 | ;; [vmlsldavaq_p_s] | |
3297 | ;; [vmlsldavaxq_p_s] | |
f2170a37 | 3298 | ;; |
c68ccdf2 | 3299 | (define_insn "@mve_<mve_insn>q_p_<supf><mode>" |
f2170a37 SP |
3300 | [ |
3301 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3302 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3303 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3304 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
724d6566 | 3305 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
c68ccdf2 | 3306 | MVE_VMLxLDAVAxQ_P)) |
f2170a37 SP |
3307 | ] |
3308 | "TARGET_HAVE_MVE" | |
c68ccdf2 | 3309 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" |
f2170a37 SP |
3310 | [(set_attr "type" "mve_move") |
3311 | (set_attr "length""8")]) | |
3312 | ||
3313 | ;; | |
e2f992f7 CL |
3314 | ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s] |
3315 | ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u] | |
8f5b7d21 CL |
3316 | ;; [vqrshrunbq_m_n_s] |
3317 | ;; [vqrshruntq_m_n_s] | |
e2f992f7 CL |
3318 | ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s] |
3319 | ;; [vqshrntq_m_n_s, vqshrntq_m_n_u] | |
8f5b7d21 CL |
3320 | ;; [vqshrunbq_m_n_s] |
3321 | ;; [vqshruntq_m_n_s] | |
e2f992f7 CL |
3322 | ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s] |
3323 | ;; [vrshrntq_m_n_u, vrshrntq_m_n_s] | |
3324 | ;; [vshrnbq_m_n_s, vshrnbq_m_n_u] | |
3325 | ;; [vshrntq_m_n_s, vshrntq_m_n_u] | |
f2170a37 | 3326 | ;; |
e2f992f7 | 3327 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
f2170a37 SP |
3328 | [ |
3329 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
3330 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
e2f992f7 CL |
3331 | (match_operand:MVE_5 2 "s_register_operand" "w") |
3332 | (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") | |
3333 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] | |
3334 | MVE_SHRN_M_N)) | |
f2170a37 SP |
3335 | ] |
3336 | "TARGET_HAVE_MVE" | |
e2f992f7 | 3337 | "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %3" |
f2170a37 SP |
3338 | [(set_attr "type" "mve_move") |
3339 | (set_attr "length""8")]) | |
3340 | ||
3341 | ;; | |
3342 | ;; [vrmlaldavhaq_p_s]) | |
3343 | ;; | |
3344 | (define_insn "mve_vrmlaldavhaq_p_sv4si" | |
3345 | [ | |
3346 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3347 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3348 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3349 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 3350 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3351 | VRMLALDAVHAQ_P_S)) |
3352 | ] | |
3353 | "TARGET_HAVE_MVE" | |
3354 | "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3" | |
3355 | [(set_attr "type" "mve_move") | |
3356 | (set_attr "length""8")]) | |
3357 | ||
f2170a37 | 3358 | ;; |
2cc50fd9 CL |
3359 | ;; [vshllbq_m_n_u, vshllbq_m_n_s] |
3360 | ;; [vshlltq_m_n_u, vshlltq_m_n_s] | |
f2170a37 | 3361 | ;; |
2cc50fd9 | 3362 | (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" |
f2170a37 SP |
3363 | [ |
3364 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3365 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
3366 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
3367 | (match_operand:SI 3 "immediate_operand" "i") | |
724d6566 | 3368 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
2cc50fd9 | 3369 | VSHLLxQ_M_N)) |
f2170a37 SP |
3370 | ] |
3371 | "TARGET_HAVE_MVE" | |
2cc50fd9 | 3372 | "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3" |
f2170a37 SP |
3373 | [(set_attr "type" "mve_move") |
3374 | (set_attr "length""8")]) | |
f2170a37 | 3375 | |
f2170a37 SP |
3376 | ;; |
3377 | ;; [vmullbq_poly_m_p]) | |
3378 | ;; | |
3379 | (define_insn "mve_vmullbq_poly_m_p<mode>" | |
3380 | [ | |
3381 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3382 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
3383 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
3384 | (match_operand:MVE_3 3 "s_register_operand" "w") | |
724d6566 | 3385 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3386 | VMULLBQ_POLY_M_P)) |
3387 | ] | |
3388 | "TARGET_HAVE_MVE" | |
3389 | "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3" | |
3390 | [(set_attr "type" "mve_move") | |
3391 | (set_attr "length""8")]) | |
3392 | ||
3393 | ;; | |
3394 | ;; [vmulltq_poly_m_p]) | |
3395 | ;; | |
3396 | (define_insn "mve_vmulltq_poly_m_p<mode>" | |
3397 | [ | |
3398 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3399 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") | |
3400 | (match_operand:MVE_3 2 "s_register_operand" "w") | |
3401 | (match_operand:MVE_3 3 "s_register_operand" "w") | |
724d6566 | 3402 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3403 | VMULLTQ_POLY_M_P)) |
3404 | ] | |
3405 | "TARGET_HAVE_MVE" | |
3406 | "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3" | |
3407 | [(set_attr "type" "mve_move") | |
3408 | (set_attr "length""8")]) | |
3409 | ||
3410 | ;; | |
3411 | ;; [vqdmullbq_m_n_s]) | |
3412 | ;; | |
3413 | (define_insn "mve_vqdmullbq_m_n_s<mode>" | |
3414 | [ | |
6debbff6 | 3415 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
3416 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3417 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3418 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3419 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3420 | VQDMULLBQ_M_N_S)) |
3421 | ] | |
3422 | "TARGET_HAVE_MVE" | |
3423 | "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3424 | [(set_attr "type" "mve_move") | |
3425 | (set_attr "length""8")]) | |
3426 | ||
3427 | ;; | |
3428 | ;; [vqdmullbq_m_s]) | |
3429 | ;; | |
3430 | (define_insn "mve_vqdmullbq_m_s<mode>" | |
3431 | [ | |
6debbff6 | 3432 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
3433 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3434 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3435 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
724d6566 | 3436 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3437 | VQDMULLBQ_M_S)) |
3438 | ] | |
3439 | "TARGET_HAVE_MVE" | |
3440 | "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3441 | [(set_attr "type" "mve_move") | |
3442 | (set_attr "length""8")]) | |
3443 | ||
3444 | ;; | |
3445 | ;; [vqdmulltq_m_n_s]) | |
3446 | ;; | |
3447 | (define_insn "mve_vqdmulltq_m_n_s<mode>" | |
3448 | [ | |
6debbff6 | 3449 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
3450 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3451 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3452 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3453 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3454 | VQDMULLTQ_M_N_S)) |
3455 | ] | |
3456 | "TARGET_HAVE_MVE" | |
3457 | "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3458 | [(set_attr "type" "mve_move") | |
3459 | (set_attr "length""8")]) | |
3460 | ||
3461 | ;; | |
3462 | ;; [vqdmulltq_m_s]) | |
3463 | ;; | |
3464 | (define_insn "mve_vqdmulltq_m_s<mode>" | |
3465 | [ | |
6debbff6 | 3466 | (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") |
f2170a37 SP |
3467 | (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") |
3468 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3469 | (match_operand:MVE_5 3 "s_register_operand" "w") | |
724d6566 | 3470 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3471 | VQDMULLTQ_M_S)) |
3472 | ] | |
3473 | "TARGET_HAVE_MVE" | |
3474 | "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3" | |
3475 | [(set_attr "type" "mve_move") | |
3476 | (set_attr "length""8")]) | |
3477 | ||
f2170a37 SP |
3478 | ;; |
3479 | ;; [vrmlaldavhaq_p_u]) | |
3480 | ;; | |
3481 | (define_insn "mve_vrmlaldavhaq_p_uv4si" | |
3482 | [ | |
3483 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3484 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3485 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3486 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 3487 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3488 | VRMLALDAVHAQ_P_U)) |
3489 | ] | |
3490 | "TARGET_HAVE_MVE" | |
3491 | "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3" | |
3492 | [(set_attr "type" "mve_move") | |
3493 | (set_attr "length""8")]) | |
3494 | ||
3495 | ;; | |
3496 | ;; [vrmlaldavhaxq_p_s]) | |
3497 | ;; | |
3498 | (define_insn "mve_vrmlaldavhaxq_p_sv4si" | |
3499 | [ | |
3500 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3501 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3502 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3503 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 3504 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3505 | VRMLALDAVHAXQ_P_S)) |
3506 | ] | |
3507 | "TARGET_HAVE_MVE" | |
3508 | "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3" | |
3509 | [(set_attr "type" "mve_move") | |
3510 | (set_attr "length""8")]) | |
3511 | ||
3512 | ;; | |
3513 | ;; [vrmlsldavhaq_p_s]) | |
3514 | ;; | |
3515 | (define_insn "mve_vrmlsldavhaq_p_sv4si" | |
3516 | [ | |
3517 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3518 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3519 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3520 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 3521 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3522 | VRMLSLDAVHAQ_P_S)) |
3523 | ] | |
3524 | "TARGET_HAVE_MVE" | |
3525 | "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3" | |
3526 | [(set_attr "type" "mve_move") | |
3527 | (set_attr "length""8")]) | |
3528 | ||
3529 | ;; | |
3530 | ;; [vrmlsldavhaxq_p_s]) | |
3531 | ;; | |
3532 | (define_insn "mve_vrmlsldavhaxq_p_sv4si" | |
3533 | [ | |
3534 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3535 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3536 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3537 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 3538 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
f2170a37 SP |
3539 | VRMLSLDAVHAXQ_P_S)) |
3540 | ] | |
3541 | "TARGET_HAVE_MVE" | |
3542 | "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" | |
3543 | [(set_attr "type" "mve_move") | |
3544 | (set_attr "length""8")]) | |
532e9e24 SP |
3545 | |
3546 | ;; | |
1736f4af | 3547 | ;; [vabdq_m_f] |
b0b3a5e9 | 3548 | ;; [vaddq_m_f] |
5ea7a47c CL |
3549 | ;; [vmaxnmq_m_f] |
3550 | ;; [vminnmq_m_f] | |
b0b3a5e9 | 3551 | ;; [vmulq_m_f] |
5ea7a47c | 3552 | ;; [vsubq_m_f] |
532e9e24 | 3553 | ;; |
b0b3a5e9 | 3554 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
532e9e24 SP |
3555 | [ |
3556 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3557 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3558 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3559 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3560 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
b0b3a5e9 | 3561 | MVE_FP_M_BINARY)) |
532e9e24 SP |
3562 | ] |
3563 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
b0b3a5e9 | 3564 | "vpst\;<mve_insn>t.f%#<V_sz_elem> %q0, %q2, %q3" |
532e9e24 SP |
3565 | [(set_attr "type" "mve_move") |
3566 | (set_attr "length""8")]) | |
3567 | ||
3568 | ;; | |
b0b3a5e9 CL |
3569 | ;; [vaddq_m_n_f] |
3570 | ;; [vsubq_m_n_f] | |
3571 | ;; [vmulq_m_n_f] | |
532e9e24 | 3572 | ;; |
b0b3a5e9 | 3573 | (define_insn "@mve_<mve_insn>q_m_n_f<mode>" |
532e9e24 SP |
3574 | [ |
3575 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3576 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3577 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3578 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3579 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
b0b3a5e9 | 3580 | MVE_FP_M_N_BINARY)) |
532e9e24 SP |
3581 | ] |
3582 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
b0b3a5e9 | 3583 | "vpst\;<mve_insn>t.f%#<V_sz_elem> %q0, %q2, %3" |
532e9e24 SP |
3584 | [(set_attr "type" "mve_move") |
3585 | (set_attr "length""8")]) | |
3586 | ||
3587 | ;; | |
67e4e591 CL |
3588 | ;; [vandq_m_f] |
3589 | ;; [vbicq_m_f] | |
3590 | ;; [veorq_m_f] | |
3591 | ;; [vorrq_m_f] | |
532e9e24 | 3592 | ;; |
67e4e591 | 3593 | (define_insn "@mve_<mve_insn>q_m_f<mode>" |
532e9e24 SP |
3594 | [ |
3595 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3596 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3597 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3598 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3599 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
67e4e591 | 3600 | MVE_FP_M_BINARY_LOGIC)) |
532e9e24 SP |
3601 | ] |
3602 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
67e4e591 | 3603 | "vpst\;<mve_insn>t %q0, %q2, %q3" |
532e9e24 SP |
3604 | [(set_attr "type" "mve_move") |
3605 | (set_attr "length""8")]) | |
3606 | ||
3607 | ;; | |
3608 | ;; [vbrsrq_m_n_f]) | |
3609 | ;; | |
3610 | (define_insn "mve_vbrsrq_m_n_f<mode>" | |
3611 | [ | |
3612 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3613 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3614 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3615 | (match_operand:SI 3 "s_register_operand" "r") | |
724d6566 | 3616 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3617 | VBRSRQ_M_N_F)) |
3618 | ] | |
3619 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3620 | "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" | |
3621 | [(set_attr "type" "mve_move") | |
3622 | (set_attr "length""8")]) | |
3623 | ||
3624 | ;; | |
3625 | ;; [vcaddq_rot270_m_f]) | |
3626 | ;; | |
3627 | (define_insn "mve_vcaddq_rot270_m_f<mode>" | |
3628 | [ | |
6debbff6 | 3629 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3630 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3631 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3632 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3633 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3634 | VCADDQ_ROT270_M_F)) |
3635 | ] | |
3636 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3637 | "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
3638 | [(set_attr "type" "mve_move") | |
3639 | (set_attr "length""8")]) | |
3640 | ||
3641 | ;; | |
3642 | ;; [vcaddq_rot90_m_f]) | |
3643 | ;; | |
3644 | (define_insn "mve_vcaddq_rot90_m_f<mode>" | |
3645 | [ | |
6debbff6 | 3646 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3647 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3648 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3649 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3650 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3651 | VCADDQ_ROT90_M_F)) |
3652 | ] | |
3653 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3654 | "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
3655 | [(set_attr "type" "mve_move") | |
3656 | (set_attr "length""8")]) | |
3657 | ||
3658 | ;; | |
3659 | ;; [vcmlaq_m_f]) | |
3660 | ;; | |
3661 | (define_insn "mve_vcmlaq_m_f<mode>" | |
3662 | [ | |
3663 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3664 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3665 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3666 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3667 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3668 | VCMLAQ_M_F)) |
3669 | ] | |
3670 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3671 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0" | |
3672 | [(set_attr "type" "mve_move") | |
3673 | (set_attr "length""8")]) | |
3674 | ||
3675 | ;; | |
3676 | ;; [vcmlaq_rot180_m_f]) | |
3677 | ;; | |
3678 | (define_insn "mve_vcmlaq_rot180_m_f<mode>" | |
3679 | [ | |
3680 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3681 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3682 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3683 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3684 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3685 | VCMLAQ_ROT180_M_F)) |
3686 | ] | |
3687 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3688 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180" | |
3689 | [(set_attr "type" "mve_move") | |
3690 | (set_attr "length""8")]) | |
3691 | ||
3692 | ;; | |
3693 | ;; [vcmlaq_rot270_m_f]) | |
3694 | ;; | |
3695 | (define_insn "mve_vcmlaq_rot270_m_f<mode>" | |
3696 | [ | |
3697 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3698 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3699 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3700 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3701 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3702 | VCMLAQ_ROT270_M_F)) |
3703 | ] | |
3704 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3705 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
3706 | [(set_attr "type" "mve_move") | |
3707 | (set_attr "length""8")]) | |
3708 | ||
3709 | ;; | |
3710 | ;; [vcmlaq_rot90_m_f]) | |
3711 | ;; | |
3712 | (define_insn "mve_vcmlaq_rot90_m_f<mode>" | |
3713 | [ | |
3714 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3715 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3716 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3717 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3718 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3719 | VCMLAQ_ROT90_M_F)) |
3720 | ] | |
3721 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3722 | "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
3723 | [(set_attr "type" "mve_move") | |
3724 | (set_attr "length""8")]) | |
3725 | ||
3726 | ;; | |
3727 | ;; [vcmulq_m_f]) | |
3728 | ;; | |
3729 | (define_insn "mve_vcmulq_m_f<mode>" | |
3730 | [ | |
6debbff6 | 3731 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3732 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3733 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3734 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3735 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3736 | VCMULQ_M_F)) |
3737 | ] | |
3738 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3739 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0" | |
3740 | [(set_attr "type" "mve_move") | |
3741 | (set_attr "length""8")]) | |
3742 | ||
3743 | ;; | |
3744 | ;; [vcmulq_rot180_m_f]) | |
3745 | ;; | |
3746 | (define_insn "mve_vcmulq_rot180_m_f<mode>" | |
3747 | [ | |
6debbff6 | 3748 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3749 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3750 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3751 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3752 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3753 | VCMULQ_ROT180_M_F)) |
3754 | ] | |
3755 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3756 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180" | |
3757 | [(set_attr "type" "mve_move") | |
3758 | (set_attr "length""8")]) | |
3759 | ||
3760 | ;; | |
3761 | ;; [vcmulq_rot270_m_f]) | |
3762 | ;; | |
3763 | (define_insn "mve_vcmulq_rot270_m_f<mode>" | |
3764 | [ | |
6debbff6 | 3765 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3766 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3767 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3768 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3769 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3770 | VCMULQ_ROT270_M_F)) |
3771 | ] | |
3772 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3773 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270" | |
3774 | [(set_attr "type" "mve_move") | |
3775 | (set_attr "length""8")]) | |
3776 | ||
3777 | ;; | |
3778 | ;; [vcmulq_rot90_m_f]) | |
3779 | ;; | |
3780 | (define_insn "mve_vcmulq_rot90_m_f<mode>" | |
3781 | [ | |
6debbff6 | 3782 | (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") |
532e9e24 SP |
3783 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") |
3784 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3785 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3786 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3787 | VCMULQ_ROT90_M_F)) |
3788 | ] | |
3789 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3790 | "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90" | |
3791 | [(set_attr "type" "mve_move") | |
3792 | (set_attr "length""8")]) | |
3793 | ||
532e9e24 SP |
3794 | ;; |
3795 | ;; [vfmaq_m_f]) | |
3796 | ;; | |
3797 | (define_insn "mve_vfmaq_m_f<mode>" | |
3798 | [ | |
3799 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3800 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3801 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3802 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3803 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3804 | VFMAQ_M_F)) |
3805 | ] | |
3806 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3807 | "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3" | |
3808 | [(set_attr "type" "mve_move") | |
3809 | (set_attr "length""8")]) | |
3810 | ||
3811 | ;; | |
3812 | ;; [vfmaq_m_n_f]) | |
3813 | ;; | |
3814 | (define_insn "mve_vfmaq_m_n_f<mode>" | |
3815 | [ | |
3816 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3817 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3818 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3819 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3820 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3821 | VFMAQ_M_N_F)) |
3822 | ] | |
3823 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3824 | "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3" | |
3825 | [(set_attr "type" "mve_move") | |
3826 | (set_attr "length""8")]) | |
3827 | ||
3828 | ;; | |
3829 | ;; [vfmasq_m_n_f]) | |
3830 | ;; | |
3831 | (define_insn "mve_vfmasq_m_n_f<mode>" | |
3832 | [ | |
3833 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3834 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3835 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3836 | (match_operand:<V_elem> 3 "s_register_operand" "r") | |
724d6566 | 3837 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3838 | VFMASQ_M_N_F)) |
3839 | ] | |
3840 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3841 | "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3" | |
3842 | [(set_attr "type" "mve_move") | |
3843 | (set_attr "length""8")]) | |
3844 | ||
3845 | ;; | |
3846 | ;; [vfmsq_m_f]) | |
3847 | ;; | |
3848 | (define_insn "mve_vfmsq_m_f<mode>" | |
3849 | [ | |
3850 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3851 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3852 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3853 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3854 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3855 | VFMSQ_M_F)) |
3856 | ] | |
3857 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3858 | "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3" | |
3859 | [(set_attr "type" "mve_move") | |
3860 | (set_attr "length""8")]) | |
3861 | ||
532e9e24 SP |
3862 | ;; |
3863 | ;; [vornq_m_f]) | |
3864 | ;; | |
3865 | (define_insn "mve_vornq_m_f<mode>" | |
3866 | [ | |
3867 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3868 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3869 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3870 | (match_operand:MVE_0 3 "s_register_operand" "w") | |
724d6566 | 3871 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] |
532e9e24 SP |
3872 | VORNQ_M_F)) |
3873 | ] | |
3874 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3875 | "vpst\;vornt %q0, %q2, %q3" | |
3876 | [(set_attr "type" "mve_move") | |
3877 | (set_attr "length""8")]) | |
3878 | ||
4ff68575 SP |
3879 | ;; |
3880 | ;; [vstrbq_s vstrbq_u] | |
3881 | ;; | |
3882 | (define_insn "mve_vstrbq_<supf><mode>" | |
d91524d5 | 3883 | [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") |
4ff68575 SP |
3884 | (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")] |
3885 | VSTRBQ)) | |
3886 | ] | |
3887 | "TARGET_HAVE_MVE" | |
3888 | { | |
3889 | rtx ops[2]; | |
3890 | int regno = REGNO (operands[1]); | |
3891 | ops[1] = gen_rtx_REG (TImode, regno); | |
3892 | ops[0] = operands[0]; | |
3893 | output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops); | |
3894 | return ""; | |
3895 | } | |
3896 | [(set_attr "length" "4")]) | |
3897 | ||
3898 | ;; | |
3899 | ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] | |
3900 | ;; | |
9a810e57 SP |
3901 | (define_expand "mve_vstrbq_scatter_offset_<supf><mode>" |
3902 | [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") | |
3903 | (match_operand:MVE_2 1 "s_register_operand") | |
3904 | (match_operand:MVE_2 2 "s_register_operand") | |
3905 | (unspec:V4SI [(const_int 0)] VSTRBSOQ)] | |
4ff68575 SP |
3906 | "TARGET_HAVE_MVE" |
3907 | { | |
9a810e57 SP |
3908 | rtx ind = XEXP (operands[0], 0); |
3909 | gcc_assert (REG_P (ind)); | |
3910 | emit_insn (gen_mve_vstrbq_scatter_offset_<supf><mode>_insn (ind, operands[1], | |
3911 | operands[2])); | |
3912 | DONE; | |
3913 | }) | |
3914 | ||
3915 | (define_insn "mve_vstrbq_scatter_offset_<supf><mode>_insn" | |
3916 | [(set (mem:BLK (scratch)) | |
3917 | (unspec:BLK | |
3918 | [(match_operand:SI 0 "register_operand" "r") | |
3919 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
3920 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
3921 | VSTRBSOQ))] | |
3922 | "TARGET_HAVE_MVE" | |
3923 | "vstrb.<V_sz_elem>\t%q2, [%0, %q1]" | |
4ff68575 SP |
3924 | [(set_attr "length" "4")]) |
3925 | ||
3926 | ;; | |
3927 | ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] | |
3928 | ;; | |
3929 | (define_insn "mve_vstrwq_scatter_base_<supf>v4si" | |
3930 | [(set (mem:BLK (scratch)) | |
3931 | (unspec:BLK | |
3932 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
3933 | (match_operand:SI 1 "immediate_operand" "i") | |
3934 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
3935 | VSTRWSBQ)) | |
3936 | ] | |
3937 | "TARGET_HAVE_MVE" | |
3938 | { | |
3939 | rtx ops[3]; | |
3940 | ops[0] = operands[0]; | |
3941 | ops[1] = operands[1]; | |
3942 | ops[2] = operands[2]; | |
3943 | output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); | |
3944 | return ""; | |
3945 | } | |
3946 | [(set_attr "length" "4")]) | |
535a8645 SP |
3947 | |
3948 | ;; | |
3949 | ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] | |
3950 | ;; | |
3951 | (define_insn "mve_vldrbq_gather_offset_<supf><mode>" | |
3952 | [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") | |
3953 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") | |
3954 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
3955 | VLDRBGOQ)) | |
3956 | ] | |
3957 | "TARGET_HAVE_MVE" | |
3958 | { | |
3959 | rtx ops[3]; | |
3960 | ops[0] = operands[0]; | |
3961 | ops[1] = operands[1]; | |
3962 | ops[2] = operands[2]; | |
3963 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) | |
3964 | output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops); | |
3965 | else | |
3966 | output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
3967 | return ""; | |
3968 | } | |
3969 | [(set_attr "length" "4")]) | |
3970 | ||
3971 | ;; | |
3972 | ;; [vldrbq_s vldrbq_u] | |
3973 | ;; | |
3974 | (define_insn "mve_vldrbq_<supf><mode>" | |
3975 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
d91524d5 | 3976 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")] |
535a8645 SP |
3977 | VLDRBQ)) |
3978 | ] | |
3979 | "TARGET_HAVE_MVE" | |
3980 | { | |
3981 | rtx ops[2]; | |
3982 | int regno = REGNO (operands[0]); | |
3983 | ops[0] = gen_rtx_REG (TImode, regno); | |
3984 | ops[1] = operands[1]; | |
d91524d5 SP |
3985 | if (<V_sz_elem> == 8) |
3986 | output_asm_insn ("vldrb.<V_sz_elem>\t%q0, %E1",ops); | |
3987 | else | |
3988 | output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops); | |
535a8645 SP |
3989 | return ""; |
3990 | } | |
3991 | [(set_attr "length" "4")]) | |
3992 | ||
3993 | ;; | |
3994 | ;; [vldrwq_gather_base_s vldrwq_gather_base_u] | |
3995 | ;; | |
3996 | (define_insn "mve_vldrwq_gather_base_<supf>v4si" | |
3997 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
3998 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
3999 | (match_operand:SI 2 "immediate_operand" "i")] | |
4000 | VLDRWGBQ)) | |
4001 | ] | |
4002 | "TARGET_HAVE_MVE" | |
4003 | { | |
4004 | rtx ops[3]; | |
4005 | ops[0] = operands[0]; | |
4006 | ops[1] = operands[1]; | |
4007 | ops[2] = operands[2]; | |
4008 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); | |
4009 | return ""; | |
4010 | } | |
4011 | [(set_attr "length" "4")]) | |
405e918c SP |
4012 | |
4013 | ;; | |
4014 | ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u] | |
4015 | ;; | |
9a810e57 SP |
4016 | (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>" |
4017 | [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") | |
4018 | (match_operand:MVE_2 1 "s_register_operand") | |
4019 | (match_operand:MVE_2 2 "s_register_operand") | |
724d6566 | 4020 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") |
9a810e57 | 4021 | (unspec:V4SI [(const_int 0)] VSTRBSOQ)] |
405e918c SP |
4022 | "TARGET_HAVE_MVE" |
4023 | { | |
9a810e57 SP |
4024 | rtx ind = XEXP (operands[0], 0); |
4025 | gcc_assert (REG_P (ind)); | |
4026 | emit_insn ( | |
4027 | gen_mve_vstrbq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], | |
4028 | operands[2], | |
4029 | operands[3])); | |
4030 | DONE; | |
4031 | }) | |
4032 | ||
4033 | (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn" | |
4034 | [(set (mem:BLK (scratch)) | |
4035 | (unspec:BLK | |
4036 | [(match_operand:SI 0 "register_operand" "r") | |
4037 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
4038 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 4039 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
4040 | VSTRBSOQ))] |
4041 | "TARGET_HAVE_MVE" | |
4042 | "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]" | |
405e918c SP |
4043 | [(set_attr "length" "8")]) |
4044 | ||
4045 | ;; | |
4046 | ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u] | |
4047 | ;; | |
4048 | (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" | |
4049 | [(set (mem:BLK (scratch)) | |
4050 | (unspec:BLK | |
4051 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
4052 | (match_operand:SI 1 "immediate_operand" "i") | |
4053 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 4054 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
405e918c SP |
4055 | VSTRWSBQ)) |
4056 | ] | |
4057 | "TARGET_HAVE_MVE" | |
4058 | { | |
4059 | rtx ops[3]; | |
4060 | ops[0] = operands[0]; | |
4061 | ops[1] = operands[1]; | |
4062 | ops[2] = operands[2]; | |
4063 | output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); | |
4064 | return ""; | |
4065 | } | |
4066 | [(set_attr "length" "8")]) | |
4067 | ||
405e918c | 4068 | (define_insn "mve_vstrbq_p_<supf><mode>" |
d91524d5 | 4069 | [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") |
c1093923 AV |
4070 | (unspec:<MVE_B_ELEM> |
4071 | [(match_operand:MVE_2 1 "s_register_operand" "w") | |
4072 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") | |
4073 | (match_dup 0)] | |
4074 | VSTRBQ))] | |
405e918c SP |
4075 | "TARGET_HAVE_MVE" |
4076 | { | |
4077 | rtx ops[2]; | |
4078 | int regno = REGNO (operands[1]); | |
4079 | ops[1] = gen_rtx_REG (TImode, regno); | |
4080 | ops[0] = operands[0]; | |
d91524d5 | 4081 | output_asm_insn ("vpst\;vstrbt.<V_sz_elem>\t%q1, %E0",ops); |
405e918c SP |
4082 | return ""; |
4083 | } | |
4084 | [(set_attr "length" "8")]) | |
429d607b SP |
4085 | |
4086 | ;; | |
4087 | ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] | |
4088 | ;; | |
4089 | (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" | |
4090 | [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") | |
4091 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") | |
4092 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
724d6566 | 4093 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
429d607b SP |
4094 | VLDRBGOQ)) |
4095 | ] | |
4096 | "TARGET_HAVE_MVE" | |
4097 | { | |
4098 | rtx ops[4]; | |
4099 | ops[0] = operands[0]; | |
4100 | ops[1] = operands[1]; | |
4101 | ops[2] = operands[2]; | |
4102 | ops[3] = operands[3]; | |
4103 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) | |
4104 | output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops); | |
4105 | else | |
4106 | output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
4107 | return ""; | |
4108 | } | |
4109 | [(set_attr "length" "8")]) | |
4110 | ||
4111 | ;; | |
4112 | ;; [vldrbq_z_s vldrbq_z_u] | |
4113 | ;; | |
4114 | (define_insn "mve_vldrbq_z_<supf><mode>" | |
4115 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
d91524d5 | 4116 | (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux") |
724d6566 | 4117 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] |
429d607b SP |
4118 | VLDRBQ)) |
4119 | ] | |
4120 | "TARGET_HAVE_MVE" | |
4121 | { | |
4122 | rtx ops[2]; | |
4123 | int regno = REGNO (operands[0]); | |
4124 | ops[0] = gen_rtx_REG (TImode, regno); | |
4125 | ops[1] = operands[1]; | |
d91524d5 SP |
4126 | if (<V_sz_elem> == 8) |
4127 | output_asm_insn ("vpst\;vldrbt.<V_sz_elem>\t%q0, %E1",ops); | |
4128 | else | |
4129 | output_asm_insn ("vpst\;vldrbt.<supf><V_sz_elem>\t%q0, %E1",ops); | |
429d607b SP |
4130 | return ""; |
4131 | } | |
4132 | [(set_attr "length" "8")]) | |
4133 | ||
4134 | ;; | |
4135 | ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] | |
4136 | ;; | |
4137 | (define_insn "mve_vldrwq_gather_base_z_<supf>v4si" | |
4138 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
4139 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
4140 | (match_operand:SI 2 "immediate_operand" "i") | |
6a7c13a0 | 4141 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
429d607b SP |
4142 | VLDRWGBQ)) |
4143 | ] | |
4144 | "TARGET_HAVE_MVE" | |
4145 | { | |
4146 | rtx ops[3]; | |
4147 | ops[0] = operands[0]; | |
4148 | ops[1] = operands[1]; | |
4149 | ops[2] = operands[2]; | |
4150 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); | |
4151 | return ""; | |
4152 | } | |
4153 | [(set_attr "length" "8")]) | |
bf1e3d5a SP |
4154 | |
4155 | ;; | |
4156 | ;; [vldrhq_f] | |
4157 | ;; | |
4158 | (define_insn "mve_vldrhq_fv8hf" | |
4159 | [(set (match_operand:V8HF 0 "s_register_operand" "=w") | |
d91524d5 | 4160 | (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
4161 | VLDRHQ_F)) |
4162 | ] | |
4163 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4164 | { | |
4165 | rtx ops[2]; | |
4166 | int regno = REGNO (operands[0]); | |
4167 | ops[0] = gen_rtx_REG (TImode, regno); | |
4168 | ops[1] = operands[1]; | |
d91524d5 | 4169 | output_asm_insn ("vldrh.16\t%q0, %E1",ops); |
bf1e3d5a SP |
4170 | return ""; |
4171 | } | |
4172 | [(set_attr "length" "4")]) | |
4173 | ||
4174 | ;; | |
4175 | ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] | |
4176 | ;; | |
4177 | (define_insn "mve_vldrhq_gather_offset_<supf><mode>" | |
4178 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
4179 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
4180 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
4181 | VLDRHGOQ)) | |
4182 | ] | |
4183 | "TARGET_HAVE_MVE" | |
4184 | { | |
4185 | rtx ops[3]; | |
4186 | ops[0] = operands[0]; | |
4187 | ops[1] = operands[1]; | |
4188 | ops[2] = operands[2]; | |
4189 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
4190 | output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops); | |
4191 | else | |
4192 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
4193 | return ""; | |
4194 | } | |
4195 | [(set_attr "length" "4")]) | |
4196 | ||
4197 | ;; | |
4198 | ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] | |
4199 | ;; | |
4200 | (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>" | |
4201 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
4202 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
4203 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
724d6566 | 4204 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") |
bf1e3d5a SP |
4205 | ]VLDRHGOQ)) |
4206 | ] | |
4207 | "TARGET_HAVE_MVE" | |
4208 | { | |
4209 | rtx ops[4]; | |
4210 | ops[0] = operands[0]; | |
4211 | ops[1] = operands[1]; | |
4212 | ops[2] = operands[2]; | |
4213 | ops[3] = operands[3]; | |
4214 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
4215 | output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops); | |
4216 | else | |
4217 | output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); | |
4218 | return ""; | |
4219 | } | |
4220 | [(set_attr "length" "8")]) | |
4221 | ||
4222 | ;; | |
4223 | ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] | |
4224 | ;; | |
4225 | (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>" | |
4226 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
4227 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
4228 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
4229 | VLDRHGSOQ)) | |
4230 | ] | |
4231 | "TARGET_HAVE_MVE" | |
4232 | { | |
4233 | rtx ops[3]; | |
4234 | ops[0] = operands[0]; | |
4235 | ops[1] = operands[1]; | |
4236 | ops[2] = operands[2]; | |
4237 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
4238 | output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4239 | else | |
4240 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4241 | return ""; | |
4242 | } | |
4243 | [(set_attr "length" "4")]) | |
4244 | ||
4245 | ;; | |
4246 | ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] | |
4247 | ;; | |
4248 | (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>" | |
4249 | [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") | |
4250 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") | |
4251 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
724d6566 | 4252 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") |
bf1e3d5a SP |
4253 | ]VLDRHGSOQ)) |
4254 | ] | |
4255 | "TARGET_HAVE_MVE" | |
4256 | { | |
4257 | rtx ops[4]; | |
4258 | ops[0] = operands[0]; | |
4259 | ops[1] = operands[1]; | |
4260 | ops[2] = operands[2]; | |
4261 | ops[3] = operands[3]; | |
4262 | if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) | |
4263 | output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4264 | else | |
4265 | output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4266 | return ""; | |
4267 | } | |
4268 | [(set_attr "length" "8")]) | |
4269 | ||
bf1e3d5a SP |
4270 | ;; |
4271 | ;; [vldrhq_s, vldrhq_u] | |
4272 | ;; | |
4273 | (define_insn "mve_vldrhq_<supf><mode>" | |
4274 | [(set (match_operand:MVE_6 0 "s_register_operand" "=w") | |
d91524d5 | 4275 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
4276 | VLDRHQ)) |
4277 | ] | |
4278 | "TARGET_HAVE_MVE" | |
4279 | { | |
4280 | rtx ops[2]; | |
4281 | int regno = REGNO (operands[0]); | |
4282 | ops[0] = gen_rtx_REG (TImode, regno); | |
4283 | ops[1] = operands[1]; | |
d91524d5 SP |
4284 | if (<V_sz_elem> == 16) |
4285 | output_asm_insn ("vldrh.16\t%q0, %E1",ops); | |
4286 | else | |
4287 | output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops); | |
bf1e3d5a SP |
4288 | return ""; |
4289 | } | |
4290 | [(set_attr "length" "4")]) | |
4291 | ||
4292 | ;; | |
4293 | ;; [vldrhq_z_f] | |
4294 | ;; | |
4295 | (define_insn "mve_vldrhq_z_fv8hf" | |
4296 | [(set (match_operand:V8HF 0 "s_register_operand" "=w") | |
d91524d5 | 4297 | (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux") |
c6b4ea7a | 4298 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] |
bf1e3d5a SP |
4299 | VLDRHQ_F)) |
4300 | ] | |
4301 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4302 | { | |
4303 | rtx ops[2]; | |
4304 | int regno = REGNO (operands[0]); | |
4305 | ops[0] = gen_rtx_REG (TImode, regno); | |
4306 | ops[1] = operands[1]; | |
d91524d5 | 4307 | output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); |
bf1e3d5a SP |
4308 | return ""; |
4309 | } | |
4310 | [(set_attr "length" "8")]) | |
4311 | ||
4312 | ;; | |
4313 | ;; [vldrhq_z_s vldrhq_z_u] | |
4314 | ;; | |
4315 | (define_insn "mve_vldrhq_z_<supf><mode>" | |
4316 | [(set (match_operand:MVE_6 0 "s_register_operand" "=w") | |
d91524d5 | 4317 | (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux") |
724d6566 | 4318 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] |
bf1e3d5a SP |
4319 | VLDRHQ)) |
4320 | ] | |
4321 | "TARGET_HAVE_MVE" | |
4322 | { | |
4323 | rtx ops[2]; | |
4324 | int regno = REGNO (operands[0]); | |
4325 | ops[0] = gen_rtx_REG (TImode, regno); | |
4326 | ops[1] = operands[1]; | |
d91524d5 SP |
4327 | if (<V_sz_elem> == 16) |
4328 | output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); | |
4329 | else | |
4330 | output_asm_insn ("vpst\;vldrht.<supf><V_sz_elem>\t%q0, %E1",ops); | |
bf1e3d5a SP |
4331 | return ""; |
4332 | } | |
4333 | [(set_attr "length" "8")]) | |
4334 | ||
4335 | ;; | |
4336 | ;; [vldrwq_f] | |
4337 | ;; | |
4338 | (define_insn "mve_vldrwq_fv4sf" | |
4339 | [(set (match_operand:V4SF 0 "s_register_operand" "=w") | |
5efeaa0d | 4340 | (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
4341 | VLDRWQ_F)) |
4342 | ] | |
4343 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4344 | { | |
4345 | rtx ops[2]; | |
4346 | int regno = REGNO (operands[0]); | |
4347 | ops[0] = gen_rtx_REG (TImode, regno); | |
4348 | ops[1] = operands[1]; | |
d91524d5 | 4349 | output_asm_insn ("vldrw.32\t%q0, %E1",ops); |
bf1e3d5a SP |
4350 | return ""; |
4351 | } | |
4352 | [(set_attr "length" "4")]) | |
4353 | ||
4354 | ;; | |
4355 | ;; [vldrwq_s vldrwq_u] | |
4356 | ;; | |
4357 | (define_insn "mve_vldrwq_<supf>v4si" | |
4358 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
5efeaa0d | 4359 | (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")] |
bf1e3d5a SP |
4360 | VLDRWQ)) |
4361 | ] | |
4362 | "TARGET_HAVE_MVE" | |
4363 | { | |
4364 | rtx ops[2]; | |
4365 | int regno = REGNO (operands[0]); | |
4366 | ops[0] = gen_rtx_REG (TImode, regno); | |
4367 | ops[1] = operands[1]; | |
d91524d5 | 4368 | output_asm_insn ("vldrw.32\t%q0, %E1",ops); |
bf1e3d5a SP |
4369 | return ""; |
4370 | } | |
4371 | [(set_attr "length" "4")]) | |
4372 | ||
4373 | ;; | |
4374 | ;; [vldrwq_z_f] | |
4375 | ;; | |
4376 | (define_insn "mve_vldrwq_z_fv4sf" | |
4377 | [(set (match_operand:V4SF 0 "s_register_operand" "=w") | |
5efeaa0d | 4378 | (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux") |
6a7c13a0 | 4379 | (match_operand:V4BI 2 "vpr_register_operand" "Up")] |
bf1e3d5a SP |
4380 | VLDRWQ_F)) |
4381 | ] | |
4382 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4383 | { | |
4384 | rtx ops[2]; | |
4385 | int regno = REGNO (operands[0]); | |
4386 | ops[0] = gen_rtx_REG (TImode, regno); | |
4387 | ops[1] = operands[1]; | |
d91524d5 | 4388 | output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); |
bf1e3d5a SP |
4389 | return ""; |
4390 | } | |
4391 | [(set_attr "length" "8")]) | |
4392 | ||
4393 | ;; | |
4394 | ;; [vldrwq_z_s vldrwq_z_u] | |
4395 | ;; | |
4396 | (define_insn "mve_vldrwq_z_<supf>v4si" | |
4397 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
5efeaa0d | 4398 | (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux") |
6a7c13a0 | 4399 | (match_operand:V4BI 2 "vpr_register_operand" "Up")] |
bf1e3d5a SP |
4400 | VLDRWQ)) |
4401 | ] | |
4402 | "TARGET_HAVE_MVE" | |
4403 | { | |
4404 | rtx ops[2]; | |
4405 | int regno = REGNO (operands[0]); | |
4406 | ops[0] = gen_rtx_REG (TImode, regno); | |
4407 | ops[1] = operands[1]; | |
d91524d5 | 4408 | output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); |
bf1e3d5a SP |
4409 | return ""; |
4410 | } | |
4411 | [(set_attr "length" "8")]) | |
4412 | ||
4413 | (define_expand "mve_vld1q_f<mode>" | |
4414 | [(match_operand:MVE_0 0 "s_register_operand") | |
d91524d5 | 4415 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "mve_memory_operand")] VLD1Q_F) |
bf1e3d5a SP |
4416 | ] |
4417 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
4418 | { | |
4419 | emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); | |
4420 | DONE; | |
4421 | }) | |
4422 | ||
4423 | (define_expand "mve_vld1q_<supf><mode>" | |
4424 | [(match_operand:MVE_2 0 "s_register_operand") | |
d91524d5 | 4425 | (unspec:MVE_2 [(match_operand:MVE_2 1 "mve_memory_operand")] VLD1Q) |
bf1e3d5a SP |
4426 | ] |
4427 | "TARGET_HAVE_MVE" | |
4428 | { | |
4429 | emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); | |
4430 | DONE; | |
4431 | }) | |
4cc23303 SP |
4432 | |
4433 | ;; | |
4434 | ;; [vldrdq_gather_base_s vldrdq_gather_base_u] | |
4435 | ;; | |
4436 | (define_insn "mve_vldrdq_gather_base_<supf>v2di" | |
4437 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4438 | (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") | |
4439 | (match_operand:SI 2 "immediate_operand" "i")] | |
4440 | VLDRDGBQ)) | |
4441 | ] | |
4442 | "TARGET_HAVE_MVE" | |
4443 | { | |
4444 | rtx ops[3]; | |
4445 | ops[0] = operands[0]; | |
4446 | ops[1] = operands[1]; | |
4447 | ops[2] = operands[2]; | |
4448 | output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops); | |
4449 | return ""; | |
4450 | } | |
4451 | [(set_attr "length" "4")]) | |
4452 | ||
4453 | ;; | |
4454 | ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u] | |
4455 | ;; | |
4456 | (define_insn "mve_vldrdq_gather_base_z_<supf>v2di" | |
4457 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4458 | (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") | |
4459 | (match_operand:SI 2 "immediate_operand" "i") | |
e0bc13d3 | 4460 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4461 | VLDRDGBQ)) |
4462 | ] | |
4463 | "TARGET_HAVE_MVE" | |
4464 | { | |
4465 | rtx ops[3]; | |
4466 | ops[0] = operands[0]; | |
4467 | ops[1] = operands[1]; | |
4468 | ops[2] = operands[2]; | |
4469 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops); | |
4470 | return ""; | |
4471 | } | |
4472 | [(set_attr "length" "8")]) | |
4473 | ||
4474 | ;; | |
4475 | ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u] | |
4476 | ;; | |
4477 | (define_insn "mve_vldrdq_gather_offset_<supf>v2di" | |
4478 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4479 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
4480 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
4481 | VLDRDGOQ)) | |
4482 | ] | |
4483 | "TARGET_HAVE_MVE" | |
4484 | { | |
4485 | rtx ops[3]; | |
4486 | ops[0] = operands[0]; | |
4487 | ops[1] = operands[1]; | |
4488 | ops[2] = operands[2]; | |
4489 | output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops); | |
4490 | return ""; | |
4491 | } | |
4492 | [(set_attr "length" "4")]) | |
4493 | ||
4494 | ;; | |
4495 | ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u] | |
4496 | ;; | |
4497 | (define_insn "mve_vldrdq_gather_offset_z_<supf>v2di" | |
4498 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4499 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
4500 | (match_operand:V2DI 2 "s_register_operand" "w") | |
e0bc13d3 | 4501 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4502 | VLDRDGOQ)) |
4503 | ] | |
4504 | "TARGET_HAVE_MVE" | |
4505 | { | |
4506 | rtx ops[3]; | |
4507 | ops[0] = operands[0]; | |
4508 | ops[1] = operands[1]; | |
4509 | ops[2] = operands[2]; | |
4510 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops); | |
4511 | return ""; | |
4512 | } | |
4513 | [(set_attr "length" "8")]) | |
4514 | ||
4515 | ;; | |
4516 | ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u] | |
4517 | ;; | |
4518 | (define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di" | |
4519 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4520 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
4521 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
4522 | VLDRDGSOQ)) | |
4523 | ] | |
4524 | "TARGET_HAVE_MVE" | |
4525 | { | |
4526 | rtx ops[3]; | |
4527 | ops[0] = operands[0]; | |
4528 | ops[1] = operands[1]; | |
4529 | ops[2] = operands[2]; | |
4530 | output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops); | |
4531 | return ""; | |
4532 | } | |
4533 | [(set_attr "length" "4")]) | |
4534 | ||
4535 | ;; | |
4536 | ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u] | |
4537 | ;; | |
4538 | (define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di" | |
4539 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
4540 | (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") | |
4541 | (match_operand:V2DI 2 "s_register_operand" "w") | |
e0bc13d3 | 4542 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4543 | VLDRDGSOQ)) |
4544 | ] | |
4545 | "TARGET_HAVE_MVE" | |
4546 | { | |
4547 | rtx ops[3]; | |
4548 | ops[0] = operands[0]; | |
4549 | ops[1] = operands[1]; | |
4550 | ops[2] = operands[2]; | |
4551 | output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops); | |
4552 | return ""; | |
4553 | } | |
4554 | [(set_attr "length" "8")]) | |
4555 | ||
4556 | ;; | |
4557 | ;; [vldrhq_gather_offset_f] | |
4558 | ;; | |
4559 | (define_insn "mve_vldrhq_gather_offset_fv8hf" | |
4560 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
4561 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
4562 | (match_operand:V8HI 2 "s_register_operand" "w")] | |
4563 | VLDRHQGO_F)) | |
4564 | ] | |
4565 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4566 | { | |
4567 | rtx ops[3]; | |
4568 | ops[0] = operands[0]; | |
4569 | ops[1] = operands[1]; | |
4570 | ops[2] = operands[2]; | |
4571 | output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops); | |
4572 | return ""; | |
4573 | } | |
4574 | [(set_attr "length" "4")]) | |
4575 | ||
4576 | ;; | |
4577 | ;; [vldrhq_gather_offset_z_f] | |
4578 | ;; | |
4579 | (define_insn "mve_vldrhq_gather_offset_z_fv8hf" | |
4580 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
4581 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
4582 | (match_operand:V8HI 2 "s_register_operand" "w") | |
6a7c13a0 | 4583 | (match_operand:V8BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4584 | VLDRHQGO_F)) |
4585 | ] | |
4586 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4587 | { | |
4588 | rtx ops[4]; | |
4589 | ops[0] = operands[0]; | |
4590 | ops[1] = operands[1]; | |
4591 | ops[2] = operands[2]; | |
4592 | ops[3] = operands[3]; | |
4593 | output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops); | |
4594 | return ""; | |
4595 | } | |
4596 | [(set_attr "length" "8")]) | |
4597 | ||
4598 | ;; | |
4599 | ;; [vldrhq_gather_shifted_offset_f] | |
4600 | ;; | |
4601 | (define_insn "mve_vldrhq_gather_shifted_offset_fv8hf" | |
4602 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
4603 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
4604 | (match_operand:V8HI 2 "s_register_operand" "w")] | |
4605 | VLDRHQGSO_F)) | |
4606 | ] | |
4607 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4608 | { | |
4609 | rtx ops[3]; | |
4610 | ops[0] = operands[0]; | |
4611 | ops[1] = operands[1]; | |
4612 | ops[2] = operands[2]; | |
4613 | output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4614 | return ""; | |
4615 | } | |
4616 | [(set_attr "length" "4")]) | |
4617 | ||
4618 | ;; | |
4619 | ;; [vldrhq_gather_shifted_offset_z_f] | |
4620 | ;; | |
4621 | (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" | |
4622 | [(set (match_operand:V8HF 0 "s_register_operand" "=&w") | |
4623 | (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") | |
4624 | (match_operand:V8HI 2 "s_register_operand" "w") | |
6a7c13a0 | 4625 | (match_operand:V8BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4626 | VLDRHQGSO_F)) |
4627 | ] | |
4628 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4629 | { | |
4630 | rtx ops[4]; | |
4631 | ops[0] = operands[0]; | |
4632 | ops[1] = operands[1]; | |
4633 | ops[2] = operands[2]; | |
4634 | ops[3] = operands[3]; | |
4635 | output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops); | |
4636 | return ""; | |
4637 | } | |
4638 | [(set_attr "length" "8")]) | |
4639 | ||
4640 | ;; | |
4641 | ;; [vldrwq_gather_base_f] | |
4642 | ;; | |
4643 | (define_insn "mve_vldrwq_gather_base_fv4sf" | |
4644 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4645 | (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") | |
4646 | (match_operand:SI 2 "immediate_operand" "i")] | |
4647 | VLDRWQGB_F)) | |
4648 | ] | |
4649 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4650 | { | |
4651 | rtx ops[3]; | |
4652 | ops[0] = operands[0]; | |
4653 | ops[1] = operands[1]; | |
4654 | ops[2] = operands[2]; | |
4655 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); | |
4656 | return ""; | |
4657 | } | |
4658 | [(set_attr "length" "4")]) | |
4659 | ||
4660 | ;; | |
4661 | ;; [vldrwq_gather_base_z_f] | |
4662 | ;; | |
4663 | (define_insn "mve_vldrwq_gather_base_z_fv4sf" | |
4664 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4665 | (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") | |
4666 | (match_operand:SI 2 "immediate_operand" "i") | |
6a7c13a0 | 4667 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4668 | VLDRWQGB_F)) |
4669 | ] | |
4670 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4671 | { | |
4672 | rtx ops[3]; | |
4673 | ops[0] = operands[0]; | |
4674 | ops[1] = operands[1]; | |
4675 | ops[2] = operands[2]; | |
4676 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); | |
4677 | return ""; | |
4678 | } | |
4679 | [(set_attr "length" "8")]) | |
4680 | ||
4681 | ;; | |
4682 | ;; [vldrwq_gather_offset_f] | |
4683 | ;; | |
4684 | (define_insn "mve_vldrwq_gather_offset_fv4sf" | |
4685 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4686 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
4687 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
4688 | VLDRWQGO_F)) | |
4689 | ] | |
4690 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4691 | { | |
4692 | rtx ops[3]; | |
4693 | ops[0] = operands[0]; | |
4694 | ops[1] = operands[1]; | |
4695 | ops[2] = operands[2]; | |
4696 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); | |
4697 | return ""; | |
4698 | } | |
4699 | [(set_attr "length" "4")]) | |
4700 | ||
4701 | ;; | |
4702 | ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u] | |
4703 | ;; | |
4704 | (define_insn "mve_vldrwq_gather_offset_<supf>v4si" | |
4705 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
4706 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
4707 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
4708 | VLDRWGOQ)) | |
4709 | ] | |
4710 | "TARGET_HAVE_MVE" | |
4711 | { | |
4712 | rtx ops[3]; | |
4713 | ops[0] = operands[0]; | |
4714 | ops[1] = operands[1]; | |
4715 | ops[2] = operands[2]; | |
4716 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); | |
4717 | return ""; | |
4718 | } | |
4719 | [(set_attr "length" "4")]) | |
4720 | ||
4721 | ;; | |
4722 | ;; [vldrwq_gather_offset_z_f] | |
4723 | ;; | |
4724 | (define_insn "mve_vldrwq_gather_offset_z_fv4sf" | |
4725 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4726 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
4727 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 4728 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4729 | VLDRWQGO_F)) |
4730 | ] | |
4731 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4732 | { | |
4733 | rtx ops[4]; | |
4734 | ops[0] = operands[0]; | |
4735 | ops[1] = operands[1]; | |
4736 | ops[2] = operands[2]; | |
4737 | ops[3] = operands[3]; | |
4738 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); | |
4739 | return ""; | |
4740 | } | |
4741 | [(set_attr "length" "8")]) | |
4742 | ||
4743 | ;; | |
4744 | ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u] | |
4745 | ;; | |
4746 | (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" | |
4747 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
4748 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
4749 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 4750 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4751 | VLDRWGOQ)) |
4752 | ] | |
4753 | "TARGET_HAVE_MVE" | |
4754 | { | |
4755 | rtx ops[4]; | |
4756 | ops[0] = operands[0]; | |
4757 | ops[1] = operands[1]; | |
4758 | ops[2] = operands[2]; | |
4759 | ops[3] = operands[3]; | |
4760 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); | |
4761 | return ""; | |
4762 | } | |
4763 | [(set_attr "length" "8")]) | |
4764 | ||
4765 | ;; | |
4766 | ;; [vldrwq_gather_shifted_offset_f] | |
4767 | ;; | |
4768 | (define_insn "mve_vldrwq_gather_shifted_offset_fv4sf" | |
4769 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4770 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
4771 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
4772 | VLDRWQGSO_F)) | |
4773 | ] | |
4774 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4775 | { | |
4776 | rtx ops[3]; | |
4777 | ops[0] = operands[0]; | |
4778 | ops[1] = operands[1]; | |
4779 | ops[2] = operands[2]; | |
4780 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
4781 | return ""; | |
4782 | } | |
4783 | [(set_attr "length" "4")]) | |
4784 | ||
4785 | ;; | |
4786 | ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u] | |
4787 | ;; | |
4788 | (define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si" | |
4789 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
4790 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
4791 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
4792 | VLDRWGSOQ)) | |
4793 | ] | |
4794 | "TARGET_HAVE_MVE" | |
4795 | { | |
4796 | rtx ops[3]; | |
4797 | ops[0] = operands[0]; | |
4798 | ops[1] = operands[1]; | |
4799 | ops[2] = operands[2]; | |
4800 | output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
4801 | return ""; | |
4802 | } | |
4803 | [(set_attr "length" "4")]) | |
4804 | ||
4805 | ;; | |
4806 | ;; [vldrwq_gather_shifted_offset_z_f] | |
4807 | ;; | |
4808 | (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" | |
4809 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
4810 | (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") | |
4811 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 4812 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4813 | VLDRWQGSO_F)) |
4814 | ] | |
4815 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4816 | { | |
4817 | rtx ops[4]; | |
4818 | ops[0] = operands[0]; | |
4819 | ops[1] = operands[1]; | |
4820 | ops[2] = operands[2]; | |
4821 | ops[3] = operands[3]; | |
4822 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
4823 | return ""; | |
4824 | } | |
4825 | [(set_attr "length" "8")]) | |
4826 | ||
4827 | ;; | |
4828 | ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u] | |
4829 | ;; | |
4830 | (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" | |
4831 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
4832 | (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") | |
4833 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 4834 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
4cc23303 SP |
4835 | VLDRWGSOQ)) |
4836 | ] | |
4837 | "TARGET_HAVE_MVE" | |
4838 | { | |
4839 | rtx ops[4]; | |
4840 | ops[0] = operands[0]; | |
4841 | ops[1] = operands[1]; | |
4842 | ops[2] = operands[2]; | |
4843 | ops[3] = operands[3]; | |
4844 | output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); | |
4845 | return ""; | |
4846 | } | |
4847 | [(set_attr "length" "8")]) | |
5cad47e0 SP |
4848 | |
4849 | ;; | |
4850 | ;; [vstrhq_f] | |
4851 | ;; | |
4852 | (define_insn "mve_vstrhq_fv8hf" | |
d91524d5 | 4853 | [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
4854 | (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")] |
4855 | VSTRHQ_F)) | |
4856 | ] | |
4857 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
4858 | { | |
4859 | rtx ops[2]; | |
4860 | int regno = REGNO (operands[1]); | |
4861 | ops[1] = gen_rtx_REG (TImode, regno); | |
4862 | ops[0] = operands[0]; | |
4863 | output_asm_insn ("vstrh.16\t%q1, %E0",ops); | |
4864 | return ""; | |
4865 | } | |
4866 | [(set_attr "length" "4")]) | |
4867 | ||
4868 | ;; | |
4869 | ;; [vstrhq_p_f] | |
4870 | ;; | |
4871 | (define_insn "mve_vstrhq_p_fv8hf" | |
d91524d5 | 4872 | [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") |
c1093923 AV |
4873 | (unspec:V8HI |
4874 | [(match_operand:V8HF 1 "s_register_operand" "w") | |
4875 | (match_operand:V8BI 2 "vpr_register_operand" "Up") | |
4876 | (match_dup 0)] | |
4877 | VSTRHQ_F))] | |
5cad47e0 SP |
4878 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
4879 | { | |
4880 | rtx ops[2]; | |
4881 | int regno = REGNO (operands[1]); | |
4882 | ops[1] = gen_rtx_REG (TImode, regno); | |
4883 | ops[0] = operands[0]; | |
d91524d5 | 4884 | output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops); |
5cad47e0 SP |
4885 | return ""; |
4886 | } | |
4887 | [(set_attr "length" "8")]) | |
4888 | ||
4889 | ;; | |
4890 | ;; [vstrhq_p_s vstrhq_p_u] | |
4891 | ;; | |
4892 | (define_insn "mve_vstrhq_p_<supf><mode>" | |
d91524d5 | 4893 | [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") |
c1093923 AV |
4894 | (unspec:<MVE_H_ELEM> |
4895 | [(match_operand:MVE_6 1 "s_register_operand" "w") | |
4896 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") | |
4897 | (match_dup 0)] | |
5cad47e0 SP |
4898 | VSTRHQ)) |
4899 | ] | |
4900 | "TARGET_HAVE_MVE" | |
4901 | { | |
4902 | rtx ops[2]; | |
4903 | int regno = REGNO (operands[1]); | |
4904 | ops[1] = gen_rtx_REG (TImode, regno); | |
4905 | ops[0] = operands[0]; | |
d91524d5 | 4906 | output_asm_insn ("vpst\;vstrht.<V_sz_elem>\t%q1, %E0",ops); |
5cad47e0 SP |
4907 | return ""; |
4908 | } | |
4909 | [(set_attr "length" "8")]) | |
4910 | ||
4911 | ;; | |
4912 | ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u] | |
4913 | ;; | |
9a810e57 SP |
4914 | (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>" |
4915 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
4916 | (match_operand:MVE_6 1 "s_register_operand") | |
4917 | (match_operand:MVE_6 2 "s_register_operand") | |
724d6566 | 4918 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand") |
9a810e57 | 4919 | (unspec:V4SI [(const_int 0)] VSTRHSOQ)] |
5cad47e0 SP |
4920 | "TARGET_HAVE_MVE" |
4921 | { | |
9a810e57 SP |
4922 | rtx ind = XEXP (operands[0], 0); |
4923 | gcc_assert (REG_P (ind)); | |
4924 | emit_insn ( | |
4925 | gen_mve_vstrhq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], | |
4926 | operands[2], | |
4927 | operands[3])); | |
4928 | DONE; | |
4929 | }) | |
4930 | ||
4931 | (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn" | |
4932 | [(set (mem:BLK (scratch)) | |
4933 | (unspec:BLK | |
4934 | [(match_operand:SI 0 "register_operand" "r") | |
4935 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
4936 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
724d6566 | 4937 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
4938 | VSTRHSOQ))] |
4939 | "TARGET_HAVE_MVE" | |
4940 | "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]" | |
5cad47e0 SP |
4941 | [(set_attr "length" "8")]) |
4942 | ||
4943 | ;; | |
4944 | ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u] | |
4945 | ;; | |
9a810e57 SP |
4946 | (define_expand "mve_vstrhq_scatter_offset_<supf><mode>" |
4947 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
4948 | (match_operand:MVE_6 1 "s_register_operand") | |
4949 | (match_operand:MVE_6 2 "s_register_operand") | |
4950 | (unspec:V4SI [(const_int 0)] VSTRHSOQ)] | |
5cad47e0 SP |
4951 | "TARGET_HAVE_MVE" |
4952 | { | |
9a810e57 SP |
4953 | rtx ind = XEXP (operands[0], 0); |
4954 | gcc_assert (REG_P (ind)); | |
4955 | emit_insn (gen_mve_vstrhq_scatter_offset_<supf><mode>_insn (ind, operands[1], | |
4956 | operands[2])); | |
4957 | DONE; | |
4958 | }) | |
4959 | ||
4960 | (define_insn "mve_vstrhq_scatter_offset_<supf><mode>_insn" | |
4961 | [(set (mem:BLK (scratch)) | |
4962 | (unspec:BLK | |
4963 | [(match_operand:SI 0 "register_operand" "r") | |
4964 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
4965 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
4966 | VSTRHSOQ))] | |
4967 | "TARGET_HAVE_MVE" | |
4968 | "vstrh.<V_sz_elem>\t%q2, [%0, %q1]" | |
5cad47e0 SP |
4969 | [(set_attr "length" "4")]) |
4970 | ||
4971 | ;; | |
4972 | ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u] | |
4973 | ;; | |
9a810e57 SP |
4974 | (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>" |
4975 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
4976 | (match_operand:MVE_6 1 "s_register_operand") | |
4977 | (match_operand:MVE_6 2 "s_register_operand") | |
724d6566 | 4978 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand") |
9a810e57 | 4979 | (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] |
5cad47e0 SP |
4980 | "TARGET_HAVE_MVE" |
4981 | { | |
9a810e57 SP |
4982 | rtx ind = XEXP (operands[0], 0); |
4983 | gcc_assert (REG_P (ind)); | |
4984 | emit_insn ( | |
4985 | gen_mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn (ind, operands[1], | |
4986 | operands[2], | |
4987 | operands[3])); | |
4988 | DONE; | |
4989 | }) | |
4990 | ||
4991 | (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn" | |
4992 | [(set (mem:BLK (scratch)) | |
4993 | (unspec:BLK | |
4994 | [(match_operand:SI 0 "register_operand" "r") | |
4995 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
4996 | (match_operand:MVE_6 2 "s_register_operand" "w") | |
724d6566 | 4997 | (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
4998 | VSTRHSSOQ))] |
4999 | "TARGET_HAVE_MVE" | |
5000 | "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" | |
5cad47e0 SP |
5001 | [(set_attr "length" "8")]) |
5002 | ||
5003 | ;; | |
5004 | ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u] | |
5005 | ;; | |
9a810e57 SP |
5006 | (define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>" |
5007 | [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") | |
5008 | (match_operand:MVE_6 1 "s_register_operand") | |
5009 | (match_operand:MVE_6 2 "s_register_operand") | |
5010 | (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] | |
5cad47e0 SP |
5011 | "TARGET_HAVE_MVE" |
5012 | { | |
9a810e57 SP |
5013 | rtx ind = XEXP (operands[0], 0); |
5014 | gcc_assert (REG_P (ind)); | |
5015 | emit_insn ( | |
5016 | gen_mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn (ind, operands[1], | |
5017 | operands[2])); | |
5018 | DONE; | |
5019 | }) | |
5020 | ||
5021 | (define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn" | |
5022 | [(set (mem:BLK (scratch)) | |
5023 | (unspec:BLK | |
5024 | [(match_operand:SI 0 "register_operand" "r") | |
5025 | (match_operand:MVE_6 1 "s_register_operand" "w") | |
5026 | (match_operand:MVE_6 2 "s_register_operand" "w")] | |
5027 | VSTRHSSOQ))] | |
5028 | "TARGET_HAVE_MVE" | |
5029 | "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" | |
5cad47e0 SP |
5030 | [(set_attr "length" "4")]) |
5031 | ||
5032 | ;; | |
5033 | ;; [vstrhq_s, vstrhq_u] | |
5034 | ;; | |
5035 | (define_insn "mve_vstrhq_<supf><mode>" | |
d91524d5 | 5036 | [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
5037 | (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")] |
5038 | VSTRHQ)) | |
5039 | ] | |
5040 | "TARGET_HAVE_MVE" | |
5041 | { | |
5042 | rtx ops[2]; | |
5043 | int regno = REGNO (operands[1]); | |
5044 | ops[1] = gen_rtx_REG (TImode, regno); | |
5045 | ops[0] = operands[0]; | |
5046 | output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops); | |
5047 | return ""; | |
5048 | } | |
5049 | [(set_attr "length" "4")]) | |
5050 | ||
5051 | ;; | |
5052 | ;; [vstrwq_f] | |
5053 | ;; | |
5054 | (define_insn "mve_vstrwq_fv4sf" | |
5efeaa0d | 5055 | [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
5056 | (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")] |
5057 | VSTRWQ_F)) | |
5058 | ] | |
5059 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5060 | { | |
5061 | rtx ops[2]; | |
5062 | int regno = REGNO (operands[1]); | |
5063 | ops[1] = gen_rtx_REG (TImode, regno); | |
5064 | ops[0] = operands[0]; | |
5065 | output_asm_insn ("vstrw.32\t%q1, %E0",ops); | |
5066 | return ""; | |
5067 | } | |
5068 | [(set_attr "length" "4")]) | |
5069 | ||
5070 | ;; | |
5071 | ;; [vstrwq_p_f] | |
5072 | ;; | |
5073 | (define_insn "mve_vstrwq_p_fv4sf" | |
5efeaa0d | 5074 | [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") |
c1093923 AV |
5075 | (unspec:V4SI |
5076 | [(match_operand:V4SF 1 "s_register_operand" "w") | |
5077 | (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") | |
5078 | (match_dup 0)] | |
5079 | VSTRWQ_F))] | |
5cad47e0 SP |
5080 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5081 | { | |
5082 | rtx ops[2]; | |
5083 | int regno = REGNO (operands[1]); | |
5084 | ops[1] = gen_rtx_REG (TImode, regno); | |
5085 | ops[0] = operands[0]; | |
d91524d5 | 5086 | output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); |
5cad47e0 SP |
5087 | return ""; |
5088 | } | |
5089 | [(set_attr "length" "8")]) | |
5090 | ||
5091 | ;; | |
5092 | ;; [vstrwq_p_s vstrwq_p_u] | |
5093 | ;; | |
5094 | (define_insn "mve_vstrwq_p_<supf>v4si" | |
5efeaa0d | 5095 | [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") |
c1093923 AV |
5096 | (unspec:V4SI |
5097 | [(match_operand:V4SI 1 "s_register_operand" "w") | |
5098 | (match_operand:V4BI 2 "vpr_register_operand" "Up") | |
5099 | (match_dup 0)] | |
5100 | VSTRWQ))] | |
5cad47e0 SP |
5101 | "TARGET_HAVE_MVE" |
5102 | { | |
5103 | rtx ops[2]; | |
5104 | int regno = REGNO (operands[1]); | |
5105 | ops[1] = gen_rtx_REG (TImode, regno); | |
5106 | ops[0] = operands[0]; | |
d91524d5 | 5107 | output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); |
5cad47e0 SP |
5108 | return ""; |
5109 | } | |
5110 | [(set_attr "length" "8")]) | |
5111 | ||
5112 | ;; | |
5113 | ;; [vstrwq_s vstrwq_u] | |
5114 | ;; | |
5115 | (define_insn "mve_vstrwq_<supf>v4si" | |
5efeaa0d | 5116 | [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") |
5cad47e0 SP |
5117 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")] |
5118 | VSTRWQ)) | |
5119 | ] | |
5120 | "TARGET_HAVE_MVE" | |
5121 | { | |
5122 | rtx ops[2]; | |
5123 | int regno = REGNO (operands[1]); | |
5124 | ops[1] = gen_rtx_REG (TImode, regno); | |
5125 | ops[0] = operands[0]; | |
5126 | output_asm_insn ("vstrw.32\t%q1, %E0",ops); | |
5127 | return ""; | |
5128 | } | |
5129 | [(set_attr "length" "4")]) | |
5130 | ||
5131 | (define_expand "mve_vst1q_f<mode>" | |
91d206ad | 5132 | [(match_operand:<MVE_CNVT> 0 "mve_memory_operand") |
5cad47e0 SP |
5133 | (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F) |
5134 | ] | |
5135 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
5136 | { | |
5137 | emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); | |
5138 | DONE; | |
5139 | }) | |
5140 | ||
5141 | (define_expand "mve_vst1q_<supf><mode>" | |
91d206ad | 5142 | [(match_operand:MVE_2 0 "mve_memory_operand") |
5cad47e0 SP |
5143 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q) |
5144 | ] | |
5145 | "TARGET_HAVE_MVE" | |
5146 | { | |
5147 | emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); | |
5148 | DONE; | |
5149 | }) | |
7a5fffa5 SP |
5150 | |
5151 | ;; | |
5152 | ;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u] | |
5153 | ;; | |
5154 | (define_insn "mve_vstrdq_scatter_base_p_<supf>v2di" | |
5155 | [(set (mem:BLK (scratch)) | |
5156 | (unspec:BLK | |
5157 | [(match_operand:V2DI 0 "s_register_operand" "w") | |
5158 | (match_operand:SI 1 "mve_vldrd_immediate" "Ri") | |
5159 | (match_operand:V2DI 2 "s_register_operand" "w") | |
e0bc13d3 | 5160 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
7a5fffa5 SP |
5161 | VSTRDSBQ)) |
5162 | ] | |
5163 | "TARGET_HAVE_MVE" | |
5164 | { | |
5165 | rtx ops[3]; | |
5166 | ops[0] = operands[0]; | |
5167 | ops[1] = operands[1]; | |
5168 | ops[2] = operands[2]; | |
5169 | output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops); | |
5170 | return ""; | |
5171 | } | |
5172 | [(set_attr "length" "8")]) | |
5173 | ||
5174 | ;; | |
5175 | ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u] | |
5176 | ;; | |
5177 | (define_insn "mve_vstrdq_scatter_base_<supf>v2di" | |
5178 | [(set (mem:BLK (scratch)) | |
5179 | (unspec:BLK | |
5180 | [(match_operand:V2DI 0 "s_register_operand" "=w") | |
5181 | (match_operand:SI 1 "mve_vldrd_immediate" "Ri") | |
5182 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
5183 | VSTRDSBQ)) | |
5184 | ] | |
5185 | "TARGET_HAVE_MVE" | |
5186 | { | |
5187 | rtx ops[3]; | |
5188 | ops[0] = operands[0]; | |
5189 | ops[1] = operands[1]; | |
5190 | ops[2] = operands[2]; | |
5191 | output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops); | |
5192 | return ""; | |
5193 | } | |
5194 | [(set_attr "length" "4")]) | |
5195 | ||
5196 | ;; | |
5197 | ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u] | |
5198 | ;; | |
9a810e57 SP |
5199 | (define_expand "mve_vstrdq_scatter_offset_p_<supf>v2di" |
5200 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
5201 | (match_operand:V2DI 1 "s_register_operand") | |
5202 | (match_operand:V2DI 2 "s_register_operand") | |
e0bc13d3 | 5203 | (match_operand:V2QI 3 "vpr_register_operand") |
9a810e57 | 5204 | (unspec:V4SI [(const_int 0)] VSTRDSOQ)] |
7a5fffa5 SP |
5205 | "TARGET_HAVE_MVE" |
5206 | { | |
9a810e57 SP |
5207 | rtx ind = XEXP (operands[0], 0); |
5208 | gcc_assert (REG_P (ind)); | |
5209 | emit_insn (gen_mve_vstrdq_scatter_offset_p_<supf>v2di_insn (ind, operands[1], | |
5210 | operands[2], | |
5211 | operands[3])); | |
5212 | DONE; | |
5213 | }) | |
5214 | ||
5215 | (define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di_insn" | |
5216 | [(set (mem:BLK (scratch)) | |
5217 | (unspec:BLK | |
5218 | [(match_operand:SI 0 "register_operand" "r") | |
5219 | (match_operand:V2DI 1 "s_register_operand" "w") | |
5220 | (match_operand:V2DI 2 "s_register_operand" "w") | |
e0bc13d3 | 5221 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5222 | VSTRDSOQ))] |
5223 | "TARGET_HAVE_MVE" | |
5224 | "vpst\;vstrdt.64\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5225 | [(set_attr "length" "8")]) |
5226 | ||
5227 | ;; | |
5228 | ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u] | |
5229 | ;; | |
9a810e57 SP |
5230 | (define_expand "mve_vstrdq_scatter_offset_<supf>v2di" |
5231 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
5232 | (match_operand:V2DI 1 "s_register_operand") | |
5233 | (match_operand:V2DI 2 "s_register_operand") | |
5234 | (unspec:V4SI [(const_int 0)] VSTRDSOQ)] | |
7a5fffa5 SP |
5235 | "TARGET_HAVE_MVE" |
5236 | { | |
9a810e57 SP |
5237 | rtx ind = XEXP (operands[0], 0); |
5238 | gcc_assert (REG_P (ind)); | |
5239 | emit_insn (gen_mve_vstrdq_scatter_offset_<supf>v2di_insn (ind, operands[1], | |
5240 | operands[2])); | |
5241 | DONE; | |
5242 | }) | |
5243 | ||
5244 | (define_insn "mve_vstrdq_scatter_offset_<supf>v2di_insn" | |
5245 | [(set (mem:BLK (scratch)) | |
5246 | (unspec:BLK | |
5247 | [(match_operand:SI 0 "register_operand" "r") | |
5248 | (match_operand:V2DI 1 "s_register_operand" "w") | |
5249 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
5250 | VSTRDSOQ))] | |
5251 | "TARGET_HAVE_MVE" | |
5252 | "vstrd.64\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5253 | [(set_attr "length" "4")]) |
5254 | ||
5255 | ;; | |
5256 | ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u] | |
5257 | ;; | |
9a810e57 SP |
5258 | (define_expand "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di" |
5259 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
5260 | (match_operand:V2DI 1 "s_register_operand") | |
5261 | (match_operand:V2DI 2 "s_register_operand") | |
e0bc13d3 | 5262 | (match_operand:V2QI 3 "vpr_register_operand") |
9a810e57 | 5263 | (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] |
7a5fffa5 SP |
5264 | "TARGET_HAVE_MVE" |
5265 | { | |
9a810e57 SP |
5266 | rtx ind = XEXP (operands[0], 0); |
5267 | gcc_assert (REG_P (ind)); | |
5268 | emit_insn ( | |
5269 | gen_mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn (ind, operands[1], | |
5270 | operands[2], | |
5271 | operands[3])); | |
5272 | DONE; | |
5273 | }) | |
5274 | ||
5275 | (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn" | |
5276 | [(set (mem:BLK (scratch)) | |
5277 | (unspec:BLK | |
5278 | [(match_operand:SI 0 "register_operand" "r") | |
5279 | (match_operand:V2DI 1 "s_register_operand" "w") | |
5280 | (match_operand:V2DI 2 "s_register_operand" "w") | |
e0bc13d3 | 5281 | (match_operand:V2QI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5282 | VSTRDSSOQ))] |
5283 | "TARGET_HAVE_MVE" | |
5284 | "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]" | |
7a5fffa5 SP |
5285 | [(set_attr "length" "8")]) |
5286 | ||
5287 | ;; | |
5288 | ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u] | |
5289 | ;; | |
9a810e57 SP |
5290 | (define_expand "mve_vstrdq_scatter_shifted_offset_<supf>v2di" |
5291 | [(match_operand:V2DI 0 "mve_scatter_memory") | |
5292 | (match_operand:V2DI 1 "s_register_operand") | |
5293 | (match_operand:V2DI 2 "s_register_operand") | |
5294 | (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] | |
7a5fffa5 SP |
5295 | "TARGET_HAVE_MVE" |
5296 | { | |
9a810e57 SP |
5297 | rtx ind = XEXP (operands[0], 0); |
5298 | gcc_assert (REG_P (ind)); | |
5299 | emit_insn ( | |
5300 | gen_mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn (ind, operands[1], | |
5301 | operands[2])); | |
5302 | DONE; | |
5303 | }) | |
5304 | ||
5305 | (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn" | |
5306 | [(set (mem:BLK (scratch)) | |
5307 | (unspec:BLK | |
5308 | [(match_operand:SI 0 "register_operand" "r") | |
5309 | (match_operand:V2DI 1 "s_register_operand" "w") | |
5310 | (match_operand:V2DI 2 "s_register_operand" "w")] | |
5311 | VSTRDSSOQ))] | |
5312 | "TARGET_HAVE_MVE" | |
5313 | "vstrd.64\t%q2, [%0, %q1, UXTW #3]" | |
7a5fffa5 SP |
5314 | [(set_attr "length" "4")]) |
5315 | ||
5316 | ;; | |
5317 | ;; [vstrhq_scatter_offset_f] | |
5318 | ;; | |
9a810e57 SP |
5319 | (define_expand "mve_vstrhq_scatter_offset_fv8hf" |
5320 | [(match_operand:V8HI 0 "mve_scatter_memory") | |
5321 | (match_operand:V8HI 1 "s_register_operand") | |
5322 | (match_operand:V8HF 2 "s_register_operand") | |
5323 | (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] | |
7a5fffa5 SP |
5324 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5325 | { | |
9a810e57 SP |
5326 | rtx ind = XEXP (operands[0], 0); |
5327 | gcc_assert (REG_P (ind)); | |
5328 | emit_insn (gen_mve_vstrhq_scatter_offset_fv8hf_insn (ind, operands[1], | |
5329 | operands[2])); | |
5330 | DONE; | |
5331 | }) | |
5332 | ||
5333 | (define_insn "mve_vstrhq_scatter_offset_fv8hf_insn" | |
5334 | [(set (mem:BLK (scratch)) | |
5335 | (unspec:BLK | |
5336 | [(match_operand:SI 0 "register_operand" "r") | |
5337 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5338 | (match_operand:V8HF 2 "s_register_operand" "w")] | |
5339 | VSTRHQSO_F))] | |
5340 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5341 | "vstrh.16\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5342 | [(set_attr "length" "4")]) |
5343 | ||
5344 | ;; | |
5345 | ;; [vstrhq_scatter_offset_p_f] | |
5346 | ;; | |
9a810e57 SP |
5347 | (define_expand "mve_vstrhq_scatter_offset_p_fv8hf" |
5348 | [(match_operand:V8HI 0 "mve_scatter_memory") | |
5349 | (match_operand:V8HI 1 "s_register_operand") | |
5350 | (match_operand:V8HF 2 "s_register_operand") | |
6a7c13a0 | 5351 | (match_operand:V8BI 3 "vpr_register_operand") |
9a810e57 | 5352 | (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] |
7a5fffa5 SP |
5353 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5354 | { | |
9a810e57 SP |
5355 | rtx ind = XEXP (operands[0], 0); |
5356 | gcc_assert (REG_P (ind)); | |
5357 | emit_insn (gen_mve_vstrhq_scatter_offset_p_fv8hf_insn (ind, operands[1], | |
5358 | operands[2], | |
5359 | operands[3])); | |
5360 | DONE; | |
5361 | }) | |
5362 | ||
5363 | (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" | |
5364 | [(set (mem:BLK (scratch)) | |
5365 | (unspec:BLK | |
5366 | [(match_operand:SI 0 "register_operand" "r") | |
5367 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5368 | (match_operand:V8HF 2 "s_register_operand" "w") | |
6a7c13a0 | 5369 | (match_operand:V8BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5370 | VSTRHQSO_F))] |
5371 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5372 | "vpst\;vstrht.16\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5373 | [(set_attr "length" "8")]) |
5374 | ||
5375 | ;; | |
5376 | ;; [vstrhq_scatter_shifted_offset_f] | |
5377 | ;; | |
9a810e57 SP |
5378 | (define_expand "mve_vstrhq_scatter_shifted_offset_fv8hf" |
5379 | [(match_operand:V8HI 0 "memory_operand" "=Us") | |
5380 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5381 | (match_operand:V8HF 2 "s_register_operand" "w") | |
5382 | (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] | |
7a5fffa5 SP |
5383 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5384 | { | |
9a810e57 SP |
5385 | rtx ind = XEXP (operands[0], 0); |
5386 | gcc_assert (REG_P (ind)); | |
5387 | emit_insn (gen_mve_vstrhq_scatter_shifted_offset_fv8hf_insn (ind, operands[1], | |
5388 | operands[2])); | |
5389 | DONE; | |
5390 | }) | |
5391 | ||
5392 | (define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf_insn" | |
5393 | [(set (mem:BLK (scratch)) | |
5394 | (unspec:BLK | |
5395 | [(match_operand:SI 0 "register_operand" "r") | |
5396 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5397 | (match_operand:V8HF 2 "s_register_operand" "w")] | |
5398 | VSTRHQSSO_F))] | |
5399 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5400 | "vstrh.16\t%q2, [%0, %q1, uxtw #1]" | |
7a5fffa5 SP |
5401 | [(set_attr "length" "4")]) |
5402 | ||
5403 | ;; | |
5404 | ;; [vstrhq_scatter_shifted_offset_p_f] | |
5405 | ;; | |
9a810e57 SP |
5406 | (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" |
5407 | [(match_operand:V8HI 0 "memory_operand" "=Us") | |
5408 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5409 | (match_operand:V8HF 2 "s_register_operand" "w") | |
6a7c13a0 | 5410 | (match_operand:V8BI 3 "vpr_register_operand" "Up") |
9a810e57 | 5411 | (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] |
7a5fffa5 SP |
5412 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5413 | { | |
9a810e57 SP |
5414 | rtx ind = XEXP (operands[0], 0); |
5415 | gcc_assert (REG_P (ind)); | |
5416 | emit_insn ( | |
5417 | gen_mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn (ind, operands[1], | |
5418 | operands[2], | |
5419 | operands[3])); | |
5420 | DONE; | |
5421 | }) | |
5422 | ||
5423 | (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" | |
5424 | [(set (mem:BLK (scratch)) | |
5425 | (unspec:BLK | |
5426 | [(match_operand:SI 0 "register_operand" "r") | |
5427 | (match_operand:V8HI 1 "s_register_operand" "w") | |
5428 | (match_operand:V8HF 2 "s_register_operand" "w") | |
6a7c13a0 | 5429 | (match_operand:V8BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5430 | VSTRHQSSO_F))] |
5431 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5432 | "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" | |
7a5fffa5 SP |
5433 | [(set_attr "length" "8")]) |
5434 | ||
5435 | ;; | |
5436 | ;; [vstrwq_scatter_base_f] | |
5437 | ;; | |
5438 | (define_insn "mve_vstrwq_scatter_base_fv4sf" | |
5439 | [(set (mem:BLK (scratch)) | |
5440 | (unspec:BLK | |
5441 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
5442 | (match_operand:SI 1 "immediate_operand" "i") | |
5443 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
5444 | VSTRWQSB_F)) | |
5445 | ] | |
5446 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5447 | { | |
5448 | rtx ops[3]; | |
5449 | ops[0] = operands[0]; | |
5450 | ops[1] = operands[1]; | |
5451 | ops[2] = operands[2]; | |
5452 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops); | |
5453 | return ""; | |
5454 | } | |
5455 | [(set_attr "length" "4")]) | |
5456 | ||
5457 | ;; | |
5458 | ;; [vstrwq_scatter_base_p_f] | |
5459 | ;; | |
5460 | (define_insn "mve_vstrwq_scatter_base_p_fv4sf" | |
5461 | [(set (mem:BLK (scratch)) | |
5462 | (unspec:BLK | |
5463 | [(match_operand:V4SI 0 "s_register_operand" "w") | |
5464 | (match_operand:SI 1 "immediate_operand" "i") | |
5465 | (match_operand:V4SF 2 "s_register_operand" "w") | |
6a7c13a0 | 5466 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
7a5fffa5 SP |
5467 | VSTRWQSB_F)) |
5468 | ] | |
5469 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5470 | { | |
5471 | rtx ops[3]; | |
5472 | ops[0] = operands[0]; | |
5473 | ops[1] = operands[1]; | |
5474 | ops[2] = operands[2]; | |
5475 | output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); | |
5476 | return ""; | |
5477 | } | |
5478 | [(set_attr "length" "8")]) | |
5479 | ||
5480 | ;; | |
5481 | ;; [vstrwq_scatter_offset_f] | |
5482 | ;; | |
9a810e57 SP |
5483 | (define_expand "mve_vstrwq_scatter_offset_fv4sf" |
5484 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5485 | (match_operand:V4SI 1 "s_register_operand") | |
5486 | (match_operand:V4SF 2 "s_register_operand") | |
5487 | (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] | |
7a5fffa5 SP |
5488 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5489 | { | |
9a810e57 SP |
5490 | rtx ind = XEXP (operands[0], 0); |
5491 | gcc_assert (REG_P (ind)); | |
5492 | emit_insn (gen_mve_vstrwq_scatter_offset_fv4sf_insn (ind, operands[1], | |
5493 | operands[2])); | |
5494 | DONE; | |
5495 | }) | |
5496 | ||
5497 | (define_insn "mve_vstrwq_scatter_offset_fv4sf_insn" | |
5498 | [(set (mem:BLK (scratch)) | |
5499 | (unspec:BLK | |
5500 | [(match_operand:SI 0 "register_operand" "r") | |
5501 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5502 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
5503 | VSTRWQSO_F))] | |
5504 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5505 | "vstrw.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5506 | [(set_attr "length" "4")]) |
5507 | ||
5508 | ;; | |
5509 | ;; [vstrwq_scatter_offset_p_f] | |
5510 | ;; | |
9a810e57 SP |
5511 | (define_expand "mve_vstrwq_scatter_offset_p_fv4sf" |
5512 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5513 | (match_operand:V4SI 1 "s_register_operand") | |
5514 | (match_operand:V4SF 2 "s_register_operand") | |
6a7c13a0 | 5515 | (match_operand:V4BI 3 "vpr_register_operand") |
9a810e57 | 5516 | (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] |
7a5fffa5 SP |
5517 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5518 | { | |
9a810e57 SP |
5519 | rtx ind = XEXP (operands[0], 0); |
5520 | gcc_assert (REG_P (ind)); | |
5521 | emit_insn (gen_mve_vstrwq_scatter_offset_p_fv4sf_insn (ind, operands[1], | |
5522 | operands[2], | |
5523 | operands[3])); | |
5524 | DONE; | |
5525 | }) | |
5526 | ||
5527 | (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" | |
5528 | [(set (mem:BLK (scratch)) | |
5529 | (unspec:BLK | |
5530 | [(match_operand:SI 0 "register_operand" "r") | |
5531 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5532 | (match_operand:V4SF 2 "s_register_operand" "w") | |
6a7c13a0 | 5533 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5534 | VSTRWQSO_F))] |
5535 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5536 | "vpst\;vstrwt.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5537 | [(set_attr "length" "8")]) |
5538 | ||
5539 | ;; | |
9a810e57 | 5540 | ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] |
7a5fffa5 | 5541 | ;; |
9a810e57 SP |
5542 | (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" |
5543 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5544 | (match_operand:V4SI 1 "s_register_operand") | |
5545 | (match_operand:V4SI 2 "s_register_operand") | |
6a7c13a0 | 5546 | (match_operand:V4BI 3 "vpr_register_operand") |
9a810e57 | 5547 | (unspec:V4SI [(const_int 0)] VSTRWSOQ)] |
7a5fffa5 SP |
5548 | "TARGET_HAVE_MVE" |
5549 | { | |
9a810e57 SP |
5550 | rtx ind = XEXP (operands[0], 0); |
5551 | gcc_assert (REG_P (ind)); | |
5552 | emit_insn (gen_mve_vstrwq_scatter_offset_p_<supf>v4si_insn (ind, operands[1], | |
5553 | operands[2], | |
5554 | operands[3])); | |
5555 | DONE; | |
5556 | }) | |
5557 | ||
5558 | (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" | |
5559 | [(set (mem:BLK (scratch)) | |
5560 | (unspec:BLK | |
5561 | [(match_operand:SI 0 "register_operand" "r") | |
5562 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5563 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 5564 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5565 | VSTRWSOQ))] |
5566 | "TARGET_HAVE_MVE" | |
5567 | "vpst\;vstrwt.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5568 | [(set_attr "length" "8")]) |
5569 | ||
5570 | ;; | |
5571 | ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] | |
5572 | ;; | |
9a810e57 SP |
5573 | (define_expand "mve_vstrwq_scatter_offset_<supf>v4si" |
5574 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5575 | (match_operand:V4SI 1 "s_register_operand") | |
5576 | (match_operand:V4SI 2 "s_register_operand") | |
5577 | (unspec:V4SI [(const_int 0)] VSTRWSOQ)] | |
7a5fffa5 SP |
5578 | "TARGET_HAVE_MVE" |
5579 | { | |
9a810e57 SP |
5580 | rtx ind = XEXP (operands[0], 0); |
5581 | gcc_assert (REG_P (ind)); | |
5582 | emit_insn (gen_mve_vstrwq_scatter_offset_<supf>v4si_insn (ind, operands[1], | |
5583 | operands[2])); | |
5584 | DONE; | |
5585 | }) | |
5586 | ||
5587 | (define_insn "mve_vstrwq_scatter_offset_<supf>v4si_insn" | |
5588 | [(set (mem:BLK (scratch)) | |
5589 | (unspec:BLK | |
5590 | [(match_operand:SI 0 "register_operand" "r") | |
5591 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5592 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
5593 | VSTRWSOQ))] | |
5594 | "TARGET_HAVE_MVE" | |
5595 | "vstrw.32\t%q2, [%0, %q1]" | |
7a5fffa5 SP |
5596 | [(set_attr "length" "4")]) |
5597 | ||
5598 | ;; | |
5599 | ;; [vstrwq_scatter_shifted_offset_f] | |
5600 | ;; | |
9a810e57 SP |
5601 | (define_expand "mve_vstrwq_scatter_shifted_offset_fv4sf" |
5602 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5603 | (match_operand:V4SI 1 "s_register_operand") | |
5604 | (match_operand:V4SF 2 "s_register_operand") | |
5605 | (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] | |
7a5fffa5 SP |
5606 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5607 | { | |
9a810e57 SP |
5608 | rtx ind = XEXP (operands[0], 0); |
5609 | gcc_assert (REG_P (ind)); | |
5610 | emit_insn (gen_mve_vstrwq_scatter_shifted_offset_fv4sf_insn (ind, operands[1], | |
5611 | operands[2])); | |
5612 | DONE; | |
5613 | }) | |
5614 | ||
5615 | (define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf_insn" | |
5616 | [(set (mem:BLK (scratch)) | |
5617 | (unspec:BLK | |
5618 | [(match_operand:SI 0 "register_operand" "r") | |
5619 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5620 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
5621 | VSTRWQSSO_F))] | |
5622 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5623 | "vstrw.32\t%q2, [%0, %q1, uxtw #2]" | |
5624 | [(set_attr "length" "8")]) | |
7a5fffa5 SP |
5625 | |
5626 | ;; | |
5627 | ;; [vstrwq_scatter_shifted_offset_p_f] | |
5628 | ;; | |
9a810e57 SP |
5629 | (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" |
5630 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5631 | (match_operand:V4SI 1 "s_register_operand") | |
5632 | (match_operand:V4SF 2 "s_register_operand") | |
6a7c13a0 | 5633 | (match_operand:V4BI 3 "vpr_register_operand") |
9a810e57 | 5634 | (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] |
7a5fffa5 SP |
5635 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" |
5636 | { | |
9a810e57 SP |
5637 | rtx ind = XEXP (operands[0], 0); |
5638 | gcc_assert (REG_P (ind)); | |
5639 | emit_insn ( | |
5640 | gen_mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn (ind, operands[1], | |
5641 | operands[2], | |
5642 | operands[3])); | |
5643 | DONE; | |
5644 | }) | |
5645 | ||
5646 | (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" | |
5647 | [(set (mem:BLK (scratch)) | |
5648 | (unspec:BLK | |
5649 | [(match_operand:SI 0 "register_operand" "r") | |
5650 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5651 | (match_operand:V4SF 2 "s_register_operand" "w") | |
6a7c13a0 | 5652 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5653 | VSTRWQSSO_F))] |
5654 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
5655 | "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 SP |
5656 | [(set_attr "length" "8")]) |
5657 | ||
5658 | ;; | |
5659 | ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u] | |
5660 | ;; | |
9a810e57 SP |
5661 | (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" |
5662 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5663 | (match_operand:V4SI 1 "s_register_operand") | |
5664 | (match_operand:V4SI 2 "s_register_operand") | |
6a7c13a0 | 5665 | (match_operand:V4BI 3 "vpr_register_operand") |
9a810e57 | 5666 | (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] |
7a5fffa5 SP |
5667 | "TARGET_HAVE_MVE" |
5668 | { | |
9a810e57 SP |
5669 | rtx ind = XEXP (operands[0], 0); |
5670 | gcc_assert (REG_P (ind)); | |
5671 | emit_insn ( | |
5672 | gen_mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn (ind, operands[1], | |
5673 | operands[2], | |
5674 | operands[3])); | |
5675 | DONE; | |
5676 | }) | |
5677 | ||
5678 | (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" | |
5679 | [(set (mem:BLK (scratch)) | |
5680 | (unspec:BLK | |
5681 | [(match_operand:SI 0 "register_operand" "r") | |
5682 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5683 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6a7c13a0 | 5684 | (match_operand:V4BI 3 "vpr_register_operand" "Up")] |
9a810e57 SP |
5685 | VSTRWSSOQ))] |
5686 | "TARGET_HAVE_MVE" | |
5687 | "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 SP |
5688 | [(set_attr "length" "8")]) |
5689 | ||
5690 | ;; | |
5691 | ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u] | |
5692 | ;; | |
9a810e57 SP |
5693 | (define_expand "mve_vstrwq_scatter_shifted_offset_<supf>v4si" |
5694 | [(match_operand:V4SI 0 "mve_scatter_memory") | |
5695 | (match_operand:V4SI 1 "s_register_operand") | |
5696 | (match_operand:V4SI 2 "s_register_operand") | |
5697 | (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] | |
7a5fffa5 SP |
5698 | "TARGET_HAVE_MVE" |
5699 | { | |
9a810e57 SP |
5700 | rtx ind = XEXP (operands[0], 0); |
5701 | gcc_assert (REG_P (ind)); | |
5702 | emit_insn ( | |
5703 | gen_mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn (ind, operands[1], | |
5704 | operands[2])); | |
5705 | DONE; | |
5706 | }) | |
5707 | ||
5708 | (define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn" | |
5709 | [(set (mem:BLK (scratch)) | |
5710 | (unspec:BLK | |
5711 | [(match_operand:SI 0 "register_operand" "r") | |
5712 | (match_operand:V4SI 1 "s_register_operand" "w") | |
5713 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
5714 | VSTRWSSOQ))] | |
5715 | "TARGET_HAVE_MVE" | |
5716 | "vstrw.32\t%q2, [%0, %q1, uxtw #2]" | |
7a5fffa5 | 5717 | [(set_attr "length" "4")]) |
3eff57aa | 5718 | |
92f80065 SP |
5719 | ;; |
5720 | ;; [vidupq_n_u]) | |
5721 | ;; | |
5722 | (define_expand "mve_vidupq_n_u<mode>" | |
5723 | [(match_operand:MVE_2 0 "s_register_operand") | |
5724 | (match_operand:SI 1 "s_register_operand") | |
5725 | (match_operand:SI 2 "mve_imm_selective_upto_8")] | |
5726 | "TARGET_HAVE_MVE" | |
5727 | { | |
5728 | rtx temp = gen_reg_rtx (SImode); | |
5729 | emit_move_insn (temp, operands[1]); | |
5730 | rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); | |
5731 | emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1], | |
5732 | operands[2], inc)); | |
5733 | DONE; | |
5734 | }) | |
5735 | ||
5736 | ;; | |
5737 | ;; [vidupq_u_insn]) | |
5738 | ;; | |
5739 | (define_insn "mve_vidupq_u<mode>_insn" | |
5740 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5741 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
5742 | (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] | |
5743 | VIDUPQ)) | |
3d537943 | 5744 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
5745 | (plus:SI (match_dup 2) |
5746 | (match_operand:SI 4 "immediate_operand" "i")))] | |
5747 | "TARGET_HAVE_MVE" | |
5748 | "vidup.u%#<V_sz_elem>\t%q0, %1, %3") | |
5749 | ||
5750 | ;; | |
5751 | ;; [vidupq_m_n_u]) | |
5752 | ;; | |
5753 | (define_expand "mve_vidupq_m_n_u<mode>" | |
5754 | [(match_operand:MVE_2 0 "s_register_operand") | |
5755 | (match_operand:MVE_2 1 "s_register_operand") | |
5756 | (match_operand:SI 2 "s_register_operand") | |
5757 | (match_operand:SI 3 "mve_imm_selective_upto_8") | |
724d6566 | 5758 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] |
92f80065 SP |
5759 | "TARGET_HAVE_MVE" |
5760 | { | |
5761 | rtx temp = gen_reg_rtx (SImode); | |
5762 | emit_move_insn (temp, operands[2]); | |
5763 | rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); | |
5764 | emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, | |
5765 | operands[2], operands[3], | |
5766 | operands[4], inc)); | |
5767 | DONE; | |
5768 | }) | |
5769 | ||
5770 | ;; | |
5771 | ;; [vidupq_m_wb_u_insn]) | |
5772 | ;; | |
5773 | (define_insn "mve_vidupq_m_wb_u<mode>_insn" | |
5774 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5775 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5776 | (match_operand:SI 3 "s_register_operand" "2") | |
5777 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") | |
724d6566 | 5778 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] |
92f80065 | 5779 | VIDUPQ_M)) |
3d537943 | 5780 | (set (match_operand:SI 2 "s_register_operand" "=Te") |
92f80065 SP |
5781 | (plus:SI (match_dup 3) |
5782 | (match_operand:SI 6 "immediate_operand" "i")))] | |
5783 | "TARGET_HAVE_MVE" | |
5784 | "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4" | |
5785 | [(set_attr "length""8")]) | |
5786 | ||
5787 | ;; | |
5788 | ;; [vddupq_n_u]) | |
5789 | ;; | |
5790 | (define_expand "mve_vddupq_n_u<mode>" | |
5791 | [(match_operand:MVE_2 0 "s_register_operand") | |
5792 | (match_operand:SI 1 "s_register_operand") | |
5793 | (match_operand:SI 2 "mve_imm_selective_upto_8")] | |
5794 | "TARGET_HAVE_MVE" | |
5795 | { | |
5796 | rtx temp = gen_reg_rtx (SImode); | |
5797 | emit_move_insn (temp, operands[1]); | |
5798 | rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); | |
5799 | emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1], | |
5800 | operands[2], inc)); | |
5801 | DONE; | |
5802 | }) | |
5803 | ||
5804 | ;; | |
5805 | ;; [vddupq_u_insn]) | |
5806 | ;; | |
5807 | (define_insn "mve_vddupq_u<mode>_insn" | |
5808 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5809 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
5810 | (match_operand:SI 3 "immediate_operand" "i")] | |
5811 | VDDUPQ)) | |
3d537943 | 5812 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
5813 | (minus:SI (match_dup 2) |
5814 | (match_operand:SI 4 "immediate_operand" "i")))] | |
5815 | "TARGET_HAVE_MVE" | |
f3f4295a | 5816 | "vddup.u%#<V_sz_elem>\t%q0, %1, %3") |
92f80065 SP |
5817 | |
5818 | ;; | |
5819 | ;; [vddupq_m_n_u]) | |
5820 | ;; | |
5821 | (define_expand "mve_vddupq_m_n_u<mode>" | |
5822 | [(match_operand:MVE_2 0 "s_register_operand") | |
5823 | (match_operand:MVE_2 1 "s_register_operand") | |
5824 | (match_operand:SI 2 "s_register_operand") | |
5825 | (match_operand:SI 3 "mve_imm_selective_upto_8") | |
724d6566 | 5826 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] |
92f80065 SP |
5827 | "TARGET_HAVE_MVE" |
5828 | { | |
5829 | rtx temp = gen_reg_rtx (SImode); | |
5830 | emit_move_insn (temp, operands[2]); | |
5831 | rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); | |
5832 | emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, | |
5833 | operands[2], operands[3], | |
5834 | operands[4], inc)); | |
5835 | DONE; | |
5836 | }) | |
5837 | ||
5838 | ;; | |
5839 | ;; [vddupq_m_wb_u_insn]) | |
5840 | ;; | |
5841 | (define_insn "mve_vddupq_m_wb_u<mode>_insn" | |
5842 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5843 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
5844 | (match_operand:SI 3 "s_register_operand" "2") | |
5845 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") | |
724d6566 | 5846 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] |
92f80065 | 5847 | VDDUPQ_M)) |
3d537943 | 5848 | (set (match_operand:SI 2 "s_register_operand" "=Te") |
92f80065 SP |
5849 | (minus:SI (match_dup 3) |
5850 | (match_operand:SI 6 "immediate_operand" "i")))] | |
5851 | "TARGET_HAVE_MVE" | |
f3f4295a | 5852 | "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4" |
92f80065 SP |
5853 | [(set_attr "length""8")]) |
5854 | ||
5855 | ;; | |
5856 | ;; [vdwdupq_n_u]) | |
5857 | ;; | |
5858 | (define_expand "mve_vdwdupq_n_u<mode>" | |
5859 | [(match_operand:MVE_2 0 "s_register_operand") | |
5860 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 5861 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
5862 | (match_operand:SI 3 "mve_imm_selective_upto_8")] |
5863 | "TARGET_HAVE_MVE" | |
5864 | { | |
5865 | rtx ignore_wb = gen_reg_rtx (SImode); | |
5866 | emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb, | |
5867 | operands[1], operands[2], | |
5868 | operands[3])); | |
5869 | DONE; | |
5870 | }) | |
5871 | ||
5872 | ;; | |
5873 | ;; [vdwdupq_wb_u]) | |
5874 | ;; | |
5875 | (define_expand "mve_vdwdupq_wb_u<mode>" | |
5876 | [(match_operand:SI 0 "s_register_operand") | |
5877 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 5878 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
5879 | (match_operand:SI 3 "mve_imm_selective_upto_8") |
5880 | (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
5881 | "TARGET_HAVE_MVE" | |
5882 | { | |
5883 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
5884 | emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0], | |
5885 | operands[1], operands[2], | |
5886 | operands[3])); | |
5887 | DONE; | |
5888 | }) | |
5889 | ||
5890 | ;; | |
5891 | ;; [vdwdupq_wb_u_insn]) | |
5892 | ;; | |
5893 | (define_insn "mve_vdwdupq_wb_u<mode>_insn" | |
5894 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
5895 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9ce780ef | 5896 | (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) |
92f80065 SP |
5897 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] |
5898 | VDWDUPQ)) | |
3d537943 | 5899 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 | 5900 | (unspec:SI [(match_dup 2) |
9ce780ef | 5901 | (subreg:SI (match_dup 3) 4) |
92f80065 SP |
5902 | (match_dup 4)] |
5903 | VDWDUPQ))] | |
5904 | "TARGET_HAVE_MVE" | |
9ce780ef | 5905 | "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" |
92f80065 SP |
5906 | ) |
5907 | ||
5908 | ;; | |
5909 | ;; [vdwdupq_m_n_u]) | |
5910 | ;; | |
5911 | (define_expand "mve_vdwdupq_m_n_u<mode>" | |
5912 | [(match_operand:MVE_2 0 "s_register_operand") | |
5913 | (match_operand:MVE_2 1 "s_register_operand") | |
5914 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 5915 | (match_operand:DI 3 "s_register_operand") |
92f80065 | 5916 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
724d6566 | 5917 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] |
92f80065 SP |
5918 | "TARGET_HAVE_MVE" |
5919 | { | |
5920 | rtx ignore_wb = gen_reg_rtx (SImode); | |
5921 | emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, | |
5922 | operands[1], operands[2], | |
5923 | operands[3], operands[4], | |
5924 | operands[5])); | |
5925 | DONE; | |
5926 | }) | |
5927 | ||
5928 | ;; | |
5929 | ;; [vdwdupq_m_wb_u]) | |
5930 | ;; | |
5931 | (define_expand "mve_vdwdupq_m_wb_u<mode>" | |
5932 | [(match_operand:SI 0 "s_register_operand") | |
5933 | (match_operand:MVE_2 1 "s_register_operand") | |
5934 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 5935 | (match_operand:DI 3 "s_register_operand") |
92f80065 | 5936 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
724d6566 | 5937 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] |
92f80065 SP |
5938 | "TARGET_HAVE_MVE" |
5939 | { | |
5940 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
5941 | emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], | |
5942 | operands[1], operands[2], | |
5943 | operands[3], operands[4], | |
5944 | operands[5])); | |
5945 | DONE; | |
5946 | }) | |
5947 | ||
5948 | ;; | |
5949 | ;; [vdwdupq_m_wb_u_insn]) | |
5950 | ;; | |
5951 | (define_insn "mve_vdwdupq_m_wb_u<mode>_insn" | |
5952 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9ce780ef | 5953 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") |
92f80065 | 5954 | (match_operand:SI 3 "s_register_operand" "1") |
9ce780ef | 5955 | (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) |
92f80065 | 5956 | (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") |
724d6566 | 5957 | (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] |
92f80065 | 5958 | VDWDUPQ_M)) |
3d537943 | 5959 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
5960 | (unspec:SI [(match_dup 2) |
5961 | (match_dup 3) | |
9ce780ef | 5962 | (subreg:SI (match_dup 4) 4) |
92f80065 SP |
5963 | (match_dup 5) |
5964 | (match_dup 6)] | |
5965 | VDWDUPQ_M)) | |
5966 | ] | |
5967 | "TARGET_HAVE_MVE" | |
d5cc5a6d | 5968 | "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" |
92f80065 SP |
5969 | [(set_attr "type" "mve_move") |
5970 | (set_attr "length""8")]) | |
5971 | ||
5972 | ;; | |
5973 | ;; [viwdupq_n_u]) | |
5974 | ;; | |
5975 | (define_expand "mve_viwdupq_n_u<mode>" | |
5976 | [(match_operand:MVE_2 0 "s_register_operand") | |
5977 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 5978 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
5979 | (match_operand:SI 3 "mve_imm_selective_upto_8")] |
5980 | "TARGET_HAVE_MVE" | |
5981 | { | |
5982 | rtx ignore_wb = gen_reg_rtx (SImode); | |
5983 | emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb, | |
5984 | operands[1], operands[2], | |
5985 | operands[3])); | |
5986 | DONE; | |
5987 | }) | |
5988 | ||
5989 | ;; | |
5990 | ;; [viwdupq_wb_u]) | |
5991 | ;; | |
5992 | (define_expand "mve_viwdupq_wb_u<mode>" | |
5993 | [(match_operand:SI 0 "s_register_operand") | |
5994 | (match_operand:SI 1 "s_register_operand") | |
9ce780ef | 5995 | (match_operand:DI 2 "s_register_operand") |
92f80065 SP |
5996 | (match_operand:SI 3 "mve_imm_selective_upto_8") |
5997 | (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
5998 | "TARGET_HAVE_MVE" | |
5999 | { | |
6000 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
6001 | emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0], | |
6002 | operands[1], operands[2], | |
6003 | operands[3])); | |
6004 | DONE; | |
6005 | }) | |
6006 | ||
6007 | ;; | |
6008 | ;; [viwdupq_wb_u_insn]) | |
6009 | ;; | |
6010 | (define_insn "mve_viwdupq_wb_u<mode>_insn" | |
6011 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
6012 | (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") | |
9ce780ef | 6013 | (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) |
92f80065 SP |
6014 | (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] |
6015 | VIWDUPQ)) | |
3d537943 | 6016 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 | 6017 | (unspec:SI [(match_dup 2) |
9ce780ef | 6018 | (subreg:SI (match_dup 3) 4) |
92f80065 SP |
6019 | (match_dup 4)] |
6020 | VIWDUPQ))] | |
6021 | "TARGET_HAVE_MVE" | |
9ce780ef | 6022 | "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" |
92f80065 SP |
6023 | ) |
6024 | ||
6025 | ;; | |
6026 | ;; [viwdupq_m_n_u]) | |
6027 | ;; | |
6028 | (define_expand "mve_viwdupq_m_n_u<mode>" | |
6029 | [(match_operand:MVE_2 0 "s_register_operand") | |
6030 | (match_operand:MVE_2 1 "s_register_operand") | |
6031 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 6032 | (match_operand:DI 3 "s_register_operand") |
92f80065 | 6033 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
724d6566 | 6034 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] |
92f80065 SP |
6035 | "TARGET_HAVE_MVE" |
6036 | { | |
6037 | rtx ignore_wb = gen_reg_rtx (SImode); | |
6038 | emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, | |
6039 | operands[1], operands[2], | |
6040 | operands[3], operands[4], | |
6041 | operands[5])); | |
6042 | DONE; | |
6043 | }) | |
6044 | ||
6045 | ;; | |
6046 | ;; [viwdupq_m_wb_u]) | |
6047 | ;; | |
6048 | (define_expand "mve_viwdupq_m_wb_u<mode>" | |
6049 | [(match_operand:SI 0 "s_register_operand") | |
6050 | (match_operand:MVE_2 1 "s_register_operand") | |
6051 | (match_operand:SI 2 "s_register_operand") | |
9ce780ef | 6052 | (match_operand:DI 3 "s_register_operand") |
92f80065 | 6053 | (match_operand:SI 4 "mve_imm_selective_upto_8") |
724d6566 | 6054 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] |
92f80065 SP |
6055 | "TARGET_HAVE_MVE" |
6056 | { | |
6057 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
6058 | emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], | |
6059 | operands[1], operands[2], | |
6060 | operands[3], operands[4], | |
6061 | operands[5])); | |
6062 | DONE; | |
6063 | }) | |
6064 | ||
6065 | ;; | |
6066 | ;; [viwdupq_m_wb_u_insn]) | |
6067 | ;; | |
6068 | (define_insn "mve_viwdupq_m_wb_u<mode>_insn" | |
6069 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
9ce780ef | 6070 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") |
92f80065 | 6071 | (match_operand:SI 3 "s_register_operand" "1") |
9ce780ef | 6072 | (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) |
92f80065 | 6073 | (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") |
724d6566 | 6074 | (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] |
92f80065 | 6075 | VIWDUPQ_M)) |
3d537943 | 6076 | (set (match_operand:SI 1 "s_register_operand" "=Te") |
92f80065 SP |
6077 | (unspec:SI [(match_dup 2) |
6078 | (match_dup 3) | |
9ce780ef | 6079 | (subreg:SI (match_dup 4) 4) |
92f80065 SP |
6080 | (match_dup 5) |
6081 | (match_dup 6)] | |
6082 | VIWDUPQ_M)) | |
6083 | ] | |
6084 | "TARGET_HAVE_MVE" | |
9ce780ef | 6085 | "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" |
92f80065 SP |
6086 | [(set_attr "type" "mve_move") |
6087 | (set_attr "length""8")]) | |
9ce780ef | 6088 | |
41e1a7ff | 6089 | ;; |
37753588 | 6090 | ;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u] |
41e1a7ff | 6091 | ;; |
37753588 | 6092 | (define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si" |
41e1a7ff SP |
6093 | [(set (mem:BLK (scratch)) |
6094 | (unspec:BLK | |
6095 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
6096 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6097 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
6098 | VSTRWSBWBQ)) | |
6099 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6100 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
6101 | VSTRWSBWBQ)) | |
6102 | ] | |
6103 | "TARGET_HAVE_MVE" | |
6104 | { | |
6105 | rtx ops[3]; | |
6106 | ops[0] = operands[1]; | |
6107 | ops[1] = operands[2]; | |
6108 | ops[2] = operands[3]; | |
6109 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); | |
6110 | return ""; | |
6111 | } | |
6112 | [(set_attr "length" "4")]) | |
6113 | ||
41e1a7ff SP |
6114 | ;; |
6115 | ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] | |
6116 | ;; | |
37753588 | 6117 | (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" |
41e1a7ff SP |
6118 | [(set (mem:BLK (scratch)) |
6119 | (unspec:BLK | |
6120 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
6121 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6122 | (match_operand:V4SI 3 "s_register_operand" "w") | |
6a7c13a0 | 6123 | (match_operand:V4BI 4 "vpr_register_operand")] |
41e1a7ff SP |
6124 | VSTRWSBWBQ)) |
6125 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6126 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
6127 | VSTRWSBWBQ)) | |
6128 | ] | |
6129 | "TARGET_HAVE_MVE" | |
6130 | { | |
6131 | rtx ops[3]; | |
6132 | ops[0] = operands[1]; | |
6133 | ops[1] = operands[2]; | |
6134 | ops[2] = operands[3]; | |
6135 | output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); | |
6136 | return ""; | |
6137 | } | |
6138 | [(set_attr "length" "8")]) | |
6139 | ||
41e1a7ff SP |
6140 | ;; |
6141 | ;; [vstrwq_scatter_base_wb_f] | |
6142 | ;; | |
37753588 | 6143 | (define_insn "mve_vstrwq_scatter_base_wb_fv4sf" |
41e1a7ff SP |
6144 | [(set (mem:BLK (scratch)) |
6145 | (unspec:BLK | |
6146 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
6147 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6148 | (match_operand:V4SF 3 "s_register_operand" "w")] | |
6149 | VSTRWQSBWB_F)) | |
6150 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6151 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
6152 | VSTRWQSBWB_F)) | |
6153 | ] | |
6154 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6155 | { | |
6156 | rtx ops[3]; | |
6157 | ops[0] = operands[1]; | |
6158 | ops[1] = operands[2]; | |
6159 | ops[2] = operands[3]; | |
6160 | output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); | |
6161 | return ""; | |
6162 | } | |
6163 | [(set_attr "length" "4")]) | |
6164 | ||
41e1a7ff SP |
6165 | ;; |
6166 | ;; [vstrwq_scatter_base_wb_p_f] | |
6167 | ;; | |
37753588 | 6168 | (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" |
41e1a7ff SP |
6169 | [(set (mem:BLK (scratch)) |
6170 | (unspec:BLK | |
6171 | [(match_operand:V4SI 1 "s_register_operand" "0") | |
6172 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6173 | (match_operand:V4SF 3 "s_register_operand" "w") | |
6a7c13a0 | 6174 | (match_operand:V4BI 4 "vpr_register_operand")] |
41e1a7ff SP |
6175 | VSTRWQSBWB_F)) |
6176 | (set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6177 | (unspec:V4SI [(match_dup 1) (match_dup 2)] | |
6178 | VSTRWQSBWB_F)) | |
6179 | ] | |
6180 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6181 | { | |
6182 | rtx ops[3]; | |
6183 | ops[0] = operands[1]; | |
6184 | ops[1] = operands[2]; | |
6185 | ops[2] = operands[3]; | |
6186 | output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); | |
6187 | return ""; | |
6188 | } | |
6189 | [(set_attr "length" "8")]) | |
6190 | ||
41e1a7ff SP |
6191 | ;; |
6192 | ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] | |
6193 | ;; | |
37753588 | 6194 | (define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di" |
41e1a7ff SP |
6195 | [(set (mem:BLK (scratch)) |
6196 | (unspec:BLK | |
6197 | [(match_operand:V2DI 1 "s_register_operand" "0") | |
6198 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6199 | (match_operand:V2DI 3 "s_register_operand" "w")] | |
6200 | VSTRDSBWBQ)) | |
6201 | (set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
6202 | (unspec:V2DI [(match_dup 1) (match_dup 2)] | |
6203 | VSTRDSBWBQ)) | |
6204 | ] | |
6205 | "TARGET_HAVE_MVE" | |
6206 | { | |
6207 | rtx ops[3]; | |
6208 | ops[0] = operands[1]; | |
6209 | ops[1] = operands[2]; | |
6210 | ops[2] = operands[3]; | |
6211 | output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops); | |
6212 | return ""; | |
6213 | } | |
6214 | [(set_attr "length" "4")]) | |
6215 | ||
41e1a7ff SP |
6216 | ;; |
6217 | ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] | |
6218 | ;; | |
37753588 | 6219 | (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di" |
41e1a7ff SP |
6220 | [(set (mem:BLK (scratch)) |
6221 | (unspec:BLK | |
6222 | [(match_operand:V2DI 1 "s_register_operand" "0") | |
6223 | (match_operand:SI 2 "mve_vldrd_immediate" "Ri") | |
6224 | (match_operand:V2DI 3 "s_register_operand" "w") | |
e0bc13d3 | 6225 | (match_operand:V2QI 4 "vpr_register_operand")] |
41e1a7ff SP |
6226 | VSTRDSBWBQ)) |
6227 | (set (match_operand:V2DI 0 "s_register_operand" "=w") | |
6228 | (unspec:V2DI [(match_dup 1) (match_dup 2)] | |
6229 | VSTRDSBWBQ)) | |
6230 | ] | |
6231 | "TARGET_HAVE_MVE" | |
6232 | { | |
6233 | rtx ops[3]; | |
6234 | ops[0] = operands[1]; | |
6235 | ops[1] = operands[2]; | |
6236 | ops[2] = operands[3]; | |
37753588 | 6237 | output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops); |
41e1a7ff SP |
6238 | return ""; |
6239 | } | |
6240 | [(set_attr "length" "8")]) | |
6241 | ||
6242 | (define_expand "mve_vldrwq_gather_base_wb_<supf>v4si" | |
6243 | [(match_operand:V4SI 0 "s_register_operand") | |
6244 | (match_operand:V4SI 1 "s_register_operand") | |
6245 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6246 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
6247 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
6248 | { |
6249 | rtx ignore_result = gen_reg_rtx (V4SImode); | |
6250 | emit_insn ( | |
6251 | gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0], | |
6252 | operands[1], operands[2])); | |
6253 | DONE; | |
6254 | }) | |
6255 | ||
6256 | (define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si" | |
6257 | [(match_operand:V4SI 0 "s_register_operand") | |
6258 | (match_operand:V4SI 1 "s_register_operand") | |
6259 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6260 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] | |
6261 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
6262 | { |
6263 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
6264 | emit_insn ( | |
6265 | gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb, | |
6266 | operands[1], operands[2])); | |
6267 | DONE; | |
6268 | }) | |
6269 | ||
6270 | ;; | |
6271 | ;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u] | |
6272 | ;; | |
6273 | (define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn" | |
6274 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
6275 | (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") | |
6276 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
6277 | (mem:BLK (scratch))] | |
6278 | VLDRWGBWBQ)) | |
6279 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
6280 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
6281 | VLDRWGBWBQ)) | |
6282 | ] | |
6283 | "TARGET_HAVE_MVE" | |
6284 | { | |
6285 | rtx ops[3]; | |
6286 | ops[0] = operands[0]; | |
6287 | ops[1] = operands[2]; | |
6288 | ops[2] = operands[3]; | |
6289 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); | |
6290 | return ""; | |
6291 | } | |
6292 | [(set_attr "length" "4")]) | |
6293 | ||
6294 | (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" | |
6295 | [(match_operand:V4SI 0 "s_register_operand") | |
6296 | (match_operand:V4SI 1 "s_register_operand") | |
6297 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6a7c13a0 | 6298 | (match_operand:V4BI 3 "vpr_register_operand") |
41e1a7ff SP |
6299 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] |
6300 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
6301 | { |
6302 | rtx ignore_result = gen_reg_rtx (V4SImode); | |
6303 | emit_insn ( | |
6304 | gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0], | |
6305 | operands[1], operands[2], | |
6306 | operands[3])); | |
6307 | DONE; | |
6308 | }) | |
6309 | (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" | |
6310 | [(match_operand:V4SI 0 "s_register_operand") | |
6311 | (match_operand:V4SI 1 "s_register_operand") | |
6312 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6a7c13a0 | 6313 | (match_operand:V4BI 3 "vpr_register_operand") |
ff825b81 SP |
6314 | (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] |
6315 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
6316 | { |
6317 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
6318 | emit_insn ( | |
6319 | gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb, | |
6320 | operands[1], operands[2], | |
6321 | operands[3])); | |
6322 | DONE; | |
6323 | }) | |
6324 | ||
6325 | ;; | |
6326 | ;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u] | |
6327 | ;; | |
6328 | (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" | |
6329 | [(set (match_operand:V4SI 0 "s_register_operand" "=&w") | |
6330 | (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") | |
6331 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
6a7c13a0 | 6332 | (match_operand:V4BI 4 "vpr_register_operand" "Up") |
41e1a7ff SP |
6333 | (mem:BLK (scratch))] |
6334 | VLDRWGBWBQ)) | |
6335 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
6336 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
6337 | VLDRWGBWBQ)) | |
6338 | ] | |
6339 | "TARGET_HAVE_MVE" | |
6340 | { | |
6341 | rtx ops[3]; | |
6342 | ops[0] = operands[0]; | |
6343 | ops[1] = operands[2]; | |
6344 | ops[2] = operands[3]; | |
ff825b81 | 6345 | output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
6346 | return ""; |
6347 | } | |
6348 | [(set_attr "length" "8")]) | |
6349 | ||
6350 | (define_expand "mve_vldrwq_gather_base_wb_fv4sf" | |
ff825b81 SP |
6351 | [(match_operand:V4SI 0 "s_register_operand") |
6352 | (match_operand:V4SI 1 "s_register_operand") | |
6353 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6354 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
6355 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6356 | { | |
6357 | rtx ignore_result = gen_reg_rtx (V4SFmode); | |
6358 | emit_insn ( | |
6359 | gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0], | |
6360 | operands[1], operands[2])); | |
6361 | DONE; | |
6362 | }) | |
6363 | ||
6364 | (define_expand "mve_vldrwq_gather_base_nowb_fv4sf" | |
41e1a7ff SP |
6365 | [(match_operand:V4SF 0 "s_register_operand") |
6366 | (match_operand:V4SI 1 "s_register_operand") | |
6367 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6368 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] | |
6369 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6370 | { | |
6371 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
6372 | emit_insn ( | |
6373 | gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb, | |
6374 | operands[1], operands[2])); | |
6375 | DONE; | |
6376 | }) | |
6377 | ||
6378 | ;; | |
6379 | ;; [vldrwq_gather_base_wb_f] | |
6380 | ;; | |
6381 | (define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn" | |
6382 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
6383 | (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") | |
6384 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
6385 | (mem:BLK (scratch))] | |
6386 | VLDRWQGBWB_F)) | |
6387 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
6388 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
6389 | VLDRWQGBWB_F)) | |
6390 | ] | |
6391 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6392 | { | |
6393 | rtx ops[3]; | |
6394 | ops[0] = operands[0]; | |
6395 | ops[1] = operands[2]; | |
6396 | ops[2] = operands[3]; | |
6397 | output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); | |
6398 | return ""; | |
6399 | } | |
6400 | [(set_attr "length" "4")]) | |
6401 | ||
6402 | (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" | |
ff825b81 SP |
6403 | [(match_operand:V4SI 0 "s_register_operand") |
6404 | (match_operand:V4SI 1 "s_register_operand") | |
6405 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6a7c13a0 | 6406 | (match_operand:V4BI 3 "vpr_register_operand") |
ff825b81 SP |
6407 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] |
6408 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6409 | { | |
6410 | rtx ignore_result = gen_reg_rtx (V4SFmode); | |
6411 | emit_insn ( | |
6412 | gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0], | |
6413 | operands[1], operands[2], | |
6414 | operands[3])); | |
6415 | DONE; | |
6416 | }) | |
6417 | ||
6418 | (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" | |
41e1a7ff SP |
6419 | [(match_operand:V4SF 0 "s_register_operand") |
6420 | (match_operand:V4SI 1 "s_register_operand") | |
6421 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6a7c13a0 | 6422 | (match_operand:V4BI 3 "vpr_register_operand") |
41e1a7ff SP |
6423 | (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] |
6424 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6425 | { | |
6426 | rtx ignore_wb = gen_reg_rtx (V4SImode); | |
6427 | emit_insn ( | |
6428 | gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb, | |
6429 | operands[1], operands[2], | |
6430 | operands[3])); | |
6431 | DONE; | |
6432 | }) | |
6433 | ||
6434 | ;; | |
6435 | ;; [vldrwq_gather_base_wb_z_f] | |
6436 | ;; | |
6437 | (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" | |
6438 | [(set (match_operand:V4SF 0 "s_register_operand" "=&w") | |
6439 | (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") | |
6440 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
6a7c13a0 | 6441 | (match_operand:V4BI 4 "vpr_register_operand" "Up") |
41e1a7ff SP |
6442 | (mem:BLK (scratch))] |
6443 | VLDRWQGBWB_F)) | |
6444 | (set (match_operand:V4SI 1 "s_register_operand" "=&w") | |
6445 | (unspec:V4SI [(match_dup 2) (match_dup 3)] | |
6446 | VLDRWQGBWB_F)) | |
6447 | ] | |
6448 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
6449 | { | |
6450 | rtx ops[3]; | |
6451 | ops[0] = operands[0]; | |
6452 | ops[1] = operands[2]; | |
6453 | ops[2] = operands[3]; | |
ff825b81 | 6454 | output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
6455 | return ""; |
6456 | } | |
6457 | [(set_attr "length" "8")]) | |
6458 | ||
6459 | (define_expand "mve_vldrdq_gather_base_wb_<supf>v2di" | |
6460 | [(match_operand:V2DI 0 "s_register_operand") | |
6461 | (match_operand:V2DI 1 "s_register_operand") | |
6462 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6463 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
6464 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
6465 | { |
6466 | rtx ignore_result = gen_reg_rtx (V2DImode); | |
6467 | emit_insn ( | |
6468 | gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0], | |
6469 | operands[1], operands[2])); | |
6470 | DONE; | |
6471 | }) | |
6472 | ||
6473 | (define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di" | |
6474 | [(match_operand:V2DI 0 "s_register_operand") | |
6475 | (match_operand:V2DI 1 "s_register_operand") | |
6476 | (match_operand:SI 2 "mve_vldrd_immediate") | |
6477 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] | |
6478 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
6479 | { |
6480 | rtx ignore_wb = gen_reg_rtx (V2DImode); | |
6481 | emit_insn ( | |
6482 | gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb, | |
6483 | operands[1], operands[2])); | |
6484 | DONE; | |
6485 | }) | |
6486 | ||
ff825b81 | 6487 | |
41e1a7ff SP |
6488 | ;; |
6489 | ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u] | |
6490 | ;; | |
6491 | (define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn" | |
6492 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
6493 | (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") | |
6494 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
6495 | (mem:BLK (scratch))] | |
6496 | VLDRDGBWBQ)) | |
6497 | (set (match_operand:V2DI 1 "s_register_operand" "=&w") | |
6498 | (unspec:V2DI [(match_dup 2) (match_dup 3)] | |
6499 | VLDRDGBWBQ)) | |
6500 | ] | |
6501 | "TARGET_HAVE_MVE" | |
6502 | { | |
6503 | rtx ops[3]; | |
6504 | ops[0] = operands[0]; | |
6505 | ops[1] = operands[2]; | |
6506 | ops[2] = operands[3]; | |
6507 | output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops); | |
6508 | return ""; | |
6509 | } | |
6510 | [(set_attr "length" "4")]) | |
6511 | ||
6512 | (define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di" | |
6513 | [(match_operand:V2DI 0 "s_register_operand") | |
6514 | (match_operand:V2DI 1 "s_register_operand") | |
6515 | (match_operand:SI 2 "mve_vldrd_immediate") | |
e0bc13d3 | 6516 | (match_operand:V2QI 3 "vpr_register_operand") |
41e1a7ff SP |
6517 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] |
6518 | "TARGET_HAVE_MVE" | |
ff825b81 SP |
6519 | { |
6520 | rtx ignore_result = gen_reg_rtx (V2DImode); | |
6521 | emit_insn ( | |
6522 | gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0], | |
6523 | operands[1], operands[2], | |
6524 | operands[3])); | |
6525 | DONE; | |
6526 | }) | |
6527 | ||
6528 | (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di" | |
6529 | [(match_operand:V2DI 0 "s_register_operand") | |
6530 | (match_operand:V2DI 1 "s_register_operand") | |
6531 | (match_operand:SI 2 "mve_vldrd_immediate") | |
e0bc13d3 | 6532 | (match_operand:V2QI 3 "vpr_register_operand") |
ff825b81 SP |
6533 | (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] |
6534 | "TARGET_HAVE_MVE" | |
41e1a7ff SP |
6535 | { |
6536 | rtx ignore_wb = gen_reg_rtx (V2DImode); | |
6537 | emit_insn ( | |
6538 | gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb, | |
6539 | operands[1], operands[2], | |
6540 | operands[3])); | |
6541 | DONE; | |
6542 | }) | |
6543 | ||
c3562f81 SP |
6544 | (define_insn "get_fpscr_nzcvqc" |
6545 | [(set (match_operand:SI 0 "register_operand" "=r") | |
6546 | (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] | |
6547 | "TARGET_HAVE_MVE" | |
6548 | "vmrs\\t%0, FPSCR_nzcvqc" | |
6549 | [(set_attr "type" "mve_move")]) | |
6550 | ||
6551 | (define_insn "set_fpscr_nzcvqc" | |
6552 | [(set (reg:SI VFPCC_REGNUM) | |
6553 | (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
6554 | VUNSPEC_SET_FPSCR_NZCVQC))] | |
6555 | "TARGET_HAVE_MVE" | |
6556 | "vmsr\\tFPSCR_nzcvqc, %0" | |
6557 | [(set_attr "type" "mve_move")]) | |
6558 | ||
41e1a7ff SP |
6559 | ;; |
6560 | ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] | |
6561 | ;; | |
6562 | (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn" | |
6563 | [(set (match_operand:V2DI 0 "s_register_operand" "=&w") | |
6564 | (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") | |
6565 | (match_operand:SI 3 "mve_vldrd_immediate" "Ri") | |
e0bc13d3 | 6566 | (match_operand:V2QI 4 "vpr_register_operand" "Up") |
41e1a7ff SP |
6567 | (mem:BLK (scratch))] |
6568 | VLDRDGBWBQ)) | |
6569 | (set (match_operand:V2DI 1 "s_register_operand" "=&w") | |
6570 | (unspec:V2DI [(match_dup 2) (match_dup 3)] | |
6571 | VLDRDGBWBQ)) | |
6572 | ] | |
6573 | "TARGET_HAVE_MVE" | |
6574 | { | |
6575 | rtx ops[3]; | |
6576 | ops[0] = operands[0]; | |
6577 | ops[1] = operands[2]; | |
6578 | ops[2] = operands[3]; | |
ff825b81 | 6579 | output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops); |
41e1a7ff SP |
6580 | return ""; |
6581 | } | |
6582 | [(set_attr "length" "8")]) | |
c3562f81 SP |
6583 | ;; |
6584 | ;; [vadciq_m_s, vadciq_m_u]) | |
6585 | ;; | |
6586 | (define_insn "mve_vadciq_m_<supf>v4si" | |
6587 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6588 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") | |
6589 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6590 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 6591 | (match_operand:V4BI 4 "vpr_register_operand" "Up")] |
c3562f81 SP |
6592 | VADCIQ_M)) |
6593 | (set (reg:SI VFPCC_REGNUM) | |
6594 | (unspec:SI [(const_int 0)] | |
6595 | VADCIQ_M)) | |
6596 | ] | |
6597 | "TARGET_HAVE_MVE" | |
6598 | "vpst\;vadcit.i32\t%q0, %q2, %q3" | |
6599 | [(set_attr "type" "mve_move") | |
6600 | (set_attr "length" "8")]) | |
6601 | ||
6602 | ;; | |
6603 | ;; [vadciq_u, vadciq_s]) | |
6604 | ;; | |
6605 | (define_insn "mve_vadciq_<supf>v4si" | |
6606 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6607 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6608 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
6609 | VADCIQ)) | |
6610 | (set (reg:SI VFPCC_REGNUM) | |
6611 | (unspec:SI [(const_int 0)] | |
6612 | VADCIQ)) | |
6613 | ] | |
6614 | "TARGET_HAVE_MVE" | |
6615 | "vadci.i32\t%q0, %q1, %q2" | |
6616 | [(set_attr "type" "mve_move") | |
6617 | (set_attr "length" "4")]) | |
6618 | ||
6619 | ;; | |
6620 | ;; [vadcq_m_s, vadcq_m_u]) | |
6621 | ;; | |
6622 | (define_insn "mve_vadcq_m_<supf>v4si" | |
6623 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6624 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") | |
6625 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6626 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 6627 | (match_operand:V4BI 4 "vpr_register_operand" "Up")] |
c3562f81 SP |
6628 | VADCQ_M)) |
6629 | (set (reg:SI VFPCC_REGNUM) | |
6630 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
6631 | VADCQ_M)) | |
6632 | ] | |
6633 | "TARGET_HAVE_MVE" | |
6634 | "vpst\;vadct.i32\t%q0, %q2, %q3" | |
6635 | [(set_attr "type" "mve_move") | |
6636 | (set_attr "length" "8")]) | |
6637 | ||
6638 | ;; | |
6639 | ;; [vadcq_u, vadcq_s]) | |
6640 | ;; | |
6641 | (define_insn "mve_vadcq_<supf>v4si" | |
6642 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6643 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6644 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
6645 | VADCQ)) | |
6646 | (set (reg:SI VFPCC_REGNUM) | |
6647 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
6648 | VADCQ)) | |
6649 | ] | |
6650 | "TARGET_HAVE_MVE" | |
6651 | "vadc.i32\t%q0, %q1, %q2" | |
6652 | [(set_attr "type" "mve_move") | |
6653 | (set_attr "length" "4") | |
6654 | (set_attr "conds" "set")]) | |
6655 | ||
6656 | ;; | |
6657 | ;; [vsbciq_m_u, vsbciq_m_s]) | |
6658 | ;; | |
6659 | (define_insn "mve_vsbciq_m_<supf>v4si" | |
6660 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6661 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6662 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6663 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 6664 | (match_operand:V4BI 4 "vpr_register_operand" "Up")] |
c3562f81 SP |
6665 | VSBCIQ_M)) |
6666 | (set (reg:SI VFPCC_REGNUM) | |
6667 | (unspec:SI [(const_int 0)] | |
6668 | VSBCIQ_M)) | |
6669 | ] | |
6670 | "TARGET_HAVE_MVE" | |
6671 | "vpst\;vsbcit.i32\t%q0, %q2, %q3" | |
6672 | [(set_attr "type" "mve_move") | |
6673 | (set_attr "length" "8")]) | |
6674 | ||
6675 | ;; | |
6676 | ;; [vsbciq_s, vsbciq_u]) | |
6677 | ;; | |
6678 | (define_insn "mve_vsbciq_<supf>v4si" | |
6679 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6680 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6681 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
6682 | VSBCIQ)) | |
6683 | (set (reg:SI VFPCC_REGNUM) | |
6684 | (unspec:SI [(const_int 0)] | |
6685 | VSBCIQ)) | |
6686 | ] | |
6687 | "TARGET_HAVE_MVE" | |
6688 | "vsbci.i32\t%q0, %q1, %q2" | |
6689 | [(set_attr "type" "mve_move") | |
6690 | (set_attr "length" "4")]) | |
6691 | ||
6692 | ;; | |
6693 | ;; [vsbcq_m_u, vsbcq_m_s]) | |
6694 | ;; | |
6695 | (define_insn "mve_vsbcq_m_<supf>v4si" | |
6696 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6697 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6698 | (match_operand:V4SI 2 "s_register_operand" "w") | |
6699 | (match_operand:V4SI 3 "s_register_operand" "w") | |
c6b4ea7a | 6700 | (match_operand:V4BI 4 "vpr_register_operand" "Up")] |
c3562f81 SP |
6701 | VSBCQ_M)) |
6702 | (set (reg:SI VFPCC_REGNUM) | |
6703 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
6704 | VSBCQ_M)) | |
6705 | ] | |
6706 | "TARGET_HAVE_MVE" | |
6707 | "vpst\;vsbct.i32\t%q0, %q2, %q3" | |
6708 | [(set_attr "type" "mve_move") | |
6709 | (set_attr "length" "8")]) | |
6710 | ||
6711 | ;; | |
6712 | ;; [vsbcq_s, vsbcq_u]) | |
6713 | ;; | |
6714 | (define_insn "mve_vsbcq_<supf>v4si" | |
6715 | [(set (match_operand:V4SI 0 "s_register_operand" "=w") | |
6716 | (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") | |
6717 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
6718 | VSBCQ)) | |
6719 | (set (reg:SI VFPCC_REGNUM) | |
6720 | (unspec:SI [(reg:SI VFPCC_REGNUM)] | |
6721 | VSBCQ)) | |
6722 | ] | |
6723 | "TARGET_HAVE_MVE" | |
6724 | "vsbc.i32\t%q0, %q1, %q2" | |
6725 | [(set_attr "type" "mve_move") | |
6726 | (set_attr "length" "4")]) | |
1dfcc3b5 SP |
6727 | |
6728 | ;; | |
6729 | ;; [vst2q]) | |
6730 | ;; | |
6731 | (define_insn "mve_vst2q<mode>" | |
4269a656 | 6732 | [(set (match_operand:OI 0 "mve_struct_operand" "=Ug") |
1dfcc3b5 SP |
6733 | (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") |
6734 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
6735 | VST2Q)) | |
6736 | ] | |
6737 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6738 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6739 | { | |
6740 | rtx ops[4]; | |
6741 | int regno = REGNO (operands[1]); | |
6742 | ops[0] = gen_rtx_REG (TImode, regno); | |
6743 | ops[1] = gen_rtx_REG (TImode, regno + 4); | |
6744 | rtx reg = operands[0]; | |
6745 | while (reg && !REG_P (reg)) | |
6746 | reg = XEXP (reg, 0); | |
6747 | gcc_assert (REG_P (reg)); | |
6748 | ops[2] = reg; | |
6749 | ops[3] = operands[0]; | |
6750 | output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" | |
6751 | "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops); | |
6752 | return ""; | |
6753 | } | |
6754 | [(set_attr "length" "8")]) | |
6755 | ||
6756 | ;; | |
6757 | ;; [vld2q]) | |
6758 | ;; | |
6759 | (define_insn "mve_vld2q<mode>" | |
6760 | [(set (match_operand:OI 0 "s_register_operand" "=w") | |
4269a656 | 6761 | (unspec:OI [(match_operand:OI 1 "mve_struct_operand" "Ug") |
1dfcc3b5 SP |
6762 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] |
6763 | VLD2Q)) | |
6764 | ] | |
6765 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6766 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6767 | { | |
6768 | rtx ops[4]; | |
6769 | int regno = REGNO (operands[0]); | |
6770 | ops[0] = gen_rtx_REG (TImode, regno); | |
6771 | ops[1] = gen_rtx_REG (TImode, regno + 4); | |
6772 | rtx reg = operands[1]; | |
6773 | while (reg && !REG_P (reg)) | |
6774 | reg = XEXP (reg, 0); | |
6775 | gcc_assert (REG_P (reg)); | |
6776 | ops[2] = reg; | |
6777 | ops[3] = operands[1]; | |
6778 | output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" | |
6779 | "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops); | |
6780 | return ""; | |
6781 | } | |
6782 | [(set_attr "length" "8")]) | |
6783 | ||
6784 | ;; | |
6785 | ;; [vld4q]) | |
6786 | ;; | |
6787 | (define_insn "mve_vld4q<mode>" | |
6788 | [(set (match_operand:XI 0 "s_register_operand" "=w") | |
4269a656 | 6789 | (unspec:XI [(match_operand:XI 1 "mve_struct_operand" "Ug") |
1dfcc3b5 SP |
6790 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] |
6791 | VLD4Q)) | |
6792 | ] | |
6793 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6794 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6795 | { | |
6796 | rtx ops[6]; | |
6797 | int regno = REGNO (operands[0]); | |
6798 | ops[0] = gen_rtx_REG (TImode, regno); | |
6799 | ops[1] = gen_rtx_REG (TImode, regno+4); | |
6800 | ops[2] = gen_rtx_REG (TImode, regno+8); | |
6801 | ops[3] = gen_rtx_REG (TImode, regno + 12); | |
6802 | rtx reg = operands[1]; | |
6803 | while (reg && !REG_P (reg)) | |
6804 | reg = XEXP (reg, 0); | |
6805 | gcc_assert (REG_P (reg)); | |
6806 | ops[4] = reg; | |
6807 | ops[5] = operands[1]; | |
6808 | output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
6809 | "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
6810 | "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
6811 | "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); | |
6812 | return ""; | |
6813 | } | |
6814 | [(set_attr "length" "16")]) | |
1a5c27b1 SP |
6815 | ;; |
6816 | ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f]) | |
6817 | ;; | |
6818 | (define_insn "mve_vec_extract<mode><V_elem_l>" | |
302b6836 | 6819 | [(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=r") |
1a5c27b1 SP |
6820 | (vec_select:<V_elem> |
6821 | (match_operand:MVE_VLD_ST 1 "s_register_operand" "w") | |
6822 | (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | |
6823 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6824 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6825 | { | |
6826 | if (BYTES_BIG_ENDIAN) | |
6827 | { | |
6828 | int elt = INTVAL (operands[2]); | |
6829 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
6830 | operands[2] = GEN_INT (elt); | |
6831 | } | |
6832 | return "vmov.<V_extr_elem>\t%0, %q1[%c2]"; | |
6833 | } | |
6834 | [(set_attr "type" "mve_move")]) | |
6835 | ||
6836 | (define_insn "mve_vec_extractv2didi" | |
302b6836 | 6837 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r") |
1a5c27b1 SP |
6838 | (vec_select:DI |
6839 | (match_operand:V2DI 1 "s_register_operand" "w") | |
6840 | (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | |
6841 | "TARGET_HAVE_MVE" | |
6842 | { | |
6843 | int elt = INTVAL (operands[2]); | |
6844 | if (BYTES_BIG_ENDIAN) | |
6845 | elt = 1 - elt; | |
6846 | ||
6847 | if (elt == 0) | |
6848 | return "vmov\t%Q0, %R0, %e1"; | |
6849 | else | |
302b6836 | 6850 | return "vmov\t%Q0, %R0, %f1"; |
1a5c27b1 SP |
6851 | } |
6852 | [(set_attr "type" "mve_move")]) | |
6853 | ||
6854 | (define_insn "*mve_vec_extract_sext_internal<mode>" | |
6855 | [(set (match_operand:SI 0 "s_register_operand" "=r") | |
6856 | (sign_extend:SI | |
6857 | (vec_select:<V_elem> | |
6858 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
6859 | (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
6860 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6861 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6862 | { | |
6863 | if (BYTES_BIG_ENDIAN) | |
6864 | { | |
6865 | int elt = INTVAL (operands[2]); | |
6866 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
6867 | operands[2] = GEN_INT (elt); | |
6868 | } | |
6869 | return "vmov.s<V_sz_elem>\t%0, %q1[%c2]"; | |
6870 | } | |
6871 | [(set_attr "type" "mve_move")]) | |
6872 | ||
6873 | (define_insn "*mve_vec_extract_zext_internal<mode>" | |
6874 | [(set (match_operand:SI 0 "s_register_operand" "=r") | |
6875 | (zero_extend:SI | |
6876 | (vec_select:<V_elem> | |
6877 | (match_operand:MVE_2 1 "s_register_operand" "w") | |
6878 | (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
6879 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6880 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6881 | { | |
6882 | if (BYTES_BIG_ENDIAN) | |
6883 | { | |
6884 | int elt = INTVAL (operands[2]); | |
6885 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
6886 | operands[2] = GEN_INT (elt); | |
6887 | } | |
6888 | return "vmov.u<V_sz_elem>\t%0, %q1[%c2]"; | |
6889 | } | |
6890 | [(set_attr "type" "mve_move")]) | |
6891 | ||
6892 | ;; | |
6893 | ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f]) | |
6894 | ;; | |
6895 | (define_insn "mve_vec_set<mode>_internal" | |
6896 | [(set (match_operand:VQ2 0 "s_register_operand" "=w") | |
6897 | (vec_merge:VQ2 | |
6898 | (vec_duplicate:VQ2 | |
6899 | (match_operand:<V_elem> 1 "nonimmediate_operand" "r")) | |
6900 | (match_operand:VQ2 3 "s_register_operand" "0") | |
6901 | (match_operand:SI 2 "immediate_operand" "i")))] | |
6902 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
6903 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
6904 | { | |
6905 | int elt = ffs ((int) INTVAL (operands[2])) - 1; | |
6906 | if (BYTES_BIG_ENDIAN) | |
6907 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | |
6908 | operands[2] = GEN_INT (elt); | |
6909 | ||
6910 | return "vmov.<V_sz_elem>\t%q0[%c2], %1"; | |
6911 | } | |
6912 | [(set_attr "type" "mve_move")]) | |
6913 | ||
6914 | (define_insn "mve_vec_setv2di_internal" | |
6915 | [(set (match_operand:V2DI 0 "s_register_operand" "=w") | |
6916 | (vec_merge:V2DI | |
6917 | (vec_duplicate:V2DI | |
6918 | (match_operand:DI 1 "nonimmediate_operand" "r")) | |
6919 | (match_operand:V2DI 3 "s_register_operand" "0") | |
6920 | (match_operand:SI 2 "immediate_operand" "i")))] | |
6921 | "TARGET_HAVE_MVE" | |
6922 | { | |
6923 | int elt = ffs ((int) INTVAL (operands[2])) - 1; | |
6924 | if (BYTES_BIG_ENDIAN) | |
6925 | elt = 1 - elt; | |
6926 | ||
6927 | if (elt == 0) | |
6928 | return "vmov\t%e0, %Q1, %R1"; | |
6929 | else | |
6930 | return "vmov\t%f0, %J1, %K1"; | |
6931 | } | |
6932 | [(set_attr "type" "mve_move")]) | |
85244449 SP |
6933 | |
6934 | ;; | |
6935 | ;; [uqrshll_di] | |
6936 | ;; | |
6937 | (define_insn "mve_uqrshll_sat<supf>_di" | |
6af59870 SP |
6938 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
6939 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
6940 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
6941 | UQRSHLLQ))] |
6942 | "TARGET_HAVE_MVE" | |
6943 | "uqrshll%?\\t%Q1, %R1, #<supf>, %2" | |
6944 | [(set_attr "predicable" "yes")]) | |
6945 | ||
6946 | ;; | |
6947 | ;; [sqrshrl_di] | |
6948 | ;; | |
6949 | (define_insn "mve_sqrshrl_sat<supf>_di" | |
6af59870 SP |
6950 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
6951 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
6952 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
6953 | SQRSHRLQ))] |
6954 | "TARGET_HAVE_MVE" | |
6955 | "sqrshrl%?\\t%Q1, %R1, #<supf>, %2" | |
6956 | [(set_attr "predicable" "yes")]) | |
6957 | ||
6958 | ;; | |
6959 | ;; [uqrshl_si] | |
6960 | ;; | |
6961 | (define_insn "mve_uqrshl_si" | |
6af59870 SP |
6962 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
6963 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
6964 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
6965 | UQRSHL))] |
6966 | "TARGET_HAVE_MVE" | |
6967 | "uqrshl%?\\t%1, %2" | |
6968 | [(set_attr "predicable" "yes")]) | |
6969 | ||
6970 | ;; | |
6971 | ;; [sqrshr_si] | |
6972 | ;; | |
6973 | (define_insn "mve_sqrshr_si" | |
6af59870 SP |
6974 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
6975 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
6976 | (match_operand:SI 2 "register_operand" "r")] | |
85244449 SP |
6977 | SQRSHR))] |
6978 | "TARGET_HAVE_MVE" | |
6979 | "sqrshr%?\\t%1, %2" | |
6980 | [(set_attr "predicable" "yes")]) | |
6981 | ||
6982 | ;; | |
6983 | ;; [uqshll_di] | |
6984 | ;; | |
6985 | (define_insn "mve_uqshll_di" | |
6af59870 SP |
6986 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
6987 | (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") | |
6988 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
6989 | "TARGET_HAVE_MVE" |
6990 | "uqshll%?\\t%Q1, %R1, %2" | |
6991 | [(set_attr "predicable" "yes")]) | |
6992 | ||
6993 | ;; | |
6994 | ;; [urshrl_di] | |
6995 | ;; | |
6996 | (define_insn "mve_urshrl_di" | |
6af59870 SP |
6997 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
6998 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
6999 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
7000 | URSHRL))] |
7001 | "TARGET_HAVE_MVE" | |
7002 | "urshrl%?\\t%Q1, %R1, %2" | |
7003 | [(set_attr "predicable" "yes")]) | |
7004 | ||
7005 | ;; | |
7006 | ;; [uqshl_si] | |
7007 | ;; | |
7008 | (define_insn "mve_uqshl_si" | |
6af59870 SP |
7009 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
7010 | (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0") | |
7011 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
7012 | "TARGET_HAVE_MVE" |
7013 | "uqshl%?\\t%1, %2" | |
7014 | [(set_attr "predicable" "yes")]) | |
7015 | ||
7016 | ;; | |
7017 | ;; [urshr_si] | |
7018 | ;; | |
7019 | (define_insn "mve_urshr_si" | |
6af59870 SP |
7020 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
7021 | (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") | |
7022 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
7023 | URSHR))] |
7024 | "TARGET_HAVE_MVE" | |
7025 | "urshr%?\\t%1, %2" | |
7026 | [(set_attr "predicable" "yes")]) | |
7027 | ||
7028 | ;; | |
7029 | ;; [sqshl_si] | |
7030 | ;; | |
7031 | (define_insn "mve_sqshl_si" | |
6af59870 SP |
7032 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
7033 | (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0") | |
7034 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
7035 | "TARGET_HAVE_MVE" |
7036 | "sqshl%?\\t%1, %2" | |
7037 | [(set_attr "predicable" "yes")]) | |
7038 | ||
7039 | ;; | |
7040 | ;; [srshr_si] | |
7041 | ;; | |
7042 | (define_insn "mve_srshr_si" | |
6af59870 SP |
7043 | [(set (match_operand:SI 0 "arm_general_register_operand" "=r") |
7044 | (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0") | |
7045 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
7046 | SRSHR))] |
7047 | "TARGET_HAVE_MVE" | |
7048 | "srshr%?\\t%1, %2" | |
7049 | [(set_attr "predicable" "yes")]) | |
7050 | ||
7051 | ;; | |
7052 | ;; [srshrl_di] | |
7053 | ;; | |
7054 | (define_insn "mve_srshrl_di" | |
6af59870 SP |
7055 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
7056 | (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") | |
7057 | (match_operand:SI 2 "immediate_operand" "Pg")] | |
85244449 SP |
7058 | SRSHRL))] |
7059 | "TARGET_HAVE_MVE" | |
7060 | "srshrl%?\\t%Q1, %R1, %2" | |
7061 | [(set_attr "predicable" "yes")]) | |
7062 | ||
7063 | ;; | |
7064 | ;; [sqshll_di] | |
7065 | ;; | |
7066 | (define_insn "mve_sqshll_di" | |
6af59870 SP |
7067 | [(set (match_operand:DI 0 "arm_low_register_operand" "=l") |
7068 | (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") | |
7069 | (match_operand:SI 2 "immediate_operand" "Pg")))] | |
85244449 SP |
7070 | "TARGET_HAVE_MVE" |
7071 | "sqshll%?\\t%Q1, %R1, %2" | |
7072 | [(set_attr "predicable" "yes")]) | |
88c9a831 SP |
7073 | |
7074 | ;; | |
7075 | ;; [vshlcq_m_u vshlcq_m_s] | |
7076 | ;; | |
7077 | (define_expand "mve_vshlcq_m_vec_<supf><mode>" | |
7078 | [(match_operand:MVE_2 0 "s_register_operand") | |
7079 | (match_operand:MVE_2 1 "s_register_operand") | |
7080 | (match_operand:SI 2 "s_register_operand") | |
7081 | (match_operand:SI 3 "mve_imm_32") | |
724d6566 | 7082 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand") |
88c9a831 SP |
7083 | (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] |
7084 | "TARGET_HAVE_MVE" | |
7085 | { | |
7086 | rtx ignore_wb = gen_reg_rtx (SImode); | |
7087 | emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1], | |
7088 | operands[2], operands[3], | |
7089 | operands[4])); | |
7090 | DONE; | |
7091 | }) | |
7092 | ||
7093 | (define_expand "mve_vshlcq_m_carry_<supf><mode>" | |
7094 | [(match_operand:SI 0 "s_register_operand") | |
7095 | (match_operand:MVE_2 1 "s_register_operand") | |
7096 | (match_operand:SI 2 "s_register_operand") | |
7097 | (match_operand:SI 3 "mve_imm_32") | |
724d6566 | 7098 | (match_operand:<MVE_VPRED> 4 "vpr_register_operand") |
88c9a831 SP |
7099 | (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] |
7100 | "TARGET_HAVE_MVE" | |
7101 | { | |
7102 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
7103 | emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0], | |
7104 | operands[1], operands[2], | |
7105 | operands[3], operands[4])); | |
7106 | DONE; | |
7107 | }) | |
7108 | ||
7109 | (define_insn "mve_vshlcq_m_<supf><mode>" | |
7110 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
7111 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") | |
7112 | (match_operand:SI 3 "s_register_operand" "1") | |
7113 | (match_operand:SI 4 "mve_imm_32" "Rf") | |
724d6566 | 7114 | (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] |
88c9a831 SP |
7115 | VSHLCQ_M)) |
7116 | (set (match_operand:SI 1 "s_register_operand" "=r") | |
7117 | (unspec:SI [(match_dup 2) | |
7118 | (match_dup 3) | |
7119 | (match_dup 4) | |
7120 | (match_dup 5)] | |
7121 | VSHLCQ_M)) | |
7122 | ] | |
7123 | "TARGET_HAVE_MVE" | |
7124 | "vpst\;vshlct\t%q0, %1, %4" | |
7125 | [(set_attr "type" "mve_move") | |
7126 | (set_attr "length" "8")]) | |
479ccabc | 7127 | |
78bf9163 MM |
7128 | ;; CDE instructions on MVE registers. |
7129 | ||
7130 | (define_insn "arm_vcx1qv16qi" | |
7131 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7132 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7133 | (match_operand:SI 2 "const_int_mve_cde1_operand" "i")] | |
7134 | UNSPEC_VCDE))] | |
7135 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7136 | "vcx1\\tp%c1, %q0, #%c2" | |
7137 | [(set_attr "type" "coproc")] | |
7138 | ) | |
7139 | ||
7140 | (define_insn "arm_vcx1qav16qi" | |
7141 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7142 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7143 | (match_operand:V16QI 2 "register_operand" "0") | |
7144 | (match_operand:SI 3 "const_int_mve_cde1_operand" "i")] | |
7145 | UNSPEC_VCDEA))] | |
7146 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7147 | "vcx1a\\tp%c1, %q0, #%c3" | |
7148 | [(set_attr "type" "coproc")] | |
7149 | ) | |
7150 | ||
7151 | (define_insn "arm_vcx2qv16qi" | |
7152 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7153 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7154 | (match_operand:V16QI 2 "register_operand" "t") | |
7155 | (match_operand:SI 3 "const_int_mve_cde2_operand" "i")] | |
7156 | UNSPEC_VCDE))] | |
7157 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7158 | "vcx2\\tp%c1, %q0, %q2, #%c3" | |
7159 | [(set_attr "type" "coproc")] | |
7160 | ) | |
7161 | ||
7162 | (define_insn "arm_vcx2qav16qi" | |
7163 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7164 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7165 | (match_operand:V16QI 2 "register_operand" "0") | |
7166 | (match_operand:V16QI 3 "register_operand" "t") | |
7167 | (match_operand:SI 4 "const_int_mve_cde2_operand" "i")] | |
7168 | UNSPEC_VCDEA))] | |
7169 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7170 | "vcx2a\\tp%c1, %q0, %q3, #%c4" | |
7171 | [(set_attr "type" "coproc")] | |
7172 | ) | |
7173 | ||
7174 | (define_insn "arm_vcx3qv16qi" | |
7175 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7176 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7177 | (match_operand:V16QI 2 "register_operand" "t") | |
7178 | (match_operand:V16QI 3 "register_operand" "t") | |
7179 | (match_operand:SI 4 "const_int_mve_cde3_operand" "i")] | |
7180 | UNSPEC_VCDE))] | |
7181 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7182 | "vcx3\\tp%c1, %q0, %q2, %q3, #%c4" | |
7183 | [(set_attr "type" "coproc")] | |
7184 | ) | |
7185 | ||
7186 | (define_insn "arm_vcx3qav16qi" | |
7187 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7188 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7189 | (match_operand:V16QI 2 "register_operand" "0") | |
7190 | (match_operand:V16QI 3 "register_operand" "t") | |
7191 | (match_operand:V16QI 4 "register_operand" "t") | |
7192 | (match_operand:SI 5 "const_int_mve_cde3_operand" "i")] | |
7193 | UNSPEC_VCDEA))] | |
7194 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7195 | "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5" | |
7196 | [(set_attr "type" "coproc")] | |
7197 | ) | |
ef684c78 MM |
7198 | |
7199 | (define_insn "arm_vcx1q<a>_p_v16qi" | |
7200 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7201 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7202 | (match_operand:V16QI 2 "register_operand" "0") | |
7203 | (match_operand:SI 3 "const_int_mve_cde1_operand" "i") | |
c6b4ea7a | 7204 | (match_operand:V16BI 4 "vpr_register_operand" "Up")] |
ef684c78 MM |
7205 | CDE_VCX))] |
7206 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7207 | "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3" | |
7208 | [(set_attr "type" "coproc") | |
7209 | (set_attr "length" "8")] | |
7210 | ) | |
7211 | ||
7212 | (define_insn "arm_vcx2q<a>_p_v16qi" | |
7213 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7214 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7215 | (match_operand:V16QI 2 "register_operand" "0") | |
7216 | (match_operand:V16QI 3 "register_operand" "t") | |
7217 | (match_operand:SI 4 "const_int_mve_cde2_operand" "i") | |
c6b4ea7a | 7218 | (match_operand:V16BI 5 "vpr_register_operand" "Up")] |
ef684c78 MM |
7219 | CDE_VCX))] |
7220 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7221 | "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4" | |
7222 | [(set_attr "type" "coproc") | |
7223 | (set_attr "length" "8")] | |
7224 | ) | |
7225 | ||
7226 | (define_insn "arm_vcx3q<a>_p_v16qi" | |
7227 | [(set (match_operand:V16QI 0 "register_operand" "=t") | |
7228 | (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") | |
7229 | (match_operand:V16QI 2 "register_operand" "0") | |
7230 | (match_operand:V16QI 3 "register_operand" "t") | |
7231 | (match_operand:V16QI 4 "register_operand" "t") | |
7232 | (match_operand:SI 5 "const_int_mve_cde3_operand" "i") | |
c6b4ea7a | 7233 | (match_operand:V16BI 6 "vpr_register_operand" "Up")] |
ef684c78 MM |
7234 | CDE_VCX))] |
7235 | "TARGET_CDE && TARGET_HAVE_MVE" | |
7236 | "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5" | |
7237 | [(set_attr "type" "coproc") | |
7238 | (set_attr "length" "8")] | |
7239 | ) | |
25bef689 CL |
7240 | |
7241 | (define_insn "*movmisalign<mode>_mve_store" | |
6a116728 | 7242 | [(set (match_operand:MVE_VLD_ST 0 "mve_memory_operand" "=Ux") |
25bef689 CL |
7243 | (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")] |
7244 | UNSPEC_MISALIGNED_ACCESS))] | |
7245 | "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
7246 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) | |
7247 | && !BYTES_BIG_ENDIAN && unaligned_access" | |
7248 | "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0" | |
7249 | [(set_attr "type" "mve_store")] | |
7250 | ) | |
7251 | ||
7252 | ||
7253 | (define_insn "*movmisalign<mode>_mve_load" | |
7254 | [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") | |
6a116728 | 7255 | (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "mve_memory_operand" " Ux")] |
25bef689 CL |
7256 | UNSPEC_MISALIGNED_ACCESS))] |
7257 | "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
7258 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) | |
7259 | && !BYTES_BIG_ENDIAN && unaligned_access" | |
7260 | "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1" | |
7261 | [(set_attr "type" "mve_load")] | |
7262 | ) | |
91224cf6 CL |
7263 | |
7264 | ;; Expander for VxBI moves | |
7265 | (define_expand "mov<mode>" | |
7266 | [(set (match_operand:MVE_7 0 "nonimmediate_operand") | |
7267 | (match_operand:MVE_7 1 "general_operand"))] | |
7268 | "TARGET_HAVE_MVE" | |
7269 | { | |
7270 | if (!register_operand (operands[0], <MODE>mode)) | |
7271 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
7272 | } | |
7273 | ) | |
df0e57c2 CL |
7274 | |
7275 | ;; Expanders for vec_cmp and vcond | |
7276 | ||
7277 | (define_expand "vec_cmp<mode><MVE_vpred>" | |
7278 | [(set (match_operand:<MVE_VPRED> 0 "s_register_operand") | |
7279 | (match_operator:<MVE_VPRED> 1 "comparison_operator" | |
7280 | [(match_operand:MVE_VLD_ST 2 "s_register_operand") | |
7281 | (match_operand:MVE_VLD_ST 3 "reg_or_zero_operand")]))] | |
7282 | "TARGET_HAVE_MVE | |
7283 | && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | |
7284 | { | |
7285 | arm_expand_vector_compare (operands[0], GET_CODE (operands[1]), | |
7286 | operands[2], operands[3], false); | |
7287 | DONE; | |
7288 | }) | |
7289 | ||
7290 | (define_expand "vec_cmpu<mode><MVE_vpred>" | |
7291 | [(set (match_operand:<MVE_VPRED> 0 "s_register_operand") | |
7292 | (match_operator:<MVE_VPRED> 1 "comparison_operator" | |
7293 | [(match_operand:MVE_2 2 "s_register_operand") | |
7294 | (match_operand:MVE_2 3 "reg_or_zero_operand")]))] | |
7295 | "TARGET_HAVE_MVE" | |
7296 | { | |
7297 | arm_expand_vector_compare (operands[0], GET_CODE (operands[1]), | |
7298 | operands[2], operands[3], false); | |
7299 | DONE; | |
7300 | }) | |
7301 | ||
7302 | (define_expand "vcond_mask_<mode><MVE_vpred>" | |
7303 | [(set (match_operand:MVE_VLD_ST 0 "s_register_operand") | |
7304 | (if_then_else:MVE_VLD_ST | |
7305 | (match_operand:<MVE_VPRED> 3 "s_register_operand") | |
7306 | (match_operand:MVE_VLD_ST 1 "s_register_operand") | |
7307 | (match_operand:MVE_VLD_ST 2 "s_register_operand")))] | |
7308 | "TARGET_HAVE_MVE" | |
7309 | { | |
7310 | switch (GET_MODE_CLASS (<MODE>mode)) | |
7311 | { | |
7312 | case MODE_VECTOR_INT: | |
7313 | emit_insn (gen_mve_vpselq (VPSELQ_S, <MODE>mode, operands[0], | |
7314 | operands[1], operands[2], operands[3])); | |
7315 | break; | |
7316 | case MODE_VECTOR_FLOAT: | |
7317 | emit_insn (gen_mve_vpselq_f (<MODE>mode, operands[0], | |
7318 | operands[1], operands[2], operands[3])); | |
7319 | break; | |
7320 | default: | |
7321 | gcc_unreachable (); | |
7322 | } | |
7323 | DONE; | |
7324 | }) | |
00d97bf3 CL |
7325 | |
7326 | ;; Reinterpret operand 1 in operand 0's mode, without changing its contents. | |
7327 | (define_expand "@arm_mve_reinterpret<mode>" | |
7328 | [(set (match_operand:MVE_vecs 0 "register_operand") | |
7329 | (unspec:MVE_vecs | |
7330 | [(match_operand 1 "arm_any_register_operand")] | |
7331 | REINTERPRET))] | |
7332 | "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) | |
7333 | || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" | |
7334 | { | |
7335 | machine_mode src_mode = GET_MODE (operands[1]); | |
7336 | if (targetm.can_change_mode_class (<MODE>mode, src_mode, VFP_REGS)) | |
7337 | { | |
7338 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1])); | |
7339 | DONE; | |
7340 | } | |
7341 | } | |
7342 | ) |