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[ARM][GCC][5/2x]: MVE intrinsics with binary operands.
[thirdparty/gcc.git] / gcc / config / arm / mve.md
CommitLineData
63c8f7d6
SP		 1;; Arm M-profile Vector Extension Machine Description
2;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful, but
12;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14;; General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
19
63c8f7d6
SP		 20(define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32")
21 (V2DI "u64")])
14782c81
SP		 22(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
23(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
a50f6abf 24(define_mode_iterator MVE_0 [V8HF V4SF])
f166a8cd 25(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
6df4618c 26(define_mode_iterator MVE_3 [V16QI V8HI])
5db0eb95
SP		 27(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
28(define_mode_iterator MVE_5 [V8HI V4SI])
14782c81 29
a50f6abf
SP		 30(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
31 VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
6df4618c
SP		 32 VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
33 VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
34 VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
35 VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
36 VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
37 VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
38 VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
39 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
4be8cf77
SP		 40 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
41 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
f166a8cd 42 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
d71dba7b 43 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
33203b4c
SP		 44 VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
45 VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
46 VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
47 VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
48 VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
49 VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
50 VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
51 VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
52 VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
53 VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
54 VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
55 VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
56 VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
57 VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
58 VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
59 VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
60 VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
61 VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
62 VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
63 VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
64 VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
65 VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
66 VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
67 VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
68 VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
f9355dee
SP		 69 VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
70 VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
71 VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
72 VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
73 VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
74 VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
75 VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
76 VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
77 VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
78 VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
79 VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
80 VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
81 VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
82 VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
83 VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
84 VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
85 VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
86 VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
87 VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
88 VMULLBQ_POLY_P])
a50f6abf
SP		 89
90(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
91 (V8HF "V8HI") (V4SF "V4SI")])
92
6df4618c
SP		 93(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
94 (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
95 (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
96 (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
97 (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
98 (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
99 (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
100 (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
101 (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
102 (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
103 (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
4be8cf77 104 (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
f166a8cd
SP		 105 (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
106 (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
d71dba7b
SP		 107 (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
108 (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
33203b4c
SP		 109 (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
110 (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
111 (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
112 (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
113 (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
114 (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
115 (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
116 (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
117 (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
118 (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
119 (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
120 (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
121 (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
122 (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
123 (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
124 (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
125 (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
126 (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
127 (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
128 (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
129 (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
130 (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
131 (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
132 (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
133 (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
134 (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
135 (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
136 (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
137 (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
138 (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
139 (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
140 (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
f9355dee
SP		 141 (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
142 (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
143 (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
144 (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
145 (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
146 (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
147 (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
148 (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
149 (VRMLALDAVHQ_S "s")])
5db0eb95 150
a475f153 151(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
f9355dee
SP		 152 (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
153 (VCTP32Q_M "32") (VCTP64Q_M "64")])
f166a8cd
SP		 154(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
155 (V4SI "mve_imm_32")])
156(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
33203b4c 157(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
a475f153 158
a50f6abf 159(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
5db0eb95
SP		 160(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
161(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
162(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
6df4618c
SP		 163(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
164(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
165(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
166(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
167(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
168(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
169(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
170(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
171(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
172(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
173(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
174(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
175(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
a475f153 176(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
f9355dee 177(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
4be8cf77 178(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
f166a8cd
SP		 179(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
180(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
181(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
d71dba7b
SP		 182(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
183(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
184(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
33203b4c
SP		 185(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
186(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
187(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
188(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
189(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
190(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
191(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
192(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
193(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
194(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
195(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
196(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
197(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
198(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
199(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
200(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
201(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
202(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
203(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
204(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
205(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
206(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
207(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
208(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
209(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
210(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
211(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
212(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
213(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
214(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
215(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
216(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
217(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
218(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
219(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
220(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
221(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
222(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
223(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
224(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
225(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
226(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
227(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
228(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
229(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
230(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
231(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
f9355dee
SP		 232(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
233(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
234(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
235(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
236(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
237(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
238(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
239(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
240(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
241(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
242(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
243(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
63c8f7d6
SP		 244
245(define_insn "*mve_mov<mode>"
246 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
247 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))]
248 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
249{
250 if (which_alternative == 3 || which_alternative == 6)
251 {
252 int width, is_valid;
253 static char templ[40];
254
255 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
256 &operands[1], &width);
257
258 gcc_assert (is_valid != 0);
259
260 if (width == 0)
261 return "vmov.f32\t%q0, %1 @ <mode>";
262 else
263 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width);
264 return templ;
265 }
266 switch (which_alternative)
267 {
268 case 0:
269 return "vmov\t%q0, %q1";
270 case 1:
271 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
272 case 2:
273 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
274 case 4:
275 if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
276 || (MEM_P (operands[1])
277 && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
278 return output_move_neon (operands);
279 else
280 return "vldrb.8 %q0, %E1";
281 case 5:
282 return output_move_neon (operands);
283 case 7:
284 return "vstrb.8 %q1, %E0";
285 default:
286 gcc_unreachable ();
287 return "";
288 }
289}
290 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
291 (set_attr "length" "4,8,8,4,8,8,4,4")
292 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
293 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
294
295(define_insn "*mve_mov<mode>"
296 [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
297 (vec_duplicate:MVE_types
298 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
299 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
300{
301 if (which_alternative == 0)
302 return "vdup.<V_sz_elem>\t%q0, %1";
303 return "vmov.<V_sz_elem>\t%q0, %1";
304}
305 [(set_attr "length" "4,4")
306 (set_attr "type" "mve_move,mve_move")])
14782c81
SP		 307
308;;
309;; [vst4q])
310;;
311(define_insn "mve_vst4q<mode>"
312 [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
313 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
314 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
315 VST4Q))
316 ]
317 "TARGET_HAVE_MVE"
318{
319 rtx ops[6];
320 int regno = REGNO (operands[1]);
321 ops[0] = gen_rtx_REG (TImode, regno);
322 ops[1] = gen_rtx_REG (TImode, regno+4);
323 ops[2] = gen_rtx_REG (TImode, regno+8);
324 ops[3] = gen_rtx_REG (TImode, regno+12);
325 rtx reg = operands[0];
326 while (reg && !REG_P (reg))
327 reg = XEXP (reg, 0);
328 gcc_assert (REG_P (reg));
329 ops[4] = reg;
330 ops[5] = operands[0];
331 /* Here in first three instructions data is stored to ops[4]'s location but
332 in the fourth instruction data is stored to operands[0], this is to
333 support the writeback. */
334 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
335 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
336 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
337 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
338 return "";
339}
340 [(set_attr "length" "16")])
a50f6abf
SP		 341
342;;
343;; [vrndxq_f])
344;;
345(define_insn "mve_vrndxq_f<mode>"
346 [
347 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
348 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
349 VRNDXQ_F))
350 ]
351 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
352 "vrintx.f%#<V_sz_elem> %q0, %q1"
353 [(set_attr "type" "mve_move")
354])
355
356;;
357;; [vrndq_f])
358;;
359(define_insn "mve_vrndq_f<mode>"
360 [
361 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
362 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
363 VRNDQ_F))
364 ]
365 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
366 "vrintz.f%#<V_sz_elem> %q0, %q1"
367 [(set_attr "type" "mve_move")
368])
369
370;;
371;; [vrndpq_f])
372;;
373(define_insn "mve_vrndpq_f<mode>"
374 [
375 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
376 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
377 VRNDPQ_F))
378 ]
379 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
380 "vrintp.f%#<V_sz_elem> %q0, %q1"
381 [(set_attr "type" "mve_move")
382])
383
384;;
385;; [vrndnq_f])
386;;
387(define_insn "mve_vrndnq_f<mode>"
388 [
389 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
390 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
391 VRNDNQ_F))
392 ]
393 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
394 "vrintn.f%#<V_sz_elem> %q0, %q1"
395 [(set_attr "type" "mve_move")
396])
397
398;;
399;; [vrndmq_f])
400;;
401(define_insn "mve_vrndmq_f<mode>"
402 [
403 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
404 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
405 VRNDMQ_F))
406 ]
407 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
408 "vrintm.f%#<V_sz_elem> %q0, %q1"
409 [(set_attr "type" "mve_move")
410])
411
412;;
413;; [vrndaq_f])
414;;
415(define_insn "mve_vrndaq_f<mode>"
416 [
417 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
418 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
419 VRNDAQ_F))
420 ]
421 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
422 "vrinta.f%#<V_sz_elem> %q0, %q1"
423 [(set_attr "type" "mve_move")
424])
425
426;;
427;; [vrev64q_f])
428;;
429(define_insn "mve_vrev64q_f<mode>"
430 [
431 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
432 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
433 VREV64Q_F))
434 ]
435 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
436 "vrev64.%#<V_sz_elem> %q0, %q1"
437 [(set_attr "type" "mve_move")
438])
439
440;;
441;; [vnegq_f])
442;;
443(define_insn "mve_vnegq_f<mode>"
444 [
445 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
446 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
447 VNEGQ_F))
448 ]
449 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
450 "vneg.f%#<V_sz_elem> %q0, %q1"
451 [(set_attr "type" "mve_move")
452])
453
454;;
455;; [vdupq_n_f])
456;;
457(define_insn "mve_vdupq_n_f<mode>"
458 [
459 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
460 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
461 VDUPQ_N_F))
462 ]
463 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
464 "vdup.%#<V_sz_elem> %q0, %1"
465 [(set_attr "type" "mve_move")
466])
467
468;;
469;; [vabsq_f])
470;;
471(define_insn "mve_vabsq_f<mode>"
472 [
473 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
474 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
475 VABSQ_F))
476 ]
477 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
478 "vabs.f%#<V_sz_elem> %q0, %q1"
479 [(set_attr "type" "mve_move")
480])
481
482;;
483;; [vrev32q_f])
484;;
485(define_insn "mve_vrev32q_fv8hf"
486 [
487 (set (match_operand:V8HF 0 "s_register_operand" "=w")
488 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
489 VREV32Q_F))
490 ]
491 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
492 "vrev32.16 %q0, %q1"
493 [(set_attr "type" "mve_move")
494])
495;;
496;; [vcvttq_f32_f16])
497;;
498(define_insn "mve_vcvttq_f32_f16v4sf"
499 [
500 (set (match_operand:V4SF 0 "s_register_operand" "=w")
501 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
502 VCVTTQ_F32_F16))
503 ]
504 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
505 "vcvtt.f32.f16 %q0, %q1"
506 [(set_attr "type" "mve_move")
507])
508
509;;
510;; [vcvtbq_f32_f16])
511;;
512(define_insn "mve_vcvtbq_f32_f16v4sf"
513 [
514 (set (match_operand:V4SF 0 "s_register_operand" "=w")
515 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
516 VCVTBQ_F32_F16))
517 ]
518 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
519 "vcvtb.f32.f16 %q0, %q1"
520 [(set_attr "type" "mve_move")
521])
522
523;;
524;; [vcvtq_to_f_s, vcvtq_to_f_u])
525;;
526(define_insn "mve_vcvtq_to_f_<supf><mode>"
527 [
528 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
529 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
530 VCVTQ_TO_F))
531 ]
532 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
533 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
534 [(set_attr "type" "mve_move")
535])
5db0eb95
SP		 536
537;;
538;; [vrev64q_u, vrev64q_s])
539;;
540(define_insn "mve_vrev64q_<supf><mode>"
541 [
542 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
543 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
544 VREV64Q))
545 ]
546 "TARGET_HAVE_MVE"
547 "vrev64.%#<V_sz_elem> %q0, %q1"
548 [(set_attr "type" "mve_move")
549])
550
551;;
552;; [vcvtq_from_f_s, vcvtq_from_f_u])
553;;
554(define_insn "mve_vcvtq_from_f_<supf><mode>"
555 [
556 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
557 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
558 VCVTQ_FROM_F))
559 ]
560 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
561 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
562 [(set_attr "type" "mve_move")
563])
6df4618c
SP		 564;; [vqnegq_s])
565;;
566(define_insn "mve_vqnegq_s<mode>"
567 [
568 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
569 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
570 VQNEGQ_S))
571 ]
572 "TARGET_HAVE_MVE"
573 "vqneg.s%#<V_sz_elem> %q0, %q1"
574 [(set_attr "type" "mve_move")
575])
576
577;;
578;; [vqabsq_s])
579;;
580(define_insn "mve_vqabsq_s<mode>"
581 [
582 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
583 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
584 VQABSQ_S))
585 ]
586 "TARGET_HAVE_MVE"
587 "vqabs.s%#<V_sz_elem> %q0, %q1"
588 [(set_attr "type" "mve_move")
589])
590
591;;
592;; [vnegq_s])
593;;
594(define_insn "mve_vnegq_s<mode>"
595 [
596 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
597 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
598 VNEGQ_S))
599 ]
600 "TARGET_HAVE_MVE"
601 "vneg.s%#<V_sz_elem> %q0, %q1"
602 [(set_attr "type" "mve_move")
603])
604
605;;
606;; [vmvnq_u, vmvnq_s])
607;;
608(define_insn "mve_vmvnq_<supf><mode>"
609 [
610 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
611 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
612 VMVNQ))
613 ]
614 "TARGET_HAVE_MVE"
615 "vmvn %q0, %q1"
616 [(set_attr "type" "mve_move")
617])
618
619;;
620;; [vdupq_n_u, vdupq_n_s])
621;;
622(define_insn "mve_vdupq_n_<supf><mode>"
623 [
624 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
625 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
626 VDUPQ_N))
627 ]
628 "TARGET_HAVE_MVE"
629 "vdup.%#<V_sz_elem> %q0, %1"
630 [(set_attr "type" "mve_move")
631])
632
633;;
634;; [vclzq_u, vclzq_s])
635;;
636(define_insn "mve_vclzq_<supf><mode>"
637 [
638 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
639 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
640 VCLZQ))
641 ]
642 "TARGET_HAVE_MVE"
643 "vclz.i%#<V_sz_elem> %q0, %q1"
644 [(set_attr "type" "mve_move")
645])
646
647;;
648;; [vclsq_s])
649;;
650(define_insn "mve_vclsq_s<mode>"
651 [
652 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
653 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
654 VCLSQ_S))
655 ]
656 "TARGET_HAVE_MVE"
657 "vcls.s%#<V_sz_elem> %q0, %q1"
658 [(set_attr "type" "mve_move")
659])
660
661;;
662;; [vaddvq_s, vaddvq_u])
663;;
664(define_insn "mve_vaddvq_<supf><mode>"
665 [
666 (set (match_operand:SI 0 "s_register_operand" "=e")
667 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
668 VADDVQ))
669 ]
670 "TARGET_HAVE_MVE"
671 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1"
672 [(set_attr "type" "mve_move")
673])
674
675;;
676;; [vabsq_s])
677;;
678(define_insn "mve_vabsq_s<mode>"
679 [
680 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
681 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
682 VABSQ_S))
683 ]
684 "TARGET_HAVE_MVE"
685 "vabs.s%#<V_sz_elem>\t%q0, %q1"
686 [(set_attr "type" "mve_move")
687])
688
689;;
690;; [vrev32q_u, vrev32q_s])
691;;
692(define_insn "mve_vrev32q_<supf><mode>"
693 [
694 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
695 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
696 VREV32Q))
697 ]
698 "TARGET_HAVE_MVE"
699 "vrev32.%#<V_sz_elem>\t%q0, %q1"
700 [(set_attr "type" "mve_move")
701])
702
703;;
704;; [vmovltq_u, vmovltq_s])
705;;
706(define_insn "mve_vmovltq_<supf><mode>"
707 [
708 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
709 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
710 VMOVLTQ))
711 ]
712 "TARGET_HAVE_MVE"
713 "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
714 [(set_attr "type" "mve_move")
715])
716
717;;
718;; [vmovlbq_s, vmovlbq_u])
719;;
720(define_insn "mve_vmovlbq_<supf><mode>"
721 [
722 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
723 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
724 VMOVLBQ))
725 ]
726 "TARGET_HAVE_MVE"
727 "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
728 [(set_attr "type" "mve_move")
729])
730
731;;
732;; [vcvtpq_s, vcvtpq_u])
733;;
734(define_insn "mve_vcvtpq_<supf><mode>"
735 [
736 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
737 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
738 VCVTPQ))
739 ]
740 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
741 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
742 [(set_attr "type" "mve_move")
743])
744
745;;
746;; [vcvtnq_s, vcvtnq_u])
747;;
748(define_insn "mve_vcvtnq_<supf><mode>"
749 [
750 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
751 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
752 VCVTNQ))
753 ]
754 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
755 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
756 [(set_attr "type" "mve_move")
757])
758
759;;
760;; [vcvtmq_s, vcvtmq_u])
761;;
762(define_insn "mve_vcvtmq_<supf><mode>"
763 [
764 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
765 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
766 VCVTMQ))
767 ]
768 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
769 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
770 [(set_attr "type" "mve_move")
771])
772
773;;
774;; [vcvtaq_u, vcvtaq_s])
775;;
776(define_insn "mve_vcvtaq_<supf><mode>"
777 [
778 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
779 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
780 VCVTAQ))
781 ]
782 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
783 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
784 [(set_attr "type" "mve_move")
785])
5db0eb95
SP		 786
787;;
788;; [vmvnq_n_u, vmvnq_n_s])
789;;
790(define_insn "mve_vmvnq_n_<supf><mode>"
791 [
792 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
793 (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
794 VMVNQ_N))
795 ]
796 "TARGET_HAVE_MVE"
797 "vmvn.i%#<V_sz_elem> %q0, %1"
798 [(set_attr "type" "mve_move")
799])
6df4618c
SP		 800
801;;
802;; [vrev16q_u, vrev16q_s])
803;;
804(define_insn "mve_vrev16q_<supf>v16qi"
805 [
806 (set (match_operand:V16QI 0 "s_register_operand" "=w")
807 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
808 VREV16Q))
809 ]
810 "TARGET_HAVE_MVE"
811 "vrev16.8 %q0, %q1"
812 [(set_attr "type" "mve_move")
813])
814
815;;
816;; [vaddlvq_s vaddlvq_u])
817;;
818(define_insn "mve_vaddlvq_<supf>v4si"
819 [
820 (set (match_operand:DI 0 "s_register_operand" "=r")
821 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
822 VADDLVQ))
823 ]
824 "TARGET_HAVE_MVE"
825 "vaddlv.<supf>32 %Q0, %R0, %q1"
826 [(set_attr "type" "mve_move")
827])
a475f153
SP		 828
829;;
830;; [vctp8q vctp16q vctp32q vctp64q])
831;;
832(define_insn "mve_vctp<mode1>qhi"
833 [
834 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
835 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
836 VCTPQ))
837 ]
838 "TARGET_HAVE_MVE"
839 "vctp.<mode1> %1"
840 [(set_attr "type" "mve_move")
841])
842
843;;
844;; [vpnot])
845;;
846(define_insn "mve_vpnothi"
847 [
848 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
849 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
850 VPNOT))
851 ]
852 "TARGET_HAVE_MVE"
853 "vpnot"
854 [(set_attr "type" "mve_move")
855])
4be8cf77
SP		 856
857;;
858;; [vsubq_n_f])
859;;
860(define_insn "mve_vsubq_n_f<mode>"
861 [
862 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
863 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
864 (match_operand:<V_elem> 2 "s_register_operand" "r")]
865 VSUBQ_N_F))
866 ]
867 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
868 "vsub.f<V_sz_elem> %q0, %q1, %2"
869 [(set_attr "type" "mve_move")
870])
871
872;;
873;; [vbrsrq_n_f])
874;;
875(define_insn "mve_vbrsrq_n_f<mode>"
876 [
877 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
878 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
879 (match_operand:SI 2 "s_register_operand" "r")]
880 VBRSRQ_N_F))
881 ]
882 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
883 "vbrsr.<V_sz_elem> %q0, %q1, %2"
884 [(set_attr "type" "mve_move")
885])
886
887;;
888;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
889;;
890(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
891 [
892 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
893 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
894 (match_operand:SI 2 "mve_imm_16" "Rd")]
895 VCVTQ_N_TO_F))
896 ]
897 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
898 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
899 [(set_attr "type" "mve_move")
900])
901
902;; [vcreateq_f])
903;;
904(define_insn "mve_vcreateq_f<mode>"
905 [
906 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
907 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
908 (match_operand:DI 2 "s_register_operand" "r")]
909 VCREATEQ_F))
910 ]
911 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
912 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
913 [(set_attr "type" "mve_move")
914 (set_attr "length""8")])
f166a8cd
SP		 915
916;;
917;; [vcreateq_u, vcreateq_s])
918;;
919(define_insn "mve_vcreateq_<supf><mode>"
920 [
921 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
922 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
923 (match_operand:DI 2 "s_register_operand" "r")]
924 VCREATEQ))
925 ]
926 "TARGET_HAVE_MVE"
927 "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
928 [(set_attr "type" "mve_move")
929 (set_attr "length""8")])
930
931;;
932;; [vshrq_n_s, vshrq_n_u])
933;;
934(define_insn "mve_vshrq_n_<supf><mode>"
935 [
936 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
937 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
938 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
939 VSHRQ_N))
940 ]
941 "TARGET_HAVE_MVE"
942 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
943 [(set_attr "type" "mve_move")
944])
945
946;;
947;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
948;;
949(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
950 [
951 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
952 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
953 (match_operand:SI 2 "mve_imm_16" "Rd")]
954 VCVTQ_N_FROM_F))
955 ]
956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
957 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
958 [(set_attr "type" "mve_move")
959])
d71dba7b
SP		 960
961;;
962;; [vaddlvq_p_s])
963;;
964(define_insn "mve_vaddlvq_p_<supf>v4si"
965 [
966 (set (match_operand:DI 0 "s_register_operand" "=r")
967 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
968 (match_operand:HI 2 "vpr_register_operand" "Up")]
969 VADDLVQ_P))
970 ]
971 "TARGET_HAVE_MVE"
972 "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
973 [(set_attr "type" "mve_move")
974 (set_attr "length""8")])
975
976;;
977;; [vcmpneq_u, vcmpneq_s])
978;;
979(define_insn "mve_vcmpneq_<supf><mode>"
980 [
981 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
982 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
983 (match_operand:MVE_2 2 "s_register_operand" "w")]
984 VCMPNEQ))
985 ]
986 "TARGET_HAVE_MVE"
987 "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
988 [(set_attr "type" "mve_move")
989])
990
991;;
992;; [vshlq_s, vshlq_u])
993;;
994(define_insn "mve_vshlq_<supf><mode>"
995 [
996 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
997 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
998 (match_operand:MVE_2 2 "s_register_operand" "w")]
999 VSHLQ))
1000 ]
1001 "TARGET_HAVE_MVE"
1002 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1003 [(set_attr "type" "mve_move")
1004])
33203b4c
SP		 1005
1006;;
1007;; [vabdq_s, vabdq_u])
1008;;
1009(define_insn "mve_vabdq_<supf><mode>"
1010 [
1011 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1012 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1013 (match_operand:MVE_2 2 "s_register_operand" "w")]
1014 VABDQ))
1015 ]
1016 "TARGET_HAVE_MVE"
1017 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2"
1018 [(set_attr "type" "mve_move")
1019])
1020
1021;;
1022;; [vaddq_n_s, vaddq_n_u])
1023;;
1024(define_insn "mve_vaddq_n_<supf><mode>"
1025 [
1026 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1027 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1028 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1029 VADDQ_N))
1030 ]
1031 "TARGET_HAVE_MVE"
1032 "vadd.i%#<V_sz_elem> %q0, %q1, %2"
1033 [(set_attr "type" "mve_move")
1034])
1035
1036;;
1037;; [vaddvaq_s, vaddvaq_u])
1038;;
1039(define_insn "mve_vaddvaq_<supf><mode>"
1040 [
1041 (set (match_operand:SI 0 "s_register_operand" "=e")
1042 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1043 (match_operand:MVE_2 2 "s_register_operand" "w")]
1044 VADDVAQ))
1045 ]
1046 "TARGET_HAVE_MVE"
1047 "vaddva.<supf>%#<V_sz_elem> %0, %q2"
1048 [(set_attr "type" "mve_move")
1049])
1050
1051;;
1052;; [vaddvq_p_u, vaddvq_p_s])
1053;;
1054(define_insn "mve_vaddvq_p_<supf><mode>"
1055 [
1056 (set (match_operand:SI 0 "s_register_operand" "=e")
1057 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1058 (match_operand:HI 2 "vpr_register_operand" "Up")]
1059 VADDVQ_P))
1060 ]
1061 "TARGET_HAVE_MVE"
1062 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1"
1063 [(set_attr "type" "mve_move")
1064 (set_attr "length""8")])
1065
1066;;
1067;; [vandq_u, vandq_s])
1068;;
1069(define_insn "mve_vandq_<supf><mode>"
1070 [
1071 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1072 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1073 (match_operand:MVE_2 2 "s_register_operand" "w")]
1074 VANDQ))
1075 ]
1076 "TARGET_HAVE_MVE"
1077 "vand %q0, %q1, %q2"
1078 [(set_attr "type" "mve_move")
1079])
1080
1081;;
1082;; [vbicq_s, vbicq_u])
1083;;
1084(define_insn "mve_vbicq_<supf><mode>"
1085 [
1086 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1087 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1088 (match_operand:MVE_2 2 "s_register_operand" "w")]
1089 VBICQ))
1090 ]
1091 "TARGET_HAVE_MVE"
1092 "vbic %q0, %q1, %q2"
1093 [(set_attr "type" "mve_move")
1094])
1095
1096;;
1097;; [vbrsrq_n_u, vbrsrq_n_s])
1098;;
1099(define_insn "mve_vbrsrq_n_<supf><mode>"
1100 [
1101 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1102 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1103 (match_operand:SI 2 "s_register_operand" "r")]
1104 VBRSRQ_N))
1105 ]
1106 "TARGET_HAVE_MVE"
1107 "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
1108 [(set_attr "type" "mve_move")
1109])
1110
1111;;
1112;; [vcaddq_rot270_s, vcaddq_rot270_u])
1113;;
1114(define_insn "mve_vcaddq_rot270_<supf><mode>"
1115 [
1116 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1117 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1118 (match_operand:MVE_2 2 "s_register_operand" "w")]
1119 VCADDQ_ROT270))
1120 ]
1121 "TARGET_HAVE_MVE"
1122 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
1123 [(set_attr "type" "mve_move")
1124])
1125
1126;;
1127;; [vcaddq_rot90_u, vcaddq_rot90_s])
1128;;
1129(define_insn "mve_vcaddq_rot90_<supf><mode>"
1130 [
1131 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1132 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1133 (match_operand:MVE_2 2 "s_register_operand" "w")]
1134 VCADDQ_ROT90))
1135 ]
1136 "TARGET_HAVE_MVE"
1137 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
1138 [(set_attr "type" "mve_move")
1139])
1140
1141;;
1142;; [vcmpcsq_n_u])
1143;;
1144(define_insn "mve_vcmpcsq_n_u<mode>"
1145 [
1146 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1147 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1148 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1149 VCMPCSQ_N_U))
1150 ]
1151 "TARGET_HAVE_MVE"
1152 "vcmp.u%#<V_sz_elem> cs, %q1, %2"
1153 [(set_attr "type" "mve_move")
1154])
1155
1156;;
1157;; [vcmpcsq_u])
1158;;
1159(define_insn "mve_vcmpcsq_u<mode>"
1160 [
1161 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1162 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1163 (match_operand:MVE_2 2 "s_register_operand" "w")]
1164 VCMPCSQ_U))
1165 ]
1166 "TARGET_HAVE_MVE"
1167 "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
1168 [(set_attr "type" "mve_move")
1169])
1170
1171;;
1172;; [vcmpeqq_n_s, vcmpeqq_n_u])
1173;;
1174(define_insn "mve_vcmpeqq_n_<supf><mode>"
1175 [
1176 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1177 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1178 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1179 VCMPEQQ_N))
1180 ]
1181 "TARGET_HAVE_MVE"
1182 "vcmp.i%#<V_sz_elem> eq, %q1, %2"
1183 [(set_attr "type" "mve_move")
1184])
1185
1186;;
1187;; [vcmpeqq_u, vcmpeqq_s])
1188;;
1189(define_insn "mve_vcmpeqq_<supf><mode>"
1190 [
1191 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1192 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1193 (match_operand:MVE_2 2 "s_register_operand" "w")]
1194 VCMPEQQ))
1195 ]
1196 "TARGET_HAVE_MVE"
1197 "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
1198 [(set_attr "type" "mve_move")
1199])
1200
1201;;
1202;; [vcmpgeq_n_s])
1203;;
1204(define_insn "mve_vcmpgeq_n_s<mode>"
1205 [
1206 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1207 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1208 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1209 VCMPGEQ_N_S))
1210 ]
1211 "TARGET_HAVE_MVE"
1212 "vcmp.s%#<V_sz_elem> ge, %q1, %2"
1213 [(set_attr "type" "mve_move")
1214])
1215
1216;;
1217;; [vcmpgeq_s])
1218;;
1219(define_insn "mve_vcmpgeq_s<mode>"
1220 [
1221 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1222 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1223 (match_operand:MVE_2 2 "s_register_operand" "w")]
1224 VCMPGEQ_S))
1225 ]
1226 "TARGET_HAVE_MVE"
1227 "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
1228 [(set_attr "type" "mve_move")
1229])
1230
1231;;
1232;; [vcmpgtq_n_s])
1233;;
1234(define_insn "mve_vcmpgtq_n_s<mode>"
1235 [
1236 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1237 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1238 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1239 VCMPGTQ_N_S))
1240 ]
1241 "TARGET_HAVE_MVE"
1242 "vcmp.s%#<V_sz_elem> gt, %q1, %2"
1243 [(set_attr "type" "mve_move")
1244])
1245
1246;;
1247;; [vcmpgtq_s])
1248;;
1249(define_insn "mve_vcmpgtq_s<mode>"
1250 [
1251 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1252 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1253 (match_operand:MVE_2 2 "s_register_operand" "w")]
1254 VCMPGTQ_S))
1255 ]
1256 "TARGET_HAVE_MVE"
1257 "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
1258 [(set_attr "type" "mve_move")
1259])
1260
1261;;
1262;; [vcmphiq_n_u])
1263;;
1264(define_insn "mve_vcmphiq_n_u<mode>"
1265 [
1266 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1267 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1268 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1269 VCMPHIQ_N_U))
1270 ]
1271 "TARGET_HAVE_MVE"
1272 "vcmp.u%#<V_sz_elem> hi, %q1, %2"
1273 [(set_attr "type" "mve_move")
1274])
1275
1276;;
1277;; [vcmphiq_u])
1278;;
1279(define_insn "mve_vcmphiq_u<mode>"
1280 [
1281 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1282 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1283 (match_operand:MVE_2 2 "s_register_operand" "w")]
1284 VCMPHIQ_U))
1285 ]
1286 "TARGET_HAVE_MVE"
1287 "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
1288 [(set_attr "type" "mve_move")
1289])
1290
1291;;
1292;; [vcmpleq_n_s])
1293;;
1294(define_insn "mve_vcmpleq_n_s<mode>"
1295 [
1296 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1297 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1298 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1299 VCMPLEQ_N_S))
1300 ]
1301 "TARGET_HAVE_MVE"
1302 "vcmp.s%#<V_sz_elem> le, %q1, %2"
1303 [(set_attr "type" "mve_move")
1304])
1305
1306;;
1307;; [vcmpleq_s])
1308;;
1309(define_insn "mve_vcmpleq_s<mode>"
1310 [
1311 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1312 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1313 (match_operand:MVE_2 2 "s_register_operand" "w")]
1314 VCMPLEQ_S))
1315 ]
1316 "TARGET_HAVE_MVE"
1317 "vcmp.s%#<V_sz_elem> le, %q1, %q2"
1318 [(set_attr "type" "mve_move")
1319])
1320
1321;;
1322;; [vcmpltq_n_s])
1323;;
1324(define_insn "mve_vcmpltq_n_s<mode>"
1325 [
1326 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1327 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1328 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1329 VCMPLTQ_N_S))
1330 ]
1331 "TARGET_HAVE_MVE"
1332 "vcmp.s%#<V_sz_elem> lt, %q1, %2"
1333 [(set_attr "type" "mve_move")
1334])
1335
1336;;
1337;; [vcmpltq_s])
1338;;
1339(define_insn "mve_vcmpltq_s<mode>"
1340 [
1341 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1342 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1343 (match_operand:MVE_2 2 "s_register_operand" "w")]
1344 VCMPLTQ_S))
1345 ]
1346 "TARGET_HAVE_MVE"
1347 "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
1348 [(set_attr "type" "mve_move")
1349])
1350
1351;;
1352;; [vcmpneq_n_u, vcmpneq_n_s])
1353;;
1354(define_insn "mve_vcmpneq_n_<supf><mode>"
1355 [
1356 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
1357 (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
1358 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1359 VCMPNEQ_N))
1360 ]
1361 "TARGET_HAVE_MVE"
1362 "vcmp.i%#<V_sz_elem> ne, %q1, %2"
1363 [(set_attr "type" "mve_move")
1364])
1365
1366;;
1367;; [veorq_u, veorq_s])
1368;;
1369(define_insn "mve_veorq_<supf><mode>"
1370 [
1371 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1372 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1373 (match_operand:MVE_2 2 "s_register_operand" "w")]
1374 VEORQ))
1375 ]
1376 "TARGET_HAVE_MVE"
1377 "veor %q0, %q1, %q2"
1378 [(set_attr "type" "mve_move")
1379])
1380
1381;;
1382;; [vhaddq_n_u, vhaddq_n_s])
1383;;
1384(define_insn "mve_vhaddq_n_<supf><mode>"
1385 [
1386 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1387 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1388 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1389 VHADDQ_N))
1390 ]
1391 "TARGET_HAVE_MVE"
1392 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1393 [(set_attr "type" "mve_move")
1394])
1395
1396;;
1397;; [vhaddq_s, vhaddq_u])
1398;;
1399(define_insn "mve_vhaddq_<supf><mode>"
1400 [
1401 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1402 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1403 (match_operand:MVE_2 2 "s_register_operand" "w")]
1404 VHADDQ))
1405 ]
1406 "TARGET_HAVE_MVE"
1407 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1408 [(set_attr "type" "mve_move")
1409])
1410
1411;;
1412;; [vhcaddq_rot270_s])
1413;;
1414(define_insn "mve_vhcaddq_rot270_s<mode>"
1415 [
1416 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1417 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1418 (match_operand:MVE_2 2 "s_register_operand" "w")]
1419 VHCADDQ_ROT270_S))
1420 ]
1421 "TARGET_HAVE_MVE"
1422 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
1423 [(set_attr "type" "mve_move")
1424])
1425
1426;;
1427;; [vhcaddq_rot90_s])
1428;;
1429(define_insn "mve_vhcaddq_rot90_s<mode>"
1430 [
1431 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1432 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1433 (match_operand:MVE_2 2 "s_register_operand" "w")]
1434 VHCADDQ_ROT90_S))
1435 ]
1436 "TARGET_HAVE_MVE"
1437 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
1438 [(set_attr "type" "mve_move")
1439])
1440
1441;;
1442;; [vhsubq_n_u, vhsubq_n_s])
1443;;
1444(define_insn "mve_vhsubq_n_<supf><mode>"
1445 [
1446 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1447 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1448 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1449 VHSUBQ_N))
1450 ]
1451 "TARGET_HAVE_MVE"
1452 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1453 [(set_attr "type" "mve_move")
1454])
1455
1456;;
1457;; [vhsubq_s, vhsubq_u])
1458;;
1459(define_insn "mve_vhsubq_<supf><mode>"
1460 [
1461 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1462 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1463 (match_operand:MVE_2 2 "s_register_operand" "w")]
1464 VHSUBQ))
1465 ]
1466 "TARGET_HAVE_MVE"
1467 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1468 [(set_attr "type" "mve_move")
1469])
1470
1471;;
1472;; [vmaxaq_s])
1473;;
1474(define_insn "mve_vmaxaq_s<mode>"
1475 [
1476 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1477 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1478 (match_operand:MVE_2 2 "s_register_operand" "w")]
1479 VMAXAQ_S))
1480 ]
1481 "TARGET_HAVE_MVE"
1482 "vmaxa.s%#<V_sz_elem> %q0, %q2"
1483 [(set_attr "type" "mve_move")
1484])
1485
1486;;
1487;; [vmaxavq_s])
1488;;
1489(define_insn "mve_vmaxavq_s<mode>"
1490 [
1491 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1492 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1493 (match_operand:MVE_2 2 "s_register_operand" "w")]
1494 VMAXAVQ_S))
1495 ]
1496 "TARGET_HAVE_MVE"
1497 "vmaxav.s%#<V_sz_elem>\t%0, %q2"
1498 [(set_attr "type" "mve_move")
1499])
1500
1501;;
1502;; [vmaxq_u, vmaxq_s])
1503;;
1504(define_insn "mve_vmaxq_<supf><mode>"
1505 [
1506 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1507 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1508 (match_operand:MVE_2 2 "s_register_operand" "w")]
1509 VMAXQ))
1510 ]
1511 "TARGET_HAVE_MVE"
1512 "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1513 [(set_attr "type" "mve_move")
1514])
1515
1516;;
1517;; [vmaxvq_u, vmaxvq_s])
1518;;
1519(define_insn "mve_vmaxvq_<supf><mode>"
1520 [
1521 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1522 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1523 (match_operand:MVE_2 2 "s_register_operand" "w")]
1524 VMAXVQ))
1525 ]
1526 "TARGET_HAVE_MVE"
1527 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
1528 [(set_attr "type" "mve_move")
1529])
1530
1531;;
1532;; [vminaq_s])
1533;;
1534(define_insn "mve_vminaq_s<mode>"
1535 [
1536 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1537 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1538 (match_operand:MVE_2 2 "s_register_operand" "w")]
1539 VMINAQ_S))
1540 ]
1541 "TARGET_HAVE_MVE"
1542 "vmina.s%#<V_sz_elem>\t%q0, %q2"
1543 [(set_attr "type" "mve_move")
1544])
1545
1546;;
1547;; [vminavq_s])
1548;;
1549(define_insn "mve_vminavq_s<mode>"
1550 [
1551 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1552 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1553 (match_operand:MVE_2 2 "s_register_operand" "w")]
1554 VMINAVQ_S))
1555 ]
1556 "TARGET_HAVE_MVE"
1557 "vminav.s%#<V_sz_elem>\t%0, %q2"
1558 [(set_attr "type" "mve_move")
1559])
1560
1561;;
1562;; [vminq_s, vminq_u])
1563;;
1564(define_insn "mve_vminq_<supf><mode>"
1565 [
1566 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1567 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1568 (match_operand:MVE_2 2 "s_register_operand" "w")]
1569 VMINQ))
1570 ]
1571 "TARGET_HAVE_MVE"
1572 "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1573 [(set_attr "type" "mve_move")
1574])
1575
1576;;
1577;; [vminvq_u, vminvq_s])
1578;;
1579(define_insn "mve_vminvq_<supf><mode>"
1580 [
1581 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1582 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1583 (match_operand:MVE_2 2 "s_register_operand" "w")]
1584 VMINVQ))
1585 ]
1586 "TARGET_HAVE_MVE"
1587 "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
1588 [(set_attr "type" "mve_move")
1589])
1590
1591;;
1592;; [vmladavq_u, vmladavq_s])
1593;;
1594(define_insn "mve_vmladavq_<supf><mode>"
1595 [
1596 (set (match_operand:SI 0 "s_register_operand" "=e")
1597 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1598 (match_operand:MVE_2 2 "s_register_operand" "w")]
1599 VMLADAVQ))
1600 ]
1601 "TARGET_HAVE_MVE"
1602 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1603 [(set_attr "type" "mve_move")
1604])
1605
1606;;
1607;; [vmladavxq_s])
1608;;
1609(define_insn "mve_vmladavxq_s<mode>"
1610 [
1611 (set (match_operand:SI 0 "s_register_operand" "=e")
1612 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1613 (match_operand:MVE_2 2 "s_register_operand" "w")]
1614 VMLADAVXQ_S))
1615 ]
1616 "TARGET_HAVE_MVE"
1617 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1618 [(set_attr "type" "mve_move")
1619])
1620
1621;;
1622;; [vmlsdavq_s])
1623;;
1624(define_insn "mve_vmlsdavq_s<mode>"
1625 [
1626 (set (match_operand:SI 0 "s_register_operand" "=e")
1627 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1628 (match_operand:MVE_2 2 "s_register_operand" "w")]
1629 VMLSDAVQ_S))
1630 ]
1631 "TARGET_HAVE_MVE"
1632 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
1633 [(set_attr "type" "mve_move")
1634])
1635
1636;;
1637;; [vmlsdavxq_s])
1638;;
1639(define_insn "mve_vmlsdavxq_s<mode>"
1640 [
1641 (set (match_operand:SI 0 "s_register_operand" "=e")
1642 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1643 (match_operand:MVE_2 2 "s_register_operand" "w")]
1644 VMLSDAVXQ_S))
1645 ]
1646 "TARGET_HAVE_MVE"
1647 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
1648 [(set_attr "type" "mve_move")
1649])
1650
1651;;
1652;; [vmulhq_s, vmulhq_u])
1653;;
1654(define_insn "mve_vmulhq_<supf><mode>"
1655 [
1656 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1657 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1658 (match_operand:MVE_2 2 "s_register_operand" "w")]
1659 VMULHQ))
1660 ]
1661 "TARGET_HAVE_MVE"
1662 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1663 [(set_attr "type" "mve_move")
1664])
1665
1666;;
1667;; [vmullbq_int_u, vmullbq_int_s])
1668;;
1669(define_insn "mve_vmullbq_int_<supf><mode>"
1670 [
1671 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1672 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1673 (match_operand:MVE_2 2 "s_register_operand" "w")]
1674 VMULLBQ_INT))
1675 ]
1676 "TARGET_HAVE_MVE"
1677 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1678 [(set_attr "type" "mve_move")
1679])
1680
1681;;
1682;; [vmulltq_int_u, vmulltq_int_s])
1683;;
1684(define_insn "mve_vmulltq_int_<supf><mode>"
1685 [
1686 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1687 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
1688 (match_operand:MVE_2 2 "s_register_operand" "w")]
1689 VMULLTQ_INT))
1690 ]
1691 "TARGET_HAVE_MVE"
1692 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1693 [(set_attr "type" "mve_move")
1694])
1695
1696;;
1697;; [vmulq_n_u, vmulq_n_s])
1698;;
1699(define_insn "mve_vmulq_n_<supf><mode>"
1700 [
1701 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1702 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1703 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1704 VMULQ_N))
1705 ]
1706 "TARGET_HAVE_MVE"
1707 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2"
1708 [(set_attr "type" "mve_move")
1709])
1710
1711;;
1712;; [vmulq_u, vmulq_s])
1713;;
1714(define_insn "mve_vmulq_<supf><mode>"
1715 [
1716 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1717 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1718 (match_operand:MVE_2 2 "s_register_operand" "w")]
1719 VMULQ))
1720 ]
1721 "TARGET_HAVE_MVE"
1722 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
1723 [(set_attr "type" "mve_move")
1724])
1725
1726;;
1727;; [vornq_u, vornq_s])
1728;;
1729(define_insn "mve_vornq_<supf><mode>"
1730 [
1731 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1732 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1733 (match_operand:MVE_2 2 "s_register_operand" "w")]
1734 VORNQ))
1735 ]
1736 "TARGET_HAVE_MVE"
1737 "vorn %q0, %q1, %q2"
1738 [(set_attr "type" "mve_move")
1739])
1740
1741;;
1742;; [vorrq_s, vorrq_u])
1743;;
1744(define_insn "mve_vorrq_<supf><mode>"
1745 [
1746 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1747 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1748 (match_operand:MVE_2 2 "s_register_operand" "w")]
1749 VORRQ))
1750 ]
1751 "TARGET_HAVE_MVE"
1752 "vorr %q0, %q1, %q2"
1753 [(set_attr "type" "mve_move")
1754])
1755
1756;;
1757;; [vqaddq_n_s, vqaddq_n_u])
1758;;
1759(define_insn "mve_vqaddq_n_<supf><mode>"
1760 [
1761 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1762 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1763 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1764 VQADDQ_N))
1765 ]
1766 "TARGET_HAVE_MVE"
1767 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1768 [(set_attr "type" "mve_move")
1769])
1770
1771;;
1772;; [vqaddq_u, vqaddq_s])
1773;;
1774(define_insn "mve_vqaddq_<supf><mode>"
1775 [
1776 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1777 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1778 (match_operand:MVE_2 2 "s_register_operand" "w")]
1779 VQADDQ))
1780 ]
1781 "TARGET_HAVE_MVE"
1782 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1783 [(set_attr "type" "mve_move")
1784])
1785
1786;;
1787;; [vqdmulhq_n_s])
1788;;
1789(define_insn "mve_vqdmulhq_n_s<mode>"
1790 [
1791 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1792 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1793 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1794 VQDMULHQ_N_S))
1795 ]
1796 "TARGET_HAVE_MVE"
1797 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
1798 [(set_attr "type" "mve_move")
1799])
1800
1801;;
1802;; [vqdmulhq_s])
1803;;
1804(define_insn "mve_vqdmulhq_s<mode>"
1805 [
1806 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1807 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1808 (match_operand:MVE_2 2 "s_register_operand" "w")]
1809 VQDMULHQ_S))
1810 ]
1811 "TARGET_HAVE_MVE"
1812 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
1813 [(set_attr "type" "mve_move")
1814])
1815
1816;;
1817;; [vqrdmulhq_n_s])
1818;;
1819(define_insn "mve_vqrdmulhq_n_s<mode>"
1820 [
1821 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1822 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1823 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1824 VQRDMULHQ_N_S))
1825 ]
1826 "TARGET_HAVE_MVE"
1827 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
1828 [(set_attr "type" "mve_move")
1829])
1830
1831;;
1832;; [vqrdmulhq_s])
1833;;
1834(define_insn "mve_vqrdmulhq_s<mode>"
1835 [
1836 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1837 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1838 (match_operand:MVE_2 2 "s_register_operand" "w")]
1839 VQRDMULHQ_S))
1840 ]
1841 "TARGET_HAVE_MVE"
1842 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2"
1843 [(set_attr "type" "mve_move")
1844])
1845
1846;;
1847;; [vqrshlq_n_s, vqrshlq_n_u])
1848;;
1849(define_insn "mve_vqrshlq_n_<supf><mode>"
1850 [
1851 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1852 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1853 (match_operand:SI 2 "s_register_operand" "r")]
1854 VQRSHLQ_N))
1855 ]
1856 "TARGET_HAVE_MVE"
1857 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
1858 [(set_attr "type" "mve_move")
1859])
1860
1861;;
1862;; [vqrshlq_s, vqrshlq_u])
1863;;
1864(define_insn "mve_vqrshlq_<supf><mode>"
1865 [
1866 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1867 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1868 (match_operand:MVE_2 2 "s_register_operand" "w")]
1869 VQRSHLQ))
1870 ]
1871 "TARGET_HAVE_MVE"
1872 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1873 [(set_attr "type" "mve_move")
1874])
1875
1876;;
1877;; [vqshlq_n_s, vqshlq_n_u])
1878;;
1879(define_insn "mve_vqshlq_n_<supf><mode>"
1880 [
1881 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1882 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1883 (match_operand:SI 2 "immediate_operand" "i")]
1884 VQSHLQ_N))
1885 ]
1886 "TARGET_HAVE_MVE"
1887 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1888 [(set_attr "type" "mve_move")
1889])
1890
1891;;
1892;; [vqshlq_r_u, vqshlq_r_s])
1893;;
1894(define_insn "mve_vqshlq_r_<supf><mode>"
1895 [
1896 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1897 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1898 (match_operand:SI 2 "s_register_operand" "r")]
1899 VQSHLQ_R))
1900 ]
1901 "TARGET_HAVE_MVE"
1902 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
1903 [(set_attr "type" "mve_move")
1904])
1905
1906;;
1907;; [vqshlq_s, vqshlq_u])
1908;;
1909(define_insn "mve_vqshlq_<supf><mode>"
1910 [
1911 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1912 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1913 (match_operand:MVE_2 2 "s_register_operand" "w")]
1914 VQSHLQ))
1915 ]
1916 "TARGET_HAVE_MVE"
1917 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1918 [(set_attr "type" "mve_move")
1919])
1920
1921;;
1922;; [vqshluq_n_s])
1923;;
1924(define_insn "mve_vqshluq_n_s<mode>"
1925 [
1926 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1927 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1928 (match_operand:SI 2 "mve_imm_7" "Ra")]
1929 VQSHLUQ_N_S))
1930 ]
1931 "TARGET_HAVE_MVE"
1932 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
1933 [(set_attr "type" "mve_move")
1934])
1935
1936;;
1937;; [vqsubq_n_s, vqsubq_n_u])
1938;;
1939(define_insn "mve_vqsubq_n_<supf><mode>"
1940 [
1941 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1942 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1943 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1944 VQSUBQ_N))
1945 ]
1946 "TARGET_HAVE_MVE"
1947 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1948 [(set_attr "type" "mve_move")
1949])
1950
1951;;
1952;; [vqsubq_u, vqsubq_s])
1953;;
1954(define_insn "mve_vqsubq_<supf><mode>"
1955 [
1956 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1957 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1958 (match_operand:MVE_2 2 "s_register_operand" "w")]
1959 VQSUBQ))
1960 ]
1961 "TARGET_HAVE_MVE"
1962 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1963 [(set_attr "type" "mve_move")
1964])
1965
1966;;
1967;; [vrhaddq_s, vrhaddq_u])
1968;;
1969(define_insn "mve_vrhaddq_<supf><mode>"
1970 [
1971 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1972 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1973 (match_operand:MVE_2 2 "s_register_operand" "w")]
1974 VRHADDQ))
1975 ]
1976 "TARGET_HAVE_MVE"
1977 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1978 [(set_attr "type" "mve_move")
1979])
1980
1981;;
1982;; [vrmulhq_s, vrmulhq_u])
1983;;
1984(define_insn "mve_vrmulhq_<supf><mode>"
1985 [
1986 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1987 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1988 (match_operand:MVE_2 2 "s_register_operand" "w")]
1989 VRMULHQ))
1990 ]
1991 "TARGET_HAVE_MVE"
1992 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1993 [(set_attr "type" "mve_move")
1994])
1995
1996;;
1997;; [vrshlq_n_u, vrshlq_n_s])
1998;;
1999(define_insn "mve_vrshlq_n_<supf><mode>"
2000 [
2001 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2002 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2003 (match_operand:SI 2 "s_register_operand" "r")]
2004 VRSHLQ_N))
2005 ]
2006 "TARGET_HAVE_MVE"
2007 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
2008 [(set_attr "type" "mve_move")
2009])
2010
2011;;
2012;; [vrshlq_s, vrshlq_u])
2013;;
2014(define_insn "mve_vrshlq_<supf><mode>"
2015 [
2016 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2017 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2018 (match_operand:MVE_2 2 "s_register_operand" "w")]
2019 VRSHLQ))
2020 ]
2021 "TARGET_HAVE_MVE"
2022 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
2023 [(set_attr "type" "mve_move")
2024])
2025
2026;;
2027;; [vrshrq_n_s, vrshrq_n_u])
2028;;
2029(define_insn "mve_vrshrq_n_<supf><mode>"
2030 [
2031 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2032 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2033 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
2034 VRSHRQ_N))
2035 ]
2036 "TARGET_HAVE_MVE"
2037 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2038 [(set_attr "type" "mve_move")
2039])
2040
2041;;
2042;; [vshlq_n_u, vshlq_n_s])
2043;;
2044(define_insn "mve_vshlq_n_<supf><mode>"
2045 [
2046 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2047 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2048 (match_operand:SI 2 "immediate_operand" "i")]
2049 VSHLQ_N))
2050 ]
2051 "TARGET_HAVE_MVE"
2052 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2053 [(set_attr "type" "mve_move")
2054])
2055
2056;;
2057;; [vshlq_r_s, vshlq_r_u])
2058;;
2059(define_insn "mve_vshlq_r_<supf><mode>"
2060 [
2061 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2062 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2063 (match_operand:SI 2 "s_register_operand" "r")]
2064 VSHLQ_R))
2065 ]
2066 "TARGET_HAVE_MVE"
2067 "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
2068 [(set_attr "type" "mve_move")
2069])
2070
2071;;
2072;; [vsubq_n_s, vsubq_n_u])
2073;;
2074(define_insn "mve_vsubq_n_<supf><mode>"
2075 [
2076 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2077 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2078 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2079 VSUBQ_N))
2080 ]
2081 "TARGET_HAVE_MVE"
2082 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2"
2083 [(set_attr "type" "mve_move")
2084])
2085
2086;;
2087;; [vsubq_s, vsubq_u])
2088;;
2089(define_insn "mve_vsubq_<supf><mode>"
2090 [
2091 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2092 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
2093 (match_operand:MVE_2 2 "s_register_operand" "w")]
2094 VSUBQ))
2095 ]
2096 "TARGET_HAVE_MVE"
2097 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
2098 [(set_attr "type" "mve_move")
2099])
f9355dee
SP		 2100
2101;;
2102;; [vabdq_f])
2103;;
2104(define_insn "mve_vabdq_f<mode>"
2105 [
2106 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2107 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2108 (match_operand:MVE_0 2 "s_register_operand" "w")]
2109 VABDQ_F))
2110 ]
2111 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2112 "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
2113 [(set_attr "type" "mve_move")
2114])
2115
2116;;
2117;; [vaddlvaq_s vaddlvaq_u])
2118;;
2119(define_insn "mve_vaddlvaq_<supf>v4si"
2120 [
2121 (set (match_operand:DI 0 "s_register_operand" "=r")
2122 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2123 (match_operand:V4SI 2 "s_register_operand" "w")]
2124 VADDLVAQ))
2125 ]
2126 "TARGET_HAVE_MVE"
2127 "vaddlva.<supf>32 %Q0, %R0, %q2"
2128 [(set_attr "type" "mve_move")
2129])
2130
2131;;
2132;; [vaddq_n_f])
2133;;
2134(define_insn "mve_vaddq_n_f<mode>"
2135 [
2136 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2137 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2138 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2139 VADDQ_N_F))
2140 ]
2141 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2142 "vadd.f%#<V_sz_elem> %q0, %q1, %2"
2143 [(set_attr "type" "mve_move")
2144])
2145
2146;;
2147;; [vandq_f])
2148;;
2149(define_insn "mve_vandq_f<mode>"
2150 [
2151 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2152 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2153 (match_operand:MVE_0 2 "s_register_operand" "w")]
2154 VANDQ_F))
2155 ]
2156 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2157 "vand %q0, %q1, %q2"
2158 [(set_attr "type" "mve_move")
2159])
2160
2161;;
2162;; [vbicq_f])
2163;;
2164(define_insn "mve_vbicq_f<mode>"
2165 [
2166 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2167 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2168 (match_operand:MVE_0 2 "s_register_operand" "w")]
2169 VBICQ_F))
2170 ]
2171 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2172 "vbic %q0, %q1, %q2"
2173 [(set_attr "type" "mve_move")
2174])
2175
2176;;
2177;; [vbicq_n_s, vbicq_n_u])
2178;;
2179(define_insn "mve_vbicq_n_<supf><mode>"
2180 [
2181 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2182 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2183 (match_operand:SI 2 "immediate_operand" "i")]
2184 VBICQ_N))
2185 ]
2186 "TARGET_HAVE_MVE"
2187 "vbic.i%#<V_sz_elem> %q0, %2"
2188 [(set_attr "type" "mve_move")
2189])
2190
2191;;
2192;; [vcaddq_rot270_f])
2193;;
2194(define_insn "mve_vcaddq_rot270_f<mode>"
2195 [
2196 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2197 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2198 (match_operand:MVE_0 2 "s_register_operand" "w")]
2199 VCADDQ_ROT270_F))
2200 ]
2201 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2202 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2203 [(set_attr "type" "mve_move")
2204])
2205
2206;;
2207;; [vcaddq_rot90_f])
2208;;
2209(define_insn "mve_vcaddq_rot90_f<mode>"
2210 [
2211 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2212 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2213 (match_operand:MVE_0 2 "s_register_operand" "w")]
2214 VCADDQ_ROT90_F))
2215 ]
2216 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2217 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2218 [(set_attr "type" "mve_move")
2219])
2220
2221;;
2222;; [vcmpeqq_f])
2223;;
2224(define_insn "mve_vcmpeqq_f<mode>"
2225 [
2226 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2227 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2228 (match_operand:MVE_0 2 "s_register_operand" "w")]
2229 VCMPEQQ_F))
2230 ]
2231 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2232 "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
2233 [(set_attr "type" "mve_move")
2234])
2235
2236;;
2237;; [vcmpeqq_n_f])
2238;;
2239(define_insn "mve_vcmpeqq_n_f<mode>"
2240 [
2241 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2242 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2243 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2244 VCMPEQQ_N_F))
2245 ]
2246 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2247 "vcmp.f%#<V_sz_elem> eq, %q1, %2"
2248 [(set_attr "type" "mve_move")
2249])
2250
2251;;
2252;; [vcmpgeq_f])
2253;;
2254(define_insn "mve_vcmpgeq_f<mode>"
2255 [
2256 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2257 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2258 (match_operand:MVE_0 2 "s_register_operand" "w")]
2259 VCMPGEQ_F))
2260 ]
2261 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2262 "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
2263 [(set_attr "type" "mve_move")
2264])
2265
2266;;
2267;; [vcmpgeq_n_f])
2268;;
2269(define_insn "mve_vcmpgeq_n_f<mode>"
2270 [
2271 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2272 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2273 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2274 VCMPGEQ_N_F))
2275 ]
2276 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2277 "vcmp.f%#<V_sz_elem> ge, %q1, %2"
2278 [(set_attr "type" "mve_move")
2279])
2280
2281;;
2282;; [vcmpgtq_f])
2283;;
2284(define_insn "mve_vcmpgtq_f<mode>"
2285 [
2286 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2287 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2288 (match_operand:MVE_0 2 "s_register_operand" "w")]
2289 VCMPGTQ_F))
2290 ]
2291 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2292 "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
2293 [(set_attr "type" "mve_move")
2294])
2295
2296;;
2297;; [vcmpgtq_n_f])
2298;;
2299(define_insn "mve_vcmpgtq_n_f<mode>"
2300 [
2301 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2302 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2303 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2304 VCMPGTQ_N_F))
2305 ]
2306 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2307 "vcmp.f%#<V_sz_elem> gt, %q1, %2"
2308 [(set_attr "type" "mve_move")
2309])
2310
2311;;
2312;; [vcmpleq_f])
2313;;
2314(define_insn "mve_vcmpleq_f<mode>"
2315 [
2316 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2317 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2318 (match_operand:MVE_0 2 "s_register_operand" "w")]
2319 VCMPLEQ_F))
2320 ]
2321 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2322 "vcmp.f%#<V_sz_elem> le, %q1, %q2"
2323 [(set_attr "type" "mve_move")
2324])
2325
2326;;
2327;; [vcmpleq_n_f])
2328;;
2329(define_insn "mve_vcmpleq_n_f<mode>"
2330 [
2331 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2332 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2333 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2334 VCMPLEQ_N_F))
2335 ]
2336 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2337 "vcmp.f%#<V_sz_elem> le, %q1, %2"
2338 [(set_attr "type" "mve_move")
2339])
2340
2341;;
2342;; [vcmpltq_f])
2343;;
2344(define_insn "mve_vcmpltq_f<mode>"
2345 [
2346 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2347 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2348 (match_operand:MVE_0 2 "s_register_operand" "w")]
2349 VCMPLTQ_F))
2350 ]
2351 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2352 "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
2353 [(set_attr "type" "mve_move")
2354])
2355
2356;;
2357;; [vcmpltq_n_f])
2358;;
2359(define_insn "mve_vcmpltq_n_f<mode>"
2360 [
2361 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2362 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2363 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2364 VCMPLTQ_N_F))
2365 ]
2366 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2367 "vcmp.f%#<V_sz_elem> lt, %q1, %2"
2368 [(set_attr "type" "mve_move")
2369])
2370
2371;;
2372;; [vcmpneq_f])
2373;;
2374(define_insn "mve_vcmpneq_f<mode>"
2375 [
2376 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2377 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2378 (match_operand:MVE_0 2 "s_register_operand" "w")]
2379 VCMPNEQ_F))
2380 ]
2381 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2382 "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
2383 [(set_attr "type" "mve_move")
2384])
2385
2386;;
2387;; [vcmpneq_n_f])
2388;;
2389(define_insn "mve_vcmpneq_n_f<mode>"
2390 [
2391 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2392 (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
2393 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2394 VCMPNEQ_N_F))
2395 ]
2396 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2397 "vcmp.f%#<V_sz_elem> ne, %q1, %2"
2398 [(set_attr "type" "mve_move")
2399])
2400
2401;;
2402;; [vcmulq_f])
2403;;
2404(define_insn "mve_vcmulq_f<mode>"
2405 [
2406 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2407 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2408 (match_operand:MVE_0 2 "s_register_operand" "w")]
2409 VCMULQ_F))
2410 ]
2411 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2412 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
2413 [(set_attr "type" "mve_move")
2414])
2415
2416;;
2417;; [vcmulq_rot180_f])
2418;;
2419(define_insn "mve_vcmulq_rot180_f<mode>"
2420 [
2421 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2422 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2423 (match_operand:MVE_0 2 "s_register_operand" "w")]
2424 VCMULQ_ROT180_F))
2425 ]
2426 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2427 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
2428 [(set_attr "type" "mve_move")
2429])
2430
2431;;
2432;; [vcmulq_rot270_f])
2433;;
2434(define_insn "mve_vcmulq_rot270_f<mode>"
2435 [
2436 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2437 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2438 (match_operand:MVE_0 2 "s_register_operand" "w")]
2439 VCMULQ_ROT270_F))
2440 ]
2441 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2442 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
2443 [(set_attr "type" "mve_move")
2444])
2445
2446;;
2447;; [vcmulq_rot90_f])
2448;;
2449(define_insn "mve_vcmulq_rot90_f<mode>"
2450 [
2451 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2452 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2453 (match_operand:MVE_0 2 "s_register_operand" "w")]
2454 VCMULQ_ROT90_F))
2455 ]
2456 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2457 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
2458 [(set_attr "type" "mve_move")
2459])
2460
2461;;
2462;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
2463;;
2464(define_insn "mve_vctp<mode1>q_mhi"
2465 [
2466 (set (match_operand:HI 0 "vpr_register_operand" "=Up")
2467 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")
2468 (match_operand:HI 2 "vpr_register_operand" "Up")]
2469 VCTPQ_M))
2470 ]
2471 "TARGET_HAVE_MVE"
2472 "vpst\;vctpt.<mode1> %1"
2473 [(set_attr "type" "mve_move")
2474 (set_attr "length""8")])
2475
2476;;
2477;; [vcvtbq_f16_f32])
2478;;
2479(define_insn "mve_vcvtbq_f16_f32v8hf"
2480 [
2481 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2482 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2483 (match_operand:V4SF 2 "s_register_operand" "w")]
2484 VCVTBQ_F16_F32))
2485 ]
2486 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2487 "vcvtb.f16.f32 %q0, %q2"
2488 [(set_attr "type" "mve_move")
2489])
2490
2491;;
2492;; [vcvttq_f16_f32])
2493;;
2494(define_insn "mve_vcvttq_f16_f32v8hf"
2495 [
2496 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2497 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2498 (match_operand:V4SF 2 "s_register_operand" "w")]
2499 VCVTTQ_F16_F32))
2500 ]
2501 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2502 "vcvtt.f16.f32 %q0, %q2"
2503 [(set_attr "type" "mve_move")
2504])
2505
2506;;
2507;; [veorq_f])
2508;;
2509(define_insn "mve_veorq_f<mode>"
2510 [
2511 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2512 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2513 (match_operand:MVE_0 2 "s_register_operand" "w")]
2514 VEORQ_F))
2515 ]
2516 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2517 "veor %q0, %q1, %q2"
2518 [(set_attr "type" "mve_move")
2519])
2520
2521;;
2522;; [vmaxnmaq_f])
2523;;
2524(define_insn "mve_vmaxnmaq_f<mode>"
2525 [
2526 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2527 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2528 (match_operand:MVE_0 2 "s_register_operand" "w")]
2529 VMAXNMAQ_F))
2530 ]
2531 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2532 "vmaxnma.f%#<V_sz_elem> %q0, %q2"
2533 [(set_attr "type" "mve_move")
2534])
2535
2536;;
2537;; [vmaxnmavq_f])
2538;;
2539(define_insn "mve_vmaxnmavq_f<mode>"
2540 [
2541 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2542 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2543 (match_operand:MVE_0 2 "s_register_operand" "w")]
2544 VMAXNMAVQ_F))
2545 ]
2546 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2547 "vmaxnmav.f%#<V_sz_elem> %0, %q2"
2548 [(set_attr "type" "mve_move")
2549])
2550
2551;;
2552;; [vmaxnmq_f])
2553;;
2554(define_insn "mve_vmaxnmq_f<mode>"
2555 [
2556 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2557 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2558 (match_operand:MVE_0 2 "s_register_operand" "w")]
2559 VMAXNMQ_F))
2560 ]
2561 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2562 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
2563 [(set_attr "type" "mve_move")
2564])
2565
2566;;
2567;; [vmaxnmvq_f])
2568;;
2569(define_insn "mve_vmaxnmvq_f<mode>"
2570 [
2571 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2572 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2573 (match_operand:MVE_0 2 "s_register_operand" "w")]
2574 VMAXNMVQ_F))
2575 ]
2576 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2577 "vmaxnmv.f%#<V_sz_elem> %0, %q2"
2578 [(set_attr "type" "mve_move")
2579])
2580
2581;;
2582;; [vminnmaq_f])
2583;;
2584(define_insn "mve_vminnmaq_f<mode>"
2585 [
2586 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2587 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2588 (match_operand:MVE_0 2 "s_register_operand" "w")]
2589 VMINNMAQ_F))
2590 ]
2591 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2592 "vminnma.f%#<V_sz_elem> %q0, %q2"
2593 [(set_attr "type" "mve_move")
2594])
2595
2596;;
2597;; [vminnmavq_f])
2598;;
2599(define_insn "mve_vminnmavq_f<mode>"
2600 [
2601 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2602 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2603 (match_operand:MVE_0 2 "s_register_operand" "w")]
2604 VMINNMAVQ_F))
2605 ]
2606 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2607 "vminnmav.f%#<V_sz_elem> %0, %q2"
2608 [(set_attr "type" "mve_move")
2609])
2610
2611;;
2612;; [vminnmq_f])
2613;;
2614(define_insn "mve_vminnmq_f<mode>"
2615 [
2616 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2617 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2618 (match_operand:MVE_0 2 "s_register_operand" "w")]
2619 VMINNMQ_F))
2620 ]
2621 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2622 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
2623 [(set_attr "type" "mve_move")
2624])
2625
2626;;
2627;; [vminnmvq_f])
2628;;
2629(define_insn "mve_vminnmvq_f<mode>"
2630 [
2631 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2632 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2633 (match_operand:MVE_0 2 "s_register_operand" "w")]
2634 VMINNMVQ_F))
2635 ]
2636 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2637 "vminnmv.f%#<V_sz_elem> %0, %q2"
2638 [(set_attr "type" "mve_move")
2639])
2640
2641;;
2642;; [vmlaldavq_u, vmlaldavq_s])
2643;;
2644(define_insn "mve_vmlaldavq_<supf><mode>"
2645 [
2646 (set (match_operand:DI 0 "s_register_operand" "=r")
2647 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2648 (match_operand:MVE_5 2 "s_register_operand" "w")]
2649 VMLALDAVQ))
2650 ]
2651 "TARGET_HAVE_MVE"
2652 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2653 [(set_attr "type" "mve_move")
2654])
2655
2656;;
2657;; [vmlaldavxq_s])
2658;;
2659(define_insn "mve_vmlaldavxq_s<mode>"
2660 [
2661 (set (match_operand:DI 0 "s_register_operand" "=r")
2662 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2663 (match_operand:MVE_5 2 "s_register_operand" "w")]
2664 VMLALDAVXQ_S))
2665 ]
2666 "TARGET_HAVE_MVE"
2667 "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2668 [(set_attr "type" "mve_move")
2669])
2670
2671;;
2672;; [vmlsldavq_s])
2673;;
2674(define_insn "mve_vmlsldavq_s<mode>"
2675 [
2676 (set (match_operand:DI 0 "s_register_operand" "=r")
2677 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2678 (match_operand:MVE_5 2 "s_register_operand" "w")]
2679 VMLSLDAVQ_S))
2680 ]
2681 "TARGET_HAVE_MVE"
2682 "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2683 [(set_attr "type" "mve_move")
2684])
2685
2686;;
2687;; [vmlsldavxq_s])
2688;;
2689(define_insn "mve_vmlsldavxq_s<mode>"
2690 [
2691 (set (match_operand:DI 0 "s_register_operand" "=r")
2692 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2693 (match_operand:MVE_5 2 "s_register_operand" "w")]
2694 VMLSLDAVXQ_S))
2695 ]
2696 "TARGET_HAVE_MVE"
2697 "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
2698 [(set_attr "type" "mve_move")
2699])
2700
2701;;
2702;; [vmovnbq_u, vmovnbq_s])
2703;;
2704(define_insn "mve_vmovnbq_<supf><mode>"
2705 [
2706 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2707 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2708 (match_operand:MVE_5 2 "s_register_operand" "w")]
2709 VMOVNBQ))
2710 ]
2711 "TARGET_HAVE_MVE"
2712 "vmovnb.i%#<V_sz_elem> %q0, %q2"
2713 [(set_attr "type" "mve_move")
2714])
2715
2716;;
2717;; [vmovntq_s, vmovntq_u])
2718;;
2719(define_insn "mve_vmovntq_<supf><mode>"
2720 [
2721 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2722 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2723 (match_operand:MVE_5 2 "s_register_operand" "w")]
2724 VMOVNTQ))
2725 ]
2726 "TARGET_HAVE_MVE"
2727 "vmovnt.i%#<V_sz_elem> %q0, %q2"
2728 [(set_attr "type" "mve_move")
2729])
2730
2731;;
2732;; [vmulq_f])
2733;;
2734(define_insn "mve_vmulq_f<mode>"
2735 [
2736 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2737 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2738 (match_operand:MVE_0 2 "s_register_operand" "w")]
2739 VMULQ_F))
2740 ]
2741 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2742 "vmul.f%#<V_sz_elem> %q0, %q1, %q2"
2743 [(set_attr "type" "mve_move")
2744])
2745
2746;;
2747;; [vmulq_n_f])
2748;;
2749(define_insn "mve_vmulq_n_f<mode>"
2750 [
2751 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2752 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2753 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2754 VMULQ_N_F))
2755 ]
2756 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2757 "vmul.f%#<V_sz_elem> %q0, %q1, %2"
2758 [(set_attr "type" "mve_move")
2759])
2760
2761;;
2762;; [vornq_f])
2763;;
2764(define_insn "mve_vornq_f<mode>"
2765 [
2766 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2767 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2768 (match_operand:MVE_0 2 "s_register_operand" "w")]
2769 VORNQ_F))
2770 ]
2771 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2772 "vorn %q0, %q1, %q2"
2773 [(set_attr "type" "mve_move")
2774])
2775
2776;;
2777;; [vorrq_f])
2778;;
2779(define_insn "mve_vorrq_f<mode>"
2780 [
2781 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2782 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2783 (match_operand:MVE_0 2 "s_register_operand" "w")]
2784 VORRQ_F))
2785 ]
2786 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2787 "vorr %q0, %q1, %q2"
2788 [(set_attr "type" "mve_move")
2789])
2790
2791;;
2792;; [vorrq_n_u, vorrq_n_s])
2793;;
2794(define_insn "mve_vorrq_n_<supf><mode>"
2795 [
2796 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2797 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2798 (match_operand:SI 2 "immediate_operand" "i")]
2799 VORRQ_N))
2800 ]
2801 "TARGET_HAVE_MVE"
2802 "vorr.i%#<V_sz_elem> %q0, %2"
2803 [(set_attr "type" "mve_move")
2804])
2805
2806;;
2807;; [vqdmullbq_n_s])
2808;;
2809(define_insn "mve_vqdmullbq_n_s<mode>"
2810 [
2811 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2812 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2813 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2814 VQDMULLBQ_N_S))
2815 ]
2816 "TARGET_HAVE_MVE"
2817 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2"
2818 [(set_attr "type" "mve_move")
2819])
2820
2821;;
2822;; [vqdmullbq_s])
2823;;
2824(define_insn "mve_vqdmullbq_s<mode>"
2825 [
2826 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2827 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2828 (match_operand:MVE_5 2 "s_register_operand" "w")]
2829 VQDMULLBQ_S))
2830 ]
2831 "TARGET_HAVE_MVE"
2832 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2"
2833 [(set_attr "type" "mve_move")
2834])
2835
2836;;
2837;; [vqdmulltq_n_s])
2838;;
2839(define_insn "mve_vqdmulltq_n_s<mode>"
2840 [
2841 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2842 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2843 (match_operand:<V_elem> 2 "s_register_operand" "r")]
2844 VQDMULLTQ_N_S))
2845 ]
2846 "TARGET_HAVE_MVE"
2847 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2"
2848 [(set_attr "type" "mve_move")
2849])
2850
2851;;
2852;; [vqdmulltq_s])
2853;;
2854(define_insn "mve_vqdmulltq_s<mode>"
2855 [
2856 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2857 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
2858 (match_operand:MVE_5 2 "s_register_operand" "w")]
2859 VQDMULLTQ_S))
2860 ]
2861 "TARGET_HAVE_MVE"
2862 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2"
2863 [(set_attr "type" "mve_move")
2864])
2865
2866;;
2867;; [vqmovnbq_u, vqmovnbq_s])
2868;;
2869(define_insn "mve_vqmovnbq_<supf><mode>"
2870 [
2871 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2872 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2873 (match_operand:MVE_5 2 "s_register_operand" "w")]
2874 VQMOVNBQ))
2875 ]
2876 "TARGET_HAVE_MVE"
2877 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2"
2878 [(set_attr "type" "mve_move")
2879])
2880
2881;;
2882;; [vqmovntq_u, vqmovntq_s])
2883;;
2884(define_insn "mve_vqmovntq_<supf><mode>"
2885 [
2886 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2887 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2888 (match_operand:MVE_5 2 "s_register_operand" "w")]
2889 VQMOVNTQ))
2890 ]
2891 "TARGET_HAVE_MVE"
2892 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2"
2893 [(set_attr "type" "mve_move")
2894])
2895
2896;;
2897;; [vqmovunbq_s])
2898;;
2899(define_insn "mve_vqmovunbq_s<mode>"
2900 [
2901 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2902 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2903 (match_operand:MVE_5 2 "s_register_operand" "w")]
2904 VQMOVUNBQ_S))
2905 ]
2906 "TARGET_HAVE_MVE"
2907 "vqmovunb.s%#<V_sz_elem> %q0, %q2"
2908 [(set_attr "type" "mve_move")
2909])
2910
2911;;
2912;; [vqmovuntq_s])
2913;;
2914(define_insn "mve_vqmovuntq_s<mode>"
2915 [
2916 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2917 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2918 (match_operand:MVE_5 2 "s_register_operand" "w")]
2919 VQMOVUNTQ_S))
2920 ]
2921 "TARGET_HAVE_MVE"
2922 "vqmovunt.s%#<V_sz_elem> %q0, %q2"
2923 [(set_attr "type" "mve_move")
2924])
2925
2926;;
2927;; [vrmlaldavhxq_s])
2928;;
2929(define_insn "mve_vrmlaldavhxq_sv4si"
2930 [
2931 (set (match_operand:DI 0 "s_register_operand" "=r")
2932 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2933 (match_operand:V4SI 2 "s_register_operand" "w")]
2934 VRMLALDAVHXQ_S))
2935 ]
2936 "TARGET_HAVE_MVE"
2937 "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
2938 [(set_attr "type" "mve_move")
2939])
2940
2941;;
2942;; [vrmlsldavhq_s])
2943;;
2944(define_insn "mve_vrmlsldavhq_sv4si"
2945 [
2946 (set (match_operand:DI 0 "s_register_operand" "=r")
2947 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2948 (match_operand:V4SI 2 "s_register_operand" "w")]
2949 VRMLSLDAVHQ_S))
2950 ]
2951 "TARGET_HAVE_MVE"
2952 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
2953 [(set_attr "type" "mve_move")
2954])
2955
2956;;
2957;; [vrmlsldavhxq_s])
2958;;
2959(define_insn "mve_vrmlsldavhxq_sv4si"
2960 [
2961 (set (match_operand:DI 0 "s_register_operand" "=r")
2962 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2963 (match_operand:V4SI 2 "s_register_operand" "w")]
2964 VRMLSLDAVHXQ_S))
2965 ]
2966 "TARGET_HAVE_MVE"
2967 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
2968 [(set_attr "type" "mve_move")
2969])
2970
2971;;
2972;; [vshllbq_n_s, vshllbq_n_u])
2973;;
2974(define_insn "mve_vshllbq_n_<supf><mode>"
2975 [
2976 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2977 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2978 (match_operand:SI 2 "immediate_operand" "i")]
2979 VSHLLBQ_N))
2980 ]
2981 "TARGET_HAVE_MVE"
2982 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2983 [(set_attr "type" "mve_move")
2984])
2985
2986;;
2987;; [vshlltq_n_u, vshlltq_n_s])
2988;;
2989(define_insn "mve_vshlltq_n_<supf><mode>"
2990 [
2991 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2992 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
2993 (match_operand:SI 2 "immediate_operand" "i")]
2994 VSHLLTQ_N))
2995 ]
2996 "TARGET_HAVE_MVE"
2997 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
2998 [(set_attr "type" "mve_move")
2999])
3000
3001;;
3002;; [vsubq_f])
3003;;
3004(define_insn "mve_vsubq_f<mode>"
3005 [
3006 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3007 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
3008 (match_operand:MVE_0 2 "s_register_operand" "w")]
3009 VSUBQ_F))
3010 ]
3011 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3012 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
3013 [(set_attr "type" "mve_move")
3014])
3015
3016;;
3017;; [vmulltq_poly_p])
3018;;
3019(define_insn "mve_vmulltq_poly_p<mode>"
3020 [
3021 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3022 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3023 (match_operand:MVE_3 2 "s_register_operand" "w")]
3024 VMULLTQ_POLY_P))
3025 ]
3026 "TARGET_HAVE_MVE"
3027 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2"
3028 [(set_attr "type" "mve_move")
3029])
3030
3031;;
3032;; [vmullbq_poly_p])
3033;;
3034(define_insn "mve_vmullbq_poly_p<mode>"
3035 [
3036 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
3037 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
3038 (match_operand:MVE_3 2 "s_register_operand" "w")]
3039 VMULLBQ_POLY_P))
3040 ]
3041 "TARGET_HAVE_MVE"
3042 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2"
3043 [(set_attr "type" "mve_move")
3044])
3045
3046;;
3047;; [vrmlaldavhq_u vrmlaldavhq_s])
3048;;
3049(define_insn "mve_vrmlaldavhq_<supf>v4si"
3050 [
3051 (set (match_operand:DI 0 "s_register_operand" "=r")
3052 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
3053 (match_operand:V4SI 2 "s_register_operand" "w")]
3054 VRMLALDAVHQ))
3055 ]
3056 "TARGET_HAVE_MVE"
3057 "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
3058 [(set_attr "type" "mve_move")
3059])
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