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a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
a5544970 | 2 | ;; Copyright (C) 2004-2019 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
d435a4be | 29 | return (REG_P (op) |
a657c98a RE |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
89d75572 TP |
34 | ; Predicate for stack protector guard's address in |
35 | ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns | |
36 | (define_predicate "guard_addr_operand" | |
37 | (match_test "true") | |
38 | { | |
39 | return (CONSTANT_ADDRESS_P (op) | |
40 | || !targetm.cannot_force_const_mem (mode, op)); | |
41 | }) | |
42 | ||
43 | ; Predicate for stack protector guard in stack_protect_combined_set and | |
44 | ; stack_protect_combined_test patterns | |
45 | (define_predicate "guard_operand" | |
46 | (match_code "mem") | |
47 | { | |
48 | return guard_addr_operand (XEXP (op, 0), mode); | |
49 | }) | |
50 | ||
1c50eada KT |
51 | (define_predicate "imm_for_neon_inv_logic_operand" |
52 | (match_code "const_vector") | |
53 | { | |
54 | return (TARGET_NEON | |
55 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
56 | }) | |
57 | ||
58 | (define_predicate "neon_inv_logic_op2" | |
59 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
60 | (match_operand 0 "s_register_operand"))) | |
61 | ||
b6af05a9 KT |
62 | (define_predicate "imm_for_neon_logic_operand" |
63 | (match_code "const_vector") | |
64 | { | |
65 | return (TARGET_NEON | |
66 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
67 | }) | |
68 | ||
69 | (define_predicate "neon_logic_op2" | |
70 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
71 | (match_operand 0 "s_register_operand"))) | |
72 | ||
8b0497de | 73 | ;; Any general register. |
03158648 | 74 | (define_predicate "arm_hard_general_register_operand" |
a657c98a RE |
75 | (match_code "reg") |
76 | { | |
03158648 | 77 | return REGNO (op) <= LAST_ARM_REGNUM; |
a657c98a RE |
78 | }) |
79 | ||
5b3e6663 PB |
80 | ;; A low register. |
81 | (define_predicate "low_register_operand" | |
82 | (and (match_code "reg") | |
83 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
84 | ||
85 | ;; A low register or const_int. | |
86 | (define_predicate "low_reg_or_int_operand" | |
87 | (ior (match_code "const_int") | |
88 | (match_operand 0 "low_register_operand"))) | |
89 | ||
a657c98a RE |
90 | ;; Any core register, or any pseudo. */ |
91 | (define_predicate "arm_general_register_operand" | |
92 | (match_code "reg,subreg") | |
93 | { | |
94 | if (GET_CODE (op) == SUBREG) | |
95 | op = SUBREG_REG (op); | |
96 | ||
d435a4be | 97 | return (REG_P (op) |
a657c98a RE |
98 | && (REGNO (op) <= LAST_ARM_REGNUM |
99 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
100 | }) | |
101 | ||
fb117b1c BE |
102 | (define_predicate "arm_general_adddi_operand" |
103 | (ior (match_operand 0 "arm_general_register_operand") | |
104 | (and (match_code "const_int") | |
105 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
106 | ||
4e6f5666 JZ |
107 | (define_predicate "vfp_register_operand" |
108 | (match_code "reg,subreg") | |
109 | { | |
110 | if (GET_CODE (op) == SUBREG) | |
111 | op = SUBREG_REG (op); | |
112 | ||
113 | /* We don't consider registers whose class is NO_REGS | |
114 | to be a register operand. */ | |
d435a4be | 115 | return (REG_P (op) |
4e6f5666 | 116 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
34db4735 | 117 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
118 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
119 | || (TARGET_VFPD32 | |
120 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
121 | }) | |
122 | ||
315d7bd4 CL |
123 | (define_predicate "vfp_hard_register_operand" |
124 | (match_code "reg") | |
125 | { | |
126 | return (IS_VFP_REGNUM (REGNO (op))); | |
127 | }) | |
128 | ||
681676df RE |
129 | (define_predicate "zero_operand" |
130 | (and (match_code "const_int,const_double,const_vector") | |
131 | (match_test "op == CONST0_RTX (mode)"))) | |
132 | ||
133 | ;; Match a register, or zero in the appropriate mode. | |
134 | (define_predicate "reg_or_zero_operand" | |
135 | (ior (match_operand 0 "s_register_operand") | |
136 | (match_operand 0 "zero_operand"))) | |
137 | ||
fa01135d RE |
138 | (define_special_predicate "subreg_lowpart_operator" |
139 | (and (match_code "subreg") | |
140 | (match_test "subreg_lowpart_p (op)"))) | |
141 | ||
a657c98a RE |
142 | ;; Reg, subreg(reg) or const_int. |
143 | (define_predicate "reg_or_int_operand" | |
144 | (ior (match_code "const_int") | |
145 | (match_operand 0 "s_register_operand"))) | |
146 | ||
147 | (define_predicate "arm_immediate_operand" | |
148 | (and (match_code "const_int") | |
149 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
150 | ||
73160ba9 DJ |
151 | ;; A constant value which fits into two instructions, each taking |
152 | ;; an arithmetic constant operand for one of the words. | |
153 | (define_predicate "arm_immediate_di_operand" | |
154 | (and (match_code "const_int,const_double") | |
155 | (match_test "arm_const_double_by_immediates (op)"))) | |
156 | ||
a657c98a RE |
157 | (define_predicate "arm_neg_immediate_operand" |
158 | (and (match_code "const_int") | |
159 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
160 | ||
161 | (define_predicate "arm_not_immediate_operand" | |
162 | (and (match_code "const_int") | |
163 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
164 | ||
f0c6475a | 165 | (define_predicate "const0_operand" |
d1fb6940 | 166 | (match_test "op == CONST0_RTX (mode)")) |
f0c6475a | 167 | |
a657c98a RE |
168 | ;; Something valid on the RHS of an ARM data-processing instruction |
169 | (define_predicate "arm_rhs_operand" | |
170 | (ior (match_operand 0 "s_register_operand") | |
171 | (match_operand 0 "arm_immediate_operand"))) | |
172 | ||
173 | (define_predicate "arm_rhsm_operand" | |
174 | (ior (match_operand 0 "arm_rhs_operand") | |
175 | (match_operand 0 "memory_operand"))) | |
176 | ||
fc02bcca JL |
177 | (define_predicate "const_int_I_operand" |
178 | (and (match_operand 0 "const_int_operand") | |
179 | (match_test "satisfies_constraint_I (op)"))) | |
180 | ||
181 | (define_predicate "const_int_M_operand" | |
182 | (and (match_operand 0 "const_int_operand") | |
183 | (match_test "satisfies_constraint_M (op)"))) | |
184 | ||
55cdadd5 AS |
185 | ;; This doesn't have to do much because the constant is already checked |
186 | ;; in the shift_operator predicate. | |
c29e2982 BS |
187 | (define_predicate "shift_amount_operand" |
188 | (ior (and (match_test "TARGET_ARM") | |
189 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 190 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 191 | |
36ba4aae IR |
192 | (define_predicate "const_neon_scalar_shift_amount_operand" |
193 | (and (match_code "const_int") | |
dec21bbc | 194 | (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) |
36ba4aae | 195 | |
0775830a KT |
196 | (define_predicate "ssat16_imm" |
197 | (and (match_code "const_int") | |
198 | (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) | |
199 | ||
200 | (define_predicate "usat16_imm" | |
201 | (and (match_code "const_int") | |
202 | (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) | |
203 | ||
56289ed2 SD |
204 | (define_predicate "ldrd_strd_offset_operand" |
205 | (and (match_operand 0 "const_int_operand") | |
206 | (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) | |
207 | ||
a657c98a RE |
208 | (define_predicate "arm_add_operand" |
209 | (ior (match_operand 0 "arm_rhs_operand") | |
210 | (match_operand 0 "arm_neg_immediate_operand"))) | |
211 | ||
44cd6810 WG |
212 | (define_predicate "arm_adddi_operand" |
213 | (ior (match_operand 0 "s_register_operand") | |
214 | (and (match_code "const_int") | |
215 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
216 | ||
1ea95660 WD |
217 | (define_predicate "arm_anddi_operand" |
218 | (ior (match_operand 0 "s_register_operand") | |
219 | (and (match_code "const_int") | |
220 | (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")))) | |
221 | ||
222 | (define_predicate "arm_iordi_operand" | |
223 | (ior (match_operand 0 "s_register_operand") | |
224 | (and (match_code "const_int") | |
225 | (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")))) | |
226 | ||
227 | (define_predicate "arm_xordi_operand" | |
228 | (ior (match_operand 0 "s_register_operand") | |
229 | (and (match_code "const_int") | |
230 | (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) | |
231 | ||
a657c98a RE |
232 | (define_predicate "arm_addimm_operand" |
233 | (ior (match_operand 0 "arm_immediate_operand") | |
234 | (match_operand 0 "arm_neg_immediate_operand"))) | |
235 | ||
236 | (define_predicate "arm_not_operand" | |
237 | (ior (match_operand 0 "arm_rhs_operand") | |
238 | (match_operand 0 "arm_not_immediate_operand"))) | |
239 | ||
8b8ab8f4 RE |
240 | ;; A constant that can be used with ADC(SBC) or SBC(ADC) when bit-wise |
241 | ;; inverted. Similar to arm_not_operand, but excludes registers. | |
242 | (define_predicate "arm_adcimm_operand" | |
243 | (ior (match_operand 0 "arm_immediate_operand") | |
244 | (match_operand 0 "arm_not_immediate_operand"))) | |
245 | ||
73160ba9 DJ |
246 | (define_predicate "arm_di_operand" |
247 | (ior (match_operand 0 "s_register_operand") | |
248 | (match_operand 0 "arm_immediate_di_operand"))) | |
249 | ||
a657c98a RE |
250 | ;; True if the operand is a memory reference which contains an |
251 | ;; offsettable address. | |
252 | (define_predicate "offsettable_memory_operand" | |
253 | (and (match_code "mem") | |
254 | (match_test | |
255 | "offsettable_address_p (reload_completed | reload_in_progress, | |
256 | mode, XEXP (op, 0))"))) | |
257 | ||
e6add59b RS |
258 | ;; True if the operand is a memory operand that does not have an |
259 | ;; automodified base register (and thus will not generate output reloads). | |
260 | (define_predicate "call_memory_operand" | |
261 | (and (match_code "mem") | |
262 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
263 | != RTX_AUTOINC") | |
264 | (match_operand 0 "memory_operand")))) | |
265 | ||
a657c98a | 266 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 267 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
268 | (match_test "(!CONSTANT_P (op) |
269 | && (true_regnum(op) == -1 | |
d435a4be | 270 | || (REG_P (op) |
a657c98a RE |
271 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) |
272 | ||
a657c98a RE |
273 | (define_predicate "vfp_compare_operand" |
274 | (ior (match_operand 0 "s_register_operand") | |
275 | (and (match_code "const_double") | |
276 | (match_test "arm_const_double_rtx (op)")))) | |
277 | ||
a657c98a RE |
278 | ;; True for valid index operands. |
279 | (define_predicate "index_operand" | |
280 | (ior (match_operand 0 "s_register_operand") | |
281 | (and (match_operand 0 "immediate_operand") | |
d435a4be | 282 | (match_test "(!CONST_INT_P (op) |
a657c98a RE |
283 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) |
284 | ||
285 | ;; True for operators that can be combined with a shift in ARM state. | |
286 | (define_special_predicate "shiftable_operator" | |
287 | (and (match_code "plus,minus,ior,xor,and") | |
288 | (match_test "mode == GET_MODE (op)"))) | |
289 | ||
95b97fac KT |
290 | (define_special_predicate "shiftable_operator_strict_it" |
291 | (and (match_code "plus,and") | |
292 | (match_test "mode == GET_MODE (op)"))) | |
293 | ||
c112cf2b | 294 | ;; True for logical binary operators. |
a657c98a RE |
295 | (define_special_predicate "logical_binary_operator" |
296 | (and (match_code "ior,xor,and") | |
297 | (match_test "mode == GET_MODE (op)"))) | |
298 | ||
37119410 BS |
299 | ;; True for commutative operators |
300 | (define_special_predicate "commutative_binary_operator" | |
301 | (and (match_code "ior,xor,and,plus") | |
302 | (match_test "mode == GET_MODE (op)"))) | |
303 | ||
a657c98a | 304 | ;; True for shift operators. |
55cdadd5 AS |
305 | ;; Notes: |
306 | ;; * mult is only permitted with a constant shift amount | |
307 | ;; * patterns that permit register shift amounts only in ARM mode use | |
308 | ;; shift_amount_operand, patterns that always allow registers do not, | |
309 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
310 | (define_special_predicate "shift_operator" |
311 | (and (ior (ior (and (match_code "mult") | |
312 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
313 | (and (match_code "rotate") | |
d435a4be | 314 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 315 | && (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
316 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
317 | (match_test "!CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 318 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
319 | (match_test "mode == GET_MODE (op)"))) |
320 | ||
321 | (define_special_predicate "shift_nomul_operator" | |
322 | (and (ior (and (match_code "rotate") | |
323 | (match_test "CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 324 | && (UINTVAL (XEXP (op, 1))) < 32")) |
55cdadd5 | 325 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
d435a4be | 326 | (match_test "!CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 327 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
a657c98a RE |
328 | (match_test "mode == GET_MODE (op)"))) |
329 | ||
655b30bf JB |
330 | ;; True for shift operators which can be used with saturation instructions. |
331 | (define_special_predicate "sat_shift_operator" | |
5d216c70 UW |
332 | (and (ior (and (match_code "mult") |
333 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
334 | (and (match_code "ashift,ashiftrt") | |
d435a4be | 335 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 336 | && (UINTVAL (XEXP (op, 1)) < 32)"))) |
655b30bf JB |
337 | (match_test "mode == GET_MODE (op)"))) |
338 | ||
c29e2982 BS |
339 | ;; True for MULT, to identify which variant of shift_operator is in use. |
340 | (define_special_predicate "mult_operator" | |
341 | (match_code "mult")) | |
342 | ||
5b3e6663 PB |
343 | ;; True for operators that have 16-bit thumb variants. */ |
344 | (define_special_predicate "thumb_16bit_operator" | |
345 | (match_code "plus,minus,and,ior,xor")) | |
346 | ||
a657c98a RE |
347 | ;; True for EQ & NE |
348 | (define_special_predicate "equality_operator" | |
349 | (match_code "eq,ne")) | |
350 | ||
f90b7a5a PB |
351 | ;; True for integer comparisons and, if FP is active, for comparisons |
352 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
353 | (define_special_predicate "expandable_comparison_operator" |
354 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
355 | unordered,ordered,unlt,unle,unge,ungt")) | |
356 | ||
357 | ;; Likewise, but only accept comparisons that are directly supported | |
358 | ;; by ARM condition codes. | |
a657c98a | 359 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 360 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 361 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 362 | |
ac4bf407 KT |
363 | ;; Likewise, but don't ignore the mode. |
364 | ;; RTL SET operations require their operands source and destination have | |
365 | ;; the same modes, so we can't ignore the modes there. See PR target/69161. | |
366 | (define_predicate "arm_comparison_operator_mode" | |
367 | (and (match_operand 0 "expandable_comparison_operator") | |
368 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | |
369 | ||
f0c6475a BS |
370 | (define_special_predicate "lt_ge_comparison_operator" |
371 | (match_code "lt,ge")) | |
372 | ||
1e271bee RE |
373 | (define_special_predicate "arm_carry_operation" |
374 | (match_code "geu,ltu") | |
375 | { | |
376 | if (XEXP (op, 1) != const0_rtx) | |
377 | return false; | |
378 | ||
379 | rtx op0 = XEXP (op, 0); | |
380 | ||
381 | if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | |
382 | return false; | |
383 | ||
384 | machine_mode ccmode = GET_MODE (op0); | |
385 | if (ccmode == CC_Cmode) | |
386 | return GET_CODE (op) == LTU; | |
deb254e0 | 387 | else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) |
1e271bee RE |
388 | return GET_CODE (op) == GEU; |
389 | ||
390 | return false; | |
391 | } | |
392 | ) | |
393 | ||
24990170 RE |
394 | ;; Match a "borrow" operation for use with SBC. The precise code will |
395 | ;; depend on the form of the comparison. This is generally the inverse of | |
396 | ;; a carry operation, since the logic of SBC uses "not borrow" in it's | |
397 | ;; calculation. | |
398 | (define_special_predicate "arm_borrow_operation" | |
399 | (match_code "geu,ltu") | |
400 | { | |
401 | if (XEXP (op, 1) != const0_rtx) | |
402 | return false; | |
403 | rtx op0 = XEXP (op, 0); | |
404 | if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | |
405 | return false; | |
406 | machine_mode ccmode = GET_MODE (op0); | |
407 | if (ccmode == CC_Cmode) | |
408 | return GET_CODE (op) == GEU; | |
b747c183 | 409 | else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) |
24990170 RE |
410 | return GET_CODE (op) == LTU; |
411 | return false; | |
412 | } | |
413 | ) | |
414 | ||
a5a4c20a KT |
415 | ;; The vsel instruction only accepts the ARM condition codes listed below. |
416 | (define_special_predicate "arm_vsel_comparison_operator" | |
417 | (and (match_operand 0 "expandable_comparison_operator") | |
418 | (match_test "maybe_get_arm_condition_code (op) == ARM_GE | |
419 | || maybe_get_arm_condition_code (op) == ARM_GT | |
420 | || maybe_get_arm_condition_code (op) == ARM_EQ | |
421 | || maybe_get_arm_condition_code (op) == ARM_VS | |
422 | || maybe_get_arm_condition_code (op) == ARM_LT | |
423 | || maybe_get_arm_condition_code (op) == ARM_LE | |
424 | || maybe_get_arm_condition_code (op) == ARM_NE | |
425 | || maybe_get_arm_condition_code (op) == ARM_VC"))) | |
426 | ||
1572e697 KT |
427 | (define_special_predicate "arm_cond_move_operator" |
428 | (if_then_else (match_test "arm_restrict_it") | |
c8d61ab8 TP |
429 | (and (match_test "TARGET_VFP5") |
430 | (match_operand 0 "arm_vsel_comparison_operator")) | |
431 | (match_operand 0 "expandable_comparison_operator"))) | |
1572e697 | 432 | |
906668bb BS |
433 | (define_special_predicate "noov_comparison_operator" |
434 | (match_code "lt,ge,eq,ne")) | |
435 | ||
a657c98a RE |
436 | (define_special_predicate "minmax_operator" |
437 | (and (match_code "smin,smax,umin,umax") | |
438 | (match_test "mode == GET_MODE (op)"))) | |
439 | ||
440 | (define_special_predicate "cc_register" | |
441 | (and (match_code "reg") | |
442 | (and (match_test "REGNO (op) == CC_REGNUM") | |
443 | (ior (match_test "mode == GET_MODE (op)") | |
444 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
445 | ||
446 | (define_special_predicate "dominant_cc_register" | |
447 | (match_code "reg") | |
448 | { | |
449 | if (mode == VOIDmode) | |
450 | { | |
451 | mode = GET_MODE (op); | |
452 | ||
453 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
454 | return false; | |
455 | } | |
456 | ||
457 | return (cc_register (op, mode) | |
458 | && (mode == CC_DNEmode | |
459 | || mode == CC_DEQmode | |
460 | || mode == CC_DLEmode | |
461 | || mode == CC_DLTmode | |
462 | || mode == CC_DGEmode | |
463 | || mode == CC_DGTmode | |
464 | || mode == CC_DLEUmode | |
465 | || mode == CC_DLTUmode | |
466 | || mode == CC_DGEUmode | |
467 | || mode == CC_DGTUmode)); | |
468 | }) | |
469 | ||
12286f25 TP |
470 | ;; Any register, including CC |
471 | (define_predicate "cc_register_operand" | |
472 | (and (match_code "reg") | |
473 | (ior (match_operand 0 "s_register_operand") | |
474 | (match_operand 0 "cc_register")))) | |
475 | ||
a657c98a RE |
476 | (define_special_predicate "arm_extendqisi_mem_op" |
477 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
478 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
479 | XEXP (op, 0), | |
480 | SIGN_EXTEND, | |
481 | 0) | |
482 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 483 | |
01577df7 RE |
484 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
485 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
486 | (match_operand 0 "s_register_operand"))) | |
487 | ||
a657c98a RE |
488 | (define_predicate "power_of_two_operand" |
489 | (match_code "const_int") | |
490 | { | |
29b40d79 | 491 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
492 | |
493 | return value != 0 && (value & (value - 1)) == 0; | |
494 | }) | |
495 | ||
496 | (define_predicate "nonimmediate_di_operand" | |
497 | (match_code "reg,subreg,mem") | |
498 | { | |
499 | if (s_register_operand (op, mode)) | |
500 | return true; | |
501 | ||
502 | if (GET_CODE (op) == SUBREG) | |
503 | op = SUBREG_REG (op); | |
504 | ||
d435a4be | 505 | return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); |
a657c98a RE |
506 | }) |
507 | ||
508 | (define_predicate "di_operand" | |
509 | (ior (match_code "const_int,const_double") | |
510 | (and (match_code "reg,subreg,mem") | |
511 | (match_operand 0 "nonimmediate_di_operand")))) | |
512 | ||
513 | (define_predicate "nonimmediate_soft_df_operand" | |
514 | (match_code "reg,subreg,mem") | |
515 | { | |
516 | if (s_register_operand (op, mode)) | |
517 | return true; | |
518 | ||
519 | if (GET_CODE (op) == SUBREG) | |
520 | op = SUBREG_REG (op); | |
521 | ||
d435a4be | 522 | return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); |
a657c98a RE |
523 | }) |
524 | ||
525 | (define_predicate "soft_df_operand" | |
526 | (ior (match_code "const_double") | |
527 | (and (match_code "reg,subreg,mem") | |
528 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
529 | ||
8d33eae8 TP |
530 | ;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this |
531 | ;; forbids constant loaded via literal pool iff literal pools are disabled. | |
532 | (define_predicate "hard_sf_operand" | |
533 | (and (match_operand 0 "general_operand") | |
534 | (ior (not (match_code "const_double")) | |
535 | (not (match_test "arm_disable_literal_pool")) | |
536 | (match_test "satisfies_constraint_Dv (op)")))) | |
537 | ||
538 | ;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in | |
539 | ;; movdf_soft_insn, this forbids constant loaded via literal pool iff | |
540 | ;; literal pools are disabled. | |
541 | (define_predicate "hard_df_operand" | |
542 | (and (match_operand 0 "soft_df_operand") | |
543 | (ior (not (match_code "const_double")) | |
544 | (not (match_test "arm_disable_literal_pool")) | |
545 | (match_test "satisfies_constraint_Dy (op)") | |
546 | (match_test "satisfies_constraint_G (op)")))) | |
547 | ||
a657c98a RE |
548 | (define_special_predicate "load_multiple_operation" |
549 | (match_code "parallel") | |
550 | { | |
fb40241d IB |
551 | return ldm_stm_operation_p (op, /*load=*/true, SImode, |
552 | /*consecutive=*/false, | |
553 | /*return_pc=*/false); | |
a657c98a RE |
554 | }) |
555 | ||
556 | (define_special_predicate "store_multiple_operation" | |
557 | (match_code "parallel") | |
558 | { | |
fb40241d IB |
559 | return ldm_stm_operation_p (op, /*load=*/false, SImode, |
560 | /*consecutive=*/false, | |
561 | /*return_pc=*/false); | |
a657c98a RE |
562 | }) |
563 | ||
3aee1982 IB |
564 | (define_special_predicate "pop_multiple_return" |
565 | (match_code "parallel") | |
566 | { | |
567 | return ldm_stm_operation_p (op, /*load=*/true, SImode, | |
568 | /*consecutive=*/false, | |
569 | /*return_pc=*/true); | |
570 | }) | |
571 | ||
4b2678f8 IB |
572 | (define_special_predicate "pop_multiple_fp" |
573 | (match_code "parallel") | |
574 | { | |
575 | return ldm_stm_operation_p (op, /*load=*/true, DFmode, | |
576 | /*consecutive=*/true, | |
577 | /*return_pc=*/false); | |
578 | }) | |
579 | ||
a657c98a RE |
580 | (define_special_predicate "multi_register_push" |
581 | (match_code "parallel") | |
582 | { | |
583 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
584 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
585 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
586 | return false; | |
587 | ||
588 | return true; | |
589 | }) | |
590 | ||
d018b46e RH |
591 | (define_predicate "push_mult_memory_operand" |
592 | (match_code "mem") | |
593 | { | |
594 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
595 | any point in testing for thumb1 specially? All of the variants | |
596 | use the same form. */ | |
597 | if (TARGET_THUMB1) | |
598 | { | |
599 | /* ??? No attempt is made to represent STMIA, or validate that | |
600 | the stack adjustment matches the register count. This is | |
601 | true of the ARM/Thumb2 path as well. */ | |
602 | rtx x = XEXP (op, 0); | |
603 | if (GET_CODE (x) != PRE_MODIFY) | |
604 | return false; | |
605 | if (XEXP (x, 0) != stack_pointer_rtx) | |
606 | return false; | |
607 | x = XEXP (x, 1); | |
608 | if (GET_CODE (x) != PLUS) | |
609 | return false; | |
610 | if (XEXP (x, 0) != stack_pointer_rtx) | |
611 | return false; | |
612 | return CONST_INT_P (XEXP (x, 1)); | |
613 | } | |
614 | ||
615 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
616 | return memory_operand (op, mode); | |
617 | }) | |
618 | ||
a657c98a RE |
619 | ;;------------------------------------------------------------------------- |
620 | ;; | |
621 | ;; Thumb predicates | |
622 | ;; | |
623 | ||
5b3e6663 | 624 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
625 | (ior (and (match_code "reg,subreg") |
626 | (match_operand 0 "s_register_operand")) | |
627 | (and (match_code "const_int") | |
dec21bbc | 628 | (match_test "(UINTVAL (op)) < 256")))) |
a657c98a | 629 | |
5b3e6663 | 630 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
631 | (and (match_code "const_int") |
632 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
633 | ||
634 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
635 | ;; condition code register. Prior to reload we only accept a | |
636 | ;; register. After reload we have to be able to handle memory as | |
637 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
638 | ;; handle output-reloads on jump insns. | |
639 | ||
640 | ;; We could possibly handle mem before reload as well, but that might | |
641 | ;; complicate things with the need to handle increment | |
642 | ;; side-effects. | |
643 | (define_predicate "thumb_cbrch_target_operand" | |
644 | (and (match_code "reg,subreg,mem") | |
645 | (ior (match_operand 0 "s_register_operand") | |
646 | (and (match_test "reload_in_progress || reload_completed") | |
647 | (match_operand 0 "memory_operand"))))) | |
648 | ||
649 | ;;------------------------------------------------------------------------- | |
650 | ;; | |
8fd03515 | 651 | ;; iWMMXt predicates |
dae840fc | 652 | ;; |
8fd03515 XQ |
653 | |
654 | (define_predicate "imm_or_reg_operand" | |
655 | (ior (match_operand 0 "immediate_operand") | |
656 | (match_operand 0 "register_operand"))) | |
a657c98a | 657 | |
88f77cba JB |
658 | ;; Neon predicates |
659 | ||
660 | (define_predicate "const_multiple_of_8_operand" | |
661 | (match_code "const_int") | |
662 | { | |
663 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
664 | return (val & 7) == 0; | |
665 | }) | |
666 | ||
667 | (define_predicate "imm_for_neon_mov_operand" | |
00a3a76a | 668 | (match_code "const_vector,const_int") |
88f77cba JB |
669 | { |
670 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
671 | }) | |
672 | ||
31a0c825 DP |
673 | (define_predicate "imm_for_neon_lshift_operand" |
674 | (match_code "const_vector") | |
675 | { | |
676 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
677 | }) | |
678 | ||
679 | (define_predicate "imm_for_neon_rshift_operand" | |
680 | (match_code "const_vector") | |
681 | { | |
682 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
683 | }) | |
684 | ||
685 | (define_predicate "imm_lshift_or_reg_neon" | |
686 | (ior (match_operand 0 "s_register_operand") | |
687 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
688 | ||
689 | (define_predicate "imm_rshift_or_reg_neon" | |
690 | (ior (match_operand 0 "s_register_operand") | |
691 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
692 | ||
73160ba9 DJ |
693 | ;; Predicates for named expanders that overlap multiple ISAs. |
694 | ||
695 | (define_predicate "cmpdi_operand" | |
dae840fc RE |
696 | (and (match_test "TARGET_32BIT") |
697 | (match_operand 0 "arm_di_operand"))) | |
88f77cba | 698 | |
999a9cc5 MS |
699 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
700 | (define_predicate "arm_sync_memory_operand" | |
701 | (and (match_operand 0 "memory_operand") | |
702 | (match_code "reg" "0"))) | |
703 | ||
46b57af1 TB |
704 | ;; Predicates for parallel expanders based on mode. |
705 | (define_special_predicate "vect_par_constant_high" | |
706 | (match_code "parallel") | |
707 | { | |
93c590ee | 708 | return arm_simd_check_vect_par_cnst_half_p (op, mode, true); |
46b57af1 TB |
709 | }) |
710 | ||
711 | (define_special_predicate "vect_par_constant_low" | |
712 | (match_code "parallel") | |
713 | { | |
93c590ee | 714 | return arm_simd_check_vect_par_cnst_half_p (op, mode, false); |
46b57af1 | 715 | }) |
6308e208 | 716 | |
7f3d8f56 RR |
717 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
718 | (and (match_code "const_double") | |
00ea1506 RE |
719 | (match_test "TARGET_32BIT |
720 | && vfp3_const_double_for_fract_bits (op)"))) | |
c75d51aa RL |
721 | |
722 | (define_predicate "const_double_vcvt_power_of_two" | |
723 | (and (match_code "const_double") | |
00ea1506 | 724 | (match_test "TARGET_32BIT |
85f5231d | 725 | && vfp3_const_double_for_bits (op) > 0"))) |
7f3d8f56 | 726 | |
12c4ecb1 | 727 | (define_predicate "neon_struct_operand" |
6308e208 | 728 | (and (match_code "mem") |
33255ae3 | 729 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) |
9a1ea4b9 | 730 | |
33255ae3 JB |
731 | (define_predicate "neon_permissive_struct_operand" |
732 | (and (match_code "mem") | |
733 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) | |
734 | ||
735 | (define_predicate "neon_perm_struct_or_reg_operand" | |
736 | (ior (match_operand 0 "neon_permissive_struct_operand") | |
12c4ecb1 RS |
737 | (match_operand 0 "s_register_operand"))) |
738 | ||
9a1ea4b9 RR |
739 | (define_special_predicate "add_operator" |
740 | (match_code "plus")) | |
18f0fe6b RH |
741 | |
742 | (define_predicate "mem_noofs_operand" | |
743 | (and (match_code "mem") | |
744 | (match_code "reg" "0"))) | |
9adcfa3c RR |
745 | |
746 | (define_predicate "call_insn_operand" | |
10432733 JW |
747 | (ior (and (match_code "symbol_ref") |
748 | (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) | |
9adcfa3c | 749 | (match_operand 0 "s_register_operand"))) |
70cdb21e BE |
750 | |
751 | (define_special_predicate "aligned_operand" | |
752 | (ior (not (match_code "mem")) | |
753 | (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))) |