[thirdparty/gcc.git] / gcc / config / arm / predicates.md

;; Predicate definitions for ARM and Thumb
;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
;; Boston, MA 02110-1301, USA.

(define_predicate "s_register_operand"
  (match_code "reg,subreg")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);
  /* We don't consider registers whose class is NO_REGS
     to be a register operand.  */
  /* XXX might have to check for lo regs only for thumb ??? */
  return (GET_CODE (op) == REG
	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER
	      || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
})

;; Any hard register.
(define_predicate "arm_hard_register_operand"
  (match_code "reg")
{
  return REGNO (op) < FIRST_PSEUDO_REGISTER;
})

;; A low register.
(define_predicate "low_register_operand"
  (and (match_code "reg")
       (match_test "REGNO (op) <= LAST_LO_REGNUM")))

;; A low register or const_int.
(define_predicate "low_reg_or_int_operand"
  (ior (match_code "const_int")
       (match_operand 0 "low_register_operand")))

;; Any core register, or any pseudo.  */ 
(define_predicate "arm_general_register_operand"
  (match_code "reg,subreg")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);

  return (GET_CODE (op) == REG
	  && (REGNO (op) <= LAST_ARM_REGNUM
	      || REGNO (op) >= FIRST_PSEUDO_REGISTER));
})

(define_predicate "f_register_operand"
  (match_code "reg,subreg")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);

  /* We don't consider registers whose class is NO_REGS
     to be a register operand.  */
  return (GET_CODE (op) == REG
	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER
	      || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
})

;; Reg, subreg(reg) or const_int.
(define_predicate "reg_or_int_operand"
  (ior (match_code "const_int")
       (match_operand 0 "s_register_operand")))

(define_predicate "arm_immediate_operand"
  (and (match_code "const_int")
       (match_test "const_ok_for_arm (INTVAL (op))")))

(define_predicate "arm_neg_immediate_operand"
  (and (match_code "const_int")
       (match_test "const_ok_for_arm (-INTVAL (op))")))

(define_predicate "arm_not_immediate_operand"
  (and (match_code "const_int")
       (match_test "const_ok_for_arm (~INTVAL (op))")))

;; Something valid on the RHS of an ARM data-processing instruction
(define_predicate "arm_rhs_operand"
  (ior (match_operand 0 "s_register_operand")
       (match_operand 0 "arm_immediate_operand")))

(define_predicate "arm_rhsm_operand"
  (ior (match_operand 0 "arm_rhs_operand")
       (match_operand 0 "memory_operand")))

(define_predicate "arm_add_operand"
  (ior (match_operand 0 "arm_rhs_operand")
       (match_operand 0 "arm_neg_immediate_operand")))

(define_predicate "arm_addimm_operand"
  (ior (match_operand 0 "arm_immediate_operand")
       (match_operand 0 "arm_neg_immediate_operand")))

(define_predicate "arm_not_operand"
  (ior (match_operand 0 "arm_rhs_operand")
       (match_operand 0 "arm_not_immediate_operand")))

;; True if the operand is a memory reference which contains an
;; offsettable address.
(define_predicate "offsettable_memory_operand"
  (and (match_code "mem")
       (match_test
        "offsettable_address_p (reload_completed | reload_in_progress,
				mode, XEXP (op, 0))")))

;; True if the operand is a memory operand that does not have an
;; automodified base register (and thus will not generate output reloads).
(define_predicate "call_memory_operand"
  (and (match_code "mem")
       (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
			 != RTX_AUTOINC")
	    (match_operand 0 "memory_operand"))))

(define_predicate "arm_reload_memory_operand"
  (and (match_code "mem,reg,subreg")
       (match_test "(!CONSTANT_P (op)
		     && (true_regnum(op) == -1
			 || (GET_CODE (op) == REG
			     && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))

;; True for valid operands for the rhs of an floating point insns.
;;   Allows regs or certain consts on FPA, just regs for everything else.
(define_predicate "arm_float_rhs_operand"
  (ior (match_operand 0 "s_register_operand")
       (and (match_code "const_double")
	    (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))

(define_predicate "arm_float_add_operand"
  (ior (match_operand 0 "arm_float_rhs_operand")
       (and (match_code "const_double")
	    (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))

(define_predicate "vfp_compare_operand"
  (ior (match_operand 0 "s_register_operand")
       (and (match_code "const_double")
	    (match_test "arm_const_double_rtx (op)"))))

(define_predicate "arm_float_compare_operand"
  (if_then_else (match_test "TARGET_VFP")
		(match_operand 0 "vfp_compare_operand")
		(match_operand 0 "arm_float_rhs_operand")))

;; True for valid index operands.
(define_predicate "index_operand"
  (ior (match_operand 0 "s_register_operand")
       (and (match_operand 0 "immediate_operand")
	    (match_test "(GET_CODE (op) != CONST_INT
			  || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))

;; True for operators that can be combined with a shift in ARM state.
(define_special_predicate "shiftable_operator"
  (and (match_code "plus,minus,ior,xor,and")
       (match_test "mode == GET_MODE (op)")))

;; True for logical binary operators.
(define_special_predicate "logical_binary_operator"
  (and (match_code "ior,xor,and")
       (match_test "mode == GET_MODE (op)")))

;; True for shift operators.
(define_special_predicate "shift_operator"
  (and (ior (ior (and (match_code "mult")
		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
		 (and (match_code "rotate")
		      (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
	    (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
       (match_test "mode == GET_MODE (op)")))

;; True for operators that have 16-bit thumb variants.  */
(define_special_predicate "thumb_16bit_operator"
  (match_code "plus,minus,and,ior,xor"))

;; True for EQ & NE
(define_special_predicate "equality_operator"
  (match_code "eq,ne"))

;; True for comparisons other than LTGT or UNEQ.
(define_special_predicate "arm_comparison_operator"
  (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))

(define_special_predicate "minmax_operator"
  (and (match_code "smin,smax,umin,umax")
       (match_test "mode == GET_MODE (op)")))

(define_special_predicate "cc_register"
  (and (match_code "reg")
       (and (match_test "REGNO (op) == CC_REGNUM")
	    (ior (match_test "mode == GET_MODE (op)")
		 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))

(define_special_predicate "dominant_cc_register"
  (match_code "reg")
{
  if (mode == VOIDmode)
    {
      mode = GET_MODE (op);
      
      if (GET_MODE_CLASS (mode) != MODE_CC)
	return false;
    }

  return (cc_register (op, mode)
	  && (mode == CC_DNEmode
	     || mode == CC_DEQmode
	     || mode == CC_DLEmode
	     || mode == CC_DLTmode
	     || mode == CC_DGEmode
	     || mode == CC_DGTmode
	     || mode == CC_DLEUmode
	     || mode == CC_DLTUmode
	     || mode == CC_DGEUmode
	     || mode == CC_DGTUmode));
})

(define_special_predicate "arm_extendqisi_mem_op"
  (and (match_operand 0 "memory_operand")
       (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
					      0)")))

(define_predicate "power_of_two_operand"
  (match_code "const_int")
{
  HOST_WIDE_INT value = INTVAL (op);

  return value != 0 && (value & (value - 1)) == 0;
})

(define_predicate "nonimmediate_di_operand"
  (match_code "reg,subreg,mem")
{
   if (s_register_operand (op, mode))
     return true;

   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);

   return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
})

(define_predicate "di_operand"
  (ior (match_code "const_int,const_double")
       (and (match_code "reg,subreg,mem")
	    (match_operand 0 "nonimmediate_di_operand"))))

(define_predicate "nonimmediate_soft_df_operand"
  (match_code "reg,subreg,mem")
{
  if (s_register_operand (op, mode))
    return true;

  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);

  return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
})

(define_predicate "soft_df_operand"
  (ior (match_code "const_double")
       (and (match_code "reg,subreg,mem")
	    (match_operand 0 "nonimmediate_soft_df_operand"))))

(define_predicate "const_shift_operand"
  (and (match_code "const_int")
       (ior (match_operand 0 "power_of_two_operand")
	    (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))


(define_special_predicate "load_multiple_operation"
  (match_code "parallel")
{
  HOST_WIDE_INT count = XVECLEN (op, 0);
  int dest_regno;
  rtx src_addr;
  HOST_WIDE_INT i = 1, base = 0;
  rtx elt;

  if (count <= 1
      || GET_CODE (XVECEXP (op, 0, 0)) != SET)
    return false;

  /* Check to see if this might be a write-back.  */
  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
    {
      i++;
      base = 1;

      /* Now check it more carefully.  */
      if (GET_CODE (SET_DEST (elt)) != REG
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
        return false;
    }

  /* Perform a quick check so we don't blow up below.  */
  if (count <= i
      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
    return false;

  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);

  for (; i < count; i++)
    {
      elt = XVECEXP (op, 0, i);

      if (GET_CODE (elt) != SET
          || GET_CODE (SET_DEST (elt)) != REG
          || GET_MODE (SET_DEST (elt)) != SImode
          || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
          || GET_CODE (SET_SRC (elt)) != MEM
          || GET_MODE (SET_SRC (elt)) != SImode
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
          || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
        return false;
    }

  return true;
})

(define_special_predicate "store_multiple_operation"
  (match_code "parallel")
{
  HOST_WIDE_INT count = XVECLEN (op, 0);
  int src_regno;
  rtx dest_addr;
  HOST_WIDE_INT i = 1, base = 0;
  rtx elt;

  if (count <= 1
      || GET_CODE (XVECEXP (op, 0, 0)) != SET)
    return false;

  /* Check to see if this might be a write-back.  */
  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
    {
      i++;
      base = 1;

      /* Now check it more carefully.  */
      if (GET_CODE (SET_DEST (elt)) != REG
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
        return false;
    }

  /* Perform a quick check so we don't blow up below.  */
  if (count <= i
      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
    return false;

  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);

  for (; i < count; i++)
    {
      elt = XVECEXP (op, 0, i);

      if (GET_CODE (elt) != SET
          || GET_CODE (SET_SRC (elt)) != REG
          || GET_MODE (SET_SRC (elt)) != SImode
          || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
          || GET_CODE (SET_DEST (elt)) != MEM
          || GET_MODE (SET_DEST (elt)) != SImode
          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
          || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
        return false;
    }

  return true;
})

(define_special_predicate "multi_register_push"
  (match_code "parallel")
{
  if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
      || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
      || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
    return false;

  return true;
})

;;-------------------------------------------------------------------------
;;
;; Thumb predicates
;;

(define_predicate "thumb1_cmp_operand"
  (ior (and (match_code "reg,subreg")
	    (match_operand 0 "s_register_operand"))
       (and (match_code "const_int")
	    (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))

(define_predicate "thumb1_cmpneg_operand"
  (and (match_code "const_int")
       (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))

;; Return TRUE if a result can be stored in OP without clobbering the
;; condition code register.  Prior to reload we only accept a
;; register.  After reload we have to be able to handle memory as
;; well, since a pseudo may not get a hard reg and reload cannot
;; handle output-reloads on jump insns.

;; We could possibly handle mem before reload as well, but that might
;; complicate things with the need to handle increment
;; side-effects.
(define_predicate "thumb_cbrch_target_operand"
  (and (match_code "reg,subreg,mem")
       (ior (match_operand 0 "s_register_operand")
	    (and (match_test "reload_in_progress || reload_completed")
		 (match_operand 0 "memory_operand")))))

;;-------------------------------------------------------------------------
;;
;; MAVERICK predicates
;;

(define_predicate "cirrus_register_operand"
  (match_code "reg,subreg")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);

  return (GET_CODE (op) == REG
	  && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
	      || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
})

(define_predicate "cirrus_fp_register"
  (match_code "reg,subreg")
{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);

  return (GET_CODE (op) == REG
	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER
	      || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
})

(define_predicate "cirrus_shift_const"
  (and (match_code "const_int")
       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
Commit	Line	Data
a657c98a	1	;; Predicate definitions for ARM and Thumb
5b3e6663	2	;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
a657c98a RE	3	;; Contributed by ARM Ltd.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
	9	;; by the Free Software Foundation; either version 2, or (at your
	10	;; option) any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING. If not, write to
39d14dda KC	19	;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
39d14dda KC	20	;; Boston, MA 02110-1301, USA.
a657c98a RE	21
	22	(define_predicate "s_register_operand"
	23	(match_code "reg,subreg")
	24	{
	25	if (GET_CODE (op) == SUBREG)
	26	op = SUBREG_REG (op);
	27	/* We don't consider registers whose class is NO_REGS
	28	to be a register operand. */
	29	/* XXX might have to check for lo regs only for thumb ??? */
	30	return (GET_CODE (op) == REG
	31	&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
	32	\|\| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
	33	})
	34
	35	;; Any hard register.
	36	(define_predicate "arm_hard_register_operand"
	37	(match_code "reg")
	38	{
	39	return REGNO (op) < FIRST_PSEUDO_REGISTER;
	40	})
	41
5b3e6663 PB	42	;; A low register.
	43	(define_predicate "low_register_operand"
	44	(and (match_code "reg")
	45	(match_test "REGNO (op) <= LAST_LO_REGNUM")))
	46
	47	;; A low register or const_int.
	48	(define_predicate "low_reg_or_int_operand"
	49	(ior (match_code "const_int")
	50	(match_operand 0 "low_register_operand")))
	51
a657c98a RE	52	;; Any core register, or any pseudo. */
	53	(define_predicate "arm_general_register_operand"
	54	(match_code "reg,subreg")
	55	{
	56	if (GET_CODE (op) == SUBREG)
	57	op = SUBREG_REG (op);
	58
	59	return (GET_CODE (op) == REG
	60	&& (REGNO (op) <= LAST_ARM_REGNUM
	61	\|\| REGNO (op) >= FIRST_PSEUDO_REGISTER));
	62	})
	63
	64	(define_predicate "f_register_operand"
	65	(match_code "reg,subreg")
	66	{
	67	if (GET_CODE (op) == SUBREG)
	68	op = SUBREG_REG (op);
	69
	70	/* We don't consider registers whose class is NO_REGS
	71	to be a register operand. */
	72	return (GET_CODE (op) == REG
	73	&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
	74	\|\| REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
	75	})
	76
	77	;; Reg, subreg(reg) or const_int.
	78	(define_predicate "reg_or_int_operand"
	79	(ior (match_code "const_int")
	80	(match_operand 0 "s_register_operand")))
	81
	82	(define_predicate "arm_immediate_operand"
	83	(and (match_code "const_int")
	84	(match_test "const_ok_for_arm (INTVAL (op))")))
	85
	86	(define_predicate "arm_neg_immediate_operand"
	87	(and (match_code "const_int")
	88	(match_test "const_ok_for_arm (-INTVAL (op))")))
	89
	90	(define_predicate "arm_not_immediate_operand"
	91	(and (match_code "const_int")
	92	(match_test "const_ok_for_arm (~INTVAL (op))")))
	93
	94	;; Something valid on the RHS of an ARM data-processing instruction
	95	(define_predicate "arm_rhs_operand"
	96	(ior (match_operand 0 "s_register_operand")
	97	(match_operand 0 "arm_immediate_operand")))
	98
	99	(define_predicate "arm_rhsm_operand"
	100	(ior (match_operand 0 "arm_rhs_operand")
	101	(match_operand 0 "memory_operand")))
	102
	103	(define_predicate "arm_add_operand"
	104	(ior (match_operand 0 "arm_rhs_operand")
	105	(match_operand 0 "arm_neg_immediate_operand")))
	106
	107	(define_predicate "arm_addimm_operand"
	108	(ior (match_operand 0 "arm_immediate_operand")
	109	(match_operand 0 "arm_neg_immediate_operand")))
	110
	111	(define_predicate "arm_not_operand"
	112	(ior (match_operand 0 "arm_rhs_operand")
	113	(match_operand 0 "arm_not_immediate_operand")))
	114
	115	;; True if the operand is a memory reference which contains an
116	;; offsettable address.
117	(define_predicate "offsettable_memory_operand"
118	(and (match_code "mem")
119	(match_test
120	"offsettable_address_p (reload_completed \| reload_in_progress,
121	mode, XEXP (op, 0))")))
122
e6add59b RS	123	;; True if the operand is a memory operand that does not have an
	124	;; automodified base register (and thus will not generate output reloads).
	125	(define_predicate "call_memory_operand"
	126	(and (match_code "mem")
	127	(and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
	128	!= RTX_AUTOINC")
	129	(match_operand 0 "memory_operand"))))
	130
a657c98a	131	(define_predicate "arm_reload_memory_operand"
9d2da95b	132	(and (match_code "mem,reg,subreg")
a657c98a RE	133	(match_test "(!CONSTANT_P (op)
	134	&& (true_regnum(op) == -1
	135	\|\| (GET_CODE (op) == REG
	136	&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
	137
	138	;; True for valid operands for the rhs of an floating point insns.
	139	;; Allows regs or certain consts on FPA, just regs for everything else.
	140	(define_predicate "arm_float_rhs_operand"
	141	(ior (match_operand 0 "s_register_operand")
	142	(and (match_code "const_double")
	143	(match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
	144
	145	(define_predicate "arm_float_add_operand"
	146	(ior (match_operand 0 "arm_float_rhs_operand")
	147	(and (match_code "const_double")
	148	(match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
	149
	150	(define_predicate "vfp_compare_operand"
	151	(ior (match_operand 0 "s_register_operand")
	152	(and (match_code "const_double")
	153	(match_test "arm_const_double_rtx (op)"))))
	154
	155	(define_predicate "arm_float_compare_operand"
	156	(if_then_else (match_test "TARGET_VFP")
	157	(match_operand 0 "vfp_compare_operand")
	158	(match_operand 0 "arm_float_rhs_operand")))
	159
	160	;; True for valid index operands.
	161	(define_predicate "index_operand"
	162	(ior (match_operand 0 "s_register_operand")
	163	(and (match_operand 0 "immediate_operand")
	164	(match_test "(GET_CODE (op) != CONST_INT
	165	\|\| (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
	166
	167	;; True for operators that can be combined with a shift in ARM state.
	168	(define_special_predicate "shiftable_operator"
	169	(and (match_code "plus,minus,ior,xor,and")
	170	(match_test "mode == GET_MODE (op)")))
	171
c112cf2b	172	;; True for logical binary operators.
a657c98a RE	173	(define_special_predicate "logical_binary_operator"
	174	(and (match_code "ior,xor,and")
	175	(match_test "mode == GET_MODE (op)")))
	176
	177	;; True for shift operators.
	178	(define_special_predicate "shift_operator"
	179	(and (ior (ior (and (match_code "mult")
	180	(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
	181	(and (match_code "rotate")
	182	(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
	183	&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
	184	(match_code "ashift,ashiftrt,lshiftrt,rotatert"))
	185	(match_test "mode == GET_MODE (op)")))
	186
5b3e6663 PB	187	;; True for operators that have 16-bit thumb variants. */
	188	(define_special_predicate "thumb_16bit_operator"
	189	(match_code "plus,minus,and,ior,xor"))
	190
a657c98a RE	191	;; True for EQ & NE
	192	(define_special_predicate "equality_operator"
	193	(match_code "eq,ne"))
	194
	195	;; True for comparisons other than LTGT or UNEQ.
	196	(define_special_predicate "arm_comparison_operator"
	197	(match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
	198
	199	(define_special_predicate "minmax_operator"
	200	(and (match_code "smin,smax,umin,umax")
	201	(match_test "mode == GET_MODE (op)")))
	202
	203	(define_special_predicate "cc_register"
	204	(and (match_code "reg")
	205	(and (match_test "REGNO (op) == CC_REGNUM")
	206	(ior (match_test "mode == GET_MODE (op)")
	207	(match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
	208
	209	(define_special_predicate "dominant_cc_register"
	210	(match_code "reg")
	211	{
	212	if (mode == VOIDmode)
	213	{
	214	mode = GET_MODE (op);
	215
	216	if (GET_MODE_CLASS (mode) != MODE_CC)
	217	return false;
	218	}
	219
	220	return (cc_register (op, mode)
	221	&& (mode == CC_DNEmode
	222	\|\| mode == CC_DEQmode
	223	\|\| mode == CC_DLEmode
	224	\|\| mode == CC_DLTmode
	225	\|\| mode == CC_DGEmode
	226	\|\| mode == CC_DGTmode
	227	\|\| mode == CC_DLEUmode
	228	\|\| mode == CC_DLTUmode
	229	\|\| mode == CC_DGEUmode
	230	\|\| mode == CC_DGTUmode));
	231	})
	232
	233	(define_special_predicate "arm_extendqisi_mem_op"
	234	(and (match_operand 0 "memory_operand")
	235	(match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
	236	0)")))
	237
	238	(define_predicate "power_of_two_operand"
	239	(match_code "const_int")
	240	{
	241	HOST_WIDE_INT value = INTVAL (op);
	242
	243	return value != 0 && (value & (value - 1)) == 0;
	244	})
	245
	246	(define_predicate "nonimmediate_di_operand"
	247	(match_code "reg,subreg,mem")
	248	{
	249	if (s_register_operand (op, mode))
	250	return true;
	251
	252	if (GET_CODE (op) == SUBREG)
	253	op = SUBREG_REG (op);
	254
255	return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
256	})
257
258	(define_predicate "di_operand"
259	(ior (match_code "const_int,const_double")
260	(and (match_code "reg,subreg,mem")
261	(match_operand 0 "nonimmediate_di_operand"))))
262
263	(define_predicate "nonimmediate_soft_df_operand"
264	(match_code "reg,subreg,mem")
265	{
266	if (s_register_operand (op, mode))
267	return true;
268
269	if (GET_CODE (op) == SUBREG)
270	op = SUBREG_REG (op);
271
272	return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
273	})
274
275	(define_predicate "soft_df_operand"
276	(ior (match_code "const_double")
277	(and (match_code "reg,subreg,mem")
278	(match_operand 0 "nonimmediate_soft_df_operand"))))
279
280	(define_predicate "const_shift_operand"
281	(and (match_code "const_int")
282	(ior (match_operand 0 "power_of_two_operand")
283	(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
284
285
286	(define_special_predicate "load_multiple_operation"
287	(match_code "parallel")
288	{
289	HOST_WIDE_INT count = XVECLEN (op, 0);
290	int dest_regno;
291	rtx src_addr;
292	HOST_WIDE_INT i = 1, base = 0;
293	rtx elt;
294
295	if (count <= 1
296	\|\| GET_CODE (XVECEXP (op, 0, 0)) != SET)
297	return false;
298
299	/* Check to see if this might be a write-back. */
300	if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
301	{
302	i++;
303	base = 1;
304
305	/* Now check it more carefully. */
306	if (GET_CODE (SET_DEST (elt)) != REG
307	\|\| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
308	\|\| GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
309	\|\| INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
310	return false;
311	}
312
313	/* Perform a quick check so we don't blow up below. */
314	if (count <= i
315	\|\| GET_CODE (XVECEXP (op, 0, i - 1)) != SET
316	\|\| GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
317	\|\| GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
318	return false;
319
320	dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
321	src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
322
323	for (; i < count; i++)
324	{
325	elt = XVECEXP (op, 0, i);
326
327	if (GET_CODE (elt) != SET
328	\|\| GET_CODE (SET_DEST (elt)) != REG
329	\|\| GET_MODE (SET_DEST (elt)) != SImode
330	\|\| REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
331	\|\| GET_CODE (SET_SRC (elt)) != MEM
332	\|\| GET_MODE (SET_SRC (elt)) != SImode
333	\|\| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
334	\|\| !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
335	\|\| GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
336	\|\| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
337	return false;
338	}
339
340	return true;
341	})
342
343	(define_special_predicate "store_multiple_operation"
344	(match_code "parallel")
345	{
346	HOST_WIDE_INT count = XVECLEN (op, 0);
347	int src_regno;
348	rtx dest_addr;
349	HOST_WIDE_INT i = 1, base = 0;
350	rtx elt;
351
352	if (count <= 1
353	\|\| GET_CODE (XVECEXP (op, 0, 0)) != SET)
354	return false;
355
356	/* Check to see if this might be a write-back. */
357	if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
358	{
359	i++;
360	base = 1;
361
362	/* Now check it more carefully. */
363	if (GET_CODE (SET_DEST (elt)) != REG
364	\|\| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
365	\|\| GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
366	\|\| INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
367	return false;
368	}
369
370	/* Perform a quick check so we don't blow up below. */
371	if (count <= i
372	\|\| GET_CODE (XVECEXP (op, 0, i - 1)) != SET
373	\|\| GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
374	\|\| GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
375	return false;
376
377	src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
378	dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
379
380	for (; i < count; i++)
381	{
382	elt = XVECEXP (op, 0, i);
383
384	if (GET_CODE (elt) != SET
385	\|\| GET_CODE (SET_SRC (elt)) != REG
386	\|\| GET_MODE (SET_SRC (elt)) != SImode
387	\|\| REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
388	\|\| GET_CODE (SET_DEST (elt)) != MEM
389	\|\| GET_MODE (SET_DEST (elt)) != SImode
390	\|\| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
391	\|\| !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
392	\|\| GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
393	\|\| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
394	return false;
395	}
396
397	return true;
398	})
399
400	(define_special_predicate "multi_register_push"
401	(match_code "parallel")
402	{
403	if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
404	\|\| (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
405	\|\| (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
406	return false;
407
408	return true;
409	})
410
411	;;-------------------------------------------------------------------------
412	;;
413	;; Thumb predicates
414	;;
415
5b3e6663	416	(define_predicate "thumb1_cmp_operand"
a657c98a RE	417	(ior (and (match_code "reg,subreg")
	418	(match_operand 0 "s_register_operand"))
	419	(and (match_code "const_int")
	420	(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
	421
5b3e6663	422	(define_predicate "thumb1_cmpneg_operand"
a657c98a RE	423	(and (match_code "const_int")
	424	(match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
	425
	426	;; Return TRUE if a result can be stored in OP without clobbering the
	427	;; condition code register. Prior to reload we only accept a
	428	;; register. After reload we have to be able to handle memory as
	429	;; well, since a pseudo may not get a hard reg and reload cannot
	430	;; handle output-reloads on jump insns.
	431
	432	;; We could possibly handle mem before reload as well, but that might
	433	;; complicate things with the need to handle increment
	434	;; side-effects.
	435	(define_predicate "thumb_cbrch_target_operand"
	436	(and (match_code "reg,subreg,mem")
	437	(ior (match_operand 0 "s_register_operand")
	438	(and (match_test "reload_in_progress \|\| reload_completed")
	439	(match_operand 0 "memory_operand")))))
	440
	441	;;-------------------------------------------------------------------------
	442	;;
	443	;; MAVERICK predicates
	444	;;
	445
	446	(define_predicate "cirrus_register_operand"
	447	(match_code "reg,subreg")
	448	{
	449	if (GET_CODE (op) == SUBREG)
	450	op = SUBREG_REG (op);
	451
	452	return (GET_CODE (op) == REG
	453	&& (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
	454	\|\| REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
	455	})
	456
	457	(define_predicate "cirrus_fp_register"
	458	(match_code "reg,subreg")
	459	{
	460	if (GET_CODE (op) == SUBREG)
	461	op = SUBREG_REG (op);
	462
	463	return (GET_CODE (op) == REG
	464	&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
	465	\|\| REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
	466	})
	467
	468	(define_predicate "cirrus_shift_const"
	469	(and (match_code "const_int")
	470	(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
	471
	472