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a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
8fd03515 | 2 | ;; Copyright (C) 2004, 2007, 2008, 2010, 2012 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
29 | return (GET_CODE (op) == REG | |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
34 | ;; Any hard register. | |
35 | (define_predicate "arm_hard_register_operand" | |
36 | (match_code "reg") | |
37 | { | |
38 | return REGNO (op) < FIRST_PSEUDO_REGISTER; | |
39 | }) | |
40 | ||
5b3e6663 PB |
41 | ;; A low register. |
42 | (define_predicate "low_register_operand" | |
43 | (and (match_code "reg") | |
44 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
45 | ||
46 | ;; A low register or const_int. | |
47 | (define_predicate "low_reg_or_int_operand" | |
48 | (ior (match_code "const_int") | |
49 | (match_operand 0 "low_register_operand"))) | |
50 | ||
a657c98a RE |
51 | ;; Any core register, or any pseudo. */ |
52 | (define_predicate "arm_general_register_operand" | |
53 | (match_code "reg,subreg") | |
54 | { | |
55 | if (GET_CODE (op) == SUBREG) | |
56 | op = SUBREG_REG (op); | |
57 | ||
58 | return (GET_CODE (op) == REG | |
59 | && (REGNO (op) <= LAST_ARM_REGNUM | |
60 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
61 | }) | |
62 | ||
63 | (define_predicate "f_register_operand" | |
64 | (match_code "reg,subreg") | |
65 | { | |
66 | if (GET_CODE (op) == SUBREG) | |
67 | op = SUBREG_REG (op); | |
68 | ||
69 | /* We don't consider registers whose class is NO_REGS | |
70 | to be a register operand. */ | |
71 | return (GET_CODE (op) == REG | |
72 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
73 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); | |
74 | }) | |
75 | ||
4e6f5666 JZ |
76 | (define_predicate "vfp_register_operand" |
77 | (match_code "reg,subreg") | |
78 | { | |
79 | if (GET_CODE (op) == SUBREG) | |
80 | op = SUBREG_REG (op); | |
81 | ||
82 | /* We don't consider registers whose class is NO_REGS | |
83 | to be a register operand. */ | |
84 | return (GET_CODE (op) == REG | |
85 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
34db4735 | 86 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
87 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
88 | || (TARGET_VFPD32 | |
89 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
90 | }) | |
91 | ||
681676df RE |
92 | (define_predicate "zero_operand" |
93 | (and (match_code "const_int,const_double,const_vector") | |
94 | (match_test "op == CONST0_RTX (mode)"))) | |
95 | ||
96 | ;; Match a register, or zero in the appropriate mode. | |
97 | (define_predicate "reg_or_zero_operand" | |
98 | (ior (match_operand 0 "s_register_operand") | |
99 | (match_operand 0 "zero_operand"))) | |
100 | ||
fa01135d RE |
101 | (define_special_predicate "subreg_lowpart_operator" |
102 | (and (match_code "subreg") | |
103 | (match_test "subreg_lowpart_p (op)"))) | |
104 | ||
a657c98a RE |
105 | ;; Reg, subreg(reg) or const_int. |
106 | (define_predicate "reg_or_int_operand" | |
107 | (ior (match_code "const_int") | |
108 | (match_operand 0 "s_register_operand"))) | |
109 | ||
110 | (define_predicate "arm_immediate_operand" | |
111 | (and (match_code "const_int") | |
112 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
113 | ||
73160ba9 DJ |
114 | ;; A constant value which fits into two instructions, each taking |
115 | ;; an arithmetic constant operand for one of the words. | |
116 | (define_predicate "arm_immediate_di_operand" | |
117 | (and (match_code "const_int,const_double") | |
118 | (match_test "arm_const_double_by_immediates (op)"))) | |
119 | ||
a657c98a RE |
120 | (define_predicate "arm_neg_immediate_operand" |
121 | (and (match_code "const_int") | |
122 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
123 | ||
124 | (define_predicate "arm_not_immediate_operand" | |
125 | (and (match_code "const_int") | |
126 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
127 | ||
f0c6475a BS |
128 | (define_predicate "const0_operand" |
129 | (and (match_code "const_int") | |
130 | (match_test "INTVAL (op) == 0"))) | |
131 | ||
a657c98a RE |
132 | ;; Something valid on the RHS of an ARM data-processing instruction |
133 | (define_predicate "arm_rhs_operand" | |
134 | (ior (match_operand 0 "s_register_operand") | |
135 | (match_operand 0 "arm_immediate_operand"))) | |
136 | ||
137 | (define_predicate "arm_rhsm_operand" | |
138 | (ior (match_operand 0 "arm_rhs_operand") | |
139 | (match_operand 0 "memory_operand"))) | |
140 | ||
55cdadd5 AS |
141 | ;; This doesn't have to do much because the constant is already checked |
142 | ;; in the shift_operator predicate. | |
c29e2982 BS |
143 | (define_predicate "shift_amount_operand" |
144 | (ior (and (match_test "TARGET_ARM") | |
145 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 146 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 147 | |
36ba4aae IR |
148 | (define_predicate "const_neon_scalar_shift_amount_operand" |
149 | (and (match_code "const_int") | |
150 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode) | |
151 | && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0"))) | |
152 | ||
a657c98a RE |
153 | (define_predicate "arm_add_operand" |
154 | (ior (match_operand 0 "arm_rhs_operand") | |
155 | (match_operand 0 "arm_neg_immediate_operand"))) | |
156 | ||
157 | (define_predicate "arm_addimm_operand" | |
158 | (ior (match_operand 0 "arm_immediate_operand") | |
159 | (match_operand 0 "arm_neg_immediate_operand"))) | |
160 | ||
161 | (define_predicate "arm_not_operand" | |
162 | (ior (match_operand 0 "arm_rhs_operand") | |
163 | (match_operand 0 "arm_not_immediate_operand"))) | |
164 | ||
73160ba9 DJ |
165 | (define_predicate "arm_di_operand" |
166 | (ior (match_operand 0 "s_register_operand") | |
167 | (match_operand 0 "arm_immediate_di_operand"))) | |
168 | ||
a657c98a RE |
169 | ;; True if the operand is a memory reference which contains an |
170 | ;; offsettable address. | |
171 | (define_predicate "offsettable_memory_operand" | |
172 | (and (match_code "mem") | |
173 | (match_test | |
174 | "offsettable_address_p (reload_completed | reload_in_progress, | |
175 | mode, XEXP (op, 0))"))) | |
176 | ||
e6add59b RS |
177 | ;; True if the operand is a memory operand that does not have an |
178 | ;; automodified base register (and thus will not generate output reloads). | |
179 | (define_predicate "call_memory_operand" | |
180 | (and (match_code "mem") | |
181 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
182 | != RTX_AUTOINC") | |
183 | (match_operand 0 "memory_operand")))) | |
184 | ||
a657c98a | 185 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 186 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
187 | (match_test "(!CONSTANT_P (op) |
188 | && (true_regnum(op) == -1 | |
189 | || (GET_CODE (op) == REG | |
190 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) | |
191 | ||
192 | ;; True for valid operands for the rhs of an floating point insns. | |
193 | ;; Allows regs or certain consts on FPA, just regs for everything else. | |
194 | (define_predicate "arm_float_rhs_operand" | |
195 | (ior (match_operand 0 "s_register_operand") | |
196 | (and (match_code "const_double") | |
197 | (match_test "TARGET_FPA && arm_const_double_rtx (op)")))) | |
198 | ||
199 | (define_predicate "arm_float_add_operand" | |
200 | (ior (match_operand 0 "arm_float_rhs_operand") | |
201 | (and (match_code "const_double") | |
202 | (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)")))) | |
203 | ||
204 | (define_predicate "vfp_compare_operand" | |
205 | (ior (match_operand 0 "s_register_operand") | |
206 | (and (match_code "const_double") | |
207 | (match_test "arm_const_double_rtx (op)")))) | |
208 | ||
209 | (define_predicate "arm_float_compare_operand" | |
210 | (if_then_else (match_test "TARGET_VFP") | |
211 | (match_operand 0 "vfp_compare_operand") | |
212 | (match_operand 0 "arm_float_rhs_operand"))) | |
213 | ||
214 | ;; True for valid index operands. | |
215 | (define_predicate "index_operand" | |
216 | (ior (match_operand 0 "s_register_operand") | |
217 | (and (match_operand 0 "immediate_operand") | |
218 | (match_test "(GET_CODE (op) != CONST_INT | |
219 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) | |
220 | ||
221 | ;; True for operators that can be combined with a shift in ARM state. | |
222 | (define_special_predicate "shiftable_operator" | |
223 | (and (match_code "plus,minus,ior,xor,and") | |
224 | (match_test "mode == GET_MODE (op)"))) | |
225 | ||
c112cf2b | 226 | ;; True for logical binary operators. |
a657c98a RE |
227 | (define_special_predicate "logical_binary_operator" |
228 | (and (match_code "ior,xor,and") | |
229 | (match_test "mode == GET_MODE (op)"))) | |
230 | ||
37119410 BS |
231 | ;; True for commutative operators |
232 | (define_special_predicate "commutative_binary_operator" | |
233 | (and (match_code "ior,xor,and,plus") | |
234 | (match_test "mode == GET_MODE (op)"))) | |
235 | ||
a657c98a | 236 | ;; True for shift operators. |
55cdadd5 AS |
237 | ;; Notes: |
238 | ;; * mult is only permitted with a constant shift amount | |
239 | ;; * patterns that permit register shift amounts only in ARM mode use | |
240 | ;; shift_amount_operand, patterns that always allow registers do not, | |
241 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
242 | (define_special_predicate "shift_operator" |
243 | (and (ior (ior (and (match_code "mult") | |
244 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
245 | (and (match_code "rotate") | |
246 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
247 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
55cdadd5 AS |
248 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
249 | (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT | |
250 | || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
a657c98a RE |
251 | (match_test "mode == GET_MODE (op)"))) |
252 | ||
655b30bf JB |
253 | ;; True for shift operators which can be used with saturation instructions. |
254 | (define_special_predicate "sat_shift_operator" | |
5d216c70 UW |
255 | (and (ior (and (match_code "mult") |
256 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
257 | (and (match_code "ashift,ashiftrt") | |
258 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
259 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) | |
655b30bf JB |
260 | (match_test "mode == GET_MODE (op)"))) |
261 | ||
c29e2982 BS |
262 | ;; True for MULT, to identify which variant of shift_operator is in use. |
263 | (define_special_predicate "mult_operator" | |
264 | (match_code "mult")) | |
265 | ||
5b3e6663 PB |
266 | ;; True for operators that have 16-bit thumb variants. */ |
267 | (define_special_predicate "thumb_16bit_operator" | |
268 | (match_code "plus,minus,and,ior,xor")) | |
269 | ||
a657c98a RE |
270 | ;; True for EQ & NE |
271 | (define_special_predicate "equality_operator" | |
272 | (match_code "eq,ne")) | |
273 | ||
f90b7a5a PB |
274 | ;; True for integer comparisons and, if FP is active, for comparisons |
275 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
276 | (define_special_predicate "expandable_comparison_operator" |
277 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
278 | unordered,ordered,unlt,unle,unge,ungt")) | |
279 | ||
280 | ;; Likewise, but only accept comparisons that are directly supported | |
281 | ;; by ARM condition codes. | |
a657c98a | 282 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 283 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 284 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 285 | |
f0c6475a BS |
286 | (define_special_predicate "lt_ge_comparison_operator" |
287 | (match_code "lt,ge")) | |
288 | ||
906668bb BS |
289 | (define_special_predicate "noov_comparison_operator" |
290 | (match_code "lt,ge,eq,ne")) | |
291 | ||
a657c98a RE |
292 | (define_special_predicate "minmax_operator" |
293 | (and (match_code "smin,smax,umin,umax") | |
294 | (match_test "mode == GET_MODE (op)"))) | |
295 | ||
296 | (define_special_predicate "cc_register" | |
297 | (and (match_code "reg") | |
298 | (and (match_test "REGNO (op) == CC_REGNUM") | |
299 | (ior (match_test "mode == GET_MODE (op)") | |
300 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
301 | ||
302 | (define_special_predicate "dominant_cc_register" | |
303 | (match_code "reg") | |
304 | { | |
305 | if (mode == VOIDmode) | |
306 | { | |
307 | mode = GET_MODE (op); | |
308 | ||
309 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
310 | return false; | |
311 | } | |
312 | ||
313 | return (cc_register (op, mode) | |
314 | && (mode == CC_DNEmode | |
315 | || mode == CC_DEQmode | |
316 | || mode == CC_DLEmode | |
317 | || mode == CC_DLTmode | |
318 | || mode == CC_DGEmode | |
319 | || mode == CC_DGTmode | |
320 | || mode == CC_DLEUmode | |
321 | || mode == CC_DLTUmode | |
322 | || mode == CC_DGEUmode | |
323 | || mode == CC_DGTUmode)); | |
324 | }) | |
325 | ||
326 | (define_special_predicate "arm_extendqisi_mem_op" | |
327 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
328 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
329 | XEXP (op, 0), | |
330 | SIGN_EXTEND, | |
331 | 0) | |
332 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 333 | |
01577df7 RE |
334 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
335 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
336 | (match_operand 0 "s_register_operand"))) | |
337 | ||
a657c98a RE |
338 | (define_predicate "power_of_two_operand" |
339 | (match_code "const_int") | |
340 | { | |
29b40d79 | 341 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
342 | |
343 | return value != 0 && (value & (value - 1)) == 0; | |
344 | }) | |
345 | ||
346 | (define_predicate "nonimmediate_di_operand" | |
347 | (match_code "reg,subreg,mem") | |
348 | { | |
349 | if (s_register_operand (op, mode)) | |
350 | return true; | |
351 | ||
352 | if (GET_CODE (op) == SUBREG) | |
353 | op = SUBREG_REG (op); | |
354 | ||
355 | return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); | |
356 | }) | |
357 | ||
358 | (define_predicate "di_operand" | |
359 | (ior (match_code "const_int,const_double") | |
360 | (and (match_code "reg,subreg,mem") | |
361 | (match_operand 0 "nonimmediate_di_operand")))) | |
362 | ||
363 | (define_predicate "nonimmediate_soft_df_operand" | |
364 | (match_code "reg,subreg,mem") | |
365 | { | |
366 | if (s_register_operand (op, mode)) | |
367 | return true; | |
368 | ||
369 | if (GET_CODE (op) == SUBREG) | |
370 | op = SUBREG_REG (op); | |
371 | ||
372 | return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); | |
373 | }) | |
374 | ||
375 | (define_predicate "soft_df_operand" | |
376 | (ior (match_code "const_double") | |
377 | (and (match_code "reg,subreg,mem") | |
378 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
379 | ||
a657c98a RE |
380 | (define_special_predicate "load_multiple_operation" |
381 | (match_code "parallel") | |
382 | { | |
fb40241d IB |
383 | return ldm_stm_operation_p (op, /*load=*/true, SImode, |
384 | /*consecutive=*/false, | |
385 | /*return_pc=*/false); | |
a657c98a RE |
386 | }) |
387 | ||
388 | (define_special_predicate "store_multiple_operation" | |
389 | (match_code "parallel") | |
390 | { | |
fb40241d IB |
391 | return ldm_stm_operation_p (op, /*load=*/false, SImode, |
392 | /*consecutive=*/false, | |
393 | /*return_pc=*/false); | |
a657c98a RE |
394 | }) |
395 | ||
396 | (define_special_predicate "multi_register_push" | |
397 | (match_code "parallel") | |
398 | { | |
399 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
400 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
401 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
402 | return false; | |
403 | ||
404 | return true; | |
405 | }) | |
406 | ||
d018b46e RH |
407 | (define_predicate "push_mult_memory_operand" |
408 | (match_code "mem") | |
409 | { | |
410 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
411 | any point in testing for thumb1 specially? All of the variants | |
412 | use the same form. */ | |
413 | if (TARGET_THUMB1) | |
414 | { | |
415 | /* ??? No attempt is made to represent STMIA, or validate that | |
416 | the stack adjustment matches the register count. This is | |
417 | true of the ARM/Thumb2 path as well. */ | |
418 | rtx x = XEXP (op, 0); | |
419 | if (GET_CODE (x) != PRE_MODIFY) | |
420 | return false; | |
421 | if (XEXP (x, 0) != stack_pointer_rtx) | |
422 | return false; | |
423 | x = XEXP (x, 1); | |
424 | if (GET_CODE (x) != PLUS) | |
425 | return false; | |
426 | if (XEXP (x, 0) != stack_pointer_rtx) | |
427 | return false; | |
428 | return CONST_INT_P (XEXP (x, 1)); | |
429 | } | |
430 | ||
431 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
432 | return memory_operand (op, mode); | |
433 | }) | |
434 | ||
a657c98a RE |
435 | ;;------------------------------------------------------------------------- |
436 | ;; | |
437 | ;; Thumb predicates | |
438 | ;; | |
439 | ||
5b3e6663 | 440 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
441 | (ior (and (match_code "reg,subreg") |
442 | (match_operand 0 "s_register_operand")) | |
443 | (and (match_code "const_int") | |
444 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256")))) | |
445 | ||
5b3e6663 | 446 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
447 | (and (match_code "const_int") |
448 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
449 | ||
450 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
451 | ;; condition code register. Prior to reload we only accept a | |
452 | ;; register. After reload we have to be able to handle memory as | |
453 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
454 | ;; handle output-reloads on jump insns. | |
455 | ||
456 | ;; We could possibly handle mem before reload as well, but that might | |
457 | ;; complicate things with the need to handle increment | |
458 | ;; side-effects. | |
459 | (define_predicate "thumb_cbrch_target_operand" | |
460 | (and (match_code "reg,subreg,mem") | |
461 | (ior (match_operand 0 "s_register_operand") | |
462 | (and (match_test "reload_in_progress || reload_completed") | |
463 | (match_operand 0 "memory_operand"))))) | |
464 | ||
465 | ;;------------------------------------------------------------------------- | |
466 | ;; | |
467 | ;; MAVERICK predicates | |
468 | ;; | |
469 | ||
470 | (define_predicate "cirrus_register_operand" | |
471 | (match_code "reg,subreg") | |
472 | { | |
473 | if (GET_CODE (op) == SUBREG) | |
474 | op = SUBREG_REG (op); | |
475 | ||
476 | return (GET_CODE (op) == REG | |
477 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
478 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
479 | }) | |
480 | ||
481 | (define_predicate "cirrus_fp_register" | |
482 | (match_code "reg,subreg") | |
483 | { | |
484 | if (GET_CODE (op) == SUBREG) | |
485 | op = SUBREG_REG (op); | |
486 | ||
487 | return (GET_CODE (op) == REG | |
488 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
489 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
490 | }) | |
491 | ||
492 | (define_predicate "cirrus_shift_const" | |
493 | (and (match_code "const_int") | |
494 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64"))) | |
495 | ||
8fd03515 XQ |
496 | ;; iWMMXt predicates |
497 | ||
498 | (define_predicate "imm_or_reg_operand" | |
499 | (ior (match_operand 0 "immediate_operand") | |
500 | (match_operand 0 "register_operand"))) | |
a657c98a | 501 | |
88f77cba JB |
502 | ;; Neon predicates |
503 | ||
504 | (define_predicate "const_multiple_of_8_operand" | |
505 | (match_code "const_int") | |
506 | { | |
507 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
508 | return (val & 7) == 0; | |
509 | }) | |
510 | ||
511 | (define_predicate "imm_for_neon_mov_operand" | |
00a3a76a | 512 | (match_code "const_vector,const_int") |
88f77cba JB |
513 | { |
514 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
515 | }) | |
516 | ||
31a0c825 DP |
517 | (define_predicate "imm_for_neon_lshift_operand" |
518 | (match_code "const_vector") | |
519 | { | |
520 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
521 | }) | |
522 | ||
523 | (define_predicate "imm_for_neon_rshift_operand" | |
524 | (match_code "const_vector") | |
525 | { | |
526 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
527 | }) | |
528 | ||
529 | (define_predicate "imm_lshift_or_reg_neon" | |
530 | (ior (match_operand 0 "s_register_operand") | |
531 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
532 | ||
533 | (define_predicate "imm_rshift_or_reg_neon" | |
534 | (ior (match_operand 0 "s_register_operand") | |
535 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
536 | ||
88f77cba JB |
537 | (define_predicate "imm_for_neon_logic_operand" |
538 | (match_code "const_vector") | |
539 | { | |
b3b7bbce SL |
540 | return (TARGET_NEON |
541 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
88f77cba JB |
542 | }) |
543 | ||
544 | (define_predicate "imm_for_neon_inv_logic_operand" | |
545 | (match_code "const_vector") | |
546 | { | |
b3b7bbce SL |
547 | return (TARGET_NEON |
548 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
88f77cba JB |
549 | }) |
550 | ||
551 | (define_predicate "neon_logic_op2" | |
552 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
553 | (match_operand 0 "s_register_operand"))) | |
554 | ||
555 | (define_predicate "neon_inv_logic_op2" | |
556 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
557 | (match_operand 0 "s_register_operand"))) | |
558 | ||
559 | ;; TODO: We could check lane numbers more precisely based on the mode. | |
560 | (define_predicate "neon_lane_number" | |
561 | (and (match_code "const_int") | |
3460fdf3 | 562 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))) |
73160ba9 DJ |
563 | ;; Predicates for named expanders that overlap multiple ISAs. |
564 | ||
565 | (define_predicate "cmpdi_operand" | |
566 | (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") | |
567 | (and (match_test "TARGET_ARM") | |
568 | (match_operand 0 "cirrus_fp_register")) | |
569 | (and (match_test "TARGET_32BIT") | |
570 | (match_operand 0 "arm_di_operand")))) | |
88f77cba | 571 | |
999a9cc5 MS |
572 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
573 | (define_predicate "arm_sync_memory_operand" | |
574 | (and (match_operand 0 "memory_operand") | |
575 | (match_code "reg" "0"))) | |
576 | ||
46b57af1 TB |
577 | ;; Predicates for parallel expanders based on mode. |
578 | (define_special_predicate "vect_par_constant_high" | |
579 | (match_code "parallel") | |
580 | { | |
581 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
582 | int i; | |
583 | int base = GET_MODE_NUNITS (mode); | |
584 | ||
585 | if ((count < 1) | |
586 | || (count != base/2)) | |
587 | return false; | |
588 | ||
589 | if (!VECTOR_MODE_P (mode)) | |
590 | return false; | |
591 | ||
592 | for (i = 0; i < count; i++) | |
593 | { | |
594 | rtx elt = XVECEXP (op, 0, i); | |
595 | int val; | |
596 | ||
597 | if (GET_CODE (elt) != CONST_INT) | |
598 | return false; | |
599 | ||
600 | val = INTVAL (elt); | |
601 | if (val != (base/2) + i) | |
602 | return false; | |
603 | } | |
604 | return true; | |
605 | }) | |
606 | ||
607 | (define_special_predicate "vect_par_constant_low" | |
608 | (match_code "parallel") | |
609 | { | |
610 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
611 | int i; | |
612 | int base = GET_MODE_NUNITS (mode); | |
613 | ||
614 | if ((count < 1) | |
615 | || (count != base/2)) | |
616 | return false; | |
617 | ||
618 | if (!VECTOR_MODE_P (mode)) | |
619 | return false; | |
620 | ||
621 | for (i = 0; i < count; i++) | |
622 | { | |
623 | rtx elt = XVECEXP (op, 0, i); | |
624 | int val; | |
625 | ||
626 | if (GET_CODE (elt) != CONST_INT) | |
627 | return false; | |
628 | ||
629 | val = INTVAL (elt); | |
630 | if (val != i) | |
631 | return false; | |
632 | } | |
633 | return true; | |
634 | }) | |
6308e208 | 635 | |
7f3d8f56 RR |
636 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
637 | (and (match_code "const_double") | |
638 | (match_test "TARGET_32BIT && TARGET_VFP | |
639 | && vfp3_const_double_for_fract_bits (op)"))) | |
640 | ||
12c4ecb1 | 641 | (define_predicate "neon_struct_operand" |
6308e208 RS |
642 | (and (match_code "mem") |
643 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) | |
9a1ea4b9 | 644 | |
12c4ecb1 RS |
645 | (define_predicate "neon_struct_or_register_operand" |
646 | (ior (match_operand 0 "neon_struct_operand") | |
647 | (match_operand 0 "s_register_operand"))) | |
648 | ||
9a1ea4b9 RR |
649 | (define_special_predicate "add_operator" |
650 | (match_code "plus")) | |
18f0fe6b RH |
651 | |
652 | (define_predicate "mem_noofs_operand" | |
653 | (and (match_code "mem") | |
654 | (match_code "reg" "0"))) |