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a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
818ab71a | 2 | ;; Copyright (C) 2004-2016 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
d435a4be | 29 | return (REG_P (op) |
a657c98a RE |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
1c50eada KT |
34 | (define_predicate "imm_for_neon_inv_logic_operand" |
35 | (match_code "const_vector") | |
36 | { | |
37 | return (TARGET_NEON | |
38 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
39 | }) | |
40 | ||
41 | (define_predicate "neon_inv_logic_op2" | |
42 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
43 | (match_operand 0 "s_register_operand"))) | |
44 | ||
b6af05a9 KT |
45 | (define_predicate "imm_for_neon_logic_operand" |
46 | (match_code "const_vector") | |
47 | { | |
48 | return (TARGET_NEON | |
49 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
50 | }) | |
51 | ||
52 | (define_predicate "neon_logic_op2" | |
53 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
54 | (match_operand 0 "s_register_operand"))) | |
55 | ||
8b0497de | 56 | ;; Any general register. |
03158648 | 57 | (define_predicate "arm_hard_general_register_operand" |
a657c98a RE |
58 | (match_code "reg") |
59 | { | |
03158648 | 60 | return REGNO (op) <= LAST_ARM_REGNUM; |
a657c98a RE |
61 | }) |
62 | ||
5b3e6663 PB |
63 | ;; A low register. |
64 | (define_predicate "low_register_operand" | |
65 | (and (match_code "reg") | |
66 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
67 | ||
68 | ;; A low register or const_int. | |
69 | (define_predicate "low_reg_or_int_operand" | |
70 | (ior (match_code "const_int") | |
71 | (match_operand 0 "low_register_operand"))) | |
72 | ||
a657c98a RE |
73 | ;; Any core register, or any pseudo. */ |
74 | (define_predicate "arm_general_register_operand" | |
75 | (match_code "reg,subreg") | |
76 | { | |
77 | if (GET_CODE (op) == SUBREG) | |
78 | op = SUBREG_REG (op); | |
79 | ||
d435a4be | 80 | return (REG_P (op) |
a657c98a RE |
81 | && (REGNO (op) <= LAST_ARM_REGNUM |
82 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
83 | }) | |
84 | ||
4e6f5666 JZ |
85 | (define_predicate "vfp_register_operand" |
86 | (match_code "reg,subreg") | |
87 | { | |
88 | if (GET_CODE (op) == SUBREG) | |
89 | op = SUBREG_REG (op); | |
90 | ||
91 | /* We don't consider registers whose class is NO_REGS | |
92 | to be a register operand. */ | |
d435a4be | 93 | return (REG_P (op) |
4e6f5666 | 94 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
34db4735 | 95 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
96 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
97 | || (TARGET_VFPD32 | |
98 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
99 | }) | |
100 | ||
315d7bd4 CL |
101 | (define_predicate "vfp_hard_register_operand" |
102 | (match_code "reg") | |
103 | { | |
104 | return (IS_VFP_REGNUM (REGNO (op))); | |
105 | }) | |
106 | ||
681676df RE |
107 | (define_predicate "zero_operand" |
108 | (and (match_code "const_int,const_double,const_vector") | |
109 | (match_test "op == CONST0_RTX (mode)"))) | |
110 | ||
111 | ;; Match a register, or zero in the appropriate mode. | |
112 | (define_predicate "reg_or_zero_operand" | |
113 | (ior (match_operand 0 "s_register_operand") | |
114 | (match_operand 0 "zero_operand"))) | |
115 | ||
fa01135d RE |
116 | (define_special_predicate "subreg_lowpart_operator" |
117 | (and (match_code "subreg") | |
118 | (match_test "subreg_lowpart_p (op)"))) | |
119 | ||
a657c98a RE |
120 | ;; Reg, subreg(reg) or const_int. |
121 | (define_predicate "reg_or_int_operand" | |
122 | (ior (match_code "const_int") | |
123 | (match_operand 0 "s_register_operand"))) | |
124 | ||
125 | (define_predicate "arm_immediate_operand" | |
126 | (and (match_code "const_int") | |
127 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
128 | ||
73160ba9 DJ |
129 | ;; A constant value which fits into two instructions, each taking |
130 | ;; an arithmetic constant operand for one of the words. | |
131 | (define_predicate "arm_immediate_di_operand" | |
132 | (and (match_code "const_int,const_double") | |
133 | (match_test "arm_const_double_by_immediates (op)"))) | |
134 | ||
a657c98a RE |
135 | (define_predicate "arm_neg_immediate_operand" |
136 | (and (match_code "const_int") | |
137 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
138 | ||
139 | (define_predicate "arm_not_immediate_operand" | |
140 | (and (match_code "const_int") | |
141 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
142 | ||
f0c6475a | 143 | (define_predicate "const0_operand" |
d1fb6940 | 144 | (match_test "op == CONST0_RTX (mode)")) |
f0c6475a | 145 | |
a657c98a RE |
146 | ;; Something valid on the RHS of an ARM data-processing instruction |
147 | (define_predicate "arm_rhs_operand" | |
148 | (ior (match_operand 0 "s_register_operand") | |
149 | (match_operand 0 "arm_immediate_operand"))) | |
150 | ||
151 | (define_predicate "arm_rhsm_operand" | |
152 | (ior (match_operand 0 "arm_rhs_operand") | |
153 | (match_operand 0 "memory_operand"))) | |
154 | ||
fc02bcca JL |
155 | (define_predicate "const_int_I_operand" |
156 | (and (match_operand 0 "const_int_operand") | |
157 | (match_test "satisfies_constraint_I (op)"))) | |
158 | ||
159 | (define_predicate "const_int_M_operand" | |
160 | (and (match_operand 0 "const_int_operand") | |
161 | (match_test "satisfies_constraint_M (op)"))) | |
162 | ||
55cdadd5 AS |
163 | ;; This doesn't have to do much because the constant is already checked |
164 | ;; in the shift_operator predicate. | |
c29e2982 BS |
165 | (define_predicate "shift_amount_operand" |
166 | (ior (and (match_test "TARGET_ARM") | |
167 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 168 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 169 | |
36ba4aae IR |
170 | (define_predicate "const_neon_scalar_shift_amount_operand" |
171 | (and (match_code "const_int") | |
dec21bbc | 172 | (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) |
36ba4aae | 173 | |
56289ed2 SD |
174 | (define_predicate "ldrd_strd_offset_operand" |
175 | (and (match_operand 0 "const_int_operand") | |
176 | (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) | |
177 | ||
a657c98a RE |
178 | (define_predicate "arm_add_operand" |
179 | (ior (match_operand 0 "arm_rhs_operand") | |
180 | (match_operand 0 "arm_neg_immediate_operand"))) | |
181 | ||
1c50eada KT |
182 | (define_predicate "arm_anddi_operand_neon" |
183 | (ior (match_operand 0 "s_register_operand") | |
184 | (and (match_code "const_int") | |
185 | (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) | |
186 | (match_operand 0 "neon_inv_logic_op2"))) | |
187 | ||
b6af05a9 KT |
188 | (define_predicate "arm_iordi_operand_neon" |
189 | (ior (match_operand 0 "s_register_operand") | |
190 | (and (match_code "const_int") | |
191 | (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")) | |
192 | (match_operand 0 "neon_logic_op2"))) | |
193 | ||
79678d04 KT |
194 | (define_predicate "arm_xordi_operand" |
195 | (ior (match_operand 0 "s_register_operand") | |
196 | (and (match_code "const_int") | |
197 | (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) | |
198 | ||
44cd6810 WG |
199 | (define_predicate "arm_adddi_operand" |
200 | (ior (match_operand 0 "s_register_operand") | |
201 | (and (match_code "const_int") | |
202 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
203 | ||
a657c98a RE |
204 | (define_predicate "arm_addimm_operand" |
205 | (ior (match_operand 0 "arm_immediate_operand") | |
206 | (match_operand 0 "arm_neg_immediate_operand"))) | |
207 | ||
208 | (define_predicate "arm_not_operand" | |
209 | (ior (match_operand 0 "arm_rhs_operand") | |
210 | (match_operand 0 "arm_not_immediate_operand"))) | |
211 | ||
73160ba9 DJ |
212 | (define_predicate "arm_di_operand" |
213 | (ior (match_operand 0 "s_register_operand") | |
214 | (match_operand 0 "arm_immediate_di_operand"))) | |
215 | ||
a657c98a RE |
216 | ;; True if the operand is a memory reference which contains an |
217 | ;; offsettable address. | |
218 | (define_predicate "offsettable_memory_operand" | |
219 | (and (match_code "mem") | |
220 | (match_test | |
221 | "offsettable_address_p (reload_completed | reload_in_progress, | |
222 | mode, XEXP (op, 0))"))) | |
223 | ||
e6add59b RS |
224 | ;; True if the operand is a memory operand that does not have an |
225 | ;; automodified base register (and thus will not generate output reloads). | |
226 | (define_predicate "call_memory_operand" | |
227 | (and (match_code "mem") | |
228 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
229 | != RTX_AUTOINC") | |
230 | (match_operand 0 "memory_operand")))) | |
231 | ||
a657c98a | 232 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 233 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
234 | (match_test "(!CONSTANT_P (op) |
235 | && (true_regnum(op) == -1 | |
d435a4be | 236 | || (REG_P (op) |
a657c98a RE |
237 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) |
238 | ||
a657c98a RE |
239 | (define_predicate "vfp_compare_operand" |
240 | (ior (match_operand 0 "s_register_operand") | |
241 | (and (match_code "const_double") | |
242 | (match_test "arm_const_double_rtx (op)")))) | |
243 | ||
a657c98a RE |
244 | ;; True for valid index operands. |
245 | (define_predicate "index_operand" | |
246 | (ior (match_operand 0 "s_register_operand") | |
247 | (and (match_operand 0 "immediate_operand") | |
d435a4be | 248 | (match_test "(!CONST_INT_P (op) |
a657c98a RE |
249 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) |
250 | ||
251 | ;; True for operators that can be combined with a shift in ARM state. | |
252 | (define_special_predicate "shiftable_operator" | |
253 | (and (match_code "plus,minus,ior,xor,and") | |
254 | (match_test "mode == GET_MODE (op)"))) | |
255 | ||
95b97fac KT |
256 | (define_special_predicate "shiftable_operator_strict_it" |
257 | (and (match_code "plus,and") | |
258 | (match_test "mode == GET_MODE (op)"))) | |
259 | ||
c112cf2b | 260 | ;; True for logical binary operators. |
a657c98a RE |
261 | (define_special_predicate "logical_binary_operator" |
262 | (and (match_code "ior,xor,and") | |
263 | (match_test "mode == GET_MODE (op)"))) | |
264 | ||
37119410 BS |
265 | ;; True for commutative operators |
266 | (define_special_predicate "commutative_binary_operator" | |
267 | (and (match_code "ior,xor,and,plus") | |
268 | (match_test "mode == GET_MODE (op)"))) | |
269 | ||
a657c98a | 270 | ;; True for shift operators. |
55cdadd5 AS |
271 | ;; Notes: |
272 | ;; * mult is only permitted with a constant shift amount | |
273 | ;; * patterns that permit register shift amounts only in ARM mode use | |
274 | ;; shift_amount_operand, patterns that always allow registers do not, | |
275 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
276 | (define_special_predicate "shift_operator" |
277 | (and (ior (ior (and (match_code "mult") | |
278 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
279 | (and (match_code "rotate") | |
d435a4be | 280 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 281 | && (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
282 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
283 | (match_test "!CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 284 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
285 | (match_test "mode == GET_MODE (op)"))) |
286 | ||
287 | (define_special_predicate "shift_nomul_operator" | |
288 | (and (ior (and (match_code "rotate") | |
289 | (match_test "CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 290 | && (UINTVAL (XEXP (op, 1))) < 32")) |
55cdadd5 | 291 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
d435a4be | 292 | (match_test "!CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 293 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
a657c98a RE |
294 | (match_test "mode == GET_MODE (op)"))) |
295 | ||
655b30bf JB |
296 | ;; True for shift operators which can be used with saturation instructions. |
297 | (define_special_predicate "sat_shift_operator" | |
5d216c70 UW |
298 | (and (ior (and (match_code "mult") |
299 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
300 | (and (match_code "ashift,ashiftrt") | |
d435a4be | 301 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 302 | && (UINTVAL (XEXP (op, 1)) < 32)"))) |
655b30bf JB |
303 | (match_test "mode == GET_MODE (op)"))) |
304 | ||
c29e2982 BS |
305 | ;; True for MULT, to identify which variant of shift_operator is in use. |
306 | (define_special_predicate "mult_operator" | |
307 | (match_code "mult")) | |
308 | ||
5b3e6663 PB |
309 | ;; True for operators that have 16-bit thumb variants. */ |
310 | (define_special_predicate "thumb_16bit_operator" | |
311 | (match_code "plus,minus,and,ior,xor")) | |
312 | ||
a657c98a RE |
313 | ;; True for EQ & NE |
314 | (define_special_predicate "equality_operator" | |
315 | (match_code "eq,ne")) | |
316 | ||
f90b7a5a PB |
317 | ;; True for integer comparisons and, if FP is active, for comparisons |
318 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
319 | (define_special_predicate "expandable_comparison_operator" |
320 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
321 | unordered,ordered,unlt,unle,unge,ungt")) | |
322 | ||
323 | ;; Likewise, but only accept comparisons that are directly supported | |
324 | ;; by ARM condition codes. | |
a657c98a | 325 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 326 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 327 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 328 | |
ac4bf407 KT |
329 | ;; Likewise, but don't ignore the mode. |
330 | ;; RTL SET operations require their operands source and destination have | |
331 | ;; the same modes, so we can't ignore the modes there. See PR target/69161. | |
332 | (define_predicate "arm_comparison_operator_mode" | |
333 | (and (match_operand 0 "expandable_comparison_operator") | |
334 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | |
335 | ||
f0c6475a BS |
336 | (define_special_predicate "lt_ge_comparison_operator" |
337 | (match_code "lt,ge")) | |
338 | ||
a5a4c20a KT |
339 | ;; The vsel instruction only accepts the ARM condition codes listed below. |
340 | (define_special_predicate "arm_vsel_comparison_operator" | |
341 | (and (match_operand 0 "expandable_comparison_operator") | |
342 | (match_test "maybe_get_arm_condition_code (op) == ARM_GE | |
343 | || maybe_get_arm_condition_code (op) == ARM_GT | |
344 | || maybe_get_arm_condition_code (op) == ARM_EQ | |
345 | || maybe_get_arm_condition_code (op) == ARM_VS | |
346 | || maybe_get_arm_condition_code (op) == ARM_LT | |
347 | || maybe_get_arm_condition_code (op) == ARM_LE | |
348 | || maybe_get_arm_condition_code (op) == ARM_NE | |
349 | || maybe_get_arm_condition_code (op) == ARM_VC"))) | |
350 | ||
1572e697 KT |
351 | (define_special_predicate "arm_cond_move_operator" |
352 | (if_then_else (match_test "arm_restrict_it") | |
353 | (and (match_test "TARGET_FPU_ARMV8") | |
354 | (match_operand 0 "arm_vsel_comparison_operator")) | |
355 | (match_operand 0 "expandable_comparison_operator"))) | |
356 | ||
906668bb BS |
357 | (define_special_predicate "noov_comparison_operator" |
358 | (match_code "lt,ge,eq,ne")) | |
359 | ||
a657c98a RE |
360 | (define_special_predicate "minmax_operator" |
361 | (and (match_code "smin,smax,umin,umax") | |
362 | (match_test "mode == GET_MODE (op)"))) | |
363 | ||
364 | (define_special_predicate "cc_register" | |
365 | (and (match_code "reg") | |
366 | (and (match_test "REGNO (op) == CC_REGNUM") | |
367 | (ior (match_test "mode == GET_MODE (op)") | |
368 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
369 | ||
370 | (define_special_predicate "dominant_cc_register" | |
371 | (match_code "reg") | |
372 | { | |
373 | if (mode == VOIDmode) | |
374 | { | |
375 | mode = GET_MODE (op); | |
376 | ||
377 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
378 | return false; | |
379 | } | |
380 | ||
381 | return (cc_register (op, mode) | |
382 | && (mode == CC_DNEmode | |
383 | || mode == CC_DEQmode | |
384 | || mode == CC_DLEmode | |
385 | || mode == CC_DLTmode | |
386 | || mode == CC_DGEmode | |
387 | || mode == CC_DGTmode | |
388 | || mode == CC_DLEUmode | |
389 | || mode == CC_DLTUmode | |
390 | || mode == CC_DGEUmode | |
391 | || mode == CC_DGTUmode)); | |
392 | }) | |
393 | ||
394 | (define_special_predicate "arm_extendqisi_mem_op" | |
395 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
396 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
397 | XEXP (op, 0), | |
398 | SIGN_EXTEND, | |
399 | 0) | |
400 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 401 | |
01577df7 RE |
402 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
403 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
404 | (match_operand 0 "s_register_operand"))) | |
405 | ||
a657c98a RE |
406 | (define_predicate "power_of_two_operand" |
407 | (match_code "const_int") | |
408 | { | |
29b40d79 | 409 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
410 | |
411 | return value != 0 && (value & (value - 1)) == 0; | |
412 | }) | |
413 | ||
414 | (define_predicate "nonimmediate_di_operand" | |
415 | (match_code "reg,subreg,mem") | |
416 | { | |
417 | if (s_register_operand (op, mode)) | |
418 | return true; | |
419 | ||
420 | if (GET_CODE (op) == SUBREG) | |
421 | op = SUBREG_REG (op); | |
422 | ||
d435a4be | 423 | return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); |
a657c98a RE |
424 | }) |
425 | ||
426 | (define_predicate "di_operand" | |
427 | (ior (match_code "const_int,const_double") | |
428 | (and (match_code "reg,subreg,mem") | |
429 | (match_operand 0 "nonimmediate_di_operand")))) | |
430 | ||
431 | (define_predicate "nonimmediate_soft_df_operand" | |
432 | (match_code "reg,subreg,mem") | |
433 | { | |
434 | if (s_register_operand (op, mode)) | |
435 | return true; | |
436 | ||
437 | if (GET_CODE (op) == SUBREG) | |
438 | op = SUBREG_REG (op); | |
439 | ||
d435a4be | 440 | return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); |
a657c98a RE |
441 | }) |
442 | ||
443 | (define_predicate "soft_df_operand" | |
444 | (ior (match_code "const_double") | |
445 | (and (match_code "reg,subreg,mem") | |
446 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
447 | ||
a657c98a RE |
448 | (define_special_predicate "load_multiple_operation" |
449 | (match_code "parallel") | |
450 | { | |
fb40241d IB |
451 | return ldm_stm_operation_p (op, /*load=*/true, SImode, |
452 | /*consecutive=*/false, | |
453 | /*return_pc=*/false); | |
a657c98a RE |
454 | }) |
455 | ||
456 | (define_special_predicate "store_multiple_operation" | |
457 | (match_code "parallel") | |
458 | { | |
fb40241d IB |
459 | return ldm_stm_operation_p (op, /*load=*/false, SImode, |
460 | /*consecutive=*/false, | |
461 | /*return_pc=*/false); | |
a657c98a RE |
462 | }) |
463 | ||
3aee1982 IB |
464 | (define_special_predicate "pop_multiple_return" |
465 | (match_code "parallel") | |
466 | { | |
467 | return ldm_stm_operation_p (op, /*load=*/true, SImode, | |
468 | /*consecutive=*/false, | |
469 | /*return_pc=*/true); | |
470 | }) | |
471 | ||
4b2678f8 IB |
472 | (define_special_predicate "pop_multiple_fp" |
473 | (match_code "parallel") | |
474 | { | |
475 | return ldm_stm_operation_p (op, /*load=*/true, DFmode, | |
476 | /*consecutive=*/true, | |
477 | /*return_pc=*/false); | |
478 | }) | |
479 | ||
a657c98a RE |
480 | (define_special_predicate "multi_register_push" |
481 | (match_code "parallel") | |
482 | { | |
483 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
484 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
485 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
486 | return false; | |
487 | ||
488 | return true; | |
489 | }) | |
490 | ||
d018b46e RH |
491 | (define_predicate "push_mult_memory_operand" |
492 | (match_code "mem") | |
493 | { | |
494 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
495 | any point in testing for thumb1 specially? All of the variants | |
496 | use the same form. */ | |
497 | if (TARGET_THUMB1) | |
498 | { | |
499 | /* ??? No attempt is made to represent STMIA, or validate that | |
500 | the stack adjustment matches the register count. This is | |
501 | true of the ARM/Thumb2 path as well. */ | |
502 | rtx x = XEXP (op, 0); | |
503 | if (GET_CODE (x) != PRE_MODIFY) | |
504 | return false; | |
505 | if (XEXP (x, 0) != stack_pointer_rtx) | |
506 | return false; | |
507 | x = XEXP (x, 1); | |
508 | if (GET_CODE (x) != PLUS) | |
509 | return false; | |
510 | if (XEXP (x, 0) != stack_pointer_rtx) | |
511 | return false; | |
512 | return CONST_INT_P (XEXP (x, 1)); | |
513 | } | |
514 | ||
515 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
516 | return memory_operand (op, mode); | |
517 | }) | |
518 | ||
a657c98a RE |
519 | ;;------------------------------------------------------------------------- |
520 | ;; | |
521 | ;; Thumb predicates | |
522 | ;; | |
523 | ||
5b3e6663 | 524 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
525 | (ior (and (match_code "reg,subreg") |
526 | (match_operand 0 "s_register_operand")) | |
527 | (and (match_code "const_int") | |
dec21bbc | 528 | (match_test "(UINTVAL (op)) < 256")))) |
a657c98a | 529 | |
5b3e6663 | 530 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
531 | (and (match_code "const_int") |
532 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
533 | ||
534 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
535 | ;; condition code register. Prior to reload we only accept a | |
536 | ;; register. After reload we have to be able to handle memory as | |
537 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
538 | ;; handle output-reloads on jump insns. | |
539 | ||
540 | ;; We could possibly handle mem before reload as well, but that might | |
541 | ;; complicate things with the need to handle increment | |
542 | ;; side-effects. | |
543 | (define_predicate "thumb_cbrch_target_operand" | |
544 | (and (match_code "reg,subreg,mem") | |
545 | (ior (match_operand 0 "s_register_operand") | |
546 | (and (match_test "reload_in_progress || reload_completed") | |
547 | (match_operand 0 "memory_operand"))))) | |
548 | ||
549 | ;;------------------------------------------------------------------------- | |
550 | ;; | |
8fd03515 | 551 | ;; iWMMXt predicates |
dae840fc | 552 | ;; |
8fd03515 XQ |
553 | |
554 | (define_predicate "imm_or_reg_operand" | |
555 | (ior (match_operand 0 "immediate_operand") | |
556 | (match_operand 0 "register_operand"))) | |
a657c98a | 557 | |
88f77cba JB |
558 | ;; Neon predicates |
559 | ||
560 | (define_predicate "const_multiple_of_8_operand" | |
561 | (match_code "const_int") | |
562 | { | |
563 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
564 | return (val & 7) == 0; | |
565 | }) | |
566 | ||
567 | (define_predicate "imm_for_neon_mov_operand" | |
00a3a76a | 568 | (match_code "const_vector,const_int") |
88f77cba JB |
569 | { |
570 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
571 | }) | |
572 | ||
31a0c825 DP |
573 | (define_predicate "imm_for_neon_lshift_operand" |
574 | (match_code "const_vector") | |
575 | { | |
576 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
577 | }) | |
578 | ||
579 | (define_predicate "imm_for_neon_rshift_operand" | |
580 | (match_code "const_vector") | |
581 | { | |
582 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
583 | }) | |
584 | ||
585 | (define_predicate "imm_lshift_or_reg_neon" | |
586 | (ior (match_operand 0 "s_register_operand") | |
587 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
588 | ||
589 | (define_predicate "imm_rshift_or_reg_neon" | |
590 | (ior (match_operand 0 "s_register_operand") | |
591 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
592 | ||
73160ba9 DJ |
593 | ;; Predicates for named expanders that overlap multiple ISAs. |
594 | ||
595 | (define_predicate "cmpdi_operand" | |
dae840fc RE |
596 | (and (match_test "TARGET_32BIT") |
597 | (match_operand 0 "arm_di_operand"))) | |
88f77cba | 598 | |
999a9cc5 MS |
599 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
600 | (define_predicate "arm_sync_memory_operand" | |
601 | (and (match_operand 0 "memory_operand") | |
602 | (match_code "reg" "0"))) | |
603 | ||
46b57af1 TB |
604 | ;; Predicates for parallel expanders based on mode. |
605 | (define_special_predicate "vect_par_constant_high" | |
606 | (match_code "parallel") | |
607 | { | |
93c590ee | 608 | return arm_simd_check_vect_par_cnst_half_p (op, mode, true); |
46b57af1 TB |
609 | }) |
610 | ||
611 | (define_special_predicate "vect_par_constant_low" | |
612 | (match_code "parallel") | |
613 | { | |
93c590ee | 614 | return arm_simd_check_vect_par_cnst_half_p (op, mode, false); |
46b57af1 | 615 | }) |
6308e208 | 616 | |
7f3d8f56 RR |
617 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
618 | (and (match_code "const_double") | |
00ea1506 RE |
619 | (match_test "TARGET_32BIT |
620 | && vfp3_const_double_for_fract_bits (op)"))) | |
c75d51aa RL |
621 | |
622 | (define_predicate "const_double_vcvt_power_of_two" | |
623 | (and (match_code "const_double") | |
00ea1506 | 624 | (match_test "TARGET_32BIT |
85f5231d | 625 | && vfp3_const_double_for_bits (op) > 0"))) |
7f3d8f56 | 626 | |
12c4ecb1 | 627 | (define_predicate "neon_struct_operand" |
6308e208 | 628 | (and (match_code "mem") |
33255ae3 | 629 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) |
9a1ea4b9 | 630 | |
33255ae3 JB |
631 | (define_predicate "neon_permissive_struct_operand" |
632 | (and (match_code "mem") | |
633 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) | |
634 | ||
635 | (define_predicate "neon_perm_struct_or_reg_operand" | |
636 | (ior (match_operand 0 "neon_permissive_struct_operand") | |
12c4ecb1 RS |
637 | (match_operand 0 "s_register_operand"))) |
638 | ||
9a1ea4b9 RR |
639 | (define_special_predicate "add_operator" |
640 | (match_code "plus")) | |
18f0fe6b RH |
641 | |
642 | (define_predicate "mem_noofs_operand" | |
643 | (and (match_code "mem") | |
644 | (match_code "reg" "0"))) | |
9adcfa3c RR |
645 | |
646 | (define_predicate "call_insn_operand" | |
10432733 JW |
647 | (ior (and (match_code "symbol_ref") |
648 | (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) | |
9adcfa3c | 649 | (match_operand 0 "s_register_operand"))) |