]>
Commit | Line | Data |
---|---|---|
a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
a5544970 | 2 | ;; Copyright (C) 2004-2019 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
d435a4be | 29 | return (REG_P (op) |
a657c98a RE |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
89d75572 TP |
34 | ; Predicate for stack protector guard's address in |
35 | ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns | |
36 | (define_predicate "guard_addr_operand" | |
37 | (match_test "true") | |
38 | { | |
39 | return (CONSTANT_ADDRESS_P (op) | |
40 | || !targetm.cannot_force_const_mem (mode, op)); | |
41 | }) | |
42 | ||
43 | ; Predicate for stack protector guard in stack_protect_combined_set and | |
44 | ; stack_protect_combined_test patterns | |
45 | (define_predicate "guard_operand" | |
46 | (match_code "mem") | |
47 | { | |
48 | return guard_addr_operand (XEXP (op, 0), mode); | |
49 | }) | |
50 | ||
1c50eada KT |
51 | (define_predicate "imm_for_neon_inv_logic_operand" |
52 | (match_code "const_vector") | |
53 | { | |
54 | return (TARGET_NEON | |
55 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
56 | }) | |
57 | ||
58 | (define_predicate "neon_inv_logic_op2" | |
59 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
60 | (match_operand 0 "s_register_operand"))) | |
61 | ||
b6af05a9 KT |
62 | (define_predicate "imm_for_neon_logic_operand" |
63 | (match_code "const_vector") | |
64 | { | |
65 | return (TARGET_NEON | |
66 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
67 | }) | |
68 | ||
69 | (define_predicate "neon_logic_op2" | |
70 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
71 | (match_operand 0 "s_register_operand"))) | |
72 | ||
8b0497de | 73 | ;; Any general register. |
03158648 | 74 | (define_predicate "arm_hard_general_register_operand" |
a657c98a RE |
75 | (match_code "reg") |
76 | { | |
03158648 | 77 | return REGNO (op) <= LAST_ARM_REGNUM; |
a657c98a RE |
78 | }) |
79 | ||
5b3e6663 PB |
80 | ;; A low register. |
81 | (define_predicate "low_register_operand" | |
82 | (and (match_code "reg") | |
83 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
84 | ||
85 | ;; A low register or const_int. | |
86 | (define_predicate "low_reg_or_int_operand" | |
87 | (ior (match_code "const_int") | |
88 | (match_operand 0 "low_register_operand"))) | |
89 | ||
a657c98a RE |
90 | ;; Any core register, or any pseudo. */ |
91 | (define_predicate "arm_general_register_operand" | |
92 | (match_code "reg,subreg") | |
93 | { | |
94 | if (GET_CODE (op) == SUBREG) | |
95 | op = SUBREG_REG (op); | |
96 | ||
d435a4be | 97 | return (REG_P (op) |
a657c98a RE |
98 | && (REGNO (op) <= LAST_ARM_REGNUM |
99 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
100 | }) | |
101 | ||
fb117b1c BE |
102 | (define_predicate "arm_general_adddi_operand" |
103 | (ior (match_operand 0 "arm_general_register_operand") | |
104 | (and (match_code "const_int") | |
105 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
106 | ||
4e6f5666 JZ |
107 | (define_predicate "vfp_register_operand" |
108 | (match_code "reg,subreg") | |
109 | { | |
110 | if (GET_CODE (op) == SUBREG) | |
111 | op = SUBREG_REG (op); | |
112 | ||
113 | /* We don't consider registers whose class is NO_REGS | |
114 | to be a register operand. */ | |
d435a4be | 115 | return (REG_P (op) |
4e6f5666 | 116 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
34db4735 | 117 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
118 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
119 | || (TARGET_VFPD32 | |
120 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
121 | }) | |
122 | ||
315d7bd4 CL |
123 | (define_predicate "vfp_hard_register_operand" |
124 | (match_code "reg") | |
125 | { | |
126 | return (IS_VFP_REGNUM (REGNO (op))); | |
127 | }) | |
128 | ||
681676df RE |
129 | (define_predicate "zero_operand" |
130 | (and (match_code "const_int,const_double,const_vector") | |
131 | (match_test "op == CONST0_RTX (mode)"))) | |
132 | ||
133 | ;; Match a register, or zero in the appropriate mode. | |
134 | (define_predicate "reg_or_zero_operand" | |
135 | (ior (match_operand 0 "s_register_operand") | |
136 | (match_operand 0 "zero_operand"))) | |
137 | ||
fa01135d RE |
138 | (define_special_predicate "subreg_lowpart_operator" |
139 | (and (match_code "subreg") | |
140 | (match_test "subreg_lowpart_p (op)"))) | |
141 | ||
a657c98a RE |
142 | ;; Reg, subreg(reg) or const_int. |
143 | (define_predicate "reg_or_int_operand" | |
144 | (ior (match_code "const_int") | |
145 | (match_operand 0 "s_register_operand"))) | |
146 | ||
147 | (define_predicate "arm_immediate_operand" | |
148 | (and (match_code "const_int") | |
149 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
150 | ||
73160ba9 DJ |
151 | ;; A constant value which fits into two instructions, each taking |
152 | ;; an arithmetic constant operand for one of the words. | |
153 | (define_predicate "arm_immediate_di_operand" | |
154 | (and (match_code "const_int,const_double") | |
155 | (match_test "arm_const_double_by_immediates (op)"))) | |
156 | ||
a657c98a RE |
157 | (define_predicate "arm_neg_immediate_operand" |
158 | (and (match_code "const_int") | |
159 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
160 | ||
161 | (define_predicate "arm_not_immediate_operand" | |
162 | (and (match_code "const_int") | |
163 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
164 | ||
f0c6475a | 165 | (define_predicate "const0_operand" |
d1fb6940 | 166 | (match_test "op == CONST0_RTX (mode)")) |
f0c6475a | 167 | |
a657c98a RE |
168 | ;; Something valid on the RHS of an ARM data-processing instruction |
169 | (define_predicate "arm_rhs_operand" | |
170 | (ior (match_operand 0 "s_register_operand") | |
171 | (match_operand 0 "arm_immediate_operand"))) | |
172 | ||
173 | (define_predicate "arm_rhsm_operand" | |
174 | (ior (match_operand 0 "arm_rhs_operand") | |
175 | (match_operand 0 "memory_operand"))) | |
176 | ||
fc02bcca JL |
177 | (define_predicate "const_int_I_operand" |
178 | (and (match_operand 0 "const_int_operand") | |
179 | (match_test "satisfies_constraint_I (op)"))) | |
180 | ||
181 | (define_predicate "const_int_M_operand" | |
182 | (and (match_operand 0 "const_int_operand") | |
183 | (match_test "satisfies_constraint_M (op)"))) | |
184 | ||
55cdadd5 AS |
185 | ;; This doesn't have to do much because the constant is already checked |
186 | ;; in the shift_operator predicate. | |
c29e2982 BS |
187 | (define_predicate "shift_amount_operand" |
188 | (ior (and (match_test "TARGET_ARM") | |
189 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 190 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 191 | |
36ba4aae IR |
192 | (define_predicate "const_neon_scalar_shift_amount_operand" |
193 | (and (match_code "const_int") | |
dec21bbc | 194 | (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) |
36ba4aae | 195 | |
56289ed2 SD |
196 | (define_predicate "ldrd_strd_offset_operand" |
197 | (and (match_operand 0 "const_int_operand") | |
198 | (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) | |
199 | ||
a657c98a RE |
200 | (define_predicate "arm_add_operand" |
201 | (ior (match_operand 0 "arm_rhs_operand") | |
202 | (match_operand 0 "arm_neg_immediate_operand"))) | |
203 | ||
44cd6810 WG |
204 | (define_predicate "arm_adddi_operand" |
205 | (ior (match_operand 0 "s_register_operand") | |
206 | (and (match_code "const_int") | |
207 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
208 | ||
a657c98a RE |
209 | (define_predicate "arm_addimm_operand" |
210 | (ior (match_operand 0 "arm_immediate_operand") | |
211 | (match_operand 0 "arm_neg_immediate_operand"))) | |
212 | ||
213 | (define_predicate "arm_not_operand" | |
214 | (ior (match_operand 0 "arm_rhs_operand") | |
215 | (match_operand 0 "arm_not_immediate_operand"))) | |
216 | ||
73160ba9 DJ |
217 | (define_predicate "arm_di_operand" |
218 | (ior (match_operand 0 "s_register_operand") | |
219 | (match_operand 0 "arm_immediate_di_operand"))) | |
220 | ||
a657c98a RE |
221 | ;; True if the operand is a memory reference which contains an |
222 | ;; offsettable address. | |
223 | (define_predicate "offsettable_memory_operand" | |
224 | (and (match_code "mem") | |
225 | (match_test | |
226 | "offsettable_address_p (reload_completed | reload_in_progress, | |
227 | mode, XEXP (op, 0))"))) | |
228 | ||
e6add59b RS |
229 | ;; True if the operand is a memory operand that does not have an |
230 | ;; automodified base register (and thus will not generate output reloads). | |
231 | (define_predicate "call_memory_operand" | |
232 | (and (match_code "mem") | |
233 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
234 | != RTX_AUTOINC") | |
235 | (match_operand 0 "memory_operand")))) | |
236 | ||
a657c98a | 237 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 238 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
239 | (match_test "(!CONSTANT_P (op) |
240 | && (true_regnum(op) == -1 | |
d435a4be | 241 | || (REG_P (op) |
a657c98a RE |
242 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) |
243 | ||
a657c98a RE |
244 | (define_predicate "vfp_compare_operand" |
245 | (ior (match_operand 0 "s_register_operand") | |
246 | (and (match_code "const_double") | |
247 | (match_test "arm_const_double_rtx (op)")))) | |
248 | ||
a657c98a RE |
249 | ;; True for valid index operands. |
250 | (define_predicate "index_operand" | |
251 | (ior (match_operand 0 "s_register_operand") | |
252 | (and (match_operand 0 "immediate_operand") | |
d435a4be | 253 | (match_test "(!CONST_INT_P (op) |
a657c98a RE |
254 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) |
255 | ||
256 | ;; True for operators that can be combined with a shift in ARM state. | |
257 | (define_special_predicate "shiftable_operator" | |
258 | (and (match_code "plus,minus,ior,xor,and") | |
259 | (match_test "mode == GET_MODE (op)"))) | |
260 | ||
95b97fac KT |
261 | (define_special_predicate "shiftable_operator_strict_it" |
262 | (and (match_code "plus,and") | |
263 | (match_test "mode == GET_MODE (op)"))) | |
264 | ||
c112cf2b | 265 | ;; True for logical binary operators. |
a657c98a RE |
266 | (define_special_predicate "logical_binary_operator" |
267 | (and (match_code "ior,xor,and") | |
268 | (match_test "mode == GET_MODE (op)"))) | |
269 | ||
37119410 BS |
270 | ;; True for commutative operators |
271 | (define_special_predicate "commutative_binary_operator" | |
272 | (and (match_code "ior,xor,and,plus") | |
273 | (match_test "mode == GET_MODE (op)"))) | |
274 | ||
a657c98a | 275 | ;; True for shift operators. |
55cdadd5 AS |
276 | ;; Notes: |
277 | ;; * mult is only permitted with a constant shift amount | |
278 | ;; * patterns that permit register shift amounts only in ARM mode use | |
279 | ;; shift_amount_operand, patterns that always allow registers do not, | |
280 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
281 | (define_special_predicate "shift_operator" |
282 | (and (ior (ior (and (match_code "mult") | |
283 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
284 | (and (match_code "rotate") | |
d435a4be | 285 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 286 | && (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
287 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
288 | (match_test "!CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 289 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
004d3809 RE |
290 | (match_test "mode == GET_MODE (op)"))) |
291 | ||
292 | (define_special_predicate "shift_nomul_operator" | |
293 | (and (ior (and (match_code "rotate") | |
294 | (match_test "CONST_INT_P (XEXP (op, 1)) | |
dec21bbc | 295 | && (UINTVAL (XEXP (op, 1))) < 32")) |
55cdadd5 | 296 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
d435a4be | 297 | (match_test "!CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 298 | || (UINTVAL (XEXP (op, 1))) < 32"))) |
a657c98a RE |
299 | (match_test "mode == GET_MODE (op)"))) |
300 | ||
655b30bf JB |
301 | ;; True for shift operators which can be used with saturation instructions. |
302 | (define_special_predicate "sat_shift_operator" | |
5d216c70 UW |
303 | (and (ior (and (match_code "mult") |
304 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
305 | (and (match_code "ashift,ashiftrt") | |
d435a4be | 306 | (match_test "CONST_INT_P (XEXP (op, 1)) |
dec21bbc | 307 | && (UINTVAL (XEXP (op, 1)) < 32)"))) |
655b30bf JB |
308 | (match_test "mode == GET_MODE (op)"))) |
309 | ||
c29e2982 BS |
310 | ;; True for MULT, to identify which variant of shift_operator is in use. |
311 | (define_special_predicate "mult_operator" | |
312 | (match_code "mult")) | |
313 | ||
5b3e6663 PB |
314 | ;; True for operators that have 16-bit thumb variants. */ |
315 | (define_special_predicate "thumb_16bit_operator" | |
316 | (match_code "plus,minus,and,ior,xor")) | |
317 | ||
a657c98a RE |
318 | ;; True for EQ & NE |
319 | (define_special_predicate "equality_operator" | |
320 | (match_code "eq,ne")) | |
321 | ||
f90b7a5a PB |
322 | ;; True for integer comparisons and, if FP is active, for comparisons |
323 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
324 | (define_special_predicate "expandable_comparison_operator" |
325 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
326 | unordered,ordered,unlt,unle,unge,ungt")) | |
327 | ||
328 | ;; Likewise, but only accept comparisons that are directly supported | |
329 | ;; by ARM condition codes. | |
a657c98a | 330 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 331 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 332 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 333 | |
ac4bf407 KT |
334 | ;; Likewise, but don't ignore the mode. |
335 | ;; RTL SET operations require their operands source and destination have | |
336 | ;; the same modes, so we can't ignore the modes there. See PR target/69161. | |
337 | (define_predicate "arm_comparison_operator_mode" | |
338 | (and (match_operand 0 "expandable_comparison_operator") | |
339 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | |
340 | ||
f0c6475a BS |
341 | (define_special_predicate "lt_ge_comparison_operator" |
342 | (match_code "lt,ge")) | |
343 | ||
24990170 RE |
344 | ;; Match a "borrow" operation for use with SBC. The precise code will |
345 | ;; depend on the form of the comparison. This is generally the inverse of | |
346 | ;; a carry operation, since the logic of SBC uses "not borrow" in it's | |
347 | ;; calculation. | |
348 | (define_special_predicate "arm_borrow_operation" | |
349 | (match_code "geu,ltu") | |
350 | { | |
351 | if (XEXP (op, 1) != const0_rtx) | |
352 | return false; | |
353 | rtx op0 = XEXP (op, 0); | |
354 | if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | |
355 | return false; | |
356 | machine_mode ccmode = GET_MODE (op0); | |
357 | if (ccmode == CC_Cmode) | |
358 | return GET_CODE (op) == GEU; | |
359 | else if (ccmode == CCmode) | |
360 | return GET_CODE (op) == LTU; | |
361 | return false; | |
362 | } | |
363 | ) | |
364 | ||
a5a4c20a KT |
365 | ;; The vsel instruction only accepts the ARM condition codes listed below. |
366 | (define_special_predicate "arm_vsel_comparison_operator" | |
367 | (and (match_operand 0 "expandable_comparison_operator") | |
368 | (match_test "maybe_get_arm_condition_code (op) == ARM_GE | |
369 | || maybe_get_arm_condition_code (op) == ARM_GT | |
370 | || maybe_get_arm_condition_code (op) == ARM_EQ | |
371 | || maybe_get_arm_condition_code (op) == ARM_VS | |
372 | || maybe_get_arm_condition_code (op) == ARM_LT | |
373 | || maybe_get_arm_condition_code (op) == ARM_LE | |
374 | || maybe_get_arm_condition_code (op) == ARM_NE | |
375 | || maybe_get_arm_condition_code (op) == ARM_VC"))) | |
376 | ||
1572e697 KT |
377 | (define_special_predicate "arm_cond_move_operator" |
378 | (if_then_else (match_test "arm_restrict_it") | |
c8d61ab8 TP |
379 | (and (match_test "TARGET_VFP5") |
380 | (match_operand 0 "arm_vsel_comparison_operator")) | |
381 | (match_operand 0 "expandable_comparison_operator"))) | |
1572e697 | 382 | |
906668bb BS |
383 | (define_special_predicate "noov_comparison_operator" |
384 | (match_code "lt,ge,eq,ne")) | |
385 | ||
a657c98a RE |
386 | (define_special_predicate "minmax_operator" |
387 | (and (match_code "smin,smax,umin,umax") | |
388 | (match_test "mode == GET_MODE (op)"))) | |
389 | ||
390 | (define_special_predicate "cc_register" | |
391 | (and (match_code "reg") | |
392 | (and (match_test "REGNO (op) == CC_REGNUM") | |
393 | (ior (match_test "mode == GET_MODE (op)") | |
394 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
395 | ||
396 | (define_special_predicate "dominant_cc_register" | |
397 | (match_code "reg") | |
398 | { | |
399 | if (mode == VOIDmode) | |
400 | { | |
401 | mode = GET_MODE (op); | |
402 | ||
403 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
404 | return false; | |
405 | } | |
406 | ||
407 | return (cc_register (op, mode) | |
408 | && (mode == CC_DNEmode | |
409 | || mode == CC_DEQmode | |
410 | || mode == CC_DLEmode | |
411 | || mode == CC_DLTmode | |
412 | || mode == CC_DGEmode | |
413 | || mode == CC_DGTmode | |
414 | || mode == CC_DLEUmode | |
415 | || mode == CC_DLTUmode | |
416 | || mode == CC_DGEUmode | |
417 | || mode == CC_DGTUmode)); | |
418 | }) | |
419 | ||
12286f25 TP |
420 | ;; Any register, including CC |
421 | (define_predicate "cc_register_operand" | |
422 | (and (match_code "reg") | |
423 | (ior (match_operand 0 "s_register_operand") | |
424 | (match_operand 0 "cc_register")))) | |
425 | ||
a657c98a RE |
426 | (define_special_predicate "arm_extendqisi_mem_op" |
427 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
428 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
429 | XEXP (op, 0), | |
430 | SIGN_EXTEND, | |
431 | 0) | |
432 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 433 | |
01577df7 RE |
434 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
435 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
436 | (match_operand 0 "s_register_operand"))) | |
437 | ||
a657c98a RE |
438 | (define_predicate "power_of_two_operand" |
439 | (match_code "const_int") | |
440 | { | |
29b40d79 | 441 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
442 | |
443 | return value != 0 && (value & (value - 1)) == 0; | |
444 | }) | |
445 | ||
446 | (define_predicate "nonimmediate_di_operand" | |
447 | (match_code "reg,subreg,mem") | |
448 | { | |
449 | if (s_register_operand (op, mode)) | |
450 | return true; | |
451 | ||
452 | if (GET_CODE (op) == SUBREG) | |
453 | op = SUBREG_REG (op); | |
454 | ||
d435a4be | 455 | return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); |
a657c98a RE |
456 | }) |
457 | ||
458 | (define_predicate "di_operand" | |
459 | (ior (match_code "const_int,const_double") | |
460 | (and (match_code "reg,subreg,mem") | |
461 | (match_operand 0 "nonimmediate_di_operand")))) | |
462 | ||
463 | (define_predicate "nonimmediate_soft_df_operand" | |
464 | (match_code "reg,subreg,mem") | |
465 | { | |
466 | if (s_register_operand (op, mode)) | |
467 | return true; | |
468 | ||
469 | if (GET_CODE (op) == SUBREG) | |
470 | op = SUBREG_REG (op); | |
471 | ||
d435a4be | 472 | return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); |
a657c98a RE |
473 | }) |
474 | ||
475 | (define_predicate "soft_df_operand" | |
476 | (ior (match_code "const_double") | |
477 | (and (match_code "reg,subreg,mem") | |
478 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
479 | ||
8d33eae8 TP |
480 | ;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this |
481 | ;; forbids constant loaded via literal pool iff literal pools are disabled. | |
482 | (define_predicate "hard_sf_operand" | |
483 | (and (match_operand 0 "general_operand") | |
484 | (ior (not (match_code "const_double")) | |
485 | (not (match_test "arm_disable_literal_pool")) | |
486 | (match_test "satisfies_constraint_Dv (op)")))) | |
487 | ||
488 | ;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in | |
489 | ;; movdf_soft_insn, this forbids constant loaded via literal pool iff | |
490 | ;; literal pools are disabled. | |
491 | (define_predicate "hard_df_operand" | |
492 | (and (match_operand 0 "soft_df_operand") | |
493 | (ior (not (match_code "const_double")) | |
494 | (not (match_test "arm_disable_literal_pool")) | |
495 | (match_test "satisfies_constraint_Dy (op)") | |
496 | (match_test "satisfies_constraint_G (op)")))) | |
497 | ||
a657c98a RE |
498 | (define_special_predicate "load_multiple_operation" |
499 | (match_code "parallel") | |
500 | { | |
fb40241d IB |
501 | return ldm_stm_operation_p (op, /*load=*/true, SImode, |
502 | /*consecutive=*/false, | |
503 | /*return_pc=*/false); | |
a657c98a RE |
504 | }) |
505 | ||
506 | (define_special_predicate "store_multiple_operation" | |
507 | (match_code "parallel") | |
508 | { | |
fb40241d IB |
509 | return ldm_stm_operation_p (op, /*load=*/false, SImode, |
510 | /*consecutive=*/false, | |
511 | /*return_pc=*/false); | |
a657c98a RE |
512 | }) |
513 | ||
3aee1982 IB |
514 | (define_special_predicate "pop_multiple_return" |
515 | (match_code "parallel") | |
516 | { | |
517 | return ldm_stm_operation_p (op, /*load=*/true, SImode, | |
518 | /*consecutive=*/false, | |
519 | /*return_pc=*/true); | |
520 | }) | |
521 | ||
4b2678f8 IB |
522 | (define_special_predicate "pop_multiple_fp" |
523 | (match_code "parallel") | |
524 | { | |
525 | return ldm_stm_operation_p (op, /*load=*/true, DFmode, | |
526 | /*consecutive=*/true, | |
527 | /*return_pc=*/false); | |
528 | }) | |
529 | ||
a657c98a RE |
530 | (define_special_predicate "multi_register_push" |
531 | (match_code "parallel") | |
532 | { | |
533 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
534 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
535 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
536 | return false; | |
537 | ||
538 | return true; | |
539 | }) | |
540 | ||
d018b46e RH |
541 | (define_predicate "push_mult_memory_operand" |
542 | (match_code "mem") | |
543 | { | |
544 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
545 | any point in testing for thumb1 specially? All of the variants | |
546 | use the same form. */ | |
547 | if (TARGET_THUMB1) | |
548 | { | |
549 | /* ??? No attempt is made to represent STMIA, or validate that | |
550 | the stack adjustment matches the register count. This is | |
551 | true of the ARM/Thumb2 path as well. */ | |
552 | rtx x = XEXP (op, 0); | |
553 | if (GET_CODE (x) != PRE_MODIFY) | |
554 | return false; | |
555 | if (XEXP (x, 0) != stack_pointer_rtx) | |
556 | return false; | |
557 | x = XEXP (x, 1); | |
558 | if (GET_CODE (x) != PLUS) | |
559 | return false; | |
560 | if (XEXP (x, 0) != stack_pointer_rtx) | |
561 | return false; | |
562 | return CONST_INT_P (XEXP (x, 1)); | |
563 | } | |
564 | ||
565 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
566 | return memory_operand (op, mode); | |
567 | }) | |
568 | ||
a657c98a RE |
569 | ;;------------------------------------------------------------------------- |
570 | ;; | |
571 | ;; Thumb predicates | |
572 | ;; | |
573 | ||
5b3e6663 | 574 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
575 | (ior (and (match_code "reg,subreg") |
576 | (match_operand 0 "s_register_operand")) | |
577 | (and (match_code "const_int") | |
dec21bbc | 578 | (match_test "(UINTVAL (op)) < 256")))) |
a657c98a | 579 | |
5b3e6663 | 580 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
581 | (and (match_code "const_int") |
582 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
583 | ||
584 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
585 | ;; condition code register. Prior to reload we only accept a | |
586 | ;; register. After reload we have to be able to handle memory as | |
587 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
588 | ;; handle output-reloads on jump insns. | |
589 | ||
590 | ;; We could possibly handle mem before reload as well, but that might | |
591 | ;; complicate things with the need to handle increment | |
592 | ;; side-effects. | |
593 | (define_predicate "thumb_cbrch_target_operand" | |
594 | (and (match_code "reg,subreg,mem") | |
595 | (ior (match_operand 0 "s_register_operand") | |
596 | (and (match_test "reload_in_progress || reload_completed") | |
597 | (match_operand 0 "memory_operand"))))) | |
598 | ||
599 | ;;------------------------------------------------------------------------- | |
600 | ;; | |
8fd03515 | 601 | ;; iWMMXt predicates |
dae840fc | 602 | ;; |
8fd03515 XQ |
603 | |
604 | (define_predicate "imm_or_reg_operand" | |
605 | (ior (match_operand 0 "immediate_operand") | |
606 | (match_operand 0 "register_operand"))) | |
a657c98a | 607 | |
88f77cba JB |
608 | ;; Neon predicates |
609 | ||
610 | (define_predicate "const_multiple_of_8_operand" | |
611 | (match_code "const_int") | |
612 | { | |
613 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
614 | return (val & 7) == 0; | |
615 | }) | |
616 | ||
617 | (define_predicate "imm_for_neon_mov_operand" | |
00a3a76a | 618 | (match_code "const_vector,const_int") |
88f77cba JB |
619 | { |
620 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
621 | }) | |
622 | ||
31a0c825 DP |
623 | (define_predicate "imm_for_neon_lshift_operand" |
624 | (match_code "const_vector") | |
625 | { | |
626 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
627 | }) | |
628 | ||
629 | (define_predicate "imm_for_neon_rshift_operand" | |
630 | (match_code "const_vector") | |
631 | { | |
632 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
633 | }) | |
634 | ||
635 | (define_predicate "imm_lshift_or_reg_neon" | |
636 | (ior (match_operand 0 "s_register_operand") | |
637 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
638 | ||
639 | (define_predicate "imm_rshift_or_reg_neon" | |
640 | (ior (match_operand 0 "s_register_operand") | |
641 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
642 | ||
73160ba9 DJ |
643 | ;; Predicates for named expanders that overlap multiple ISAs. |
644 | ||
645 | (define_predicate "cmpdi_operand" | |
dae840fc RE |
646 | (and (match_test "TARGET_32BIT") |
647 | (match_operand 0 "arm_di_operand"))) | |
88f77cba | 648 | |
999a9cc5 MS |
649 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
650 | (define_predicate "arm_sync_memory_operand" | |
651 | (and (match_operand 0 "memory_operand") | |
652 | (match_code "reg" "0"))) | |
653 | ||
46b57af1 TB |
654 | ;; Predicates for parallel expanders based on mode. |
655 | (define_special_predicate "vect_par_constant_high" | |
656 | (match_code "parallel") | |
657 | { | |
93c590ee | 658 | return arm_simd_check_vect_par_cnst_half_p (op, mode, true); |
46b57af1 TB |
659 | }) |
660 | ||
661 | (define_special_predicate "vect_par_constant_low" | |
662 | (match_code "parallel") | |
663 | { | |
93c590ee | 664 | return arm_simd_check_vect_par_cnst_half_p (op, mode, false); |
46b57af1 | 665 | }) |
6308e208 | 666 | |
7f3d8f56 RR |
667 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
668 | (and (match_code "const_double") | |
00ea1506 RE |
669 | (match_test "TARGET_32BIT |
670 | && vfp3_const_double_for_fract_bits (op)"))) | |
c75d51aa RL |
671 | |
672 | (define_predicate "const_double_vcvt_power_of_two" | |
673 | (and (match_code "const_double") | |
00ea1506 | 674 | (match_test "TARGET_32BIT |
85f5231d | 675 | && vfp3_const_double_for_bits (op) > 0"))) |
7f3d8f56 | 676 | |
12c4ecb1 | 677 | (define_predicate "neon_struct_operand" |
6308e208 | 678 | (and (match_code "mem") |
33255ae3 | 679 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) |
9a1ea4b9 | 680 | |
33255ae3 JB |
681 | (define_predicate "neon_permissive_struct_operand" |
682 | (and (match_code "mem") | |
683 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) | |
684 | ||
685 | (define_predicate "neon_perm_struct_or_reg_operand" | |
686 | (ior (match_operand 0 "neon_permissive_struct_operand") | |
12c4ecb1 RS |
687 | (match_operand 0 "s_register_operand"))) |
688 | ||
9a1ea4b9 RR |
689 | (define_special_predicate "add_operator" |
690 | (match_code "plus")) | |
18f0fe6b RH |
691 | |
692 | (define_predicate "mem_noofs_operand" | |
693 | (and (match_code "mem") | |
694 | (match_code "reg" "0"))) | |
9adcfa3c RR |
695 | |
696 | (define_predicate "call_insn_operand" | |
10432733 JW |
697 | (ior (and (match_code "symbol_ref") |
698 | (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) | |
9adcfa3c | 699 | (match_operand 0 "s_register_operand"))) |
70cdb21e BE |
700 | |
701 | (define_special_predicate "aligned_operand" | |
702 | (ior (not (match_code "mem")) | |
703 | (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))) |