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a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
d652f226 | 2 | ;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
29 | return (GET_CODE (op) == REG | |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
34 | ;; Any hard register. | |
35 | (define_predicate "arm_hard_register_operand" | |
36 | (match_code "reg") | |
37 | { | |
38 | return REGNO (op) < FIRST_PSEUDO_REGISTER; | |
39 | }) | |
40 | ||
5b3e6663 PB |
41 | ;; A low register. |
42 | (define_predicate "low_register_operand" | |
43 | (and (match_code "reg") | |
44 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
45 | ||
46 | ;; A low register or const_int. | |
47 | (define_predicate "low_reg_or_int_operand" | |
48 | (ior (match_code "const_int") | |
49 | (match_operand 0 "low_register_operand"))) | |
50 | ||
a657c98a RE |
51 | ;; Any core register, or any pseudo. */ |
52 | (define_predicate "arm_general_register_operand" | |
53 | (match_code "reg,subreg") | |
54 | { | |
55 | if (GET_CODE (op) == SUBREG) | |
56 | op = SUBREG_REG (op); | |
57 | ||
58 | return (GET_CODE (op) == REG | |
59 | && (REGNO (op) <= LAST_ARM_REGNUM | |
60 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
61 | }) | |
62 | ||
63 | (define_predicate "f_register_operand" | |
64 | (match_code "reg,subreg") | |
65 | { | |
66 | if (GET_CODE (op) == SUBREG) | |
67 | op = SUBREG_REG (op); | |
68 | ||
69 | /* We don't consider registers whose class is NO_REGS | |
70 | to be a register operand. */ | |
71 | return (GET_CODE (op) == REG | |
72 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
73 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); | |
74 | }) | |
75 | ||
4e6f5666 JZ |
76 | (define_predicate "vfp_register_operand" |
77 | (match_code "reg,subreg") | |
78 | { | |
79 | if (GET_CODE (op) == SUBREG) | |
80 | op = SUBREG_REG (op); | |
81 | ||
82 | /* We don't consider registers whose class is NO_REGS | |
83 | to be a register operand. */ | |
84 | return (GET_CODE (op) == REG | |
85 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
34db4735 | 86 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
87 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
88 | || (TARGET_VFPD32 | |
89 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
90 | }) | |
91 | ||
fa01135d RE |
92 | (define_special_predicate "subreg_lowpart_operator" |
93 | (and (match_code "subreg") | |
94 | (match_test "subreg_lowpart_p (op)"))) | |
95 | ||
a657c98a RE |
96 | ;; Reg, subreg(reg) or const_int. |
97 | (define_predicate "reg_or_int_operand" | |
98 | (ior (match_code "const_int") | |
99 | (match_operand 0 "s_register_operand"))) | |
100 | ||
101 | (define_predicate "arm_immediate_operand" | |
102 | (and (match_code "const_int") | |
103 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
104 | ||
73160ba9 DJ |
105 | ;; A constant value which fits into two instructions, each taking |
106 | ;; an arithmetic constant operand for one of the words. | |
107 | (define_predicate "arm_immediate_di_operand" | |
108 | (and (match_code "const_int,const_double") | |
109 | (match_test "arm_const_double_by_immediates (op)"))) | |
110 | ||
a657c98a RE |
111 | (define_predicate "arm_neg_immediate_operand" |
112 | (and (match_code "const_int") | |
113 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
114 | ||
115 | (define_predicate "arm_not_immediate_operand" | |
116 | (and (match_code "const_int") | |
117 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
118 | ||
f0c6475a BS |
119 | (define_predicate "const0_operand" |
120 | (and (match_code "const_int") | |
121 | (match_test "INTVAL (op) == 0"))) | |
122 | ||
a657c98a RE |
123 | ;; Something valid on the RHS of an ARM data-processing instruction |
124 | (define_predicate "arm_rhs_operand" | |
125 | (ior (match_operand 0 "s_register_operand") | |
126 | (match_operand 0 "arm_immediate_operand"))) | |
127 | ||
128 | (define_predicate "arm_rhsm_operand" | |
129 | (ior (match_operand 0 "arm_rhs_operand") | |
130 | (match_operand 0 "memory_operand"))) | |
131 | ||
55cdadd5 AS |
132 | ;; This doesn't have to do much because the constant is already checked |
133 | ;; in the shift_operator predicate. | |
c29e2982 BS |
134 | (define_predicate "shift_amount_operand" |
135 | (ior (and (match_test "TARGET_ARM") | |
136 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 137 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 138 | |
36ba4aae IR |
139 | (define_predicate "const_neon_scalar_shift_amount_operand" |
140 | (and (match_code "const_int") | |
141 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode) | |
142 | && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0"))) | |
143 | ||
a657c98a RE |
144 | (define_predicate "arm_add_operand" |
145 | (ior (match_operand 0 "arm_rhs_operand") | |
146 | (match_operand 0 "arm_neg_immediate_operand"))) | |
147 | ||
148 | (define_predicate "arm_addimm_operand" | |
149 | (ior (match_operand 0 "arm_immediate_operand") | |
150 | (match_operand 0 "arm_neg_immediate_operand"))) | |
151 | ||
152 | (define_predicate "arm_not_operand" | |
153 | (ior (match_operand 0 "arm_rhs_operand") | |
154 | (match_operand 0 "arm_not_immediate_operand"))) | |
155 | ||
73160ba9 DJ |
156 | (define_predicate "arm_di_operand" |
157 | (ior (match_operand 0 "s_register_operand") | |
158 | (match_operand 0 "arm_immediate_di_operand"))) | |
159 | ||
a657c98a RE |
160 | ;; True if the operand is a memory reference which contains an |
161 | ;; offsettable address. | |
162 | (define_predicate "offsettable_memory_operand" | |
163 | (and (match_code "mem") | |
164 | (match_test | |
165 | "offsettable_address_p (reload_completed | reload_in_progress, | |
166 | mode, XEXP (op, 0))"))) | |
167 | ||
e6add59b RS |
168 | ;; True if the operand is a memory operand that does not have an |
169 | ;; automodified base register (and thus will not generate output reloads). | |
170 | (define_predicate "call_memory_operand" | |
171 | (and (match_code "mem") | |
172 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
173 | != RTX_AUTOINC") | |
174 | (match_operand 0 "memory_operand")))) | |
175 | ||
a657c98a | 176 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 177 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
178 | (match_test "(!CONSTANT_P (op) |
179 | && (true_regnum(op) == -1 | |
180 | || (GET_CODE (op) == REG | |
181 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) | |
182 | ||
183 | ;; True for valid operands for the rhs of an floating point insns. | |
184 | ;; Allows regs or certain consts on FPA, just regs for everything else. | |
185 | (define_predicate "arm_float_rhs_operand" | |
186 | (ior (match_operand 0 "s_register_operand") | |
187 | (and (match_code "const_double") | |
188 | (match_test "TARGET_FPA && arm_const_double_rtx (op)")))) | |
189 | ||
190 | (define_predicate "arm_float_add_operand" | |
191 | (ior (match_operand 0 "arm_float_rhs_operand") | |
192 | (and (match_code "const_double") | |
193 | (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)")))) | |
194 | ||
195 | (define_predicate "vfp_compare_operand" | |
196 | (ior (match_operand 0 "s_register_operand") | |
197 | (and (match_code "const_double") | |
198 | (match_test "arm_const_double_rtx (op)")))) | |
199 | ||
200 | (define_predicate "arm_float_compare_operand" | |
201 | (if_then_else (match_test "TARGET_VFP") | |
202 | (match_operand 0 "vfp_compare_operand") | |
203 | (match_operand 0 "arm_float_rhs_operand"))) | |
204 | ||
205 | ;; True for valid index operands. | |
206 | (define_predicate "index_operand" | |
207 | (ior (match_operand 0 "s_register_operand") | |
208 | (and (match_operand 0 "immediate_operand") | |
209 | (match_test "(GET_CODE (op) != CONST_INT | |
210 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) | |
211 | ||
212 | ;; True for operators that can be combined with a shift in ARM state. | |
213 | (define_special_predicate "shiftable_operator" | |
214 | (and (match_code "plus,minus,ior,xor,and") | |
215 | (match_test "mode == GET_MODE (op)"))) | |
216 | ||
c112cf2b | 217 | ;; True for logical binary operators. |
a657c98a RE |
218 | (define_special_predicate "logical_binary_operator" |
219 | (and (match_code "ior,xor,and") | |
220 | (match_test "mode == GET_MODE (op)"))) | |
221 | ||
37119410 BS |
222 | ;; True for commutative operators |
223 | (define_special_predicate "commutative_binary_operator" | |
224 | (and (match_code "ior,xor,and,plus") | |
225 | (match_test "mode == GET_MODE (op)"))) | |
226 | ||
a657c98a | 227 | ;; True for shift operators. |
55cdadd5 AS |
228 | ;; Notes: |
229 | ;; * mult is only permitted with a constant shift amount | |
230 | ;; * patterns that permit register shift amounts only in ARM mode use | |
231 | ;; shift_amount_operand, patterns that always allow registers do not, | |
232 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
233 | (define_special_predicate "shift_operator" |
234 | (and (ior (ior (and (match_code "mult") | |
235 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
236 | (and (match_code "rotate") | |
237 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
238 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
55cdadd5 AS |
239 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
240 | (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT | |
241 | || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
a657c98a RE |
242 | (match_test "mode == GET_MODE (op)"))) |
243 | ||
655b30bf JB |
244 | ;; True for shift operators which can be used with saturation instructions. |
245 | (define_special_predicate "sat_shift_operator" | |
5d216c70 UW |
246 | (and (ior (and (match_code "mult") |
247 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
248 | (and (match_code "ashift,ashiftrt") | |
249 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
250 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) | |
655b30bf JB |
251 | (match_test "mode == GET_MODE (op)"))) |
252 | ||
c29e2982 BS |
253 | ;; True for MULT, to identify which variant of shift_operator is in use. |
254 | (define_special_predicate "mult_operator" | |
255 | (match_code "mult")) | |
256 | ||
5b3e6663 PB |
257 | ;; True for operators that have 16-bit thumb variants. */ |
258 | (define_special_predicate "thumb_16bit_operator" | |
259 | (match_code "plus,minus,and,ior,xor")) | |
260 | ||
a657c98a RE |
261 | ;; True for EQ & NE |
262 | (define_special_predicate "equality_operator" | |
263 | (match_code "eq,ne")) | |
264 | ||
f90b7a5a PB |
265 | ;; True for integer comparisons and, if FP is active, for comparisons |
266 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
267 | (define_special_predicate "expandable_comparison_operator" |
268 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
269 | unordered,ordered,unlt,unle,unge,ungt")) | |
270 | ||
271 | ;; Likewise, but only accept comparisons that are directly supported | |
272 | ;; by ARM condition codes. | |
a657c98a | 273 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 274 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 275 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 276 | |
f0c6475a BS |
277 | (define_special_predicate "lt_ge_comparison_operator" |
278 | (match_code "lt,ge")) | |
279 | ||
906668bb BS |
280 | (define_special_predicate "noov_comparison_operator" |
281 | (match_code "lt,ge,eq,ne")) | |
282 | ||
a657c98a RE |
283 | (define_special_predicate "minmax_operator" |
284 | (and (match_code "smin,smax,umin,umax") | |
285 | (match_test "mode == GET_MODE (op)"))) | |
286 | ||
287 | (define_special_predicate "cc_register" | |
288 | (and (match_code "reg") | |
289 | (and (match_test "REGNO (op) == CC_REGNUM") | |
290 | (ior (match_test "mode == GET_MODE (op)") | |
291 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
292 | ||
293 | (define_special_predicate "dominant_cc_register" | |
294 | (match_code "reg") | |
295 | { | |
296 | if (mode == VOIDmode) | |
297 | { | |
298 | mode = GET_MODE (op); | |
299 | ||
300 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
301 | return false; | |
302 | } | |
303 | ||
304 | return (cc_register (op, mode) | |
305 | && (mode == CC_DNEmode | |
306 | || mode == CC_DEQmode | |
307 | || mode == CC_DLEmode | |
308 | || mode == CC_DLTmode | |
309 | || mode == CC_DGEmode | |
310 | || mode == CC_DGTmode | |
311 | || mode == CC_DLEUmode | |
312 | || mode == CC_DLTUmode | |
313 | || mode == CC_DGEUmode | |
314 | || mode == CC_DGTUmode)); | |
315 | }) | |
316 | ||
317 | (define_special_predicate "arm_extendqisi_mem_op" | |
318 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
319 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
320 | XEXP (op, 0), | |
321 | SIGN_EXTEND, | |
322 | 0) | |
323 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 324 | |
01577df7 RE |
325 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
326 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
327 | (match_operand 0 "s_register_operand"))) | |
328 | ||
a657c98a RE |
329 | (define_predicate "power_of_two_operand" |
330 | (match_code "const_int") | |
331 | { | |
29b40d79 | 332 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
333 | |
334 | return value != 0 && (value & (value - 1)) == 0; | |
335 | }) | |
336 | ||
337 | (define_predicate "nonimmediate_di_operand" | |
338 | (match_code "reg,subreg,mem") | |
339 | { | |
340 | if (s_register_operand (op, mode)) | |
341 | return true; | |
342 | ||
343 | if (GET_CODE (op) == SUBREG) | |
344 | op = SUBREG_REG (op); | |
345 | ||
346 | return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); | |
347 | }) | |
348 | ||
349 | (define_predicate "di_operand" | |
350 | (ior (match_code "const_int,const_double") | |
351 | (and (match_code "reg,subreg,mem") | |
352 | (match_operand 0 "nonimmediate_di_operand")))) | |
353 | ||
354 | (define_predicate "nonimmediate_soft_df_operand" | |
355 | (match_code "reg,subreg,mem") | |
356 | { | |
357 | if (s_register_operand (op, mode)) | |
358 | return true; | |
359 | ||
360 | if (GET_CODE (op) == SUBREG) | |
361 | op = SUBREG_REG (op); | |
362 | ||
363 | return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); | |
364 | }) | |
365 | ||
366 | (define_predicate "soft_df_operand" | |
367 | (ior (match_code "const_double") | |
368 | (and (match_code "reg,subreg,mem") | |
369 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
370 | ||
a657c98a RE |
371 | (define_special_predicate "load_multiple_operation" |
372 | (match_code "parallel") | |
373 | { | |
374 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
37119410 | 375 | unsigned dest_regno; |
a657c98a RE |
376 | rtx src_addr; |
377 | HOST_WIDE_INT i = 1, base = 0; | |
37119410 | 378 | HOST_WIDE_INT offset = 0; |
a657c98a | 379 | rtx elt; |
37119410 BS |
380 | bool addr_reg_loaded = false; |
381 | bool update = false; | |
a657c98a RE |
382 | |
383 | if (count <= 1 | |
37119410 BS |
384 | || GET_CODE (XVECEXP (op, 0, 0)) != SET |
385 | || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))) | |
a657c98a RE |
386 | return false; |
387 | ||
388 | /* Check to see if this might be a write-back. */ | |
389 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) | |
390 | { | |
391 | i++; | |
392 | base = 1; | |
37119410 | 393 | update = true; |
a657c98a RE |
394 | |
395 | /* Now check it more carefully. */ | |
396 | if (GET_CODE (SET_DEST (elt)) != REG | |
397 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
398 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
399 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) | |
400 | return false; | |
401 | } | |
402 | ||
403 | /* Perform a quick check so we don't blow up below. */ | |
404 | if (count <= i | |
405 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
406 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
407 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
408 | return false; | |
409 | ||
410 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
411 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
37119410 BS |
412 | if (GET_CODE (src_addr) == PLUS) |
413 | { | |
414 | if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT) | |
415 | return false; | |
416 | offset = INTVAL (XEXP (src_addr, 1)); | |
417 | src_addr = XEXP (src_addr, 0); | |
418 | } | |
419 | if (!REG_P (src_addr)) | |
420 | return false; | |
a657c98a RE |
421 | |
422 | for (; i < count; i++) | |
423 | { | |
424 | elt = XVECEXP (op, 0, i); | |
425 | ||
426 | if (GET_CODE (elt) != SET | |
427 | || GET_CODE (SET_DEST (elt)) != REG | |
428 | || GET_MODE (SET_DEST (elt)) != SImode | |
37119410 | 429 | || REGNO (SET_DEST (elt)) <= dest_regno |
a657c98a RE |
430 | || GET_CODE (SET_SRC (elt)) != MEM |
431 | || GET_MODE (SET_SRC (elt)) != SImode | |
37119410 BS |
432 | || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS |
433 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
434 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
435 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4) | |
436 | && (!REG_P (XEXP (SET_SRC (elt), 0)) | |
437 | || offset + (i - base) * 4 != 0))) | |
a657c98a | 438 | return false; |
37119410 BS |
439 | dest_regno = REGNO (SET_DEST (elt)); |
440 | if (dest_regno == REGNO (src_addr)) | |
441 | addr_reg_loaded = true; | |
a657c98a | 442 | } |
37119410 BS |
443 | /* For Thumb, we only have updating instructions. If the pattern does |
444 | not describe an update, it must be because the address register is | |
445 | in the list of loaded registers - on the hardware, this has the effect | |
446 | of overriding the update. */ | |
447 | if (update && addr_reg_loaded) | |
448 | return false; | |
449 | if (TARGET_THUMB1) | |
450 | return update || addr_reg_loaded; | |
a657c98a RE |
451 | return true; |
452 | }) | |
453 | ||
454 | (define_special_predicate "store_multiple_operation" | |
455 | (match_code "parallel") | |
456 | { | |
457 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
37119410 | 458 | unsigned src_regno; |
a657c98a | 459 | rtx dest_addr; |
37119410 | 460 | HOST_WIDE_INT i = 1, base = 0, offset = 0; |
a657c98a RE |
461 | rtx elt; |
462 | ||
463 | if (count <= 1 | |
464 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
465 | return false; | |
466 | ||
467 | /* Check to see if this might be a write-back. */ | |
468 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) | |
469 | { | |
470 | i++; | |
471 | base = 1; | |
472 | ||
473 | /* Now check it more carefully. */ | |
474 | if (GET_CODE (SET_DEST (elt)) != REG | |
475 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
476 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
477 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) | |
478 | return false; | |
479 | } | |
480 | ||
481 | /* Perform a quick check so we don't blow up below. */ | |
482 | if (count <= i | |
483 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
484 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
485 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
486 | return false; | |
487 | ||
488 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
489 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
490 | ||
37119410 BS |
491 | if (GET_CODE (dest_addr) == PLUS) |
492 | { | |
493 | if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT) | |
494 | return false; | |
495 | offset = INTVAL (XEXP (dest_addr, 1)); | |
496 | dest_addr = XEXP (dest_addr, 0); | |
497 | } | |
498 | if (!REG_P (dest_addr)) | |
499 | return false; | |
500 | ||
a657c98a RE |
501 | for (; i < count; i++) |
502 | { | |
503 | elt = XVECEXP (op, 0, i); | |
504 | ||
505 | if (GET_CODE (elt) != SET | |
506 | || GET_CODE (SET_SRC (elt)) != REG | |
507 | || GET_MODE (SET_SRC (elt)) != SImode | |
37119410 | 508 | || REGNO (SET_SRC (elt)) <= src_regno |
a657c98a RE |
509 | || GET_CODE (SET_DEST (elt)) != MEM |
510 | || GET_MODE (SET_DEST (elt)) != SImode | |
37119410 BS |
511 | || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS |
512 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
513 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
514 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4) | |
515 | && (!REG_P (XEXP (SET_DEST (elt), 0)) | |
516 | || offset + (i - base) * 4 != 0))) | |
a657c98a | 517 | return false; |
37119410 | 518 | src_regno = REGNO (SET_SRC (elt)); |
a657c98a RE |
519 | } |
520 | ||
521 | return true; | |
522 | }) | |
523 | ||
524 | (define_special_predicate "multi_register_push" | |
525 | (match_code "parallel") | |
526 | { | |
527 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
528 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
529 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
530 | return false; | |
531 | ||
532 | return true; | |
533 | }) | |
534 | ||
d018b46e RH |
535 | (define_predicate "push_mult_memory_operand" |
536 | (match_code "mem") | |
537 | { | |
538 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
539 | any point in testing for thumb1 specially? All of the variants | |
540 | use the same form. */ | |
541 | if (TARGET_THUMB1) | |
542 | { | |
543 | /* ??? No attempt is made to represent STMIA, or validate that | |
544 | the stack adjustment matches the register count. This is | |
545 | true of the ARM/Thumb2 path as well. */ | |
546 | rtx x = XEXP (op, 0); | |
547 | if (GET_CODE (x) != PRE_MODIFY) | |
548 | return false; | |
549 | if (XEXP (x, 0) != stack_pointer_rtx) | |
550 | return false; | |
551 | x = XEXP (x, 1); | |
552 | if (GET_CODE (x) != PLUS) | |
553 | return false; | |
554 | if (XEXP (x, 0) != stack_pointer_rtx) | |
555 | return false; | |
556 | return CONST_INT_P (XEXP (x, 1)); | |
557 | } | |
558 | ||
559 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
560 | return memory_operand (op, mode); | |
561 | }) | |
562 | ||
a657c98a RE |
563 | ;;------------------------------------------------------------------------- |
564 | ;; | |
565 | ;; Thumb predicates | |
566 | ;; | |
567 | ||
5b3e6663 | 568 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
569 | (ior (and (match_code "reg,subreg") |
570 | (match_operand 0 "s_register_operand")) | |
571 | (and (match_code "const_int") | |
572 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256")))) | |
573 | ||
5b3e6663 | 574 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
575 | (and (match_code "const_int") |
576 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
577 | ||
578 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
579 | ;; condition code register. Prior to reload we only accept a | |
580 | ;; register. After reload we have to be able to handle memory as | |
581 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
582 | ;; handle output-reloads on jump insns. | |
583 | ||
584 | ;; We could possibly handle mem before reload as well, but that might | |
585 | ;; complicate things with the need to handle increment | |
586 | ;; side-effects. | |
587 | (define_predicate "thumb_cbrch_target_operand" | |
588 | (and (match_code "reg,subreg,mem") | |
589 | (ior (match_operand 0 "s_register_operand") | |
590 | (and (match_test "reload_in_progress || reload_completed") | |
591 | (match_operand 0 "memory_operand"))))) | |
592 | ||
593 | ;;------------------------------------------------------------------------- | |
594 | ;; | |
595 | ;; MAVERICK predicates | |
596 | ;; | |
597 | ||
598 | (define_predicate "cirrus_register_operand" | |
599 | (match_code "reg,subreg") | |
600 | { | |
601 | if (GET_CODE (op) == SUBREG) | |
602 | op = SUBREG_REG (op); | |
603 | ||
604 | return (GET_CODE (op) == REG | |
605 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
606 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
607 | }) | |
608 | ||
609 | (define_predicate "cirrus_fp_register" | |
610 | (match_code "reg,subreg") | |
611 | { | |
612 | if (GET_CODE (op) == SUBREG) | |
613 | op = SUBREG_REG (op); | |
614 | ||
615 | return (GET_CODE (op) == REG | |
616 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
617 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
618 | }) | |
619 | ||
620 | (define_predicate "cirrus_shift_const" | |
621 | (and (match_code "const_int") | |
622 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64"))) | |
623 | ||
624 | ||
88f77cba JB |
625 | ;; Neon predicates |
626 | ||
627 | (define_predicate "const_multiple_of_8_operand" | |
628 | (match_code "const_int") | |
629 | { | |
630 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
631 | return (val & 7) == 0; | |
632 | }) | |
633 | ||
634 | (define_predicate "imm_for_neon_mov_operand" | |
635 | (match_code "const_vector") | |
636 | { | |
637 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
638 | }) | |
639 | ||
31a0c825 DP |
640 | (define_predicate "imm_for_neon_lshift_operand" |
641 | (match_code "const_vector") | |
642 | { | |
643 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
644 | }) | |
645 | ||
646 | (define_predicate "imm_for_neon_rshift_operand" | |
647 | (match_code "const_vector") | |
648 | { | |
649 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
650 | }) | |
651 | ||
652 | (define_predicate "imm_lshift_or_reg_neon" | |
653 | (ior (match_operand 0 "s_register_operand") | |
654 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
655 | ||
656 | (define_predicate "imm_rshift_or_reg_neon" | |
657 | (ior (match_operand 0 "s_register_operand") | |
658 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
659 | ||
88f77cba JB |
660 | (define_predicate "imm_for_neon_logic_operand" |
661 | (match_code "const_vector") | |
662 | { | |
b3b7bbce SL |
663 | return (TARGET_NEON |
664 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
88f77cba JB |
665 | }) |
666 | ||
667 | (define_predicate "imm_for_neon_inv_logic_operand" | |
668 | (match_code "const_vector") | |
669 | { | |
b3b7bbce SL |
670 | return (TARGET_NEON |
671 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
88f77cba JB |
672 | }) |
673 | ||
674 | (define_predicate "neon_logic_op2" | |
675 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
676 | (match_operand 0 "s_register_operand"))) | |
677 | ||
678 | (define_predicate "neon_inv_logic_op2" | |
679 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
680 | (match_operand 0 "s_register_operand"))) | |
681 | ||
682 | ;; TODO: We could check lane numbers more precisely based on the mode. | |
683 | (define_predicate "neon_lane_number" | |
684 | (and (match_code "const_int") | |
3460fdf3 | 685 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))) |
73160ba9 DJ |
686 | ;; Predicates for named expanders that overlap multiple ISAs. |
687 | ||
688 | (define_predicate "cmpdi_operand" | |
689 | (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") | |
690 | (and (match_test "TARGET_ARM") | |
691 | (match_operand 0 "cirrus_fp_register")) | |
692 | (and (match_test "TARGET_32BIT") | |
693 | (match_operand 0 "arm_di_operand")))) | |
88f77cba | 694 | |
999a9cc5 MS |
695 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
696 | (define_predicate "arm_sync_memory_operand" | |
697 | (and (match_operand 0 "memory_operand") | |
698 | (match_code "reg" "0"))) | |
699 | ||
46b57af1 TB |
700 | ;; Predicates for parallel expanders based on mode. |
701 | (define_special_predicate "vect_par_constant_high" | |
702 | (match_code "parallel") | |
703 | { | |
704 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
705 | int i; | |
706 | int base = GET_MODE_NUNITS (mode); | |
707 | ||
708 | if ((count < 1) | |
709 | || (count != base/2)) | |
710 | return false; | |
711 | ||
712 | if (!VECTOR_MODE_P (mode)) | |
713 | return false; | |
714 | ||
715 | for (i = 0; i < count; i++) | |
716 | { | |
717 | rtx elt = XVECEXP (op, 0, i); | |
718 | int val; | |
719 | ||
720 | if (GET_CODE (elt) != CONST_INT) | |
721 | return false; | |
722 | ||
723 | val = INTVAL (elt); | |
724 | if (val != (base/2) + i) | |
725 | return false; | |
726 | } | |
727 | return true; | |
728 | }) | |
729 | ||
730 | (define_special_predicate "vect_par_constant_low" | |
731 | (match_code "parallel") | |
732 | { | |
733 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
734 | int i; | |
735 | int base = GET_MODE_NUNITS (mode); | |
736 | ||
737 | if ((count < 1) | |
738 | || (count != base/2)) | |
739 | return false; | |
740 | ||
741 | if (!VECTOR_MODE_P (mode)) | |
742 | return false; | |
743 | ||
744 | for (i = 0; i < count; i++) | |
745 | { | |
746 | rtx elt = XVECEXP (op, 0, i); | |
747 | int val; | |
748 | ||
749 | if (GET_CODE (elt) != CONST_INT) | |
750 | return false; | |
751 | ||
752 | val = INTVAL (elt); | |
753 | if (val != i) | |
754 | return false; | |
755 | } | |
756 | return true; | |
757 | }) | |
6308e208 | 758 | |
7f3d8f56 RR |
759 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
760 | (and (match_code "const_double") | |
761 | (match_test "TARGET_32BIT && TARGET_VFP | |
762 | && vfp3_const_double_for_fract_bits (op)"))) | |
763 | ||
12c4ecb1 | 764 | (define_predicate "neon_struct_operand" |
6308e208 RS |
765 | (and (match_code "mem") |
766 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) | |
9a1ea4b9 | 767 | |
12c4ecb1 RS |
768 | (define_predicate "neon_struct_or_register_operand" |
769 | (ior (match_operand 0 "neon_struct_operand") | |
770 | (match_operand 0 "s_register_operand"))) | |
771 | ||
9a1ea4b9 RR |
772 | (define_special_predicate "add_operator" |
773 | (match_code "plus")) | |
18f0fe6b RH |
774 | |
775 | (define_predicate "mem_noofs_operand" | |
776 | (and (match_code "mem") | |
777 | (match_code "reg" "0"))) |