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9c9db025 | 1 | ;; Predicate definitions for ARM and Thumb |
3aea1f79 | 2 | ;; Copyright (C) 2004-2014 Free Software Foundation, Inc. |
9c9db025 | 3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
038d1e19 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
9c9db025 | 10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
9c9db025 | 20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
0438d37f | 29 | return (REG_P (op) |
9c9db025 | 30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
f6bbdcf6 | 34 | (define_predicate "imm_for_neon_inv_logic_operand" |
35 | (match_code "const_vector") | |
36 | { | |
37 | return (TARGET_NEON | |
38 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
39 | }) | |
40 | ||
41 | (define_predicate "neon_inv_logic_op2" | |
42 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
43 | (match_operand 0 "s_register_operand"))) | |
44 | ||
74d6113f | 45 | (define_predicate "imm_for_neon_logic_operand" |
46 | (match_code "const_vector") | |
47 | { | |
48 | return (TARGET_NEON | |
49 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
50 | }) | |
51 | ||
52 | (define_predicate "neon_logic_op2" | |
53 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
54 | (match_operand 0 "s_register_operand"))) | |
55 | ||
ef8395d0 | 56 | ;; Any general register. |
f0a37dbd | 57 | (define_predicate "arm_hard_general_register_operand" |
9c9db025 | 58 | (match_code "reg") |
59 | { | |
f0a37dbd | 60 | return REGNO (op) <= LAST_ARM_REGNUM; |
9c9db025 | 61 | }) |
62 | ||
25f905c2 | 63 | ;; A low register. |
64 | (define_predicate "low_register_operand" | |
65 | (and (match_code "reg") | |
66 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
67 | ||
68 | ;; A low register or const_int. | |
69 | (define_predicate "low_reg_or_int_operand" | |
70 | (ior (match_code "const_int") | |
71 | (match_operand 0 "low_register_operand"))) | |
72 | ||
9c9db025 | 73 | ;; Any core register, or any pseudo. */ |
74 | (define_predicate "arm_general_register_operand" | |
75 | (match_code "reg,subreg") | |
76 | { | |
77 | if (GET_CODE (op) == SUBREG) | |
78 | op = SUBREG_REG (op); | |
79 | ||
0438d37f | 80 | return (REG_P (op) |
9c9db025 | 81 | && (REGNO (op) <= LAST_ARM_REGNUM |
82 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
83 | }) | |
84 | ||
3cc80a30 | 85 | (define_predicate "vfp_register_operand" |
86 | (match_code "reg,subreg") | |
87 | { | |
88 | if (GET_CODE (op) == SUBREG) | |
89 | op = SUBREG_REG (op); | |
90 | ||
91 | /* We don't consider registers whose class is NO_REGS | |
92 | to be a register operand. */ | |
0438d37f | 93 | return (REG_P (op) |
3cc80a30 | 94 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER |
503a3607 | 95 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
3cc80a30 | 96 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
97 | || (TARGET_VFPD32 | |
98 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
99 | }) | |
100 | ||
2f2163a4 | 101 | (define_predicate "vfp_hard_register_operand" |
102 | (match_code "reg") | |
103 | { | |
104 | return (IS_VFP_REGNUM (REGNO (op))); | |
105 | }) | |
106 | ||
1987d213 | 107 | (define_predicate "zero_operand" |
108 | (and (match_code "const_int,const_double,const_vector") | |
109 | (match_test "op == CONST0_RTX (mode)"))) | |
110 | ||
111 | ;; Match a register, or zero in the appropriate mode. | |
112 | (define_predicate "reg_or_zero_operand" | |
113 | (ior (match_operand 0 "s_register_operand") | |
114 | (match_operand 0 "zero_operand"))) | |
115 | ||
1c274529 | 116 | (define_special_predicate "subreg_lowpart_operator" |
117 | (and (match_code "subreg") | |
118 | (match_test "subreg_lowpart_p (op)"))) | |
119 | ||
9c9db025 | 120 | ;; Reg, subreg(reg) or const_int. |
121 | (define_predicate "reg_or_int_operand" | |
122 | (ior (match_code "const_int") | |
123 | (match_operand 0 "s_register_operand"))) | |
124 | ||
125 | (define_predicate "arm_immediate_operand" | |
126 | (and (match_code "const_int") | |
127 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
128 | ||
a8045a4f | 129 | ;; A constant value which fits into two instructions, each taking |
130 | ;; an arithmetic constant operand for one of the words. | |
131 | (define_predicate "arm_immediate_di_operand" | |
132 | (and (match_code "const_int,const_double") | |
133 | (match_test "arm_const_double_by_immediates (op)"))) | |
134 | ||
9c9db025 | 135 | (define_predicate "arm_neg_immediate_operand" |
136 | (and (match_code "const_int") | |
137 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
138 | ||
139 | (define_predicate "arm_not_immediate_operand" | |
140 | (and (match_code "const_int") | |
141 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
142 | ||
a8e6c15d | 143 | (define_predicate "const0_operand" |
144 | (and (match_code "const_int") | |
145 | (match_test "INTVAL (op) == 0"))) | |
146 | ||
9c9db025 | 147 | ;; Something valid on the RHS of an ARM data-processing instruction |
148 | (define_predicate "arm_rhs_operand" | |
149 | (ior (match_operand 0 "s_register_operand") | |
150 | (match_operand 0 "arm_immediate_operand"))) | |
151 | ||
152 | (define_predicate "arm_rhsm_operand" | |
153 | (ior (match_operand 0 "arm_rhs_operand") | |
154 | (match_operand 0 "memory_operand"))) | |
155 | ||
809003b3 | 156 | (define_predicate "const_int_I_operand" |
157 | (and (match_operand 0 "const_int_operand") | |
158 | (match_test "satisfies_constraint_I (op)"))) | |
159 | ||
160 | (define_predicate "const_int_M_operand" | |
161 | (and (match_operand 0 "const_int_operand") | |
162 | (match_test "satisfies_constraint_M (op)"))) | |
163 | ||
63b58df5 | 164 | ;; This doesn't have to do much because the constant is already checked |
165 | ;; in the shift_operator predicate. | |
d5d4dc8d | 166 | (define_predicate "shift_amount_operand" |
167 | (ior (and (match_test "TARGET_ARM") | |
168 | (match_operand 0 "s_register_operand")) | |
63b58df5 | 169 | (match_operand 0 "const_int_operand"))) |
d5d4dc8d | 170 | |
6083c152 | 171 | (define_predicate "const_neon_scalar_shift_amount_operand" |
172 | (and (match_code "const_int") | |
173 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode) | |
174 | && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0"))) | |
175 | ||
1653cf17 | 176 | (define_predicate "ldrd_strd_offset_operand" |
177 | (and (match_operand 0 "const_int_operand") | |
178 | (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) | |
179 | ||
9c9db025 | 180 | (define_predicate "arm_add_operand" |
181 | (ior (match_operand 0 "arm_rhs_operand") | |
182 | (match_operand 0 "arm_neg_immediate_operand"))) | |
183 | ||
f6bbdcf6 | 184 | (define_predicate "arm_anddi_operand_neon" |
185 | (ior (match_operand 0 "s_register_operand") | |
186 | (and (match_code "const_int") | |
187 | (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) | |
188 | (match_operand 0 "neon_inv_logic_op2"))) | |
189 | ||
74d6113f | 190 | (define_predicate "arm_iordi_operand_neon" |
191 | (ior (match_operand 0 "s_register_operand") | |
192 | (and (match_code "const_int") | |
193 | (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")) | |
194 | (match_operand 0 "neon_logic_op2"))) | |
195 | ||
8ee7dc6f | 196 | (define_predicate "arm_xordi_operand" |
197 | (ior (match_operand 0 "s_register_operand") | |
198 | (and (match_code "const_int") | |
199 | (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) | |
200 | ||
10e5ccd5 | 201 | (define_predicate "arm_adddi_operand" |
202 | (ior (match_operand 0 "s_register_operand") | |
203 | (and (match_code "const_int") | |
204 | (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) | |
205 | ||
9c9db025 | 206 | (define_predicate "arm_addimm_operand" |
207 | (ior (match_operand 0 "arm_immediate_operand") | |
208 | (match_operand 0 "arm_neg_immediate_operand"))) | |
209 | ||
210 | (define_predicate "arm_not_operand" | |
211 | (ior (match_operand 0 "arm_rhs_operand") | |
212 | (match_operand 0 "arm_not_immediate_operand"))) | |
213 | ||
a8045a4f | 214 | (define_predicate "arm_di_operand" |
215 | (ior (match_operand 0 "s_register_operand") | |
216 | (match_operand 0 "arm_immediate_di_operand"))) | |
217 | ||
9c9db025 | 218 | ;; True if the operand is a memory reference which contains an |
219 | ;; offsettable address. | |
220 | (define_predicate "offsettable_memory_operand" | |
221 | (and (match_code "mem") | |
222 | (match_test | |
223 | "offsettable_address_p (reload_completed | reload_in_progress, | |
224 | mode, XEXP (op, 0))"))) | |
225 | ||
a3c63a9d | 226 | ;; True if the operand is a memory operand that does not have an |
227 | ;; automodified base register (and thus will not generate output reloads). | |
228 | (define_predicate "call_memory_operand" | |
229 | (and (match_code "mem") | |
230 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
231 | != RTX_AUTOINC") | |
232 | (match_operand 0 "memory_operand")))) | |
233 | ||
9c9db025 | 234 | (define_predicate "arm_reload_memory_operand" |
d530a8c4 | 235 | (and (match_code "mem,reg,subreg") |
9c9db025 | 236 | (match_test "(!CONSTANT_P (op) |
237 | && (true_regnum(op) == -1 | |
0438d37f | 238 | || (REG_P (op) |
9c9db025 | 239 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) |
240 | ||
9c9db025 | 241 | (define_predicate "vfp_compare_operand" |
242 | (ior (match_operand 0 "s_register_operand") | |
243 | (and (match_code "const_double") | |
244 | (match_test "arm_const_double_rtx (op)")))) | |
245 | ||
246 | (define_predicate "arm_float_compare_operand" | |
247 | (if_then_else (match_test "TARGET_VFP") | |
248 | (match_operand 0 "vfp_compare_operand") | |
d86c91f6 | 249 | (match_operand 0 "s_register_operand"))) |
9c9db025 | 250 | |
251 | ;; True for valid index operands. | |
252 | (define_predicate "index_operand" | |
253 | (ior (match_operand 0 "s_register_operand") | |
254 | (and (match_operand 0 "immediate_operand") | |
0438d37f | 255 | (match_test "(!CONST_INT_P (op) |
9c9db025 | 256 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) |
257 | ||
258 | ;; True for operators that can be combined with a shift in ARM state. | |
259 | (define_special_predicate "shiftable_operator" | |
260 | (and (match_code "plus,minus,ior,xor,and") | |
261 | (match_test "mode == GET_MODE (op)"))) | |
262 | ||
4369e6ad | 263 | (define_special_predicate "shiftable_operator_strict_it" |
264 | (and (match_code "plus,and") | |
265 | (match_test "mode == GET_MODE (op)"))) | |
266 | ||
84cbcde5 | 267 | ;; True for logical binary operators. |
9c9db025 | 268 | (define_special_predicate "logical_binary_operator" |
269 | (and (match_code "ior,xor,and") | |
270 | (match_test "mode == GET_MODE (op)"))) | |
271 | ||
320ea44d | 272 | ;; True for commutative operators |
273 | (define_special_predicate "commutative_binary_operator" | |
274 | (and (match_code "ior,xor,and,plus") | |
275 | (match_test "mode == GET_MODE (op)"))) | |
276 | ||
9c9db025 | 277 | ;; True for shift operators. |
63b58df5 | 278 | ;; Notes: |
279 | ;; * mult is only permitted with a constant shift amount | |
280 | ;; * patterns that permit register shift amounts only in ARM mode use | |
281 | ;; shift_amount_operand, patterns that always allow registers do not, | |
282 | ;; so we don't have to worry about that sort of thing here. | |
9c9db025 | 283 | (define_special_predicate "shift_operator" |
284 | (and (ior (ior (and (match_code "mult") | |
285 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
286 | (and (match_code "rotate") | |
0438d37f | 287 | (match_test "CONST_INT_P (XEXP (op, 1)) |
9c9db025 | 288 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) |
63b58df5 | 289 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
0438d37f | 290 | (match_test "!CONST_INT_P (XEXP (op, 1)) |
63b58df5 | 291 | || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) |
9c9db025 | 292 | (match_test "mode == GET_MODE (op)"))) |
293 | ||
bbbe4599 | 294 | ;; True for shift operators which can be used with saturation instructions. |
295 | (define_special_predicate "sat_shift_operator" | |
b49e3742 | 296 | (and (ior (and (match_code "mult") |
297 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
298 | (and (match_code "ashift,ashiftrt") | |
0438d37f | 299 | (match_test "CONST_INT_P (XEXP (op, 1)) |
b49e3742 | 300 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) |
bbbe4599 | 301 | (match_test "mode == GET_MODE (op)"))) |
302 | ||
d5d4dc8d | 303 | ;; True for MULT, to identify which variant of shift_operator is in use. |
304 | (define_special_predicate "mult_operator" | |
305 | (match_code "mult")) | |
306 | ||
25f905c2 | 307 | ;; True for operators that have 16-bit thumb variants. */ |
308 | (define_special_predicate "thumb_16bit_operator" | |
309 | (match_code "plus,minus,and,ior,xor")) | |
310 | ||
9c9db025 | 311 | ;; True for EQ & NE |
312 | (define_special_predicate "equality_operator" | |
313 | (match_code "eq,ne")) | |
314 | ||
74f4459c | 315 | ;; True for integer comparisons and, if FP is active, for comparisons |
316 | ;; other than LTGT or UNEQ. | |
aa06947a | 317 | (define_special_predicate "expandable_comparison_operator" |
318 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
319 | unordered,ordered,unlt,unle,unge,ungt")) | |
320 | ||
321 | ;; Likewise, but only accept comparisons that are directly supported | |
322 | ;; by ARM condition codes. | |
9c9db025 | 323 | (define_special_predicate "arm_comparison_operator" |
aa06947a | 324 | (and (match_operand 0 "expandable_comparison_operator") |
23628a13 | 325 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
9c9db025 | 326 | |
a8e6c15d | 327 | (define_special_predicate "lt_ge_comparison_operator" |
328 | (match_code "lt,ge")) | |
329 | ||
91cb50d2 | 330 | ;; The vsel instruction only accepts the ARM condition codes listed below. |
331 | (define_special_predicate "arm_vsel_comparison_operator" | |
332 | (and (match_operand 0 "expandable_comparison_operator") | |
333 | (match_test "maybe_get_arm_condition_code (op) == ARM_GE | |
334 | || maybe_get_arm_condition_code (op) == ARM_GT | |
335 | || maybe_get_arm_condition_code (op) == ARM_EQ | |
336 | || maybe_get_arm_condition_code (op) == ARM_VS | |
337 | || maybe_get_arm_condition_code (op) == ARM_LT | |
338 | || maybe_get_arm_condition_code (op) == ARM_LE | |
339 | || maybe_get_arm_condition_code (op) == ARM_NE | |
340 | || maybe_get_arm_condition_code (op) == ARM_VC"))) | |
341 | ||
4df97ffc | 342 | (define_special_predicate "arm_cond_move_operator" |
343 | (if_then_else (match_test "arm_restrict_it") | |
344 | (and (match_test "TARGET_FPU_ARMV8") | |
345 | (match_operand 0 "arm_vsel_comparison_operator")) | |
346 | (match_operand 0 "expandable_comparison_operator"))) | |
347 | ||
747b7458 | 348 | (define_special_predicate "noov_comparison_operator" |
349 | (match_code "lt,ge,eq,ne")) | |
350 | ||
9c9db025 | 351 | (define_special_predicate "minmax_operator" |
352 | (and (match_code "smin,smax,umin,umax") | |
353 | (match_test "mode == GET_MODE (op)"))) | |
354 | ||
355 | (define_special_predicate "cc_register" | |
356 | (and (match_code "reg") | |
357 | (and (match_test "REGNO (op) == CC_REGNUM") | |
358 | (ior (match_test "mode == GET_MODE (op)") | |
359 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
360 | ||
361 | (define_special_predicate "dominant_cc_register" | |
362 | (match_code "reg") | |
363 | { | |
364 | if (mode == VOIDmode) | |
365 | { | |
366 | mode = GET_MODE (op); | |
367 | ||
368 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
369 | return false; | |
370 | } | |
371 | ||
372 | return (cc_register (op, mode) | |
373 | && (mode == CC_DNEmode | |
374 | || mode == CC_DEQmode | |
375 | || mode == CC_DLEmode | |
376 | || mode == CC_DLTmode | |
377 | || mode == CC_DGEmode | |
378 | || mode == CC_DGTmode | |
379 | || mode == CC_DLEUmode | |
380 | || mode == CC_DLTUmode | |
381 | || mode == CC_DGEUmode | |
382 | || mode == CC_DGTUmode)); | |
383 | }) | |
384 | ||
385 | (define_special_predicate "arm_extendqisi_mem_op" | |
386 | (and (match_operand 0 "memory_operand") | |
6d97728e | 387 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
388 | XEXP (op, 0), | |
389 | SIGN_EXTEND, | |
390 | 0) | |
391 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
9c9db025 | 392 | |
bed7d9a5 | 393 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
394 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
395 | (match_operand 0 "s_register_operand"))) | |
396 | ||
9c9db025 | 397 | (define_predicate "power_of_two_operand" |
398 | (match_code "const_int") | |
399 | { | |
422101e8 | 400 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
9c9db025 | 401 | |
402 | return value != 0 && (value & (value - 1)) == 0; | |
403 | }) | |
404 | ||
405 | (define_predicate "nonimmediate_di_operand" | |
406 | (match_code "reg,subreg,mem") | |
407 | { | |
408 | if (s_register_operand (op, mode)) | |
409 | return true; | |
410 | ||
411 | if (GET_CODE (op) == SUBREG) | |
412 | op = SUBREG_REG (op); | |
413 | ||
0438d37f | 414 | return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); |
9c9db025 | 415 | }) |
416 | ||
417 | (define_predicate "di_operand" | |
418 | (ior (match_code "const_int,const_double") | |
419 | (and (match_code "reg,subreg,mem") | |
420 | (match_operand 0 "nonimmediate_di_operand")))) | |
421 | ||
422 | (define_predicate "nonimmediate_soft_df_operand" | |
423 | (match_code "reg,subreg,mem") | |
424 | { | |
425 | if (s_register_operand (op, mode)) | |
426 | return true; | |
427 | ||
428 | if (GET_CODE (op) == SUBREG) | |
429 | op = SUBREG_REG (op); | |
430 | ||
0438d37f | 431 | return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); |
9c9db025 | 432 | }) |
433 | ||
434 | (define_predicate "soft_df_operand" | |
435 | (ior (match_code "const_double") | |
436 | (and (match_code "reg,subreg,mem") | |
437 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
438 | ||
9c9db025 | 439 | (define_special_predicate "load_multiple_operation" |
440 | (match_code "parallel") | |
441 | { | |
394cb8e0 | 442 | return ldm_stm_operation_p (op, /*load=*/true, SImode, |
443 | /*consecutive=*/false, | |
444 | /*return_pc=*/false); | |
9c9db025 | 445 | }) |
446 | ||
447 | (define_special_predicate "store_multiple_operation" | |
448 | (match_code "parallel") | |
449 | { | |
394cb8e0 | 450 | return ldm_stm_operation_p (op, /*load=*/false, SImode, |
451 | /*consecutive=*/false, | |
452 | /*return_pc=*/false); | |
9c9db025 | 453 | }) |
454 | ||
426be8c5 | 455 | (define_special_predicate "pop_multiple_return" |
456 | (match_code "parallel") | |
457 | { | |
458 | return ldm_stm_operation_p (op, /*load=*/true, SImode, | |
459 | /*consecutive=*/false, | |
460 | /*return_pc=*/true); | |
461 | }) | |
462 | ||
1a0b0f12 | 463 | (define_special_predicate "pop_multiple_fp" |
464 | (match_code "parallel") | |
465 | { | |
466 | return ldm_stm_operation_p (op, /*load=*/true, DFmode, | |
467 | /*consecutive=*/true, | |
468 | /*return_pc=*/false); | |
469 | }) | |
470 | ||
9c9db025 | 471 | (define_special_predicate "multi_register_push" |
472 | (match_code "parallel") | |
473 | { | |
474 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
475 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
476 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
477 | return false; | |
478 | ||
479 | return true; | |
480 | }) | |
481 | ||
7571d3f7 | 482 | (define_predicate "push_mult_memory_operand" |
483 | (match_code "mem") | |
484 | { | |
485 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
486 | any point in testing for thumb1 specially? All of the variants | |
487 | use the same form. */ | |
488 | if (TARGET_THUMB1) | |
489 | { | |
490 | /* ??? No attempt is made to represent STMIA, or validate that | |
491 | the stack adjustment matches the register count. This is | |
492 | true of the ARM/Thumb2 path as well. */ | |
493 | rtx x = XEXP (op, 0); | |
494 | if (GET_CODE (x) != PRE_MODIFY) | |
495 | return false; | |
496 | if (XEXP (x, 0) != stack_pointer_rtx) | |
497 | return false; | |
498 | x = XEXP (x, 1); | |
499 | if (GET_CODE (x) != PLUS) | |
500 | return false; | |
501 | if (XEXP (x, 0) != stack_pointer_rtx) | |
502 | return false; | |
503 | return CONST_INT_P (XEXP (x, 1)); | |
504 | } | |
505 | ||
506 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
507 | return memory_operand (op, mode); | |
508 | }) | |
509 | ||
9c9db025 | 510 | ;;------------------------------------------------------------------------- |
511 | ;; | |
512 | ;; Thumb predicates | |
513 | ;; | |
514 | ||
25f905c2 | 515 | (define_predicate "thumb1_cmp_operand" |
9c9db025 | 516 | (ior (and (match_code "reg,subreg") |
517 | (match_operand 0 "s_register_operand")) | |
518 | (and (match_code "const_int") | |
519 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256")))) | |
520 | ||
25f905c2 | 521 | (define_predicate "thumb1_cmpneg_operand" |
9c9db025 | 522 | (and (match_code "const_int") |
523 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
524 | ||
525 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
526 | ;; condition code register. Prior to reload we only accept a | |
527 | ;; register. After reload we have to be able to handle memory as | |
528 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
529 | ;; handle output-reloads on jump insns. | |
530 | ||
531 | ;; We could possibly handle mem before reload as well, but that might | |
532 | ;; complicate things with the need to handle increment | |
533 | ;; side-effects. | |
534 | (define_predicate "thumb_cbrch_target_operand" | |
535 | (and (match_code "reg,subreg,mem") | |
536 | (ior (match_operand 0 "s_register_operand") | |
537 | (and (match_test "reload_in_progress || reload_completed") | |
538 | (match_operand 0 "memory_operand"))))) | |
539 | ||
540 | ;;------------------------------------------------------------------------- | |
541 | ;; | |
6b8f7c28 | 542 | ;; iWMMXt predicates |
d86c91f6 | 543 | ;; |
6b8f7c28 | 544 | |
545 | (define_predicate "imm_or_reg_operand" | |
546 | (ior (match_operand 0 "immediate_operand") | |
547 | (match_operand 0 "register_operand"))) | |
9c9db025 | 548 | |
d98a3884 | 549 | ;; Neon predicates |
550 | ||
551 | (define_predicate "const_multiple_of_8_operand" | |
552 | (match_code "const_int") | |
553 | { | |
554 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
555 | return (val & 7) == 0; | |
556 | }) | |
557 | ||
558 | (define_predicate "imm_for_neon_mov_operand" | |
87f800b2 | 559 | (match_code "const_vector,const_int") |
d98a3884 | 560 | { |
561 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
562 | }) | |
563 | ||
73f20323 | 564 | (define_predicate "imm_for_neon_lshift_operand" |
565 | (match_code "const_vector") | |
566 | { | |
567 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
568 | }) | |
569 | ||
570 | (define_predicate "imm_for_neon_rshift_operand" | |
571 | (match_code "const_vector") | |
572 | { | |
573 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
574 | }) | |
575 | ||
576 | (define_predicate "imm_lshift_or_reg_neon" | |
577 | (ior (match_operand 0 "s_register_operand") | |
578 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
579 | ||
580 | (define_predicate "imm_rshift_or_reg_neon" | |
581 | (ior (match_operand 0 "s_register_operand") | |
582 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
583 | ||
a8045a4f | 584 | ;; Predicates for named expanders that overlap multiple ISAs. |
585 | ||
586 | (define_predicate "cmpdi_operand" | |
d86c91f6 | 587 | (and (match_test "TARGET_32BIT") |
588 | (match_operand 0 "arm_di_operand"))) | |
d98a3884 | 589 | |
94056610 | 590 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
591 | (define_predicate "arm_sync_memory_operand" | |
592 | (and (match_operand 0 "memory_operand") | |
593 | (match_code "reg" "0"))) | |
594 | ||
6e4376d7 | 595 | ;; Predicates for parallel expanders based on mode. |
596 | (define_special_predicate "vect_par_constant_high" | |
597 | (match_code "parallel") | |
598 | { | |
599 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
600 | int i; | |
601 | int base = GET_MODE_NUNITS (mode); | |
602 | ||
603 | if ((count < 1) | |
604 | || (count != base/2)) | |
605 | return false; | |
606 | ||
607 | if (!VECTOR_MODE_P (mode)) | |
608 | return false; | |
609 | ||
610 | for (i = 0; i < count; i++) | |
611 | { | |
612 | rtx elt = XVECEXP (op, 0, i); | |
613 | int val; | |
614 | ||
0438d37f | 615 | if (!CONST_INT_P (elt)) |
6e4376d7 | 616 | return false; |
617 | ||
618 | val = INTVAL (elt); | |
619 | if (val != (base/2) + i) | |
620 | return false; | |
621 | } | |
622 | return true; | |
623 | }) | |
624 | ||
625 | (define_special_predicate "vect_par_constant_low" | |
626 | (match_code "parallel") | |
627 | { | |
628 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
629 | int i; | |
630 | int base = GET_MODE_NUNITS (mode); | |
631 | ||
632 | if ((count < 1) | |
633 | || (count != base/2)) | |
634 | return false; | |
635 | ||
636 | if (!VECTOR_MODE_P (mode)) | |
637 | return false; | |
638 | ||
639 | for (i = 0; i < count; i++) | |
640 | { | |
641 | rtx elt = XVECEXP (op, 0, i); | |
642 | int val; | |
643 | ||
0438d37f | 644 | if (!CONST_INT_P (elt)) |
6e4376d7 | 645 | return false; |
646 | ||
647 | val = INTVAL (elt); | |
648 | if (val != i) | |
649 | return false; | |
650 | } | |
651 | return true; | |
652 | }) | |
e5bf7a7a | 653 | |
4a62aafb | 654 | (define_predicate "const_double_vcvt_power_of_two_reciprocal" |
655 | (and (match_code "const_double") | |
7cb1e49b | 656 | (match_test "TARGET_32BIT && TARGET_VFP |
657 | && vfp3_const_double_for_fract_bits (op)"))) | |
658 | ||
659 | (define_predicate "const_double_vcvt_power_of_two" | |
660 | (and (match_code "const_double") | |
661 | (match_test "TARGET_32BIT && TARGET_VFP | |
662 | && vfp3_const_double_for_bits (op)"))) | |
4a62aafb | 663 | |
4c1dfb84 | 664 | (define_predicate "neon_struct_operand" |
e5bf7a7a | 665 | (and (match_code "mem") |
1c2054e4 | 666 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) |
7392680c | 667 | |
1c2054e4 | 668 | (define_predicate "neon_permissive_struct_operand" |
669 | (and (match_code "mem") | |
670 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) | |
671 | ||
672 | (define_predicate "neon_perm_struct_or_reg_operand" | |
673 | (ior (match_operand 0 "neon_permissive_struct_operand") | |
4c1dfb84 | 674 | (match_operand 0 "s_register_operand"))) |
675 | ||
7392680c | 676 | (define_special_predicate "add_operator" |
677 | (match_code "plus")) | |
e1b93706 | 678 | |
679 | (define_predicate "mem_noofs_operand" | |
680 | (and (match_code "mem") | |
681 | (match_code "reg" "0"))) | |
33ae7c4b | 682 | |
683 | (define_predicate "call_insn_operand" | |
684 | (ior (match_code "symbol_ref") | |
685 | (match_operand 0 "s_register_operand"))) |