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a657c98a 1;; Predicate definitions for ARM and Thumb
23a5b65a 2;; Copyright (C) 2004-2014 Free Software Foundation, Inc.
a657c98a
RE
3;; Contributed by ARM Ltd.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
2f83c7d6 9;; by the Free Software Foundation; either version 3, or (at your
a657c98a
RE
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
2f83c7d6
NC
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
a657c98a
RE
20
21(define_predicate "s_register_operand"
22 (match_code "reg,subreg")
23{
24 if (GET_CODE (op) == SUBREG)
25 op = SUBREG_REG (op);
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
d435a4be 29 return (REG_P (op)
a657c98a
RE
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
32})
33
1c50eada
KT
34(define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
36{
37 return (TARGET_NEON
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
39})
40
41(define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
44
b6af05a9
KT
45(define_predicate "imm_for_neon_logic_operand"
46 (match_code "const_vector")
47{
48 return (TARGET_NEON
49 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
50})
51
52(define_predicate "neon_logic_op2"
53 (ior (match_operand 0 "imm_for_neon_logic_operand")
54 (match_operand 0 "s_register_operand")))
55
8b0497de 56;; Any general register.
03158648 57(define_predicate "arm_hard_general_register_operand"
a657c98a
RE
58 (match_code "reg")
59{
03158648 60 return REGNO (op) <= LAST_ARM_REGNUM;
a657c98a
RE
61})
62
5b3e6663
PB
63;; A low register.
64(define_predicate "low_register_operand"
65 (and (match_code "reg")
66 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
67
68;; A low register or const_int.
69(define_predicate "low_reg_or_int_operand"
70 (ior (match_code "const_int")
71 (match_operand 0 "low_register_operand")))
72
a657c98a
RE
73;; Any core register, or any pseudo. */
74(define_predicate "arm_general_register_operand"
75 (match_code "reg,subreg")
76{
77 if (GET_CODE (op) == SUBREG)
78 op = SUBREG_REG (op);
79
d435a4be 80 return (REG_P (op)
a657c98a
RE
81 && (REGNO (op) <= LAST_ARM_REGNUM
82 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
83})
84
4e6f5666
JZ
85(define_predicate "vfp_register_operand"
86 (match_code "reg,subreg")
87{
88 if (GET_CODE (op) == SUBREG)
89 op = SUBREG_REG (op);
90
91 /* We don't consider registers whose class is NO_REGS
92 to be a register operand. */
d435a4be 93 return (REG_P (op)
4e6f5666 94 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
34db4735 95 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
4e6f5666
JZ
96 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
97 || (TARGET_VFPD32
98 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
99})
100
315d7bd4
CL
101(define_predicate "vfp_hard_register_operand"
102 (match_code "reg")
103{
104 return (IS_VFP_REGNUM (REGNO (op)));
105})
106
681676df
RE
107(define_predicate "zero_operand"
108 (and (match_code "const_int,const_double,const_vector")
109 (match_test "op == CONST0_RTX (mode)")))
110
111;; Match a register, or zero in the appropriate mode.
112(define_predicate "reg_or_zero_operand"
113 (ior (match_operand 0 "s_register_operand")
114 (match_operand 0 "zero_operand")))
115
fa01135d
RE
116(define_special_predicate "subreg_lowpart_operator"
117 (and (match_code "subreg")
118 (match_test "subreg_lowpart_p (op)")))
119
a657c98a
RE
120;; Reg, subreg(reg) or const_int.
121(define_predicate "reg_or_int_operand"
122 (ior (match_code "const_int")
123 (match_operand 0 "s_register_operand")))
124
125(define_predicate "arm_immediate_operand"
126 (and (match_code "const_int")
127 (match_test "const_ok_for_arm (INTVAL (op))")))
128
73160ba9
DJ
129;; A constant value which fits into two instructions, each taking
130;; an arithmetic constant operand for one of the words.
131(define_predicate "arm_immediate_di_operand"
132 (and (match_code "const_int,const_double")
133 (match_test "arm_const_double_by_immediates (op)")))
134
a657c98a
RE
135(define_predicate "arm_neg_immediate_operand"
136 (and (match_code "const_int")
137 (match_test "const_ok_for_arm (-INTVAL (op))")))
138
139(define_predicate "arm_not_immediate_operand"
140 (and (match_code "const_int")
141 (match_test "const_ok_for_arm (~INTVAL (op))")))
142
f0c6475a
BS
143(define_predicate "const0_operand"
144 (and (match_code "const_int")
145 (match_test "INTVAL (op) == 0")))
146
a657c98a
RE
147;; Something valid on the RHS of an ARM data-processing instruction
148(define_predicate "arm_rhs_operand"
149 (ior (match_operand 0 "s_register_operand")
150 (match_operand 0 "arm_immediate_operand")))
151
152(define_predicate "arm_rhsm_operand"
153 (ior (match_operand 0 "arm_rhs_operand")
154 (match_operand 0 "memory_operand")))
155
fc02bcca
JL
156(define_predicate "const_int_I_operand"
157 (and (match_operand 0 "const_int_operand")
158 (match_test "satisfies_constraint_I (op)")))
159
160(define_predicate "const_int_M_operand"
161 (and (match_operand 0 "const_int_operand")
162 (match_test "satisfies_constraint_M (op)")))
163
55cdadd5
AS
164;; This doesn't have to do much because the constant is already checked
165;; in the shift_operator predicate.
c29e2982
BS
166(define_predicate "shift_amount_operand"
167 (ior (and (match_test "TARGET_ARM")
168 (match_operand 0 "s_register_operand"))
55cdadd5 169 (match_operand 0 "const_int_operand")))
c29e2982 170
36ba4aae
IR
171(define_predicate "const_neon_scalar_shift_amount_operand"
172 (and (match_code "const_int")
173 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
174 && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
175
56289ed2
SD
176(define_predicate "ldrd_strd_offset_operand"
177 (and (match_operand 0 "const_int_operand")
178 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
179
a657c98a
RE
180(define_predicate "arm_add_operand"
181 (ior (match_operand 0 "arm_rhs_operand")
182 (match_operand 0 "arm_neg_immediate_operand")))
183
1c50eada
KT
184(define_predicate "arm_anddi_operand_neon"
185 (ior (match_operand 0 "s_register_operand")
186 (and (match_code "const_int")
187 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
188 (match_operand 0 "neon_inv_logic_op2")))
189
b6af05a9
KT
190(define_predicate "arm_iordi_operand_neon"
191 (ior (match_operand 0 "s_register_operand")
192 (and (match_code "const_int")
193 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
194 (match_operand 0 "neon_logic_op2")))
195
79678d04
KT
196(define_predicate "arm_xordi_operand"
197 (ior (match_operand 0 "s_register_operand")
198 (and (match_code "const_int")
199 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
200
44cd6810
WG
201(define_predicate "arm_adddi_operand"
202 (ior (match_operand 0 "s_register_operand")
203 (and (match_code "const_int")
204 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
205
a657c98a
RE
206(define_predicate "arm_addimm_operand"
207 (ior (match_operand 0 "arm_immediate_operand")
208 (match_operand 0 "arm_neg_immediate_operand")))
209
210(define_predicate "arm_not_operand"
211 (ior (match_operand 0 "arm_rhs_operand")
212 (match_operand 0 "arm_not_immediate_operand")))
213
73160ba9
DJ
214(define_predicate "arm_di_operand"
215 (ior (match_operand 0 "s_register_operand")
216 (match_operand 0 "arm_immediate_di_operand")))
217
a657c98a
RE
218;; True if the operand is a memory reference which contains an
219;; offsettable address.
220(define_predicate "offsettable_memory_operand"
221 (and (match_code "mem")
222 (match_test
223 "offsettable_address_p (reload_completed | reload_in_progress,
224 mode, XEXP (op, 0))")))
225
e6add59b
RS
226;; True if the operand is a memory operand that does not have an
227;; automodified base register (and thus will not generate output reloads).
228(define_predicate "call_memory_operand"
229 (and (match_code "mem")
230 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
231 != RTX_AUTOINC")
232 (match_operand 0 "memory_operand"))))
233
a657c98a 234(define_predicate "arm_reload_memory_operand"
9d2da95b 235 (and (match_code "mem,reg,subreg")
a657c98a
RE
236 (match_test "(!CONSTANT_P (op)
237 && (true_regnum(op) == -1
d435a4be 238 || (REG_P (op)
a657c98a
RE
239 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
240
a657c98a
RE
241(define_predicate "vfp_compare_operand"
242 (ior (match_operand 0 "s_register_operand")
243 (and (match_code "const_double")
244 (match_test "arm_const_double_rtx (op)"))))
245
246(define_predicate "arm_float_compare_operand"
247 (if_then_else (match_test "TARGET_VFP")
248 (match_operand 0 "vfp_compare_operand")
dae840fc 249 (match_operand 0 "s_register_operand")))
a657c98a
RE
250
251;; True for valid index operands.
252(define_predicate "index_operand"
253 (ior (match_operand 0 "s_register_operand")
254 (and (match_operand 0 "immediate_operand")
d435a4be 255 (match_test "(!CONST_INT_P (op)
a657c98a
RE
256 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
257
258;; True for operators that can be combined with a shift in ARM state.
259(define_special_predicate "shiftable_operator"
260 (and (match_code "plus,minus,ior,xor,and")
261 (match_test "mode == GET_MODE (op)")))
262
95b97fac
KT
263(define_special_predicate "shiftable_operator_strict_it"
264 (and (match_code "plus,and")
265 (match_test "mode == GET_MODE (op)")))
266
c112cf2b 267;; True for logical binary operators.
a657c98a
RE
268(define_special_predicate "logical_binary_operator"
269 (and (match_code "ior,xor,and")
270 (match_test "mode == GET_MODE (op)")))
271
37119410
BS
272;; True for commutative operators
273(define_special_predicate "commutative_binary_operator"
274 (and (match_code "ior,xor,and,plus")
275 (match_test "mode == GET_MODE (op)")))
276
a657c98a 277;; True for shift operators.
55cdadd5
AS
278;; Notes:
279;; * mult is only permitted with a constant shift amount
280;; * patterns that permit register shift amounts only in ARM mode use
281;; shift_amount_operand, patterns that always allow registers do not,
282;; so we don't have to worry about that sort of thing here.
a657c98a
RE
283(define_special_predicate "shift_operator"
284 (and (ior (ior (and (match_code "mult")
285 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
286 (and (match_code "rotate")
d435a4be 287 (match_test "CONST_INT_P (XEXP (op, 1))
a657c98a 288 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
55cdadd5 289 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
d435a4be 290 (match_test "!CONST_INT_P (XEXP (op, 1))
55cdadd5 291 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
a657c98a
RE
292 (match_test "mode == GET_MODE (op)")))
293
655b30bf
JB
294;; True for shift operators which can be used with saturation instructions.
295(define_special_predicate "sat_shift_operator"
5d216c70
UW
296 (and (ior (and (match_code "mult")
297 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
298 (and (match_code "ashift,ashiftrt")
d435a4be 299 (match_test "CONST_INT_P (XEXP (op, 1))
5d216c70 300 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
655b30bf
JB
301 (match_test "mode == GET_MODE (op)")))
302
c29e2982
BS
303;; True for MULT, to identify which variant of shift_operator is in use.
304(define_special_predicate "mult_operator"
305 (match_code "mult"))
306
5b3e6663
PB
307;; True for operators that have 16-bit thumb variants. */
308(define_special_predicate "thumb_16bit_operator"
309 (match_code "plus,minus,and,ior,xor"))
310
a657c98a
RE
311;; True for EQ & NE
312(define_special_predicate "equality_operator"
313 (match_code "eq,ne"))
314
f90b7a5a
PB
315;; True for integer comparisons and, if FP is active, for comparisons
316;; other than LTGT or UNEQ.
aa0b3f8f
RS
317(define_special_predicate "expandable_comparison_operator"
318 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
319 unordered,ordered,unlt,unle,unge,ungt"))
320
321;; Likewise, but only accept comparisons that are directly supported
322;; by ARM condition codes.
a657c98a 323(define_special_predicate "arm_comparison_operator"
aa0b3f8f 324 (and (match_operand 0 "expandable_comparison_operator")
723d95fe 325 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
a657c98a 326
f0c6475a
BS
327(define_special_predicate "lt_ge_comparison_operator"
328 (match_code "lt,ge"))
329
a5a4c20a
KT
330;; The vsel instruction only accepts the ARM condition codes listed below.
331(define_special_predicate "arm_vsel_comparison_operator"
332 (and (match_operand 0 "expandable_comparison_operator")
333 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
334 || maybe_get_arm_condition_code (op) == ARM_GT
335 || maybe_get_arm_condition_code (op) == ARM_EQ
336 || maybe_get_arm_condition_code (op) == ARM_VS
337 || maybe_get_arm_condition_code (op) == ARM_LT
338 || maybe_get_arm_condition_code (op) == ARM_LE
339 || maybe_get_arm_condition_code (op) == ARM_NE
340 || maybe_get_arm_condition_code (op) == ARM_VC")))
341
1572e697
KT
342(define_special_predicate "arm_cond_move_operator"
343 (if_then_else (match_test "arm_restrict_it")
344 (and (match_test "TARGET_FPU_ARMV8")
345 (match_operand 0 "arm_vsel_comparison_operator"))
346 (match_operand 0 "expandable_comparison_operator")))
347
906668bb
BS
348(define_special_predicate "noov_comparison_operator"
349 (match_code "lt,ge,eq,ne"))
350
a657c98a
RE
351(define_special_predicate "minmax_operator"
352 (and (match_code "smin,smax,umin,umax")
353 (match_test "mode == GET_MODE (op)")))
354
355(define_special_predicate "cc_register"
356 (and (match_code "reg")
357 (and (match_test "REGNO (op) == CC_REGNUM")
358 (ior (match_test "mode == GET_MODE (op)")
359 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
360
361(define_special_predicate "dominant_cc_register"
362 (match_code "reg")
363{
364 if (mode == VOIDmode)
365 {
366 mode = GET_MODE (op);
367
368 if (GET_MODE_CLASS (mode) != MODE_CC)
369 return false;
370 }
371
372 return (cc_register (op, mode)
373 && (mode == CC_DNEmode
374 || mode == CC_DEQmode
375 || mode == CC_DLEmode
376 || mode == CC_DLTmode
377 || mode == CC_DGEmode
378 || mode == CC_DGTmode
379 || mode == CC_DLEUmode
380 || mode == CC_DLTUmode
381 || mode == CC_DGEUmode
382 || mode == CC_DGTUmode));
383})
384
385(define_special_predicate "arm_extendqisi_mem_op"
386 (and (match_operand 0 "memory_operand")
8d4f1548
RR
387 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
388 XEXP (op, 0),
389 SIGN_EXTEND,
390 0)
391 : memory_address_p (QImode, XEXP (op, 0))")))
a657c98a 392
01577df7
RE
393(define_special_predicate "arm_reg_or_extendqisi_mem_op"
394 (ior (match_operand 0 "arm_extendqisi_mem_op")
395 (match_operand 0 "s_register_operand")))
396
a657c98a
RE
397(define_predicate "power_of_two_operand"
398 (match_code "const_int")
399{
29b40d79 400 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
a657c98a
RE
401
402 return value != 0 && (value & (value - 1)) == 0;
403})
404
405(define_predicate "nonimmediate_di_operand"
406 (match_code "reg,subreg,mem")
407{
408 if (s_register_operand (op, mode))
409 return true;
410
411 if (GET_CODE (op) == SUBREG)
412 op = SUBREG_REG (op);
413
d435a4be 414 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
a657c98a
RE
415})
416
417(define_predicate "di_operand"
418 (ior (match_code "const_int,const_double")
419 (and (match_code "reg,subreg,mem")
420 (match_operand 0 "nonimmediate_di_operand"))))
421
422(define_predicate "nonimmediate_soft_df_operand"
423 (match_code "reg,subreg,mem")
424{
425 if (s_register_operand (op, mode))
426 return true;
427
428 if (GET_CODE (op) == SUBREG)
429 op = SUBREG_REG (op);
430
d435a4be 431 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
a657c98a
RE
432})
433
434(define_predicate "soft_df_operand"
435 (ior (match_code "const_double")
436 (and (match_code "reg,subreg,mem")
437 (match_operand 0 "nonimmediate_soft_df_operand"))))
438
a657c98a
RE
439(define_special_predicate "load_multiple_operation"
440 (match_code "parallel")
441{
fb40241d
IB
442 return ldm_stm_operation_p (op, /*load=*/true, SImode,
443 /*consecutive=*/false,
444 /*return_pc=*/false);
a657c98a
RE
445})
446
447(define_special_predicate "store_multiple_operation"
448 (match_code "parallel")
449{
fb40241d
IB
450 return ldm_stm_operation_p (op, /*load=*/false, SImode,
451 /*consecutive=*/false,
452 /*return_pc=*/false);
a657c98a
RE
453})
454
3aee1982
IB
455(define_special_predicate "pop_multiple_return"
456 (match_code "parallel")
457{
458 return ldm_stm_operation_p (op, /*load=*/true, SImode,
459 /*consecutive=*/false,
460 /*return_pc=*/true);
461})
462
4b2678f8
IB
463(define_special_predicate "pop_multiple_fp"
464 (match_code "parallel")
465{
466 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
467 /*consecutive=*/true,
468 /*return_pc=*/false);
469})
470
a657c98a
RE
471(define_special_predicate "multi_register_push"
472 (match_code "parallel")
473{
474 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
475 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
476 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
477 return false;
478
479 return true;
480})
481
d018b46e
RH
482(define_predicate "push_mult_memory_operand"
483 (match_code "mem")
484{
485 /* ??? Given how PUSH_MULT is generated in the prologues, is there
486 any point in testing for thumb1 specially? All of the variants
487 use the same form. */
488 if (TARGET_THUMB1)
489 {
490 /* ??? No attempt is made to represent STMIA, or validate that
491 the stack adjustment matches the register count. This is
492 true of the ARM/Thumb2 path as well. */
493 rtx x = XEXP (op, 0);
494 if (GET_CODE (x) != PRE_MODIFY)
495 return false;
496 if (XEXP (x, 0) != stack_pointer_rtx)
497 return false;
498 x = XEXP (x, 1);
499 if (GET_CODE (x) != PLUS)
500 return false;
501 if (XEXP (x, 0) != stack_pointer_rtx)
502 return false;
503 return CONST_INT_P (XEXP (x, 1));
504 }
505
506 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
507 return memory_operand (op, mode);
508})
509
a657c98a
RE
510;;-------------------------------------------------------------------------
511;;
512;; Thumb predicates
513;;
514
5b3e6663 515(define_predicate "thumb1_cmp_operand"
a657c98a
RE
516 (ior (and (match_code "reg,subreg")
517 (match_operand 0 "s_register_operand"))
518 (and (match_code "const_int")
519 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
520
5b3e6663 521(define_predicate "thumb1_cmpneg_operand"
a657c98a
RE
522 (and (match_code "const_int")
523 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
524
525;; Return TRUE if a result can be stored in OP without clobbering the
526;; condition code register. Prior to reload we only accept a
527;; register. After reload we have to be able to handle memory as
528;; well, since a pseudo may not get a hard reg and reload cannot
529;; handle output-reloads on jump insns.
530
531;; We could possibly handle mem before reload as well, but that might
532;; complicate things with the need to handle increment
533;; side-effects.
534(define_predicate "thumb_cbrch_target_operand"
535 (and (match_code "reg,subreg,mem")
536 (ior (match_operand 0 "s_register_operand")
537 (and (match_test "reload_in_progress || reload_completed")
538 (match_operand 0 "memory_operand")))))
539
540;;-------------------------------------------------------------------------
541;;
8fd03515 542;; iWMMXt predicates
dae840fc 543;;
8fd03515
XQ
544
545(define_predicate "imm_or_reg_operand"
546 (ior (match_operand 0 "immediate_operand")
547 (match_operand 0 "register_operand")))
a657c98a 548
88f77cba
JB
549;; Neon predicates
550
551(define_predicate "const_multiple_of_8_operand"
552 (match_code "const_int")
553{
554 unsigned HOST_WIDE_INT val = INTVAL (op);
555 return (val & 7) == 0;
556})
557
558(define_predicate "imm_for_neon_mov_operand"
00a3a76a 559 (match_code "const_vector,const_int")
88f77cba
JB
560{
561 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
562})
563
31a0c825
DP
564(define_predicate "imm_for_neon_lshift_operand"
565 (match_code "const_vector")
566{
567 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
568})
569
570(define_predicate "imm_for_neon_rshift_operand"
571 (match_code "const_vector")
572{
573 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
574})
575
576(define_predicate "imm_lshift_or_reg_neon"
577 (ior (match_operand 0 "s_register_operand")
578 (match_operand 0 "imm_for_neon_lshift_operand")))
579
580(define_predicate "imm_rshift_or_reg_neon"
581 (ior (match_operand 0 "s_register_operand")
582 (match_operand 0 "imm_for_neon_rshift_operand")))
583
73160ba9
DJ
584;; Predicates for named expanders that overlap multiple ISAs.
585
586(define_predicate "cmpdi_operand"
dae840fc
RE
587 (and (match_test "TARGET_32BIT")
588 (match_operand 0 "arm_di_operand")))
88f77cba 589
999a9cc5
MS
590;; True if the operand is memory reference suitable for a ldrex/strex.
591(define_predicate "arm_sync_memory_operand"
592 (and (match_operand 0 "memory_operand")
593 (match_code "reg" "0")))
594
46b57af1
TB
595;; Predicates for parallel expanders based on mode.
596(define_special_predicate "vect_par_constant_high"
597 (match_code "parallel")
598{
599 HOST_WIDE_INT count = XVECLEN (op, 0);
600 int i;
601 int base = GET_MODE_NUNITS (mode);
602
603 if ((count < 1)
604 || (count != base/2))
605 return false;
606
607 if (!VECTOR_MODE_P (mode))
608 return false;
609
610 for (i = 0; i < count; i++)
611 {
612 rtx elt = XVECEXP (op, 0, i);
613 int val;
614
d435a4be 615 if (!CONST_INT_P (elt))
46b57af1
TB
616 return false;
617
618 val = INTVAL (elt);
619 if (val != (base/2) + i)
620 return false;
621 }
622 return true;
623})
624
625(define_special_predicate "vect_par_constant_low"
626 (match_code "parallel")
627{
628 HOST_WIDE_INT count = XVECLEN (op, 0);
629 int i;
630 int base = GET_MODE_NUNITS (mode);
631
632 if ((count < 1)
633 || (count != base/2))
634 return false;
635
636 if (!VECTOR_MODE_P (mode))
637 return false;
638
639 for (i = 0; i < count; i++)
640 {
641 rtx elt = XVECEXP (op, 0, i);
642 int val;
643
d435a4be 644 if (!CONST_INT_P (elt))
46b57af1
TB
645 return false;
646
647 val = INTVAL (elt);
648 if (val != i)
649 return false;
650 }
651 return true;
652})
6308e208 653
7f3d8f56
RR
654(define_predicate "const_double_vcvt_power_of_two_reciprocal"
655 (and (match_code "const_double")
c75d51aa
RL
656 (match_test "TARGET_32BIT && TARGET_VFP
657 && vfp3_const_double_for_fract_bits (op)")))
658
659(define_predicate "const_double_vcvt_power_of_two"
660 (and (match_code "const_double")
661 (match_test "TARGET_32BIT && TARGET_VFP
662 && vfp3_const_double_for_bits (op)")))
7f3d8f56 663
12c4ecb1 664(define_predicate "neon_struct_operand"
6308e208 665 (and (match_code "mem")
33255ae3 666 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
9a1ea4b9 667
33255ae3
JB
668(define_predicate "neon_permissive_struct_operand"
669 (and (match_code "mem")
670 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
671
672(define_predicate "neon_perm_struct_or_reg_operand"
673 (ior (match_operand 0 "neon_permissive_struct_operand")
12c4ecb1
RS
674 (match_operand 0 "s_register_operand")))
675
9a1ea4b9
RR
676(define_special_predicate "add_operator"
677 (match_code "plus"))
18f0fe6b
RH
678
679(define_predicate "mem_noofs_operand"
680 (and (match_code "mem")
681 (match_code "reg" "0")))
9adcfa3c
RR
682
683(define_predicate "call_insn_operand"
10432733
JW
684 (ior (and (match_code "symbol_ref")
685 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
9adcfa3c 686 (match_operand 0 "s_register_operand")))