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a657c98a | 1 | ;; Predicate definitions for ARM and Thumb |
d652f226 | 2 | ;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc. |
a657c98a RE |
3 | ;; Contributed by ARM Ltd. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
a657c98a RE |
10 | ;; option) any later version. |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
a657c98a RE |
20 | |
21 | (define_predicate "s_register_operand" | |
22 | (match_code "reg,subreg") | |
23 | { | |
24 | if (GET_CODE (op) == SUBREG) | |
25 | op = SUBREG_REG (op); | |
26 | /* We don't consider registers whose class is NO_REGS | |
27 | to be a register operand. */ | |
28 | /* XXX might have to check for lo regs only for thumb ??? */ | |
29 | return (GET_CODE (op) == REG | |
30 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
31 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
32 | }) | |
33 | ||
34 | ;; Any hard register. | |
35 | (define_predicate "arm_hard_register_operand" | |
36 | (match_code "reg") | |
37 | { | |
38 | return REGNO (op) < FIRST_PSEUDO_REGISTER; | |
39 | }) | |
40 | ||
5b3e6663 PB |
41 | ;; A low register. |
42 | (define_predicate "low_register_operand" | |
43 | (and (match_code "reg") | |
44 | (match_test "REGNO (op) <= LAST_LO_REGNUM"))) | |
45 | ||
46 | ;; A low register or const_int. | |
47 | (define_predicate "low_reg_or_int_operand" | |
48 | (ior (match_code "const_int") | |
49 | (match_operand 0 "low_register_operand"))) | |
50 | ||
a657c98a RE |
51 | ;; Any core register, or any pseudo. */ |
52 | (define_predicate "arm_general_register_operand" | |
53 | (match_code "reg,subreg") | |
54 | { | |
55 | if (GET_CODE (op) == SUBREG) | |
56 | op = SUBREG_REG (op); | |
57 | ||
58 | return (GET_CODE (op) == REG | |
59 | && (REGNO (op) <= LAST_ARM_REGNUM | |
60 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
61 | }) | |
62 | ||
63 | (define_predicate "f_register_operand" | |
64 | (match_code "reg,subreg") | |
65 | { | |
66 | if (GET_CODE (op) == SUBREG) | |
67 | op = SUBREG_REG (op); | |
68 | ||
69 | /* We don't consider registers whose class is NO_REGS | |
70 | to be a register operand. */ | |
71 | return (GET_CODE (op) == REG | |
72 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
73 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); | |
74 | }) | |
75 | ||
4e6f5666 JZ |
76 | (define_predicate "vfp_register_operand" |
77 | (match_code "reg,subreg") | |
78 | { | |
79 | if (GET_CODE (op) == SUBREG) | |
80 | op = SUBREG_REG (op); | |
81 | ||
82 | /* We don't consider registers whose class is NO_REGS | |
83 | to be a register operand. */ | |
84 | return (GET_CODE (op) == REG | |
85 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
34db4735 | 86 | || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS |
4e6f5666 JZ |
87 | || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS |
88 | || (TARGET_VFPD32 | |
89 | && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); | |
90 | }) | |
91 | ||
fa01135d RE |
92 | (define_special_predicate "subreg_lowpart_operator" |
93 | (and (match_code "subreg") | |
94 | (match_test "subreg_lowpart_p (op)"))) | |
95 | ||
a657c98a RE |
96 | ;; Reg, subreg(reg) or const_int. |
97 | (define_predicate "reg_or_int_operand" | |
98 | (ior (match_code "const_int") | |
99 | (match_operand 0 "s_register_operand"))) | |
100 | ||
101 | (define_predicate "arm_immediate_operand" | |
102 | (and (match_code "const_int") | |
103 | (match_test "const_ok_for_arm (INTVAL (op))"))) | |
104 | ||
73160ba9 DJ |
105 | ;; A constant value which fits into two instructions, each taking |
106 | ;; an arithmetic constant operand for one of the words. | |
107 | (define_predicate "arm_immediate_di_operand" | |
108 | (and (match_code "const_int,const_double") | |
109 | (match_test "arm_const_double_by_immediates (op)"))) | |
110 | ||
a657c98a RE |
111 | (define_predicate "arm_neg_immediate_operand" |
112 | (and (match_code "const_int") | |
113 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | |
114 | ||
115 | (define_predicate "arm_not_immediate_operand" | |
116 | (and (match_code "const_int") | |
117 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | |
118 | ||
f0c6475a BS |
119 | (define_predicate "const0_operand" |
120 | (and (match_code "const_int") | |
121 | (match_test "INTVAL (op) == 0"))) | |
122 | ||
a657c98a RE |
123 | ;; Something valid on the RHS of an ARM data-processing instruction |
124 | (define_predicate "arm_rhs_operand" | |
125 | (ior (match_operand 0 "s_register_operand") | |
126 | (match_operand 0 "arm_immediate_operand"))) | |
127 | ||
128 | (define_predicate "arm_rhsm_operand" | |
129 | (ior (match_operand 0 "arm_rhs_operand") | |
130 | (match_operand 0 "memory_operand"))) | |
131 | ||
55cdadd5 AS |
132 | ;; This doesn't have to do much because the constant is already checked |
133 | ;; in the shift_operator predicate. | |
c29e2982 BS |
134 | (define_predicate "shift_amount_operand" |
135 | (ior (and (match_test "TARGET_ARM") | |
136 | (match_operand 0 "s_register_operand")) | |
55cdadd5 | 137 | (match_operand 0 "const_int_operand"))) |
c29e2982 | 138 | |
a657c98a RE |
139 | (define_predicate "arm_add_operand" |
140 | (ior (match_operand 0 "arm_rhs_operand") | |
141 | (match_operand 0 "arm_neg_immediate_operand"))) | |
142 | ||
143 | (define_predicate "arm_addimm_operand" | |
144 | (ior (match_operand 0 "arm_immediate_operand") | |
145 | (match_operand 0 "arm_neg_immediate_operand"))) | |
146 | ||
147 | (define_predicate "arm_not_operand" | |
148 | (ior (match_operand 0 "arm_rhs_operand") | |
149 | (match_operand 0 "arm_not_immediate_operand"))) | |
150 | ||
73160ba9 DJ |
151 | (define_predicate "arm_di_operand" |
152 | (ior (match_operand 0 "s_register_operand") | |
153 | (match_operand 0 "arm_immediate_di_operand"))) | |
154 | ||
a657c98a RE |
155 | ;; True if the operand is a memory reference which contains an |
156 | ;; offsettable address. | |
157 | (define_predicate "offsettable_memory_operand" | |
158 | (and (match_code "mem") | |
159 | (match_test | |
160 | "offsettable_address_p (reload_completed | reload_in_progress, | |
161 | mode, XEXP (op, 0))"))) | |
162 | ||
e6add59b RS |
163 | ;; True if the operand is a memory operand that does not have an |
164 | ;; automodified base register (and thus will not generate output reloads). | |
165 | (define_predicate "call_memory_operand" | |
166 | (and (match_code "mem") | |
167 | (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) | |
168 | != RTX_AUTOINC") | |
169 | (match_operand 0 "memory_operand")))) | |
170 | ||
a657c98a | 171 | (define_predicate "arm_reload_memory_operand" |
9d2da95b | 172 | (and (match_code "mem,reg,subreg") |
a657c98a RE |
173 | (match_test "(!CONSTANT_P (op) |
174 | && (true_regnum(op) == -1 | |
175 | || (GET_CODE (op) == REG | |
176 | && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) | |
177 | ||
178 | ;; True for valid operands for the rhs of an floating point insns. | |
179 | ;; Allows regs or certain consts on FPA, just regs for everything else. | |
180 | (define_predicate "arm_float_rhs_operand" | |
181 | (ior (match_operand 0 "s_register_operand") | |
182 | (and (match_code "const_double") | |
183 | (match_test "TARGET_FPA && arm_const_double_rtx (op)")))) | |
184 | ||
185 | (define_predicate "arm_float_add_operand" | |
186 | (ior (match_operand 0 "arm_float_rhs_operand") | |
187 | (and (match_code "const_double") | |
188 | (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)")))) | |
189 | ||
190 | (define_predicate "vfp_compare_operand" | |
191 | (ior (match_operand 0 "s_register_operand") | |
192 | (and (match_code "const_double") | |
193 | (match_test "arm_const_double_rtx (op)")))) | |
194 | ||
195 | (define_predicate "arm_float_compare_operand" | |
196 | (if_then_else (match_test "TARGET_VFP") | |
197 | (match_operand 0 "vfp_compare_operand") | |
198 | (match_operand 0 "arm_float_rhs_operand"))) | |
199 | ||
200 | ;; True for valid index operands. | |
201 | (define_predicate "index_operand" | |
202 | (ior (match_operand 0 "s_register_operand") | |
203 | (and (match_operand 0 "immediate_operand") | |
204 | (match_test "(GET_CODE (op) != CONST_INT | |
205 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) | |
206 | ||
207 | ;; True for operators that can be combined with a shift in ARM state. | |
208 | (define_special_predicate "shiftable_operator" | |
209 | (and (match_code "plus,minus,ior,xor,and") | |
210 | (match_test "mode == GET_MODE (op)"))) | |
211 | ||
c112cf2b | 212 | ;; True for logical binary operators. |
a657c98a RE |
213 | (define_special_predicate "logical_binary_operator" |
214 | (and (match_code "ior,xor,and") | |
215 | (match_test "mode == GET_MODE (op)"))) | |
216 | ||
37119410 BS |
217 | ;; True for commutative operators |
218 | (define_special_predicate "commutative_binary_operator" | |
219 | (and (match_code "ior,xor,and,plus") | |
220 | (match_test "mode == GET_MODE (op)"))) | |
221 | ||
a657c98a | 222 | ;; True for shift operators. |
55cdadd5 AS |
223 | ;; Notes: |
224 | ;; * mult is only permitted with a constant shift amount | |
225 | ;; * patterns that permit register shift amounts only in ARM mode use | |
226 | ;; shift_amount_operand, patterns that always allow registers do not, | |
227 | ;; so we don't have to worry about that sort of thing here. | |
a657c98a RE |
228 | (define_special_predicate "shift_operator" |
229 | (and (ior (ior (and (match_code "mult") | |
230 | (match_test "power_of_two_operand (XEXP (op, 1), mode)")) | |
231 | (and (match_code "rotate") | |
232 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
233 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
55cdadd5 AS |
234 | (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
235 | (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT | |
236 | || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) | |
a657c98a RE |
237 | (match_test "mode == GET_MODE (op)"))) |
238 | ||
655b30bf JB |
239 | ;; True for shift operators which can be used with saturation instructions. |
240 | (define_special_predicate "sat_shift_operator" | |
241 | (and (match_code "ashift,ashiftrt") | |
242 | (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT | |
243 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) <= 32)") | |
244 | (match_test "mode == GET_MODE (op)"))) | |
245 | ||
c29e2982 BS |
246 | ;; True for MULT, to identify which variant of shift_operator is in use. |
247 | (define_special_predicate "mult_operator" | |
248 | (match_code "mult")) | |
249 | ||
5b3e6663 PB |
250 | ;; True for operators that have 16-bit thumb variants. */ |
251 | (define_special_predicate "thumb_16bit_operator" | |
252 | (match_code "plus,minus,and,ior,xor")) | |
253 | ||
a657c98a RE |
254 | ;; True for EQ & NE |
255 | (define_special_predicate "equality_operator" | |
256 | (match_code "eq,ne")) | |
257 | ||
f90b7a5a PB |
258 | ;; True for integer comparisons and, if FP is active, for comparisons |
259 | ;; other than LTGT or UNEQ. | |
aa0b3f8f RS |
260 | (define_special_predicate "expandable_comparison_operator" |
261 | (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | |
262 | unordered,ordered,unlt,unle,unge,ungt")) | |
263 | ||
264 | ;; Likewise, but only accept comparisons that are directly supported | |
265 | ;; by ARM condition codes. | |
a657c98a | 266 | (define_special_predicate "arm_comparison_operator" |
aa0b3f8f | 267 | (and (match_operand 0 "expandable_comparison_operator") |
723d95fe | 268 | (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) |
a657c98a | 269 | |
f0c6475a BS |
270 | (define_special_predicate "lt_ge_comparison_operator" |
271 | (match_code "lt,ge")) | |
272 | ||
906668bb BS |
273 | (define_special_predicate "noov_comparison_operator" |
274 | (match_code "lt,ge,eq,ne")) | |
275 | ||
a657c98a RE |
276 | (define_special_predicate "minmax_operator" |
277 | (and (match_code "smin,smax,umin,umax") | |
278 | (match_test "mode == GET_MODE (op)"))) | |
279 | ||
280 | (define_special_predicate "cc_register" | |
281 | (and (match_code "reg") | |
282 | (and (match_test "REGNO (op) == CC_REGNUM") | |
283 | (ior (match_test "mode == GET_MODE (op)") | |
284 | (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) | |
285 | ||
286 | (define_special_predicate "dominant_cc_register" | |
287 | (match_code "reg") | |
288 | { | |
289 | if (mode == VOIDmode) | |
290 | { | |
291 | mode = GET_MODE (op); | |
292 | ||
293 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
294 | return false; | |
295 | } | |
296 | ||
297 | return (cc_register (op, mode) | |
298 | && (mode == CC_DNEmode | |
299 | || mode == CC_DEQmode | |
300 | || mode == CC_DLEmode | |
301 | || mode == CC_DLTmode | |
302 | || mode == CC_DGEmode | |
303 | || mode == CC_DGTmode | |
304 | || mode == CC_DLEUmode | |
305 | || mode == CC_DLTUmode | |
306 | || mode == CC_DGEUmode | |
307 | || mode == CC_DGTUmode)); | |
308 | }) | |
309 | ||
310 | (define_special_predicate "arm_extendqisi_mem_op" | |
311 | (and (match_operand 0 "memory_operand") | |
8d4f1548 RR |
312 | (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, |
313 | XEXP (op, 0), | |
314 | SIGN_EXTEND, | |
315 | 0) | |
316 | : memory_address_p (QImode, XEXP (op, 0))"))) | |
a657c98a | 317 | |
01577df7 RE |
318 | (define_special_predicate "arm_reg_or_extendqisi_mem_op" |
319 | (ior (match_operand 0 "arm_extendqisi_mem_op") | |
320 | (match_operand 0 "s_register_operand"))) | |
321 | ||
a657c98a RE |
322 | (define_predicate "power_of_two_operand" |
323 | (match_code "const_int") | |
324 | { | |
29b40d79 | 325 | unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; |
a657c98a RE |
326 | |
327 | return value != 0 && (value & (value - 1)) == 0; | |
328 | }) | |
329 | ||
330 | (define_predicate "nonimmediate_di_operand" | |
331 | (match_code "reg,subreg,mem") | |
332 | { | |
333 | if (s_register_operand (op, mode)) | |
334 | return true; | |
335 | ||
336 | if (GET_CODE (op) == SUBREG) | |
337 | op = SUBREG_REG (op); | |
338 | ||
339 | return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); | |
340 | }) | |
341 | ||
342 | (define_predicate "di_operand" | |
343 | (ior (match_code "const_int,const_double") | |
344 | (and (match_code "reg,subreg,mem") | |
345 | (match_operand 0 "nonimmediate_di_operand")))) | |
346 | ||
347 | (define_predicate "nonimmediate_soft_df_operand" | |
348 | (match_code "reg,subreg,mem") | |
349 | { | |
350 | if (s_register_operand (op, mode)) | |
351 | return true; | |
352 | ||
353 | if (GET_CODE (op) == SUBREG) | |
354 | op = SUBREG_REG (op); | |
355 | ||
356 | return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); | |
357 | }) | |
358 | ||
359 | (define_predicate "soft_df_operand" | |
360 | (ior (match_code "const_double") | |
361 | (and (match_code "reg,subreg,mem") | |
362 | (match_operand 0 "nonimmediate_soft_df_operand")))) | |
363 | ||
a657c98a RE |
364 | (define_special_predicate "load_multiple_operation" |
365 | (match_code "parallel") | |
366 | { | |
367 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
37119410 | 368 | unsigned dest_regno; |
a657c98a RE |
369 | rtx src_addr; |
370 | HOST_WIDE_INT i = 1, base = 0; | |
37119410 | 371 | HOST_WIDE_INT offset = 0; |
a657c98a | 372 | rtx elt; |
37119410 BS |
373 | bool addr_reg_loaded = false; |
374 | bool update = false; | |
a657c98a RE |
375 | |
376 | if (count <= 1 | |
37119410 BS |
377 | || GET_CODE (XVECEXP (op, 0, 0)) != SET |
378 | || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))) | |
a657c98a RE |
379 | return false; |
380 | ||
381 | /* Check to see if this might be a write-back. */ | |
382 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) | |
383 | { | |
384 | i++; | |
385 | base = 1; | |
37119410 | 386 | update = true; |
a657c98a RE |
387 | |
388 | /* Now check it more carefully. */ | |
389 | if (GET_CODE (SET_DEST (elt)) != REG | |
390 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
391 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
392 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) | |
393 | return false; | |
394 | } | |
395 | ||
396 | /* Perform a quick check so we don't blow up below. */ | |
397 | if (count <= i | |
398 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
399 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
400 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
401 | return false; | |
402 | ||
403 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
404 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
37119410 BS |
405 | if (GET_CODE (src_addr) == PLUS) |
406 | { | |
407 | if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT) | |
408 | return false; | |
409 | offset = INTVAL (XEXP (src_addr, 1)); | |
410 | src_addr = XEXP (src_addr, 0); | |
411 | } | |
412 | if (!REG_P (src_addr)) | |
413 | return false; | |
a657c98a RE |
414 | |
415 | for (; i < count; i++) | |
416 | { | |
417 | elt = XVECEXP (op, 0, i); | |
418 | ||
419 | if (GET_CODE (elt) != SET | |
420 | || GET_CODE (SET_DEST (elt)) != REG | |
421 | || GET_MODE (SET_DEST (elt)) != SImode | |
37119410 | 422 | || REGNO (SET_DEST (elt)) <= dest_regno |
a657c98a RE |
423 | || GET_CODE (SET_SRC (elt)) != MEM |
424 | || GET_MODE (SET_SRC (elt)) != SImode | |
37119410 BS |
425 | || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS |
426 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
427 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
428 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4) | |
429 | && (!REG_P (XEXP (SET_SRC (elt), 0)) | |
430 | || offset + (i - base) * 4 != 0))) | |
a657c98a | 431 | return false; |
37119410 BS |
432 | dest_regno = REGNO (SET_DEST (elt)); |
433 | if (dest_regno == REGNO (src_addr)) | |
434 | addr_reg_loaded = true; | |
a657c98a | 435 | } |
37119410 BS |
436 | /* For Thumb, we only have updating instructions. If the pattern does |
437 | not describe an update, it must be because the address register is | |
438 | in the list of loaded registers - on the hardware, this has the effect | |
439 | of overriding the update. */ | |
440 | if (update && addr_reg_loaded) | |
441 | return false; | |
442 | if (TARGET_THUMB1) | |
443 | return update || addr_reg_loaded; | |
a657c98a RE |
444 | return true; |
445 | }) | |
446 | ||
447 | (define_special_predicate "store_multiple_operation" | |
448 | (match_code "parallel") | |
449 | { | |
450 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
37119410 | 451 | unsigned src_regno; |
a657c98a | 452 | rtx dest_addr; |
37119410 | 453 | HOST_WIDE_INT i = 1, base = 0, offset = 0; |
a657c98a RE |
454 | rtx elt; |
455 | ||
456 | if (count <= 1 | |
457 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
458 | return false; | |
459 | ||
460 | /* Check to see if this might be a write-back. */ | |
461 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) | |
462 | { | |
463 | i++; | |
464 | base = 1; | |
465 | ||
466 | /* Now check it more carefully. */ | |
467 | if (GET_CODE (SET_DEST (elt)) != REG | |
468 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
469 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
470 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) | |
471 | return false; | |
472 | } | |
473 | ||
474 | /* Perform a quick check so we don't blow up below. */ | |
475 | if (count <= i | |
476 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
477 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
478 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
479 | return false; | |
480 | ||
481 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
482 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
483 | ||
37119410 BS |
484 | if (GET_CODE (dest_addr) == PLUS) |
485 | { | |
486 | if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT) | |
487 | return false; | |
488 | offset = INTVAL (XEXP (dest_addr, 1)); | |
489 | dest_addr = XEXP (dest_addr, 0); | |
490 | } | |
491 | if (!REG_P (dest_addr)) | |
492 | return false; | |
493 | ||
a657c98a RE |
494 | for (; i < count; i++) |
495 | { | |
496 | elt = XVECEXP (op, 0, i); | |
497 | ||
498 | if (GET_CODE (elt) != SET | |
499 | || GET_CODE (SET_SRC (elt)) != REG | |
500 | || GET_MODE (SET_SRC (elt)) != SImode | |
37119410 | 501 | || REGNO (SET_SRC (elt)) <= src_regno |
a657c98a RE |
502 | || GET_CODE (SET_DEST (elt)) != MEM |
503 | || GET_MODE (SET_DEST (elt)) != SImode | |
37119410 BS |
504 | || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS |
505 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
506 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
507 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4) | |
508 | && (!REG_P (XEXP (SET_DEST (elt), 0)) | |
509 | || offset + (i - base) * 4 != 0))) | |
a657c98a | 510 | return false; |
37119410 | 511 | src_regno = REGNO (SET_SRC (elt)); |
a657c98a RE |
512 | } |
513 | ||
514 | return true; | |
515 | }) | |
516 | ||
517 | (define_special_predicate "multi_register_push" | |
518 | (match_code "parallel") | |
519 | { | |
520 | if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
521 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
522 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) | |
523 | return false; | |
524 | ||
525 | return true; | |
526 | }) | |
527 | ||
d018b46e RH |
528 | (define_predicate "push_mult_memory_operand" |
529 | (match_code "mem") | |
530 | { | |
531 | /* ??? Given how PUSH_MULT is generated in the prologues, is there | |
532 | any point in testing for thumb1 specially? All of the variants | |
533 | use the same form. */ | |
534 | if (TARGET_THUMB1) | |
535 | { | |
536 | /* ??? No attempt is made to represent STMIA, or validate that | |
537 | the stack adjustment matches the register count. This is | |
538 | true of the ARM/Thumb2 path as well. */ | |
539 | rtx x = XEXP (op, 0); | |
540 | if (GET_CODE (x) != PRE_MODIFY) | |
541 | return false; | |
542 | if (XEXP (x, 0) != stack_pointer_rtx) | |
543 | return false; | |
544 | x = XEXP (x, 1); | |
545 | if (GET_CODE (x) != PLUS) | |
546 | return false; | |
547 | if (XEXP (x, 0) != stack_pointer_rtx) | |
548 | return false; | |
549 | return CONST_INT_P (XEXP (x, 1)); | |
550 | } | |
551 | ||
552 | /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ | |
553 | return memory_operand (op, mode); | |
554 | }) | |
555 | ||
a657c98a RE |
556 | ;;------------------------------------------------------------------------- |
557 | ;; | |
558 | ;; Thumb predicates | |
559 | ;; | |
560 | ||
5b3e6663 | 561 | (define_predicate "thumb1_cmp_operand" |
a657c98a RE |
562 | (ior (and (match_code "reg,subreg") |
563 | (match_operand 0 "s_register_operand")) | |
564 | (and (match_code "const_int") | |
565 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256")))) | |
566 | ||
5b3e6663 | 567 | (define_predicate "thumb1_cmpneg_operand" |
a657c98a RE |
568 | (and (match_code "const_int") |
569 | (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) | |
570 | ||
571 | ;; Return TRUE if a result can be stored in OP without clobbering the | |
572 | ;; condition code register. Prior to reload we only accept a | |
573 | ;; register. After reload we have to be able to handle memory as | |
574 | ;; well, since a pseudo may not get a hard reg and reload cannot | |
575 | ;; handle output-reloads on jump insns. | |
576 | ||
577 | ;; We could possibly handle mem before reload as well, but that might | |
578 | ;; complicate things with the need to handle increment | |
579 | ;; side-effects. | |
580 | (define_predicate "thumb_cbrch_target_operand" | |
581 | (and (match_code "reg,subreg,mem") | |
582 | (ior (match_operand 0 "s_register_operand") | |
583 | (and (match_test "reload_in_progress || reload_completed") | |
584 | (match_operand 0 "memory_operand"))))) | |
585 | ||
586 | ;;------------------------------------------------------------------------- | |
587 | ;; | |
588 | ;; MAVERICK predicates | |
589 | ;; | |
590 | ||
591 | (define_predicate "cirrus_register_operand" | |
592 | (match_code "reg,subreg") | |
593 | { | |
594 | if (GET_CODE (op) == SUBREG) | |
595 | op = SUBREG_REG (op); | |
596 | ||
597 | return (GET_CODE (op) == REG | |
598 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
599 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
600 | }) | |
601 | ||
602 | (define_predicate "cirrus_fp_register" | |
603 | (match_code "reg,subreg") | |
604 | { | |
605 | if (GET_CODE (op) == SUBREG) | |
606 | op = SUBREG_REG (op); | |
607 | ||
608 | return (GET_CODE (op) == REG | |
609 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
610 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
611 | }) | |
612 | ||
613 | (define_predicate "cirrus_shift_const" | |
614 | (and (match_code "const_int") | |
615 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64"))) | |
616 | ||
617 | ||
88f77cba JB |
618 | ;; Neon predicates |
619 | ||
620 | (define_predicate "const_multiple_of_8_operand" | |
621 | (match_code "const_int") | |
622 | { | |
623 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
624 | return (val & 7) == 0; | |
625 | }) | |
626 | ||
627 | (define_predicate "imm_for_neon_mov_operand" | |
628 | (match_code "const_vector") | |
629 | { | |
630 | return neon_immediate_valid_for_move (op, mode, NULL, NULL); | |
631 | }) | |
632 | ||
31a0c825 DP |
633 | (define_predicate "imm_for_neon_lshift_operand" |
634 | (match_code "const_vector") | |
635 | { | |
636 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); | |
637 | }) | |
638 | ||
639 | (define_predicate "imm_for_neon_rshift_operand" | |
640 | (match_code "const_vector") | |
641 | { | |
642 | return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); | |
643 | }) | |
644 | ||
645 | (define_predicate "imm_lshift_or_reg_neon" | |
646 | (ior (match_operand 0 "s_register_operand") | |
647 | (match_operand 0 "imm_for_neon_lshift_operand"))) | |
648 | ||
649 | (define_predicate "imm_rshift_or_reg_neon" | |
650 | (ior (match_operand 0 "s_register_operand") | |
651 | (match_operand 0 "imm_for_neon_rshift_operand"))) | |
652 | ||
88f77cba JB |
653 | (define_predicate "imm_for_neon_logic_operand" |
654 | (match_code "const_vector") | |
655 | { | |
b3b7bbce SL |
656 | return (TARGET_NEON |
657 | && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | |
88f77cba JB |
658 | }) |
659 | ||
660 | (define_predicate "imm_for_neon_inv_logic_operand" | |
661 | (match_code "const_vector") | |
662 | { | |
b3b7bbce SL |
663 | return (TARGET_NEON |
664 | && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | |
88f77cba JB |
665 | }) |
666 | ||
667 | (define_predicate "neon_logic_op2" | |
668 | (ior (match_operand 0 "imm_for_neon_logic_operand") | |
669 | (match_operand 0 "s_register_operand"))) | |
670 | ||
671 | (define_predicate "neon_inv_logic_op2" | |
672 | (ior (match_operand 0 "imm_for_neon_inv_logic_operand") | |
673 | (match_operand 0 "s_register_operand"))) | |
674 | ||
675 | ;; TODO: We could check lane numbers more precisely based on the mode. | |
676 | (define_predicate "neon_lane_number" | |
677 | (and (match_code "const_int") | |
3460fdf3 | 678 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))) |
73160ba9 DJ |
679 | ;; Predicates for named expanders that overlap multiple ISAs. |
680 | ||
681 | (define_predicate "cmpdi_operand" | |
682 | (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") | |
683 | (and (match_test "TARGET_ARM") | |
684 | (match_operand 0 "cirrus_fp_register")) | |
685 | (and (match_test "TARGET_32BIT") | |
686 | (match_operand 0 "arm_di_operand")))) | |
88f77cba | 687 | |
999a9cc5 MS |
688 | ;; True if the operand is memory reference suitable for a ldrex/strex. |
689 | (define_predicate "arm_sync_memory_operand" | |
690 | (and (match_operand 0 "memory_operand") | |
691 | (match_code "reg" "0"))) | |
692 | ||
46b57af1 TB |
693 | ;; Predicates for parallel expanders based on mode. |
694 | (define_special_predicate "vect_par_constant_high" | |
695 | (match_code "parallel") | |
696 | { | |
697 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
698 | int i; | |
699 | int base = GET_MODE_NUNITS (mode); | |
700 | ||
701 | if ((count < 1) | |
702 | || (count != base/2)) | |
703 | return false; | |
704 | ||
705 | if (!VECTOR_MODE_P (mode)) | |
706 | return false; | |
707 | ||
708 | for (i = 0; i < count; i++) | |
709 | { | |
710 | rtx elt = XVECEXP (op, 0, i); | |
711 | int val; | |
712 | ||
713 | if (GET_CODE (elt) != CONST_INT) | |
714 | return false; | |
715 | ||
716 | val = INTVAL (elt); | |
717 | if (val != (base/2) + i) | |
718 | return false; | |
719 | } | |
720 | return true; | |
721 | }) | |
722 | ||
723 | (define_special_predicate "vect_par_constant_low" | |
724 | (match_code "parallel") | |
725 | { | |
726 | HOST_WIDE_INT count = XVECLEN (op, 0); | |
727 | int i; | |
728 | int base = GET_MODE_NUNITS (mode); | |
729 | ||
730 | if ((count < 1) | |
731 | || (count != base/2)) | |
732 | return false; | |
733 | ||
734 | if (!VECTOR_MODE_P (mode)) | |
735 | return false; | |
736 | ||
737 | for (i = 0; i < count; i++) | |
738 | { | |
739 | rtx elt = XVECEXP (op, 0, i); | |
740 | int val; | |
741 | ||
742 | if (GET_CODE (elt) != CONST_INT) | |
743 | return false; | |
744 | ||
745 | val = INTVAL (elt); | |
746 | if (val != i) | |
747 | return false; | |
748 | } | |
749 | return true; | |
750 | }) | |
6308e208 | 751 | |
12c4ecb1 | 752 | (define_predicate "neon_struct_operand" |
6308e208 RS |
753 | (and (match_code "mem") |
754 | (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) | |
9a1ea4b9 | 755 | |
12c4ecb1 RS |
756 | (define_predicate "neon_struct_or_register_operand" |
757 | (ior (match_operand 0 "neon_struct_operand") | |
758 | (match_operand 0 "s_register_operand"))) | |
759 | ||
9a1ea4b9 RR |
760 | (define_special_predicate "add_operator" |
761 | (match_code "plus")) |