]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/arm/t-aprofile
t-aprofile: Add cortex-a15.cortex-a7, cortex-a12, cortex-a57, cortex-a57.cortex-a53.
[thirdparty/gcc.git] / gcc / config / arm / t-aprofile
CommitLineData
c9acb877
MGD
1# Copyright (C) 2012-2013 Free Software Foundation, Inc.
2#
3# This file is part of GCC.
4#
5# GCC is free software; you can redistribute it and/or modify
6# it under the terms of the GNU General Public License as published by
7# the Free Software Foundation; either version 3, or (at your option)
8# any later version.
9#
10# GCC is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with GCC; see the file COPYING3. If not see
17# <http://www.gnu.org/licenses/>.
18
19# This is a target makefile fragment that attempts to get
20# multilibs built for the range of CPU's, FPU's and ABI's that
21# are relevant for the A-profile architecture. It should
22# not be used in conjunction with another make file fragment and
23# assumes --with-arch, --with-cpu, --with-fpu, --with-float, --with-mode
24# have their default values during the configure step. We enforce
25# this during the top-level configury.
26
27MULTILIB_OPTIONS =
28MULTILIB_DIRNAMES =
29MULTILIB_EXCEPTIONS =
30MULTILIB_MATCHES =
31MULTILIB_REUSE =
32
33# We have the following hierachy:
34# ISA: A32 (.) or T32 (thumb)
35# Architecture: ARMv7-A (v7-a), ARMv7VE (v7ve), or ARMv8-A (v8-a).
36# FPU: VFPv3-D16 (fpv3), NEONv1 (simdv1), VFPv4-D16 (fpv4),
37# NEON-VFPV4 (simdvfpv4), NEON for ARMv8 (simdv8), or None (.).
38# Float-abi: Soft (.), softfp (softfp), or hard (hardfp).
39
40# We use the option -mcpu=cortex-a7 because we do not yet have march=armv7ve
41# or march=armv7a+virt as a command line option for the compiler.
42MULTILIB_OPTIONS += mthumb
43MULTILIB_DIRNAMES += thumb
44
45MULTILIB_OPTIONS += march=armv7-a/mcpu=cortex-a7/march=armv8-a
46MULTILIB_DIRNAMES += v7-a v7ve v8-a
47
48MULTILIB_OPTIONS += mfpu=vfpv3-d16/mfpu=neon/mfpu=vfpv4-d16/mfpu=neon-vfpv4/mfpu=neon-fp-armv8
49MULTILIB_DIRNAMES += fpv3 simdv1 fpv4 simdvfpv4 simdv8
50
51MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard
52MULTILIB_DIRNAMES += softfp hard
53
54# We don't build no-float libraries with an FPU.
55MULTILIB_EXCEPTIONS += *mfpu=vfpv3-d16
56MULTILIB_EXCEPTIONS += *mfpu=neon
57MULTILIB_EXCEPTIONS += *mfpu=vfpv4-d16
58MULTILIB_EXCEPTIONS += *mfpu=neon-vfpv4
59MULTILIB_EXCEPTIONS += *mfpu=neon-fp-armv8
60
61# We don't build libraries requiring an FPU at the CPU/Arch/ISA level.
62MULTILIB_EXCEPTIONS += mfloat-abi=*
63MULTILIB_EXCEPTIONS += mfpu=*
64MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=*
65MULTILIB_EXCEPTIONS += mthumb/mfpu=*
66MULTILIB_EXCEPTIONS += *march=armv7-a/mfloat-abi=*
67MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/mfloat-abi=*
68MULTILIB_EXCEPTIONS += *march=armv8-a/mfloat-abi=*
69
70# Ensure the correct FPU variants apply to the correct base architectures.
71MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=vfpv3-d16*
72MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon/*
73MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv3-d16*
74MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon/*
75MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=vfpv4-d16*
76MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-vfpv4*
77MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv4-d16*
78MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon-vfpv4*
79MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-fp-armv8*
80MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon-fp-armv8*
81
82# CPU Matches
83MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8
84MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9
85MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5
0d78a2d4
JG
86MULTILIB_MATCHES += mcpu?cortex-a7=mcpu?cortex-a15=mcpu?cortex-a12
87MULTILIB_MATCHES += mcpu?cortex-a7=mcpu?cortex-a15.cortex-a7
c9acb877 88MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53
0d78a2d4
JG
89MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57
90MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53
c9acb877
MGD
91
92# FPU matches
93MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3
94MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
95MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16-d16
96MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?vfpv4
97MULTILIB_MATCHES += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8
98
99
100# Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a.
101# So if new CPUs are added above at the newer architecture levels,
102# do something to map them below here.
103# We take the approach of mapping down to v7-a regardless of what
104# the fp option is if the integer architecture brings things down.
105# This applies to any similar combination at the v7ve and v8-a arch
106# levels.
107
108MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard
109MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp
110MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard
111MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
112MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
113MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
114MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
115MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
116MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
117MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
118
119
120MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard
121MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp
122MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv8-a/mfpu.neon/mfloat-abi.hard
123MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv8-a/mfpu.neon/mfloat-abi.softfp
124MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard
125MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp
126MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard
127MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
128
129
130MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard
131MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp
132MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
133MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
134MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
135MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
136
137
138MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard
139MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp
140MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard
141MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp
142
143
144
145# And again for mthumb.
146
147MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard
148MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp
149MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard
150MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
151MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
152MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
153MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
154MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
155MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
156MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
157
158
159MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard
160MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp
161MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.hard
162MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.softfp
163MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard
164MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp
165MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard
166MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
167
168
169MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard
170MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp
171MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
172MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
173MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
174MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
175
176
177MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard
178MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp
179MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard
180MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp