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Commit | Line | Data |
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e15a9970 | 1 | ;; Instruction Classification for ARM for GNU compiler. |
2 | ||
f1717362 | 3 | ;; Copyright (C) 1991-2016 Free Software Foundation, Inc. |
e15a9970 | 4 | ;; Contributed by ARM Ltd. |
5 | ||
6 | ;; This file is part of GCC. | |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify it | |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 3, or (at your | |
11 | ;; option) any later version. | |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | ; TYPE attribute is used to classify instructions for use in scheduling. | |
23 | ; | |
24 | ; Instruction classification: | |
25 | ; | |
d82e788e | 26 | ; adc_imm add/subtract with carry and with an immediate operand. |
27 | ; adc_reg add/subtract with carry and no immediate operand. | |
28 | ; adcs_imm as adc_imm, setting condition flags. | |
29 | ; adcs_reg as adc_reg, setting condition flags. | |
30 | ; adr calculate address. | |
31 | ; alu_ext From ARMv8-A: any arithmetic instruction that has a | |
32 | ; sign/zero-extended. | |
33 | ; AArch64 Only. | |
34 | ; source operand | |
35 | ; alu_imm any arithmetic instruction that doesn't have a shifted | |
36 | ; operand and has an immediate operand. This | |
e15a9970 | 37 | ; excludes MOV, MVN and RSB(S) immediate. |
112eda6f | 38 | ; alu_sreg any arithmetic instruction that doesn't have a shifted |
d82e788e | 39 | ; or an immediate operand. This excludes |
112eda6f | 40 | ; MOV and MVN but includes MOVT. This also excludes |
41 | ; DSP-kind instructions. This is also the default. | |
d82e788e | 42 | ; alu_shift_imm any arithmetic instruction that has a source operand |
43 | ; shifted by a constant. This excludes simple shifts. | |
44 | ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a | |
e15a9970 | 45 | ; register. |
112eda6f | 46 | ; alu_dsp_reg any DSP-kind instruction like QSUB8. |
d82e788e | 47 | ; alus_ext From ARMv8-A: as alu_ext, setting condition flags. |
48 | ; AArch64 Only. | |
49 | ; alus_imm as alu_imm, setting condition flags. | |
112eda6f | 50 | ; alus_sreg as alu_sreg, setting condition flags. |
d82e788e | 51 | ; alus_shift_imm as alu_shift_imm, setting condition flags. |
52 | ; alus_shift_reg as alu_shift_reg, setting condition flags. | |
53 | ; bfm bitfield move operation. | |
e15a9970 | 54 | ; block blockage insn, this blocks all functional units. |
55 | ; branch branch. | |
56 | ; call subroutine call. | |
57 | ; clz count leading zeros (CLZ). | |
d82e788e | 58 | ; csel From ARMv8-A: conditional select. |
e15a9970 | 59 | ; extend extend instruction (SXTB, SXTH, UXTB, UXTH). |
d453f27a | 60 | ; f_cvt conversion between float representations. |
61 | ; f_cvtf2i conversion between float and integral types. | |
62 | ; f_cvti2f conversion between integral and float types. | |
e15a9970 | 63 | ; f_flag transfer of co-processor flags to the CPSR. |
64 | ; f_load[d,s] double/single load from memory. Used for VFP unit. | |
52432540 | 65 | ; f_mcr transfer arm to vfp reg. |
66 | ; f_mcrr transfer two arm regs to vfp reg. | |
e15a9970 | 67 | ; f_minmax[d,s] double/single floating point minimum/maximum. |
52432540 | 68 | ; f_mrc transfer vfp to arm reg. |
69 | ; f_mrrc transfer vfp to two arm regs. | |
e15a9970 | 70 | ; f_rint[d,s] double/single floating point rount to integral. |
e15a9970 | 71 | ; f_store[d,s] double/single store to memory. Used for VFP unit. |
72 | ; fadd[d,s] double/single floating-point scalar addition. | |
73 | ; fcmp[d,s] double/single floating-point compare. | |
74 | ; fconst[d,s] double/single load immediate. | |
d82e788e | 75 | ; fcsel From ARMv8-A: Floating-point conditional select. |
e15a9970 | 76 | ; fdiv[d,s] double/single precision floating point division. |
77 | ; ffarith[d,s] double/single floating point abs/neg/cpy. | |
78 | ; ffma[d,s] double/single floating point fused multiply-accumulate. | |
79 | ; float floating point arithmetic operation. | |
80 | ; fmac[d,s] double/single floating point multiply-accumulate. | |
57a7b13e | 81 | ; fmov floating point to floating point register move. |
e15a9970 | 82 | ; fmul[d,s] double/single floating point multiply. |
e62582b3 | 83 | ; fsqrt[d,s] double/single precision floating point square root. |
062447bb | 84 | ; load_acq load-acquire. |
e15a9970 | 85 | ; load_byte load byte(s) from memory to arm registers. |
86 | ; load1 load 1 word from memory to arm registers. | |
87 | ; load2 load 2 words from memory to arm registers. | |
88 | ; load3 load 3 words from memory to arm registers. | |
89 | ; load4 load 4 words from memory to arm registers. | |
d82e788e | 90 | ; logic_imm any logical instruction that doesn't have a shifted |
91 | ; operand and has an immediate operand. | |
92 | ; logic_reg any logical instruction that doesn't have a shifted | |
93 | ; operand or an immediate operand. | |
94 | ; logic_shift_imm any logical instruction that has a source operand | |
95 | ; shifted by a constant. This excludes simple shifts. | |
96 | ; logic_shift_reg as logic_shift_imm, with the shift amount specified in a | |
97 | ; register. | |
98 | ; logics_imm as logic_imm, setting condition flags. | |
99 | ; logics_reg as logic_reg, setting condition flags. | |
100 | ; logics_shift_imm as logic_shift_imm, setting condition flags. | |
101 | ; logics_shift_reg as logic_shift_reg, setting condition flags. | |
e15a9970 | 102 | ; mla integer multiply accumulate. |
103 | ; mlas integer multiply accumulate, flag setting. | |
104 | ; mov_imm simple MOV instruction that moves an immediate to | |
105 | ; register. This includes MOVW, but not MOVT. | |
106 | ; mov_reg simple MOV instruction that moves a register to another | |
107 | ; register. This includes MOVW, but not MOVT. | |
108 | ; mov_shift simple MOV instruction, shifted operand by a constant. | |
109 | ; mov_shift_reg simple MOV instruction, shifted operand by a register. | |
4b5d7374 | 110 | ; mrs system/special/co-processor register move. |
e15a9970 | 111 | ; mul integer multiply. |
112 | ; muls integer multiply, flag setting. | |
1b7da4ac | 113 | ; multiple more than one instruction, candidate for future |
114 | ; splitting, or better modeling. | |
e15a9970 | 115 | ; mvn_imm inverting move instruction, immediate. |
116 | ; mvn_reg inverting move instruction, register. | |
117 | ; mvn_shift inverting move instruction, shifted operand by a constant. | |
118 | ; mvn_shift_reg inverting move instruction, shifted operand by a register. | |
1b7da4ac | 119 | ; no_insn an insn which does not represent an instruction in the |
120 | ; final output, thus having no impact on scheduling. | |
d82e788e | 121 | ; rbit reverse bits. |
122 | ; rev reverse bytes. | |
498b8714 | 123 | ; rotate_imm rotate by immediate. |
e15a9970 | 124 | ; sdiv signed division. |
d82e788e | 125 | ; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an |
e15a9970 | 126 | ; immediate. |
127 | ; shift_reg simple shift by a register. | |
128 | ; smlad signed multiply accumulate dual. | |
129 | ; smladx signed multiply accumulate dual reverse. | |
130 | ; smlal signed multiply accumulate long. | |
131 | ; smlald signed multiply accumulate long dual. | |
132 | ; smlals signed multiply accumulate long, flag setting. | |
133 | ; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate. | |
134 | ; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate. | |
135 | ; smlawy signed multiply accumulate wide, 32x16-bit, | |
136 | ; 32-bit accumulate. | |
137 | ; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate. | |
138 | ; smlsd signed multiply subtract dual. | |
139 | ; smlsdx signed multiply subtract dual reverse. | |
140 | ; smlsld signed multiply subtract long dual. | |
141 | ; smmla signed most significant word multiply accumulate. | |
142 | ; smmul signed most significant word multiply. | |
143 | ; smmulr signed most significant word multiply, rounded. | |
144 | ; smuad signed dual multiply add. | |
145 | ; smuadx signed dual multiply add reverse. | |
146 | ; smull signed multiply long. | |
147 | ; smulls signed multiply long, flag setting. | |
148 | ; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate. | |
149 | ; smulxy signed multiply, 16x16-bit, 32-bit accumulate. | |
150 | ; smusd signed dual multiply subtract. | |
151 | ; smusdx signed dual multiply subtract reverse. | |
062447bb | 152 | ; store_rel store-release. |
e15a9970 | 153 | ; store1 store 1 word to memory from arm registers. |
154 | ; store2 store 2 words to memory from arm registers. | |
155 | ; store3 store 3 words to memory from arm registers. | |
156 | ; store4 store 4 (or more) words to memory from arm registers. | |
ad9d4399 | 157 | ; trap cause a trap in the kernel. |
e15a9970 | 158 | ; udiv unsigned division. |
159 | ; umaal unsigned multiply accumulate accumulate long. | |
160 | ; umlal unsigned multiply accumulate long. | |
161 | ; umlals unsigned multiply accumulate long, flag setting. | |
162 | ; umull unsigned multiply long. | |
163 | ; umulls unsigned multiply long, flag setting. | |
1b7da4ac | 164 | ; untyped insn without type information - default, and error, |
165 | ; case. | |
e15a9970 | 166 | ; |
167 | ; The classification below is for instructions used by the Wireless MMX | |
168 | ; Technology. Each attribute value is used to classify an instruction of the | |
169 | ; same name or family. | |
170 | ; | |
171 | ; wmmx_tandc | |
172 | ; wmmx_tbcst | |
173 | ; wmmx_textrc | |
174 | ; wmmx_textrm | |
175 | ; wmmx_tinsr | |
176 | ; wmmx_tmcr | |
177 | ; wmmx_tmcrr | |
178 | ; wmmx_tmia | |
179 | ; wmmx_tmiaph | |
180 | ; wmmx_tmiaxy | |
181 | ; wmmx_tmrc | |
182 | ; wmmx_tmrrc | |
183 | ; wmmx_tmovmsk | |
184 | ; wmmx_torc | |
185 | ; wmmx_torvsc | |
186 | ; wmmx_wabs | |
187 | ; wmmx_wdiff | |
188 | ; wmmx_wacc | |
189 | ; wmmx_wadd | |
190 | ; wmmx_waddbhus | |
191 | ; wmmx_waddsubhx | |
192 | ; wmmx_waligni | |
193 | ; wmmx_walignr | |
194 | ; wmmx_wand | |
195 | ; wmmx_wandn | |
196 | ; wmmx_wavg2 | |
197 | ; wmmx_wavg4 | |
198 | ; wmmx_wcmpeq | |
199 | ; wmmx_wcmpgt | |
200 | ; wmmx_wmac | |
201 | ; wmmx_wmadd | |
202 | ; wmmx_wmax | |
203 | ; wmmx_wmerge | |
204 | ; wmmx_wmiawxy | |
205 | ; wmmx_wmiaxy | |
206 | ; wmmx_wmin | |
207 | ; wmmx_wmov | |
208 | ; wmmx_wmul | |
209 | ; wmmx_wmulw | |
210 | ; wmmx_wldr | |
211 | ; wmmx_wor | |
212 | ; wmmx_wpack | |
213 | ; wmmx_wqmiaxy | |
214 | ; wmmx_wqmulm | |
215 | ; wmmx_wqmulwm | |
216 | ; wmmx_wror | |
217 | ; wmmx_wsad | |
218 | ; wmmx_wshufh | |
219 | ; wmmx_wsll | |
220 | ; wmmx_wsra | |
221 | ; wmmx_wsrl | |
222 | ; wmmx_wstr | |
223 | ; wmmx_wsub | |
224 | ; wmmx_wsubaddhx | |
225 | ; wmmx_wunpckeh | |
226 | ; wmmx_wunpckel | |
227 | ; wmmx_wunpckih | |
228 | ; wmmx_wunpckil | |
229 | ; wmmx_wxor | |
52432540 | 230 | ; |
231 | ; The classification below is for NEON instructions. | |
232 | ; | |
90ad8a62 | 233 | ; neon_add |
234 | ; neon_add_q | |
235 | ; neon_add_widen | |
236 | ; neon_add_long | |
237 | ; neon_qadd | |
238 | ; neon_qadd_q | |
239 | ; neon_add_halve | |
240 | ; neon_add_halve_q | |
241 | ; neon_add_halve_narrow_q | |
242 | ; neon_sub | |
243 | ; neon_sub_q | |
244 | ; neon_sub_widen | |
245 | ; neon_sub_long | |
246 | ; neon_qsub | |
247 | ; neon_qsub_q | |
248 | ; neon_sub_halve | |
249 | ; neon_sub_halve_q | |
250 | ; neon_sub_halve_narrow_q | |
251 | ; neon_abs | |
252 | ; neon_abs_q | |
253 | ; neon_neg | |
254 | ; neon_neg_q | |
255 | ; neon_qneg | |
256 | ; neon_qneg_q | |
257 | ; neon_qabs | |
258 | ; neon_qabs_q | |
259 | ; neon_abd | |
260 | ; neon_abd_q | |
261 | ; neon_abd_long | |
262 | ; neon_minmax | |
263 | ; neon_minmax_q | |
264 | ; neon_compare | |
265 | ; neon_compare_q | |
266 | ; neon_compare_zero | |
267 | ; neon_compare_zero_q | |
268 | ; neon_arith_acc | |
269 | ; neon_arith_acc_q | |
270 | ; neon_reduc_add | |
271 | ; neon_reduc_add_q | |
272 | ; neon_reduc_add_long | |
273 | ; neon_reduc_add_acc | |
274 | ; neon_reduc_add_acc_q | |
275 | ; neon_reduc_minmax | |
276 | ; neon_reduc_minmax_q | |
277 | ; neon_logic | |
278 | ; neon_logic_q | |
279 | ; neon_tst | |
280 | ; neon_tst_q | |
281 | ; neon_shift_imm | |
282 | ; neon_shift_imm_q | |
283 | ; neon_shift_imm_narrow_q | |
284 | ; neon_shift_imm_long | |
285 | ; neon_shift_reg | |
286 | ; neon_shift_reg_q | |
287 | ; neon_shift_acc | |
288 | ; neon_shift_acc_q | |
289 | ; neon_sat_shift_imm | |
290 | ; neon_sat_shift_imm_q | |
291 | ; neon_sat_shift_imm_narrow_q | |
292 | ; neon_sat_shift_reg | |
293 | ; neon_sat_shift_reg_q | |
294 | ; neon_ins | |
295 | ; neon_ins_q | |
296 | ; neon_move | |
297 | ; neon_move_q | |
298 | ; neon_move_narrow_q | |
299 | ; neon_permute | |
300 | ; neon_permute_q | |
301 | ; neon_zip | |
302 | ; neon_zip_q | |
303 | ; neon_tbl1 | |
304 | ; neon_tbl1_q | |
305 | ; neon_tbl2 | |
306 | ; neon_tbl2_q | |
307 | ; neon_tbl3 | |
308 | ; neon_tbl3_q | |
309 | ; neon_tbl4 | |
310 | ; neon_tbl4_q | |
311 | ; neon_bsl | |
312 | ; neon_bsl_q | |
313 | ; neon_cls | |
314 | ; neon_cls_q | |
315 | ; neon_cnt | |
316 | ; neon_cnt_q | |
317 | ; neon_ext | |
318 | ; neon_ext_q | |
319 | ; neon_rbit | |
320 | ; neon_rbit_q | |
321 | ; neon_rev | |
322 | ; neon_rev_q | |
323 | ; neon_mul_b | |
324 | ; neon_mul_b_q | |
325 | ; neon_mul_h | |
326 | ; neon_mul_h_q | |
327 | ; neon_mul_s | |
328 | ; neon_mul_s_q | |
329 | ; neon_mul_b_long | |
330 | ; neon_mul_h_long | |
331 | ; neon_mul_s_long | |
6d077882 | 332 | ; neon_mul_d_long |
90ad8a62 | 333 | ; neon_mul_h_scalar |
334 | ; neon_mul_h_scalar_q | |
335 | ; neon_mul_s_scalar | |
336 | ; neon_mul_s_scalar_q | |
337 | ; neon_mul_h_scalar_long | |
338 | ; neon_mul_s_scalar_long | |
339 | ; neon_sat_mul_b | |
340 | ; neon_sat_mul_b_q | |
341 | ; neon_sat_mul_h | |
342 | ; neon_sat_mul_h_q | |
343 | ; neon_sat_mul_s | |
344 | ; neon_sat_mul_s_q | |
345 | ; neon_sat_mul_b_long | |
346 | ; neon_sat_mul_h_long | |
347 | ; neon_sat_mul_s_long | |
348 | ; neon_sat_mul_h_scalar | |
349 | ; neon_sat_mul_h_scalar_q | |
350 | ; neon_sat_mul_s_scalar | |
351 | ; neon_sat_mul_s_scalar_q | |
352 | ; neon_sat_mul_h_scalar_long | |
353 | ; neon_sat_mul_s_scalar_long | |
354 | ; neon_mla_b | |
355 | ; neon_mla_b_q | |
356 | ; neon_mla_h | |
357 | ; neon_mla_h_q | |
358 | ; neon_mla_s | |
359 | ; neon_mla_s_q | |
360 | ; neon_mla_b_long | |
361 | ; neon_mla_h_long | |
362 | ; neon_mla_s_long | |
363 | ; neon_mla_h_scalar | |
364 | ; neon_mla_h_scalar_q | |
365 | ; neon_mla_s_scalar | |
366 | ; neon_mla_s_scalar_q | |
367 | ; neon_mla_h_scalar_long | |
368 | ; neon_mla_s_scalar_long | |
369 | ; neon_sat_mla_b_long | |
370 | ; neon_sat_mla_h_long | |
371 | ; neon_sat_mla_s_long | |
372 | ; neon_sat_mla_h_scalar_long | |
373 | ; neon_sat_mla_s_scalar_long | |
374 | ; neon_to_gp | |
375 | ; neon_to_gp_q | |
376 | ; neon_from_gp | |
377 | ; neon_from_gp_q | |
378 | ; neon_ldr | |
648c8771 | 379 | ; neon_ldp |
380 | ; neon_ldp_q | |
90ad8a62 | 381 | ; neon_load1_1reg |
382 | ; neon_load1_1reg_q | |
383 | ; neon_load1_2reg | |
384 | ; neon_load1_2reg_q | |
385 | ; neon_load1_3reg | |
386 | ; neon_load1_3reg_q | |
387 | ; neon_load1_4reg | |
388 | ; neon_load1_4reg_q | |
389 | ; neon_load1_all_lanes | |
390 | ; neon_load1_all_lanes_q | |
391 | ; neon_load1_one_lane | |
392 | ; neon_load1_one_lane_q | |
393 | ; neon_load2_2reg | |
394 | ; neon_load2_2reg_q | |
395 | ; neon_load2_4reg | |
396 | ; neon_load2_4reg_q | |
397 | ; neon_load2_all_lanes | |
398 | ; neon_load2_all_lanes_q | |
399 | ; neon_load2_one_lane | |
400 | ; neon_load2_one_lane_q | |
401 | ; neon_load3_3reg | |
402 | ; neon_load3_3reg_q | |
403 | ; neon_load3_all_lanes | |
404 | ; neon_load3_all_lanes_q | |
405 | ; neon_load3_one_lane | |
406 | ; neon_load3_one_lane_q | |
407 | ; neon_load4_4reg | |
408 | ; neon_load4_4reg_q | |
409 | ; neon_load4_all_lanes | |
410 | ; neon_load4_all_lanes_q | |
411 | ; neon_load4_one_lane | |
412 | ; neon_load4_one_lane_q | |
413 | ; neon_str | |
648c8771 | 414 | ; neon_stp |
415 | ; neon_stp_q | |
90ad8a62 | 416 | ; neon_store1_1reg |
417 | ; neon_store1_1reg_q | |
418 | ; neon_store1_2reg | |
419 | ; neon_store1_2reg_q | |
420 | ; neon_store1_3reg | |
421 | ; neon_store1_3reg_q | |
422 | ; neon_store1_4reg | |
423 | ; neon_store1_4reg_q | |
424 | ; neon_store1_one_lane | |
425 | ; neon_store1_one_lane_q | |
426 | ; neon_store2_2reg | |
427 | ; neon_store2_2reg_q | |
428 | ; neon_store2_4reg | |
429 | ; neon_store2_4reg_q | |
430 | ; neon_store2_one_lane | |
431 | ; neon_store2_one_lane_q | |
432 | ; neon_store3_3reg | |
433 | ; neon_store3_3reg_q | |
434 | ; neon_store3_one_lane | |
435 | ; neon_store3_one_lane_q | |
436 | ; neon_store4_4reg | |
437 | ; neon_store4_4reg_q | |
438 | ; neon_store4_one_lane | |
439 | ; neon_store4_one_lane_q | |
440 | ; neon_fp_abs_s | |
441 | ; neon_fp_abs_s_q | |
442 | ; neon_fp_abs_d | |
443 | ; neon_fp_abs_d_q | |
444 | ; neon_fp_neg_s | |
445 | ; neon_fp_neg_s_q | |
446 | ; neon_fp_neg_d | |
447 | ; neon_fp_neg_d_q | |
448 | ; neon_fp_abd_s | |
449 | ; neon_fp_abd_s_q | |
450 | ; neon_fp_abd_d | |
451 | ; neon_fp_abd_d_q | |
452 | ; neon_fp_addsub_s | |
453 | ; neon_fp_addsub_s_q | |
454 | ; neon_fp_addsub_d | |
455 | ; neon_fp_addsub_d_q | |
456 | ; neon_fp_compare_s | |
457 | ; neon_fp_compare_s_q | |
458 | ; neon_fp_compare_d | |
459 | ; neon_fp_compare_d_q | |
460 | ; neon_fp_minmax_s | |
461 | ; neon_fp_minmax_s_q | |
462 | ; neon_fp_minmax_d | |
463 | ; neon_fp_minmax_d_q | |
464 | ; neon_fp_reduc_add_s | |
465 | ; neon_fp_reduc_add_s_q | |
466 | ; neon_fp_reduc_add_d | |
467 | ; neon_fp_reduc_add_d_q | |
468 | ; neon_fp_reduc_minmax_s | |
469 | ; neon_fp_reduc_minmax_s_q | |
470 | ; neon_fp_reduc_minmax_d | |
471 | ; neon_fp_reduc_minmax_d_q | |
472 | ; neon_fp_cvt_narrow_s_q | |
473 | ; neon_fp_cvt_narrow_d_q | |
474 | ; neon_fp_cvt_widen_h | |
475 | ; neon_fp_cvt_widen_s | |
476 | ; neon_fp_to_int_s | |
477 | ; neon_fp_to_int_s_q | |
478 | ; neon_fp_to_int_d | |
479 | ; neon_fp_to_int_d_q | |
480 | ; neon_int_to_fp_s | |
481 | ; neon_int_to_fp_s_q | |
482 | ; neon_int_to_fp_d | |
483 | ; neon_int_to_fp_d_q | |
484 | ; neon_fp_round_s | |
485 | ; neon_fp_round_s_q | |
486 | ; neon_fp_round_d | |
487 | ; neon_fp_round_d_q | |
488 | ; neon_fp_recpe_s | |
489 | ; neon_fp_recpe_s_q | |
490 | ; neon_fp_recpe_d | |
491 | ; neon_fp_recpe_d_q | |
492 | ; neon_fp_recps_s | |
493 | ; neon_fp_recps_s_q | |
494 | ; neon_fp_recps_d | |
495 | ; neon_fp_recps_d_q | |
496 | ; neon_fp_recpx_s | |
497 | ; neon_fp_recpx_s_q | |
498 | ; neon_fp_recpx_d | |
499 | ; neon_fp_recpx_d_q | |
500 | ; neon_fp_rsqrte_s | |
501 | ; neon_fp_rsqrte_s_q | |
502 | ; neon_fp_rsqrte_d | |
503 | ; neon_fp_rsqrte_d_q | |
504 | ; neon_fp_rsqrts_s | |
505 | ; neon_fp_rsqrts_s_q | |
506 | ; neon_fp_rsqrts_d | |
507 | ; neon_fp_rsqrts_d_q | |
508 | ; neon_fp_mul_s | |
509 | ; neon_fp_mul_s_q | |
510 | ; neon_fp_mul_s_scalar | |
511 | ; neon_fp_mul_s_scalar_q | |
512 | ; neon_fp_mul_d | |
513 | ; neon_fp_mul_d_q | |
514 | ; neon_fp_mul_d_scalar_q | |
515 | ; neon_fp_mla_s | |
516 | ; neon_fp_mla_s_q | |
517 | ; neon_fp_mla_s_scalar | |
518 | ; neon_fp_mla_s_scalar_q | |
519 | ; neon_fp_mla_d | |
520 | ; neon_fp_mla_d_q | |
521 | ; neon_fp_mla_d_scalar_q | |
522 | ; neon_fp_sqrt_s | |
523 | ; neon_fp_sqrt_s_q | |
524 | ; neon_fp_sqrt_d | |
525 | ; neon_fp_sqrt_d_q | |
526 | ; neon_fp_div_s | |
527 | ; neon_fp_div_s_q | |
528 | ; neon_fp_div_d | |
529 | ; neon_fp_div_d_q | |
6d077882 | 530 | ; |
531 | ; The classification below is for Crypto instructions. | |
532 | ; | |
31c72114 | 533 | ; crypto_aese |
534 | ; crypto_aesmc | |
6d077882 | 535 | ; crypto_sha1_xor |
536 | ; crypto_sha1_fast | |
537 | ; crypto_sha1_slow | |
538 | ; crypto_sha256_fast | |
539 | ; crypto_sha256_slow | |
e15a9970 | 540 | |
541 | (define_attr "type" | |
d82e788e | 542 | "adc_imm,\ |
543 | adc_reg,\ | |
544 | adcs_imm,\ | |
545 | adcs_reg,\ | |
546 | adr,\ | |
547 | alu_ext,\ | |
548 | alu_imm,\ | |
112eda6f | 549 | alu_sreg,\ |
d82e788e | 550 | alu_shift_imm,\ |
551 | alu_shift_reg,\ | |
112eda6f | 552 | alu_dsp_reg,\ |
d82e788e | 553 | alus_ext,\ |
554 | alus_imm,\ | |
112eda6f | 555 | alus_sreg,\ |
d82e788e | 556 | alus_shift_imm,\ |
557 | alus_shift_reg,\ | |
558 | bfm,\ | |
e15a9970 | 559 | block,\ |
560 | branch,\ | |
561 | call,\ | |
562 | clz,\ | |
1b7da4ac | 563 | no_insn,\ |
d82e788e | 564 | csel,\ |
2a0c73f2 | 565 | crc,\ |
e15a9970 | 566 | extend,\ |
e15a9970 | 567 | f_cvt,\ |
d453f27a | 568 | f_cvtf2i,\ |
569 | f_cvti2f,\ | |
e15a9970 | 570 | f_flag,\ |
571 | f_loadd,\ | |
572 | f_loads,\ | |
52432540 | 573 | f_mcr,\ |
574 | f_mcrr,\ | |
e15a9970 | 575 | f_minmaxd,\ |
576 | f_minmaxs,\ | |
52432540 | 577 | f_mrc,\ |
578 | f_mrrc,\ | |
e15a9970 | 579 | f_rintd,\ |
580 | f_rints,\ | |
e15a9970 | 581 | f_stored,\ |
582 | f_stores,\ | |
583 | faddd,\ | |
584 | fadds,\ | |
585 | fcmpd,\ | |
586 | fcmps,\ | |
587 | fconstd,\ | |
588 | fconsts,\ | |
d82e788e | 589 | fcsel,\ |
e15a9970 | 590 | fdivd,\ |
591 | fdivs,\ | |
592 | ffarithd,\ | |
593 | ffariths,\ | |
594 | ffmad,\ | |
595 | ffmas,\ | |
596 | float,\ | |
597 | fmacd,\ | |
598 | fmacs,\ | |
57a7b13e | 599 | fmov,\ |
e15a9970 | 600 | fmuld,\ |
601 | fmuls,\ | |
e62582b3 | 602 | fsqrts,\ |
603 | fsqrtd,\ | |
062447bb | 604 | load_acq,\ |
e15a9970 | 605 | load_byte,\ |
606 | load1,\ | |
607 | load2,\ | |
608 | load3,\ | |
609 | load4,\ | |
d82e788e | 610 | logic_imm,\ |
611 | logic_reg,\ | |
612 | logic_shift_imm,\ | |
613 | logic_shift_reg,\ | |
614 | logics_imm,\ | |
615 | logics_reg,\ | |
616 | logics_shift_imm,\ | |
617 | logics_shift_reg,\ | |
e15a9970 | 618 | mla,\ |
619 | mlas,\ | |
620 | mov_imm,\ | |
621 | mov_reg,\ | |
622 | mov_shift,\ | |
623 | mov_shift_reg,\ | |
4b5d7374 | 624 | mrs,\ |
e15a9970 | 625 | mul,\ |
626 | muls,\ | |
1b7da4ac | 627 | multiple,\ |
e15a9970 | 628 | mvn_imm,\ |
629 | mvn_reg,\ | |
630 | mvn_shift,\ | |
631 | mvn_shift_reg,\ | |
1b7da4ac | 632 | nop,\ |
d82e788e | 633 | rbit,\ |
634 | rev,\ | |
498b8714 | 635 | rotate_imm,\ |
e15a9970 | 636 | sdiv,\ |
d82e788e | 637 | shift_imm,\ |
e15a9970 | 638 | shift_reg,\ |
639 | smlad,\ | |
640 | smladx,\ | |
641 | smlal,\ | |
642 | smlald,\ | |
643 | smlals,\ | |
644 | smlalxy,\ | |
645 | smlawx,\ | |
646 | smlawy,\ | |
647 | smlaxy,\ | |
648 | smlsd,\ | |
649 | smlsdx,\ | |
650 | smlsld,\ | |
651 | smmla,\ | |
652 | smmul,\ | |
653 | smmulr,\ | |
654 | smuad,\ | |
655 | smuadx,\ | |
656 | smull,\ | |
657 | smulls,\ | |
658 | smulwy,\ | |
659 | smulxy,\ | |
660 | smusd,\ | |
661 | smusdx,\ | |
062447bb | 662 | store_rel,\ |
e15a9970 | 663 | store1,\ |
664 | store2,\ | |
665 | store3,\ | |
666 | store4,\ | |
ad9d4399 | 667 | trap,\ |
e15a9970 | 668 | udiv,\ |
669 | umaal,\ | |
670 | umlal,\ | |
671 | umlals,\ | |
672 | umull,\ | |
673 | umulls,\ | |
1b7da4ac | 674 | untyped,\ |
e15a9970 | 675 | wmmx_tandc,\ |
676 | wmmx_tbcst,\ | |
677 | wmmx_textrc,\ | |
678 | wmmx_textrm,\ | |
679 | wmmx_tinsr,\ | |
680 | wmmx_tmcr,\ | |
681 | wmmx_tmcrr,\ | |
682 | wmmx_tmia,\ | |
683 | wmmx_tmiaph,\ | |
684 | wmmx_tmiaxy,\ | |
685 | wmmx_tmrc,\ | |
686 | wmmx_tmrrc,\ | |
687 | wmmx_tmovmsk,\ | |
688 | wmmx_torc,\ | |
689 | wmmx_torvsc,\ | |
690 | wmmx_wabs,\ | |
691 | wmmx_wabsdiff,\ | |
692 | wmmx_wacc,\ | |
693 | wmmx_wadd,\ | |
694 | wmmx_waddbhus,\ | |
695 | wmmx_waddsubhx,\ | |
696 | wmmx_waligni,\ | |
697 | wmmx_walignr,\ | |
698 | wmmx_wand,\ | |
699 | wmmx_wandn,\ | |
700 | wmmx_wavg2,\ | |
701 | wmmx_wavg4,\ | |
702 | wmmx_wcmpeq,\ | |
703 | wmmx_wcmpgt,\ | |
704 | wmmx_wmac,\ | |
705 | wmmx_wmadd,\ | |
706 | wmmx_wmax,\ | |
707 | wmmx_wmerge,\ | |
708 | wmmx_wmiawxy,\ | |
709 | wmmx_wmiaxy,\ | |
710 | wmmx_wmin,\ | |
711 | wmmx_wmov,\ | |
712 | wmmx_wmul,\ | |
713 | wmmx_wmulw,\ | |
714 | wmmx_wldr,\ | |
715 | wmmx_wor,\ | |
716 | wmmx_wpack,\ | |
717 | wmmx_wqmiaxy,\ | |
718 | wmmx_wqmulm,\ | |
719 | wmmx_wqmulwm,\ | |
720 | wmmx_wror,\ | |
721 | wmmx_wsad,\ | |
722 | wmmx_wshufh,\ | |
723 | wmmx_wsll,\ | |
724 | wmmx_wsra,\ | |
725 | wmmx_wsrl,\ | |
726 | wmmx_wstr,\ | |
727 | wmmx_wsub,\ | |
728 | wmmx_wsubaddhx,\ | |
729 | wmmx_wunpckeh,\ | |
730 | wmmx_wunpckel,\ | |
731 | wmmx_wunpckih,\ | |
732 | wmmx_wunpckil,\ | |
52432540 | 733 | wmmx_wxor,\ |
90ad8a62 | 734 | \ |
735 | neon_add,\ | |
736 | neon_add_q,\ | |
737 | neon_add_widen,\ | |
738 | neon_add_long,\ | |
739 | neon_qadd,\ | |
740 | neon_qadd_q,\ | |
741 | neon_add_halve,\ | |
742 | neon_add_halve_q,\ | |
743 | neon_add_halve_narrow_q,\ | |
744 | \ | |
745 | neon_sub,\ | |
746 | neon_sub_q,\ | |
747 | neon_sub_widen,\ | |
748 | neon_sub_long,\ | |
749 | neon_qsub,\ | |
750 | neon_qsub_q,\ | |
751 | neon_sub_halve,\ | |
752 | neon_sub_halve_q,\ | |
753 | neon_sub_halve_narrow_q,\ | |
754 | \ | |
755 | neon_abs,\ | |
756 | neon_abs_q,\ | |
757 | neon_neg,\ | |
758 | neon_neg_q,\ | |
759 | neon_qneg,\ | |
760 | neon_qneg_q,\ | |
761 | neon_qabs,\ | |
762 | neon_qabs_q,\ | |
763 | neon_abd,\ | |
764 | neon_abd_q,\ | |
765 | neon_abd_long,\ | |
766 | \ | |
767 | neon_minmax,\ | |
768 | neon_minmax_q,\ | |
769 | neon_compare,\ | |
770 | neon_compare_q,\ | |
771 | neon_compare_zero,\ | |
772 | neon_compare_zero_q,\ | |
773 | \ | |
774 | neon_arith_acc,\ | |
775 | neon_arith_acc_q,\ | |
776 | neon_reduc_add,\ | |
777 | neon_reduc_add_q,\ | |
778 | neon_reduc_add_long,\ | |
779 | neon_reduc_add_acc,\ | |
780 | neon_reduc_add_acc_q,\ | |
781 | neon_reduc_minmax,\ | |
782 | neon_reduc_minmax_q,\ | |
783 | neon_logic,\ | |
784 | neon_logic_q,\ | |
785 | neon_tst,\ | |
786 | neon_tst_q,\ | |
787 | \ | |
788 | neon_shift_imm,\ | |
789 | neon_shift_imm_q,\ | |
790 | neon_shift_imm_narrow_q,\ | |
791 | neon_shift_imm_long,\ | |
792 | neon_shift_reg,\ | |
793 | neon_shift_reg_q,\ | |
794 | neon_shift_acc,\ | |
795 | neon_shift_acc_q,\ | |
796 | neon_sat_shift_imm,\ | |
797 | neon_sat_shift_imm_q,\ | |
798 | neon_sat_shift_imm_narrow_q,\ | |
799 | neon_sat_shift_reg,\ | |
800 | neon_sat_shift_reg_q,\ | |
801 | \ | |
802 | neon_ins,\ | |
803 | neon_ins_q,\ | |
804 | neon_move,\ | |
805 | neon_move_q,\ | |
806 | neon_move_narrow_q,\ | |
807 | neon_permute,\ | |
808 | neon_permute_q,\ | |
809 | neon_zip,\ | |
810 | neon_zip_q,\ | |
811 | neon_tbl1,\ | |
812 | neon_tbl1_q,\ | |
813 | neon_tbl2,\ | |
814 | neon_tbl2_q,\ | |
815 | neon_tbl3,\ | |
816 | neon_tbl3_q,\ | |
817 | neon_tbl4,\ | |
818 | neon_tbl4_q,\ | |
819 | \ | |
820 | neon_bsl,\ | |
821 | neon_bsl_q,\ | |
822 | neon_cls,\ | |
823 | neon_cls_q,\ | |
824 | neon_cnt,\ | |
825 | neon_cnt_q,\ | |
826 | neon_dup,\ | |
827 | neon_dup_q,\ | |
828 | neon_ext,\ | |
829 | neon_ext_q,\ | |
830 | neon_rbit,\ | |
831 | neon_rbit_q,\ | |
832 | neon_rev,\ | |
833 | neon_rev_q,\ | |
834 | \ | |
835 | neon_mul_b,\ | |
836 | neon_mul_b_q,\ | |
837 | neon_mul_h,\ | |
838 | neon_mul_h_q,\ | |
839 | neon_mul_s,\ | |
840 | neon_mul_s_q,\ | |
841 | neon_mul_b_long,\ | |
842 | neon_mul_h_long,\ | |
843 | neon_mul_s_long,\ | |
6d077882 | 844 | neon_mul_d_long,\ |
90ad8a62 | 845 | neon_mul_h_scalar,\ |
846 | neon_mul_h_scalar_q,\ | |
847 | neon_mul_s_scalar,\ | |
848 | neon_mul_s_scalar_q,\ | |
849 | neon_mul_h_scalar_long,\ | |
850 | neon_mul_s_scalar_long,\ | |
851 | \ | |
852 | neon_sat_mul_b,\ | |
853 | neon_sat_mul_b_q,\ | |
854 | neon_sat_mul_h,\ | |
855 | neon_sat_mul_h_q,\ | |
856 | neon_sat_mul_s,\ | |
857 | neon_sat_mul_s_q,\ | |
858 | neon_sat_mul_b_long,\ | |
859 | neon_sat_mul_h_long,\ | |
860 | neon_sat_mul_s_long,\ | |
861 | neon_sat_mul_h_scalar,\ | |
862 | neon_sat_mul_h_scalar_q,\ | |
863 | neon_sat_mul_s_scalar,\ | |
864 | neon_sat_mul_s_scalar_q,\ | |
865 | neon_sat_mul_h_scalar_long,\ | |
866 | neon_sat_mul_s_scalar_long,\ | |
867 | \ | |
868 | neon_mla_b,\ | |
869 | neon_mla_b_q,\ | |
870 | neon_mla_h,\ | |
871 | neon_mla_h_q,\ | |
872 | neon_mla_s,\ | |
873 | neon_mla_s_q,\ | |
874 | neon_mla_b_long,\ | |
875 | neon_mla_h_long,\ | |
876 | neon_mla_s_long,\ | |
877 | neon_mla_h_scalar,\ | |
878 | neon_mla_h_scalar_q,\ | |
879 | neon_mla_s_scalar,\ | |
880 | neon_mla_s_scalar_q,\ | |
881 | neon_mla_h_scalar_long,\ | |
882 | neon_mla_s_scalar_long,\ | |
883 | \ | |
884 | neon_sat_mla_b_long,\ | |
885 | neon_sat_mla_h_long,\ | |
886 | neon_sat_mla_s_long,\ | |
887 | neon_sat_mla_h_scalar_long,\ | |
888 | neon_sat_mla_s_scalar_long,\ | |
889 | \ | |
890 | neon_to_gp,\ | |
891 | neon_to_gp_q,\ | |
892 | neon_from_gp,\ | |
893 | neon_from_gp_q,\ | |
894 | \ | |
895 | neon_ldr,\ | |
648c8771 | 896 | neon_ldp,\ |
897 | neon_ldp_q,\ | |
90ad8a62 | 898 | neon_load1_1reg,\ |
899 | neon_load1_1reg_q,\ | |
900 | neon_load1_2reg,\ | |
901 | neon_load1_2reg_q,\ | |
902 | neon_load1_3reg,\ | |
903 | neon_load1_3reg_q,\ | |
904 | neon_load1_4reg,\ | |
905 | neon_load1_4reg_q,\ | |
906 | neon_load1_all_lanes,\ | |
907 | neon_load1_all_lanes_q,\ | |
908 | neon_load1_one_lane,\ | |
909 | neon_load1_one_lane_q,\ | |
910 | \ | |
911 | neon_load2_2reg,\ | |
912 | neon_load2_2reg_q,\ | |
913 | neon_load2_4reg,\ | |
914 | neon_load2_4reg_q,\ | |
915 | neon_load2_all_lanes,\ | |
916 | neon_load2_all_lanes_q,\ | |
917 | neon_load2_one_lane,\ | |
918 | neon_load2_one_lane_q,\ | |
919 | \ | |
920 | neon_load3_3reg,\ | |
921 | neon_load3_3reg_q,\ | |
922 | neon_load3_all_lanes,\ | |
923 | neon_load3_all_lanes_q,\ | |
924 | neon_load3_one_lane,\ | |
925 | neon_load3_one_lane_q,\ | |
926 | \ | |
927 | neon_load4_4reg,\ | |
928 | neon_load4_4reg_q,\ | |
929 | neon_load4_all_lanes,\ | |
930 | neon_load4_all_lanes_q,\ | |
931 | neon_load4_one_lane,\ | |
932 | neon_load4_one_lane_q,\ | |
933 | \ | |
934 | neon_str,\ | |
648c8771 | 935 | neon_stp,\ |
936 | neon_stp_q,\ | |
90ad8a62 | 937 | neon_store1_1reg,\ |
938 | neon_store1_1reg_q,\ | |
939 | neon_store1_2reg,\ | |
940 | neon_store1_2reg_q,\ | |
941 | neon_store1_3reg,\ | |
942 | neon_store1_3reg_q,\ | |
943 | neon_store1_4reg,\ | |
944 | neon_store1_4reg_q,\ | |
945 | neon_store1_one_lane,\ | |
946 | neon_store1_one_lane_q,\ | |
947 | \ | |
948 | neon_store2_2reg,\ | |
949 | neon_store2_2reg_q,\ | |
950 | neon_store2_4reg,\ | |
951 | neon_store2_4reg_q,\ | |
952 | neon_store2_one_lane,\ | |
953 | neon_store2_one_lane_q,\ | |
954 | \ | |
955 | neon_store3_3reg,\ | |
956 | neon_store3_3reg_q,\ | |
957 | neon_store3_one_lane,\ | |
958 | neon_store3_one_lane_q,\ | |
959 | \ | |
960 | neon_store4_4reg,\ | |
961 | neon_store4_4reg_q,\ | |
962 | neon_store4_one_lane,\ | |
963 | neon_store4_one_lane_q,\ | |
964 | \ | |
965 | neon_fp_abs_s,\ | |
966 | neon_fp_abs_s_q,\ | |
967 | neon_fp_abs_d,\ | |
968 | neon_fp_abs_d_q,\ | |
969 | neon_fp_neg_s,\ | |
970 | neon_fp_neg_s_q,\ | |
971 | neon_fp_neg_d,\ | |
972 | neon_fp_neg_d_q,\ | |
973 | \ | |
974 | neon_fp_abd_s,\ | |
975 | neon_fp_abd_s_q,\ | |
976 | neon_fp_abd_d,\ | |
977 | neon_fp_abd_d_q,\ | |
978 | neon_fp_addsub_s,\ | |
979 | neon_fp_addsub_s_q,\ | |
980 | neon_fp_addsub_d,\ | |
981 | neon_fp_addsub_d_q,\ | |
982 | neon_fp_compare_s,\ | |
983 | neon_fp_compare_s_q,\ | |
984 | neon_fp_compare_d,\ | |
985 | neon_fp_compare_d_q,\ | |
986 | neon_fp_minmax_s,\ | |
987 | neon_fp_minmax_s_q,\ | |
988 | neon_fp_minmax_d,\ | |
989 | neon_fp_minmax_d_q,\ | |
990 | \ | |
991 | neon_fp_reduc_add_s,\ | |
992 | neon_fp_reduc_add_s_q,\ | |
993 | neon_fp_reduc_add_d,\ | |
994 | neon_fp_reduc_add_d_q,\ | |
995 | neon_fp_reduc_minmax_s,\ | |
996 | neon_fp_reduc_minmax_s_q,\ | |
997 | neon_fp_reduc_minmax_d,\ | |
998 | neon_fp_reduc_minmax_d_q,\ | |
999 | \ | |
1000 | neon_fp_cvt_narrow_s_q,\ | |
1001 | neon_fp_cvt_narrow_d_q,\ | |
1002 | neon_fp_cvt_widen_h,\ | |
1003 | neon_fp_cvt_widen_s,\ | |
1004 | \ | |
1005 | neon_fp_to_int_s,\ | |
1006 | neon_fp_to_int_s_q,\ | |
1007 | neon_fp_to_int_d,\ | |
1008 | neon_fp_to_int_d_q,\ | |
1009 | neon_int_to_fp_s,\ | |
1010 | neon_int_to_fp_s_q,\ | |
1011 | neon_int_to_fp_d,\ | |
1012 | neon_int_to_fp_d_q,\ | |
1013 | neon_fp_round_s,\ | |
1014 | neon_fp_round_s_q,\ | |
1015 | neon_fp_round_d,\ | |
1016 | neon_fp_round_d_q,\ | |
1017 | \ | |
1018 | neon_fp_recpe_s,\ | |
1019 | neon_fp_recpe_s_q,\ | |
1020 | neon_fp_recpe_d,\ | |
1021 | neon_fp_recpe_d_q,\ | |
1022 | neon_fp_recps_s,\ | |
1023 | neon_fp_recps_s_q,\ | |
1024 | neon_fp_recps_d,\ | |
1025 | neon_fp_recps_d_q,\ | |
1026 | neon_fp_recpx_s,\ | |
1027 | neon_fp_recpx_s_q,\ | |
1028 | neon_fp_recpx_d,\ | |
1029 | neon_fp_recpx_d_q,\ | |
1030 | \ | |
1031 | neon_fp_rsqrte_s,\ | |
1032 | neon_fp_rsqrte_s_q,\ | |
1033 | neon_fp_rsqrte_d,\ | |
1034 | neon_fp_rsqrte_d_q,\ | |
1035 | neon_fp_rsqrts_s,\ | |
1036 | neon_fp_rsqrts_s_q,\ | |
1037 | neon_fp_rsqrts_d,\ | |
1038 | neon_fp_rsqrts_d_q,\ | |
1039 | \ | |
1040 | neon_fp_mul_s,\ | |
1041 | neon_fp_mul_s_q,\ | |
1042 | neon_fp_mul_s_scalar,\ | |
1043 | neon_fp_mul_s_scalar_q,\ | |
1044 | neon_fp_mul_d,\ | |
1045 | neon_fp_mul_d_q,\ | |
1046 | neon_fp_mul_d_scalar_q,\ | |
1047 | \ | |
1048 | neon_fp_mla_s,\ | |
1049 | neon_fp_mla_s_q,\ | |
1050 | neon_fp_mla_s_scalar,\ | |
1051 | neon_fp_mla_s_scalar_q,\ | |
1052 | neon_fp_mla_d,\ | |
1053 | neon_fp_mla_d_q,\ | |
1054 | neon_fp_mla_d_scalar_q,\ | |
1055 | \ | |
1056 | neon_fp_sqrt_s,\ | |
1057 | neon_fp_sqrt_s_q,\ | |
1058 | neon_fp_sqrt_d,\ | |
1059 | neon_fp_sqrt_d_q,\ | |
1060 | neon_fp_div_s,\ | |
1061 | neon_fp_div_s_q,\ | |
1062 | neon_fp_div_d,\ | |
6d077882 | 1063 | neon_fp_div_d_q,\ |
1064 | \ | |
31c72114 | 1065 | crypto_aese,\ |
1066 | crypto_aesmc,\ | |
6d077882 | 1067 | crypto_sha1_xor,\ |
1068 | crypto_sha1_fast,\ | |
1069 | crypto_sha1_slow,\ | |
1070 | crypto_sha256_fast,\ | |
1071 | crypto_sha256_slow" | |
90ad8a62 | 1072 | (const_string "untyped")) |
e15a9970 | 1073 | |
1074 | ; Is this an (integer side) multiply with a 32-bit (or smaller) result? | |
1075 | (define_attr "mul32" "no,yes" | |
1076 | (if_then_else | |
1077 | (eq_attr "type" | |
1078 | "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\ | |
1079 | smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld") | |
1080 | (const_string "yes") | |
1081 | (const_string "no"))) | |
1082 | ||
1083 | ; Is this an (integer side) multiply with a 64-bit result? | |
1084 | (define_attr "mul64" "no,yes" | |
1085 | (if_then_else | |
1086 | (eq_attr "type" | |
1087 | "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") | |
1088 | (const_string "yes") | |
1089 | (const_string "no"))) | |
31c72114 | 1090 | |
1091 | ; YES if the "type" attribute assigned to the insn denotes an | |
1092 | ; Advanced SIMD instruction, NO otherwise. | |
1093 | (define_attr "is_neon_type" "yes,no" | |
1094 | (if_then_else (eq_attr "type" | |
1095 | "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ | |
1096 | neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ | |
1097 | neon_add_halve_narrow_q,\ | |
1098 | neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ | |
1099 | neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ | |
1100 | neon_sub_halve_narrow_q,\ | |
1101 | neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\ | |
1102 | neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ | |
1103 | neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ | |
1104 | neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ | |
1105 | neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ | |
1106 | neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ | |
1107 | neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ | |
1108 | neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ | |
1109 | neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ | |
1110 | neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ | |
1111 | neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ | |
1112 | neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ | |
1113 | neon_sat_shift_reg, neon_sat_shift_reg_q,\ | |
1114 | neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ | |
1115 | neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ | |
1116 | neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ | |
1117 | neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ | |
1118 | neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ | |
1119 | neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ | |
1120 | neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ | |
1121 | neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ | |
1122 | neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ | |
1123 | neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ | |
1124 | neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ | |
1125 | neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ | |
1126 | neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ | |
1127 | neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ | |
1128 | neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ | |
1129 | neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ | |
1130 | neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ | |
1131 | neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ | |
1132 | neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ | |
1133 | neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ | |
1134 | neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ | |
1135 | neon_sat_mla_b_long, neon_sat_mla_h_long,\ | |
1136 | neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ | |
1137 | neon_sat_mla_s_scalar_long,\ | |
1138 | neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ | |
648c8771 | 1139 | neon_ldr, neon_ldp, neon_ldp_q,\ |
1140 | neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ | |
31c72114 | 1141 | neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ |
1142 | neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ | |
1143 | neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ | |
1144 | neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ | |
1145 | neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ | |
1146 | neon_load2_one_lane, neon_load2_one_lane_q,\ | |
1147 | neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ | |
1148 | neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ | |
1149 | neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ | |
1150 | neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ | |
648c8771 | 1151 | neon_str, neon_stp, neon_stp_q,\ |
1152 | neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ | |
31c72114 | 1153 | neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ |
1154 | neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ | |
1155 | neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ | |
1156 | neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ | |
1157 | neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ | |
1158 | neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ | |
1159 | neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ | |
1160 | neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ | |
7f203d5f | 1161 | neon_fp_abs_s, neon_fp_abs_s_q, neon_fp_abs_d, neon_fp_abs_d_q,\ |
31c72114 | 1162 | neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ |
1163 | neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ | |
1164 | neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ | |
1165 | neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ | |
7f203d5f | 1166 | neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ |
31c72114 | 1167 | neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ |
1168 | neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, | |
1169 | neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ | |
1170 | neon_fp_reduc_minmax_d_q,\ | |
1171 | neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ | |
1172 | neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ | |
1173 | neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ | |
7f203d5f | 1174 | neon_fp_to_int_d, neon_fp_to_int_d_q,\ |
1175 | neon_int_to_fp_d, neon_int_to_fp_d_q,\ | |
31c72114 | 1176 | neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ |
1177 | neon_fp_recpe_s_q,\ | |
1178 | neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ | |
1179 | neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ | |
1180 | neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ | |
1181 | neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ | |
1182 | neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ | |
1183 | neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ | |
1184 | neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ | |
1185 | neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ | |
1186 | neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ | |
1187 | neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ | |
1188 | neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ | |
1189 | neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ | |
1190 | neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\ | |
1191 | crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\ | |
1192 | crypto_sha256_fast, crypto_sha256_slow") | |
1193 | (const_string "yes") | |
1194 | (const_string "no"))) |